drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Texas Instruments DP83867 PHY
   4  *
   5  * Copyright (C) 2015 Texas Instruments Inc.
   6  */
   7
   8 #include <linux/ethtool.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mii.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/phy.h>
  14 #include <linux/delay.h>
  15
  16 #include <dt-bindings/net/ti-dp83867.h>
  17
  18 #define DP83867_PHY_ID          0x2000a231
  19 #define DP83867_DEVADDR         0x1f
  20
  21 #define MII_DP83867_PHYCTRL     0x10
  22 #define MII_DP83867_MICR        0x12
  23 #define MII_DP83867_ISR         0x13
  24 #define DP83867_CTRL            0x1f
  25 #define DP83867_CFG3            0x1e
  26
  27 /* Extended Registers */
  28 #define DP83867_CFG4            0x0031
  29 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
  30 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
  31 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
  32 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
  33 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
  34
  35 #define DP83867_RGMIICTL        0x0032
  36 #define DP83867_STRAP_STS1      0x006E
  37 #define DP83867_RGMIIDCTL       0x0086
  38 #define DP83867_IO_MUX_CFG      0x0170
  39 #define DP83867_10M_SGMII_CFG   0x016F
  40 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  41
  42 #define DP83867_SW_RESET        BIT(15)
  43 #define DP83867_SW_RESTART      BIT(14)
  44
  45 /* MICR Interrupt bits */
  46 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  47 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  48 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  49 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  50 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  51 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  52 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  53 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  54 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  55 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  56 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  57 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  58
  59 /* RGMIICTL bits */
  60 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  61 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  62
  63 /* STRAP_STS1 bits */
  64 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  65
  66 /* PHY CTRL bits */
  67 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  68 #define DP83867_PHYCR_FIFO_DEPTH_MASK           (3 << 14)
  69 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
  70
  71 /* RGMIIDCTL bits */
  72 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  73
  74 /* IO_MUX_CFG bits */
  75 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  76
  77 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  78 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  79 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
  80 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
  81
  82 /* CFG4 bits */
  83 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
  84
  85 enum {
  86         DP83867_PORT_MIRROING_KEEP,
  87         DP83867_PORT_MIRROING_EN,
  88         DP83867_PORT_MIRROING_DIS,
  89 };
  90
  91 struct dp83867_private {
  92         int rx_id_delay;
  93         int tx_id_delay;
  94         int fifo_depth;
  95         int io_impedance;
  96         int port_mirroring;
  97         bool rxctrl_strap_quirk;
  98         int clk_output_sel;
  99 };
 100
 101 static int dp83867_ack_interrupt(struct phy_device *phydev)
 102 {
 103         int err = phy_read(phydev, MII_DP83867_ISR);
 104
 105         if (err < 0)
 106                 return err;
 107
 108         return 0;
 109 }
 110
 111 static int dp83867_config_intr(struct phy_device *phydev)
 112 {
 113         int micr_status;
 114
 115         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 116                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 117                 if (micr_status < 0)
 118                         return micr_status;
 119
 120                 micr_status |=
 121                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 122                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 123                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 124                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 125                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 126                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 127
 128                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 129         }
 130
 131         micr_status = 0x0;
 132         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 133 }
 134
 135 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 136 {
 137         struct dp83867_private *dp83867 =
 138                 (struct dp83867_private *)phydev->priv;
 139
 140         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 141                 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 142                                  DP83867_CFG4_PORT_MIRROR_EN);
 143         else
 144                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 145                                    DP83867_CFG4_PORT_MIRROR_EN);
 146         return 0;
 147 }
 148
 149 #ifdef CONFIG_OF_MDIO
 150 static int dp83867_of_init(struct phy_device *phydev)
 151 {
 152         struct dp83867_private *dp83867 = phydev->priv;
 153         struct device *dev = &phydev->mdio.dev;
 154         struct device_node *of_node = dev->of_node;
 155         int ret;
 156
 157         if (!of_node)
 158                 return -ENODEV;
 159
 160         dp83867->io_impedance = -EINVAL;
 161
 162         /* Optional configuration */
 163         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 164                                    &dp83867->clk_output_sel);
 165         if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
 166                 /* Keep the default value if ti,clk-output-sel is not set
 167                  * or too high
 168                  */
 169                 dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
 170
 171         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 172                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 173         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 174                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 175
 176         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 177                                         "ti,dp83867-rxctrl-strap-quirk");
 178
 179         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 180                                    &dp83867->rx_id_delay);
 181         if (ret &&
 182             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 183              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 184                 return ret;
 185
 186         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 187                                    &dp83867->tx_id_delay);
 188         if (ret &&
 189             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 190              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 191                 return ret;
 192
 193         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 194                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 195
 196         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 197                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 198
 199         return of_property_read_u32(of_node, "ti,fifo-depth",
 200                                    &dp83867->fifo_depth);
 201 }
 202 #else
 203 static int dp83867_of_init(struct phy_device *phydev)
 204 {
 205         return 0;
 206 }
 207 #endif /* CONFIG_OF_MDIO */
 208
 209 static int dp83867_config_init(struct phy_device *phydev)
 210 {
 211         struct dp83867_private *dp83867;
 212         int ret, val, bs;
 213         u16 delay;
 214
 215         if (!phydev->priv) {
 216                 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 217                                        GFP_KERNEL);
 218                 if (!dp83867)
 219                         return -ENOMEM;
 220
 221                 phydev->priv = dp83867;
 222                 ret = dp83867_of_init(phydev);
 223                 if (ret)
 224                         return ret;
 225         } else {
 226                 dp83867 = (struct dp83867_private *)phydev->priv;
 227         }
 228
 229         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 230         if (dp83867->rxctrl_strap_quirk)
 231                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 232                                    BIT(7));
 233
 234         if (phy_interface_is_rgmii(phydev)) {
 235                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 236                 if (val < 0)
 237                         return val;
 238                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 239                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 240
 241                 /* The code below checks if "port mirroring" N/A MODE4 has been
 242                  * enabled during power on bootstrap.
 243                  *
 244                  * Such N/A mode enabled by mistake can put PHY IC in some
 245                  * internal testing mode and disable RGMII transmission.
 246                  *
 247                  * In this particular case one needs to check STRAP_STS1
 248                  * register's bit 11 (marked as RESERVED).
 249                  */
 250
 251                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 252                 if (bs & DP83867_STRAP_STS1_RESERVED)
 253                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 254
 255                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 256                 if (ret)
 257                         return ret;
 258
 259                 /* Set up RGMII delays */
 260                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 261
 262                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 263                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 264
 265                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 266                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 267
 268                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 269                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 270
 271                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 272
 273                 delay = (dp83867->rx_id_delay |
 274                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 275
 276                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 277                               delay);
 278
 279                 if (dp83867->io_impedance >= 0)
 280                         phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 281                                        DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
 282                                        dp83867->io_impedance &
 283                                        DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
 284         }
 285
 286         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 287                 /* For support SPEED_10 in SGMII mode
 288                  * DP83867_10M_SGMII_RATE_ADAPT bit
 289                  * has to be cleared by software. That
 290                  * does not affect SPEED_100 and
 291                  * SPEED_1000.
 292                  */
 293                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 294                                      DP83867_10M_SGMII_CFG,
 295                                      DP83867_10M_SGMII_RATE_ADAPT_MASK,
 296                                      0);
 297                 if (ret)
 298                         return ret;
 299
 300                 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
 301                  * are 01). That is not enough to finalize autoneg on some
 302                  * devices. Increase this timer duration to maximum 16ms.
 303                  */
 304                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 305                                      DP83867_CFG4,
 306                                      DP83867_CFG4_SGMII_ANEG_MASK,
 307                                      DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
 308
 309                 if (ret)
 310                         return ret;
 311         }
 312
 313         /* Enable Interrupt output INT_OE in CFG3 register */
 314         if (phy_interrupt_is_valid(phydev)) {
 315                 val = phy_read(phydev, DP83867_CFG3);
 316                 val |= BIT(7);
 317                 phy_write(phydev, DP83867_CFG3, val);
 318         }
 319
 320         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 321                 dp83867_config_port_mirroring(phydev);
 322
 323         /* Clock output selection if muxing property is set */
 324         if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK)
 325                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 326                                DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,
 327                                dp83867->clk_output_sel <<
 328                                DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 329
 330         return 0;
 331 }
 332
 333 static int dp83867_phy_reset(struct phy_device *phydev)
 334 {
 335         int err;
 336
 337         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 338         if (err < 0)
 339                 return err;
 340
 341         usleep_range(10, 20);
 342
 343         return 0;
 344 }
 345
 346 static struct phy_driver dp83867_driver[] = {
 347         {
 348                 .phy_id         = DP83867_PHY_ID,
 349                 .phy_id_mask    = 0xfffffff0,
 350                 .name           = "TI DP83867",
 351                 /* PHY_GBIT_FEATURES */
 352
 353                 .config_init    = dp83867_config_init,
 354                 .soft_reset     = dp83867_phy_reset,
 355
 356                 /* IRQ related */
 357                 .ack_interrupt  = dp83867_ack_interrupt,
 358                 .config_intr    = dp83867_config_intr,
 359
 360                 .suspend        = genphy_suspend,
 361                 .resume         = genphy_resume,
 362         },
 363 };
 364 module_phy_driver(dp83867_driver);
 365
 366 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 367         { DP83867_PHY_ID, 0xfffffff0 },
 368         { }
 369 };
 370
 371 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 372
 373 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 374 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 375 MODULE_LICENSE("GPL v2");