drivers/net/phy/dp83867.c

   1 /*
   2  * Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/ethtool.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mii.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/phy.h>
  22
  23 #include <dt-bindings/net/ti-dp83867.h>
  24
  25 #define DP83867_PHY_ID          0x2000a231
  26 #define DP83867_DEVADDR         0x1f
  27
  28 #define MII_DP83867_PHYCTRL     0x10
  29 #define MII_DP83867_MICR        0x12
  30 #define MII_DP83867_ISR         0x13
  31 #define DP83867_CTRL            0x1f
  32
  33 /* Extended Registers */
  34 #define DP83867_RGMIICTL        0x0032
  35 #define DP83867_RGMIIDCTL       0x0086
  36
  37 #define DP83867_SW_RESET        BIT(15)
  38 #define DP83867_SW_RESTART      BIT(14)
  39
  40 /* MICR Interrupt bits */
  41 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  42 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  43 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  44 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  45 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  46 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  47 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  48 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  49 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  50 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  51 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  52 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  53
  54 /* RGMIICTL bits */
  55 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  56 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  57
  58 /* PHY CTRL bits */
  59 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  60
  61 /* RGMIIDCTL bits */
  62 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  63
  64 struct dp83867_private {
  65         int rx_id_delay;
  66         int tx_id_delay;
  67         int fifo_depth;
  68         int values_are_sane;
  69 };
  70
  71 static int dp83867_ack_interrupt(struct phy_device *phydev)
  72 {
  73         int err = phy_read(phydev, MII_DP83867_ISR);
  74
  75         if (err < 0)
  76                 return err;
  77
  78         return 0;
  79 }
  80
  81 static int dp83867_config_intr(struct phy_device *phydev)
  82 {
  83         int micr_status;
  84
  85         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  86                 micr_status = phy_read(phydev, MII_DP83867_MICR);
  87                 if (micr_status < 0)
  88                         return micr_status;
  89
  90                 micr_status |=
  91                         (MII_DP83867_MICR_AN_ERR_INT_EN |
  92                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
  93                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
  94                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
  95
  96                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
  97         }
  98
  99         micr_status = 0x0;
 100         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 101 }
 102
 103 #if IS_ENABLED(CONFIG_OF_MDIO)
 104 static int dp83867_of_init(struct phy_device *phydev)
 105 {
 106         struct dp83867_private *dp83867 = phydev->priv;
 107         struct device *dev = &phydev->mdio.dev;
 108         struct device_node *of_node = dev->of_node;
 109         int ret;
 110
 111         if (!of_node)
 112                 return -ENODEV;
 113
 114         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 115                                    &dp83867->rx_id_delay);
 116         if (ret)
 117                 goto invalid_dt;
 118
 119         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 120                                    &dp83867->tx_id_delay);
 121         if (ret)
 122                 goto invalid_dt;
 123
 124         ret = of_property_read_u32(of_node, "ti,fifo-depth",
 125                                    &dp83867->fifo_depth);
 126         if (ret)
 127                 goto invalid_dt;
 128
 129         dp83867->values_are_sane = 1;
 130
 131         return 0;
 132
 133 invalid_dt:
 134         phydev_err(phydev, "missing properties in device tree");
 135
 136         /*
 137          * We can still run with a broken dt by not using any of the optional
 138          * parameters, so just don't set dp83867->values_are_sane.
 139          */
 140         return 0;
 141 }
 142 #else
 143 static int dp83867_of_init(struct phy_device *phydev)
 144 {
 145         return 0;
 146 }
 147 #endif /* CONFIG_OF_MDIO */
 148
 149 static int dp83867_config_init(struct phy_device *phydev)
 150 {
 151         struct dp83867_private *dp83867;
 152         int ret;
 153         u16 val, delay;
 154
 155         if (!phydev->priv) {
 156                 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 157                                        GFP_KERNEL);
 158                 if (!dp83867)
 159                         return -ENOMEM;
 160
 161                 phydev->priv = dp83867;
 162                 ret = dp83867_of_init(phydev);
 163                 if (ret)
 164                         return ret;
 165         } else {
 166                 dp83867 = (struct dp83867_private *)phydev->priv;
 167         }
 168
 169         /*
 170          * With no or broken device tree, we don't have the values that we would
 171          * want to configure the phy with. In that case, cross our fingers and
 172          * assume that firmware did everything correctly for us or that we don't
 173          * need them.
 174          */
 175         if (!dp83867->values_are_sane)
 176                 return 0;
 177
 178         if (phy_interface_is_rgmii(phydev)) {
 179                 ret = phy_write(phydev, MII_DP83867_PHYCTRL,
 180                         (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 181                 if (ret)
 182                         return ret;
 183         }
 184
 185         if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
 186             (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
 187                 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
 188                                             DP83867_DEVADDR);
 189
 190                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 191                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 192
 193                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 194                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 195
 196                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 197                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 198
 199                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 200                                        DP83867_DEVADDR, val);
 201
 202                 delay = (dp83867->rx_id_delay |
 203                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 204
 205                 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 206                                        DP83867_DEVADDR, delay);
 207         }
 208
 209         return 0;
 210 }
 211
 212 static int dp83867_phy_reset(struct phy_device *phydev)
 213 {
 214         int err;
 215
 216         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 217         if (err < 0)
 218                 return err;
 219
 220         return dp83867_config_init(phydev);
 221 }
 222
 223 static struct phy_driver dp83867_driver[] = {
 224         {
 225                 .phy_id         = DP83867_PHY_ID,
 226                 .phy_id_mask    = 0xfffffff0,
 227                 .name           = "TI DP83867",
 228                 .features       = PHY_GBIT_FEATURES,
 229                 .flags          = PHY_HAS_INTERRUPT,
 230
 231                 .config_init    = dp83867_config_init,
 232                 .soft_reset     = dp83867_phy_reset,
 233
 234                 /* IRQ related */
 235                 .ack_interrupt  = dp83867_ack_interrupt,
 236                 .config_intr    = dp83867_config_intr,
 237
 238                 .config_aneg    = genphy_config_aneg,
 239                 .read_status    = genphy_read_status,
 240                 .suspend        = genphy_suspend,
 241                 .resume         = genphy_resume,
 242         },
 243 };
 244 module_phy_driver(dp83867_driver);
 245
 246 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 247         { DP83867_PHY_ID, 0xfffffff0 },
 248         { }
 249 };
 250
 251 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 252
 253 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 254 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 255 MODULE_LICENSE("GPL");