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[mirror_ubuntu-bionic-kernel.git] / drivers / net / phy / marvell.c
1 /*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/ctype.h>
21 #include <linux/errno.h>
22 #include <linux/unistd.h>
23 #include <linux/hwmon.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/skbuff.h>
30 #include <linux/spinlock.h>
31 #include <linux/mm.h>
32 #include <linux/module.h>
33 #include <linux/mii.h>
34 #include <linux/ethtool.h>
35 #include <linux/phy.h>
36 #include <linux/marvell_phy.h>
37 #include <linux/of.h>
38
39 #include <linux/io.h>
40 #include <asm/irq.h>
41 #include <linux/uaccess.h>
42
43 #define MII_MARVELL_PHY_PAGE 22
44
45 #define MII_M1011_IEVENT 0x13
46 #define MII_M1011_IEVENT_CLEAR 0x0000
47
48 #define MII_M1011_IMASK 0x12
49 #define MII_M1011_IMASK_INIT 0x6400
50 #define MII_M1011_IMASK_CLEAR 0x0000
51
52 #define MII_M1011_PHY_SCR 0x10
53 #define MII_M1011_PHY_SCR_MDI 0x0000
54 #define MII_M1011_PHY_SCR_MDI_X 0x0020
55 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
56
57 #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
58 #define MII_M1145_PHY_EXT_SR 0x1b
59 #define MII_M1145_PHY_EXT_CR 0x14
60 #define MII_M1145_RGMII_RX_DELAY 0x0080
61 #define MII_M1145_RGMII_TX_DELAY 0x0002
62 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
63 #define MII_M1145_HWCFG_MODE_MASK 0xf
64 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
65
66 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
67 #define MII_M1145_HWCFG_MODE_MASK 0xf
68 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
69
70 #define MII_M1111_PHY_LED_CONTROL 0x18
71 #define MII_M1111_PHY_LED_DIRECT 0x4100
72 #define MII_M1111_PHY_LED_COMBINE 0x411c
73 #define MII_M1111_PHY_EXT_CR 0x14
74 #define MII_M1111_RX_DELAY 0x80
75 #define MII_M1111_TX_DELAY 0x2
76 #define MII_M1111_PHY_EXT_SR 0x1b
77
78 #define MII_M1111_HWCFG_MODE_MASK 0xf
79 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
80 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
81 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
82 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
83 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
84 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
85
86 #define MII_M1111_COPPER 0
87 #define MII_M1111_FIBER 1
88
89 #define MII_88E1121_PHY_MSCR_PAGE 2
90 #define MII_88E1121_PHY_MSCR_REG 21
91 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
92 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
93 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
94
95 #define MII_88E1121_MISC_TEST 0x1a
96 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
97 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
98 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
99 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
100 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
101 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
102
103 #define MII_88E1510_TEMP_SENSOR 0x1b
104 #define MII_88E1510_TEMP_SENSOR_MASK 0xff
105
106 #define MII_88E1318S_PHY_MSCR1_REG 16
107 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
108
109 /* Copper Specific Interrupt Enable Register */
110 #define MII_88E1318S_PHY_CSIER 0x12
111 /* WOL Event Interrupt Enable */
112 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
113
114 /* LED Timer Control Register */
115 #define MII_88E1318S_PHY_LED_PAGE 0x03
116 #define MII_88E1318S_PHY_LED_TCR 0x12
117 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
118 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
119 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
120
121 /* Magic Packet MAC address registers */
122 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
123 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
124 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
125
126 #define MII_88E1318S_PHY_WOL_PAGE 0x11
127 #define MII_88E1318S_PHY_WOL_CTRL 0x10
128 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
129 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
130
131 #define MII_88E1121_PHY_LED_CTRL 16
132 #define MII_88E1121_PHY_LED_PAGE 3
133 #define MII_88E1121_PHY_LED_DEF 0x0030
134
135 #define MII_M1011_PHY_STATUS 0x11
136 #define MII_M1011_PHY_STATUS_1000 0x8000
137 #define MII_M1011_PHY_STATUS_100 0x4000
138 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
139 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
140 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
141 #define MII_M1011_PHY_STATUS_LINK 0x0400
142
143 #define MII_M1116R_CONTROL_REG_MAC 21
144
145 #define MII_88E3016_PHY_SPEC_CTRL 0x10
146 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
147 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
148
149 #define MII_88E1510_GEN_CTRL_REG_1 0x14
150 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
151 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
152 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
153
154 #define LPA_FIBER_1000HALF 0x40
155 #define LPA_FIBER_1000FULL 0x20
156
157 #define LPA_PAUSE_FIBER 0x180
158 #define LPA_PAUSE_ASYM_FIBER 0x100
159
160 #define ADVERTISE_FIBER_1000HALF 0x40
161 #define ADVERTISE_FIBER_1000FULL 0x20
162
163 #define ADVERTISE_PAUSE_FIBER 0x180
164 #define ADVERTISE_PAUSE_ASYM_FIBER 0x100
165
166 #define REGISTER_LINK_STATUS 0x400
167 #define NB_FIBER_STATS 1
168
169 MODULE_DESCRIPTION("Marvell PHY driver");
170 MODULE_AUTHOR("Andy Fleming");
171 MODULE_LICENSE("GPL");
172
173 struct marvell_hw_stat {
174 const char *string;
175 u8 page;
176 u8 reg;
177 u8 bits;
178 };
179
180 static struct marvell_hw_stat marvell_hw_stats[] = {
181 { "phy_receive_errors_copper", 0, 21, 16},
182 { "phy_idle_errors", 0, 10, 8 },
183 { "phy_receive_errors_fiber", 1, 21, 16},
184 };
185
186 struct marvell_priv {
187 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
188 char *hwmon_name;
189 struct device *hwmon_dev;
190 };
191
192 static int marvell_ack_interrupt(struct phy_device *phydev)
193 {
194 int err;
195
196 /* Clear the interrupts by reading the reg */
197 err = phy_read(phydev, MII_M1011_IEVENT);
198
199 if (err < 0)
200 return err;
201
202 return 0;
203 }
204
205 static int marvell_config_intr(struct phy_device *phydev)
206 {
207 int err;
208
209 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
210 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
211 else
212 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
213
214 return err;
215 }
216
217 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
218 {
219 int reg;
220 int err;
221 int val;
222
223 /* get the current settings */
224 reg = phy_read(phydev, MII_M1011_PHY_SCR);
225 if (reg < 0)
226 return reg;
227
228 val = reg;
229 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
230 switch (polarity) {
231 case ETH_TP_MDI:
232 val |= MII_M1011_PHY_SCR_MDI;
233 break;
234 case ETH_TP_MDI_X:
235 val |= MII_M1011_PHY_SCR_MDI_X;
236 break;
237 case ETH_TP_MDI_AUTO:
238 case ETH_TP_MDI_INVALID:
239 default:
240 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
241 break;
242 }
243
244 if (val != reg) {
245 /* Set the new polarity value in the register */
246 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
247 if (err)
248 return err;
249 }
250
251 return 0;
252 }
253
254 static int marvell_config_aneg(struct phy_device *phydev)
255 {
256 int err;
257
258 /* The Marvell PHY has an errata which requires
259 * that certain registers get written in order
260 * to restart autonegotiation */
261 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
262
263 if (err < 0)
264 return err;
265
266 err = phy_write(phydev, 0x1d, 0x1f);
267 if (err < 0)
268 return err;
269
270 err = phy_write(phydev, 0x1e, 0x200c);
271 if (err < 0)
272 return err;
273
274 err = phy_write(phydev, 0x1d, 0x5);
275 if (err < 0)
276 return err;
277
278 err = phy_write(phydev, 0x1e, 0);
279 if (err < 0)
280 return err;
281
282 err = phy_write(phydev, 0x1e, 0x100);
283 if (err < 0)
284 return err;
285
286 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
287 if (err < 0)
288 return err;
289
290 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
291 MII_M1111_PHY_LED_DIRECT);
292 if (err < 0)
293 return err;
294
295 err = genphy_config_aneg(phydev);
296 if (err < 0)
297 return err;
298
299 if (phydev->autoneg != AUTONEG_ENABLE) {
300 int bmcr;
301
302 /*
303 * A write to speed/duplex bits (that is performed by
304 * genphy_config_aneg() call above) must be followed by
305 * a software reset. Otherwise, the write has no effect.
306 */
307 bmcr = phy_read(phydev, MII_BMCR);
308 if (bmcr < 0)
309 return bmcr;
310
311 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
312 if (err < 0)
313 return err;
314 }
315
316 return 0;
317 }
318
319 static int m88e1111_config_aneg(struct phy_device *phydev)
320 {
321 int err;
322
323 /* The Marvell PHY has an errata which requires
324 * that certain registers get written in order
325 * to restart autonegotiation
326 */
327 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
328
329 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
330 if (err < 0)
331 return err;
332
333 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
334 MII_M1111_PHY_LED_DIRECT);
335 if (err < 0)
336 return err;
337
338 err = genphy_config_aneg(phydev);
339 if (err < 0)
340 return err;
341
342 if (phydev->autoneg != AUTONEG_ENABLE) {
343 int bmcr;
344
345 /* A write to speed/duplex bits (that is performed by
346 * genphy_config_aneg() call above) must be followed by
347 * a software reset. Otherwise, the write has no effect.
348 */
349 bmcr = phy_read(phydev, MII_BMCR);
350 if (bmcr < 0)
351 return bmcr;
352
353 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
354 if (err < 0)
355 return err;
356 }
357
358 return 0;
359 }
360
361 #ifdef CONFIG_OF_MDIO
362 /*
363 * Set and/or override some configuration registers based on the
364 * marvell,reg-init property stored in the of_node for the phydev.
365 *
366 * marvell,reg-init = <reg-page reg mask value>,...;
367 *
368 * There may be one or more sets of <reg-page reg mask value>:
369 *
370 * reg-page: which register bank to use.
371 * reg: the register.
372 * mask: if non-zero, ANDed with existing register value.
373 * value: ORed with the masked value and written to the regiser.
374 *
375 */
376 static int marvell_of_reg_init(struct phy_device *phydev)
377 {
378 const __be32 *paddr;
379 int len, i, saved_page, current_page, ret;
380
381 if (!phydev->mdio.dev.of_node)
382 return 0;
383
384 paddr = of_get_property(phydev->mdio.dev.of_node,
385 "marvell,reg-init", &len);
386 if (!paddr || len < (4 * sizeof(*paddr)))
387 return 0;
388
389 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
390 if (saved_page < 0)
391 return saved_page;
392 current_page = saved_page;
393
394 ret = 0;
395 len /= sizeof(*paddr);
396 for (i = 0; i < len - 3; i += 4) {
397 u16 reg_page = be32_to_cpup(paddr + i);
398 u16 reg = be32_to_cpup(paddr + i + 1);
399 u16 mask = be32_to_cpup(paddr + i + 2);
400 u16 val_bits = be32_to_cpup(paddr + i + 3);
401 int val;
402
403 if (reg_page != current_page) {
404 current_page = reg_page;
405 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
406 if (ret < 0)
407 goto err;
408 }
409
410 val = 0;
411 if (mask) {
412 val = phy_read(phydev, reg);
413 if (val < 0) {
414 ret = val;
415 goto err;
416 }
417 val &= mask;
418 }
419 val |= val_bits;
420
421 ret = phy_write(phydev, reg, val);
422 if (ret < 0)
423 goto err;
424
425 }
426 err:
427 if (current_page != saved_page) {
428 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
429 if (ret == 0)
430 ret = i;
431 }
432 return ret;
433 }
434 #else
435 static int marvell_of_reg_init(struct phy_device *phydev)
436 {
437 return 0;
438 }
439 #endif /* CONFIG_OF_MDIO */
440
441 static int m88e1121_config_aneg(struct phy_device *phydev)
442 {
443 int err, oldpage, mscr;
444
445 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
446
447 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
448 MII_88E1121_PHY_MSCR_PAGE);
449 if (err < 0)
450 return err;
451
452 if (phy_interface_is_rgmii(phydev)) {
453
454 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
455 MII_88E1121_PHY_MSCR_DELAY_MASK;
456
457 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
458 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
459 MII_88E1121_PHY_MSCR_TX_DELAY);
460 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
461 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
462 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
463 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
464
465 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
466 if (err < 0)
467 return err;
468 }
469
470 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
471
472 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
473 if (err < 0)
474 return err;
475
476 err = phy_write(phydev, MII_M1011_PHY_SCR,
477 MII_M1011_PHY_SCR_AUTO_CROSS);
478 if (err < 0)
479 return err;
480
481 return genphy_config_aneg(phydev);
482 }
483
484 static int m88e1318_config_aneg(struct phy_device *phydev)
485 {
486 int err, oldpage, mscr;
487
488 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
489
490 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
491 MII_88E1121_PHY_MSCR_PAGE);
492 if (err < 0)
493 return err;
494
495 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
496 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
497
498 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
499 if (err < 0)
500 return err;
501
502 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
503 if (err < 0)
504 return err;
505
506 return m88e1121_config_aneg(phydev);
507 }
508
509 /**
510 * ethtool_adv_to_fiber_adv_t
511 * @ethadv: the ethtool advertisement settings
512 *
513 * A small helper function that translates ethtool advertisement
514 * settings to phy autonegotiation advertisements for the
515 * MII_ADV register for fiber link.
516 */
517 static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
518 {
519 u32 result = 0;
520
521 if (ethadv & ADVERTISED_1000baseT_Half)
522 result |= ADVERTISE_FIBER_1000HALF;
523 if (ethadv & ADVERTISED_1000baseT_Full)
524 result |= ADVERTISE_FIBER_1000FULL;
525
526 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
527 result |= LPA_PAUSE_ASYM_FIBER;
528 else if (ethadv & ADVERTISE_PAUSE_CAP)
529 result |= (ADVERTISE_PAUSE_FIBER
530 & (~ADVERTISE_PAUSE_ASYM_FIBER));
531
532 return result;
533 }
534
535 /**
536 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
537 * @phydev: target phy_device struct
538 *
539 * Description: If auto-negotiation is enabled, we configure the
540 * advertising, and then restart auto-negotiation. If it is not
541 * enabled, then we write the BMCR. Adapted for fiber link in
542 * some Marvell's devices.
543 */
544 static int marvell_config_aneg_fiber(struct phy_device *phydev)
545 {
546 int changed = 0;
547 int err;
548 int adv, oldadv;
549 u32 advertise;
550
551 if (phydev->autoneg != AUTONEG_ENABLE)
552 return genphy_setup_forced(phydev);
553
554 /* Only allow advertising what this PHY supports */
555 phydev->advertising &= phydev->supported;
556 advertise = phydev->advertising;
557
558 /* Setup fiber advertisement */
559 adv = phy_read(phydev, MII_ADVERTISE);
560 if (adv < 0)
561 return adv;
562
563 oldadv = adv;
564 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
565 | LPA_PAUSE_FIBER);
566 adv |= ethtool_adv_to_fiber_adv_t(advertise);
567
568 if (adv != oldadv) {
569 err = phy_write(phydev, MII_ADVERTISE, adv);
570 if (err < 0)
571 return err;
572
573 changed = 1;
574 }
575
576 if (changed == 0) {
577 /* Advertisement hasn't changed, but maybe aneg was never on to
578 * begin with? Or maybe phy was isolated?
579 */
580 int ctl = phy_read(phydev, MII_BMCR);
581
582 if (ctl < 0)
583 return ctl;
584
585 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
586 changed = 1; /* do restart aneg */
587 }
588
589 /* Only restart aneg if we are advertising something different
590 * than we were before.
591 */
592 if (changed > 0)
593 changed = genphy_restart_aneg(phydev);
594
595 return changed;
596 }
597
598 static int m88e1510_config_aneg(struct phy_device *phydev)
599 {
600 int err;
601
602 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
603 if (err < 0)
604 goto error;
605
606 /* Configure the copper link first */
607 err = m88e1318_config_aneg(phydev);
608 if (err < 0)
609 goto error;
610
611 /* Then the fiber link */
612 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
613 if (err < 0)
614 goto error;
615
616 err = marvell_config_aneg_fiber(phydev);
617 if (err < 0)
618 goto error;
619
620 return phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
621
622 error:
623 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
624 return err;
625 }
626
627 static int marvell_config_init(struct phy_device *phydev)
628 {
629 /* Set registers from marvell,reg-init DT property */
630 return marvell_of_reg_init(phydev);
631 }
632
633 static int m88e1116r_config_init(struct phy_device *phydev)
634 {
635 int temp;
636 int err;
637
638 temp = phy_read(phydev, MII_BMCR);
639 temp |= BMCR_RESET;
640 err = phy_write(phydev, MII_BMCR, temp);
641 if (err < 0)
642 return err;
643
644 mdelay(500);
645
646 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
647 if (err < 0)
648 return err;
649
650 temp = phy_read(phydev, MII_M1011_PHY_SCR);
651 temp |= (7 << 12); /* max number of gigabit attempts */
652 temp |= (1 << 11); /* enable downshift */
653 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
654 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
655 if (err < 0)
656 return err;
657
658 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
659 if (err < 0)
660 return err;
661 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
662 temp |= (1 << 5);
663 temp |= (1 << 4);
664 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
665 if (err < 0)
666 return err;
667 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
668 if (err < 0)
669 return err;
670
671 temp = phy_read(phydev, MII_BMCR);
672 temp |= BMCR_RESET;
673 err = phy_write(phydev, MII_BMCR, temp);
674 if (err < 0)
675 return err;
676
677 mdelay(500);
678
679 return marvell_config_init(phydev);
680 }
681
682 static int m88e3016_config_init(struct phy_device *phydev)
683 {
684 int reg;
685
686 /* Enable Scrambler and Auto-Crossover */
687 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
688 if (reg < 0)
689 return reg;
690
691 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
692 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
693
694 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
695 if (reg < 0)
696 return reg;
697
698 return marvell_config_init(phydev);
699 }
700
701 static int m88e1111_config_init(struct phy_device *phydev)
702 {
703 int err;
704 int temp;
705
706 if (phy_interface_is_rgmii(phydev)) {
707
708 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
709 if (temp < 0)
710 return temp;
711
712 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
713 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
714 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
715 temp &= ~MII_M1111_TX_DELAY;
716 temp |= MII_M1111_RX_DELAY;
717 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
718 temp &= ~MII_M1111_RX_DELAY;
719 temp |= MII_M1111_TX_DELAY;
720 }
721
722 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
723 if (err < 0)
724 return err;
725
726 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
727 if (temp < 0)
728 return temp;
729
730 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
731
732 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
733 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
734 else
735 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
736
737 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
738 if (err < 0)
739 return err;
740 }
741
742 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
743 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
744 if (temp < 0)
745 return temp;
746
747 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
748 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
749 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
750
751 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
752 if (err < 0)
753 return err;
754
755 /* make sure copper is selected */
756 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
757 if (err < 0)
758 return err;
759
760 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
761 err & (~0xff));
762 if (err < 0)
763 return err;
764 }
765
766 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
767 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
768 if (temp < 0)
769 return temp;
770 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
771 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
772 if (err < 0)
773 return err;
774
775 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
776 if (temp < 0)
777 return temp;
778 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
779 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
780 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
781 if (err < 0)
782 return err;
783
784 /* soft reset */
785 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
786 if (err < 0)
787 return err;
788 do
789 temp = phy_read(phydev, MII_BMCR);
790 while (temp & BMCR_RESET);
791
792 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
793 if (temp < 0)
794 return temp;
795 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
796 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
797 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
798 if (err < 0)
799 return err;
800 }
801
802 err = marvell_of_reg_init(phydev);
803 if (err < 0)
804 return err;
805
806 return phy_write(phydev, MII_BMCR, BMCR_RESET);
807 }
808
809 static int m88e1121_config_init(struct phy_device *phydev)
810 {
811 int err, oldpage;
812
813 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
814
815 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
816 if (err < 0)
817 return err;
818
819 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
820 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
821 MII_88E1121_PHY_LED_DEF);
822 if (err < 0)
823 return err;
824
825 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
826
827 /* Set marvell,reg-init configuration from device tree */
828 return marvell_config_init(phydev);
829 }
830
831 static int m88e1510_config_init(struct phy_device *phydev)
832 {
833 int err;
834 int temp;
835
836 /* SGMII-to-Copper mode initialization */
837 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
838 /* Select page 18 */
839 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18);
840 if (err < 0)
841 return err;
842
843 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
844 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
845 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
846 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
847 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
848 if (err < 0)
849 return err;
850
851 /* PHY reset is necessary after changing MODE[2:0] */
852 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
853 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
854 if (err < 0)
855 return err;
856
857 /* Reset page selection */
858 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
859 if (err < 0)
860 return err;
861 }
862
863 return m88e1121_config_init(phydev);
864 }
865
866 static int m88e1118_config_aneg(struct phy_device *phydev)
867 {
868 int err;
869
870 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
871 if (err < 0)
872 return err;
873
874 err = phy_write(phydev, MII_M1011_PHY_SCR,
875 MII_M1011_PHY_SCR_AUTO_CROSS);
876 if (err < 0)
877 return err;
878
879 err = genphy_config_aneg(phydev);
880 return 0;
881 }
882
883 static int m88e1118_config_init(struct phy_device *phydev)
884 {
885 int err;
886
887 /* Change address */
888 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
889 if (err < 0)
890 return err;
891
892 /* Enable 1000 Mbit */
893 err = phy_write(phydev, 0x15, 0x1070);
894 if (err < 0)
895 return err;
896
897 /* Change address */
898 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
899 if (err < 0)
900 return err;
901
902 /* Adjust LED Control */
903 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
904 err = phy_write(phydev, 0x10, 0x1100);
905 else
906 err = phy_write(phydev, 0x10, 0x021e);
907 if (err < 0)
908 return err;
909
910 err = marvell_of_reg_init(phydev);
911 if (err < 0)
912 return err;
913
914 /* Reset address */
915 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
916 if (err < 0)
917 return err;
918
919 return phy_write(phydev, MII_BMCR, BMCR_RESET);
920 }
921
922 static int m88e1149_config_init(struct phy_device *phydev)
923 {
924 int err;
925
926 /* Change address */
927 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
928 if (err < 0)
929 return err;
930
931 /* Enable 1000 Mbit */
932 err = phy_write(phydev, 0x15, 0x1048);
933 if (err < 0)
934 return err;
935
936 err = marvell_of_reg_init(phydev);
937 if (err < 0)
938 return err;
939
940 /* Reset address */
941 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
942 if (err < 0)
943 return err;
944
945 return phy_write(phydev, MII_BMCR, BMCR_RESET);
946 }
947
948 static int m88e1145_config_init(struct phy_device *phydev)
949 {
950 int err;
951 int temp;
952
953 /* Take care of errata E0 & E1 */
954 err = phy_write(phydev, 0x1d, 0x001b);
955 if (err < 0)
956 return err;
957
958 err = phy_write(phydev, 0x1e, 0x418f);
959 if (err < 0)
960 return err;
961
962 err = phy_write(phydev, 0x1d, 0x0016);
963 if (err < 0)
964 return err;
965
966 err = phy_write(phydev, 0x1e, 0xa2da);
967 if (err < 0)
968 return err;
969
970 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
971 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
972 if (temp < 0)
973 return temp;
974
975 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
976
977 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
978 if (err < 0)
979 return err;
980
981 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
982 err = phy_write(phydev, 0x1d, 0x0012);
983 if (err < 0)
984 return err;
985
986 temp = phy_read(phydev, 0x1e);
987 if (temp < 0)
988 return temp;
989
990 temp &= 0xf03f;
991 temp |= 2 << 9; /* 36 ohm */
992 temp |= 2 << 6; /* 39 ohm */
993
994 err = phy_write(phydev, 0x1e, temp);
995 if (err < 0)
996 return err;
997
998 err = phy_write(phydev, 0x1d, 0x3);
999 if (err < 0)
1000 return err;
1001
1002 err = phy_write(phydev, 0x1e, 0x8000);
1003 if (err < 0)
1004 return err;
1005 }
1006 }
1007
1008 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1009 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
1010 if (temp < 0)
1011 return temp;
1012
1013 temp &= ~MII_M1145_HWCFG_MODE_MASK;
1014 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
1015 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
1016
1017 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
1018 if (err < 0)
1019 return err;
1020 }
1021
1022 err = marvell_of_reg_init(phydev);
1023 if (err < 0)
1024 return err;
1025
1026 return 0;
1027 }
1028
1029 /**
1030 * fiber_lpa_to_ethtool_lpa_t
1031 * @lpa: value of the MII_LPA register for fiber link
1032 *
1033 * A small helper function that translates MII_LPA
1034 * bits to ethtool LP advertisement settings.
1035 */
1036 static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1037 {
1038 u32 result = 0;
1039
1040 if (lpa & LPA_FIBER_1000HALF)
1041 result |= ADVERTISED_1000baseT_Half;
1042 if (lpa & LPA_FIBER_1000FULL)
1043 result |= ADVERTISED_1000baseT_Full;
1044
1045 return result;
1046 }
1047
1048 /**
1049 * marvell_update_link - update link status in real time in @phydev
1050 * @phydev: target phy_device struct
1051 *
1052 * Description: Update the value in phydev->link to reflect the
1053 * current link value.
1054 */
1055 static int marvell_update_link(struct phy_device *phydev, int fiber)
1056 {
1057 int status;
1058
1059 /* Use the generic register for copper link, or specific
1060 * register for fiber case */
1061 if (fiber) {
1062 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1063 if (status < 0)
1064 return status;
1065
1066 if ((status & REGISTER_LINK_STATUS) == 0)
1067 phydev->link = 0;
1068 else
1069 phydev->link = 1;
1070 } else {
1071 return genphy_update_link(phydev);
1072 }
1073
1074 return 0;
1075 }
1076
1077 /* marvell_read_status_page
1078 *
1079 * Description:
1080 * Check the link, then figure out the current state
1081 * by comparing what we advertise with what the link partner
1082 * advertises. Start by checking the gigabit possibilities,
1083 * then move on to 10/100.
1084 */
1085 static int marvell_read_status_page(struct phy_device *phydev, int page)
1086 {
1087 int adv;
1088 int err;
1089 int lpa;
1090 int lpagb;
1091 int status = 0;
1092 int fiber;
1093
1094 /* Detect and update the link, but return if there
1095 * was an error */
1096 if (page == MII_M1111_FIBER)
1097 fiber = 1;
1098 else
1099 fiber = 0;
1100
1101 err = marvell_update_link(phydev, fiber);
1102 if (err)
1103 return err;
1104
1105 if (AUTONEG_ENABLE == phydev->autoneg) {
1106 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1107 if (status < 0)
1108 return status;
1109
1110 lpa = phy_read(phydev, MII_LPA);
1111 if (lpa < 0)
1112 return lpa;
1113
1114 lpagb = phy_read(phydev, MII_STAT1000);
1115 if (lpagb < 0)
1116 return lpagb;
1117
1118 adv = phy_read(phydev, MII_ADVERTISE);
1119 if (adv < 0)
1120 return adv;
1121
1122 lpa &= adv;
1123
1124 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1125 phydev->duplex = DUPLEX_FULL;
1126 else
1127 phydev->duplex = DUPLEX_HALF;
1128
1129 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1130 phydev->pause = phydev->asym_pause = 0;
1131
1132 switch (status) {
1133 case MII_M1011_PHY_STATUS_1000:
1134 phydev->speed = SPEED_1000;
1135 break;
1136
1137 case MII_M1011_PHY_STATUS_100:
1138 phydev->speed = SPEED_100;
1139 break;
1140
1141 default:
1142 phydev->speed = SPEED_10;
1143 break;
1144 }
1145
1146 if (!fiber) {
1147 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
1148 mii_lpa_to_ethtool_lpa_t(lpa);
1149
1150 if (phydev->duplex == DUPLEX_FULL) {
1151 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1152 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1153 }
1154 } else {
1155 /* The fiber link is only 1000M capable */
1156 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1157
1158 if (phydev->duplex == DUPLEX_FULL) {
1159 if (!(lpa & LPA_PAUSE_FIBER)) {
1160 phydev->pause = 0;
1161 phydev->asym_pause = 0;
1162 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1163 phydev->pause = 1;
1164 phydev->asym_pause = 1;
1165 } else {
1166 phydev->pause = 1;
1167 phydev->asym_pause = 0;
1168 }
1169 }
1170 }
1171 } else {
1172 int bmcr = phy_read(phydev, MII_BMCR);
1173
1174 if (bmcr < 0)
1175 return bmcr;
1176
1177 if (bmcr & BMCR_FULLDPLX)
1178 phydev->duplex = DUPLEX_FULL;
1179 else
1180 phydev->duplex = DUPLEX_HALF;
1181
1182 if (bmcr & BMCR_SPEED1000)
1183 phydev->speed = SPEED_1000;
1184 else if (bmcr & BMCR_SPEED100)
1185 phydev->speed = SPEED_100;
1186 else
1187 phydev->speed = SPEED_10;
1188
1189 phydev->pause = phydev->asym_pause = 0;
1190 phydev->lp_advertising = 0;
1191 }
1192
1193 return 0;
1194 }
1195
1196 /* marvell_read_status
1197 *
1198 * Some Marvell's phys have two modes: fiber and copper.
1199 * Both need status checked.
1200 * Description:
1201 * First, check the fiber link and status.
1202 * If the fiber link is down, check the copper link and status which
1203 * will be the default value if both link are down.
1204 */
1205 static int marvell_read_status(struct phy_device *phydev)
1206 {
1207 int err;
1208
1209 /* Check the fiber mode first */
1210 if (phydev->supported & SUPPORTED_FIBRE &&
1211 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1212 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1213 if (err < 0)
1214 goto error;
1215
1216 err = marvell_read_status_page(phydev, MII_M1111_FIBER);
1217 if (err < 0)
1218 goto error;
1219
1220 /* If the fiber link is up, it is the selected and used link.
1221 * In this case, we need to stay in the fiber page.
1222 * Please to be careful about that, avoid to restore Copper page
1223 * in other functions which could break the behaviour
1224 * for some fiber phy like 88E1512.
1225 * */
1226 if (phydev->link)
1227 return 0;
1228
1229 /* If fiber link is down, check and save copper mode state */
1230 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1231 if (err < 0)
1232 goto error;
1233 }
1234
1235 return marvell_read_status_page(phydev, MII_M1111_COPPER);
1236
1237 error:
1238 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1239 return err;
1240 }
1241
1242 /* marvell_suspend
1243 *
1244 * Some Marvell's phys have two modes: fiber and copper.
1245 * Both need to be suspended
1246 */
1247 static int marvell_suspend(struct phy_device *phydev)
1248 {
1249 int err;
1250
1251 /* Suspend the fiber mode first */
1252 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1253 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1254 if (err < 0)
1255 goto error;
1256
1257 /* With the page set, use the generic suspend */
1258 err = genphy_suspend(phydev);
1259 if (err < 0)
1260 goto error;
1261
1262 /* Then, the copper link */
1263 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1264 if (err < 0)
1265 goto error;
1266 }
1267
1268 /* With the page set, use the generic suspend */
1269 return genphy_suspend(phydev);
1270
1271 error:
1272 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1273 return err;
1274 }
1275
1276 /* marvell_resume
1277 *
1278 * Some Marvell's phys have two modes: fiber and copper.
1279 * Both need to be resumed
1280 */
1281 static int marvell_resume(struct phy_device *phydev)
1282 {
1283 int err;
1284
1285 /* Resume the fiber mode first */
1286 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1287 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1288 if (err < 0)
1289 goto error;
1290
1291 /* With the page set, use the generic resume */
1292 err = genphy_resume(phydev);
1293 if (err < 0)
1294 goto error;
1295
1296 /* Then, the copper link */
1297 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1298 if (err < 0)
1299 goto error;
1300 }
1301
1302 /* With the page set, use the generic resume */
1303 return genphy_resume(phydev);
1304
1305 error:
1306 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1307 return err;
1308 }
1309
1310 static int marvell_aneg_done(struct phy_device *phydev)
1311 {
1312 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1313 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1314 }
1315
1316 static int m88e1121_did_interrupt(struct phy_device *phydev)
1317 {
1318 int imask;
1319
1320 imask = phy_read(phydev, MII_M1011_IEVENT);
1321
1322 if (imask & MII_M1011_IMASK_INIT)
1323 return 1;
1324
1325 return 0;
1326 }
1327
1328 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1329 {
1330 wol->supported = WAKE_MAGIC;
1331 wol->wolopts = 0;
1332
1333 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
1334 MII_88E1318S_PHY_WOL_PAGE) < 0)
1335 return;
1336
1337 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1338 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1339 wol->wolopts |= WAKE_MAGIC;
1340
1341 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
1342 return;
1343 }
1344
1345 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1346 {
1347 int err, oldpage, temp;
1348
1349 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1350
1351 if (wol->wolopts & WAKE_MAGIC) {
1352 /* Explicitly switch to page 0x00, just to be sure */
1353 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
1354 if (err < 0)
1355 return err;
1356
1357 /* Enable the WOL interrupt */
1358 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1359 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1360 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1361 if (err < 0)
1362 return err;
1363
1364 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1365 MII_88E1318S_PHY_LED_PAGE);
1366 if (err < 0)
1367 return err;
1368
1369 /* Setup LED[2] as interrupt pin (active low) */
1370 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1371 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1372 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1373 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1374 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1375 if (err < 0)
1376 return err;
1377
1378 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1379 MII_88E1318S_PHY_WOL_PAGE);
1380 if (err < 0)
1381 return err;
1382
1383 /* Store the device address for the magic packet */
1384 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1385 ((phydev->attached_dev->dev_addr[5] << 8) |
1386 phydev->attached_dev->dev_addr[4]));
1387 if (err < 0)
1388 return err;
1389 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1390 ((phydev->attached_dev->dev_addr[3] << 8) |
1391 phydev->attached_dev->dev_addr[2]));
1392 if (err < 0)
1393 return err;
1394 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1395 ((phydev->attached_dev->dev_addr[1] << 8) |
1396 phydev->attached_dev->dev_addr[0]));
1397 if (err < 0)
1398 return err;
1399
1400 /* Clear WOL status and enable magic packet matching */
1401 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1402 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1403 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1404 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1405 if (err < 0)
1406 return err;
1407 } else {
1408 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1409 MII_88E1318S_PHY_WOL_PAGE);
1410 if (err < 0)
1411 return err;
1412
1413 /* Clear WOL status and disable magic packet matching */
1414 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1415 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1416 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1417 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1418 if (err < 0)
1419 return err;
1420 }
1421
1422 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1423 if (err < 0)
1424 return err;
1425
1426 return 0;
1427 }
1428
1429 static int marvell_get_sset_count(struct phy_device *phydev)
1430 {
1431 if (phydev->supported & SUPPORTED_FIBRE)
1432 return ARRAY_SIZE(marvell_hw_stats);
1433 else
1434 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1435 }
1436
1437 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1438 {
1439 int i;
1440
1441 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1442 memcpy(data + i * ETH_GSTRING_LEN,
1443 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1444 }
1445 }
1446
1447 #ifndef UINT64_MAX
1448 #define UINT64_MAX (u64)(~((u64)0))
1449 #endif
1450 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1451 {
1452 struct marvell_hw_stat stat = marvell_hw_stats[i];
1453 struct marvell_priv *priv = phydev->priv;
1454 int err, oldpage, val;
1455 u64 ret;
1456
1457 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1458 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1459 stat.page);
1460 if (err < 0)
1461 return UINT64_MAX;
1462
1463 val = phy_read(phydev, stat.reg);
1464 if (val < 0) {
1465 ret = UINT64_MAX;
1466 } else {
1467 val = val & ((1 << stat.bits) - 1);
1468 priv->stats[i] += val;
1469 ret = priv->stats[i];
1470 }
1471
1472 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1473
1474 return ret;
1475 }
1476
1477 static void marvell_get_stats(struct phy_device *phydev,
1478 struct ethtool_stats *stats, u64 *data)
1479 {
1480 int i;
1481
1482 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1483 data[i] = marvell_get_stat(phydev, i);
1484 }
1485
1486 #ifdef CONFIG_HWMON
1487 static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
1488 {
1489 int ret;
1490 int val;
1491
1492 *temp = 0;
1493
1494 mutex_lock(&phydev->lock);
1495
1496 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1497 if (ret < 0)
1498 goto error;
1499
1500 /* Enable temperature sensor */
1501 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1502 if (ret < 0)
1503 goto error;
1504
1505 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1506 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1507 if (ret < 0)
1508 goto error;
1509
1510 /* Wait for temperature to stabilize */
1511 usleep_range(10000, 12000);
1512
1513 val = phy_read(phydev, MII_88E1121_MISC_TEST);
1514 if (val < 0) {
1515 ret = val;
1516 goto error;
1517 }
1518
1519 /* Disable temperature sensor */
1520 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1521 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1522 if (ret < 0)
1523 goto error;
1524
1525 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
1526
1527 error:
1528 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1529 mutex_unlock(&phydev->lock);
1530
1531 return ret;
1532 }
1533
1534 static int m88e1121_hwmon_read(struct device *dev,
1535 enum hwmon_sensor_types type,
1536 u32 attr, int channel, long *temp)
1537 {
1538 struct phy_device *phydev = dev_get_drvdata(dev);
1539 int err;
1540
1541 switch (attr) {
1542 case hwmon_temp_input:
1543 err = m88e1121_get_temp(phydev, temp);
1544 break;
1545 default:
1546 return -EOPNOTSUPP;
1547 }
1548
1549 return err;
1550 }
1551
1552 static umode_t m88e1121_hwmon_is_visible(const void *data,
1553 enum hwmon_sensor_types type,
1554 u32 attr, int channel)
1555 {
1556 if (type != hwmon_temp)
1557 return 0;
1558
1559 switch (attr) {
1560 case hwmon_temp_input:
1561 return 0444;
1562 default:
1563 return 0;
1564 }
1565 }
1566
1567 static u32 m88e1121_hwmon_chip_config[] = {
1568 HWMON_C_REGISTER_TZ,
1569 0
1570 };
1571
1572 static const struct hwmon_channel_info m88e1121_hwmon_chip = {
1573 .type = hwmon_chip,
1574 .config = m88e1121_hwmon_chip_config,
1575 };
1576
1577 static u32 m88e1121_hwmon_temp_config[] = {
1578 HWMON_T_INPUT,
1579 0
1580 };
1581
1582 static const struct hwmon_channel_info m88e1121_hwmon_temp = {
1583 .type = hwmon_temp,
1584 .config = m88e1121_hwmon_temp_config,
1585 };
1586
1587 static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {
1588 &m88e1121_hwmon_chip,
1589 &m88e1121_hwmon_temp,
1590 NULL
1591 };
1592
1593 static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {
1594 .is_visible = m88e1121_hwmon_is_visible,
1595 .read = m88e1121_hwmon_read,
1596 };
1597
1598 static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {
1599 .ops = &m88e1121_hwmon_hwmon_ops,
1600 .info = m88e1121_hwmon_info,
1601 };
1602
1603 static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
1604 {
1605 int ret;
1606
1607 *temp = 0;
1608
1609 mutex_lock(&phydev->lock);
1610
1611 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1612 if (ret < 0)
1613 goto error;
1614
1615 ret = phy_read(phydev, MII_88E1510_TEMP_SENSOR);
1616 if (ret < 0)
1617 goto error;
1618
1619 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
1620
1621 error:
1622 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1623 mutex_unlock(&phydev->lock);
1624
1625 return ret;
1626 }
1627
1628 int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
1629 {
1630 int ret;
1631
1632 *temp = 0;
1633
1634 mutex_lock(&phydev->lock);
1635
1636 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1637 if (ret < 0)
1638 goto error;
1639
1640 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1641 if (ret < 0)
1642 goto error;
1643
1644 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
1645 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
1646 /* convert to mC */
1647 *temp *= 1000;
1648
1649 error:
1650 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1651 mutex_unlock(&phydev->lock);
1652
1653 return ret;
1654 }
1655
1656 int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
1657 {
1658 int ret;
1659
1660 mutex_lock(&phydev->lock);
1661
1662 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1663 if (ret < 0)
1664 goto error;
1665
1666 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1667 if (ret < 0)
1668 goto error;
1669
1670 temp = temp / 1000;
1671 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
1672 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1673 (ret & ~MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) |
1674 (temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT));
1675
1676 error:
1677 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1678 mutex_unlock(&phydev->lock);
1679
1680 return ret;
1681 }
1682
1683 int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
1684 {
1685 int ret;
1686
1687 *alarm = false;
1688
1689 mutex_lock(&phydev->lock);
1690
1691 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1692 if (ret < 0)
1693 goto error;
1694
1695 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1696 if (ret < 0)
1697 goto error;
1698 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
1699
1700 error:
1701 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1702 mutex_unlock(&phydev->lock);
1703
1704 return ret;
1705 }
1706
1707 static int m88e1510_hwmon_read(struct device *dev,
1708 enum hwmon_sensor_types type,
1709 u32 attr, int channel, long *temp)
1710 {
1711 struct phy_device *phydev = dev_get_drvdata(dev);
1712 int err;
1713
1714 switch (attr) {
1715 case hwmon_temp_input:
1716 err = m88e1510_get_temp(phydev, temp);
1717 break;
1718 case hwmon_temp_crit:
1719 err = m88e1510_get_temp_critical(phydev, temp);
1720 break;
1721 case hwmon_temp_max_alarm:
1722 err = m88e1510_get_temp_alarm(phydev, temp);
1723 break;
1724 default:
1725 return -EOPNOTSUPP;
1726 }
1727
1728 return err;
1729 }
1730
1731 static int m88e1510_hwmon_write(struct device *dev,
1732 enum hwmon_sensor_types type,
1733 u32 attr, int channel, long temp)
1734 {
1735 struct phy_device *phydev = dev_get_drvdata(dev);
1736 int err;
1737
1738 switch (attr) {
1739 case hwmon_temp_crit:
1740 err = m88e1510_set_temp_critical(phydev, temp);
1741 break;
1742 default:
1743 return -EOPNOTSUPP;
1744 }
1745 return err;
1746 }
1747
1748 static umode_t m88e1510_hwmon_is_visible(const void *data,
1749 enum hwmon_sensor_types type,
1750 u32 attr, int channel)
1751 {
1752 if (type != hwmon_temp)
1753 return 0;
1754
1755 switch (attr) {
1756 case hwmon_temp_input:
1757 case hwmon_temp_max_alarm:
1758 return 0444;
1759 case hwmon_temp_crit:
1760 return 0644;
1761 default:
1762 return 0;
1763 }
1764 }
1765
1766 static u32 m88e1510_hwmon_temp_config[] = {
1767 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
1768 0
1769 };
1770
1771 static const struct hwmon_channel_info m88e1510_hwmon_temp = {
1772 .type = hwmon_temp,
1773 .config = m88e1510_hwmon_temp_config,
1774 };
1775
1776 static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {
1777 &m88e1121_hwmon_chip,
1778 &m88e1510_hwmon_temp,
1779 NULL
1780 };
1781
1782 static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {
1783 .is_visible = m88e1510_hwmon_is_visible,
1784 .read = m88e1510_hwmon_read,
1785 .write = m88e1510_hwmon_write,
1786 };
1787
1788 static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {
1789 .ops = &m88e1510_hwmon_hwmon_ops,
1790 .info = m88e1510_hwmon_info,
1791 };
1792
1793 static int marvell_hwmon_name(struct phy_device *phydev)
1794 {
1795 struct marvell_priv *priv = phydev->priv;
1796 struct device *dev = &phydev->mdio.dev;
1797 const char *devname = dev_name(dev);
1798 size_t len = strlen(devname);
1799 int i, j;
1800
1801 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
1802 if (!priv->hwmon_name)
1803 return -ENOMEM;
1804
1805 for (i = j = 0; i < len && devname[i]; i++) {
1806 if (isalnum(devname[i]))
1807 priv->hwmon_name[j++] = devname[i];
1808 }
1809
1810 return 0;
1811 }
1812
1813 static int marvell_hwmon_probe(struct phy_device *phydev,
1814 const struct hwmon_chip_info *chip)
1815 {
1816 struct marvell_priv *priv = phydev->priv;
1817 struct device *dev = &phydev->mdio.dev;
1818 int err;
1819
1820 err = marvell_hwmon_name(phydev);
1821 if (err)
1822 return err;
1823
1824 priv->hwmon_dev = devm_hwmon_device_register_with_info(
1825 dev, priv->hwmon_name, phydev, chip, NULL);
1826
1827 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
1828 }
1829
1830 static int m88e1121_hwmon_probe(struct phy_device *phydev)
1831 {
1832 return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);
1833 }
1834
1835 static int m88e1510_hwmon_probe(struct phy_device *phydev)
1836 {
1837 return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);
1838 }
1839 #else
1840 static int m88e1121_hwmon_probe(struct phy_device *phydev)
1841 {
1842 return 0;
1843 }
1844
1845 static int m88e1510_hwmon_probe(struct phy_device *phydev)
1846 {
1847 return 0;
1848 }
1849 #endif
1850
1851 static int marvell_probe(struct phy_device *phydev)
1852 {
1853 struct marvell_priv *priv;
1854
1855 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1856 if (!priv)
1857 return -ENOMEM;
1858
1859 phydev->priv = priv;
1860
1861 return 0;
1862 }
1863
1864 static int m88e1121_probe(struct phy_device *phydev)
1865 {
1866 int err;
1867
1868 err = marvell_probe(phydev);
1869 if (err)
1870 return err;
1871
1872 return m88e1121_hwmon_probe(phydev);
1873 }
1874
1875 static int m88e1510_probe(struct phy_device *phydev)
1876 {
1877 int err;
1878
1879 err = marvell_probe(phydev);
1880 if (err)
1881 return err;
1882
1883 return m88e1510_hwmon_probe(phydev);
1884 }
1885
1886 static struct phy_driver marvell_drivers[] = {
1887 {
1888 .phy_id = MARVELL_PHY_ID_88E1101,
1889 .phy_id_mask = MARVELL_PHY_ID_MASK,
1890 .name = "Marvell 88E1101",
1891 .features = PHY_GBIT_FEATURES,
1892 .flags = PHY_HAS_INTERRUPT,
1893 .probe = marvell_probe,
1894 .config_init = &marvell_config_init,
1895 .config_aneg = &marvell_config_aneg,
1896 .read_status = &genphy_read_status,
1897 .ack_interrupt = &marvell_ack_interrupt,
1898 .config_intr = &marvell_config_intr,
1899 .resume = &genphy_resume,
1900 .suspend = &genphy_suspend,
1901 .get_sset_count = marvell_get_sset_count,
1902 .get_strings = marvell_get_strings,
1903 .get_stats = marvell_get_stats,
1904 },
1905 {
1906 .phy_id = MARVELL_PHY_ID_88E1112,
1907 .phy_id_mask = MARVELL_PHY_ID_MASK,
1908 .name = "Marvell 88E1112",
1909 .features = PHY_GBIT_FEATURES,
1910 .flags = PHY_HAS_INTERRUPT,
1911 .probe = marvell_probe,
1912 .config_init = &m88e1111_config_init,
1913 .config_aneg = &marvell_config_aneg,
1914 .read_status = &genphy_read_status,
1915 .ack_interrupt = &marvell_ack_interrupt,
1916 .config_intr = &marvell_config_intr,
1917 .resume = &genphy_resume,
1918 .suspend = &genphy_suspend,
1919 .get_sset_count = marvell_get_sset_count,
1920 .get_strings = marvell_get_strings,
1921 .get_stats = marvell_get_stats,
1922 },
1923 {
1924 .phy_id = MARVELL_PHY_ID_88E1111,
1925 .phy_id_mask = MARVELL_PHY_ID_MASK,
1926 .name = "Marvell 88E1111",
1927 .features = PHY_GBIT_FEATURES,
1928 .flags = PHY_HAS_INTERRUPT,
1929 .probe = marvell_probe,
1930 .config_init = &m88e1111_config_init,
1931 .config_aneg = &m88e1111_config_aneg,
1932 .read_status = &marvell_read_status,
1933 .ack_interrupt = &marvell_ack_interrupt,
1934 .config_intr = &marvell_config_intr,
1935 .resume = &genphy_resume,
1936 .suspend = &genphy_suspend,
1937 .get_sset_count = marvell_get_sset_count,
1938 .get_strings = marvell_get_strings,
1939 .get_stats = marvell_get_stats,
1940 },
1941 {
1942 .phy_id = MARVELL_PHY_ID_88E1118,
1943 .phy_id_mask = MARVELL_PHY_ID_MASK,
1944 .name = "Marvell 88E1118",
1945 .features = PHY_GBIT_FEATURES,
1946 .flags = PHY_HAS_INTERRUPT,
1947 .probe = marvell_probe,
1948 .config_init = &m88e1118_config_init,
1949 .config_aneg = &m88e1118_config_aneg,
1950 .read_status = &genphy_read_status,
1951 .ack_interrupt = &marvell_ack_interrupt,
1952 .config_intr = &marvell_config_intr,
1953 .resume = &genphy_resume,
1954 .suspend = &genphy_suspend,
1955 .get_sset_count = marvell_get_sset_count,
1956 .get_strings = marvell_get_strings,
1957 .get_stats = marvell_get_stats,
1958 },
1959 {
1960 .phy_id = MARVELL_PHY_ID_88E1121R,
1961 .phy_id_mask = MARVELL_PHY_ID_MASK,
1962 .name = "Marvell 88E1121R",
1963 .features = PHY_GBIT_FEATURES,
1964 .flags = PHY_HAS_INTERRUPT,
1965 .probe = &m88e1121_probe,
1966 .config_init = &m88e1121_config_init,
1967 .config_aneg = &m88e1121_config_aneg,
1968 .read_status = &marvell_read_status,
1969 .ack_interrupt = &marvell_ack_interrupt,
1970 .config_intr = &marvell_config_intr,
1971 .did_interrupt = &m88e1121_did_interrupt,
1972 .resume = &genphy_resume,
1973 .suspend = &genphy_suspend,
1974 .get_sset_count = marvell_get_sset_count,
1975 .get_strings = marvell_get_strings,
1976 .get_stats = marvell_get_stats,
1977 },
1978 {
1979 .phy_id = MARVELL_PHY_ID_88E1318S,
1980 .phy_id_mask = MARVELL_PHY_ID_MASK,
1981 .name = "Marvell 88E1318S",
1982 .features = PHY_GBIT_FEATURES,
1983 .flags = PHY_HAS_INTERRUPT,
1984 .probe = marvell_probe,
1985 .config_init = &m88e1121_config_init,
1986 .config_aneg = &m88e1318_config_aneg,
1987 .read_status = &marvell_read_status,
1988 .ack_interrupt = &marvell_ack_interrupt,
1989 .config_intr = &marvell_config_intr,
1990 .did_interrupt = &m88e1121_did_interrupt,
1991 .get_wol = &m88e1318_get_wol,
1992 .set_wol = &m88e1318_set_wol,
1993 .resume = &genphy_resume,
1994 .suspend = &genphy_suspend,
1995 .get_sset_count = marvell_get_sset_count,
1996 .get_strings = marvell_get_strings,
1997 .get_stats = marvell_get_stats,
1998 },
1999 {
2000 .phy_id = MARVELL_PHY_ID_88E1145,
2001 .phy_id_mask = MARVELL_PHY_ID_MASK,
2002 .name = "Marvell 88E1145",
2003 .features = PHY_GBIT_FEATURES,
2004 .flags = PHY_HAS_INTERRUPT,
2005 .probe = marvell_probe,
2006 .config_init = &m88e1145_config_init,
2007 .config_aneg = &marvell_config_aneg,
2008 .read_status = &genphy_read_status,
2009 .ack_interrupt = &marvell_ack_interrupt,
2010 .config_intr = &marvell_config_intr,
2011 .resume = &genphy_resume,
2012 .suspend = &genphy_suspend,
2013 .get_sset_count = marvell_get_sset_count,
2014 .get_strings = marvell_get_strings,
2015 .get_stats = marvell_get_stats,
2016 },
2017 {
2018 .phy_id = MARVELL_PHY_ID_88E1149R,
2019 .phy_id_mask = MARVELL_PHY_ID_MASK,
2020 .name = "Marvell 88E1149R",
2021 .features = PHY_GBIT_FEATURES,
2022 .flags = PHY_HAS_INTERRUPT,
2023 .probe = marvell_probe,
2024 .config_init = &m88e1149_config_init,
2025 .config_aneg = &m88e1118_config_aneg,
2026 .read_status = &genphy_read_status,
2027 .ack_interrupt = &marvell_ack_interrupt,
2028 .config_intr = &marvell_config_intr,
2029 .resume = &genphy_resume,
2030 .suspend = &genphy_suspend,
2031 .get_sset_count = marvell_get_sset_count,
2032 .get_strings = marvell_get_strings,
2033 .get_stats = marvell_get_stats,
2034 },
2035 {
2036 .phy_id = MARVELL_PHY_ID_88E1240,
2037 .phy_id_mask = MARVELL_PHY_ID_MASK,
2038 .name = "Marvell 88E1240",
2039 .features = PHY_GBIT_FEATURES,
2040 .flags = PHY_HAS_INTERRUPT,
2041 .probe = marvell_probe,
2042 .config_init = &m88e1111_config_init,
2043 .config_aneg = &marvell_config_aneg,
2044 .read_status = &genphy_read_status,
2045 .ack_interrupt = &marvell_ack_interrupt,
2046 .config_intr = &marvell_config_intr,
2047 .resume = &genphy_resume,
2048 .suspend = &genphy_suspend,
2049 .get_sset_count = marvell_get_sset_count,
2050 .get_strings = marvell_get_strings,
2051 .get_stats = marvell_get_stats,
2052 },
2053 {
2054 .phy_id = MARVELL_PHY_ID_88E1116R,
2055 .phy_id_mask = MARVELL_PHY_ID_MASK,
2056 .name = "Marvell 88E1116R",
2057 .features = PHY_GBIT_FEATURES,
2058 .flags = PHY_HAS_INTERRUPT,
2059 .probe = marvell_probe,
2060 .config_init = &m88e1116r_config_init,
2061 .config_aneg = &genphy_config_aneg,
2062 .read_status = &genphy_read_status,
2063 .ack_interrupt = &marvell_ack_interrupt,
2064 .config_intr = &marvell_config_intr,
2065 .resume = &genphy_resume,
2066 .suspend = &genphy_suspend,
2067 .get_sset_count = marvell_get_sset_count,
2068 .get_strings = marvell_get_strings,
2069 .get_stats = marvell_get_stats,
2070 },
2071 {
2072 .phy_id = MARVELL_PHY_ID_88E1510,
2073 .phy_id_mask = MARVELL_PHY_ID_MASK,
2074 .name = "Marvell 88E1510",
2075 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
2076 .flags = PHY_HAS_INTERRUPT,
2077 .probe = &m88e1510_probe,
2078 .config_init = &m88e1510_config_init,
2079 .config_aneg = &m88e1510_config_aneg,
2080 .read_status = &marvell_read_status,
2081 .ack_interrupt = &marvell_ack_interrupt,
2082 .config_intr = &marvell_config_intr,
2083 .did_interrupt = &m88e1121_did_interrupt,
2084 .get_wol = &m88e1318_get_wol,
2085 .set_wol = &m88e1318_set_wol,
2086 .resume = &marvell_resume,
2087 .suspend = &marvell_suspend,
2088 .get_sset_count = marvell_get_sset_count,
2089 .get_strings = marvell_get_strings,
2090 .get_stats = marvell_get_stats,
2091 },
2092 {
2093 .phy_id = MARVELL_PHY_ID_88E1540,
2094 .phy_id_mask = MARVELL_PHY_ID_MASK,
2095 .name = "Marvell 88E1540",
2096 .features = PHY_GBIT_FEATURES,
2097 .flags = PHY_HAS_INTERRUPT,
2098 .probe = m88e1510_probe,
2099 .config_init = &marvell_config_init,
2100 .config_aneg = &m88e1510_config_aneg,
2101 .read_status = &marvell_read_status,
2102 .ack_interrupt = &marvell_ack_interrupt,
2103 .config_intr = &marvell_config_intr,
2104 .did_interrupt = &m88e1121_did_interrupt,
2105 .resume = &genphy_resume,
2106 .suspend = &genphy_suspend,
2107 .get_sset_count = marvell_get_sset_count,
2108 .get_strings = marvell_get_strings,
2109 .get_stats = marvell_get_stats,
2110 },
2111 {
2112 .phy_id = MARVELL_PHY_ID_88E1545,
2113 .phy_id_mask = MARVELL_PHY_ID_MASK,
2114 .name = "Marvell 88E1545",
2115 .probe = m88e1510_probe,
2116 .features = PHY_GBIT_FEATURES,
2117 .flags = PHY_HAS_INTERRUPT,
2118 .config_init = &marvell_config_init,
2119 .config_aneg = &m88e1510_config_aneg,
2120 .read_status = &marvell_read_status,
2121 .ack_interrupt = &marvell_ack_interrupt,
2122 .config_intr = &marvell_config_intr,
2123 .did_interrupt = &m88e1121_did_interrupt,
2124 .resume = &genphy_resume,
2125 .suspend = &genphy_suspend,
2126 .get_sset_count = marvell_get_sset_count,
2127 .get_strings = marvell_get_strings,
2128 .get_stats = marvell_get_stats,
2129 },
2130 {
2131 .phy_id = MARVELL_PHY_ID_88E3016,
2132 .phy_id_mask = MARVELL_PHY_ID_MASK,
2133 .name = "Marvell 88E3016",
2134 .features = PHY_BASIC_FEATURES,
2135 .flags = PHY_HAS_INTERRUPT,
2136 .probe = marvell_probe,
2137 .config_aneg = &genphy_config_aneg,
2138 .config_init = &m88e3016_config_init,
2139 .aneg_done = &marvell_aneg_done,
2140 .read_status = &marvell_read_status,
2141 .ack_interrupt = &marvell_ack_interrupt,
2142 .config_intr = &marvell_config_intr,
2143 .did_interrupt = &m88e1121_did_interrupt,
2144 .resume = &genphy_resume,
2145 .suspend = &genphy_suspend,
2146 .get_sset_count = marvell_get_sset_count,
2147 .get_strings = marvell_get_strings,
2148 .get_stats = marvell_get_stats,
2149 },
2150 {
2151 .phy_id = MARVELL_PHY_ID_88E6390,
2152 .phy_id_mask = MARVELL_PHY_ID_MASK,
2153 .name = "Marvell 88E6390",
2154 .features = PHY_GBIT_FEATURES,
2155 .flags = PHY_HAS_INTERRUPT,
2156 .probe = m88e1510_probe,
2157 .config_init = &marvell_config_init,
2158 .config_aneg = &m88e1510_config_aneg,
2159 .read_status = &marvell_read_status,
2160 .ack_interrupt = &marvell_ack_interrupt,
2161 .config_intr = &marvell_config_intr,
2162 .did_interrupt = &m88e1121_did_interrupt,
2163 .resume = &genphy_resume,
2164 .suspend = &genphy_suspend,
2165 .get_sset_count = marvell_get_sset_count,
2166 .get_strings = marvell_get_strings,
2167 .get_stats = marvell_get_stats,
2168 },
2169 };
2170
2171 module_phy_driver(marvell_drivers);
2172
2173 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
2174 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
2175 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
2176 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
2177 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
2178 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
2179 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
2180 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
2181 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
2182 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
2183 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
2184 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
2185 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
2186 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
2187 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
2188 { MARVELL_PHY_ID_88E6390, MARVELL_PHY_ID_MASK },
2189 { }
2190 };
2191
2192 MODULE_DEVICE_TABLE(mdio, marvell_tbl);
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