2 * drivers/net/phy/micrel.c
4 * Driver for Micrel PHYs
6 * Author: David J. Choi
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
22 * Switch : ksz8873, ksz886x
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/phy.h>
28 #include <linux/micrel_phy.h>
30 #include <linux/clk.h>
32 /* Operation Mode Strap Override */
33 #define MII_KSZPHY_OMSO 0x16
34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39 /* general Interrupt control/status reg in vendor specific block. */
40 #define MII_KSZPHY_INTCS 0x1B
41 #define KSZPHY_INTCS_JABBER BIT(15)
42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44 #define KSZPHY_INTCS_PARELLEL BIT(12)
45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48 #define KSZPHY_INTCS_LINK_UP BIT(8)
49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
53 #define MII_KSZPHY_CTRL_1 0x1e
55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
56 #define MII_KSZPHY_CTRL_2 0x1f
57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
58 /* bitmap of PHY register to set interrupt mode */
59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
62 /* Write/read to/from extended registers */
63 #define MII_KSZPHY_EXTREG 0x0b
64 #define KSZPHY_EXTREG_WRITE 0x8000
66 #define MII_KSZPHY_EXTREG_WRITE 0x0c
67 #define MII_KSZPHY_EXTREG_READ 0x0d
69 /* Extended registers */
70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
76 struct kszphy_hw_stat
{
82 static struct kszphy_hw_stat kszphy_hw_stats
[] = {
83 { "phy_receive_errors", 21, 16},
84 { "phy_idle_errors", 10, 8 },
89 u16 interrupt_level_mask
;
90 bool has_broadcast_disable
;
91 bool has_nand_tree_disable
;
92 bool has_rmii_ref_clk_sel
;
96 const struct kszphy_type
*type
;
98 bool rmii_ref_clk_sel
;
99 bool rmii_ref_clk_sel_val
;
100 u64 stats
[ARRAY_SIZE(kszphy_hw_stats
)];
103 static const struct kszphy_type ksz8021_type
= {
104 .led_mode_reg
= MII_KSZPHY_CTRL_2
,
105 .has_broadcast_disable
= true,
106 .has_nand_tree_disable
= true,
107 .has_rmii_ref_clk_sel
= true,
110 static const struct kszphy_type ksz8041_type
= {
111 .led_mode_reg
= MII_KSZPHY_CTRL_1
,
114 static const struct kszphy_type ksz8051_type
= {
115 .led_mode_reg
= MII_KSZPHY_CTRL_2
,
116 .has_nand_tree_disable
= true,
119 static const struct kszphy_type ksz8081_type
= {
120 .led_mode_reg
= MII_KSZPHY_CTRL_2
,
121 .has_broadcast_disable
= true,
122 .has_nand_tree_disable
= true,
123 .has_rmii_ref_clk_sel
= true,
126 static const struct kszphy_type ks8737_type
= {
127 .interrupt_level_mask
= BIT(14),
130 static const struct kszphy_type ksz9021_type
= {
131 .interrupt_level_mask
= BIT(14),
134 static int kszphy_extended_write(struct phy_device
*phydev
,
137 phy_write(phydev
, MII_KSZPHY_EXTREG
, KSZPHY_EXTREG_WRITE
| regnum
);
138 return phy_write(phydev
, MII_KSZPHY_EXTREG_WRITE
, val
);
141 static int kszphy_extended_read(struct phy_device
*phydev
,
144 phy_write(phydev
, MII_KSZPHY_EXTREG
, regnum
);
145 return phy_read(phydev
, MII_KSZPHY_EXTREG_READ
);
148 static int kszphy_ack_interrupt(struct phy_device
*phydev
)
150 /* bit[7..0] int status, which is a read and clear register. */
153 rc
= phy_read(phydev
, MII_KSZPHY_INTCS
);
155 return (rc
< 0) ? rc
: 0;
158 static int kszphy_config_intr(struct phy_device
*phydev
)
160 const struct kszphy_type
*type
= phydev
->drv
->driver_data
;
164 if (type
&& type
->interrupt_level_mask
)
165 mask
= type
->interrupt_level_mask
;
167 mask
= KSZPHY_CTRL_INT_ACTIVE_HIGH
;
169 /* set the interrupt pin active low */
170 temp
= phy_read(phydev
, MII_KSZPHY_CTRL
);
174 phy_write(phydev
, MII_KSZPHY_CTRL
, temp
);
176 /* enable / disable interrupts */
177 if (phydev
->interrupts
== PHY_INTERRUPT_ENABLED
)
178 temp
= KSZPHY_INTCS_ALL
;
182 return phy_write(phydev
, MII_KSZPHY_INTCS
, temp
);
185 static int kszphy_rmii_clk_sel(struct phy_device
*phydev
, bool val
)
189 ctrl
= phy_read(phydev
, MII_KSZPHY_CTRL
);
194 ctrl
|= KSZPHY_RMII_REF_CLK_SEL
;
196 ctrl
&= ~KSZPHY_RMII_REF_CLK_SEL
;
198 return phy_write(phydev
, MII_KSZPHY_CTRL
, ctrl
);
201 static int kszphy_setup_led(struct phy_device
*phydev
, u32 reg
, int val
)
206 case MII_KSZPHY_CTRL_1
:
209 case MII_KSZPHY_CTRL_2
:
216 temp
= phy_read(phydev
, reg
);
222 temp
&= ~(3 << shift
);
223 temp
|= val
<< shift
;
224 rc
= phy_write(phydev
, reg
, temp
);
227 dev_err(&phydev
->dev
, "failed to set led mode\n");
232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
233 * unique (non-broadcast) address on a shared bus.
235 static int kszphy_broadcast_disable(struct phy_device
*phydev
)
239 ret
= phy_read(phydev
, MII_KSZPHY_OMSO
);
243 ret
= phy_write(phydev
, MII_KSZPHY_OMSO
, ret
| KSZPHY_OMSO_B_CAST_OFF
);
246 dev_err(&phydev
->dev
, "failed to disable broadcast address\n");
251 static int kszphy_nand_tree_disable(struct phy_device
*phydev
)
255 ret
= phy_read(phydev
, MII_KSZPHY_OMSO
);
259 if (!(ret
& KSZPHY_OMSO_NAND_TREE_ON
))
262 ret
= phy_write(phydev
, MII_KSZPHY_OMSO
,
263 ret
& ~KSZPHY_OMSO_NAND_TREE_ON
);
266 dev_err(&phydev
->dev
, "failed to disable NAND tree mode\n");
271 static int kszphy_config_init(struct phy_device
*phydev
)
273 struct kszphy_priv
*priv
= phydev
->priv
;
274 const struct kszphy_type
*type
;
282 if (type
->has_broadcast_disable
)
283 kszphy_broadcast_disable(phydev
);
285 if (type
->has_nand_tree_disable
)
286 kszphy_nand_tree_disable(phydev
);
288 if (priv
->rmii_ref_clk_sel
) {
289 ret
= kszphy_rmii_clk_sel(phydev
, priv
->rmii_ref_clk_sel_val
);
291 dev_err(&phydev
->dev
, "failed to set rmii reference clock\n");
296 if (priv
->led_mode
>= 0)
297 kszphy_setup_led(phydev
, type
->led_mode_reg
, priv
->led_mode
);
302 static int ksz9021_load_values_from_of(struct phy_device
*phydev
,
303 const struct device_node
*of_node
,
305 const char *field1
, const char *field2
,
306 const char *field3
, const char *field4
)
315 if (!of_property_read_u32(of_node
, field1
, &val1
))
318 if (!of_property_read_u32(of_node
, field2
, &val2
))
321 if (!of_property_read_u32(of_node
, field3
, &val3
))
324 if (!of_property_read_u32(of_node
, field4
, &val4
))
331 newval
= kszphy_extended_read(phydev
, reg
);
336 newval
= ((newval
& 0xfff0) | ((val1
/ PS_TO_REG
) & 0xf) << 0);
339 newval
= ((newval
& 0xff0f) | ((val2
/ PS_TO_REG
) & 0xf) << 4);
342 newval
= ((newval
& 0xf0ff) | ((val3
/ PS_TO_REG
) & 0xf) << 8);
345 newval
= ((newval
& 0x0fff) | ((val4
/ PS_TO_REG
) & 0xf) << 12);
347 return kszphy_extended_write(phydev
, reg
, newval
);
350 static int ksz9021_config_init(struct phy_device
*phydev
)
352 const struct device
*dev
= &phydev
->dev
;
353 const struct device_node
*of_node
= dev
->of_node
;
354 const struct device
*dev_walker
;
356 /* The Micrel driver has a deprecated option to place phy OF
357 * properties in the MAC node. Walk up the tree of devices to
358 * find a device with an OF node.
360 dev_walker
= &phydev
->dev
;
362 of_node
= dev_walker
->of_node
;
363 dev_walker
= dev_walker
->parent
;
365 } while (!of_node
&& dev_walker
);
368 ksz9021_load_values_from_of(phydev
, of_node
,
369 MII_KSZPHY_CLK_CONTROL_PAD_SKEW
,
370 "txen-skew-ps", "txc-skew-ps",
371 "rxdv-skew-ps", "rxc-skew-ps");
372 ksz9021_load_values_from_of(phydev
, of_node
,
373 MII_KSZPHY_RX_DATA_PAD_SKEW
,
374 "rxd0-skew-ps", "rxd1-skew-ps",
375 "rxd2-skew-ps", "rxd3-skew-ps");
376 ksz9021_load_values_from_of(phydev
, of_node
,
377 MII_KSZPHY_TX_DATA_PAD_SKEW
,
378 "txd0-skew-ps", "txd1-skew-ps",
379 "txd2-skew-ps", "txd3-skew-ps");
384 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
385 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
387 #define KSZ9031_PS_TO_REG 60
389 /* Extended registers */
390 /* MMD Address 0x0 */
391 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
392 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
394 /* MMD Address 0x2 */
395 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
396 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
397 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
398 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
400 static int ksz9031_extended_write(struct phy_device
*phydev
,
401 u8 mode
, u32 dev_addr
, u32 regnum
, u16 val
)
403 phy_write(phydev
, MII_KSZ9031RN_MMD_CTRL_REG
, dev_addr
);
404 phy_write(phydev
, MII_KSZ9031RN_MMD_REGDATA_REG
, regnum
);
405 phy_write(phydev
, MII_KSZ9031RN_MMD_CTRL_REG
, (mode
<< 14) | dev_addr
);
406 return phy_write(phydev
, MII_KSZ9031RN_MMD_REGDATA_REG
, val
);
409 static int ksz9031_extended_read(struct phy_device
*phydev
,
410 u8 mode
, u32 dev_addr
, u32 regnum
)
412 phy_write(phydev
, MII_KSZ9031RN_MMD_CTRL_REG
, dev_addr
);
413 phy_write(phydev
, MII_KSZ9031RN_MMD_REGDATA_REG
, regnum
);
414 phy_write(phydev
, MII_KSZ9031RN_MMD_CTRL_REG
, (mode
<< 14) | dev_addr
);
415 return phy_read(phydev
, MII_KSZ9031RN_MMD_REGDATA_REG
);
418 static int ksz9031_of_load_skew_values(struct phy_device
*phydev
,
419 const struct device_node
*of_node
,
420 u16 reg
, size_t field_sz
,
421 const char *field
[], u8 numfields
)
423 int val
[4] = {-1, -2, -3, -4};
430 for (i
= 0; i
< numfields
; i
++)
431 if (!of_property_read_u32(of_node
, field
[i
], val
+ i
))
437 if (matches
< numfields
)
438 newval
= ksz9031_extended_read(phydev
, OP_DATA
, 2, reg
);
442 maxval
= (field_sz
== 4) ? 0xf : 0x1f;
443 for (i
= 0; i
< numfields
; i
++)
444 if (val
[i
] != -(i
+ 1)) {
446 mask
^= maxval
<< (field_sz
* i
);
447 newval
= (newval
& mask
) |
448 (((val
[i
] / KSZ9031_PS_TO_REG
) & maxval
)
452 return ksz9031_extended_write(phydev
, OP_DATA
, 2, reg
, newval
);
455 static int ksz9031_center_flp_timing(struct phy_device
*phydev
)
459 /* Center KSZ9031RNX FLP timing at 16ms. */
460 result
= ksz9031_extended_write(phydev
, OP_DATA
, 0,
461 MII_KSZ9031RN_FLP_BURST_TX_HI
, 0x0006);
462 result
= ksz9031_extended_write(phydev
, OP_DATA
, 0,
463 MII_KSZ9031RN_FLP_BURST_TX_LO
, 0x1A80);
468 return genphy_restart_aneg(phydev
);
471 static int ksz9031_config_init(struct phy_device
*phydev
)
473 const struct device
*dev
= &phydev
->dev
;
474 const struct device_node
*of_node
= dev
->of_node
;
475 static const char *clk_skews
[2] = {"rxc-skew-ps", "txc-skew-ps"};
476 static const char *rx_data_skews
[4] = {
477 "rxd0-skew-ps", "rxd1-skew-ps",
478 "rxd2-skew-ps", "rxd3-skew-ps"
480 static const char *tx_data_skews
[4] = {
481 "txd0-skew-ps", "txd1-skew-ps",
482 "txd2-skew-ps", "txd3-skew-ps"
484 static const char *control_skews
[2] = {"txen-skew-ps", "rxdv-skew-ps"};
486 if (!of_node
&& dev
->parent
->of_node
)
487 of_node
= dev
->parent
->of_node
;
490 ksz9031_of_load_skew_values(phydev
, of_node
,
491 MII_KSZ9031RN_CLK_PAD_SKEW
, 5,
494 ksz9031_of_load_skew_values(phydev
, of_node
,
495 MII_KSZ9031RN_CONTROL_PAD_SKEW
, 4,
498 ksz9031_of_load_skew_values(phydev
, of_node
,
499 MII_KSZ9031RN_RX_DATA_PAD_SKEW
, 4,
502 ksz9031_of_load_skew_values(phydev
, of_node
,
503 MII_KSZ9031RN_TX_DATA_PAD_SKEW
, 4,
507 return ksz9031_center_flp_timing(phydev
);
510 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
511 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
512 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
513 static int ksz8873mll_read_status(struct phy_device
*phydev
)
518 regval
= phy_read(phydev
, KSZ8873MLL_GLOBAL_CONTROL_4
);
520 regval
= phy_read(phydev
, KSZ8873MLL_GLOBAL_CONTROL_4
);
522 if (regval
& KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX
)
523 phydev
->duplex
= DUPLEX_HALF
;
525 phydev
->duplex
= DUPLEX_FULL
;
527 if (regval
& KSZ8873MLL_GLOBAL_CONTROL_4_SPEED
)
528 phydev
->speed
= SPEED_10
;
530 phydev
->speed
= SPEED_100
;
533 phydev
->pause
= phydev
->asym_pause
= 0;
538 static int ksz9031_read_status(struct phy_device
*phydev
)
543 err
= genphy_read_status(phydev
);
547 /* Make sure the PHY is not broken. Read idle error count,
548 * and reset the PHY if it is maxed out.
550 regval
= phy_read(phydev
, MII_STAT1000
);
551 if ((regval
& 0xFF) == 0xFF) {
559 static int ksz8873mll_config_aneg(struct phy_device
*phydev
)
564 /* This routine returns -1 as an indication to the caller that the
565 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
566 * MMD extended PHY registers.
569 ksz9021_rd_mmd_phyreg(struct phy_device
*phydev
, int ptrad
, int devnum
,
575 /* This routine does nothing since the Micrel ksz9021 does not support
576 * standard IEEE MMD extended PHY registers.
579 ksz9021_wr_mmd_phyreg(struct phy_device
*phydev
, int ptrad
, int devnum
,
584 static int kszphy_get_sset_count(struct phy_device
*phydev
)
586 return ARRAY_SIZE(kszphy_hw_stats
);
589 static void kszphy_get_strings(struct phy_device
*phydev
, u8
*data
)
593 for (i
= 0; i
< ARRAY_SIZE(kszphy_hw_stats
); i
++) {
594 memcpy(data
+ i
* ETH_GSTRING_LEN
,
595 kszphy_hw_stats
[i
].string
, ETH_GSTRING_LEN
);
600 #define UINT64_MAX (u64)(~((u64)0))
602 static u64
kszphy_get_stat(struct phy_device
*phydev
, int i
)
604 struct kszphy_hw_stat stat
= kszphy_hw_stats
[i
];
605 struct kszphy_priv
*priv
= phydev
->priv
;
608 val
= phy_read(phydev
, stat
.reg
);
612 val
= val
& ((1 << stat
.bits
) - 1);
613 priv
->stats
[i
] += val
;
614 val
= priv
->stats
[i
];
620 static void kszphy_get_stats(struct phy_device
*phydev
,
621 struct ethtool_stats
*stats
, u64
*data
)
625 for (i
= 0; i
< ARRAY_SIZE(kszphy_hw_stats
); i
++)
626 data
[i
] = kszphy_get_stat(phydev
, i
);
629 static int kszphy_probe(struct phy_device
*phydev
)
631 const struct kszphy_type
*type
= phydev
->drv
->driver_data
;
632 const struct device_node
*np
= phydev
->dev
.of_node
;
633 struct kszphy_priv
*priv
;
637 priv
= devm_kzalloc(&phydev
->dev
, sizeof(*priv
), GFP_KERNEL
);
645 if (type
->led_mode_reg
) {
646 ret
= of_property_read_u32(np
, "micrel,led-mode",
651 if (priv
->led_mode
> 3) {
652 dev_err(&phydev
->dev
, "invalid led mode: 0x%02x\n",
660 clk
= devm_clk_get(&phydev
->dev
, "rmii-ref");
661 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
662 if (!IS_ERR_OR_NULL(clk
)) {
663 unsigned long rate
= clk_get_rate(clk
);
664 bool rmii_ref_clk_sel_25_mhz
;
666 priv
->rmii_ref_clk_sel
= type
->has_rmii_ref_clk_sel
;
667 rmii_ref_clk_sel_25_mhz
= of_property_read_bool(np
,
668 "micrel,rmii-reference-clock-select-25-mhz");
670 if (rate
> 24500000 && rate
< 25500000) {
671 priv
->rmii_ref_clk_sel_val
= rmii_ref_clk_sel_25_mhz
;
672 } else if (rate
> 49500000 && rate
< 50500000) {
673 priv
->rmii_ref_clk_sel_val
= !rmii_ref_clk_sel_25_mhz
;
675 dev_err(&phydev
->dev
, "Clock rate out of range: %ld\n", rate
);
680 /* Support legacy board-file configuration */
681 if (phydev
->dev_flags
& MICREL_PHY_50MHZ_CLK
) {
682 priv
->rmii_ref_clk_sel
= true;
683 priv
->rmii_ref_clk_sel_val
= true;
689 static struct phy_driver ksphy_driver
[] = {
691 .phy_id
= PHY_ID_KS8737
,
692 .phy_id_mask
= 0x00fffff0,
693 .name
= "Micrel KS8737",
694 .features
= (PHY_BASIC_FEATURES
| SUPPORTED_Pause
),
695 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
696 .driver_data
= &ks8737_type
,
697 .config_init
= kszphy_config_init
,
698 .config_aneg
= genphy_config_aneg
,
699 .read_status
= genphy_read_status
,
700 .ack_interrupt
= kszphy_ack_interrupt
,
701 .config_intr
= kszphy_config_intr
,
702 .get_sset_count
= kszphy_get_sset_count
,
703 .get_strings
= kszphy_get_strings
,
704 .get_stats
= kszphy_get_stats
,
705 .suspend
= genphy_suspend
,
706 .resume
= genphy_resume
,
707 .driver
= { .owner
= THIS_MODULE
,},
709 .phy_id
= PHY_ID_KSZ8021
,
710 .phy_id_mask
= 0x00ffffff,
711 .name
= "Micrel KSZ8021 or KSZ8031",
712 .features
= (PHY_BASIC_FEATURES
| SUPPORTED_Pause
|
713 SUPPORTED_Asym_Pause
),
714 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
715 .driver_data
= &ksz8021_type
,
716 .probe
= kszphy_probe
,
717 .config_init
= kszphy_config_init
,
718 .config_aneg
= genphy_config_aneg
,
719 .read_status
= genphy_read_status
,
720 .ack_interrupt
= kszphy_ack_interrupt
,
721 .config_intr
= kszphy_config_intr
,
722 .get_sset_count
= kszphy_get_sset_count
,
723 .get_strings
= kszphy_get_strings
,
724 .get_stats
= kszphy_get_stats
,
725 .suspend
= genphy_suspend
,
726 .resume
= genphy_resume
,
727 .driver
= { .owner
= THIS_MODULE
,},
729 .phy_id
= PHY_ID_KSZ8031
,
730 .phy_id_mask
= 0x00ffffff,
731 .name
= "Micrel KSZ8031",
732 .features
= (PHY_BASIC_FEATURES
| SUPPORTED_Pause
|
733 SUPPORTED_Asym_Pause
),
734 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
735 .driver_data
= &ksz8021_type
,
736 .probe
= kszphy_probe
,
737 .config_init
= kszphy_config_init
,
738 .config_aneg
= genphy_config_aneg
,
739 .read_status
= genphy_read_status
,
740 .ack_interrupt
= kszphy_ack_interrupt
,
741 .config_intr
= kszphy_config_intr
,
742 .get_sset_count
= kszphy_get_sset_count
,
743 .get_strings
= kszphy_get_strings
,
744 .get_stats
= kszphy_get_stats
,
745 .suspend
= genphy_suspend
,
746 .resume
= genphy_resume
,
747 .driver
= { .owner
= THIS_MODULE
,},
749 .phy_id
= PHY_ID_KSZ8041
,
750 .phy_id_mask
= 0x00fffff0,
751 .name
= "Micrel KSZ8041",
752 .features
= (PHY_BASIC_FEATURES
| SUPPORTED_Pause
753 | SUPPORTED_Asym_Pause
),
754 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
755 .driver_data
= &ksz8041_type
,
756 .probe
= kszphy_probe
,
757 .config_init
= kszphy_config_init
,
758 .config_aneg
= genphy_config_aneg
,
759 .read_status
= genphy_read_status
,
760 .ack_interrupt
= kszphy_ack_interrupt
,
761 .config_intr
= kszphy_config_intr
,
762 .get_sset_count
= kszphy_get_sset_count
,
763 .get_strings
= kszphy_get_strings
,
764 .get_stats
= kszphy_get_stats
,
765 .suspend
= genphy_suspend
,
766 .resume
= genphy_resume
,
767 .driver
= { .owner
= THIS_MODULE
,},
769 .phy_id
= PHY_ID_KSZ8041RNLI
,
770 .phy_id_mask
= 0x00fffff0,
771 .name
= "Micrel KSZ8041RNLI",
772 .features
= PHY_BASIC_FEATURES
|
773 SUPPORTED_Pause
| SUPPORTED_Asym_Pause
,
774 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
775 .driver_data
= &ksz8041_type
,
776 .probe
= kszphy_probe
,
777 .config_init
= kszphy_config_init
,
778 .config_aneg
= genphy_config_aneg
,
779 .read_status
= genphy_read_status
,
780 .ack_interrupt
= kszphy_ack_interrupt
,
781 .config_intr
= kszphy_config_intr
,
782 .get_sset_count
= kszphy_get_sset_count
,
783 .get_strings
= kszphy_get_strings
,
784 .get_stats
= kszphy_get_stats
,
785 .suspend
= genphy_suspend
,
786 .resume
= genphy_resume
,
787 .driver
= { .owner
= THIS_MODULE
,},
789 .phy_id
= PHY_ID_KSZ8051
,
790 .phy_id_mask
= 0x00fffff0,
791 .name
= "Micrel KSZ8051",
792 .features
= (PHY_BASIC_FEATURES
| SUPPORTED_Pause
793 | SUPPORTED_Asym_Pause
),
794 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
795 .driver_data
= &ksz8051_type
,
796 .probe
= kszphy_probe
,
797 .config_init
= kszphy_config_init
,
798 .config_aneg
= genphy_config_aneg
,
799 .read_status
= genphy_read_status
,
800 .ack_interrupt
= kszphy_ack_interrupt
,
801 .config_intr
= kszphy_config_intr
,
802 .get_sset_count
= kszphy_get_sset_count
,
803 .get_strings
= kszphy_get_strings
,
804 .get_stats
= kszphy_get_stats
,
805 .suspend
= genphy_suspend
,
806 .resume
= genphy_resume
,
807 .driver
= { .owner
= THIS_MODULE
,},
809 .phy_id
= PHY_ID_KSZ8001
,
810 .name
= "Micrel KSZ8001 or KS8721",
811 .phy_id_mask
= 0x00ffffff,
812 .features
= (PHY_BASIC_FEATURES
| SUPPORTED_Pause
),
813 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
814 .driver_data
= &ksz8041_type
,
815 .probe
= kszphy_probe
,
816 .config_init
= kszphy_config_init
,
817 .config_aneg
= genphy_config_aneg
,
818 .read_status
= genphy_read_status
,
819 .ack_interrupt
= kszphy_ack_interrupt
,
820 .config_intr
= kszphy_config_intr
,
821 .get_sset_count
= kszphy_get_sset_count
,
822 .get_strings
= kszphy_get_strings
,
823 .get_stats
= kszphy_get_stats
,
824 .suspend
= genphy_suspend
,
825 .resume
= genphy_resume
,
826 .driver
= { .owner
= THIS_MODULE
,},
828 .phy_id
= PHY_ID_KSZ8081
,
829 .name
= "Micrel KSZ8081 or KSZ8091",
830 .phy_id_mask
= 0x00fffff0,
831 .features
= (PHY_BASIC_FEATURES
| SUPPORTED_Pause
),
832 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
833 .driver_data
= &ksz8081_type
,
834 .probe
= kszphy_probe
,
835 .config_init
= kszphy_config_init
,
836 .config_aneg
= genphy_config_aneg
,
837 .read_status
= genphy_read_status
,
838 .ack_interrupt
= kszphy_ack_interrupt
,
839 .config_intr
= kszphy_config_intr
,
840 .get_sset_count
= kszphy_get_sset_count
,
841 .get_strings
= kszphy_get_strings
,
842 .get_stats
= kszphy_get_stats
,
843 .suspend
= genphy_suspend
,
844 .resume
= genphy_resume
,
845 .driver
= { .owner
= THIS_MODULE
,},
847 .phy_id
= PHY_ID_KSZ8061
,
848 .name
= "Micrel KSZ8061",
849 .phy_id_mask
= 0x00fffff0,
850 .features
= (PHY_BASIC_FEATURES
| SUPPORTED_Pause
),
851 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
852 .config_init
= kszphy_config_init
,
853 .config_aneg
= genphy_config_aneg
,
854 .read_status
= genphy_read_status
,
855 .ack_interrupt
= kszphy_ack_interrupt
,
856 .config_intr
= kszphy_config_intr
,
857 .get_sset_count
= kszphy_get_sset_count
,
858 .get_strings
= kszphy_get_strings
,
859 .get_stats
= kszphy_get_stats
,
860 .suspend
= genphy_suspend
,
861 .resume
= genphy_resume
,
862 .driver
= { .owner
= THIS_MODULE
,},
864 .phy_id
= PHY_ID_KSZ9021
,
865 .phy_id_mask
= 0x000ffffe,
866 .name
= "Micrel KSZ9021 Gigabit PHY",
867 .features
= (PHY_GBIT_FEATURES
| SUPPORTED_Pause
),
868 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
869 .driver_data
= &ksz9021_type
,
870 .config_init
= ksz9021_config_init
,
871 .config_aneg
= genphy_config_aneg
,
872 .read_status
= genphy_read_status
,
873 .ack_interrupt
= kszphy_ack_interrupt
,
874 .config_intr
= kszphy_config_intr
,
875 .get_sset_count
= kszphy_get_sset_count
,
876 .get_strings
= kszphy_get_strings
,
877 .get_stats
= kszphy_get_stats
,
878 .suspend
= genphy_suspend
,
879 .resume
= genphy_resume
,
880 .read_mmd_indirect
= ksz9021_rd_mmd_phyreg
,
881 .write_mmd_indirect
= ksz9021_wr_mmd_phyreg
,
882 .driver
= { .owner
= THIS_MODULE
, },
884 .phy_id
= PHY_ID_KSZ9031
,
885 .phy_id_mask
= 0x00fffff0,
886 .name
= "Micrel KSZ9031 Gigabit PHY",
887 .features
= (PHY_GBIT_FEATURES
| SUPPORTED_Pause
),
888 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
889 .driver_data
= &ksz9021_type
,
890 .config_init
= ksz9031_config_init
,
891 .config_aneg
= genphy_config_aneg
,
892 .read_status
= ksz9031_read_status
,
893 .ack_interrupt
= kszphy_ack_interrupt
,
894 .config_intr
= kszphy_config_intr
,
895 .get_sset_count
= kszphy_get_sset_count
,
896 .get_strings
= kszphy_get_strings
,
897 .get_stats
= kszphy_get_stats
,
898 .suspend
= genphy_suspend
,
899 .resume
= genphy_resume
,
900 .driver
= { .owner
= THIS_MODULE
, },
902 .phy_id
= PHY_ID_KSZ8873MLL
,
903 .phy_id_mask
= 0x00fffff0,
904 .name
= "Micrel KSZ8873MLL Switch",
905 .features
= (SUPPORTED_Pause
| SUPPORTED_Asym_Pause
),
906 .flags
= PHY_HAS_MAGICANEG
,
907 .config_init
= kszphy_config_init
,
908 .config_aneg
= ksz8873mll_config_aneg
,
909 .read_status
= ksz8873mll_read_status
,
910 .get_sset_count
= kszphy_get_sset_count
,
911 .get_strings
= kszphy_get_strings
,
912 .get_stats
= kszphy_get_stats
,
913 .suspend
= genphy_suspend
,
914 .resume
= genphy_resume
,
915 .driver
= { .owner
= THIS_MODULE
, },
917 .phy_id
= PHY_ID_KSZ886X
,
918 .phy_id_mask
= 0x00fffff0,
919 .name
= "Micrel KSZ886X Switch",
920 .features
= (PHY_BASIC_FEATURES
| SUPPORTED_Pause
),
921 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
922 .config_init
= kszphy_config_init
,
923 .config_aneg
= genphy_config_aneg
,
924 .read_status
= genphy_read_status
,
925 .get_sset_count
= kszphy_get_sset_count
,
926 .get_strings
= kszphy_get_strings
,
927 .get_stats
= kszphy_get_stats
,
928 .suspend
= genphy_suspend
,
929 .resume
= genphy_resume
,
930 .driver
= { .owner
= THIS_MODULE
, },
933 module_phy_driver(ksphy_driver
);
935 MODULE_DESCRIPTION("Micrel PHY driver");
936 MODULE_AUTHOR("David J. Choi");
937 MODULE_LICENSE("GPL");
939 static struct mdio_device_id __maybe_unused micrel_tbl
[] = {
940 { PHY_ID_KSZ9021
, 0x000ffffe },
941 { PHY_ID_KSZ9031
, 0x00fffff0 },
942 { PHY_ID_KSZ8001
, 0x00ffffff },
943 { PHY_ID_KS8737
, 0x00fffff0 },
944 { PHY_ID_KSZ8021
, 0x00ffffff },
945 { PHY_ID_KSZ8031
, 0x00ffffff },
946 { PHY_ID_KSZ8041
, 0x00fffff0 },
947 { PHY_ID_KSZ8051
, 0x00fffff0 },
948 { PHY_ID_KSZ8061
, 0x00fffff0 },
949 { PHY_ID_KSZ8081
, 0x00fffff0 },
950 { PHY_ID_KSZ8873MLL
, 0x00fffff0 },
951 { PHY_ID_KSZ886X
, 0x00fffff0 },
955 MODULE_DEVICE_TABLE(mdio
, micrel_tbl
);