drivers/net/phy/phy-c45.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Clause 45 PHY support
   4  */
   5 #include <linux/ethtool.h>
   6 #include <linux/export.h>
   7 #include <linux/mdio.h>
   8 #include <linux/mii.h>
   9 #include <linux/phy.h>
  10
  11 /**
  12  * genphy_c45_setup_forced - configures a forced speed
  13  * @phydev: target phy_device struct
  14  */
  15 int genphy_c45_pma_setup_forced(struct phy_device *phydev)
  16 {
  17         int ctrl1, ctrl2, ret;
  18
  19         /* Half duplex is not supported */
  20         if (phydev->duplex != DUPLEX_FULL)
  21                 return -EINVAL;
  22
  23         ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
  24         if (ctrl1 < 0)
  25                 return ctrl1;
  26
  27         ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
  28         if (ctrl2 < 0)
  29                 return ctrl2;
  30
  31         ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
  32         /*
  33          * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0.  See 45.2.1.6.1
  34          * in 802.3-2012 and 802.3-2015.
  35          */
  36         ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
  37
  38         switch (phydev->speed) {
  39         case SPEED_10:
  40                 ctrl2 |= MDIO_PMA_CTRL2_10BT;
  41                 break;
  42         case SPEED_100:
  43                 ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
  44                 ctrl2 |= MDIO_PMA_CTRL2_100BTX;
  45                 break;
  46         case SPEED_1000:
  47                 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
  48                 /* Assume 1000base-T */
  49                 ctrl2 |= MDIO_PMA_CTRL2_1000BT;
  50                 break;
  51         case SPEED_2500:
  52                 ctrl1 |= MDIO_CTRL1_SPEED2_5G;
  53                 /* Assume 2.5Gbase-T */
  54                 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
  55                 break;
  56         case SPEED_5000:
  57                 ctrl1 |= MDIO_CTRL1_SPEED5G;
  58                 /* Assume 5Gbase-T */
  59                 ctrl2 |= MDIO_PMA_CTRL2_5GBT;
  60                 break;
  61         case SPEED_10000:
  62                 ctrl1 |= MDIO_CTRL1_SPEED10G;
  63                 /* Assume 10Gbase-T */
  64                 ctrl2 |= MDIO_PMA_CTRL2_10GBT;
  65                 break;
  66         default:
  67                 return -EINVAL;
  68         }
  69
  70         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
  71         if (ret < 0)
  72                 return ret;
  73
  74         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
  75         if (ret < 0)
  76                 return ret;
  77
  78         return genphy_c45_an_disable_aneg(phydev);
  79 }
  80 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
  81
  82 /**
  83  * genphy_c45_an_config_aneg - configure advertisement registers
  84  * @phydev: target phy_device struct
  85  *
  86  * Configure advertisement registers based on modes set in phydev->advertising
  87  *
  88  * Returns negative errno code on failure, 0 if advertisement didn't change,
  89  * or 1 if advertised modes changed.
  90  */
  91 int genphy_c45_an_config_aneg(struct phy_device *phydev)
  92 {
  93         int changed, ret;
  94         u32 adv;
  95
  96         linkmode_and(phydev->advertising, phydev->advertising,
  97                      phydev->supported);
  98
  99         changed = genphy_config_eee_advert(phydev);
 100
 101         adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
 102
 103         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
 104                                      ADVERTISE_ALL | ADVERTISE_100BASE4 |
 105                                      ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
 106                                      adv);
 107         if (ret < 0)
 108                 return ret;
 109         if (ret > 0)
 110                 changed = 1;
 111
 112         adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
 113
 114         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
 115                                      MDIO_AN_10GBT_CTRL_ADV10G |
 116                                      MDIO_AN_10GBT_CTRL_ADV5G |
 117                                      MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
 118         if (ret < 0)
 119                 return ret;
 120         if (ret > 0)
 121                 changed = 1;
 122
 123         return changed;
 124 }
 125 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
 126
 127 /**
 128  * genphy_c45_an_disable_aneg - disable auto-negotiation
 129  * @phydev: target phy_device struct
 130  *
 131  * Disable auto-negotiation in the Clause 45 PHY. The link parameters
 132  * parameters are controlled through the PMA/PMD MMD registers.
 133  *
 134  * Returns zero on success, negative errno code on failure.
 135  */
 136 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
 137 {
 138
 139         return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
 140                                   MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 141 }
 142 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
 143
 144 /**
 145  * genphy_c45_restart_aneg - Enable and restart auto-negotiation
 146  * @phydev: target phy_device struct
 147  *
 148  * This assumes that the auto-negotiation MMD is present.
 149  *
 150  * Enable and restart auto-negotiation.
 151  */
 152 int genphy_c45_restart_aneg(struct phy_device *phydev)
 153 {
 154         return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
 155                                 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 156 }
 157 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
 158
 159 /**
 160  * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
 161  * @phydev: target phy_device struct
 162  * @restart: whether aneg restart is requested
 163  *
 164  * This assumes that the auto-negotiation MMD is present.
 165  *
 166  * Check, and restart auto-negotiation if needed.
 167  */
 168 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
 169 {
 170         int ret = 0;
 171
 172         if (!restart) {
 173                 /* Configure and restart aneg if it wasn't set before */
 174                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
 175                 if (ret < 0)
 176                         return ret;
 177
 178                 if (!(ret & MDIO_AN_CTRL1_ENABLE))
 179                         restart = true;
 180         }
 181
 182         if (restart)
 183                 ret = genphy_c45_restart_aneg(phydev);
 184
 185         return ret;
 186 }
 187 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
 188
 189 /**
 190  * genphy_c45_aneg_done - return auto-negotiation complete status
 191  * @phydev: target phy_device struct
 192  *
 193  * This assumes that the auto-negotiation MMD is present.
 194  *
 195  * Reads the status register from the auto-negotiation MMD, returning:
 196  * - positive if auto-negotiation is complete
 197  * - negative errno code on error
 198  * - zero otherwise
 199  */
 200 int genphy_c45_aneg_done(struct phy_device *phydev)
 201 {
 202         int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 203
 204         return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
 205 }
 206 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
 207
 208 /**
 209  * genphy_c45_read_link - read the overall link status from the MMDs
 210  * @phydev: target phy_device struct
 211  *
 212  * Read the link status from the specified MMDs, and if they all indicate
 213  * that the link is up, set phydev->link to 1.  If an error is encountered,
 214  * a negative errno will be returned, otherwise zero.
 215  */
 216 int genphy_c45_read_link(struct phy_device *phydev)
 217 {
 218         u32 mmd_mask = MDIO_DEVS_PMAPMD;
 219         int val, devad;
 220         bool link = true;
 221
 222         while (mmd_mask && link) {
 223                 devad = __ffs(mmd_mask);
 224                 mmd_mask &= ~BIT(devad);
 225
 226                 /* The link state is latched low so that momentary link
 227                  * drops can be detected. Do not double-read the status
 228                  * in polling mode to detect such short link drops.
 229                  */
 230                 if (!phy_polling_mode(phydev)) {
 231                         val = phy_read_mmd(phydev, devad, MDIO_STAT1);
 232                         if (val < 0)
 233                                 return val;
 234                         else if (val & MDIO_STAT1_LSTATUS)
 235                                 continue;
 236                 }
 237
 238                 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
 239                 if (val < 0)
 240                         return val;
 241
 242                 if (!(val & MDIO_STAT1_LSTATUS))
 243                         link = false;
 244         }
 245
 246         phydev->link = link;
 247
 248         return 0;
 249 }
 250 EXPORT_SYMBOL_GPL(genphy_c45_read_link);
 251
 252 /**
 253  * genphy_c45_read_lpa - read the link partner advertisement and pause
 254  * @phydev: target phy_device struct
 255  *
 256  * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
 257  * filling in the link partner advertisement, pause and asym_pause members
 258  * in @phydev.  This assumes that the auto-negotiation MMD is present, and
 259  * the backplane bit (7.48.0) is clear.  Clause 45 PHY drivers are expected
 260  * to fill in the remainder of the link partner advert from vendor registers.
 261  */
 262 int genphy_c45_read_lpa(struct phy_device *phydev)
 263 {
 264         int val;
 265
 266         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 267         if (val < 0)
 268                 return val;
 269
 270         if (!(val & MDIO_AN_STAT1_COMPLETE)) {
 271                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 272                                    phydev->lp_advertising);
 273                 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
 274                 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
 275                 phydev->pause = 0;
 276                 phydev->asym_pause = 0;
 277
 278                 return 0;
 279         }
 280
 281         linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
 282                          val & MDIO_AN_STAT1_LPABLE);
 283
 284         /* Read the link partner's base page advertisement */
 285         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
 286         if (val < 0)
 287                 return val;
 288
 289         mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
 290         phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
 291         phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
 292
 293         /* Read the link partner's 10G advertisement */
 294         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
 295         if (val < 0)
 296                 return val;
 297
 298         mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
 299
 300         return 0;
 301 }
 302 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
 303
 304 /**
 305  * genphy_c45_read_pma - read link speed etc from PMA
 306  * @phydev: target phy_device struct
 307  */
 308 int genphy_c45_read_pma(struct phy_device *phydev)
 309 {
 310         int val;
 311
 312         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
 313         if (val < 0)
 314                 return val;
 315
 316         switch (val & MDIO_CTRL1_SPEEDSEL) {
 317         case 0:
 318                 phydev->speed = SPEED_10;
 319                 break;
 320         case MDIO_PMA_CTRL1_SPEED100:
 321                 phydev->speed = SPEED_100;
 322                 break;
 323         case MDIO_PMA_CTRL1_SPEED1000:
 324                 phydev->speed = SPEED_1000;
 325                 break;
 326         case MDIO_CTRL1_SPEED2_5G:
 327                 phydev->speed = SPEED_2500;
 328                 break;
 329         case MDIO_CTRL1_SPEED5G:
 330                 phydev->speed = SPEED_5000;
 331                 break;
 332         case MDIO_CTRL1_SPEED10G:
 333                 phydev->speed = SPEED_10000;
 334                 break;
 335         default:
 336                 phydev->speed = SPEED_UNKNOWN;
 337                 break;
 338         }
 339
 340         phydev->duplex = DUPLEX_FULL;
 341
 342         return 0;
 343 }
 344 EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
 345
 346 /**
 347  * genphy_c45_read_mdix - read mdix status from PMA
 348  * @phydev: target phy_device struct
 349  */
 350 int genphy_c45_read_mdix(struct phy_device *phydev)
 351 {
 352         int val;
 353
 354         if (phydev->speed == SPEED_10000) {
 355                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
 356                                    MDIO_PMA_10GBT_SWAPPOL);
 357                 if (val < 0)
 358                         return val;
 359
 360                 switch (val) {
 361                 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
 362                         phydev->mdix = ETH_TP_MDI;
 363                         break;
 364
 365                 case 0:
 366                         phydev->mdix = ETH_TP_MDI_X;
 367                         break;
 368
 369                 default:
 370                         phydev->mdix = ETH_TP_MDI_INVALID;
 371                         break;
 372                 }
 373         }
 374
 375         return 0;
 376 }
 377 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
 378
 379 /**
 380  * genphy_c45_pma_read_abilities - read supported link modes from PMA
 381  * @phydev: target phy_device struct
 382  *
 383  * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
 384  * 1.8.9 is set, the list of supported modes is build using the values in the
 385  * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
 386  * modes. If bit 1.11.14 is set, then the list is also extended with the modes
 387  * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
 388  * 5GBASET are supported.
 389  */
 390 int genphy_c45_pma_read_abilities(struct phy_device *phydev)
 391 {
 392         int val;
 393
 394         linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
 395         if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
 396                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 397                 if (val < 0)
 398                         return val;
 399
 400                 if (val & MDIO_AN_STAT1_ABLE)
 401                         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 402                                          phydev->supported);
 403         }
 404
 405         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
 406         if (val < 0)
 407                 return val;
 408
 409         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 410                          phydev->supported,
 411                          val & MDIO_PMA_STAT2_10GBSR);
 412
 413         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
 414                          phydev->supported,
 415                          val & MDIO_PMA_STAT2_10GBLR);
 416
 417         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
 418                          phydev->supported,
 419                          val & MDIO_PMA_STAT2_10GBER);
 420
 421         if (val & MDIO_PMA_STAT2_EXTABLE) {
 422                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
 423                 if (val < 0)
 424                         return val;
 425
 426                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
 427                                  phydev->supported,
 428                                  val & MDIO_PMA_EXTABLE_10GBLRM);
 429                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 430                                  phydev->supported,
 431                                  val & MDIO_PMA_EXTABLE_10GBT);
 432                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
 433                                  phydev->supported,
 434                                  val & MDIO_PMA_EXTABLE_10GBKX4);
 435                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
 436                                  phydev->supported,
 437                                  val & MDIO_PMA_EXTABLE_10GBKR);
 438                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 439                                  phydev->supported,
 440                                  val & MDIO_PMA_EXTABLE_1000BT);
 441                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
 442                                  phydev->supported,
 443                                  val & MDIO_PMA_EXTABLE_1000BKX);
 444
 445                 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
 446                                  phydev->supported,
 447                                  val & MDIO_PMA_EXTABLE_100BTX);
 448                 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
 449                                  phydev->supported,
 450                                  val & MDIO_PMA_EXTABLE_100BTX);
 451
 452                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
 453                                  phydev->supported,
 454                                  val & MDIO_PMA_EXTABLE_10BT);
 455                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
 456                                  phydev->supported,
 457                                  val & MDIO_PMA_EXTABLE_10BT);
 458
 459                 if (val & MDIO_PMA_EXTABLE_NBT) {
 460                         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
 461                                            MDIO_PMA_NG_EXTABLE);
 462                         if (val < 0)
 463                                 return val;
 464
 465                         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 466                                          phydev->supported,
 467                                          val & MDIO_PMA_NG_EXTABLE_2_5GBT);
 468
 469                         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 470                                          phydev->supported,
 471                                          val & MDIO_PMA_NG_EXTABLE_5GBT);
 472                 }
 473         }
 474
 475         return 0;
 476 }
 477 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
 478
 479 /**
 480  * genphy_c45_read_status - read PHY status
 481  * @phydev: target phy_device struct
 482  *
 483  * Reads status from PHY and sets phy_device members accordingly.
 484  */
 485 int genphy_c45_read_status(struct phy_device *phydev)
 486 {
 487         int ret;
 488
 489         ret = genphy_c45_read_link(phydev);
 490         if (ret)
 491                 return ret;
 492
 493         phydev->speed = SPEED_UNKNOWN;
 494         phydev->duplex = DUPLEX_UNKNOWN;
 495         phydev->pause = 0;
 496         phydev->asym_pause = 0;
 497
 498         if (phydev->autoneg == AUTONEG_ENABLE) {
 499                 ret = genphy_c45_read_lpa(phydev);
 500                 if (ret)
 501                         return ret;
 502
 503                 phy_resolve_aneg_linkmode(phydev);
 504         } else {
 505                 ret = genphy_c45_read_pma(phydev);
 506         }
 507
 508         return ret;
 509 }
 510 EXPORT_SYMBOL_GPL(genphy_c45_read_status);
 511
 512 /* The gen10g_* functions are the old Clause 45 stub */
 513
 514 int gen10g_config_aneg(struct phy_device *phydev)
 515 {
 516         return 0;
 517 }
 518 EXPORT_SYMBOL_GPL(gen10g_config_aneg);
 519
 520 struct phy_driver genphy_c45_driver = {
 521         .phy_id         = 0xffffffff,
 522         .phy_id_mask    = 0xffffffff,
 523         .name           = "Generic Clause 45 PHY",
 524         .soft_reset     = genphy_no_soft_reset,
 525         .read_status    = genphy_c45_read_status,
 526 };