drivers/net/phy/realtek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/realtek.c
   4  *
   5  * Driver for Realtek PHYs
   6  *
   7  * Author: Johnson Leung <r58129@freescale.com>
   8  *
   9  * Copyright (c) 2004 Freescale Semiconductor, Inc.
  10  */
  11 #include <linux/bitops.h>
  12 #include <linux/phy.h>
  13 #include <linux/module.h>
  14
  15 #define RTL821x_PHYSR                           0x11
  16 #define RTL821x_PHYSR_DUPLEX                    BIT(13)
  17 #define RTL821x_PHYSR_SPEED                     GENMASK(15, 14)
  18
  19 #define RTL821x_INER                            0x12
  20 #define RTL8211B_INER_INIT                      0x6400
  21 #define RTL8211E_INER_LINK_STATUS               BIT(10)
  22 #define RTL8211F_INER_LINK_STATUS               BIT(4)
  23
  24 #define RTL821x_INSR                            0x13
  25
  26 #define RTL821x_EXT_PAGE_SELECT                 0x1e
  27 #define RTL821x_PAGE_SELECT                     0x1f
  28
  29 #define RTL8211F_INSR                           0x1d
  30
  31 #define RTL8211F_TX_DELAY                       BIT(8)
  32 #define RTL8211E_TX_DELAY                       BIT(1)
  33 #define RTL8211E_RX_DELAY                       BIT(2)
  34 #define RTL8211E_MODE_MII_GMII                  BIT(3)
  35
  36 #define RTL8201F_ISR                            0x1e
  37 #define RTL8201F_IER                            0x13
  38
  39 #define RTL8366RB_POWER_SAVE                    0x15
  40 #define RTL8366RB_POWER_SAVE_ON                 BIT(12)
  41
  42 #define RTL_ADV_2500FULL                        BIT(7)
  43 #define RTL_LPADV_10000FULL                     BIT(11)
  44 #define RTL_LPADV_5000FULL                      BIT(6)
  45 #define RTL_LPADV_2500FULL                      BIT(5)
  46
  47 MODULE_DESCRIPTION("Realtek PHY driver");
  48 MODULE_AUTHOR("Johnson Leung");
  49 MODULE_LICENSE("GPL");
  50
  51 static int rtl821x_read_page(struct phy_device *phydev)
  52 {
  53         return __phy_read(phydev, RTL821x_PAGE_SELECT);
  54 }
  55
  56 static int rtl821x_write_page(struct phy_device *phydev, int page)
  57 {
  58         return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
  59 }
  60
  61 static int rtl8201_ack_interrupt(struct phy_device *phydev)
  62 {
  63         int err;
  64
  65         err = phy_read(phydev, RTL8201F_ISR);
  66
  67         return (err < 0) ? err : 0;
  68 }
  69
  70 static int rtl821x_ack_interrupt(struct phy_device *phydev)
  71 {
  72         int err;
  73
  74         err = phy_read(phydev, RTL821x_INSR);
  75
  76         return (err < 0) ? err : 0;
  77 }
  78
  79 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
  80 {
  81         int err;
  82
  83         err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
  84
  85         return (err < 0) ? err : 0;
  86 }
  87
  88 static int rtl8201_config_intr(struct phy_device *phydev)
  89 {
  90         u16 val;
  91
  92         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  93                 val = BIT(13) | BIT(12) | BIT(11);
  94         else
  95                 val = 0;
  96
  97         return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
  98 }
  99
 100 static int rtl8211b_config_intr(struct phy_device *phydev)
 101 {
 102         int err;
 103
 104         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 105                 err = phy_write(phydev, RTL821x_INER,
 106                                 RTL8211B_INER_INIT);
 107         else
 108                 err = phy_write(phydev, RTL821x_INER, 0);
 109
 110         return err;
 111 }
 112
 113 static int rtl8211e_config_intr(struct phy_device *phydev)
 114 {
 115         int err;
 116
 117         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 118                 err = phy_write(phydev, RTL821x_INER,
 119                                 RTL8211E_INER_LINK_STATUS);
 120         else
 121                 err = phy_write(phydev, RTL821x_INER, 0);
 122
 123         return err;
 124 }
 125
 126 static int rtl8211f_config_intr(struct phy_device *phydev)
 127 {
 128         u16 val;
 129
 130         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 131                 val = RTL8211F_INER_LINK_STATUS;
 132         else
 133                 val = 0;
 134
 135         return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 136 }
 137
 138 static int rtl8211_config_aneg(struct phy_device *phydev)
 139 {
 140         int ret;
 141
 142         ret = genphy_config_aneg(phydev);
 143         if (ret < 0)
 144                 return ret;
 145
 146         /* Quirk was copied from vendor driver. Unfortunately it includes no
 147          * description of the magic numbers.
 148          */
 149         if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
 150                 phy_write(phydev, 0x17, 0x2138);
 151                 phy_write(phydev, 0x0e, 0x0260);
 152         } else {
 153                 phy_write(phydev, 0x17, 0x2108);
 154                 phy_write(phydev, 0x0e, 0x0000);
 155         }
 156
 157         return 0;
 158 }
 159
 160 static int rtl8211c_config_init(struct phy_device *phydev)
 161 {
 162         /* RTL8211C has an issue when operating in Gigabit slave mode */
 163         return phy_set_bits(phydev, MII_CTRL1000,
 164                             CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
 165 }
 166
 167 static int rtl8211f_config_init(struct phy_device *phydev)
 168 {
 169         u16 val;
 170
 171         /* enable TX-delay for rgmii-{id,txid}, and disable it for rgmii and
 172          * rgmii-rxid. The RX-delay can be enabled by the external RXDLY pin.
 173          */
 174         switch (phydev->interface) {
 175         case PHY_INTERFACE_MODE_RGMII:
 176         case PHY_INTERFACE_MODE_RGMII_RXID:
 177                 val = 0;
 178                 break;
 179         case PHY_INTERFACE_MODE_RGMII_ID:
 180         case PHY_INTERFACE_MODE_RGMII_TXID:
 181                 val = RTL8211F_TX_DELAY;
 182                 break;
 183         default: /* the rest of the modes imply leaving delay as is. */
 184                 return 0;
 185         }
 186
 187         return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val);
 188 }
 189
 190 static int rtl8211e_config_init(struct phy_device *phydev)
 191 {
 192         int ret = 0, oldpage;
 193         u16 val;
 194
 195         /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
 196         switch (phydev->interface) {
 197         case PHY_INTERFACE_MODE_RGMII:
 198                 val = 0;
 199                 break;
 200         case PHY_INTERFACE_MODE_RGMII_ID:
 201                 val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
 202                 break;
 203         case PHY_INTERFACE_MODE_RGMII_RXID:
 204                 val = RTL8211E_RX_DELAY;
 205                 break;
 206         case PHY_INTERFACE_MODE_RGMII_TXID:
 207                 val = RTL8211E_TX_DELAY;
 208                 break;
 209         default: /* the rest of the modes imply leaving delays as is. */
 210                 return 0;
 211         }
 212
 213         /* According to a sample driver there is a 0x1c config register on the
 214          * 0xa4 extension page (0x7) layout. It can be used to disable/enable
 215          * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can
 216          * also be used to customize the whole configuration register:
 217          * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,
 218          * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet
 219          * for details).
 220          */
 221         oldpage = phy_select_page(phydev, 0x7);
 222         if (oldpage < 0)
 223                 goto err_restore_page;
 224
 225         ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
 226         if (ret)
 227                 goto err_restore_page;
 228
 229         ret = __phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
 230                            val);
 231
 232 err_restore_page:
 233         return phy_restore_page(phydev, oldpage, ret);
 234 }
 235
 236 static int rtl8211b_suspend(struct phy_device *phydev)
 237 {
 238         phy_write(phydev, MII_MMD_DATA, BIT(9));
 239
 240         return genphy_suspend(phydev);
 241 }
 242
 243 static int rtl8211b_resume(struct phy_device *phydev)
 244 {
 245         phy_write(phydev, MII_MMD_DATA, 0);
 246
 247         return genphy_resume(phydev);
 248 }
 249
 250 static int rtl8366rb_config_init(struct phy_device *phydev)
 251 {
 252         int ret;
 253
 254         ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
 255                            RTL8366RB_POWER_SAVE_ON);
 256         if (ret) {
 257                 dev_err(&phydev->mdio.dev,
 258                         "error enabling power management\n");
 259         }
 260
 261         return ret;
 262 }
 263
 264 static int rtl8125_get_features(struct phy_device *phydev)
 265 {
 266         linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 267                          phydev->supported);
 268
 269         return genphy_read_abilities(phydev);
 270 }
 271
 272 static int rtl8125_config_aneg(struct phy_device *phydev)
 273 {
 274         int ret = 0;
 275
 276         if (phydev->autoneg == AUTONEG_ENABLE) {
 277                 u16 adv2500 = 0;
 278
 279                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 280                                       phydev->advertising))
 281                         adv2500 = RTL_ADV_2500FULL;
 282
 283                 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
 284                                                RTL_ADV_2500FULL, adv2500);
 285                 if (ret < 0)
 286                         return ret;
 287         }
 288
 289         return __genphy_config_aneg(phydev, ret);
 290 }
 291
 292 static int rtl8125_read_status(struct phy_device *phydev)
 293 {
 294         if (phydev->autoneg == AUTONEG_ENABLE) {
 295                 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
 296
 297                 if (lpadv < 0)
 298                         return lpadv;
 299
 300                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 301                         phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
 302                 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 303                         phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
 304                 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 305                         phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
 306         }
 307
 308         return genphy_read_status(phydev);
 309 }
 310
 311 static struct phy_driver realtek_drvs[] = {
 312         {
 313                 PHY_ID_MATCH_EXACT(0x00008201),
 314                 .name           = "RTL8201CP Ethernet",
 315         }, {
 316                 PHY_ID_MATCH_EXACT(0x001cc816),
 317                 .name           = "RTL8201F Fast Ethernet",
 318                 .ack_interrupt  = &rtl8201_ack_interrupt,
 319                 .config_intr    = &rtl8201_config_intr,
 320                 .suspend        = genphy_suspend,
 321                 .resume         = genphy_resume,
 322                 .read_page      = rtl821x_read_page,
 323                 .write_page     = rtl821x_write_page,
 324         }, {
 325                 PHY_ID_MATCH_EXACT(0x001cc910),
 326                 .name           = "RTL8211 Gigabit Ethernet",
 327                 .config_aneg    = rtl8211_config_aneg,
 328                 .read_mmd       = &genphy_read_mmd_unsupported,
 329                 .write_mmd      = &genphy_write_mmd_unsupported,
 330                 .read_page      = rtl821x_read_page,
 331                 .write_page     = rtl821x_write_page,
 332         }, {
 333                 PHY_ID_MATCH_EXACT(0x001cc912),
 334                 .name           = "RTL8211B Gigabit Ethernet",
 335                 .ack_interrupt  = &rtl821x_ack_interrupt,
 336                 .config_intr    = &rtl8211b_config_intr,
 337                 .read_mmd       = &genphy_read_mmd_unsupported,
 338                 .write_mmd      = &genphy_write_mmd_unsupported,
 339                 .suspend        = rtl8211b_suspend,
 340                 .resume         = rtl8211b_resume,
 341                 .read_page      = rtl821x_read_page,
 342                 .write_page     = rtl821x_write_page,
 343         }, {
 344                 PHY_ID_MATCH_EXACT(0x001cc913),
 345                 .name           = "RTL8211C Gigabit Ethernet",
 346                 .config_init    = rtl8211c_config_init,
 347                 .read_mmd       = &genphy_read_mmd_unsupported,
 348                 .write_mmd      = &genphy_write_mmd_unsupported,
 349                 .read_page      = rtl821x_read_page,
 350                 .write_page     = rtl821x_write_page,
 351         }, {
 352                 PHY_ID_MATCH_EXACT(0x001cc914),
 353                 .name           = "RTL8211DN Gigabit Ethernet",
 354                 .ack_interrupt  = rtl821x_ack_interrupt,
 355                 .config_intr    = rtl8211e_config_intr,
 356                 .suspend        = genphy_suspend,
 357                 .resume         = genphy_resume,
 358                 .read_page      = rtl821x_read_page,
 359                 .write_page     = rtl821x_write_page,
 360         }, {
 361                 PHY_ID_MATCH_EXACT(0x001cc915),
 362                 .name           = "RTL8211E Gigabit Ethernet",
 363                 .config_init    = &rtl8211e_config_init,
 364                 .ack_interrupt  = &rtl821x_ack_interrupt,
 365                 .config_intr    = &rtl8211e_config_intr,
 366                 .suspend        = genphy_suspend,
 367                 .resume         = genphy_resume,
 368                 .read_page      = rtl821x_read_page,
 369                 .write_page     = rtl821x_write_page,
 370         }, {
 371                 PHY_ID_MATCH_EXACT(0x001cc916),
 372                 .name           = "RTL8211F Gigabit Ethernet",
 373                 .config_init    = &rtl8211f_config_init,
 374                 .ack_interrupt  = &rtl8211f_ack_interrupt,
 375                 .config_intr    = &rtl8211f_config_intr,
 376                 .suspend        = genphy_suspend,
 377                 .resume         = genphy_resume,
 378                 .read_page      = rtl821x_read_page,
 379                 .write_page     = rtl821x_write_page,
 380         }, {
 381                 PHY_ID_MATCH_EXACT(0x001cc800),
 382                 .name           = "Generic Realtek PHY",
 383                 .suspend        = genphy_suspend,
 384                 .resume         = genphy_resume,
 385                 .read_page      = rtl821x_read_page,
 386                 .write_page     = rtl821x_write_page,
 387         }, {
 388                 PHY_ID_MATCH_EXACT(0x001cca50),
 389                 .name           = "RTL8125 2.5Gbps internal",
 390                 .get_features   = rtl8125_get_features,
 391                 .config_aneg    = rtl8125_config_aneg,
 392                 .read_status    = rtl8125_read_status,
 393                 .suspend        = genphy_suspend,
 394                 .resume         = genphy_resume,
 395                 .read_page      = rtl821x_read_page,
 396                 .write_page     = rtl821x_write_page,
 397         }, {
 398                 PHY_ID_MATCH_EXACT(0x001cc961),
 399                 .name           = "RTL8366RB Gigabit Ethernet",
 400                 .config_init    = &rtl8366rb_config_init,
 401                 /* These interrupts are handled by the irq controller
 402                  * embedded inside the RTL8366RB, they get unmasked when the
 403                  * irq is requested and ACKed by reading the status register,
 404                  * which is done by the irqchip code.
 405                  */
 406                 .ack_interrupt  = genphy_no_ack_interrupt,
 407                 .config_intr    = genphy_no_config_intr,
 408                 .suspend        = genphy_suspend,
 409                 .resume         = genphy_resume,
 410         },
 411 };
 412
 413 module_phy_driver(realtek_drvs);
 414
 415 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
 416         { PHY_ID_MATCH_VENDOR(0x001cc800) },
 417         { }
 418 };
 419
 420 MODULE_DEVICE_TABLE(mdio, realtek_tbl);