drivers/net/phy/realtek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/realtek.c
   4  *
   5  * Driver for Realtek PHYs
   6  *
   7  * Author: Johnson Leung <r58129@freescale.com>
   8  *
   9  * Copyright (c) 2004 Freescale Semiconductor, Inc.
  10  */
  11 #include <linux/bitops.h>
  12 #include <linux/phy.h>
  13 #include <linux/module.h>
  14
  15 #define RTL821x_PHYSR                           0x11
  16 #define RTL821x_PHYSR_DUPLEX                    BIT(13)
  17 #define RTL821x_PHYSR_SPEED                     GENMASK(15, 14)
  18
  19 #define RTL821x_INER                            0x12
  20 #define RTL8211B_INER_INIT                      0x6400
  21 #define RTL8211E_INER_LINK_STATUS               BIT(10)
  22 #define RTL8211F_INER_LINK_STATUS               BIT(4)
  23
  24 #define RTL821x_INSR                            0x13
  25
  26 #define RTL821x_EXT_PAGE_SELECT                 0x1e
  27 #define RTL821x_PAGE_SELECT                     0x1f
  28
  29 #define RTL8211F_INSR                           0x1d
  30
  31 #define RTL8211F_TX_DELAY                       BIT(8)
  32 #define RTL8211E_TX_DELAY                       BIT(1)
  33 #define RTL8211E_RX_DELAY                       BIT(2)
  34 #define RTL8211E_MODE_MII_GMII                  BIT(3)
  35
  36 #define RTL8201F_ISR                            0x1e
  37 #define RTL8201F_IER                            0x13
  38
  39 #define RTL8366RB_POWER_SAVE                    0x15
  40 #define RTL8366RB_POWER_SAVE_ON                 BIT(12)
  41
  42 MODULE_DESCRIPTION("Realtek PHY driver");
  43 MODULE_AUTHOR("Johnson Leung");
  44 MODULE_LICENSE("GPL");
  45
  46 static int rtl821x_read_page(struct phy_device *phydev)
  47 {
  48         return __phy_read(phydev, RTL821x_PAGE_SELECT);
  49 }
  50
  51 static int rtl821x_write_page(struct phy_device *phydev, int page)
  52 {
  53         return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
  54 }
  55
  56 static int rtl8201_ack_interrupt(struct phy_device *phydev)
  57 {
  58         int err;
  59
  60         err = phy_read(phydev, RTL8201F_ISR);
  61
  62         return (err < 0) ? err : 0;
  63 }
  64
  65 static int rtl821x_ack_interrupt(struct phy_device *phydev)
  66 {
  67         int err;
  68
  69         err = phy_read(phydev, RTL821x_INSR);
  70
  71         return (err < 0) ? err : 0;
  72 }
  73
  74 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
  75 {
  76         int err;
  77
  78         err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
  79
  80         return (err < 0) ? err : 0;
  81 }
  82
  83 static int rtl8201_config_intr(struct phy_device *phydev)
  84 {
  85         u16 val;
  86
  87         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  88                 val = BIT(13) | BIT(12) | BIT(11);
  89         else
  90                 val = 0;
  91
  92         return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
  93 }
  94
  95 static int rtl8211b_config_intr(struct phy_device *phydev)
  96 {
  97         int err;
  98
  99         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 100                 err = phy_write(phydev, RTL821x_INER,
 101                                 RTL8211B_INER_INIT);
 102         else
 103                 err = phy_write(phydev, RTL821x_INER, 0);
 104
 105         return err;
 106 }
 107
 108 static int rtl8211e_config_intr(struct phy_device *phydev)
 109 {
 110         int err;
 111
 112         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 113                 err = phy_write(phydev, RTL821x_INER,
 114                                 RTL8211E_INER_LINK_STATUS);
 115         else
 116                 err = phy_write(phydev, RTL821x_INER, 0);
 117
 118         return err;
 119 }
 120
 121 static int rtl8211f_config_intr(struct phy_device *phydev)
 122 {
 123         u16 val;
 124
 125         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 126                 val = RTL8211F_INER_LINK_STATUS;
 127         else
 128                 val = 0;
 129
 130         return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 131 }
 132
 133 static int rtl8211_config_aneg(struct phy_device *phydev)
 134 {
 135         int ret;
 136
 137         ret = genphy_config_aneg(phydev);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Quirk was copied from vendor driver. Unfortunately it includes no
 142          * description of the magic numbers.
 143          */
 144         if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
 145                 phy_write(phydev, 0x17, 0x2138);
 146                 phy_write(phydev, 0x0e, 0x0260);
 147         } else {
 148                 phy_write(phydev, 0x17, 0x2108);
 149                 phy_write(phydev, 0x0e, 0x0000);
 150         }
 151
 152         return 0;
 153 }
 154
 155 static int rtl8211c_config_init(struct phy_device *phydev)
 156 {
 157         /* RTL8211C has an issue when operating in Gigabit slave mode */
 158         return phy_set_bits(phydev, MII_CTRL1000,
 159                             CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
 160 }
 161
 162 static int rtl8211f_config_init(struct phy_device *phydev)
 163 {
 164         u16 val = 0;
 165
 166         /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
 167         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 168             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 169                 val = RTL8211F_TX_DELAY;
 170
 171         return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val);
 172 }
 173
 174 static int rtl8211e_config_init(struct phy_device *phydev)
 175 {
 176         int ret = 0, oldpage;
 177         u16 val;
 178
 179         /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
 180         switch (phydev->interface) {
 181         case PHY_INTERFACE_MODE_RGMII:
 182                 val = 0;
 183                 break;
 184         case PHY_INTERFACE_MODE_RGMII_ID:
 185                 val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
 186                 break;
 187         case PHY_INTERFACE_MODE_RGMII_RXID:
 188                 val = RTL8211E_RX_DELAY;
 189                 break;
 190         case PHY_INTERFACE_MODE_RGMII_TXID:
 191                 val = RTL8211E_TX_DELAY;
 192                 break;
 193         default: /* the rest of the modes imply leaving delays as is. */
 194                 return 0;
 195         }
 196
 197         /* According to a sample driver there is a 0x1c config register on the
 198          * 0xa4 extension page (0x7) layout. It can be used to disable/enable
 199          * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can
 200          * also be used to customize the whole configuration register:
 201          * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,
 202          * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet
 203          * for details).
 204          */
 205         oldpage = phy_select_page(phydev, 0x7);
 206         if (oldpage < 0)
 207                 goto err_restore_page;
 208
 209         ret = phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
 210         if (ret)
 211                 goto err_restore_page;
 212
 213         ret = phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
 214                          val);
 215
 216 err_restore_page:
 217         return phy_restore_page(phydev, oldpage, ret);
 218 }
 219
 220 static int rtl8211b_suspend(struct phy_device *phydev)
 221 {
 222         phy_write(phydev, MII_MMD_DATA, BIT(9));
 223
 224         return genphy_suspend(phydev);
 225 }
 226
 227 static int rtl8211b_resume(struct phy_device *phydev)
 228 {
 229         phy_write(phydev, MII_MMD_DATA, 0);
 230
 231         return genphy_resume(phydev);
 232 }
 233
 234 static int rtl8366rb_config_init(struct phy_device *phydev)
 235 {
 236         int ret;
 237
 238         ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
 239                            RTL8366RB_POWER_SAVE_ON);
 240         if (ret) {
 241                 dev_err(&phydev->mdio.dev,
 242                         "error enabling power management\n");
 243         }
 244
 245         return ret;
 246 }
 247
 248 static struct phy_driver realtek_drvs[] = {
 249         {
 250                 PHY_ID_MATCH_EXACT(0x00008201),
 251                 .name           = "RTL8201CP Ethernet",
 252         }, {
 253                 PHY_ID_MATCH_EXACT(0x001cc816),
 254                 .name           = "RTL8201F Fast Ethernet",
 255                 .ack_interrupt  = &rtl8201_ack_interrupt,
 256                 .config_intr    = &rtl8201_config_intr,
 257                 .suspend        = genphy_suspend,
 258                 .resume         = genphy_resume,
 259                 .read_page      = rtl821x_read_page,
 260                 .write_page     = rtl821x_write_page,
 261         }, {
 262                 PHY_ID_MATCH_EXACT(0x001cc910),
 263                 .name           = "RTL8211 Gigabit Ethernet",
 264                 .config_aneg    = rtl8211_config_aneg,
 265                 .read_mmd       = &genphy_read_mmd_unsupported,
 266                 .write_mmd      = &genphy_write_mmd_unsupported,
 267         }, {
 268                 PHY_ID_MATCH_EXACT(0x001cc912),
 269                 .name           = "RTL8211B Gigabit Ethernet",
 270                 .ack_interrupt  = &rtl821x_ack_interrupt,
 271                 .config_intr    = &rtl8211b_config_intr,
 272                 .read_mmd       = &genphy_read_mmd_unsupported,
 273                 .write_mmd      = &genphy_write_mmd_unsupported,
 274                 .suspend        = rtl8211b_suspend,
 275                 .resume         = rtl8211b_resume,
 276         }, {
 277                 PHY_ID_MATCH_EXACT(0x001cc913),
 278                 .name           = "RTL8211C Gigabit Ethernet",
 279                 .config_init    = rtl8211c_config_init,
 280                 .read_mmd       = &genphy_read_mmd_unsupported,
 281                 .write_mmd      = &genphy_write_mmd_unsupported,
 282         }, {
 283                 PHY_ID_MATCH_EXACT(0x001cc914),
 284                 .name           = "RTL8211DN Gigabit Ethernet",
 285                 .ack_interrupt  = rtl821x_ack_interrupt,
 286                 .config_intr    = rtl8211e_config_intr,
 287                 .suspend        = genphy_suspend,
 288                 .resume         = genphy_resume,
 289         }, {
 290                 PHY_ID_MATCH_EXACT(0x001cc915),
 291                 .name           = "RTL8211E Gigabit Ethernet",
 292                 .config_init    = &rtl8211e_config_init,
 293                 .ack_interrupt  = &rtl821x_ack_interrupt,
 294                 .config_intr    = &rtl8211e_config_intr,
 295                 .suspend        = genphy_suspend,
 296                 .resume         = genphy_resume,
 297         }, {
 298                 PHY_ID_MATCH_EXACT(0x001cc916),
 299                 .name           = "RTL8211F Gigabit Ethernet",
 300                 .config_init    = &rtl8211f_config_init,
 301                 .ack_interrupt  = &rtl8211f_ack_interrupt,
 302                 .config_intr    = &rtl8211f_config_intr,
 303                 .suspend        = genphy_suspend,
 304                 .resume         = genphy_resume,
 305                 .read_page      = rtl821x_read_page,
 306                 .write_page     = rtl821x_write_page,
 307         }, {
 308                 PHY_ID_MATCH_EXACT(0x001cc800),
 309                 .name           = "Generic Realtek PHY",
 310                 .suspend        = genphy_suspend,
 311                 .resume         = genphy_resume,
 312                 .read_page      = rtl821x_read_page,
 313                 .write_page     = rtl821x_write_page,
 314         }, {
 315                 PHY_ID_MATCH_EXACT(0x001cc961),
 316                 .name           = "RTL8366RB Gigabit Ethernet",
 317                 .config_init    = &rtl8366rb_config_init,
 318                 /* These interrupts are handled by the irq controller
 319                  * embedded inside the RTL8366RB, they get unmasked when the
 320                  * irq is requested and ACKed by reading the status register,
 321                  * which is done by the irqchip code.
 322                  */
 323                 .ack_interrupt  = genphy_no_ack_interrupt,
 324                 .config_intr    = genphy_no_config_intr,
 325                 .suspend        = genphy_suspend,
 326                 .resume         = genphy_resume,
 327         },
 328 };
 329
 330 module_phy_driver(realtek_drvs);
 331
 332 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
 333         { PHY_ID_MATCH_VENDOR(0x001cc800) },
 334         { }
 335 };
 336
 337 MODULE_DEVICE_TABLE(mdio, realtek_tbl);