drivers/net/phy/rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**
   3  * drivers/net/phy/rockchip.c
   4  *
   5  * Driver for ROCKCHIP Ethernet PHYs
   6  *
   7  * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
   8  *
   9  * David Wu <david.wu@rock-chips.com>
  10  */
  11
  12 #include <linux/ethtool.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/mii.h>
  16 #include <linux/netdevice.h>
  17 #include <linux/phy.h>
  18
  19 #define INTERNAL_EPHY_ID                        0x1234d400
  20
  21 #define MII_INTERNAL_CTRL_STATUS                17
  22 #define SMI_ADDR_TSTCNTL                        20
  23 #define SMI_ADDR_TSTREAD1                       21
  24 #define SMI_ADDR_TSTREAD2                       22
  25 #define SMI_ADDR_TSTWRITE                       23
  26 #define MII_SPECIAL_CONTROL_STATUS              31
  27
  28 #define MII_AUTO_MDIX_EN                        BIT(7)
  29 #define MII_MDIX_EN                             BIT(6)
  30
  31 #define MII_SPEED_10                            BIT(2)
  32 #define MII_SPEED_100                           BIT(3)
  33
  34 #define TSTCNTL_RD                              (BIT(15) | BIT(10))
  35 #define TSTCNTL_WR                              (BIT(14) | BIT(10))
  36
  37 #define TSTMODE_ENABLE                          0x400
  38 #define TSTMODE_DISABLE                         0x0
  39
  40 #define WR_ADDR_A7CFG                           0x18
  41
  42 static int rockchip_init_tstmode(struct phy_device *phydev)
  43 {
  44         int ret;
  45
  46         /* Enable access to Analog and DSP register banks */
  47         ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
  48         if (ret)
  49                 return ret;
  50
  51         ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
  52         if (ret)
  53                 return ret;
  54
  55         return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
  56 }
  57
  58 static int rockchip_close_tstmode(struct phy_device *phydev)
  59 {
  60         /* Back to basic register bank */
  61         return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
  62 }
  63
  64 static int rockchip_integrated_phy_analog_init(struct phy_device *phydev)
  65 {
  66         int ret;
  67
  68         ret = rockchip_init_tstmode(phydev);
  69         if (ret)
  70                 return ret;
  71
  72         /*
  73          * Adjust tx amplitude to make sginal better,
  74          * the default value is 0x8.
  75          */
  76         ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB);
  77         if (ret)
  78                 return ret;
  79         ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG);
  80         if (ret)
  81                 return ret;
  82
  83         return rockchip_close_tstmode(phydev);
  84 }
  85
  86 static int rockchip_integrated_phy_config_init(struct phy_device *phydev)
  87 {
  88         int val, ret;
  89
  90         /*
  91          * The auto MIDX has linked problem on some board,
  92          * workround to disable auto MDIX.
  93          */
  94         val = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
  95         if (val < 0)
  96                 return val;
  97         val &= ~MII_AUTO_MDIX_EN;
  98         ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
  99         if (ret)
 100                 return ret;
 101
 102         return rockchip_integrated_phy_analog_init(phydev);
 103 }
 104
 105 static void rockchip_link_change_notify(struct phy_device *phydev)
 106 {
 107         int speed = SPEED_10;
 108
 109         if (phydev->autoneg == AUTONEG_ENABLE) {
 110                 int reg = phy_read(phydev, MII_SPECIAL_CONTROL_STATUS);
 111
 112                 if (reg < 0) {
 113                         phydev_err(phydev, "phy_read err: %d.\n", reg);
 114                         return;
 115                 }
 116
 117                 if (reg & MII_SPEED_100)
 118                         speed = SPEED_100;
 119                 else if (reg & MII_SPEED_10)
 120                         speed = SPEED_10;
 121         } else {
 122                 int bmcr = phy_read(phydev, MII_BMCR);
 123
 124                 if (bmcr < 0) {
 125                         phydev_err(phydev, "phy_read err: %d.\n", bmcr);
 126                         return;
 127                 }
 128
 129                 if (bmcr & BMCR_SPEED100)
 130                         speed = SPEED_100;
 131                 else
 132                         speed = SPEED_10;
 133         }
 134
 135         /*
 136          * If mode switch happens from 10BT to 100BT, all DSP/AFE
 137          * registers are set to default values. So any AFE/DSP
 138          * registers have to be re-initialized in this case.
 139          */
 140         if ((phydev->speed == SPEED_10) && (speed == SPEED_100)) {
 141                 int ret = rockchip_integrated_phy_analog_init(phydev);
 142                 if (ret)
 143                         phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n",
 144                                    ret);
 145         }
 146 }
 147
 148 static int rockchip_set_polarity(struct phy_device *phydev, int polarity)
 149 {
 150         int reg, err, val;
 151
 152         /* get the current settings */
 153         reg = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
 154         if (reg < 0)
 155                 return reg;
 156
 157         reg &= ~MII_AUTO_MDIX_EN;
 158         val = reg;
 159         switch (polarity) {
 160         case ETH_TP_MDI:
 161                 val &= ~MII_MDIX_EN;
 162                 break;
 163         case ETH_TP_MDI_X:
 164                 val |= MII_MDIX_EN;
 165                 break;
 166         case ETH_TP_MDI_AUTO:
 167         case ETH_TP_MDI_INVALID:
 168         default:
 169                 return 0;
 170         }
 171
 172         if (val != reg) {
 173                 /* Set the new polarity value in the register */
 174                 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
 175                 if (err)
 176                         return err;
 177         }
 178
 179         return 0;
 180 }
 181
 182 static int rockchip_config_aneg(struct phy_device *phydev)
 183 {
 184         int err;
 185
 186         err = rockchip_set_polarity(phydev, phydev->mdix);
 187         if (err < 0)
 188                 return err;
 189
 190         return genphy_config_aneg(phydev);
 191 }
 192
 193 static int rockchip_phy_resume(struct phy_device *phydev)
 194 {
 195         genphy_resume(phydev);
 196
 197         return rockchip_integrated_phy_config_init(phydev);
 198 }
 199
 200 static struct phy_driver rockchip_phy_driver[] = {
 201 {
 202         .phy_id                 = INTERNAL_EPHY_ID,
 203         .phy_id_mask            = 0xfffffff0,
 204         .name                   = "Rockchip integrated EPHY",
 205         .features               = PHY_BASIC_FEATURES,
 206         .flags                  = 0,
 207         .link_change_notify     = rockchip_link_change_notify,
 208         .soft_reset             = genphy_soft_reset,
 209         .config_init            = rockchip_integrated_phy_config_init,
 210         .config_aneg            = rockchip_config_aneg,
 211         .suspend                = genphy_suspend,
 212         .resume                 = rockchip_phy_resume,
 213 },
 214 };
 215
 216 module_phy_driver(rockchip_phy_driver);
 217
 218 static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
 219         { INTERNAL_EPHY_ID, 0xfffffff0 },
 220         { }
 221 };
 222
 223 MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
 224
 225 MODULE_AUTHOR("David Wu <david.wu@rock-chips.com>");
 226 MODULE_DESCRIPTION("Rockchip Ethernet PHY driver");
 227 MODULE_LICENSE("GPL");