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qlcnic: Bumped up version number
[mirror_ubuntu-zesty-kernel.git] / drivers / net / qlcnic / qlcnic.h
1 /*
2 * Copyright (C) 2009 - QLogic Corporation.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
22 *
23 */
24
25 #ifndef _QLCNIC_H_
26 #define _QLCNIC_H_
27
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ip.h>
36 #include <linux/in.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/firmware.h>
40
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/timer.h>
44
45 #include <linux/vmalloc.h>
46
47 #include <linux/io.h>
48 #include <asm/byteorder.h>
49
50 #include "qlcnic_hdr.h"
51
52 #define _QLCNIC_LINUX_MAJOR 5
53 #define _QLCNIC_LINUX_MINOR 0
54 #define _QLCNIC_LINUX_SUBVERSION 4
55 #define QLCNIC_LINUX_VERSIONID "5.0.4"
56 #define QLCNIC_DRV_IDC_VER 0x01
57
58 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
59 #define _major(v) (((v) >> 24) & 0xff)
60 #define _minor(v) (((v) >> 16) & 0xff)
61 #define _build(v) ((v) & 0xffff)
62
63 /* version in image has weird encoding:
64 * 7:0 - major
65 * 15:8 - minor
66 * 31:16 - build (little endian)
67 */
68 #define QLCNIC_DECODE_VERSION(v) \
69 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
70
71 #define QLCNIC_NUM_FLASH_SECTORS (64)
72 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
73 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
74 * QLCNIC_FLASH_SECTOR_SIZE)
75
76 #define RCV_DESC_RINGSIZE(rds_ring) \
77 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
78 #define RCV_BUFF_RINGSIZE(rds_ring) \
79 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
80 #define STATUS_DESC_RINGSIZE(sds_ring) \
81 (sizeof(struct status_desc) * (sds_ring)->num_desc)
82 #define TX_BUFF_RINGSIZE(tx_ring) \
83 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
84 #define TX_DESC_RINGSIZE(tx_ring) \
85 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
86
87 #define QLCNIC_P3P_A0 0x50
88
89 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
90
91 #define FIRST_PAGE_GROUP_START 0
92 #define FIRST_PAGE_GROUP_END 0x100000
93
94 #define P3_MAX_MTU (9600)
95 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
96
97 #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
98 #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU)
99 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
100 #define QLCNIC_LRO_BUFFER_EXTRA 2048
101
102 /* Opcodes to be used with the commands */
103 #define TX_ETHER_PKT 0x01
104 #define TX_TCP_PKT 0x02
105 #define TX_UDP_PKT 0x03
106 #define TX_IP_PKT 0x04
107 #define TX_TCP_LSO 0x05
108 #define TX_TCP_LSO6 0x06
109 #define TX_IPSEC 0x07
110 #define TX_IPSEC_CMD 0x0a
111 #define TX_TCPV6_PKT 0x0b
112 #define TX_UDPV6_PKT 0x0c
113
114 /* Tx defines */
115 #define MAX_BUFFERS_PER_CMD 32
116 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
117 #define QLCNIC_MAX_TX_TIMEOUTS 2
118
119 /*
120 * Following are the states of the Phantom. Phantom will set them and
121 * Host will read to check if the fields are correct.
122 */
123 #define PHAN_INITIALIZE_FAILED 0xffff
124 #define PHAN_INITIALIZE_COMPLETE 0xff01
125
126 /* Host writes the following to notify that it has done the init-handshake */
127 #define PHAN_INITIALIZE_ACK 0xf00f
128 #define PHAN_PEG_RCV_INITIALIZED 0xff01
129
130 #define NUM_RCV_DESC_RINGS 3
131 #define NUM_STS_DESC_RINGS 4
132
133 #define RCV_RING_NORMAL 0
134 #define RCV_RING_JUMBO 1
135
136 #define MIN_CMD_DESCRIPTORS 64
137 #define MIN_RCV_DESCRIPTORS 64
138 #define MIN_JUMBO_DESCRIPTORS 32
139
140 #define MAX_CMD_DESCRIPTORS 1024
141 #define MAX_RCV_DESCRIPTORS_1G 4096
142 #define MAX_RCV_DESCRIPTORS_10G 8192
143 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
144 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
145
146 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
147 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
148
149 #define get_next_index(index, length) \
150 (((index) + 1) & ((length) - 1))
151
152 /*
153 * Following data structures describe the descriptors that will be used.
154 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
155 * we are doing LSO (above the 1500 size packet) only.
156 */
157
158 #define FLAGS_VLAN_TAGGED 0x10
159 #define FLAGS_VLAN_OOB 0x40
160
161 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
162 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
163 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
164 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
165 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
166 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
167
168 #define qlcnic_set_tx_port(_desc, _port) \
169 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
170
171 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
172 ((_desc)->flags_opcode = \
173 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
174
175 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
176 ((_desc)->nfrags__length = \
177 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
178
179 struct cmd_desc_type0 {
180 u8 tcp_hdr_offset; /* For LSO only */
181 u8 ip_hdr_offset; /* For LSO only */
182 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
183 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
184
185 __le64 addr_buffer2;
186
187 __le16 reference_handle;
188 __le16 mss;
189 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
190 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
191 __le16 conn_id; /* IPSec offoad only */
192
193 __le64 addr_buffer3;
194 __le64 addr_buffer1;
195
196 __le16 buffer_length[4];
197
198 __le64 addr_buffer4;
199
200 u8 eth_addr[ETH_ALEN];
201 __le16 vlan_TCI;
202
203 } __attribute__ ((aligned(64)));
204
205 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
206 struct rcv_desc {
207 __le16 reference_handle;
208 __le16 reserved;
209 __le32 buffer_length; /* allocated buffer length (usually 2K) */
210 __le64 addr_buffer;
211 };
212
213 /* opcode field in status_desc */
214 #define QLCNIC_SYN_OFFLOAD 0x03
215 #define QLCNIC_RXPKT_DESC 0x04
216 #define QLCNIC_OLD_RXPKT_DESC 0x3f
217 #define QLCNIC_RESPONSE_DESC 0x05
218 #define QLCNIC_LRO_DESC 0x12
219
220 /* for status field in status_desc */
221 #define STATUS_CKSUM_OK (2)
222
223 /* owner bits of status_desc */
224 #define STATUS_OWNER_HOST (0x1ULL << 56)
225 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
226
227 /* Status descriptor:
228 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
229 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
230 53-55 desc_cnt, 56-57 owner, 58-63 opcode
231 */
232 #define qlcnic_get_sts_port(sts_data) \
233 ((sts_data) & 0x0F)
234 #define qlcnic_get_sts_status(sts_data) \
235 (((sts_data) >> 4) & 0x0F)
236 #define qlcnic_get_sts_type(sts_data) \
237 (((sts_data) >> 8) & 0x0F)
238 #define qlcnic_get_sts_totallength(sts_data) \
239 (((sts_data) >> 12) & 0xFFFF)
240 #define qlcnic_get_sts_refhandle(sts_data) \
241 (((sts_data) >> 28) & 0xFFFF)
242 #define qlcnic_get_sts_prot(sts_data) \
243 (((sts_data) >> 44) & 0x0F)
244 #define qlcnic_get_sts_pkt_offset(sts_data) \
245 (((sts_data) >> 48) & 0x1F)
246 #define qlcnic_get_sts_desc_cnt(sts_data) \
247 (((sts_data) >> 53) & 0x7)
248 #define qlcnic_get_sts_opcode(sts_data) \
249 (((sts_data) >> 58) & 0x03F)
250
251 #define qlcnic_get_lro_sts_refhandle(sts_data) \
252 ((sts_data) & 0x0FFFF)
253 #define qlcnic_get_lro_sts_length(sts_data) \
254 (((sts_data) >> 16) & 0x0FFFF)
255 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
256 (((sts_data) >> 32) & 0x0FF)
257 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
258 (((sts_data) >> 40) & 0x0FF)
259 #define qlcnic_get_lro_sts_timestamp(sts_data) \
260 (((sts_data) >> 48) & 0x1)
261 #define qlcnic_get_lro_sts_type(sts_data) \
262 (((sts_data) >> 49) & 0x7)
263 #define qlcnic_get_lro_sts_push_flag(sts_data) \
264 (((sts_data) >> 52) & 0x1)
265 #define qlcnic_get_lro_sts_seq_number(sts_data) \
266 ((sts_data) & 0x0FFFFFFFF)
267
268
269 struct status_desc {
270 __le64 status_desc_data[2];
271 } __attribute__ ((aligned(16)));
272
273 /* UNIFIED ROMIMAGE */
274 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
275 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
276 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
277 #define QLCNIC_UNI_DIR_SECT_FW 0x7
278
279 /*Offsets */
280 #define QLCNIC_UNI_CHIP_REV_OFF 10
281 #define QLCNIC_UNI_FLAGS_OFF 11
282 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
283 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
284 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
285
286 struct uni_table_desc{
287 u32 findex;
288 u32 num_entries;
289 u32 entry_size;
290 u32 reserved[5];
291 };
292
293 struct uni_data_desc{
294 u32 findex;
295 u32 size;
296 u32 reserved[5];
297 };
298
299 /* Magic number to let user know flash is programmed */
300 #define QLCNIC_BDINFO_MAGIC 0x12345678
301
302 #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021
303 #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022
304 #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023
305 #define QLCNIC_BRDTYPE_P3_4_GB 0x0024
306 #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025
307 #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026
308 #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027
309 #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028
310 #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029
311 #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a
312 #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b
313 #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031
314 #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032
315 #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080
316
317 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
318
319 /* Flash memory map */
320 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
321 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
322 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
323 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
324
325 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
326 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
327 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
328 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
329
330 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
331 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
332
333 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
334 #define QLCNIC_UNIFIED_ROMIMAGE 0
335 #define QLCNIC_FLASH_ROMIMAGE 1
336 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
337
338 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
339 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
340
341 extern char qlcnic_driver_name[];
342
343 /* Number of status descriptors to handle per interrupt */
344 #define MAX_STATUS_HANDLE (64)
345
346 /*
347 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
348 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
349 */
350 struct qlcnic_skb_frag {
351 u64 dma;
352 u64 length;
353 };
354
355 struct qlcnic_recv_crb {
356 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
357 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
358 u32 sw_int_mask[NUM_STS_DESC_RINGS];
359 };
360
361 /* Following defines are for the state of the buffers */
362 #define QLCNIC_BUFFER_FREE 0
363 #define QLCNIC_BUFFER_BUSY 1
364
365 /*
366 * There will be one qlcnic_buffer per skb packet. These will be
367 * used to save the dma info for pci_unmap_page()
368 */
369 struct qlcnic_cmd_buffer {
370 struct sk_buff *skb;
371 struct qlcnic_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
372 u32 frag_count;
373 };
374
375 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
376 struct qlcnic_rx_buffer {
377 struct list_head list;
378 struct sk_buff *skb;
379 u64 dma;
380 u16 ref_handle;
381 u16 state;
382 };
383
384 /* Board types */
385 #define QLCNIC_GBE 0x01
386 #define QLCNIC_XGBE 0x02
387
388 /*
389 * One hardware_context{} per adapter
390 * contains interrupt info as well shared hardware info.
391 */
392 struct qlcnic_hardware_context {
393 void __iomem *pci_base0;
394 void __iomem *ocm_win_crb;
395
396 unsigned long pci_len0;
397
398 rwlock_t crb_lock;
399 struct mutex mem_lock;
400
401 u8 revision_id;
402 u8 pci_func;
403 u8 linkup;
404 u16 port_type;
405 u16 board_type;
406 };
407
408 struct qlcnic_adapter_stats {
409 u64 xmitcalled;
410 u64 xmitfinished;
411 u64 rxdropped;
412 u64 txdropped;
413 u64 csummed;
414 u64 rx_pkts;
415 u64 lro_pkts;
416 u64 rxbytes;
417 u64 txbytes;
418 u64 lrobytes;
419 u64 lso_frames;
420 u64 xmit_on;
421 u64 xmit_off;
422 u64 skb_alloc_failure;
423 u64 null_skb;
424 u64 null_rxbuf;
425 u64 rx_dma_map_error;
426 u64 tx_dma_map_error;
427 };
428
429 /*
430 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
431 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
432 */
433 struct qlcnic_host_rds_ring {
434 u32 producer;
435 u32 num_desc;
436 u32 dma_size;
437 u32 skb_size;
438 u32 flags;
439 void __iomem *crb_rcv_producer;
440 struct rcv_desc *desc_head;
441 struct qlcnic_rx_buffer *rx_buf_arr;
442 struct list_head free_list;
443 spinlock_t lock;
444 dma_addr_t phys_addr;
445 };
446
447 struct qlcnic_host_sds_ring {
448 u32 consumer;
449 u32 num_desc;
450 void __iomem *crb_sts_consumer;
451 void __iomem *crb_intr_mask;
452
453 struct status_desc *desc_head;
454 struct qlcnic_adapter *adapter;
455 struct napi_struct napi;
456 struct list_head free_list[NUM_RCV_DESC_RINGS];
457
458 int irq;
459
460 dma_addr_t phys_addr;
461 char name[IFNAMSIZ+4];
462 };
463
464 struct qlcnic_host_tx_ring {
465 u32 producer;
466 __le32 *hw_consumer;
467 u32 sw_consumer;
468 void __iomem *crb_cmd_producer;
469 u32 num_desc;
470
471 struct netdev_queue *txq;
472
473 struct qlcnic_cmd_buffer *cmd_buf_arr;
474 struct cmd_desc_type0 *desc_head;
475 dma_addr_t phys_addr;
476 dma_addr_t hw_cons_phys_addr;
477 };
478
479 /*
480 * Receive context. There is one such structure per instance of the
481 * receive processing. Any state information that is relevant to
482 * the receive, and is must be in this structure. The global data may be
483 * present elsewhere.
484 */
485 struct qlcnic_recv_context {
486 u32 state;
487 u16 context_id;
488 u16 virt_port;
489
490 struct qlcnic_host_rds_ring *rds_rings;
491 struct qlcnic_host_sds_ring *sds_rings;
492 };
493
494 /* HW context creation */
495
496 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
497 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
498 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
499
500 #define QLCNIC_CDRP_CMD_BIT 0x80000000
501
502 /*
503 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
504 * in the crb QLCNIC_CDRP_CRB_OFFSET.
505 */
506 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
507 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
508
509 #define QLCNIC_CDRP_RSP_OK 0x00000001
510 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
511 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
512
513 /*
514 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
515 * the crb QLCNIC_CDRP_CRB_OFFSET.
516 */
517 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
518 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
519
520 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
521 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
522 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
523 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
524 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
525 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
526 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
527 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
528 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
529 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
530 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
531 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
532 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
533 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
534 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
535 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
536 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
537 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
538 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
539 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
540 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
541 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
542 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
543 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
544 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
545 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
546 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
547
548 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
549 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
550 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
551 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
552 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
553 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
554 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
555 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
556 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
557
558 #define QLCNIC_RCODE_SUCCESS 0
559 #define QLCNIC_RCODE_TIMEOUT 17
560 #define QLCNIC_DESTROY_CTX_RESET 0
561
562 /*
563 * Capabilities Announced
564 */
565 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
566 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
567 #define QLCNIC_CAP0_LSO (1 << 6)
568 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
569 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
570
571 /*
572 * Context state
573 */
574
575 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
576
577 /*
578 * Rx context
579 */
580
581 struct qlcnic_hostrq_sds_ring {
582 __le64 host_phys_addr; /* Ring base addr */
583 __le32 ring_size; /* Ring entries */
584 __le16 msi_index;
585 __le16 rsvd; /* Padding */
586 };
587
588 struct qlcnic_hostrq_rds_ring {
589 __le64 host_phys_addr; /* Ring base addr */
590 __le64 buff_size; /* Packet buffer size */
591 __le32 ring_size; /* Ring entries */
592 __le32 ring_kind; /* Class of ring */
593 };
594
595 struct qlcnic_hostrq_rx_ctx {
596 __le64 host_rsp_dma_addr; /* Response dma'd here */
597 __le32 capabilities[4]; /* Flag bit vector */
598 __le32 host_int_crb_mode; /* Interrupt crb usage */
599 __le32 host_rds_crb_mode; /* RDS crb usage */
600 /* These ring offsets are relative to data[0] below */
601 __le32 rds_ring_offset; /* Offset to RDS config */
602 __le32 sds_ring_offset; /* Offset to SDS config */
603 __le16 num_rds_rings; /* Count of RDS rings */
604 __le16 num_sds_rings; /* Count of SDS rings */
605 __le16 rsvd1; /* Padding */
606 __le16 rsvd2; /* Padding */
607 u8 reserved[128]; /* reserve space for future expansion*/
608 /* MUST BE 64-bit aligned.
609 The following is packed:
610 - N hostrq_rds_rings
611 - N hostrq_sds_rings */
612 char data[0];
613 };
614
615 struct qlcnic_cardrsp_rds_ring{
616 __le32 host_producer_crb; /* Crb to use */
617 __le32 rsvd1; /* Padding */
618 };
619
620 struct qlcnic_cardrsp_sds_ring {
621 __le32 host_consumer_crb; /* Crb to use */
622 __le32 interrupt_crb; /* Crb to use */
623 };
624
625 struct qlcnic_cardrsp_rx_ctx {
626 /* These ring offsets are relative to data[0] below */
627 __le32 rds_ring_offset; /* Offset to RDS config */
628 __le32 sds_ring_offset; /* Offset to SDS config */
629 __le32 host_ctx_state; /* Starting State */
630 __le32 num_fn_per_port; /* How many PCI fn share the port */
631 __le16 num_rds_rings; /* Count of RDS rings */
632 __le16 num_sds_rings; /* Count of SDS rings */
633 __le16 context_id; /* Handle for context */
634 u8 phys_port; /* Physical id of port */
635 u8 virt_port; /* Virtual/Logical id of port */
636 u8 reserved[128]; /* save space for future expansion */
637 /* MUST BE 64-bit aligned.
638 The following is packed:
639 - N cardrsp_rds_rings
640 - N cardrs_sds_rings */
641 char data[0];
642 };
643
644 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
645 (sizeof(HOSTRQ_RX) + \
646 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
647 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
648
649 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
650 (sizeof(CARDRSP_RX) + \
651 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
652 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
653
654 /*
655 * Tx context
656 */
657
658 struct qlcnic_hostrq_cds_ring {
659 __le64 host_phys_addr; /* Ring base addr */
660 __le32 ring_size; /* Ring entries */
661 __le32 rsvd; /* Padding */
662 };
663
664 struct qlcnic_hostrq_tx_ctx {
665 __le64 host_rsp_dma_addr; /* Response dma'd here */
666 __le64 cmd_cons_dma_addr; /* */
667 __le64 dummy_dma_addr; /* */
668 __le32 capabilities[4]; /* Flag bit vector */
669 __le32 host_int_crb_mode; /* Interrupt crb usage */
670 __le32 rsvd1; /* Padding */
671 __le16 rsvd2; /* Padding */
672 __le16 interrupt_ctl;
673 __le16 msi_index;
674 __le16 rsvd3; /* Padding */
675 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
676 u8 reserved[128]; /* future expansion */
677 };
678
679 struct qlcnic_cardrsp_cds_ring {
680 __le32 host_producer_crb; /* Crb to use */
681 __le32 interrupt_crb; /* Crb to use */
682 };
683
684 struct qlcnic_cardrsp_tx_ctx {
685 __le32 host_ctx_state; /* Starting state */
686 __le16 context_id; /* Handle for context */
687 u8 phys_port; /* Physical id of port */
688 u8 virt_port; /* Virtual/Logical id of port */
689 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
690 u8 reserved[128]; /* future expansion */
691 };
692
693 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
694 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
695
696 /* CRB */
697
698 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
699 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
700 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
701 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
702
703 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
704 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
705 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
706 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
707 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
708
709
710 /* MAC */
711
712 #define MC_COUNT_P3 38
713
714 #define QLCNIC_MAC_NOOP 0
715 #define QLCNIC_MAC_ADD 1
716 #define QLCNIC_MAC_DEL 2
717
718 struct qlcnic_mac_list_s {
719 struct list_head list;
720 uint8_t mac_addr[ETH_ALEN+2];
721 };
722
723 /*
724 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
725 * adjusted based on configured MTU.
726 */
727 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
728 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
729 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
730 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
731
732 #define QLCNIC_INTR_DEFAULT 0x04
733
734 union qlcnic_nic_intr_coalesce_data {
735 struct {
736 u16 rx_packets;
737 u16 rx_time_us;
738 u16 tx_packets;
739 u16 tx_time_us;
740 } data;
741 u64 word;
742 };
743
744 struct qlcnic_nic_intr_coalesce {
745 u16 stats_time_us;
746 u16 rate_sample_time;
747 u16 flags;
748 u16 rsvd_1;
749 u32 low_threshold;
750 u32 high_threshold;
751 union qlcnic_nic_intr_coalesce_data normal;
752 union qlcnic_nic_intr_coalesce_data low;
753 union qlcnic_nic_intr_coalesce_data high;
754 union qlcnic_nic_intr_coalesce_data irq;
755 };
756
757 #define QLCNIC_HOST_REQUEST 0x13
758 #define QLCNIC_REQUEST 0x14
759
760 #define QLCNIC_MAC_EVENT 0x1
761
762 #define QLCNIC_IP_UP 2
763 #define QLCNIC_IP_DOWN 3
764
765 /*
766 * Driver --> Firmware
767 */
768 #define QLCNIC_H2C_OPCODE_START 0
769 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
770 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
771 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
772 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
773 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
774 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
775 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
776 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
777 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
778 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
779 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
780 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
781 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
782 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
783 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
784 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
785 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
786 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
787 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19
788 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
789 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
790 #define QLCNIC_C2C_OPCODE 22
791 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
792 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
793 #define QLCNIC_H2C_OPCODE_LAST 25
794 /*
795 * Firmware --> Driver
796 */
797
798 #define QLCNIC_C2H_OPCODE_START 128
799 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
800 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
801 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
802 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
803 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
804 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
805 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
806 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
807 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
808 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
809 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
810 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
811 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
812 #define QLCNIC_C2H_OPCODE_LAST 142
813
814 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
815 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
816 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
817
818 #define QLCNIC_LRO_REQUEST_CLEANUP 4
819
820 /* Capabilites received */
821 #define QLCNIC_FW_CAPABILITY_BDG (1 << 8)
822 #define QLCNIC_FW_CAPABILITY_FVLANTX (1 << 9)
823 #define QLCNIC_FW_CAPABILITY_HW_LRO (1 << 10)
824
825 /* module types */
826 #define LINKEVENT_MODULE_NOT_PRESENT 1
827 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
828 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
829 #define LINKEVENT_MODULE_OPTICAL_LRM 4
830 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
831 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
832 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
833 #define LINKEVENT_MODULE_TWINAX 8
834
835 #define LINKSPEED_10GBPS 10000
836 #define LINKSPEED_1GBPS 1000
837 #define LINKSPEED_100MBPS 100
838 #define LINKSPEED_10MBPS 10
839
840 #define LINKSPEED_ENCODED_10MBPS 0
841 #define LINKSPEED_ENCODED_100MBPS 1
842 #define LINKSPEED_ENCODED_1GBPS 2
843
844 #define LINKEVENT_AUTONEG_DISABLED 0
845 #define LINKEVENT_AUTONEG_ENABLED 1
846
847 #define LINKEVENT_HALF_DUPLEX 0
848 #define LINKEVENT_FULL_DUPLEX 1
849
850 #define LINKEVENT_LINKSPEED_MBPS 0
851 #define LINKEVENT_LINKSPEED_ENCODED 1
852
853 #define AUTO_FW_RESET_ENABLED 0x01
854 /* firmware response header:
855 * 63:58 - message type
856 * 57:56 - owner
857 * 55:53 - desc count
858 * 52:48 - reserved
859 * 47:40 - completion id
860 * 39:32 - opcode
861 * 31:16 - error code
862 * 15:00 - reserved
863 */
864 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
865 ((msg_hdr >> 32) & 0xFF)
866
867 struct qlcnic_fw_msg {
868 union {
869 struct {
870 u64 hdr;
871 u64 body[7];
872 };
873 u64 words[8];
874 };
875 };
876
877 struct qlcnic_nic_req {
878 __le64 qhdr;
879 __le64 req_hdr;
880 __le64 words[6];
881 };
882
883 struct qlcnic_mac_req {
884 u8 op;
885 u8 tag;
886 u8 mac_addr[6];
887 };
888
889 #define QLCNIC_MSI_ENABLED 0x02
890 #define QLCNIC_MSIX_ENABLED 0x04
891 #define QLCNIC_LRO_ENABLED 0x08
892 #define QLCNIC_BRIDGE_ENABLED 0X10
893 #define QLCNIC_DIAG_ENABLED 0x20
894 #define QLCNIC_ESWITCH_ENABLED 0x40
895 #define QLCNIC_IS_MSI_FAMILY(adapter) \
896 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
897
898 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
899 #define QLCNIC_MSIX_TBL_SPACE 8192
900 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
901 #define QLCNIC_MSIX_TBL_PGSIZE 4096
902
903 #define QLCNIC_NETDEV_WEIGHT 128
904 #define QLCNIC_ADAPTER_UP_MAGIC 777
905
906 #define __QLCNIC_FW_ATTACHED 0
907 #define __QLCNIC_DEV_UP 1
908 #define __QLCNIC_RESETTING 2
909 #define __QLCNIC_START_FW 4
910
911 #define QLCNIC_INTERRUPT_TEST 1
912 #define QLCNIC_LOOPBACK_TEST 2
913
914 struct qlcnic_adapter {
915 struct qlcnic_hardware_context ahw;
916
917 struct net_device *netdev;
918 struct pci_dev *pdev;
919 struct list_head mac_list;
920
921 spinlock_t tx_clean_lock;
922
923 u16 num_txd;
924 u16 num_rxd;
925 u16 num_jumbo_rxd;
926
927 u8 max_rds_rings;
928 u8 max_sds_rings;
929 u8 driver_mismatch;
930 u8 msix_supported;
931 u8 rx_csum;
932 u8 portnum;
933 u8 physical_port;
934
935 u8 mc_enabled;
936 u8 max_mc_count;
937 u8 rss_supported;
938 u8 fw_wait_cnt;
939 u8 fw_fail_cnt;
940 u8 tx_timeo_cnt;
941 u8 need_fw_reset;
942
943 u8 has_link_events;
944 u8 fw_type;
945 u16 tx_context_id;
946 u16 mtu;
947 u16 is_up;
948
949 u16 link_speed;
950 u16 link_duplex;
951 u16 link_autoneg;
952 u16 module_type;
953
954 u16 op_mode;
955 u16 switch_mode;
956 u16 max_tx_ques;
957 u16 max_rx_ques;
958 u16 min_tx_bw;
959 u16 max_tx_bw;
960 u16 max_mtu;
961
962 u32 fw_hal_version;
963 u32 capabilities;
964 u32 flags;
965 u32 irq;
966 u32 temp;
967
968 u32 int_vec_bit;
969 u32 heartbit;
970
971 u8 max_mac_filters;
972 u8 dev_state;
973 u8 diag_test;
974 u8 diag_cnt;
975 u8 reset_ack_timeo;
976 u8 dev_init_timeo;
977 u16 msg_enable;
978
979 u8 mac_addr[ETH_ALEN];
980
981 u64 dev_rst_time;
982
983 struct qlcnic_pci_info *npars;
984 struct qlcnic_eswitch *eswitch;
985 struct qlcnic_nic_template *nic_ops;
986
987 struct qlcnic_adapter_stats stats;
988
989 struct qlcnic_recv_context recv_ctx;
990 struct qlcnic_host_tx_ring *tx_ring;
991
992 void __iomem *tgt_mask_reg;
993 void __iomem *tgt_status_reg;
994 void __iomem *crb_int_state_reg;
995 void __iomem *isr_int_vec;
996
997 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
998
999 struct delayed_work fw_work;
1000
1001 struct work_struct tx_timeout_task;
1002
1003 struct qlcnic_nic_intr_coalesce coal;
1004
1005 unsigned long state;
1006 __le32 file_prd_off; /*File fw product offset*/
1007 u32 fw_version;
1008 const struct firmware *fw;
1009 };
1010
1011 struct qlcnic_info {
1012 __le16 pci_func;
1013 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1014 __le16 phys_port;
1015 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1016
1017 __le32 capabilities;
1018 u8 max_mac_filters;
1019 u8 reserved1;
1020 __le16 max_mtu;
1021
1022 __le16 max_tx_ques;
1023 __le16 max_rx_ques;
1024 __le16 min_tx_bw;
1025 __le16 max_tx_bw;
1026 u8 reserved2[104];
1027 };
1028
1029 struct qlcnic_pci_info {
1030 __le16 id; /* pci function id */
1031 __le16 active; /* 1 = Enabled */
1032 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1033 __le16 default_port; /* default port number */
1034
1035 __le16 tx_min_bw; /* Multiple of 100mbpc */
1036 __le16 tx_max_bw;
1037 __le16 reserved1[2];
1038
1039 u8 mac[ETH_ALEN];
1040 u8 reserved2[106];
1041 };
1042
1043 struct qlcnic_eswitch {
1044 u8 port;
1045 u8 active_vports;
1046 u8 active_vlans;
1047 u8 active_ucast_filters;
1048 u8 max_ucast_filters;
1049 u8 max_active_vlans;
1050
1051 u32 flags;
1052 #define QLCNIC_SWITCH_ENABLE BIT_1
1053 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1054 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1055 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1056 };
1057
1058 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1059 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1060
1061 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1062 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1063 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1064 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1065 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1066 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1067
1068 #define ADDR_IN_RANGE(addr, low, high) \
1069 (((addr) < (high)) && ((addr) >= (low)))
1070
1071 #define QLCRD32(adapter, off) \
1072 (qlcnic_hw_read_wx_2M(adapter, off))
1073 #define QLCWR32(adapter, off, val) \
1074 (qlcnic_hw_write_wx_2M(adapter, off, val))
1075
1076 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1077 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1078
1079 #define qlcnic_rom_lock(a) \
1080 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1081 #define qlcnic_rom_unlock(a) \
1082 qlcnic_pcie_sem_unlock((a), 2)
1083 #define qlcnic_phy_lock(a) \
1084 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1085 #define qlcnic_phy_unlock(a) \
1086 qlcnic_pcie_sem_unlock((a), 3)
1087 #define qlcnic_api_lock(a) \
1088 qlcnic_pcie_sem_lock((a), 5, 0)
1089 #define qlcnic_api_unlock(a) \
1090 qlcnic_pcie_sem_unlock((a), 5)
1091 #define qlcnic_sw_lock(a) \
1092 qlcnic_pcie_sem_lock((a), 6, 0)
1093 #define qlcnic_sw_unlock(a) \
1094 qlcnic_pcie_sem_unlock((a), 6)
1095 #define crb_win_lock(a) \
1096 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1097 #define crb_win_unlock(a) \
1098 qlcnic_pcie_sem_unlock((a), 7)
1099
1100 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1101 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1102 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1103
1104 /* Functions from qlcnic_init.c */
1105 int qlcnic_phantom_init(struct qlcnic_adapter *adapter);
1106 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1107 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1108 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1109 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1110 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1111 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1112
1113 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1114 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1115 u8 *bytes, size_t size);
1116 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1117 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1118
1119 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1120
1121 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1122 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1123
1124 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1125 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1126
1127 int qlcnic_init_firmware(struct qlcnic_adapter *adapter);
1128 void qlcnic_watchdog_task(struct work_struct *work);
1129 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1130 struct qlcnic_host_rds_ring *rds_ring);
1131 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1132 void qlcnic_set_multi(struct net_device *netdev);
1133 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1134 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1135 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1136 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1137 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd);
1138 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1139 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1140
1141 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1142 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1143 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1144 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1145 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1146 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1147 struct qlcnic_host_tx_ring *tx_ring);
1148 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u8 *mac);
1149 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter);
1150 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter);
1151 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1152
1153 /* Functions from qlcnic_main.c */
1154 int qlcnic_reset_context(struct qlcnic_adapter *);
1155 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1156 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1157 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1158 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1159 int qlcnic_check_loopback_buff(unsigned char *data);
1160 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1161 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1162
1163 /* Management functions */
1164 int qlcnic_set_mac_address(struct qlcnic_adapter *, u8*);
1165 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1166 int qlcnic_get_nic_info(struct qlcnic_adapter *, u8);
1167 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1168 int qlcnic_get_pci_info(struct qlcnic_adapter *);
1169 int qlcnic_reset_partition(struct qlcnic_adapter *, u8);
1170
1171 /* eSwitch management functions */
1172 int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *, u8,
1173 struct qlcnic_eswitch *);
1174 int qlcnic_get_eswitch_status(struct qlcnic_adapter *, u8,
1175 struct qlcnic_eswitch *);
1176 int qlcnic_toggle_eswitch(struct qlcnic_adapter *, u8, u8);
1177 int qlcnic_config_switch_port(struct qlcnic_adapter *, u8, int, u8, u8,
1178 u8, u8, u16);
1179 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1180 extern int qlcnic_config_tso;
1181
1182 /*
1183 * QLOGIC Board information
1184 */
1185
1186 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1187 struct qlcnic_brdinfo {
1188 unsigned short vendor;
1189 unsigned short device;
1190 unsigned short sub_vendor;
1191 unsigned short sub_device;
1192 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1193 };
1194
1195 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1196 {0x1077, 0x8020, 0x1077, 0x203,
1197 "8200 Series Single Port 10GbE Converged Network Adapter "
1198 "(TCP/IP Networking)"},
1199 {0x1077, 0x8020, 0x1077, 0x207,
1200 "8200 Series Dual Port 10GbE Converged Network Adapter "
1201 "(TCP/IP Networking)"},
1202 {0x1077, 0x8020, 0x1077, 0x20b,
1203 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1204 {0x1077, 0x8020, 0x1077, 0x20c,
1205 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1206 {0x1077, 0x8020, 0x1077, 0x20f,
1207 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1208 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1209 };
1210
1211 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1212
1213 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1214 {
1215 smp_mb();
1216 if (tx_ring->producer < tx_ring->sw_consumer)
1217 return tx_ring->sw_consumer - tx_ring->producer;
1218 else
1219 return tx_ring->sw_consumer + tx_ring->num_desc -
1220 tx_ring->producer;
1221 }
1222
1223 extern const struct ethtool_ops qlcnic_ethtool_ops;
1224
1225 struct qlcnic_nic_template {
1226 int (*get_mac_addr) (struct qlcnic_adapter *, u8*);
1227 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1228 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1229 int (*set_ilb_mode) (struct qlcnic_adapter *);
1230 void (*clear_ilb_mode) (struct qlcnic_adapter *);
1231 int (*start_firmware) (struct qlcnic_adapter *);
1232 };
1233
1234 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1235 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1236 printk(KERN_INFO "%s: %s: " _fmt, \
1237 dev_name(&adapter->pdev->dev), \
1238 __func__, ##_args); \
1239 } while (0)
1240
1241 #endif /* __QLCNIC_H_ */
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