2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qlge for copyright and licensing details.
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
14 * General definitions...
16 #define DRV_NAME "qlge"
17 #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
18 #define DRV_VERSION "v1.00.00-b3"
21 #define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
23 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
26 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
27 "%s: " fmt, __func__, ##args); \
30 #define QLGE_VENDOR_ID 0x1077
31 #define QLGE_DEVICE_ID1 0x8012
32 #define QLGE_DEVICE_ID 0x8000
34 #define MAX_RX_RINGS 128
35 #define MAX_TX_RINGS 128
37 #define NUM_TX_RING_ENTRIES 256
38 #define NUM_RX_RING_ENTRIES 256
40 #define NUM_SMALL_BUFFERS 512
41 #define NUM_LARGE_BUFFERS 512
43 #define SMALL_BUFFER_SIZE 256
44 #define LARGE_BUFFER_SIZE PAGE_SIZE
45 #define MAX_SPLIT_SIZE 1023
46 #define QLGE_SB_PAD 32
48 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
49 #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
50 #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
51 #define UDELAY_COUNT 3
52 #define UDELAY_DELAY 10
55 #define TX_DESC_PER_IOCB 8
56 /* The maximum number of frags we handle is based
59 #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
60 #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
61 #else /* all other page sizes */
62 #define TX_DESC_PER_OAL 0
65 #define DB_PAGE_SIZE 4096
68 * Processor Address Register (PROC_ADDR) bit definitions.
75 PROC_ADDR_RDY
= (1 << 31),
76 PROC_ADDR_R
= (1 << 30),
77 PROC_ADDR_ERR
= (1 << 29),
78 PROC_ADDR_DA
= (1 << 28),
79 PROC_ADDR_FUNC0_MBI
= 0x00001180,
80 PROC_ADDR_FUNC0_MBO
= (PROC_ADDR_FUNC0_MBI
+ MAILBOX_COUNT
),
81 PROC_ADDR_FUNC0_CTL
= 0x000011a1,
82 PROC_ADDR_FUNC2_MBI
= 0x00001280,
83 PROC_ADDR_FUNC2_MBO
= (PROC_ADDR_FUNC2_MBI
+ MAILBOX_COUNT
),
84 PROC_ADDR_FUNC2_CTL
= 0x000012a1,
85 PROC_ADDR_MPI_RISC
= 0x00000000,
86 PROC_ADDR_MDE
= 0x00010000,
87 PROC_ADDR_REGBLOCK
= 0x00020000,
88 PROC_ADDR_RISC_REG
= 0x00030000,
92 * System Register (SYS) bit definitions.
101 SYS_OMP_DLY_MASK
= 0x3f000000,
103 * There are no values defined as of edit #15.
109 * Reset/Failover Register (RST_FO) bit definitions.
112 RST_FO_TFO
= (1 << 0),
113 RST_FO_RR_MASK
= 0x00060000,
114 RST_FO_RR_CQ_CAM
= 0x00000000,
115 RST_FO_RR_DROP
= 0x00000001,
116 RST_FO_RR_DQ
= 0x00000002,
117 RST_FO_RR_RCV_FUNC_CQ
= 0x00000003,
118 RST_FO_FRB
= (1 << 12),
119 RST_FO_MOP
= (1 << 13),
120 RST_FO_REG
= (1 << 14),
121 RST_FO_FR
= (1 << 15),
125 * Function Specific Control Register (FSC) bit definitions.
128 FSC_DBRST_MASK
= 0x00070000,
129 FSC_DBRST_256
= 0x00000000,
130 FSC_DBRST_512
= 0x00000001,
131 FSC_DBRST_768
= 0x00000002,
132 FSC_DBRST_1024
= 0x00000003,
133 FSC_DBL_MASK
= 0x00180000,
134 FSC_DBL_DBRST
= 0x00000000,
135 FSC_DBL_MAX_PLD
= 0x00000008,
136 FSC_DBL_MAX_BRST
= 0x00000010,
137 FSC_DBL_128_BYTES
= 0x00000018,
139 FSC_EPC_MASK
= 0x00c00000,
140 FSC_EPC_INBOUND
= (1 << 6),
141 FSC_EPC_OUTBOUND
= (1 << 7),
142 FSC_VM_PAGESIZE_MASK
= 0x07000000,
143 FSC_VM_PAGE_2K
= 0x00000100,
144 FSC_VM_PAGE_4K
= 0x00000200,
145 FSC_VM_PAGE_8K
= 0x00000300,
146 FSC_VM_PAGE_64K
= 0x00000600,
154 * Host Command Status Register (CSR) bit definitions.
157 CSR_ERR_STS_MASK
= 0x0000003f,
159 * There are no valued defined as of edit #15.
164 CSR_CMD_PARM_SHIFT
= 22,
165 CSR_CMD_NOP
= 0x00000000,
166 CSR_CMD_SET_RST
= 0x1000000,
167 CSR_CMD_CLR_RST
= 0x20000000,
168 CSR_CMD_SET_PAUSE
= 0x30000000,
169 CSR_CMD_CLR_PAUSE
= 0x40000000,
170 CSR_CMD_SET_H2R_INT
= 0x50000000,
171 CSR_CMD_CLR_H2R_INT
= 0x60000000,
172 CSR_CMD_PAR_EN
= 0x70000000,
173 CSR_CMD_SET_BAD_PAR
= 0x80000000,
174 CSR_CMD_CLR_BAD_PAR
= 0x90000000,
175 CSR_CMD_CLR_R2PCI_INT
= 0xa0000000,
179 * Configuration Register (CFG) bit definitions.
190 CFG_Q_MASK
= 0x7f000000,
194 * Status Register (STS) bit definitions.
203 STS_FUNC_ID_MASK
= 0x000000c0,
204 STS_FUNC_ID_SHIFT
= 6,
213 * Interrupt Enable Register (INTR_EN) bit definitions.
216 INTR_EN_INTR_MASK
= 0x007f0000,
217 INTR_EN_TYPE_MASK
= 0x03000000,
218 INTR_EN_TYPE_ENABLE
= 0x00000100,
219 INTR_EN_TYPE_DISABLE
= 0x00000200,
220 INTR_EN_TYPE_READ
= 0x00000300,
221 INTR_EN_IHD
= (1 << 13),
222 INTR_EN_IHD_MASK
= (INTR_EN_IHD
<< 16),
223 INTR_EN_EI
= (1 << 14),
224 INTR_EN_EN
= (1 << 15),
228 * Interrupt Mask Register (INTR_MASK) bit definitions.
231 INTR_MASK_PI
= (1 << 0),
232 INTR_MASK_HL0
= (1 << 1),
233 INTR_MASK_LH0
= (1 << 2),
234 INTR_MASK_HL1
= (1 << 3),
235 INTR_MASK_LH1
= (1 << 4),
236 INTR_MASK_SE
= (1 << 5),
237 INTR_MASK_LSC
= (1 << 6),
238 INTR_MASK_MC
= (1 << 7),
239 INTR_MASK_LINK_IRQS
= INTR_MASK_LSC
| INTR_MASK_SE
| INTR_MASK_MC
,
243 * Register (REV_ID) bit definitions.
246 REV_ID_MASK
= 0x0000000f,
247 REV_ID_NICROLL_SHIFT
= 0,
248 REV_ID_NICREV_SHIFT
= 4,
249 REV_ID_XGROLL_SHIFT
= 8,
250 REV_ID_XGREV_SHIFT
= 12,
251 REV_ID_CHIPREV_SHIFT
= 28,
255 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
258 FRC_ECC_ERR_VW
= (1 << 12),
259 FRC_ECC_ERR_VB
= (1 << 13),
260 FRC_ECC_ERR_NI
= (1 << 14),
261 FRC_ECC_ERR_NO
= (1 << 15),
262 FRC_ECC_PFE_SHIFT
= 16,
263 FRC_ECC_ERR_DO
= (1 << 18),
264 FRC_ECC_P14
= (1 << 19),
268 * Error Status Register (ERR_STS) bit definitions.
271 ERR_STS_NOF
= (1 << 0),
272 ERR_STS_NIF
= (1 << 1),
273 ERR_STS_DRP
= (1 << 2),
274 ERR_STS_XGP
= (1 << 3),
275 ERR_STS_FOU
= (1 << 4),
276 ERR_STS_FOC
= (1 << 5),
277 ERR_STS_FOF
= (1 << 6),
278 ERR_STS_FIU
= (1 << 7),
279 ERR_STS_FIC
= (1 << 8),
280 ERR_STS_FIF
= (1 << 9),
281 ERR_STS_MOF
= (1 << 10),
282 ERR_STS_TA
= (1 << 11),
283 ERR_STS_MA
= (1 << 12),
284 ERR_STS_MPE
= (1 << 13),
285 ERR_STS_SCE
= (1 << 14),
286 ERR_STS_STE
= (1 << 15),
287 ERR_STS_FOW
= (1 << 16),
288 ERR_STS_UE
= (1 << 17),
289 ERR_STS_MCH
= (1 << 26),
290 ERR_STS_LOC_SHIFT
= 27,
294 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
297 RAM_DBG_ADDR_FW
= (1 << 30),
298 RAM_DBG_ADDR_FR
= (1 << 31),
302 * Semaphore Register (SEM) bit definitions.
307 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
312 SEM_XGMAC0_SHIFT
= 0,
313 SEM_XGMAC1_SHIFT
= 2,
315 SEM_MAC_ADDR_SHIFT
= 6,
317 SEM_PROBE_SHIFT
= 10,
318 SEM_RT_IDX_SHIFT
= 12,
319 SEM_PROC_REG_SHIFT
= 14,
320 SEM_XGMAC0_MASK
= 0x00030000,
321 SEM_XGMAC1_MASK
= 0x000c0000,
322 SEM_ICB_MASK
= 0x00300000,
323 SEM_MAC_ADDR_MASK
= 0x00c00000,
324 SEM_FLASH_MASK
= 0x03000000,
325 SEM_PROBE_MASK
= 0x0c000000,
326 SEM_RT_IDX_MASK
= 0x30000000,
327 SEM_PROC_REG_MASK
= 0xc0000000,
331 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
334 XGMAC_ADDR_RDY
= (1 << 31),
335 XGMAC_ADDR_R
= (1 << 30),
336 XGMAC_ADDR_XME
= (1 << 29),
338 /* XGMAC control registers */
339 PAUSE_SRC_LO
= 0x00000100,
340 PAUSE_SRC_HI
= 0x00000104,
341 GLOBAL_CFG
= 0x00000108,
342 GLOBAL_CFG_RESET
= (1 << 0),
343 GLOBAL_CFG_JUMBO
= (1 << 6),
344 GLOBAL_CFG_TX_STAT_EN
= (1 << 10),
345 GLOBAL_CFG_RX_STAT_EN
= (1 << 11),
347 TX_CFG_RESET
= (1 << 0),
348 TX_CFG_EN
= (1 << 1),
349 TX_CFG_PREAM
= (1 << 2),
351 RX_CFG_RESET
= (1 << 0),
352 RX_CFG_EN
= (1 << 1),
353 RX_CFG_PREAM
= (1 << 2),
354 FLOW_CTL
= 0x0000011c,
355 PAUSE_OPCODE
= 0x00000120,
356 PAUSE_TIMER
= 0x00000124,
357 PAUSE_FRM_DEST_LO
= 0x00000128,
358 PAUSE_FRM_DEST_HI
= 0x0000012c,
359 MAC_TX_PARAMS
= 0x00000134,
360 MAC_TX_PARAMS_JUMBO
= (1 << 31),
361 MAC_TX_PARAMS_SIZE_SHIFT
= 16,
362 MAC_RX_PARAMS
= 0x00000138,
363 MAC_SYS_INT
= 0x00000144,
364 MAC_SYS_INT_MASK
= 0x00000148,
365 MAC_MGMT_INT
= 0x0000014c,
366 MAC_MGMT_IN_MASK
= 0x00000150,
367 EXT_ARB_MODE
= 0x000001fc,
369 /* XGMAC TX statistics registers */
370 TX_PKTS
= 0x00000200,
371 TX_BYTES
= 0x00000208,
372 TX_MCAST_PKTS
= 0x00000210,
373 TX_BCAST_PKTS
= 0x00000218,
374 TX_UCAST_PKTS
= 0x00000220,
375 TX_CTL_PKTS
= 0x00000228,
376 TX_PAUSE_PKTS
= 0x00000230,
377 TX_64_PKT
= 0x00000238,
378 TX_65_TO_127_PKT
= 0x00000240,
379 TX_128_TO_255_PKT
= 0x00000248,
380 TX_256_511_PKT
= 0x00000250,
381 TX_512_TO_1023_PKT
= 0x00000258,
382 TX_1024_TO_1518_PKT
= 0x00000260,
383 TX_1519_TO_MAX_PKT
= 0x00000268,
384 TX_UNDERSIZE_PKT
= 0x00000270,
385 TX_OVERSIZE_PKT
= 0x00000278,
387 /* XGMAC statistics control registers */
388 RX_HALF_FULL_DET
= 0x000002a0,
389 TX_HALF_FULL_DET
= 0x000002a4,
390 RX_OVERFLOW_DET
= 0x000002a8,
391 TX_OVERFLOW_DET
= 0x000002ac,
392 RX_HALF_FULL_MASK
= 0x000002b0,
393 TX_HALF_FULL_MASK
= 0x000002b4,
394 RX_OVERFLOW_MASK
= 0x000002b8,
395 TX_OVERFLOW_MASK
= 0x000002bc,
396 STAT_CNT_CTL
= 0x000002c0,
397 STAT_CNT_CTL_CLEAR_TX
= (1 << 0),
398 STAT_CNT_CTL_CLEAR_RX
= (1 << 1),
399 AUX_RX_HALF_FULL_DET
= 0x000002d0,
400 AUX_TX_HALF_FULL_DET
= 0x000002d4,
401 AUX_RX_OVERFLOW_DET
= 0x000002d8,
402 AUX_TX_OVERFLOW_DET
= 0x000002dc,
403 AUX_RX_HALF_FULL_MASK
= 0x000002f0,
404 AUX_TX_HALF_FULL_MASK
= 0x000002f4,
405 AUX_RX_OVERFLOW_MASK
= 0x000002f8,
406 AUX_TX_OVERFLOW_MASK
= 0x000002fc,
408 /* XGMAC RX statistics registers */
409 RX_BYTES
= 0x00000300,
410 RX_BYTES_OK
= 0x00000308,
411 RX_PKTS
= 0x00000310,
412 RX_PKTS_OK
= 0x00000318,
413 RX_BCAST_PKTS
= 0x00000320,
414 RX_MCAST_PKTS
= 0x00000328,
415 RX_UCAST_PKTS
= 0x00000330,
416 RX_UNDERSIZE_PKTS
= 0x00000338,
417 RX_OVERSIZE_PKTS
= 0x00000340,
418 RX_JABBER_PKTS
= 0x00000348,
419 RX_UNDERSIZE_FCERR_PKTS
= 0x00000350,
420 RX_DROP_EVENTS
= 0x00000358,
421 RX_FCERR_PKTS
= 0x00000360,
422 RX_ALIGN_ERR
= 0x00000368,
423 RX_SYMBOL_ERR
= 0x00000370,
424 RX_MAC_ERR
= 0x00000378,
425 RX_CTL_PKTS
= 0x00000380,
426 RX_PAUSE_PKTS
= 0x00000384,
427 RX_64_PKTS
= 0x00000390,
428 RX_65_TO_127_PKTS
= 0x00000398,
429 RX_128_255_PKTS
= 0x000003a0,
430 RX_256_511_PKTS
= 0x000003a8,
431 RX_512_TO_1023_PKTS
= 0x000003b0,
432 RX_1024_TO_1518_PKTS
= 0x000003b8,
433 RX_1519_TO_MAX_PKTS
= 0x000003c0,
434 RX_LEN_ERR_PKTS
= 0x000003c8,
436 /* XGMAC MDIO control registers */
437 MDIO_TX_DATA
= 0x00000400,
438 MDIO_RX_DATA
= 0x00000410,
439 MDIO_CMD
= 0x00000420,
440 MDIO_PHY_ADDR
= 0x00000430,
441 MDIO_PORT
= 0x00000440,
442 MDIO_STATUS
= 0x00000450,
444 /* XGMAC AUX statistics registers */
448 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
451 ETS_QUEUE_SHIFT
= 29,
455 ETS_FC_COS_SHIFT
= 23,
459 * Flash Address Register (FLASH_ADDR) bit definitions.
462 FLASH_ADDR_RDY
= (1 << 31),
463 FLASH_ADDR_R
= (1 << 30),
464 FLASH_ADDR_ERR
= (1 << 29),
468 * Stop CQ Processing Register (CQ_STOP) bit definitions.
471 CQ_STOP_QUEUE_MASK
= (0x007f0000),
472 CQ_STOP_TYPE_MASK
= (0x03000000),
473 CQ_STOP_TYPE_START
= 0x00000100,
474 CQ_STOP_TYPE_STOP
= 0x00000200,
475 CQ_STOP_TYPE_READ
= 0x00000300,
476 CQ_STOP_EN
= (1 << 15),
480 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
483 MAC_ADDR_IDX_SHIFT
= 4,
484 MAC_ADDR_TYPE_SHIFT
= 16,
485 MAC_ADDR_TYPE_MASK
= 0x000f0000,
486 MAC_ADDR_TYPE_CAM_MAC
= 0x00000000,
487 MAC_ADDR_TYPE_MULTI_MAC
= 0x00010000,
488 MAC_ADDR_TYPE_VLAN
= 0x00020000,
489 MAC_ADDR_TYPE_MULTI_FLTR
= 0x00030000,
490 MAC_ADDR_TYPE_FC_MAC
= 0x00040000,
491 MAC_ADDR_TYPE_MGMT_MAC
= 0x00050000,
492 MAC_ADDR_TYPE_MGMT_VLAN
= 0x00060000,
493 MAC_ADDR_TYPE_MGMT_V4
= 0x00070000,
494 MAC_ADDR_TYPE_MGMT_V6
= 0x00080000,
495 MAC_ADDR_TYPE_MGMT_TU_DP
= 0x00090000,
496 MAC_ADDR_ADR
= (1 << 25),
497 MAC_ADDR_RS
= (1 << 26),
498 MAC_ADDR_E
= (1 << 27),
499 MAC_ADDR_MR
= (1 << 30),
500 MAC_ADDR_MW
= (1 << 31),
501 MAX_MULTICAST_ENTRIES
= 32,
505 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
508 SPLT_HDR_EP
= (1 << 31),
512 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
515 FC_RCV_CFG_ECT
= (1 << 15),
516 FC_RCV_CFG_DFH
= (1 << 20),
517 FC_RCV_CFG_DVF
= (1 << 21),
518 FC_RCV_CFG_RCE
= (1 << 27),
519 FC_RCV_CFG_RFE
= (1 << 28),
520 FC_RCV_CFG_TEE
= (1 << 29),
521 FC_RCV_CFG_TCE
= (1 << 30),
522 FC_RCV_CFG_TFE
= (1 << 31),
526 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
529 NIC_RCV_CFG_PPE
= (1 << 0),
530 NIC_RCV_CFG_VLAN_MASK
= 0x00060000,
531 NIC_RCV_CFG_VLAN_ALL
= 0x00000000,
532 NIC_RCV_CFG_VLAN_MATCH_ONLY
= 0x00000002,
533 NIC_RCV_CFG_VLAN_MATCH_AND_NON
= 0x00000004,
534 NIC_RCV_CFG_VLAN_NONE_AND_NON
= 0x00000006,
535 NIC_RCV_CFG_RV
= (1 << 3),
536 NIC_RCV_CFG_DFQ_MASK
= (0x7f000000),
537 NIC_RCV_CFG_DFQ_SHIFT
= 8,
538 NIC_RCV_CFG_DFQ
= 0, /* HARDCODE default queue to 0. */
542 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
545 MGMT_RCV_CFG_ARP
= (1 << 0),
546 MGMT_RCV_CFG_DHC
= (1 << 1),
547 MGMT_RCV_CFG_DHS
= (1 << 2),
548 MGMT_RCV_CFG_NP
= (1 << 3),
549 MGMT_RCV_CFG_I6N
= (1 << 4),
550 MGMT_RCV_CFG_I6R
= (1 << 5),
551 MGMT_RCV_CFG_DH6
= (1 << 6),
552 MGMT_RCV_CFG_UD1
= (1 << 7),
553 MGMT_RCV_CFG_UD0
= (1 << 8),
554 MGMT_RCV_CFG_BCT
= (1 << 9),
555 MGMT_RCV_CFG_MCT
= (1 << 10),
556 MGMT_RCV_CFG_DM
= (1 << 11),
557 MGMT_RCV_CFG_RM
= (1 << 12),
558 MGMT_RCV_CFG_STL
= (1 << 13),
559 MGMT_RCV_CFG_VLAN_MASK
= 0xc0000000,
560 MGMT_RCV_CFG_VLAN_ALL
= 0x00000000,
561 MGMT_RCV_CFG_VLAN_MATCH_ONLY
= 0x00004000,
562 MGMT_RCV_CFG_VLAN_MATCH_AND_NON
= 0x00008000,
563 MGMT_RCV_CFG_VLAN_NONE_AND_NON
= 0x0000c000,
567 * Routing Index Register (RT_IDX) bit definitions.
570 RT_IDX_IDX_SHIFT
= 8,
571 RT_IDX_TYPE_MASK
= 0x000f0000,
572 RT_IDX_TYPE_RT
= 0x00000000,
573 RT_IDX_TYPE_RT_INV
= 0x00010000,
574 RT_IDX_TYPE_NICQ
= 0x00020000,
575 RT_IDX_TYPE_NICQ_INV
= 0x00030000,
576 RT_IDX_DST_MASK
= 0x00700000,
577 RT_IDX_DST_RSS
= 0x00000000,
578 RT_IDX_DST_CAM_Q
= 0x00100000,
579 RT_IDX_DST_COS_Q
= 0x00200000,
580 RT_IDX_DST_DFLT_Q
= 0x00300000,
581 RT_IDX_DST_DEST_Q
= 0x00400000,
582 RT_IDX_RS
= (1 << 26),
583 RT_IDX_E
= (1 << 27),
584 RT_IDX_MR
= (1 << 30),
585 RT_IDX_MW
= (1 << 31),
587 /* Nic Queue format - type 2 bits */
588 RT_IDX_BCAST
= (1 << 0),
589 RT_IDX_MCAST
= (1 << 1),
590 RT_IDX_MCAST_MATCH
= (1 << 2),
591 RT_IDX_MCAST_REG_MATCH
= (1 << 3),
592 RT_IDX_MCAST_HASH_MATCH
= (1 << 4),
593 RT_IDX_FC_MACH
= (1 << 5),
594 RT_IDX_ETH_FCOE
= (1 << 6),
595 RT_IDX_CAM_HIT
= (1 << 7),
596 RT_IDX_CAM_BIT0
= (1 << 8),
597 RT_IDX_CAM_BIT1
= (1 << 9),
598 RT_IDX_VLAN_TAG
= (1 << 10),
599 RT_IDX_VLAN_MATCH
= (1 << 11),
600 RT_IDX_VLAN_FILTER
= (1 << 12),
601 RT_IDX_ETH_SKIP1
= (1 << 13),
602 RT_IDX_ETH_SKIP2
= (1 << 14),
603 RT_IDX_BCAST_MCAST_MATCH
= (1 << 15),
604 RT_IDX_802_3
= (1 << 16),
605 RT_IDX_LLDP
= (1 << 17),
606 RT_IDX_UNUSED018
= (1 << 18),
607 RT_IDX_UNUSED019
= (1 << 19),
608 RT_IDX_UNUSED20
= (1 << 20),
609 RT_IDX_UNUSED21
= (1 << 21),
610 RT_IDX_ERR
= (1 << 22),
611 RT_IDX_VALID
= (1 << 23),
612 RT_IDX_TU_CSUM_ERR
= (1 << 24),
613 RT_IDX_IP_CSUM_ERR
= (1 << 25),
614 RT_IDX_MAC_ERR
= (1 << 26),
615 RT_IDX_RSS_TCP6
= (1 << 27),
616 RT_IDX_RSS_TCP4
= (1 << 28),
617 RT_IDX_RSS_IPV6
= (1 << 29),
618 RT_IDX_RSS_IPV4
= (1 << 30),
619 RT_IDX_RSS_MATCH
= (1 << 31),
621 /* Hierarchy for the NIC Queue Mask */
622 RT_IDX_ALL_ERR_SLOT
= 0,
623 RT_IDX_MAC_ERR_SLOT
= 0,
624 RT_IDX_IP_CSUM_ERR_SLOT
= 1,
625 RT_IDX_TCP_UDP_CSUM_ERR_SLOT
= 2,
626 RT_IDX_BCAST_SLOT
= 3,
627 RT_IDX_MCAST_MATCH_SLOT
= 4,
628 RT_IDX_ALLMULTI_SLOT
= 5,
629 RT_IDX_UNUSED6_SLOT
= 6,
630 RT_IDX_UNUSED7_SLOT
= 7,
631 RT_IDX_RSS_MATCH_SLOT
= 8,
632 RT_IDX_RSS_IPV4_SLOT
= 8,
633 RT_IDX_RSS_IPV6_SLOT
= 9,
634 RT_IDX_RSS_TCP4_SLOT
= 10,
635 RT_IDX_RSS_TCP6_SLOT
= 11,
636 RT_IDX_CAM_HIT_SLOT
= 12,
637 RT_IDX_UNUSED013
= 13,
638 RT_IDX_UNUSED014
= 14,
639 RT_IDX_PROMISCUOUS_SLOT
= 15,
640 RT_IDX_MAX_SLOTS
= 16,
644 * Control Register Set Map
647 PROC_ADDR
= 0, /* Use semaphore */
648 PROC_DATA
= 0x04, /* Use semaphore */
654 ICB_RID
= 0x1c, /* Use semaphore */
655 ICB_L
= 0x20, /* Use semaphore */
656 ICB_H
= 0x24, /* Use semaphore */
673 GPIO_1
= 0x68, /* Use semaphore */
674 GPIO_2
= 0x6c, /* Use semaphore */
675 GPIO_3
= 0x70, /* Use semaphore */
677 XGMAC_ADDR
= 0x78, /* Use semaphore */
678 XGMAC_DATA
= 0x7c, /* Use semaphore */
681 FLASH_ADDR
= 0x88, /* Use semaphore */
682 FLASH_DATA
= 0x8c, /* Use semaphore */
685 WQ_PAGE_TBL_LO
= 0x98,
686 WQ_PAGE_TBL_HI
= 0x9c,
687 CQ_PAGE_TBL_LO
= 0xa0,
688 CQ_PAGE_TBL_HI
= 0xa4,
689 MAC_ADDR_IDX
= 0xa8, /* Use semaphore */
690 MAC_ADDR_DATA
= 0xac, /* Use semaphore */
696 FC_PAUSE_THRES
= 0xc4,
697 NIC_PAUSE_THRES
= 0xc8,
707 XG_SERDES_ADDR
= 0xf0,
708 XG_SERDES_DATA
= 0xf4,
709 PRB_MX_ADDR
= 0xf8, /* Use semaphore */
710 PRB_MX_DATA
= 0xfc, /* Use semaphore */
717 CAM_OUT_ROUTE_FC
= 0,
718 CAM_OUT_ROUTE_NIC
= 1,
719 CAM_OUT_FUNC_SHIFT
= 2,
720 CAM_OUT_RV
= (1 << 4),
721 CAM_OUT_SH
= (1 << 15),
722 CAM_OUT_CQ_ID_SHIFT
= 5,
726 * Mailbox definitions
729 /* Asynchronous Event Notifications */
730 AEN_SYS_ERR
= 0x00008002,
731 AEN_LINK_UP
= 0x00008011,
732 AEN_LINK_DOWN
= 0x00008012,
733 AEN_IDC_CMPLT
= 0x00008100,
734 AEN_IDC_REQ
= 0x00008101,
735 AEN_FW_INIT_DONE
= 0x00008400,
736 AEN_FW_INIT_FAIL
= 0x00008401,
738 /* Mailbox Command Opcodes. */
739 MB_CMD_NOP
= 0x00000000,
740 MB_CMD_EX_FW
= 0x00000002,
741 MB_CMD_MB_TEST
= 0x00000006,
742 MB_CMD_CSUM_TEST
= 0x00000007, /* Verify Checksum */
743 MB_CMD_ABOUT_FW
= 0x00000008,
744 MB_CMD_LOAD_RISC_RAM
= 0x0000000b,
745 MB_CMD_DUMP_RISC_RAM
= 0x0000000c,
746 MB_CMD_WRITE_RAM
= 0x0000000d,
747 MB_CMD_READ_RAM
= 0x0000000f,
748 MB_CMD_STOP_FW
= 0x00000014,
749 MB_CMD_MAKE_SYS_ERR
= 0x0000002a,
750 MB_CMD_INIT_FW
= 0x00000060,
751 MB_CMD_GET_INIT_CB
= 0x00000061,
752 MB_CMD_GET_FW_STATE
= 0x00000069,
753 MB_CMD_IDC_REQ
= 0x00000100, /* Inter-Driver Communication */
754 MB_CMD_IDC_ACK
= 0x00000101, /* Inter-Driver Communication */
755 MB_CMD_SET_WOL_MODE
= 0x00000110, /* Wake On Lan */
756 MB_WOL_DISABLE
= 0x00000000,
757 MB_WOL_MAGIC_PKT
= 0x00000001,
758 MB_WOL_FLTR
= 0x00000002,
759 MB_WOL_UCAST
= 0x00000004,
760 MB_WOL_MCAST
= 0x00000008,
761 MB_WOL_BCAST
= 0x00000010,
762 MB_WOL_LINK_UP
= 0x00000020,
763 MB_WOL_LINK_DOWN
= 0x00000040,
764 MB_CMD_SET_WOL_FLTR
= 0x00000111, /* Wake On Lan Filter */
765 MB_CMD_CLEAR_WOL_FLTR
= 0x00000112, /* Wake On Lan Filter */
766 MB_CMD_SET_WOL_MAGIC
= 0x00000113, /* Wake On Lan Magic Packet */
767 MB_CMD_CLEAR_WOL_MAGIC
= 0x00000114, /* Wake On Lan Magic Packet */
768 MB_CMD_PORT_RESET
= 0x00000120,
769 MB_CMD_SET_PORT_CFG
= 0x00000122,
770 MB_CMD_GET_PORT_CFG
= 0x00000123,
771 MB_CMD_SET_ASIC_VOLTS
= 0x00000130,
772 MB_CMD_GET_SNS_DATA
= 0x00000131, /* Temp and Volt Sense data. */
774 /* Mailbox Command Status. */
775 MB_CMD_STS_GOOD
= 0x00004000, /* Success. */
776 MB_CMD_STS_INTRMDT
= 0x00001000, /* Intermediate Complete. */
777 MB_CMD_STS_ERR
= 0x00004005, /* Error. */
781 u32 mbox_in
[MAILBOX_COUNT
];
782 u32 mbox_out
[MAILBOX_COUNT
];
787 struct flash_params
{
799 * doorbell space for the rx ring context
801 struct rx_doorbell_context
{
802 u32 cnsmr_idx
; /* 0x00 */
803 u32 valid
; /* 0x04 */
804 u32 reserved
[4]; /* 0x08-0x14 */
805 u32 lbq_prod_idx
; /* 0x18 */
806 u32 sbq_prod_idx
; /* 0x1c */
810 * doorbell space for the tx ring context
812 struct tx_doorbell_context
{
813 u32 prod_idx
; /* 0x00 */
814 u32 valid
; /* 0x04 */
815 u32 reserved
[4]; /* 0x08-0x14 */
816 u32 lbq_prod_idx
; /* 0x18 */
817 u32 sbq_prod_idx
; /* 0x1c */
820 /* DATA STRUCTURES SHARED WITH HARDWARE. */
824 #define BQ_END 0x00000001
825 #define BQ_CONT 0x00000002
826 #define BQ_MASK 0x00000003
828 } __attribute((packed
));
833 #define TX_DESC_LEN_MASK 0x000fffff
834 #define TX_DESC_C 0x40000000
835 #define TX_DESC_E 0x80000000
836 } __attribute((packed
));
839 * IOCB Definitions...
842 #define OPCODE_OB_MAC_IOCB 0x01
843 #define OPCODE_OB_MAC_TSO_IOCB 0x02
844 #define OPCODE_IB_MAC_IOCB 0x20
845 #define OPCODE_IB_MPI_IOCB 0x21
846 #define OPCODE_IB_AE_IOCB 0x3f
848 struct ob_mac_iocb_req
{
851 #define OB_MAC_IOCB_REQ_OI 0x01
852 #define OB_MAC_IOCB_REQ_I 0x02
853 #define OB_MAC_IOCB_REQ_D 0x08
854 #define OB_MAC_IOCB_REQ_F 0x10
857 #define OB_MAC_IOCB_DFP 0x02
858 #define OB_MAC_IOCB_V 0x04
861 #define OB_MAC_IOCB_LEN_MASK 0x3ffff
868 struct tx_buf_desc tbd
[TX_DESC_PER_IOCB
];
869 } __attribute((packed
));
871 struct ob_mac_iocb_rsp
{
874 #define OB_MAC_IOCB_RSP_OI 0x01 /* */
875 #define OB_MAC_IOCB_RSP_I 0x02 /* */
876 #define OB_MAC_IOCB_RSP_E 0x08 /* */
877 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
878 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
879 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
882 #define OB_MAC_IOCB_RSP_B 0x80 /* */
886 } __attribute((packed
));
888 struct ob_mac_tso_iocb_req
{
891 #define OB_MAC_TSO_IOCB_OI 0x01
892 #define OB_MAC_TSO_IOCB_I 0x02
893 #define OB_MAC_TSO_IOCB_D 0x08
894 #define OB_MAC_TSO_IOCB_IP4 0x40
895 #define OB_MAC_TSO_IOCB_IP6 0x80
897 #define OB_MAC_TSO_IOCB_LSO 0x20
898 #define OB_MAC_TSO_IOCB_UC 0x40
899 #define OB_MAC_TSO_IOCB_TC 0x80
901 #define OB_MAC_TSO_IOCB_IC 0x01
902 #define OB_MAC_TSO_IOCB_DFP 0x02
903 #define OB_MAC_TSO_IOCB_V 0x04
908 __le16 total_hdrs_len
;
909 __le16 net_trans_offset
;
910 #define OB_MAC_TRANSPORT_HDR_SHIFT 6
913 struct tx_buf_desc tbd
[TX_DESC_PER_IOCB
];
914 } __attribute((packed
));
916 struct ob_mac_tso_iocb_rsp
{
919 #define OB_MAC_TSO_IOCB_RSP_OI 0x01
920 #define OB_MAC_TSO_IOCB_RSP_I 0x02
921 #define OB_MAC_TSO_IOCB_RSP_E 0x08
922 #define OB_MAC_TSO_IOCB_RSP_S 0x10
923 #define OB_MAC_TSO_IOCB_RSP_L 0x20
924 #define OB_MAC_TSO_IOCB_RSP_P 0x40
927 #define OB_MAC_TSO_IOCB_RSP_B 0x8000
930 __le32 reserved2
[13];
931 } __attribute((packed
));
933 struct ib_mac_iocb_rsp
{
934 u8 opcode
; /* 0x20 */
936 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
937 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
938 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
939 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
940 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
941 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
942 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
943 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
944 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
945 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
946 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
948 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
949 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
950 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
951 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
952 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
953 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
954 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
955 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
956 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
957 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
958 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
959 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
961 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
962 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
963 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
964 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
965 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
966 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
967 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
968 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
969 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
970 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
971 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
972 __le32 data_len
; /* */
973 __le32 data_addr_lo
; /* */
974 __le32 data_addr_hi
; /* */
976 __le16 vlan_id
; /* 12 bits */
977 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
978 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
983 #define IB_MAC_IOCB_RSP_HV 0x20000000 /* */
984 #define IB_MAC_IOCB_RSP_HS 0x40000000 /* */
985 #define IB_MAC_IOCB_RSP_HL 0x80000000 /* */
986 __le32 hdr_len
; /* */
987 __le32 hdr_addr_lo
; /* */
988 __le32 hdr_addr_hi
; /* */
989 } __attribute((packed
));
991 struct ib_ae_iocb_rsp
{
994 #define IB_AE_IOCB_RSP_OI 0x01
995 #define IB_AE_IOCB_RSP_I 0x02
997 #define LINK_UP_EVENT 0x00
998 #define LINK_DOWN_EVENT 0x01
999 #define CAM_LOOKUP_ERR_EVENT 0x06
1000 #define SOFT_ECC_ERROR_EVENT 0x07
1001 #define MGMT_ERR_EVENT 0x08
1002 #define TEN_GIG_MAC_EVENT 0x09
1003 #define GPI0_H2L_EVENT 0x10
1004 #define GPI0_L2H_EVENT 0x20
1005 #define GPI1_H2L_EVENT 0x11
1006 #define GPI1_L2H_EVENT 0x21
1007 #define PCI_ERR_ANON_BUF_RD 0x40
1009 __le32 reserved
[15];
1010 } __attribute((packed
));
1013 * These three structures are for generic
1014 * handling of ib and ob iocbs.
1016 struct ql_net_rsp_iocb
{
1021 __le32 reserved
[14];
1022 } __attribute((packed
));
1024 struct net_req_iocb
{
1029 __le32 reserved1
[30];
1030 } __attribute((packed
));
1033 * tx ring initialization control block for chip.
1035 * "Work Queue Initialization Control Block"
1039 #define Q_LEN_V (1 << 4)
1040 #define Q_LEN_CPP_CONT 0x0000
1041 #define Q_LEN_CPP_16 0x0001
1042 #define Q_LEN_CPP_32 0x0002
1043 #define Q_LEN_CPP_64 0x0003
1045 #define Q_PRI_SHIFT 1
1046 #define Q_FLAGS_LC 0x1000
1047 #define Q_FLAGS_LB 0x2000
1048 #define Q_FLAGS_LI 0x4000
1049 #define Q_FLAGS_LO 0x8000
1051 #define Q_CQ_ID_RSS_RV 0x8000
1055 __le32 cnsmr_idx_addr_lo
;
1056 __le32 cnsmr_idx_addr_hi
;
1057 } __attribute((packed
));
1060 * rx ring initialization control block for chip.
1062 * "Completion Queue Initialization Control Block"
1069 #define FLAGS_LV 0x08
1070 #define FLAGS_LS 0x10
1071 #define FLAGS_LL 0x20
1072 #define FLAGS_LI 0x40
1073 #define FLAGS_LC 0x80
1075 #define LEN_V (1 << 4)
1076 #define LEN_CPP_CONT 0x0000
1077 #define LEN_CPP_32 0x0001
1078 #define LEN_CPP_64 0x0002
1079 #define LEN_CPP_128 0x0003
1083 __le32 prod_idx_addr_lo
;
1084 __le32 prod_idx_addr_hi
;
1089 __le16 lbq_buf_size
;
1090 __le16 lbq_len
; /* entry count */
1093 __le16 sbq_buf_size
;
1094 __le16 sbq_len
; /* entry count */
1095 } __attribute((packed
));
1099 #define RSS_L4K 0x80
1101 #define RSS_L6K 0x01
1105 #define RSS_RI4 0x10
1106 #define RSS_RT4 0x20
1107 #define RSS_RI6 0x40
1108 #define RSS_RT6 0x80
1110 __le32 hash_cq_id
[256];
1111 __le32 ipv6_hash_key
[10];
1112 __le32 ipv4_hash_key
[4];
1113 } __attribute((packed
));
1115 /* SOFTWARE/DRIVER DATA STRUCTURES. */
1118 struct tx_buf_desc oal
[TX_DESC_PER_OAL
];
1122 DECLARE_PCI_UNMAP_ADDR(mapaddr
);
1123 DECLARE_PCI_UNMAP_LEN(maplen
);
1126 struct tx_ring_desc
{
1127 struct sk_buff
*skb
;
1128 struct ob_mac_iocb_req
*queue_entry
;
1131 struct map_list map
[MAX_SKB_FRAGS
+ 1];
1133 struct tx_ring_desc
*next
;
1138 struct page
*lbq_page
;
1139 struct sk_buff
*skb
;
1141 struct bq_element
*bq
;
1143 DECLARE_PCI_UNMAP_ADDR(mapaddr
);
1144 DECLARE_PCI_UNMAP_LEN(maplen
);
1147 #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1153 struct wqicb wqicb
; /* structure used to inform chip of new queue */
1154 void *wq_base
; /* pci_alloc:virtual addr for tx */
1155 dma_addr_t wq_base_dma
; /* pci_alloc:dma addr for tx */
1156 u32
*cnsmr_idx_sh_reg
; /* shadow copy of consumer idx */
1157 dma_addr_t cnsmr_idx_sh_reg_dma
; /* dma-shadow copy of consumer */
1158 u32 wq_size
; /* size in bytes of queue area */
1159 u32 wq_len
; /* number of entries in queue */
1160 void __iomem
*prod_idx_db_reg
; /* doorbell area index reg at offset 0x00 */
1161 void __iomem
*valid_db_reg
; /* doorbell area valid reg at offset 0x04 */
1162 u16 prod_idx
; /* current value for prod idx */
1163 u16 cq_id
; /* completion (rx) queue for tx completions */
1164 u8 wq_id
; /* queue id for this entry */
1166 struct tx_ring_desc
*q
; /* descriptor list for the queue */
1168 atomic_t tx_count
; /* counts down for every outstanding IO */
1169 atomic_t queue_stopped
; /* Turns queue off when full. */
1170 struct delayed_work tx_work
;
1171 struct ql_adapter
*qdev
;
1175 * Type of inbound queue.
1178 DEFAULT_Q
= 2, /* Handles slow queue and chip/MPI events. */
1179 TX_Q
= 3, /* Handles outbound completions. */
1180 RX_Q
= 4, /* Handles inbound completions. */
1184 struct cqicb cqicb
; /* The chip's completion queue init control block. */
1186 /* Completion queue elements. */
1188 dma_addr_t cq_base_dma
;
1192 u32
*prod_idx_sh_reg
; /* Shadowed producer register. */
1193 dma_addr_t prod_idx_sh_reg_dma
;
1194 void __iomem
*cnsmr_idx_db_reg
; /* PCI doorbell mem area + 0 */
1195 u32 cnsmr_idx
; /* current sw idx */
1196 struct ql_net_rsp_iocb
*curr_entry
; /* next entry on queue */
1197 void __iomem
*valid_db_reg
; /* PCI doorbell mem area + 0x04 */
1199 /* Large buffer queue elements. */
1200 u32 lbq_len
; /* entry count */
1201 u32 lbq_size
; /* size in bytes of queue */
1204 dma_addr_t lbq_base_dma
;
1205 void *lbq_base_indirect
;
1206 dma_addr_t lbq_base_indirect_dma
;
1207 struct bq_desc
*lbq
; /* array of control blocks */
1208 void __iomem
*lbq_prod_idx_db_reg
; /* PCI doorbell mem area + 0x18 */
1209 u32 lbq_prod_idx
; /* current sw prod idx */
1210 u32 lbq_curr_idx
; /* next entry we expect */
1211 u32 lbq_clean_idx
; /* beginning of new descs */
1212 u32 lbq_free_cnt
; /* free buffer desc cnt */
1214 /* Small buffer queue elements. */
1215 u32 sbq_len
; /* entry count */
1216 u32 sbq_size
; /* size in bytes of queue */
1219 dma_addr_t sbq_base_dma
;
1220 void *sbq_base_indirect
;
1221 dma_addr_t sbq_base_indirect_dma
;
1222 struct bq_desc
*sbq
; /* array of control blocks */
1223 void __iomem
*sbq_prod_idx_db_reg
; /* PCI doorbell mem area + 0x1c */
1224 u32 sbq_prod_idx
; /* current sw prod idx */
1225 u32 sbq_curr_idx
; /* next entry we expect */
1226 u32 sbq_clean_idx
; /* beginning of new descs */
1227 u32 sbq_free_cnt
; /* free buffer desc cnt */
1229 /* Misc. handler elements. */
1230 u32 type
; /* Type of queue, tx, rx, or default. */
1231 u32 irq
; /* Which vector this ring is assigned. */
1232 u32 cpu
; /* Which CPU this should run on. */
1233 char name
[IFNAMSIZ
+ 5];
1234 struct napi_struct napi
;
1235 struct delayed_work rx_work
;
1237 struct ql_adapter
*qdev
;
1241 * RSS Initialization Control Block
1249 * These stats come from offset 200h to 278h
1250 * in the XGMAC register.
1260 u64 tx_65_to_127_pkt
;
1261 u64 tx_128_to_255_pkt
;
1263 u64 tx_512_to_1023_pkt
;
1264 u64 tx_1024_to_1518_pkt
;
1265 u64 tx_1519_to_max_pkt
;
1266 u64 tx_undersize_pkt
;
1267 u64 tx_oversize_pkt
;
1270 * These stats come from offset 300h to 3C8h
1271 * in the XGMAC register.
1280 u64 rx_undersize_pkts
;
1281 u64 rx_oversize_pkts
;
1283 u64 rx_undersize_fcerr_pkts
;
1292 u64 rx_65_to_127_pkts
;
1293 u64 rx_128_255_pkts
;
1294 u64 rx_256_511_pkts
;
1295 u64 rx_512_to_1023_pkts
;
1296 u64 rx_1024_to_1518_pkts
;
1297 u64 rx_1519_to_max_pkts
;
1298 u64 rx_len_err_pkts
;
1302 * intr_context structure is used during initialization
1303 * to hook the interrupts. It is also used in a single
1304 * irq environment as a context to the ISR.
1306 struct intr_context
{
1307 struct ql_adapter
*qdev
;
1310 u32 intr_en_mask
; /* value/mask used to enable this intr */
1311 u32 intr_dis_mask
; /* value/mask used to disable this intr */
1312 u32 intr_read_mask
; /* value/mask used to read this intr */
1313 char name
[IFNAMSIZ
* 2];
1314 atomic_t irq_cnt
; /* irq_cnt is used in single vector
1315 * environment. It's incremented for each
1316 * irq handler that is scheduled. When each
1317 * handler finishes it decrements irq_cnt and
1318 * enables interrupts if it's zero. */
1319 irq_handler_t handler
;
1322 /* adapter flags definitions. */
1324 QL_ADAPTER_UP
= (1 << 0), /* Adapter has been brought up. */
1325 QL_LEGACY_ENABLED
= (1 << 3),
1326 QL_MSI_ENABLED
= (1 << 3),
1327 QL_MSIX_ENABLED
= (1 << 4),
1328 QL_DMA64
= (1 << 5),
1329 QL_PROMISCUOUS
= (1 << 6),
1330 QL_ALLMULTI
= (1 << 7),
1333 /* link_status bit definitions */
1335 LOOPBACK_MASK
= 0x00000700,
1336 LOOPBACK_PCS
= 0x00000100,
1337 LOOPBACK_HSS
= 0x00000200,
1338 LOOPBACK_EXT
= 0x00000300,
1339 PAUSE_MASK
= 0x000000c0,
1340 PAUSE_STD
= 0x00000040,
1341 PAUSE_PRI
= 0x00000080,
1342 SPEED_MASK
= 0x00000038,
1343 SPEED_100Mb
= 0x00000000,
1344 SPEED_1Gb
= 0x00000008,
1345 SPEED_10Gb
= 0x00000010,
1346 LINK_TYPE_MASK
= 0x00000007,
1347 LINK_TYPE_XFI
= 0x00000001,
1348 LINK_TYPE_XAUI
= 0x00000002,
1349 LINK_TYPE_XFI_BP
= 0x00000003,
1350 LINK_TYPE_XAUI_BP
= 0x00000004,
1351 LINK_TYPE_10GBASET
= 0x00000005,
1355 * The main Adapter structure definition.
1356 * This structure has all fields relevant to the hardware.
1360 unsigned long flags
;
1363 struct nic_stats nic_stats
;
1365 struct vlan_group
*vlgrp
;
1367 /* PCI Configuration information for this device */
1368 struct pci_dev
*pdev
;
1369 struct net_device
*ndev
; /* Parent NET device */
1371 /* Hardware information */
1373 u32 func
; /* PCI function for this adapter */
1375 spinlock_t adapter_lock
;
1377 spinlock_t stats_lock
;
1379 /* PCI Bus Relative Register Addresses */
1380 void __iomem
*reg_base
;
1381 void __iomem
*doorbell_area
;
1382 u32 doorbell_area_size
;
1386 /* Page for Shadow Registers */
1387 void *rx_ring_shadow_reg_area
;
1388 dma_addr_t rx_ring_shadow_reg_dma
;
1389 void *tx_ring_shadow_reg_area
;
1390 dma_addr_t tx_ring_shadow_reg_dma
;
1398 struct msix_entry
*msi_x_entry
;
1399 struct intr_context intr_context
[MAX_RX_RINGS
];
1401 int tx_ring_count
; /* One per online CPU. */
1402 u32 rss_ring_first_cq_id
;/* index of first inbound (rss) rx_ring */
1403 u32 rss_ring_count
; /* One per online CPU. */
1406 * one default queue +
1407 * (CPU count * outbound completion rx_ring) +
1408 * (CPU count * inbound (RSS) completion rx_ring)
1413 struct rx_ring
*rx_ring
;
1415 struct tx_ring
*tx_ring
;
1416 u32 default_rx_queue
;
1418 u16 rx_coalesce_usecs
; /* cqicb->int_delay */
1419 u16 rx_max_coalesced_frames
; /* cqicb->pkt_int_delay */
1420 u16 tx_coalesce_usecs
; /* cqicb->int_delay */
1421 u16 tx_max_coalesced_frames
; /* cqicb->pkt_int_delay */
1428 struct flash_params flash
;
1430 struct net_device_stats stats
;
1431 struct workqueue_struct
*q_workqueue
;
1432 struct workqueue_struct
*workqueue
;
1433 struct delayed_work asic_reset_work
;
1434 struct delayed_work mpi_reset_work
;
1435 struct delayed_work mpi_work
;
1439 * Typical Register accessor for memory mapped device.
1441 static inline u32
ql_read32(const struct ql_adapter
*qdev
, int reg
)
1443 return readl(qdev
->reg_base
+ reg
);
1447 * Typical Register accessor for memory mapped device.
1449 static inline void ql_write32(const struct ql_adapter
*qdev
, int reg
, u32 val
)
1451 writel(val
, qdev
->reg_base
+ reg
);
1455 * Doorbell Registers:
1456 * Doorbell registers are virtual registers in the PCI memory space.
1457 * The space is allocated by the chip during PCI initialization. The
1458 * device driver finds the doorbell address in BAR 3 in PCI config space.
1459 * The registers are used to control outbound and inbound queues. For
1460 * example, the producer index for an outbound queue. Each queue uses
1461 * 1 4k chunk of memory. The lower half of the space is for outbound
1462 * queues. The upper half is for inbound queues.
1464 static inline void ql_write_db_reg(u32 val
, void __iomem
*addr
)
1472 * Outbound queues have a consumer index that is maintained by the chip.
1473 * Inbound queues have a producer index that is maintained by the chip.
1474 * For lower overhead, these registers are "shadowed" to host memory
1475 * which allows the device driver to track the queue progress without
1476 * PCI reads. When an entry is placed on an inbound queue, the chip will
1477 * update the relevant index register and then copy the value to the
1478 * shadow register in host memory.
1480 static inline unsigned int ql_read_sh_reg(const volatile void *addr
)
1482 return *(volatile unsigned int __force
*)addr
;
1485 extern char qlge_driver_name
[];
1486 extern const char qlge_driver_version
[];
1487 extern const struct ethtool_ops qlge_ethtool_ops
;
1489 extern int ql_sem_spinlock(struct ql_adapter
*qdev
, u32 sem_mask
);
1490 extern void ql_sem_unlock(struct ql_adapter
*qdev
, u32 sem_mask
);
1491 extern int ql_read_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32
*data
);
1492 extern int ql_get_mac_addr_reg(struct ql_adapter
*qdev
, u32 type
, u16 index
,
1494 extern int ql_get_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32
*value
);
1495 extern int ql_write_cfg(struct ql_adapter
*qdev
, void *ptr
, int size
, u32 bit
,
1497 void ql_queue_fw_error(struct ql_adapter
*qdev
);
1498 void ql_mpi_work(struct work_struct
*work
);
1499 void ql_mpi_reset_work(struct work_struct
*work
);
1500 int ql_wait_reg_rdy(struct ql_adapter
*qdev
, u32 reg
, u32 bit
, u32 ebit
);
1501 void ql_queue_asic_error(struct ql_adapter
*qdev
);
1502 u32
ql_enable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
);
1503 void ql_set_ethtool_ops(struct net_device
*ndev
);
1504 int ql_read_xgmac_reg64(struct ql_adapter
*qdev
, u32 reg
, u64
*data
);
1511 /* #define QL_IB_DUMP */
1512 /* #define QL_OB_DUMP */
1516 extern void ql_dump_xgmac_control_regs(struct ql_adapter
*qdev
);
1517 extern void ql_dump_routing_entries(struct ql_adapter
*qdev
);
1518 extern void ql_dump_regs(struct ql_adapter
*qdev
);
1519 #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
1520 #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
1521 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
1523 #define QL_DUMP_REGS(qdev)
1524 #define QL_DUMP_ROUTE(qdev)
1525 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
1529 extern void ql_dump_stat(struct ql_adapter
*qdev
);
1530 #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
1532 #define QL_DUMP_STAT(qdev)
1536 extern void ql_dump_qdev(struct ql_adapter
*qdev
);
1537 #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
1539 #define QL_DUMP_QDEV(qdev)
1543 extern void ql_dump_wqicb(struct wqicb
*wqicb
);
1544 extern void ql_dump_tx_ring(struct tx_ring
*tx_ring
);
1545 extern void ql_dump_ricb(struct ricb
*ricb
);
1546 extern void ql_dump_cqicb(struct cqicb
*cqicb
);
1547 extern void ql_dump_rx_ring(struct rx_ring
*rx_ring
);
1548 extern void ql_dump_hw_cb(struct ql_adapter
*qdev
, int size
, u32 bit
, u16 q_id
);
1549 #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
1550 #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
1551 #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
1552 #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
1553 #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
1554 #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
1555 ql_dump_hw_cb(qdev, size, bit, q_id)
1557 #define QL_DUMP_RICB(ricb)
1558 #define QL_DUMP_WQICB(wqicb)
1559 #define QL_DUMP_TX_RING(tx_ring)
1560 #define QL_DUMP_CQICB(cqicb)
1561 #define QL_DUMP_RX_RING(rx_ring)
1562 #define QL_DUMP_HW_CB(qdev, size, bit, q_id)
1566 extern void ql_dump_tx_desc(struct tx_buf_desc
*tbd
);
1567 extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req
*ob_mac_iocb
);
1568 extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp
*ob_mac_rsp
);
1569 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
1570 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
1572 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
1573 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
1577 extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp
*ib_mac_rsp
);
1578 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
1580 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
1584 extern void ql_dump_all(struct ql_adapter
*qdev
);
1585 #define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
1587 #define QL_DUMP_ALL(qdev)
1590 #endif /* _QLGE_H_ */