2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work
= 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit
= 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
97 RTL_GIGA_MAC_NONE
= 0x00,
98 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
99 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
118 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
119 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
120 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
121 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
122 RTL_GIGA_MAC_VER_25
= 0x19 // 8168D
125 #define _R(NAME,MAC,MASK) \
126 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
128 static const struct {
131 u32 RxConfigMask
; /* Clears the bits supported by this chip */
132 } rtl_chip_info
[] = {
133 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
134 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
135 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
136 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
138 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
139 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
141 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
148 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
149 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
150 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
156 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880) // PCI-E
167 static void rtl_hw_start_8169(struct net_device
*);
168 static void rtl_hw_start_8168(struct net_device
*);
169 static void rtl_hw_start_8101(struct net_device
*);
171 static struct pci_device_id rtl8169_pci_tbl
[] = {
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
178 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
180 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
181 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
183 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
187 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
189 static int rx_copybreak
= 200;
196 MAC0
= 0, /* Ethernet hardware address. */
198 MAR0
= 8, /* Multicast filter. */
199 CounterAddrLow
= 0x10,
200 CounterAddrHigh
= 0x14,
201 TxDescStartAddrLow
= 0x20,
202 TxDescStartAddrHigh
= 0x24,
203 TxHDescStartAddrLow
= 0x28,
204 TxHDescStartAddrHigh
= 0x2c,
227 RxDescAddrLow
= 0xe4,
228 RxDescAddrHigh
= 0xe8,
231 FuncEventMask
= 0xf4,
232 FuncPresetState
= 0xf8,
233 FuncForceEvent
= 0xfc,
236 enum rtl8110_registers
{
242 enum rtl8168_8101_registers
{
245 #define CSIAR_FLAG 0x80000000
246 #define CSIAR_WRITE_CMD 0x80000000
247 #define CSIAR_BYTE_ENABLE 0x0f
248 #define CSIAR_BYTE_ENABLE_SHIFT 12
249 #define CSIAR_ADDR_MASK 0x0fff
252 #define EPHYAR_FLAG 0x80000000
253 #define EPHYAR_WRITE_CMD 0x80000000
254 #define EPHYAR_REG_MASK 0x1f
255 #define EPHYAR_REG_SHIFT 16
256 #define EPHYAR_DATA_MASK 0xffff
258 #define FIX_NAK_1 (1 << 4)
259 #define FIX_NAK_2 (1 << 3)
262 enum rtl_register_content
{
263 /* InterruptStatusBits */
267 TxDescUnavail
= 0x0080,
289 /* TXPoll register p.5 */
290 HPQ
= 0x80, /* Poll cmd on the high prio queue */
291 NPQ
= 0x40, /* Poll cmd on the low prio queue */
292 FSWInt
= 0x01, /* Forced software interrupt */
296 Cfg9346_Unlock
= 0xc0,
301 AcceptBroadcast
= 0x08,
302 AcceptMulticast
= 0x04,
304 AcceptAllPhys
= 0x01,
311 TxInterFrameGapShift
= 24,
312 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
314 /* Config1 register p.24 */
317 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
318 Speed_down
= (1 << 4),
322 PMEnable
= (1 << 0), /* Power Management Enable */
324 /* Config2 register p. 25 */
325 PCI_Clock_66MHz
= 0x01,
326 PCI_Clock_33MHz
= 0x00,
328 /* Config3 register p.25 */
329 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
330 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
331 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
333 /* Config5 register p.27 */
334 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
335 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
336 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
337 LanWake
= (1 << 1), /* LanWake enable/disable */
338 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
341 TBIReset
= 0x80000000,
342 TBILoopback
= 0x40000000,
343 TBINwEnable
= 0x20000000,
344 TBINwRestart
= 0x10000000,
345 TBILinkOk
= 0x02000000,
346 TBINwComplete
= 0x01000000,
349 EnableBist
= (1 << 15), // 8168 8101
350 Mac_dbgo_oe
= (1 << 14), // 8168 8101
351 Normal_mode
= (1 << 13), // unused
352 Force_half_dup
= (1 << 12), // 8168 8101
353 Force_rxflow_en
= (1 << 11), // 8168 8101
354 Force_txflow_en
= (1 << 10), // 8168 8101
355 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
356 ASF
= (1 << 8), // 8168 8101
357 PktCntrDisable
= (1 << 7), // 8168 8101
358 Mac_dbgo_sel
= 0x001c, // 8168
363 INTT_0
= 0x0000, // 8168
364 INTT_1
= 0x0001, // 8168
365 INTT_2
= 0x0002, // 8168
366 INTT_3
= 0x0003, // 8168
368 /* rtl8169_PHYstatus */
379 TBILinkOK
= 0x02000000,
381 /* DumpCounterCommand */
385 enum desc_status_bit
{
386 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
387 RingEnd
= (1 << 30), /* End of descriptor ring */
388 FirstFrag
= (1 << 29), /* First segment of a packet */
389 LastFrag
= (1 << 28), /* Final segment of a packet */
392 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
393 MSSShift
= 16, /* MSS value position */
394 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
395 IPCS
= (1 << 18), /* Calculate IP checksum */
396 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
397 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
398 TxVlanTag
= (1 << 17), /* Add VLAN tag */
401 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
402 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
404 #define RxProtoUDP (PID1)
405 #define RxProtoTCP (PID0)
406 #define RxProtoIP (PID1 | PID0)
407 #define RxProtoMask RxProtoIP
409 IPFail
= (1 << 16), /* IP checksum failed */
410 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
411 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
412 RxVlanTag
= (1 << 16), /* VLAN tag available */
415 #define RsvdMask 0x3fffc000
432 u8 __pad
[sizeof(void *) - sizeof(u32
)];
436 RTL_FEATURE_WOL
= (1 << 0),
437 RTL_FEATURE_MSI
= (1 << 1),
438 RTL_FEATURE_GMII
= (1 << 2),
441 struct rtl8169_counters
{
448 __le32 tx_one_collision
;
449 __le32 tx_multi_collision
;
457 struct rtl8169_private
{
458 void __iomem
*mmio_addr
; /* memory map physical address */
459 struct pci_dev
*pci_dev
; /* Index of PCI device */
460 struct net_device
*dev
;
461 struct napi_struct napi
;
462 spinlock_t lock
; /* spin lock flag */
466 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
467 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
470 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
471 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
472 dma_addr_t TxPhyAddr
;
473 dma_addr_t RxPhyAddr
;
474 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
475 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
478 struct timer_list timer
;
483 int phy_1000_ctrl_reg
;
484 #ifdef CONFIG_R8169_VLAN
485 struct vlan_group
*vlgrp
;
487 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
488 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
489 void (*phy_reset_enable
)(void __iomem
*);
490 void (*hw_start
)(struct net_device
*);
491 unsigned int (*phy_reset_pending
)(void __iomem
*);
492 unsigned int (*link_ok
)(void __iomem
*);
493 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
495 struct delayed_work task
;
498 struct mii_if_info mii
;
499 struct rtl8169_counters counters
;
502 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
503 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
504 module_param(rx_copybreak
, int, 0);
505 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
506 module_param(use_dac
, int, 0);
507 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
508 module_param_named(debug
, debug
.msg_enable
, int, 0);
509 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
510 MODULE_LICENSE("GPL");
511 MODULE_VERSION(RTL8169_VERSION
);
513 static int rtl8169_open(struct net_device
*dev
);
514 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
515 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
516 static int rtl8169_init_ring(struct net_device
*dev
);
517 static void rtl_hw_start(struct net_device
*dev
);
518 static int rtl8169_close(struct net_device
*dev
);
519 static void rtl_set_rx_mode(struct net_device
*dev
);
520 static void rtl8169_tx_timeout(struct net_device
*dev
);
521 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
522 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
523 void __iomem
*, u32 budget
);
524 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
525 static void rtl8169_down(struct net_device
*dev
);
526 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
527 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
529 static const unsigned int rtl8169_rx_config
=
530 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
532 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
536 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
538 for (i
= 20; i
> 0; i
--) {
540 * Check if the RTL8169 has completed writing to the specified
543 if (!(RTL_R32(PHYAR
) & 0x80000000))
549 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
553 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
555 for (i
= 20; i
> 0; i
--) {
557 * Check if the RTL8169 has completed retrieving data from
558 * the specified MII register.
560 if (RTL_R32(PHYAR
) & 0x80000000) {
561 value
= RTL_R32(PHYAR
) & 0xffff;
569 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
571 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
574 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
577 struct rtl8169_private
*tp
= netdev_priv(dev
);
578 void __iomem
*ioaddr
= tp
->mmio_addr
;
580 mdio_write(ioaddr
, location
, val
);
583 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
585 struct rtl8169_private
*tp
= netdev_priv(dev
);
586 void __iomem
*ioaddr
= tp
->mmio_addr
;
588 return mdio_read(ioaddr
, location
);
591 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
595 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
596 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
598 for (i
= 0; i
< 100; i
++) {
599 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
605 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
610 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
612 for (i
= 0; i
< 100; i
++) {
613 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
614 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
623 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
627 RTL_W32(CSIDR
, value
);
628 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
629 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
631 for (i
= 0; i
< 100; i
++) {
632 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
638 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
643 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
644 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
646 for (i
= 0; i
< 100; i
++) {
647 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
648 value
= RTL_R32(CSIDR
);
657 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
659 RTL_W16(IntrMask
, 0x0000);
661 RTL_W16(IntrStatus
, 0xffff);
664 static void rtl8169_asic_down(void __iomem
*ioaddr
)
666 RTL_W8(ChipCmd
, 0x00);
667 rtl8169_irq_mask_and_ack(ioaddr
);
671 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
673 return RTL_R32(TBICSR
) & TBIReset
;
676 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
678 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
681 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
683 return RTL_R32(TBICSR
) & TBILinkOk
;
686 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
688 return RTL_R8(PHYstatus
) & LinkStatus
;
691 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
693 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
696 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
700 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
701 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
704 static void rtl8169_check_link_status(struct net_device
*dev
,
705 struct rtl8169_private
*tp
,
706 void __iomem
*ioaddr
)
710 spin_lock_irqsave(&tp
->lock
, flags
);
711 if (tp
->link_ok(ioaddr
)) {
712 netif_carrier_on(dev
);
713 if (netif_msg_ifup(tp
))
714 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
716 if (netif_msg_ifdown(tp
))
717 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
718 netif_carrier_off(dev
);
720 spin_unlock_irqrestore(&tp
->lock
, flags
);
723 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
725 struct rtl8169_private
*tp
= netdev_priv(dev
);
726 void __iomem
*ioaddr
= tp
->mmio_addr
;
731 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
732 wol
->supported
= WAKE_ANY
;
734 spin_lock_irq(&tp
->lock
);
736 options
= RTL_R8(Config1
);
737 if (!(options
& PMEnable
))
740 options
= RTL_R8(Config3
);
741 if (options
& LinkUp
)
742 wol
->wolopts
|= WAKE_PHY
;
743 if (options
& MagicPacket
)
744 wol
->wolopts
|= WAKE_MAGIC
;
746 options
= RTL_R8(Config5
);
748 wol
->wolopts
|= WAKE_UCAST
;
750 wol
->wolopts
|= WAKE_BCAST
;
752 wol
->wolopts
|= WAKE_MCAST
;
755 spin_unlock_irq(&tp
->lock
);
758 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
760 struct rtl8169_private
*tp
= netdev_priv(dev
);
761 void __iomem
*ioaddr
= tp
->mmio_addr
;
768 { WAKE_ANY
, Config1
, PMEnable
},
769 { WAKE_PHY
, Config3
, LinkUp
},
770 { WAKE_MAGIC
, Config3
, MagicPacket
},
771 { WAKE_UCAST
, Config5
, UWF
},
772 { WAKE_BCAST
, Config5
, BWF
},
773 { WAKE_MCAST
, Config5
, MWF
},
774 { WAKE_ANY
, Config5
, LanWake
}
777 spin_lock_irq(&tp
->lock
);
779 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
781 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
782 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
783 if (wol
->wolopts
& cfg
[i
].opt
)
784 options
|= cfg
[i
].mask
;
785 RTL_W8(cfg
[i
].reg
, options
);
788 RTL_W8(Cfg9346
, Cfg9346_Lock
);
791 tp
->features
|= RTL_FEATURE_WOL
;
793 tp
->features
&= ~RTL_FEATURE_WOL
;
794 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
796 spin_unlock_irq(&tp
->lock
);
801 static void rtl8169_get_drvinfo(struct net_device
*dev
,
802 struct ethtool_drvinfo
*info
)
804 struct rtl8169_private
*tp
= netdev_priv(dev
);
806 strcpy(info
->driver
, MODULENAME
);
807 strcpy(info
->version
, RTL8169_VERSION
);
808 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
811 static int rtl8169_get_regs_len(struct net_device
*dev
)
813 return R8169_REGS_SIZE
;
816 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
817 u8 autoneg
, u16 speed
, u8 duplex
)
819 struct rtl8169_private
*tp
= netdev_priv(dev
);
820 void __iomem
*ioaddr
= tp
->mmio_addr
;
824 reg
= RTL_R32(TBICSR
);
825 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
826 (duplex
== DUPLEX_FULL
)) {
827 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
828 } else if (autoneg
== AUTONEG_ENABLE
)
829 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
831 if (netif_msg_link(tp
)) {
832 printk(KERN_WARNING
"%s: "
833 "incorrect speed setting refused in TBI mode\n",
842 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
843 u8 autoneg
, u16 speed
, u8 duplex
)
845 struct rtl8169_private
*tp
= netdev_priv(dev
);
846 void __iomem
*ioaddr
= tp
->mmio_addr
;
849 if (autoneg
== AUTONEG_ENABLE
) {
852 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
853 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
854 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
855 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
857 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
858 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
860 /* The 8100e/8101e/8102e do Fast Ethernet only. */
861 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
862 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
863 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
864 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
865 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
866 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
867 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
868 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
869 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
870 } else if (netif_msg_link(tp
)) {
871 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
875 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
877 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
878 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
879 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
882 * Vendor specific (0x1f) and reserved (0x0e) MII
885 mdio_write(ioaddr
, 0x1f, 0x0000);
886 mdio_write(ioaddr
, 0x0e, 0x0000);
889 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
890 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
894 if (speed
== SPEED_10
)
896 else if (speed
== SPEED_100
)
897 bmcr
= BMCR_SPEED100
;
901 if (duplex
== DUPLEX_FULL
)
902 bmcr
|= BMCR_FULLDPLX
;
904 mdio_write(ioaddr
, 0x1f, 0x0000);
907 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
909 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
911 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
912 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
913 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
914 mdio_write(ioaddr
, 0x17, 0x2138);
915 mdio_write(ioaddr
, 0x0e, 0x0260);
917 mdio_write(ioaddr
, 0x17, 0x2108);
918 mdio_write(ioaddr
, 0x0e, 0x0000);
925 static int rtl8169_set_speed(struct net_device
*dev
,
926 u8 autoneg
, u16 speed
, u8 duplex
)
928 struct rtl8169_private
*tp
= netdev_priv(dev
);
931 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
933 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
934 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
939 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
941 struct rtl8169_private
*tp
= netdev_priv(dev
);
945 spin_lock_irqsave(&tp
->lock
, flags
);
946 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
947 spin_unlock_irqrestore(&tp
->lock
, flags
);
952 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
954 struct rtl8169_private
*tp
= netdev_priv(dev
);
956 return tp
->cp_cmd
& RxChkSum
;
959 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
961 struct rtl8169_private
*tp
= netdev_priv(dev
);
962 void __iomem
*ioaddr
= tp
->mmio_addr
;
965 spin_lock_irqsave(&tp
->lock
, flags
);
968 tp
->cp_cmd
|= RxChkSum
;
970 tp
->cp_cmd
&= ~RxChkSum
;
972 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
975 spin_unlock_irqrestore(&tp
->lock
, flags
);
980 #ifdef CONFIG_R8169_VLAN
982 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
985 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
986 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
989 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
990 struct vlan_group
*grp
)
992 struct rtl8169_private
*tp
= netdev_priv(dev
);
993 void __iomem
*ioaddr
= tp
->mmio_addr
;
996 spin_lock_irqsave(&tp
->lock
, flags
);
999 tp
->cp_cmd
|= RxVlan
;
1001 tp
->cp_cmd
&= ~RxVlan
;
1002 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1004 spin_unlock_irqrestore(&tp
->lock
, flags
);
1007 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1008 struct sk_buff
*skb
)
1010 u32 opts2
= le32_to_cpu(desc
->opts2
);
1011 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1014 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1015 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
1023 #else /* !CONFIG_R8169_VLAN */
1025 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1026 struct sk_buff
*skb
)
1031 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1032 struct sk_buff
*skb
)
1039 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1041 struct rtl8169_private
*tp
= netdev_priv(dev
);
1042 void __iomem
*ioaddr
= tp
->mmio_addr
;
1046 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1047 cmd
->port
= PORT_FIBRE
;
1048 cmd
->transceiver
= XCVR_INTERNAL
;
1050 status
= RTL_R32(TBICSR
);
1051 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1052 cmd
->autoneg
= !!(status
& TBINwEnable
);
1054 cmd
->speed
= SPEED_1000
;
1055 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1060 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1062 struct rtl8169_private
*tp
= netdev_priv(dev
);
1064 return mii_ethtool_gset(&tp
->mii
, cmd
);
1067 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1069 struct rtl8169_private
*tp
= netdev_priv(dev
);
1070 unsigned long flags
;
1073 spin_lock_irqsave(&tp
->lock
, flags
);
1075 rc
= tp
->get_settings(dev
, cmd
);
1077 spin_unlock_irqrestore(&tp
->lock
, flags
);
1081 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1084 struct rtl8169_private
*tp
= netdev_priv(dev
);
1085 unsigned long flags
;
1087 if (regs
->len
> R8169_REGS_SIZE
)
1088 regs
->len
= R8169_REGS_SIZE
;
1090 spin_lock_irqsave(&tp
->lock
, flags
);
1091 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1092 spin_unlock_irqrestore(&tp
->lock
, flags
);
1095 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1097 struct rtl8169_private
*tp
= netdev_priv(dev
);
1099 return tp
->msg_enable
;
1102 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1104 struct rtl8169_private
*tp
= netdev_priv(dev
);
1106 tp
->msg_enable
= value
;
1109 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1116 "tx_single_collisions",
1117 "tx_multi_collisions",
1125 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1129 return ARRAY_SIZE(rtl8169_gstrings
);
1135 static void rtl8169_update_counters(struct net_device
*dev
)
1137 struct rtl8169_private
*tp
= netdev_priv(dev
);
1138 void __iomem
*ioaddr
= tp
->mmio_addr
;
1139 struct rtl8169_counters
*counters
;
1145 * Some chips are unable to dump tally counters when the receiver
1148 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1151 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1155 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1156 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1157 RTL_W32(CounterAddrLow
, cmd
);
1158 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1161 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1162 /* copy updated counters */
1163 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1169 RTL_W32(CounterAddrLow
, 0);
1170 RTL_W32(CounterAddrHigh
, 0);
1172 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1175 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1176 struct ethtool_stats
*stats
, u64
*data
)
1178 struct rtl8169_private
*tp
= netdev_priv(dev
);
1182 rtl8169_update_counters(dev
);
1184 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1185 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1186 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1187 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1188 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1189 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1190 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1191 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1192 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1193 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1194 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1195 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1196 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1199 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1203 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1208 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1209 .get_drvinfo
= rtl8169_get_drvinfo
,
1210 .get_regs_len
= rtl8169_get_regs_len
,
1211 .get_link
= ethtool_op_get_link
,
1212 .get_settings
= rtl8169_get_settings
,
1213 .set_settings
= rtl8169_set_settings
,
1214 .get_msglevel
= rtl8169_get_msglevel
,
1215 .set_msglevel
= rtl8169_set_msglevel
,
1216 .get_rx_csum
= rtl8169_get_rx_csum
,
1217 .set_rx_csum
= rtl8169_set_rx_csum
,
1218 .set_tx_csum
= ethtool_op_set_tx_csum
,
1219 .set_sg
= ethtool_op_set_sg
,
1220 .set_tso
= ethtool_op_set_tso
,
1221 .get_regs
= rtl8169_get_regs
,
1222 .get_wol
= rtl8169_get_wol
,
1223 .set_wol
= rtl8169_set_wol
,
1224 .get_strings
= rtl8169_get_strings
,
1225 .get_sset_count
= rtl8169_get_sset_count
,
1226 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1229 static void rtl8169_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
,
1230 int bitnum
, int bitval
)
1234 val
= mdio_read(ioaddr
, reg
);
1235 val
= (bitval
== 1) ?
1236 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1237 mdio_write(ioaddr
, reg
, val
& 0xffff);
1240 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1241 void __iomem
*ioaddr
)
1244 * The driver currently handles the 8168Bf and the 8168Be identically
1245 * but they can be identified more specifically through the test below
1248 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1250 * Same thing for the 8101Eb and the 8101Ec:
1252 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1260 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25
},
1263 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24
},
1264 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1265 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1266 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1267 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1268 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1269 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1270 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1271 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1274 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1275 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1276 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1277 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1280 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1281 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1282 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1283 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1284 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1285 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1286 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1287 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1288 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1289 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1290 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1291 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1292 /* FIXME: where did these entries come from ? -- FR */
1293 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1294 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1297 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1298 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1299 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1300 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1301 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1302 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1305 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1309 reg
= RTL_R32(TxConfig
);
1310 while ((reg
& p
->mask
) != p
->val
)
1312 tp
->mac_version
= p
->mac_version
;
1315 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1317 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1325 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1328 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1333 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1336 u16 regs
[5]; /* Beware of bit-sign propagation */
1337 } phy_magic
[5] = { {
1338 { 0x0000, //w 4 15 12 0
1339 0x00a1, //w 3 15 0 00a1
1340 0x0008, //w 2 15 0 0008
1341 0x1020, //w 1 15 0 1020
1342 0x1000 } },{ //w 0 15 0 1000
1343 { 0x7000, //w 4 15 12 7
1344 0xff41, //w 3 15 0 ff41
1345 0xde60, //w 2 15 0 de60
1346 0x0140, //w 1 15 0 0140
1347 0x0077 } },{ //w 0 15 0 0077
1348 { 0xa000, //w 4 15 12 a
1349 0xdf01, //w 3 15 0 df01
1350 0xdf20, //w 2 15 0 df20
1351 0xff95, //w 1 15 0 ff95
1352 0xfa00 } },{ //w 0 15 0 fa00
1353 { 0xb000, //w 4 15 12 b
1354 0xff41, //w 3 15 0 ff41
1355 0xde20, //w 2 15 0 de20
1356 0x0140, //w 1 15 0 0140
1357 0x00bb } },{ //w 0 15 0 00bb
1358 { 0xf000, //w 4 15 12 f
1359 0xdf01, //w 3 15 0 df01
1360 0xdf20, //w 2 15 0 df20
1361 0xff95, //w 1 15 0 ff95
1362 0xbf00 } //w 0 15 0 bf00
1367 mdio_write(ioaddr
, 0x1f, 0x0001); //w 31 2 0 1
1368 mdio_write(ioaddr
, 0x15, 0x1000); //w 21 15 0 1000
1369 mdio_write(ioaddr
, 0x18, 0x65c7); //w 24 15 0 65c7
1370 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1372 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1375 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1376 mdio_write(ioaddr
, pos
, val
);
1378 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1379 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1380 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1382 mdio_write(ioaddr
, 0x1f, 0x0000); //w 31 2 0 0
1385 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1387 struct phy_reg phy_reg_init
[] = {
1393 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1396 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1398 struct phy_reg phy_reg_init
[] = {
1403 mdio_write(ioaddr
, 0x1f, 0x0001);
1404 mdio_patch(ioaddr
, 0x16, 1 << 0);
1406 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1409 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1411 struct phy_reg phy_reg_init
[] = {
1417 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1420 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1422 struct phy_reg phy_reg_init
[] = {
1430 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1433 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1435 struct phy_reg phy_reg_init
[] = {
1441 mdio_write(ioaddr
, 0x1f, 0x0000);
1442 mdio_patch(ioaddr
, 0x14, 1 << 5);
1443 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1445 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1448 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1450 struct phy_reg phy_reg_init
[] = {
1470 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1472 mdio_patch(ioaddr
, 0x14, 1 << 5);
1473 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1474 mdio_write(ioaddr
, 0x1f, 0x0000);
1477 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1479 struct phy_reg phy_reg_init
[] = {
1497 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1499 mdio_patch(ioaddr
, 0x16, 1 << 0);
1500 mdio_patch(ioaddr
, 0x14, 1 << 5);
1501 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1502 mdio_write(ioaddr
, 0x1f, 0x0000);
1505 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1507 struct phy_reg phy_reg_init
[] = {
1519 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1521 mdio_patch(ioaddr
, 0x16, 1 << 0);
1522 mdio_patch(ioaddr
, 0x14, 1 << 5);
1523 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1524 mdio_write(ioaddr
, 0x1f, 0x0000);
1527 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1529 rtl8168c_3_hw_phy_config(ioaddr
);
1532 static void rtl8168d_hw_phy_config(void __iomem
*ioaddr
)
1534 struct phy_reg phy_reg_init_0
[] = {
1560 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
1562 if (mdio_read(ioaddr
, 0x06) == 0xc400) {
1563 struct phy_reg phy_reg_init_1
[] = {
1595 rtl_phy_write(ioaddr
, phy_reg_init_1
,
1596 ARRAY_SIZE(phy_reg_init_1
));
1599 mdio_write(ioaddr
, 0x1f, 0x0000);
1602 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
1604 struct phy_reg phy_reg_init
[] = {
1611 mdio_write(ioaddr
, 0x1f, 0x0000);
1612 mdio_patch(ioaddr
, 0x11, 1 << 12);
1613 mdio_patch(ioaddr
, 0x19, 1 << 13);
1615 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1618 static void rtl_hw_phy_config(struct net_device
*dev
)
1620 struct rtl8169_private
*tp
= netdev_priv(dev
);
1621 void __iomem
*ioaddr
= tp
->mmio_addr
;
1623 rtl8169_print_mac_version(tp
);
1625 switch (tp
->mac_version
) {
1626 case RTL_GIGA_MAC_VER_01
:
1628 case RTL_GIGA_MAC_VER_02
:
1629 case RTL_GIGA_MAC_VER_03
:
1630 rtl8169s_hw_phy_config(ioaddr
);
1632 case RTL_GIGA_MAC_VER_04
:
1633 rtl8169sb_hw_phy_config(ioaddr
);
1635 case RTL_GIGA_MAC_VER_07
:
1636 case RTL_GIGA_MAC_VER_08
:
1637 case RTL_GIGA_MAC_VER_09
:
1638 rtl8102e_hw_phy_config(ioaddr
);
1640 case RTL_GIGA_MAC_VER_11
:
1641 rtl8168bb_hw_phy_config(ioaddr
);
1643 case RTL_GIGA_MAC_VER_12
:
1644 rtl8168bef_hw_phy_config(ioaddr
);
1646 case RTL_GIGA_MAC_VER_17
:
1647 rtl8168bef_hw_phy_config(ioaddr
);
1649 case RTL_GIGA_MAC_VER_18
:
1650 rtl8168cp_1_hw_phy_config(ioaddr
);
1652 case RTL_GIGA_MAC_VER_19
:
1653 rtl8168c_1_hw_phy_config(ioaddr
);
1655 case RTL_GIGA_MAC_VER_20
:
1656 rtl8168c_2_hw_phy_config(ioaddr
);
1658 case RTL_GIGA_MAC_VER_21
:
1659 rtl8168c_3_hw_phy_config(ioaddr
);
1661 case RTL_GIGA_MAC_VER_22
:
1662 rtl8168c_4_hw_phy_config(ioaddr
);
1664 case RTL_GIGA_MAC_VER_23
:
1665 case RTL_GIGA_MAC_VER_24
:
1666 rtl8168cp_2_hw_phy_config(ioaddr
);
1668 case RTL_GIGA_MAC_VER_25
:
1669 rtl8168d_hw_phy_config(ioaddr
);
1677 static void rtl8169_phy_timer(unsigned long __opaque
)
1679 struct net_device
*dev
= (struct net_device
*)__opaque
;
1680 struct rtl8169_private
*tp
= netdev_priv(dev
);
1681 struct timer_list
*timer
= &tp
->timer
;
1682 void __iomem
*ioaddr
= tp
->mmio_addr
;
1683 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1685 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1687 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1690 spin_lock_irq(&tp
->lock
);
1692 if (tp
->phy_reset_pending(ioaddr
)) {
1694 * A busy loop could burn quite a few cycles on nowadays CPU.
1695 * Let's delay the execution of the timer for a few ticks.
1701 if (tp
->link_ok(ioaddr
))
1704 if (netif_msg_link(tp
))
1705 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1707 tp
->phy_reset_enable(ioaddr
);
1710 mod_timer(timer
, jiffies
+ timeout
);
1712 spin_unlock_irq(&tp
->lock
);
1715 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1717 struct rtl8169_private
*tp
= netdev_priv(dev
);
1718 struct timer_list
*timer
= &tp
->timer
;
1720 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1723 del_timer_sync(timer
);
1726 static inline void rtl8169_request_timer(struct net_device
*dev
)
1728 struct rtl8169_private
*tp
= netdev_priv(dev
);
1729 struct timer_list
*timer
= &tp
->timer
;
1731 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1734 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1737 #ifdef CONFIG_NET_POLL_CONTROLLER
1739 * Polling 'interrupt' - used by things like netconsole to send skbs
1740 * without having to re-enable interrupts. It's not called while
1741 * the interrupt routine is executing.
1743 static void rtl8169_netpoll(struct net_device
*dev
)
1745 struct rtl8169_private
*tp
= netdev_priv(dev
);
1746 struct pci_dev
*pdev
= tp
->pci_dev
;
1748 disable_irq(pdev
->irq
);
1749 rtl8169_interrupt(pdev
->irq
, dev
);
1750 enable_irq(pdev
->irq
);
1754 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1755 void __iomem
*ioaddr
)
1758 pci_release_regions(pdev
);
1759 pci_disable_device(pdev
);
1763 static void rtl8169_phy_reset(struct net_device
*dev
,
1764 struct rtl8169_private
*tp
)
1766 void __iomem
*ioaddr
= tp
->mmio_addr
;
1769 tp
->phy_reset_enable(ioaddr
);
1770 for (i
= 0; i
< 100; i
++) {
1771 if (!tp
->phy_reset_pending(ioaddr
))
1775 if (netif_msg_link(tp
))
1776 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1779 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1781 void __iomem
*ioaddr
= tp
->mmio_addr
;
1783 rtl_hw_phy_config(dev
);
1785 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1786 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1790 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1792 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1793 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1795 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1796 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1798 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1799 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1802 rtl8169_phy_reset(dev
, tp
);
1805 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1806 * only 8101. Don't panic.
1808 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1810 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1811 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1814 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
1816 void __iomem
*ioaddr
= tp
->mmio_addr
;
1820 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1821 high
= addr
[4] | (addr
[5] << 8);
1823 spin_lock_irq(&tp
->lock
);
1825 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1827 RTL_W32(MAC4
, high
);
1828 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1830 spin_unlock_irq(&tp
->lock
);
1833 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1835 struct rtl8169_private
*tp
= netdev_priv(dev
);
1836 struct sockaddr
*addr
= p
;
1838 if (!is_valid_ether_addr(addr
->sa_data
))
1839 return -EADDRNOTAVAIL
;
1841 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1843 rtl_rar_set(tp
, dev
->dev_addr
);
1848 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1850 struct rtl8169_private
*tp
= netdev_priv(dev
);
1851 struct mii_ioctl_data
*data
= if_mii(ifr
);
1853 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
1856 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
1860 data
->phy_id
= 32; /* Internal PHY */
1864 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1868 if (!capable(CAP_NET_ADMIN
))
1870 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1876 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
1881 static const struct rtl_cfg_info
{
1882 void (*hw_start
)(struct net_device
*);
1883 unsigned int region
;
1889 } rtl_cfg_infos
[] = {
1891 .hw_start
= rtl_hw_start_8169
,
1894 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1895 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1896 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1897 .features
= RTL_FEATURE_GMII
,
1898 .default_ver
= RTL_GIGA_MAC_VER_01
,
1901 .hw_start
= rtl_hw_start_8168
,
1904 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1905 TxErr
| TxOK
| RxOK
| RxErr
,
1906 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
1907 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
1908 .default_ver
= RTL_GIGA_MAC_VER_11
,
1911 .hw_start
= rtl_hw_start_8101
,
1914 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1915 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1916 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1917 .features
= RTL_FEATURE_MSI
,
1918 .default_ver
= RTL_GIGA_MAC_VER_13
,
1922 /* Cfg9346_Unlock assumed. */
1923 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
1924 const struct rtl_cfg_info
*cfg
)
1929 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
1930 if (cfg
->features
& RTL_FEATURE_MSI
) {
1931 if (pci_enable_msi(pdev
)) {
1932 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
1935 msi
= RTL_FEATURE_MSI
;
1938 RTL_W8(Config2
, cfg2
);
1942 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
1944 if (tp
->features
& RTL_FEATURE_MSI
) {
1945 pci_disable_msi(pdev
);
1946 tp
->features
&= ~RTL_FEATURE_MSI
;
1950 static const struct net_device_ops rtl8169_netdev_ops
= {
1951 .ndo_open
= rtl8169_open
,
1952 .ndo_stop
= rtl8169_close
,
1953 .ndo_get_stats
= rtl8169_get_stats
,
1954 .ndo_start_xmit
= rtl8169_start_xmit
,
1955 .ndo_tx_timeout
= rtl8169_tx_timeout
,
1956 .ndo_validate_addr
= eth_validate_addr
,
1957 .ndo_change_mtu
= rtl8169_change_mtu
,
1958 .ndo_set_mac_address
= rtl_set_mac_address
,
1959 .ndo_do_ioctl
= rtl8169_ioctl
,
1960 .ndo_set_multicast_list
= rtl_set_rx_mode
,
1961 #ifdef CONFIG_R8169_VLAN
1962 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
1964 #ifdef CONFIG_NET_POLL_CONTROLLER
1965 .ndo_poll_controller
= rtl8169_netpoll
,
1970 static int __devinit
1971 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1973 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
1974 const unsigned int region
= cfg
->region
;
1975 struct rtl8169_private
*tp
;
1976 struct mii_if_info
*mii
;
1977 struct net_device
*dev
;
1978 void __iomem
*ioaddr
;
1982 if (netif_msg_drv(&debug
)) {
1983 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
1984 MODULENAME
, RTL8169_VERSION
);
1987 dev
= alloc_etherdev(sizeof (*tp
));
1989 if (netif_msg_drv(&debug
))
1990 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
1995 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1996 dev
->netdev_ops
= &rtl8169_netdev_ops
;
1997 tp
= netdev_priv(dev
);
2000 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
2004 mii
->mdio_read
= rtl_mdio_read
;
2005 mii
->mdio_write
= rtl_mdio_write
;
2006 mii
->phy_id_mask
= 0x1f;
2007 mii
->reg_num_mask
= 0x1f;
2008 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
2010 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2011 rc
= pci_enable_device(pdev
);
2013 if (netif_msg_probe(tp
))
2014 dev_err(&pdev
->dev
, "enable failure\n");
2015 goto err_out_free_dev_1
;
2018 rc
= pci_set_mwi(pdev
);
2020 goto err_out_disable_2
;
2022 /* make sure PCI base addr 1 is MMIO */
2023 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
2024 if (netif_msg_probe(tp
)) {
2026 "region #%d not an MMIO resource, aborting\n",
2033 /* check for weird/broken PCI region reporting */
2034 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
2035 if (netif_msg_probe(tp
)) {
2037 "Invalid PCI region size(s), aborting\n");
2043 rc
= pci_request_regions(pdev
, MODULENAME
);
2045 if (netif_msg_probe(tp
))
2046 dev_err(&pdev
->dev
, "could not request regions.\n");
2050 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
2052 if ((sizeof(dma_addr_t
) > 4) &&
2053 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
2054 tp
->cp_cmd
|= PCIDAC
;
2055 dev
->features
|= NETIF_F_HIGHDMA
;
2057 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2059 if (netif_msg_probe(tp
)) {
2061 "DMA configuration failed.\n");
2063 goto err_out_free_res_4
;
2067 pci_set_master(pdev
);
2069 /* ioremap MMIO region */
2070 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
2072 if (netif_msg_probe(tp
))
2073 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
2075 goto err_out_free_res_4
;
2078 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
2079 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
2080 dev_info(&pdev
->dev
, "no PCI Express capability\n");
2082 RTL_W16(IntrMask
, 0x0000);
2084 /* Soft reset the chip. */
2085 RTL_W8(ChipCmd
, CmdReset
);
2087 /* Check that the chip has finished the reset. */
2088 for (i
= 0; i
< 100; i
++) {
2089 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2091 msleep_interruptible(1);
2094 RTL_W16(IntrStatus
, 0xffff);
2096 /* Identify chip attached to board */
2097 rtl8169_get_mac_version(tp
, ioaddr
);
2099 /* Use appropriate default if unknown */
2100 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2101 if (netif_msg_probe(tp
)) {
2102 dev_notice(&pdev
->dev
,
2103 "unknown MAC, using family default\n");
2105 tp
->mac_version
= cfg
->default_ver
;
2108 rtl8169_print_mac_version(tp
);
2110 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
2111 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
2114 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
2116 "driver bug, MAC version not found in rtl_chip_info\n");
2121 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2122 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
2123 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
2124 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
2125 tp
->features
|= RTL_FEATURE_WOL
;
2126 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
2127 tp
->features
|= RTL_FEATURE_WOL
;
2128 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
2129 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2131 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
2132 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
2133 tp
->set_speed
= rtl8169_set_speed_tbi
;
2134 tp
->get_settings
= rtl8169_gset_tbi
;
2135 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
2136 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
2137 tp
->link_ok
= rtl8169_tbi_link_ok
;
2138 tp
->do_ioctl
= rtl_tbi_ioctl
;
2140 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
2142 tp
->set_speed
= rtl8169_set_speed_xmii
;
2143 tp
->get_settings
= rtl8169_gset_xmii
;
2144 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
2145 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
2146 tp
->link_ok
= rtl8169_xmii_link_ok
;
2147 tp
->do_ioctl
= rtl_xmii_ioctl
;
2150 spin_lock_init(&tp
->lock
);
2152 tp
->mmio_addr
= ioaddr
;
2154 /* Get MAC address */
2155 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
2156 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
2157 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
2159 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
2160 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
2161 dev
->irq
= pdev
->irq
;
2162 dev
->base_addr
= (unsigned long) ioaddr
;
2164 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
2166 #ifdef CONFIG_R8169_VLAN
2167 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2170 tp
->intr_mask
= 0xffff;
2171 tp
->align
= cfg
->align
;
2172 tp
->hw_start
= cfg
->hw_start
;
2173 tp
->intr_event
= cfg
->intr_event
;
2174 tp
->napi_event
= cfg
->napi_event
;
2176 init_timer(&tp
->timer
);
2177 tp
->timer
.data
= (unsigned long) dev
;
2178 tp
->timer
.function
= rtl8169_phy_timer
;
2180 rc
= register_netdev(dev
);
2184 pci_set_drvdata(pdev
, dev
);
2186 if (netif_msg_probe(tp
)) {
2187 u32 xid
= RTL_R32(TxConfig
) & 0x7cf0f8ff;
2189 printk(KERN_INFO
"%s: %s at 0x%lx, "
2190 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2191 "XID %08x IRQ %d\n",
2193 rtl_chip_info
[tp
->chipset
].name
,
2195 dev
->dev_addr
[0], dev
->dev_addr
[1],
2196 dev
->dev_addr
[2], dev
->dev_addr
[3],
2197 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
2200 rtl8169_init_phy(dev
, tp
);
2201 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
2207 rtl_disable_msi(pdev
, tp
);
2210 pci_release_regions(pdev
);
2212 pci_clear_mwi(pdev
);
2214 pci_disable_device(pdev
);
2220 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
2222 struct net_device
*dev
= pci_get_drvdata(pdev
);
2223 struct rtl8169_private
*tp
= netdev_priv(dev
);
2225 flush_scheduled_work();
2227 unregister_netdev(dev
);
2228 rtl_disable_msi(pdev
, tp
);
2229 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
2230 pci_set_drvdata(pdev
, NULL
);
2233 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
2234 struct net_device
*dev
)
2236 unsigned int mtu
= dev
->mtu
;
2238 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
2241 static int rtl8169_open(struct net_device
*dev
)
2243 struct rtl8169_private
*tp
= netdev_priv(dev
);
2244 struct pci_dev
*pdev
= tp
->pci_dev
;
2245 int retval
= -ENOMEM
;
2248 rtl8169_set_rxbufsize(tp
, dev
);
2251 * Rx and Tx desscriptors needs 256 bytes alignment.
2252 * pci_alloc_consistent provides more.
2254 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
2256 if (!tp
->TxDescArray
)
2259 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
2261 if (!tp
->RxDescArray
)
2264 retval
= rtl8169_init_ring(dev
);
2268 INIT_DELAYED_WORK(&tp
->task
, NULL
);
2272 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
2273 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
2276 goto err_release_ring_2
;
2278 napi_enable(&tp
->napi
);
2282 rtl8169_request_timer(dev
);
2284 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2289 rtl8169_rx_clear(tp
);
2291 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
2294 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
2299 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
2301 /* Disable interrupts */
2302 rtl8169_irq_mask_and_ack(ioaddr
);
2304 /* Reset the chipset */
2305 RTL_W8(ChipCmd
, CmdReset
);
2311 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
2313 void __iomem
*ioaddr
= tp
->mmio_addr
;
2314 u32 cfg
= rtl8169_rx_config
;
2316 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
2317 RTL_W32(RxConfig
, cfg
);
2319 /* Set DMA burst size and Interframe Gap Time */
2320 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2321 (InterFrameGap
<< TxInterFrameGapShift
));
2324 static void rtl_hw_start(struct net_device
*dev
)
2326 struct rtl8169_private
*tp
= netdev_priv(dev
);
2327 void __iomem
*ioaddr
= tp
->mmio_addr
;
2330 /* Soft reset the chip. */
2331 RTL_W8(ChipCmd
, CmdReset
);
2333 /* Check that the chip has finished the reset. */
2334 for (i
= 0; i
< 100; i
++) {
2335 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2337 msleep_interruptible(1);
2342 netif_start_queue(dev
);
2346 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
2347 void __iomem
*ioaddr
)
2350 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2351 * register to be written before TxDescAddrLow to work.
2352 * Switching from MMIO to I/O access fixes the issue as well.
2354 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
2355 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
2356 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
2357 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
2360 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
2364 cmd
= RTL_R16(CPlusCmd
);
2365 RTL_W16(CPlusCmd
, cmd
);
2369 static void rtl_set_rx_max_size(void __iomem
*ioaddr
)
2371 /* Low hurts. Let's disable the filtering. */
2372 RTL_W16(RxMaxSize
, 16383);
2375 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
2382 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
2383 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
2384 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
2385 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
2390 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
2391 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
2392 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
2393 RTL_W32(0x7c, p
->val
);
2399 static void rtl_hw_start_8169(struct net_device
*dev
)
2401 struct rtl8169_private
*tp
= netdev_priv(dev
);
2402 void __iomem
*ioaddr
= tp
->mmio_addr
;
2403 struct pci_dev
*pdev
= tp
->pci_dev
;
2405 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
2406 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
2407 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
2410 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2411 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2412 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2413 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2414 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2415 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2417 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2419 rtl_set_rx_max_size(ioaddr
);
2421 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2422 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2423 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2424 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2425 rtl_set_rx_tx_config_registers(tp
);
2427 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2429 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2430 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2431 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2432 "Bit-3 and bit-14 MUST be 1\n");
2433 tp
->cp_cmd
|= (1 << 14);
2436 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2438 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
2441 * Undocumented corner. Supposedly:
2442 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2444 RTL_W16(IntrMitigate
, 0x0000);
2446 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2448 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2449 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2450 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2451 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2452 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2453 rtl_set_rx_tx_config_registers(tp
);
2456 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2458 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2461 RTL_W32(RxMissed
, 0);
2463 rtl_set_rx_mode(dev
);
2465 /* no early-rx interrupts */
2466 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2468 /* Enable all known interrupts by setting the interrupt mask. */
2469 RTL_W16(IntrMask
, tp
->intr_event
);
2472 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
2474 struct net_device
*dev
= pci_get_drvdata(pdev
);
2475 struct rtl8169_private
*tp
= netdev_priv(dev
);
2476 int cap
= tp
->pcie_cap
;
2481 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2482 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
2483 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2487 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
2491 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
2492 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
2496 unsigned int offset
;
2501 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
2506 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
2507 rtl_ephy_write(ioaddr
, e
->offset
, w
);
2512 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
2514 struct net_device
*dev
= pci_get_drvdata(pdev
);
2515 struct rtl8169_private
*tp
= netdev_priv(dev
);
2516 int cap
= tp
->pcie_cap
;
2521 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
2522 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
2523 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
2527 #define R8168_CPCMD_QUIRK_MASK (\
2538 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2540 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2542 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2544 rtl_tx_performance_tweak(pdev
,
2545 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
2548 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2550 rtl_hw_start_8168bb(ioaddr
, pdev
);
2552 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2554 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
2557 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2559 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
2561 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2563 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2565 rtl_disable_clock_request(pdev
);
2567 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2570 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2572 static struct ephy_info e_info_8168cp
[] = {
2573 { 0x01, 0, 0x0001 },
2574 { 0x02, 0x0800, 0x1000 },
2575 { 0x03, 0, 0x0042 },
2576 { 0x06, 0x0080, 0x0000 },
2580 rtl_csi_access_enable(ioaddr
);
2582 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
2584 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2587 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2589 rtl_csi_access_enable(ioaddr
);
2591 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2593 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2595 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2598 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2600 rtl_csi_access_enable(ioaddr
);
2602 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2605 RTL_W8(DBG_REG
, 0x20);
2607 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2609 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2611 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2614 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2616 static struct ephy_info e_info_8168c_1
[] = {
2617 { 0x02, 0x0800, 0x1000 },
2618 { 0x03, 0, 0x0002 },
2619 { 0x06, 0x0080, 0x0000 }
2622 rtl_csi_access_enable(ioaddr
);
2624 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
2626 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
2628 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2631 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2633 static struct ephy_info e_info_8168c_2
[] = {
2634 { 0x01, 0, 0x0001 },
2635 { 0x03, 0x0400, 0x0220 }
2638 rtl_csi_access_enable(ioaddr
);
2640 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
2642 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2645 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2647 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2650 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2652 rtl_csi_access_enable(ioaddr
);
2654 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2657 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2659 rtl_csi_access_enable(ioaddr
);
2661 rtl_disable_clock_request(pdev
);
2663 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2665 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2667 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2670 static void rtl_hw_start_8168(struct net_device
*dev
)
2672 struct rtl8169_private
*tp
= netdev_priv(dev
);
2673 void __iomem
*ioaddr
= tp
->mmio_addr
;
2674 struct pci_dev
*pdev
= tp
->pci_dev
;
2676 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2678 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2680 rtl_set_rx_max_size(ioaddr
);
2682 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2684 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2686 RTL_W16(IntrMitigate
, 0x5151);
2688 /* Work around for RxFIFO overflow. */
2689 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2690 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2691 tp
->intr_event
&= ~RxOverflow
;
2694 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2696 rtl_set_rx_mode(dev
);
2698 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2699 (InterFrameGap
<< TxInterFrameGapShift
));
2703 switch (tp
->mac_version
) {
2704 case RTL_GIGA_MAC_VER_11
:
2705 rtl_hw_start_8168bb(ioaddr
, pdev
);
2708 case RTL_GIGA_MAC_VER_12
:
2709 case RTL_GIGA_MAC_VER_17
:
2710 rtl_hw_start_8168bef(ioaddr
, pdev
);
2713 case RTL_GIGA_MAC_VER_18
:
2714 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
2717 case RTL_GIGA_MAC_VER_19
:
2718 rtl_hw_start_8168c_1(ioaddr
, pdev
);
2721 case RTL_GIGA_MAC_VER_20
:
2722 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2725 case RTL_GIGA_MAC_VER_21
:
2726 rtl_hw_start_8168c_3(ioaddr
, pdev
);
2729 case RTL_GIGA_MAC_VER_22
:
2730 rtl_hw_start_8168c_4(ioaddr
, pdev
);
2733 case RTL_GIGA_MAC_VER_23
:
2734 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
2737 case RTL_GIGA_MAC_VER_24
:
2738 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
2741 case RTL_GIGA_MAC_VER_25
:
2742 rtl_hw_start_8168d(ioaddr
, pdev
);
2746 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
2747 dev
->name
, tp
->mac_version
);
2751 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2753 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2755 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2757 RTL_W16(IntrMask
, tp
->intr_event
);
2760 #define R810X_CPCMD_QUIRK_MASK (\
2772 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2774 static struct ephy_info e_info_8102e_1
[] = {
2775 { 0x01, 0, 0x6e65 },
2776 { 0x02, 0, 0x091f },
2777 { 0x03, 0, 0xc2f9 },
2778 { 0x06, 0, 0xafb5 },
2779 { 0x07, 0, 0x0e00 },
2780 { 0x19, 0, 0xec80 },
2781 { 0x01, 0, 0x2e65 },
2786 rtl_csi_access_enable(ioaddr
);
2788 RTL_W8(DBG_REG
, FIX_NAK_1
);
2790 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2793 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
2794 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2796 cfg1
= RTL_R8(Config1
);
2797 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
2798 RTL_W8(Config1
, cfg1
& ~LEDS0
);
2800 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2802 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
2805 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2807 rtl_csi_access_enable(ioaddr
);
2809 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2811 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
2812 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2814 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2817 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2819 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2821 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
2824 static void rtl_hw_start_8101(struct net_device
*dev
)
2826 struct rtl8169_private
*tp
= netdev_priv(dev
);
2827 void __iomem
*ioaddr
= tp
->mmio_addr
;
2828 struct pci_dev
*pdev
= tp
->pci_dev
;
2830 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2831 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2832 int cap
= tp
->pcie_cap
;
2835 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
2836 PCI_EXP_DEVCTL_NOSNOOP_EN
);
2840 switch (tp
->mac_version
) {
2841 case RTL_GIGA_MAC_VER_07
:
2842 rtl_hw_start_8102e_1(ioaddr
, pdev
);
2845 case RTL_GIGA_MAC_VER_08
:
2846 rtl_hw_start_8102e_3(ioaddr
, pdev
);
2849 case RTL_GIGA_MAC_VER_09
:
2850 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2854 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2856 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2858 rtl_set_rx_max_size(ioaddr
);
2860 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2862 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2864 RTL_W16(IntrMitigate
, 0x0000);
2866 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2868 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2869 rtl_set_rx_tx_config_registers(tp
);
2871 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2875 rtl_set_rx_mode(dev
);
2877 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2879 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2881 RTL_W16(IntrMask
, tp
->intr_event
);
2884 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
2886 struct rtl8169_private
*tp
= netdev_priv(dev
);
2889 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2894 if (!netif_running(dev
))
2899 rtl8169_set_rxbufsize(tp
, dev
);
2901 ret
= rtl8169_init_ring(dev
);
2905 napi_enable(&tp
->napi
);
2909 rtl8169_request_timer(dev
);
2915 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
2917 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
2918 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2921 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
2922 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2924 struct pci_dev
*pdev
= tp
->pci_dev
;
2926 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2927 PCI_DMA_FROMDEVICE
);
2928 dev_kfree_skb(*sk_buff
);
2930 rtl8169_make_unusable_by_asic(desc
);
2933 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2935 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2937 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2940 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2943 desc
->addr
= cpu_to_le64(mapping
);
2945 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
2948 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
2949 struct net_device
*dev
,
2950 struct RxDesc
*desc
, int rx_buf_sz
,
2953 struct sk_buff
*skb
;
2957 pad
= align
? align
: NET_IP_ALIGN
;
2959 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
2963 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
2965 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
2966 PCI_DMA_FROMDEVICE
);
2968 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
2973 rtl8169_make_unusable_by_asic(desc
);
2977 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
2981 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
2982 if (tp
->Rx_skbuff
[i
]) {
2983 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
2984 tp
->RxDescArray
+ i
);
2989 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
2994 for (cur
= start
; end
- cur
!= 0; cur
++) {
2995 struct sk_buff
*skb
;
2996 unsigned int i
= cur
% NUM_RX_DESC
;
2998 WARN_ON((s32
)(end
- cur
) < 0);
3000 if (tp
->Rx_skbuff
[i
])
3003 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
3004 tp
->RxDescArray
+ i
,
3005 tp
->rx_buf_sz
, tp
->align
);
3009 tp
->Rx_skbuff
[i
] = skb
;
3014 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
3016 desc
->opts1
|= cpu_to_le32(RingEnd
);
3019 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3021 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3024 static int rtl8169_init_ring(struct net_device
*dev
)
3026 struct rtl8169_private
*tp
= netdev_priv(dev
);
3028 rtl8169_init_ring_indexes(tp
);
3030 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
3031 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
3033 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
3036 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
3041 rtl8169_rx_clear(tp
);
3045 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
3046 struct TxDesc
*desc
)
3048 unsigned int len
= tx_skb
->len
;
3050 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
3057 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
3061 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
3062 unsigned int entry
= i
% NUM_TX_DESC
;
3063 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3064 unsigned int len
= tx_skb
->len
;
3067 struct sk_buff
*skb
= tx_skb
->skb
;
3069 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
3070 tp
->TxDescArray
+ entry
);
3075 tp
->dev
->stats
.tx_dropped
++;
3078 tp
->cur_tx
= tp
->dirty_tx
= 0;
3081 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
3083 struct rtl8169_private
*tp
= netdev_priv(dev
);
3085 PREPARE_DELAYED_WORK(&tp
->task
, task
);
3086 schedule_delayed_work(&tp
->task
, 4);
3089 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
3091 struct rtl8169_private
*tp
= netdev_priv(dev
);
3092 void __iomem
*ioaddr
= tp
->mmio_addr
;
3094 synchronize_irq(dev
->irq
);
3096 /* Wait for any pending NAPI task to complete */
3097 napi_disable(&tp
->napi
);
3099 rtl8169_irq_mask_and_ack(ioaddr
);
3101 tp
->intr_mask
= 0xffff;
3102 RTL_W16(IntrMask
, tp
->intr_event
);
3103 napi_enable(&tp
->napi
);
3106 static void rtl8169_reinit_task(struct work_struct
*work
)
3108 struct rtl8169_private
*tp
=
3109 container_of(work
, struct rtl8169_private
, task
.work
);
3110 struct net_device
*dev
= tp
->dev
;
3115 if (!netif_running(dev
))
3118 rtl8169_wait_for_quiescence(dev
);
3121 ret
= rtl8169_open(dev
);
3122 if (unlikely(ret
< 0)) {
3123 if (net_ratelimit() && netif_msg_drv(tp
)) {
3124 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
3125 " Rescheduling.\n", dev
->name
, ret
);
3127 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3134 static void rtl8169_reset_task(struct work_struct
*work
)
3136 struct rtl8169_private
*tp
=
3137 container_of(work
, struct rtl8169_private
, task
.work
);
3138 struct net_device
*dev
= tp
->dev
;
3142 if (!netif_running(dev
))
3145 rtl8169_wait_for_quiescence(dev
);
3147 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
3148 rtl8169_tx_clear(tp
);
3150 if (tp
->dirty_rx
== tp
->cur_rx
) {
3151 rtl8169_init_ring_indexes(tp
);
3153 netif_wake_queue(dev
);
3154 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3156 if (net_ratelimit() && netif_msg_intr(tp
)) {
3157 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
3160 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3167 static void rtl8169_tx_timeout(struct net_device
*dev
)
3169 struct rtl8169_private
*tp
= netdev_priv(dev
);
3171 rtl8169_hw_reset(tp
->mmio_addr
);
3173 /* Let's wait a bit while any (async) irq lands on */
3174 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3177 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
3180 struct skb_shared_info
*info
= skb_shinfo(skb
);
3181 unsigned int cur_frag
, entry
;
3182 struct TxDesc
* uninitialized_var(txd
);
3185 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
3186 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
3191 entry
= (entry
+ 1) % NUM_TX_DESC
;
3193 txd
= tp
->TxDescArray
+ entry
;
3195 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
3196 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
3198 /* anti gcc 2.95.3 bugware (sic) */
3199 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3201 txd
->opts1
= cpu_to_le32(status
);
3202 txd
->addr
= cpu_to_le64(mapping
);
3204 tp
->tx_skb
[entry
].len
= len
;
3208 tp
->tx_skb
[entry
].skb
= skb
;
3209 txd
->opts1
|= cpu_to_le32(LastFrag
);
3215 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
3217 if (dev
->features
& NETIF_F_TSO
) {
3218 u32 mss
= skb_shinfo(skb
)->gso_size
;
3221 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
3223 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
3224 const struct iphdr
*ip
= ip_hdr(skb
);
3226 if (ip
->protocol
== IPPROTO_TCP
)
3227 return IPCS
| TCPCS
;
3228 else if (ip
->protocol
== IPPROTO_UDP
)
3229 return IPCS
| UDPCS
;
3230 WARN_ON(1); /* we need a WARN() */
3235 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3237 struct rtl8169_private
*tp
= netdev_priv(dev
);
3238 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
3239 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
3240 void __iomem
*ioaddr
= tp
->mmio_addr
;
3244 int ret
= NETDEV_TX_OK
;
3246 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
3247 if (netif_msg_drv(tp
)) {
3249 "%s: BUG! Tx Ring full when queue awake!\n",
3255 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
3258 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
3260 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
3262 len
= skb_headlen(skb
);
3266 opts1
|= FirstFrag
| LastFrag
;
3267 tp
->tx_skb
[entry
].skb
= skb
;
3270 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
3272 tp
->tx_skb
[entry
].len
= len
;
3273 txd
->addr
= cpu_to_le64(mapping
);
3274 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
3278 /* anti gcc 2.95.3 bugware (sic) */
3279 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3280 txd
->opts1
= cpu_to_le32(status
);
3282 tp
->cur_tx
+= frags
+ 1;
3286 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
3288 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
3289 netif_stop_queue(dev
);
3291 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
3292 netif_wake_queue(dev
);
3299 netif_stop_queue(dev
);
3300 ret
= NETDEV_TX_BUSY
;
3301 dev
->stats
.tx_dropped
++;
3305 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
3307 struct rtl8169_private
*tp
= netdev_priv(dev
);
3308 struct pci_dev
*pdev
= tp
->pci_dev
;
3309 void __iomem
*ioaddr
= tp
->mmio_addr
;
3310 u16 pci_status
, pci_cmd
;
3312 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
3313 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
3315 if (netif_msg_intr(tp
)) {
3317 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3318 dev
->name
, pci_cmd
, pci_status
);
3322 * The recovery sequence below admits a very elaborated explanation:
3323 * - it seems to work;
3324 * - I did not see what else could be done;
3325 * - it makes iop3xx happy.
3327 * Feel free to adjust to your needs.
3329 if (pdev
->broken_parity_status
)
3330 pci_cmd
&= ~PCI_COMMAND_PARITY
;
3332 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
3334 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
3336 pci_write_config_word(pdev
, PCI_STATUS
,
3337 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
3338 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
3339 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
3341 /* The infamous DAC f*ckup only happens at boot time */
3342 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
3343 if (netif_msg_intr(tp
))
3344 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
3345 tp
->cp_cmd
&= ~PCIDAC
;
3346 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3347 dev
->features
&= ~NETIF_F_HIGHDMA
;
3350 rtl8169_hw_reset(ioaddr
);
3352 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3355 static void rtl8169_tx_interrupt(struct net_device
*dev
,
3356 struct rtl8169_private
*tp
,
3357 void __iomem
*ioaddr
)
3359 unsigned int dirty_tx
, tx_left
;
3361 dirty_tx
= tp
->dirty_tx
;
3363 tx_left
= tp
->cur_tx
- dirty_tx
;
3365 while (tx_left
> 0) {
3366 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
3367 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3368 u32 len
= tx_skb
->len
;
3372 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
3373 if (status
& DescOwn
)
3376 dev
->stats
.tx_bytes
+= len
;
3377 dev
->stats
.tx_packets
++;
3379 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
3381 if (status
& LastFrag
) {
3382 dev_kfree_skb(tx_skb
->skb
);
3389 if (tp
->dirty_tx
!= dirty_tx
) {
3390 tp
->dirty_tx
= dirty_tx
;
3392 if (netif_queue_stopped(dev
) &&
3393 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
3394 netif_wake_queue(dev
);
3397 * 8168 hack: TxPoll requests are lost when the Tx packets are
3398 * too close. Let's kick an extra TxPoll request when a burst
3399 * of start_xmit activity is detected (if it is not detected,
3400 * it is slow enough). -- FR
3403 if (tp
->cur_tx
!= dirty_tx
)
3404 RTL_W8(TxPoll
, NPQ
);
3408 static inline int rtl8169_fragmented_frame(u32 status
)
3410 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
3413 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
3415 u32 opts1
= le32_to_cpu(desc
->opts1
);
3416 u32 status
= opts1
& RxProtoMask
;
3418 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
3419 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
3420 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
3421 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3423 skb
->ip_summed
= CHECKSUM_NONE
;
3426 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
3427 struct rtl8169_private
*tp
, int pkt_size
,
3430 struct sk_buff
*skb
;
3433 if (pkt_size
>= rx_copybreak
)
3436 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
3440 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
3441 PCI_DMA_FROMDEVICE
);
3442 skb_reserve(skb
, NET_IP_ALIGN
);
3443 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
3450 static int rtl8169_rx_interrupt(struct net_device
*dev
,
3451 struct rtl8169_private
*tp
,
3452 void __iomem
*ioaddr
, u32 budget
)
3454 unsigned int cur_rx
, rx_left
;
3455 unsigned int delta
, count
;
3457 cur_rx
= tp
->cur_rx
;
3458 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
3459 rx_left
= min(rx_left
, budget
);
3461 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
3462 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
3463 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
3467 status
= le32_to_cpu(desc
->opts1
);
3469 if (status
& DescOwn
)
3471 if (unlikely(status
& RxRES
)) {
3472 if (netif_msg_rx_err(tp
)) {
3474 "%s: Rx ERROR. status = %08x\n",
3477 dev
->stats
.rx_errors
++;
3478 if (status
& (RxRWT
| RxRUNT
))
3479 dev
->stats
.rx_length_errors
++;
3481 dev
->stats
.rx_crc_errors
++;
3482 if (status
& RxFOVF
) {
3483 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3484 dev
->stats
.rx_fifo_errors
++;
3486 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3488 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
3489 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
3490 int pkt_size
= (status
& 0x00001FFF) - 4;
3491 struct pci_dev
*pdev
= tp
->pci_dev
;
3494 * The driver does not support incoming fragmented
3495 * frames. They are seen as a symptom of over-mtu
3498 if (unlikely(rtl8169_fragmented_frame(status
))) {
3499 dev
->stats
.rx_dropped
++;
3500 dev
->stats
.rx_length_errors
++;
3501 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3505 rtl8169_rx_csum(skb
, desc
);
3507 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
3508 pci_dma_sync_single_for_device(pdev
, addr
,
3509 pkt_size
, PCI_DMA_FROMDEVICE
);
3510 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3512 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
3513 PCI_DMA_FROMDEVICE
);
3514 tp
->Rx_skbuff
[entry
] = NULL
;
3517 skb_put(skb
, pkt_size
);
3518 skb
->protocol
= eth_type_trans(skb
, dev
);
3520 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
3521 netif_receive_skb(skb
);
3523 dev
->stats
.rx_bytes
+= pkt_size
;
3524 dev
->stats
.rx_packets
++;
3527 /* Work around for AMD plateform. */
3528 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
3529 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
3535 count
= cur_rx
- tp
->cur_rx
;
3536 tp
->cur_rx
= cur_rx
;
3538 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
3539 if (!delta
&& count
&& netif_msg_intr(tp
))
3540 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
3541 tp
->dirty_rx
+= delta
;
3544 * FIXME: until there is periodic timer to try and refill the ring,
3545 * a temporary shortage may definitely kill the Rx process.
3546 * - disable the asic to try and avoid an overflow and kick it again
3548 * - how do others driver handle this condition (Uh oh...).
3550 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
3551 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
3556 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
3558 struct net_device
*dev
= dev_instance
;
3559 struct rtl8169_private
*tp
= netdev_priv(dev
);
3560 void __iomem
*ioaddr
= tp
->mmio_addr
;
3564 /* loop handling interrupts until we have no new ones or
3565 * we hit a invalid/hotplug case.
3567 status
= RTL_R16(IntrStatus
);
3568 while (status
&& status
!= 0xffff) {
3571 /* Handle all of the error cases first. These will reset
3572 * the chip, so just exit the loop.
3574 if (unlikely(!netif_running(dev
))) {
3575 rtl8169_asic_down(ioaddr
);
3579 /* Work around for rx fifo overflow */
3580 if (unlikely(status
& RxFIFOOver
) &&
3581 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
3582 netif_stop_queue(dev
);
3583 rtl8169_tx_timeout(dev
);
3587 if (unlikely(status
& SYSErr
)) {
3588 rtl8169_pcierr_interrupt(dev
);
3592 if (status
& LinkChg
)
3593 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3595 /* We need to see the lastest version of tp->intr_mask to
3596 * avoid ignoring an MSI interrupt and having to wait for
3597 * another event which may never come.
3600 if (status
& tp
->intr_mask
& tp
->napi_event
) {
3601 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
3602 tp
->intr_mask
= ~tp
->napi_event
;
3604 if (likely(napi_schedule_prep(&tp
->napi
)))
3605 __napi_schedule(&tp
->napi
);
3606 else if (netif_msg_intr(tp
)) {
3607 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
3612 /* We only get a new MSI interrupt when all active irq
3613 * sources on the chip have been acknowledged. So, ack
3614 * everything we've seen and check if new sources have become
3615 * active to avoid blocking all interrupts from the chip.
3618 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
3619 status
= RTL_R16(IntrStatus
);
3622 return IRQ_RETVAL(handled
);
3625 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
3627 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
3628 struct net_device
*dev
= tp
->dev
;
3629 void __iomem
*ioaddr
= tp
->mmio_addr
;
3632 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
3633 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
3635 if (work_done
< budget
) {
3636 napi_complete(napi
);
3638 /* We need for force the visibility of tp->intr_mask
3639 * for other CPUs, as we can loose an MSI interrupt
3640 * and potentially wait for a retransmit timeout if we don't.
3641 * The posted write to IntrMask is safe, as it will
3642 * eventually make it to the chip and we won't loose anything
3645 tp
->intr_mask
= 0xffff;
3647 RTL_W16(IntrMask
, tp
->intr_event
);
3653 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
3655 struct rtl8169_private
*tp
= netdev_priv(dev
);
3657 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
3660 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
3661 RTL_W32(RxMissed
, 0);
3664 static void rtl8169_down(struct net_device
*dev
)
3666 struct rtl8169_private
*tp
= netdev_priv(dev
);
3667 void __iomem
*ioaddr
= tp
->mmio_addr
;
3668 unsigned int intrmask
;
3670 rtl8169_delete_timer(dev
);
3672 netif_stop_queue(dev
);
3674 napi_disable(&tp
->napi
);
3677 spin_lock_irq(&tp
->lock
);
3679 rtl8169_asic_down(ioaddr
);
3681 rtl8169_rx_missed(dev
, ioaddr
);
3683 spin_unlock_irq(&tp
->lock
);
3685 synchronize_irq(dev
->irq
);
3687 /* Give a racing hard_start_xmit a few cycles to complete. */
3688 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3691 * And now for the 50k$ question: are IRQ disabled or not ?
3693 * Two paths lead here:
3695 * -> netif_running() is available to sync the current code and the
3696 * IRQ handler. See rtl8169_interrupt for details.
3697 * 2) dev->change_mtu
3698 * -> rtl8169_poll can not be issued again and re-enable the
3699 * interruptions. Let's simply issue the IRQ down sequence again.
3701 * No loop if hotpluged or major error (0xffff).
3703 intrmask
= RTL_R16(IntrMask
);
3704 if (intrmask
&& (intrmask
!= 0xffff))
3707 rtl8169_tx_clear(tp
);
3709 rtl8169_rx_clear(tp
);
3712 static int rtl8169_close(struct net_device
*dev
)
3714 struct rtl8169_private
*tp
= netdev_priv(dev
);
3715 struct pci_dev
*pdev
= tp
->pci_dev
;
3717 /* update counters before going down */
3718 rtl8169_update_counters(dev
);
3722 free_irq(dev
->irq
, dev
);
3724 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3726 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3728 tp
->TxDescArray
= NULL
;
3729 tp
->RxDescArray
= NULL
;
3734 static void rtl_set_rx_mode(struct net_device
*dev
)
3736 struct rtl8169_private
*tp
= netdev_priv(dev
);
3737 void __iomem
*ioaddr
= tp
->mmio_addr
;
3738 unsigned long flags
;
3739 u32 mc_filter
[2]; /* Multicast hash filter */
3743 if (dev
->flags
& IFF_PROMISC
) {
3744 /* Unconditionally log net taps. */
3745 if (netif_msg_link(tp
)) {
3746 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3750 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3752 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3753 } else if ((dev
->mc_count
> multicast_filter_limit
)
3754 || (dev
->flags
& IFF_ALLMULTI
)) {
3755 /* Too many to filter perfectly -- accept all multicasts. */
3756 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3757 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3759 struct dev_mc_list
*mclist
;
3762 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3763 mc_filter
[1] = mc_filter
[0] = 0;
3764 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3765 i
++, mclist
= mclist
->next
) {
3766 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3767 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3768 rx_mode
|= AcceptMulticast
;
3772 spin_lock_irqsave(&tp
->lock
, flags
);
3774 tmp
= rtl8169_rx_config
| rx_mode
|
3775 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3777 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3778 u32 data
= mc_filter
[0];
3780 mc_filter
[0] = swab32(mc_filter
[1]);
3781 mc_filter
[1] = swab32(data
);
3784 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3785 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3787 RTL_W32(RxConfig
, tmp
);
3789 spin_unlock_irqrestore(&tp
->lock
, flags
);
3793 * rtl8169_get_stats - Get rtl8169 read/write statistics
3794 * @dev: The Ethernet Device to get statistics for
3796 * Get TX/RX statistics for rtl8169
3798 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3800 struct rtl8169_private
*tp
= netdev_priv(dev
);
3801 void __iomem
*ioaddr
= tp
->mmio_addr
;
3802 unsigned long flags
;
3804 if (netif_running(dev
)) {
3805 spin_lock_irqsave(&tp
->lock
, flags
);
3806 rtl8169_rx_missed(dev
, ioaddr
);
3807 spin_unlock_irqrestore(&tp
->lock
, flags
);
3813 static void rtl8169_net_suspend(struct net_device
*dev
)
3815 struct rtl8169_private
*tp
= netdev_priv(dev
);
3816 void __iomem
*ioaddr
= tp
->mmio_addr
;
3818 if (!netif_running(dev
))
3821 netif_device_detach(dev
);
3822 netif_stop_queue(dev
);
3824 spin_lock_irq(&tp
->lock
);
3826 rtl8169_asic_down(ioaddr
);
3828 rtl8169_rx_missed(dev
, ioaddr
);
3830 spin_unlock_irq(&tp
->lock
);
3835 static int rtl8169_suspend(struct device
*device
)
3837 struct pci_dev
*pdev
= to_pci_dev(device
);
3838 struct net_device
*dev
= pci_get_drvdata(pdev
);
3840 rtl8169_net_suspend(dev
);
3845 static int rtl8169_resume(struct device
*device
)
3847 struct pci_dev
*pdev
= to_pci_dev(device
);
3848 struct net_device
*dev
= pci_get_drvdata(pdev
);
3850 if (!netif_running(dev
))
3853 netif_device_attach(dev
);
3855 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3860 static struct dev_pm_ops rtl8169_pm_ops
= {
3861 .suspend
= rtl8169_suspend
,
3862 .resume
= rtl8169_resume
,
3863 .freeze
= rtl8169_suspend
,
3864 .thaw
= rtl8169_resume
,
3865 .poweroff
= rtl8169_suspend
,
3866 .restore
= rtl8169_resume
,
3869 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
3871 #else /* !CONFIG_PM */
3873 #define RTL8169_PM_OPS NULL
3875 #endif /* !CONFIG_PM */
3877 static void rtl_shutdown(struct pci_dev
*pdev
)
3879 struct net_device
*dev
= pci_get_drvdata(pdev
);
3881 rtl8169_net_suspend(dev
);
3883 if (system_state
== SYSTEM_POWER_OFF
) {
3884 pci_wake_from_d3(pdev
, true);
3885 pci_set_power_state(pdev
, PCI_D3hot
);
3889 static struct pci_driver rtl8169_pci_driver
= {
3891 .id_table
= rtl8169_pci_tbl
,
3892 .probe
= rtl8169_init_one
,
3893 .remove
= __devexit_p(rtl8169_remove_one
),
3894 .shutdown
= rtl_shutdown
,
3895 .driver
.pm
= RTL8169_PM_OPS
,
3898 static int __init
rtl8169_init_module(void)
3900 return pci_register_driver(&rtl8169_pci_driver
);
3903 static void __exit
rtl8169_cleanup_module(void)
3905 pci_unregister_driver(&rtl8169_pci_driver
);
3908 module_init(rtl8169_init_module
);
3909 module_exit(rtl8169_cleanup_module
);