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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph...
[mirror_ubuntu-zesty-kernel.git] / drivers / net / r8169.c
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28
29 #include <asm/system.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
36
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
40 #ifdef RTL8169_DEBUG
41 #define assert(expr) \
42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
44 #expr,__FILE__,__func__,__LINE__); \
45 }
46 #define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
48 #else
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
52
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
55
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
62
63 /* MAC address length */
64 #define MAC_ADDR_LEN 6
65
66 #define MAX_READ_REQUEST_SHIFT 12
67 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
83
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
87
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) readl (ioaddr + (reg))
95
96 enum mac_version {
97 RTL_GIGA_MAC_NONE = 0x00,
98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
126 };
127
128 #define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
130
131 static const struct {
132 const char *name;
133 u8 mac_version;
134 u32 RxConfigMask; /* Clears the bits supported by this chip */
135 } rtl_chip_info[] = {
136 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
142 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
150 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
164 };
165 #undef _R
166
167 enum cfg_version {
168 RTL_CFG_0 = 0x00,
169 RTL_CFG_1,
170 RTL_CFG_2
171 };
172
173 static void rtl_hw_start_8169(struct net_device *);
174 static void rtl_hw_start_8168(struct net_device *);
175 static void rtl_hw_start_8101(struct net_device *);
176
177 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
184 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
186 { PCI_VENDOR_ID_LINKSYS, 0x1032,
187 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
188 { 0x0001, 0x8168,
189 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
190 {0,},
191 };
192
193 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
195 static int rx_buf_sz = 16383;
196 static int use_dac;
197 static struct {
198 u32 msg_enable;
199 } debug = { -1 };
200
201 enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
203 MAC4 = 4,
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
236
237 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
238
239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
240
241 #define TxPacketMax (8064 >> 7)
242
243 FuncEvent = 0xf0,
244 FuncEventMask = 0xf4,
245 FuncPresetState = 0xf8,
246 FuncForceEvent = 0xfc,
247 };
248
249 enum rtl8110_registers {
250 TBICSR = 0x64,
251 TBI_ANAR = 0x68,
252 TBI_LPAR = 0x6a,
253 };
254
255 enum rtl8168_8101_registers {
256 CSIDR = 0x64,
257 CSIAR = 0x68,
258 #define CSIAR_FLAG 0x80000000
259 #define CSIAR_WRITE_CMD 0x80000000
260 #define CSIAR_BYTE_ENABLE 0x0f
261 #define CSIAR_BYTE_ENABLE_SHIFT 12
262 #define CSIAR_ADDR_MASK 0x0fff
263 PMCH = 0x6f,
264 EPHYAR = 0x80,
265 #define EPHYAR_FLAG 0x80000000
266 #define EPHYAR_WRITE_CMD 0x80000000
267 #define EPHYAR_REG_MASK 0x1f
268 #define EPHYAR_REG_SHIFT 16
269 #define EPHYAR_DATA_MASK 0xffff
270 DBG_REG = 0xd1,
271 #define FIX_NAK_1 (1 << 4)
272 #define FIX_NAK_2 (1 << 3)
273 EFUSEAR = 0xdc,
274 #define EFUSEAR_FLAG 0x80000000
275 #define EFUSEAR_WRITE_CMD 0x80000000
276 #define EFUSEAR_READ_CMD 0x00000000
277 #define EFUSEAR_REG_MASK 0x03ff
278 #define EFUSEAR_REG_SHIFT 8
279 #define EFUSEAR_DATA_MASK 0xff
280 };
281
282 enum rtl8168_registers {
283 ERIDR = 0x70,
284 ERIAR = 0x74,
285 #define ERIAR_FLAG 0x80000000
286 #define ERIAR_WRITE_CMD 0x80000000
287 #define ERIAR_READ_CMD 0x00000000
288 #define ERIAR_ADDR_BYTE_ALIGN 4
289 #define ERIAR_EXGMAC 0
290 #define ERIAR_MSIX 1
291 #define ERIAR_ASF 2
292 #define ERIAR_TYPE_SHIFT 16
293 #define ERIAR_BYTEEN 0x0f
294 #define ERIAR_BYTEEN_SHIFT 12
295 EPHY_RXER_NUM = 0x7c,
296 OCPDR = 0xb0, /* OCP GPHY access */
297 #define OCPDR_WRITE_CMD 0x80000000
298 #define OCPDR_READ_CMD 0x00000000
299 #define OCPDR_REG_MASK 0x7f
300 #define OCPDR_GPHY_REG_SHIFT 16
301 #define OCPDR_DATA_MASK 0xffff
302 OCPAR = 0xb4,
303 #define OCPAR_FLAG 0x80000000
304 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
305 #define OCPAR_GPHY_READ_CMD 0x0000f060
306 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
307 };
308
309 enum rtl_register_content {
310 /* InterruptStatusBits */
311 SYSErr = 0x8000,
312 PCSTimeout = 0x4000,
313 SWInt = 0x0100,
314 TxDescUnavail = 0x0080,
315 RxFIFOOver = 0x0040,
316 LinkChg = 0x0020,
317 RxOverflow = 0x0010,
318 TxErr = 0x0008,
319 TxOK = 0x0004,
320 RxErr = 0x0002,
321 RxOK = 0x0001,
322
323 /* RxStatusDesc */
324 RxFOVF = (1 << 23),
325 RxRWT = (1 << 22),
326 RxRES = (1 << 21),
327 RxRUNT = (1 << 20),
328 RxCRC = (1 << 19),
329
330 /* ChipCmdBits */
331 CmdReset = 0x10,
332 CmdRxEnb = 0x08,
333 CmdTxEnb = 0x04,
334 RxBufEmpty = 0x01,
335
336 /* TXPoll register p.5 */
337 HPQ = 0x80, /* Poll cmd on the high prio queue */
338 NPQ = 0x40, /* Poll cmd on the low prio queue */
339 FSWInt = 0x01, /* Forced software interrupt */
340
341 /* Cfg9346Bits */
342 Cfg9346_Lock = 0x00,
343 Cfg9346_Unlock = 0xc0,
344
345 /* rx_mode_bits */
346 AcceptErr = 0x20,
347 AcceptRunt = 0x10,
348 AcceptBroadcast = 0x08,
349 AcceptMulticast = 0x04,
350 AcceptMyPhys = 0x02,
351 AcceptAllPhys = 0x01,
352
353 /* RxConfigBits */
354 RxCfgFIFOShift = 13,
355 RxCfgDMAShift = 8,
356
357 /* TxConfigBits */
358 TxInterFrameGapShift = 24,
359 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
360
361 /* Config1 register p.24 */
362 LEDS1 = (1 << 7),
363 LEDS0 = (1 << 6),
364 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
365 Speed_down = (1 << 4),
366 MEMMAP = (1 << 3),
367 IOMAP = (1 << 2),
368 VPD = (1 << 1),
369 PMEnable = (1 << 0), /* Power Management Enable */
370
371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz = 0x01,
373 PCI_Clock_33MHz = 0x00,
374
375 /* Config3 register p.25 */
376 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
378 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
379
380 /* Config5 register p.27 */
381 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF = (1 << 5), /* Accept Multicast wakeup frame */
383 UWF = (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake = (1 << 1), /* LanWake enable/disable */
385 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
386
387 /* TBICSR p.28 */
388 TBIReset = 0x80000000,
389 TBILoopback = 0x40000000,
390 TBINwEnable = 0x20000000,
391 TBINwRestart = 0x10000000,
392 TBILinkOk = 0x02000000,
393 TBINwComplete = 0x01000000,
394
395 /* CPlusCmd p.31 */
396 EnableBist = (1 << 15), // 8168 8101
397 Mac_dbgo_oe = (1 << 14), // 8168 8101
398 Normal_mode = (1 << 13), // unused
399 Force_half_dup = (1 << 12), // 8168 8101
400 Force_rxflow_en = (1 << 11), // 8168 8101
401 Force_txflow_en = (1 << 10), // 8168 8101
402 Cxpl_dbg_sel = (1 << 9), // 8168 8101
403 ASF = (1 << 8), // 8168 8101
404 PktCntrDisable = (1 << 7), // 8168 8101
405 Mac_dbgo_sel = 0x001c, // 8168
406 RxVlan = (1 << 6),
407 RxChkSum = (1 << 5),
408 PCIDAC = (1 << 4),
409 PCIMulRW = (1 << 3),
410 INTT_0 = 0x0000, // 8168
411 INTT_1 = 0x0001, // 8168
412 INTT_2 = 0x0002, // 8168
413 INTT_3 = 0x0003, // 8168
414
415 /* rtl8169_PHYstatus */
416 TBI_Enable = 0x80,
417 TxFlowCtrl = 0x40,
418 RxFlowCtrl = 0x20,
419 _1000bpsF = 0x10,
420 _100bps = 0x08,
421 _10bps = 0x04,
422 LinkStatus = 0x02,
423 FullDup = 0x01,
424
425 /* _TBICSRBit */
426 TBILinkOK = 0x02000000,
427
428 /* DumpCounterCommand */
429 CounterDump = 0x8,
430 };
431
432 enum desc_status_bit {
433 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd = (1 << 30), /* End of descriptor ring */
435 FirstFrag = (1 << 29), /* First segment of a packet */
436 LastFrag = (1 << 28), /* Final segment of a packet */
437
438 /* Tx private */
439 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift = 16, /* MSS value position */
441 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS = (1 << 18), /* Calculate IP checksum */
443 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag = (1 << 17), /* Add VLAN tag */
446
447 /* Rx private */
448 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
449 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
450
451 #define RxProtoUDP (PID1)
452 #define RxProtoTCP (PID0)
453 #define RxProtoIP (PID1 | PID0)
454 #define RxProtoMask RxProtoIP
455
456 IPFail = (1 << 16), /* IP checksum failed */
457 UDPFail = (1 << 15), /* UDP/IP checksum failed */
458 TCPFail = (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag = (1 << 16), /* VLAN tag available */
460 };
461
462 #define RsvdMask 0x3fffc000
463
464 struct TxDesc {
465 __le32 opts1;
466 __le32 opts2;
467 __le64 addr;
468 };
469
470 struct RxDesc {
471 __le32 opts1;
472 __le32 opts2;
473 __le64 addr;
474 };
475
476 struct ring_info {
477 struct sk_buff *skb;
478 u32 len;
479 u8 __pad[sizeof(void *) - sizeof(u32)];
480 };
481
482 enum features {
483 RTL_FEATURE_WOL = (1 << 0),
484 RTL_FEATURE_MSI = (1 << 1),
485 RTL_FEATURE_GMII = (1 << 2),
486 };
487
488 struct rtl8169_counters {
489 __le64 tx_packets;
490 __le64 rx_packets;
491 __le64 tx_errors;
492 __le32 rx_errors;
493 __le16 rx_missed;
494 __le16 align_errors;
495 __le32 tx_one_collision;
496 __le32 tx_multi_collision;
497 __le64 rx_unicast;
498 __le64 rx_broadcast;
499 __le32 rx_multicast;
500 __le16 tx_aborted;
501 __le16 tx_underun;
502 };
503
504 struct rtl8169_private {
505 void __iomem *mmio_addr; /* memory map physical address */
506 struct pci_dev *pci_dev; /* Index of PCI device */
507 struct net_device *dev;
508 struct napi_struct napi;
509 spinlock_t lock; /* spin lock flag */
510 u32 msg_enable;
511 int chipset;
512 int mac_version;
513 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
515 u32 dirty_rx;
516 u32 dirty_tx;
517 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
518 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr;
520 dma_addr_t RxPhyAddr;
521 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
522 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
523 struct timer_list timer;
524 u16 cp_cmd;
525 u16 intr_event;
526 u16 napi_event;
527 u16 intr_mask;
528 int phy_1000_ctrl_reg;
529 #ifdef CONFIG_R8169_VLAN
530 struct vlan_group *vlgrp;
531 #endif
532
533 struct mdio_ops {
534 void (*write)(void __iomem *, int, int);
535 int (*read)(void __iomem *, int);
536 } mdio_ops;
537
538 struct pll_power_ops {
539 void (*down)(struct rtl8169_private *);
540 void (*up)(struct rtl8169_private *);
541 } pll_power_ops;
542
543 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
544 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
545 void (*phy_reset_enable)(struct rtl8169_private *tp);
546 void (*hw_start)(struct net_device *);
547 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
548 unsigned int (*link_ok)(void __iomem *);
549 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
550 int pcie_cap;
551 struct delayed_work task;
552 unsigned features;
553
554 struct mii_if_info mii;
555 struct rtl8169_counters counters;
556 u32 saved_wolopts;
557
558 const struct firmware *fw;
559 };
560
561 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
562 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
563 module_param(use_dac, int, 0);
564 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
565 module_param_named(debug, debug.msg_enable, int, 0);
566 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
567 MODULE_LICENSE("GPL");
568 MODULE_VERSION(RTL8169_VERSION);
569 MODULE_FIRMWARE(FIRMWARE_8168D_1);
570 MODULE_FIRMWARE(FIRMWARE_8168D_2);
571
572 static int rtl8169_open(struct net_device *dev);
573 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
574 struct net_device *dev);
575 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
576 static int rtl8169_init_ring(struct net_device *dev);
577 static void rtl_hw_start(struct net_device *dev);
578 static int rtl8169_close(struct net_device *dev);
579 static void rtl_set_rx_mode(struct net_device *dev);
580 static void rtl8169_tx_timeout(struct net_device *dev);
581 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
582 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
583 void __iomem *, u32 budget);
584 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
585 static void rtl8169_down(struct net_device *dev);
586 static void rtl8169_rx_clear(struct rtl8169_private *tp);
587 static int rtl8169_poll(struct napi_struct *napi, int budget);
588
589 static const unsigned int rtl8169_rx_config =
590 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
591
592 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
593 {
594 void __iomem *ioaddr = tp->mmio_addr;
595 int i;
596
597 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
598 for (i = 0; i < 20; i++) {
599 udelay(100);
600 if (RTL_R32(OCPAR) & OCPAR_FLAG)
601 break;
602 }
603 return RTL_R32(OCPDR);
604 }
605
606 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
607 {
608 void __iomem *ioaddr = tp->mmio_addr;
609 int i;
610
611 RTL_W32(OCPDR, data);
612 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
613 for (i = 0; i < 20; i++) {
614 udelay(100);
615 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
616 break;
617 }
618 }
619
620 static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
621 {
622 int i;
623
624 RTL_W8(ERIDR, cmd);
625 RTL_W32(ERIAR, 0x800010e8);
626 msleep(2);
627 for (i = 0; i < 5; i++) {
628 udelay(100);
629 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
630 break;
631 }
632
633 ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
634 }
635
636 #define OOB_CMD_RESET 0x00
637 #define OOB_CMD_DRIVER_START 0x05
638 #define OOB_CMD_DRIVER_STOP 0x06
639
640 static void rtl8168_driver_start(struct rtl8169_private *tp)
641 {
642 int i;
643
644 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
645
646 for (i = 0; i < 10; i++) {
647 msleep(10);
648 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
649 break;
650 }
651 }
652
653 static void rtl8168_driver_stop(struct rtl8169_private *tp)
654 {
655 int i;
656
657 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
658
659 for (i = 0; i < 10; i++) {
660 msleep(10);
661 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
662 break;
663 }
664 }
665
666
667 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
668 {
669 int i;
670
671 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
672
673 for (i = 20; i > 0; i--) {
674 /*
675 * Check if the RTL8169 has completed writing to the specified
676 * MII register.
677 */
678 if (!(RTL_R32(PHYAR) & 0x80000000))
679 break;
680 udelay(25);
681 }
682 /*
683 * According to hardware specs a 20us delay is required after write
684 * complete indication, but before sending next command.
685 */
686 udelay(20);
687 }
688
689 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
690 {
691 int i, value = -1;
692
693 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
694
695 for (i = 20; i > 0; i--) {
696 /*
697 * Check if the RTL8169 has completed retrieving data from
698 * the specified MII register.
699 */
700 if (RTL_R32(PHYAR) & 0x80000000) {
701 value = RTL_R32(PHYAR) & 0xffff;
702 break;
703 }
704 udelay(25);
705 }
706 /*
707 * According to hardware specs a 20us delay is required after read
708 * complete indication, but before sending next command.
709 */
710 udelay(20);
711
712 return value;
713 }
714
715 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
716 {
717 int i;
718
719 RTL_W32(OCPDR, data |
720 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
721 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
722 RTL_W32(EPHY_RXER_NUM, 0);
723
724 for (i = 0; i < 100; i++) {
725 mdelay(1);
726 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
727 break;
728 }
729 }
730
731 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
732 {
733 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
734 (value & OCPDR_DATA_MASK));
735 }
736
737 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
738 {
739 int i;
740
741 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
742
743 mdelay(1);
744 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
745 RTL_W32(EPHY_RXER_NUM, 0);
746
747 for (i = 0; i < 100; i++) {
748 mdelay(1);
749 if (RTL_R32(OCPAR) & OCPAR_FLAG)
750 break;
751 }
752
753 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
754 }
755
756 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
757
758 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
759 {
760 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
761 }
762
763 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
764 {
765 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
766 }
767
768 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
769 {
770 r8168dp_2_mdio_start(ioaddr);
771
772 r8169_mdio_write(ioaddr, reg_addr, value);
773
774 r8168dp_2_mdio_stop(ioaddr);
775 }
776
777 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
778 {
779 int value;
780
781 r8168dp_2_mdio_start(ioaddr);
782
783 value = r8169_mdio_read(ioaddr, reg_addr);
784
785 r8168dp_2_mdio_stop(ioaddr);
786
787 return value;
788 }
789
790 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
791 {
792 tp->mdio_ops.write(tp->mmio_addr, location, val);
793 }
794
795 static int rtl_readphy(struct rtl8169_private *tp, int location)
796 {
797 return tp->mdio_ops.read(tp->mmio_addr, location);
798 }
799
800 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
801 {
802 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
803 }
804
805 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
806 {
807 int val;
808
809 val = rtl_readphy(tp, reg_addr);
810 rtl_writephy(tp, reg_addr, (val | p) & ~m);
811 }
812
813 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
814 int val)
815 {
816 struct rtl8169_private *tp = netdev_priv(dev);
817
818 rtl_writephy(tp, location, val);
819 }
820
821 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
822 {
823 struct rtl8169_private *tp = netdev_priv(dev);
824
825 return rtl_readphy(tp, location);
826 }
827
828 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
829 {
830 unsigned int i;
831
832 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
833 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
834
835 for (i = 0; i < 100; i++) {
836 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
837 break;
838 udelay(10);
839 }
840 }
841
842 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
843 {
844 u16 value = 0xffff;
845 unsigned int i;
846
847 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
848
849 for (i = 0; i < 100; i++) {
850 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
851 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
852 break;
853 }
854 udelay(10);
855 }
856
857 return value;
858 }
859
860 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
861 {
862 unsigned int i;
863
864 RTL_W32(CSIDR, value);
865 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
866 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
867
868 for (i = 0; i < 100; i++) {
869 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
870 break;
871 udelay(10);
872 }
873 }
874
875 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
876 {
877 u32 value = ~0x00;
878 unsigned int i;
879
880 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
881 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
882
883 for (i = 0; i < 100; i++) {
884 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
885 value = RTL_R32(CSIDR);
886 break;
887 }
888 udelay(10);
889 }
890
891 return value;
892 }
893
894 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
895 {
896 u8 value = 0xff;
897 unsigned int i;
898
899 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
900
901 for (i = 0; i < 300; i++) {
902 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
903 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
904 break;
905 }
906 udelay(100);
907 }
908
909 return value;
910 }
911
912 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
913 {
914 RTL_W16(IntrMask, 0x0000);
915
916 RTL_W16(IntrStatus, 0xffff);
917 }
918
919 static void rtl8169_asic_down(void __iomem *ioaddr)
920 {
921 RTL_W8(ChipCmd, 0x00);
922 rtl8169_irq_mask_and_ack(ioaddr);
923 RTL_R16(CPlusCmd);
924 }
925
926 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
927 {
928 void __iomem *ioaddr = tp->mmio_addr;
929
930 return RTL_R32(TBICSR) & TBIReset;
931 }
932
933 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
934 {
935 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
936 }
937
938 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
939 {
940 return RTL_R32(TBICSR) & TBILinkOk;
941 }
942
943 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
944 {
945 return RTL_R8(PHYstatus) & LinkStatus;
946 }
947
948 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
949 {
950 void __iomem *ioaddr = tp->mmio_addr;
951
952 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
953 }
954
955 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
956 {
957 unsigned int val;
958
959 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
960 rtl_writephy(tp, MII_BMCR, val & 0xffff);
961 }
962
963 static void __rtl8169_check_link_status(struct net_device *dev,
964 struct rtl8169_private *tp,
965 void __iomem *ioaddr,
966 bool pm)
967 {
968 unsigned long flags;
969
970 spin_lock_irqsave(&tp->lock, flags);
971 if (tp->link_ok(ioaddr)) {
972 /* This is to cancel a scheduled suspend if there's one. */
973 if (pm)
974 pm_request_resume(&tp->pci_dev->dev);
975 netif_carrier_on(dev);
976 if (net_ratelimit())
977 netif_info(tp, ifup, dev, "link up\n");
978 } else {
979 netif_carrier_off(dev);
980 netif_info(tp, ifdown, dev, "link down\n");
981 if (pm)
982 pm_schedule_suspend(&tp->pci_dev->dev, 100);
983 }
984 spin_unlock_irqrestore(&tp->lock, flags);
985 }
986
987 static void rtl8169_check_link_status(struct net_device *dev,
988 struct rtl8169_private *tp,
989 void __iomem *ioaddr)
990 {
991 __rtl8169_check_link_status(dev, tp, ioaddr, false);
992 }
993
994 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
995
996 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
997 {
998 void __iomem *ioaddr = tp->mmio_addr;
999 u8 options;
1000 u32 wolopts = 0;
1001
1002 options = RTL_R8(Config1);
1003 if (!(options & PMEnable))
1004 return 0;
1005
1006 options = RTL_R8(Config3);
1007 if (options & LinkUp)
1008 wolopts |= WAKE_PHY;
1009 if (options & MagicPacket)
1010 wolopts |= WAKE_MAGIC;
1011
1012 options = RTL_R8(Config5);
1013 if (options & UWF)
1014 wolopts |= WAKE_UCAST;
1015 if (options & BWF)
1016 wolopts |= WAKE_BCAST;
1017 if (options & MWF)
1018 wolopts |= WAKE_MCAST;
1019
1020 return wolopts;
1021 }
1022
1023 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1024 {
1025 struct rtl8169_private *tp = netdev_priv(dev);
1026
1027 spin_lock_irq(&tp->lock);
1028
1029 wol->supported = WAKE_ANY;
1030 wol->wolopts = __rtl8169_get_wol(tp);
1031
1032 spin_unlock_irq(&tp->lock);
1033 }
1034
1035 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1036 {
1037 void __iomem *ioaddr = tp->mmio_addr;
1038 unsigned int i;
1039 static const struct {
1040 u32 opt;
1041 u16 reg;
1042 u8 mask;
1043 } cfg[] = {
1044 { WAKE_ANY, Config1, PMEnable },
1045 { WAKE_PHY, Config3, LinkUp },
1046 { WAKE_MAGIC, Config3, MagicPacket },
1047 { WAKE_UCAST, Config5, UWF },
1048 { WAKE_BCAST, Config5, BWF },
1049 { WAKE_MCAST, Config5, MWF },
1050 { WAKE_ANY, Config5, LanWake }
1051 };
1052
1053 RTL_W8(Cfg9346, Cfg9346_Unlock);
1054
1055 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1056 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1057 if (wolopts & cfg[i].opt)
1058 options |= cfg[i].mask;
1059 RTL_W8(cfg[i].reg, options);
1060 }
1061
1062 RTL_W8(Cfg9346, Cfg9346_Lock);
1063 }
1064
1065 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1066 {
1067 struct rtl8169_private *tp = netdev_priv(dev);
1068
1069 spin_lock_irq(&tp->lock);
1070
1071 if (wol->wolopts)
1072 tp->features |= RTL_FEATURE_WOL;
1073 else
1074 tp->features &= ~RTL_FEATURE_WOL;
1075 __rtl8169_set_wol(tp, wol->wolopts);
1076 spin_unlock_irq(&tp->lock);
1077
1078 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1079
1080 return 0;
1081 }
1082
1083 static void rtl8169_get_drvinfo(struct net_device *dev,
1084 struct ethtool_drvinfo *info)
1085 {
1086 struct rtl8169_private *tp = netdev_priv(dev);
1087
1088 strcpy(info->driver, MODULENAME);
1089 strcpy(info->version, RTL8169_VERSION);
1090 strcpy(info->bus_info, pci_name(tp->pci_dev));
1091 }
1092
1093 static int rtl8169_get_regs_len(struct net_device *dev)
1094 {
1095 return R8169_REGS_SIZE;
1096 }
1097
1098 static int rtl8169_set_speed_tbi(struct net_device *dev,
1099 u8 autoneg, u16 speed, u8 duplex)
1100 {
1101 struct rtl8169_private *tp = netdev_priv(dev);
1102 void __iomem *ioaddr = tp->mmio_addr;
1103 int ret = 0;
1104 u32 reg;
1105
1106 reg = RTL_R32(TBICSR);
1107 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1108 (duplex == DUPLEX_FULL)) {
1109 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1110 } else if (autoneg == AUTONEG_ENABLE)
1111 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1112 else {
1113 netif_warn(tp, link, dev,
1114 "incorrect speed setting refused in TBI mode\n");
1115 ret = -EOPNOTSUPP;
1116 }
1117
1118 return ret;
1119 }
1120
1121 static int rtl8169_set_speed_xmii(struct net_device *dev,
1122 u8 autoneg, u16 speed, u8 duplex)
1123 {
1124 struct rtl8169_private *tp = netdev_priv(dev);
1125 int giga_ctrl, bmcr;
1126
1127 if (autoneg == AUTONEG_ENABLE) {
1128 int auto_nego;
1129
1130 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1131 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1132 ADVERTISE_100HALF | ADVERTISE_100FULL);
1133 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1134
1135 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1136 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1137
1138 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1139 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1140 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1141 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1142 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1143 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1144 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1145 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1146 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1147 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1148 } else {
1149 netif_info(tp, link, dev,
1150 "PHY does not support 1000Mbps\n");
1151 }
1152
1153 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1154
1155 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1156 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1157 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1158 /*
1159 * Wake up the PHY.
1160 * Vendor specific (0x1f) and reserved (0x0e) MII
1161 * registers.
1162 */
1163 rtl_writephy(tp, 0x1f, 0x0000);
1164 rtl_writephy(tp, 0x0e, 0x0000);
1165 }
1166
1167 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1168 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1169 } else {
1170 giga_ctrl = 0;
1171
1172 if (speed == SPEED_10)
1173 bmcr = 0;
1174 else if (speed == SPEED_100)
1175 bmcr = BMCR_SPEED100;
1176 else
1177 return -EINVAL;
1178
1179 if (duplex == DUPLEX_FULL)
1180 bmcr |= BMCR_FULLDPLX;
1181
1182 rtl_writephy(tp, 0x1f, 0x0000);
1183 }
1184
1185 tp->phy_1000_ctrl_reg = giga_ctrl;
1186
1187 rtl_writephy(tp, MII_BMCR, bmcr);
1188
1189 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1190 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1191 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1192 rtl_writephy(tp, 0x17, 0x2138);
1193 rtl_writephy(tp, 0x0e, 0x0260);
1194 } else {
1195 rtl_writephy(tp, 0x17, 0x2108);
1196 rtl_writephy(tp, 0x0e, 0x0000);
1197 }
1198 }
1199
1200 return 0;
1201 }
1202
1203 static int rtl8169_set_speed(struct net_device *dev,
1204 u8 autoneg, u16 speed, u8 duplex)
1205 {
1206 struct rtl8169_private *tp = netdev_priv(dev);
1207 int ret;
1208
1209 ret = tp->set_speed(dev, autoneg, speed, duplex);
1210
1211 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1212 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1213
1214 return ret;
1215 }
1216
1217 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1218 {
1219 struct rtl8169_private *tp = netdev_priv(dev);
1220 unsigned long flags;
1221 int ret;
1222
1223 spin_lock_irqsave(&tp->lock, flags);
1224 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1225 spin_unlock_irqrestore(&tp->lock, flags);
1226
1227 return ret;
1228 }
1229
1230 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1231 {
1232 struct rtl8169_private *tp = netdev_priv(dev);
1233
1234 return tp->cp_cmd & RxChkSum;
1235 }
1236
1237 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1238 {
1239 struct rtl8169_private *tp = netdev_priv(dev);
1240 void __iomem *ioaddr = tp->mmio_addr;
1241 unsigned long flags;
1242
1243 spin_lock_irqsave(&tp->lock, flags);
1244
1245 if (data)
1246 tp->cp_cmd |= RxChkSum;
1247 else
1248 tp->cp_cmd &= ~RxChkSum;
1249
1250 RTL_W16(CPlusCmd, tp->cp_cmd);
1251 RTL_R16(CPlusCmd);
1252
1253 spin_unlock_irqrestore(&tp->lock, flags);
1254
1255 return 0;
1256 }
1257
1258 #ifdef CONFIG_R8169_VLAN
1259
1260 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1261 struct sk_buff *skb)
1262 {
1263 return (vlan_tx_tag_present(skb)) ?
1264 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1265 }
1266
1267 static void rtl8169_vlan_rx_register(struct net_device *dev,
1268 struct vlan_group *grp)
1269 {
1270 struct rtl8169_private *tp = netdev_priv(dev);
1271 void __iomem *ioaddr = tp->mmio_addr;
1272 unsigned long flags;
1273
1274 spin_lock_irqsave(&tp->lock, flags);
1275 tp->vlgrp = grp;
1276 /*
1277 * Do not disable RxVlan on 8110SCd.
1278 */
1279 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1280 tp->cp_cmd |= RxVlan;
1281 else
1282 tp->cp_cmd &= ~RxVlan;
1283 RTL_W16(CPlusCmd, tp->cp_cmd);
1284 RTL_R16(CPlusCmd);
1285 spin_unlock_irqrestore(&tp->lock, flags);
1286 }
1287
1288 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1289 struct sk_buff *skb, int polling)
1290 {
1291 u32 opts2 = le32_to_cpu(desc->opts2);
1292 struct vlan_group *vlgrp = tp->vlgrp;
1293 int ret;
1294
1295 if (vlgrp && (opts2 & RxVlanTag)) {
1296 u16 vtag = swab16(opts2 & 0xffff);
1297
1298 if (likely(polling))
1299 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1300 else
1301 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1302 ret = 0;
1303 } else
1304 ret = -1;
1305 desc->opts2 = 0;
1306 return ret;
1307 }
1308
1309 #else /* !CONFIG_R8169_VLAN */
1310
1311 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1312 struct sk_buff *skb)
1313 {
1314 return 0;
1315 }
1316
1317 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1318 struct sk_buff *skb, int polling)
1319 {
1320 return -1;
1321 }
1322
1323 #endif
1324
1325 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1326 {
1327 struct rtl8169_private *tp = netdev_priv(dev);
1328 void __iomem *ioaddr = tp->mmio_addr;
1329 u32 status;
1330
1331 cmd->supported =
1332 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1333 cmd->port = PORT_FIBRE;
1334 cmd->transceiver = XCVR_INTERNAL;
1335
1336 status = RTL_R32(TBICSR);
1337 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1338 cmd->autoneg = !!(status & TBINwEnable);
1339
1340 cmd->speed = SPEED_1000;
1341 cmd->duplex = DUPLEX_FULL; /* Always set */
1342
1343 return 0;
1344 }
1345
1346 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1347 {
1348 struct rtl8169_private *tp = netdev_priv(dev);
1349
1350 return mii_ethtool_gset(&tp->mii, cmd);
1351 }
1352
1353 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1354 {
1355 struct rtl8169_private *tp = netdev_priv(dev);
1356 unsigned long flags;
1357 int rc;
1358
1359 spin_lock_irqsave(&tp->lock, flags);
1360
1361 rc = tp->get_settings(dev, cmd);
1362
1363 spin_unlock_irqrestore(&tp->lock, flags);
1364 return rc;
1365 }
1366
1367 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1368 void *p)
1369 {
1370 struct rtl8169_private *tp = netdev_priv(dev);
1371 unsigned long flags;
1372
1373 if (regs->len > R8169_REGS_SIZE)
1374 regs->len = R8169_REGS_SIZE;
1375
1376 spin_lock_irqsave(&tp->lock, flags);
1377 memcpy_fromio(p, tp->mmio_addr, regs->len);
1378 spin_unlock_irqrestore(&tp->lock, flags);
1379 }
1380
1381 static u32 rtl8169_get_msglevel(struct net_device *dev)
1382 {
1383 struct rtl8169_private *tp = netdev_priv(dev);
1384
1385 return tp->msg_enable;
1386 }
1387
1388 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1389 {
1390 struct rtl8169_private *tp = netdev_priv(dev);
1391
1392 tp->msg_enable = value;
1393 }
1394
1395 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1396 "tx_packets",
1397 "rx_packets",
1398 "tx_errors",
1399 "rx_errors",
1400 "rx_missed",
1401 "align_errors",
1402 "tx_single_collisions",
1403 "tx_multi_collisions",
1404 "unicast",
1405 "broadcast",
1406 "multicast",
1407 "tx_aborted",
1408 "tx_underrun",
1409 };
1410
1411 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1412 {
1413 switch (sset) {
1414 case ETH_SS_STATS:
1415 return ARRAY_SIZE(rtl8169_gstrings);
1416 default:
1417 return -EOPNOTSUPP;
1418 }
1419 }
1420
1421 static void rtl8169_update_counters(struct net_device *dev)
1422 {
1423 struct rtl8169_private *tp = netdev_priv(dev);
1424 void __iomem *ioaddr = tp->mmio_addr;
1425 struct rtl8169_counters *counters;
1426 dma_addr_t paddr;
1427 u32 cmd;
1428 int wait = 1000;
1429 struct device *d = &tp->pci_dev->dev;
1430
1431 /*
1432 * Some chips are unable to dump tally counters when the receiver
1433 * is disabled.
1434 */
1435 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1436 return;
1437
1438 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1439 if (!counters)
1440 return;
1441
1442 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1443 cmd = (u64)paddr & DMA_BIT_MASK(32);
1444 RTL_W32(CounterAddrLow, cmd);
1445 RTL_W32(CounterAddrLow, cmd | CounterDump);
1446
1447 while (wait--) {
1448 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1449 /* copy updated counters */
1450 memcpy(&tp->counters, counters, sizeof(*counters));
1451 break;
1452 }
1453 udelay(10);
1454 }
1455
1456 RTL_W32(CounterAddrLow, 0);
1457 RTL_W32(CounterAddrHigh, 0);
1458
1459 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1460 }
1461
1462 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1463 struct ethtool_stats *stats, u64 *data)
1464 {
1465 struct rtl8169_private *tp = netdev_priv(dev);
1466
1467 ASSERT_RTNL();
1468
1469 rtl8169_update_counters(dev);
1470
1471 data[0] = le64_to_cpu(tp->counters.tx_packets);
1472 data[1] = le64_to_cpu(tp->counters.rx_packets);
1473 data[2] = le64_to_cpu(tp->counters.tx_errors);
1474 data[3] = le32_to_cpu(tp->counters.rx_errors);
1475 data[4] = le16_to_cpu(tp->counters.rx_missed);
1476 data[5] = le16_to_cpu(tp->counters.align_errors);
1477 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1478 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1479 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1480 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1481 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1482 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1483 data[12] = le16_to_cpu(tp->counters.tx_underun);
1484 }
1485
1486 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1487 {
1488 switch(stringset) {
1489 case ETH_SS_STATS:
1490 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1491 break;
1492 }
1493 }
1494
1495 static const struct ethtool_ops rtl8169_ethtool_ops = {
1496 .get_drvinfo = rtl8169_get_drvinfo,
1497 .get_regs_len = rtl8169_get_regs_len,
1498 .get_link = ethtool_op_get_link,
1499 .get_settings = rtl8169_get_settings,
1500 .set_settings = rtl8169_set_settings,
1501 .get_msglevel = rtl8169_get_msglevel,
1502 .set_msglevel = rtl8169_set_msglevel,
1503 .get_rx_csum = rtl8169_get_rx_csum,
1504 .set_rx_csum = rtl8169_set_rx_csum,
1505 .set_tx_csum = ethtool_op_set_tx_csum,
1506 .set_sg = ethtool_op_set_sg,
1507 .set_tso = ethtool_op_set_tso,
1508 .get_regs = rtl8169_get_regs,
1509 .get_wol = rtl8169_get_wol,
1510 .set_wol = rtl8169_set_wol,
1511 .get_strings = rtl8169_get_strings,
1512 .get_sset_count = rtl8169_get_sset_count,
1513 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1514 };
1515
1516 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1517 void __iomem *ioaddr)
1518 {
1519 /*
1520 * The driver currently handles the 8168Bf and the 8168Be identically
1521 * but they can be identified more specifically through the test below
1522 * if needed:
1523 *
1524 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1525 *
1526 * Same thing for the 8101Eb and the 8101Ec:
1527 *
1528 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1529 */
1530 static const struct {
1531 u32 mask;
1532 u32 val;
1533 int mac_version;
1534 } mac_info[] = {
1535 /* 8168D family. */
1536 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1537 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1538 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1539
1540 /* 8168DP family. */
1541 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1542 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1543
1544 /* 8168C family. */
1545 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1546 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1547 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1548 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1549 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1550 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1551 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1552 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1553 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1554
1555 /* 8168B family. */
1556 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1557 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1558 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1559 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1560
1561 /* 8101 family. */
1562 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1563 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1564 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1565 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1566 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1567 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1568 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1569 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1570 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1571 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1572 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1573 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1574 /* FIXME: where did these entries come from ? -- FR */
1575 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1576 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1577
1578 /* 8110 family. */
1579 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1580 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1581 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1582 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1583 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1584 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1585
1586 /* Catch-all */
1587 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1588 }, *p = mac_info;
1589 u32 reg;
1590
1591 reg = RTL_R32(TxConfig);
1592 while ((reg & p->mask) != p->val)
1593 p++;
1594 tp->mac_version = p->mac_version;
1595 }
1596
1597 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1598 {
1599 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1600 }
1601
1602 struct phy_reg {
1603 u16 reg;
1604 u16 val;
1605 };
1606
1607 static void rtl_writephy_batch(struct rtl8169_private *tp,
1608 const struct phy_reg *regs, int len)
1609 {
1610 while (len-- > 0) {
1611 rtl_writephy(tp, regs->reg, regs->val);
1612 regs++;
1613 }
1614 }
1615
1616 #define PHY_READ 0x00000000
1617 #define PHY_DATA_OR 0x10000000
1618 #define PHY_DATA_AND 0x20000000
1619 #define PHY_BJMPN 0x30000000
1620 #define PHY_READ_EFUSE 0x40000000
1621 #define PHY_READ_MAC_BYTE 0x50000000
1622 #define PHY_WRITE_MAC_BYTE 0x60000000
1623 #define PHY_CLEAR_READCOUNT 0x70000000
1624 #define PHY_WRITE 0x80000000
1625 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1626 #define PHY_COMP_EQ_SKIPN 0xa0000000
1627 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1628 #define PHY_WRITE_PREVIOUS 0xc0000000
1629 #define PHY_SKIPN 0xd0000000
1630 #define PHY_DELAY_MS 0xe0000000
1631 #define PHY_WRITE_ERI_WORD 0xf0000000
1632
1633 static void
1634 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1635 {
1636 __le32 *phytable = (__le32 *)fw->data;
1637 struct net_device *dev = tp->dev;
1638 size_t index, fw_size = fw->size / sizeof(*phytable);
1639 u32 predata, count;
1640
1641 if (fw->size % sizeof(*phytable)) {
1642 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1643 return;
1644 }
1645
1646 for (index = 0; index < fw_size; index++) {
1647 u32 action = le32_to_cpu(phytable[index]);
1648 u32 regno = (action & 0x0fff0000) >> 16;
1649
1650 switch(action & 0xf0000000) {
1651 case PHY_READ:
1652 case PHY_DATA_OR:
1653 case PHY_DATA_AND:
1654 case PHY_READ_EFUSE:
1655 case PHY_CLEAR_READCOUNT:
1656 case PHY_WRITE:
1657 case PHY_WRITE_PREVIOUS:
1658 case PHY_DELAY_MS:
1659 break;
1660
1661 case PHY_BJMPN:
1662 if (regno > index) {
1663 netif_err(tp, probe, tp->dev,
1664 "Out of range of firmware\n");
1665 return;
1666 }
1667 break;
1668 case PHY_READCOUNT_EQ_SKIP:
1669 if (index + 2 >= fw_size) {
1670 netif_err(tp, probe, tp->dev,
1671 "Out of range of firmware\n");
1672 return;
1673 }
1674 break;
1675 case PHY_COMP_EQ_SKIPN:
1676 case PHY_COMP_NEQ_SKIPN:
1677 case PHY_SKIPN:
1678 if (index + 1 + regno >= fw_size) {
1679 netif_err(tp, probe, tp->dev,
1680 "Out of range of firmware\n");
1681 return;
1682 }
1683 break;
1684
1685 case PHY_READ_MAC_BYTE:
1686 case PHY_WRITE_MAC_BYTE:
1687 case PHY_WRITE_ERI_WORD:
1688 default:
1689 netif_err(tp, probe, tp->dev,
1690 "Invalid action 0x%08x\n", action);
1691 return;
1692 }
1693 }
1694
1695 predata = 0;
1696 count = 0;
1697
1698 for (index = 0; index < fw_size; ) {
1699 u32 action = le32_to_cpu(phytable[index]);
1700 u32 data = action & 0x0000ffff;
1701 u32 regno = (action & 0x0fff0000) >> 16;
1702
1703 if (!action)
1704 break;
1705
1706 switch(action & 0xf0000000) {
1707 case PHY_READ:
1708 predata = rtl_readphy(tp, regno);
1709 count++;
1710 index++;
1711 break;
1712 case PHY_DATA_OR:
1713 predata |= data;
1714 index++;
1715 break;
1716 case PHY_DATA_AND:
1717 predata &= data;
1718 index++;
1719 break;
1720 case PHY_BJMPN:
1721 index -= regno;
1722 break;
1723 case PHY_READ_EFUSE:
1724 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1725 index++;
1726 break;
1727 case PHY_CLEAR_READCOUNT:
1728 count = 0;
1729 index++;
1730 break;
1731 case PHY_WRITE:
1732 rtl_writephy(tp, regno, data);
1733 index++;
1734 break;
1735 case PHY_READCOUNT_EQ_SKIP:
1736 if (count == data)
1737 index += 2;
1738 else
1739 index += 1;
1740 break;
1741 case PHY_COMP_EQ_SKIPN:
1742 if (predata == data)
1743 index += regno;
1744 index++;
1745 break;
1746 case PHY_COMP_NEQ_SKIPN:
1747 if (predata != data)
1748 index += regno;
1749 index++;
1750 break;
1751 case PHY_WRITE_PREVIOUS:
1752 rtl_writephy(tp, regno, predata);
1753 index++;
1754 break;
1755 case PHY_SKIPN:
1756 index += regno + 1;
1757 break;
1758 case PHY_DELAY_MS:
1759 mdelay(data);
1760 index++;
1761 break;
1762
1763 case PHY_READ_MAC_BYTE:
1764 case PHY_WRITE_MAC_BYTE:
1765 case PHY_WRITE_ERI_WORD:
1766 default:
1767 BUG();
1768 }
1769 }
1770 }
1771
1772 static void rtl_release_firmware(struct rtl8169_private *tp)
1773 {
1774 release_firmware(tp->fw);
1775 tp->fw = NULL;
1776 }
1777
1778 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1779 {
1780 const struct firmware **fw = &tp->fw;
1781 int rc = !*fw;
1782
1783 if (rc) {
1784 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1785 if (rc < 0)
1786 goto out;
1787 }
1788
1789 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1790 rtl_phy_write_fw(tp, *fw);
1791 out:
1792 return rc;
1793 }
1794
1795 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1796 {
1797 static const struct phy_reg phy_reg_init[] = {
1798 { 0x1f, 0x0001 },
1799 { 0x06, 0x006e },
1800 { 0x08, 0x0708 },
1801 { 0x15, 0x4000 },
1802 { 0x18, 0x65c7 },
1803
1804 { 0x1f, 0x0001 },
1805 { 0x03, 0x00a1 },
1806 { 0x02, 0x0008 },
1807 { 0x01, 0x0120 },
1808 { 0x00, 0x1000 },
1809 { 0x04, 0x0800 },
1810 { 0x04, 0x0000 },
1811
1812 { 0x03, 0xff41 },
1813 { 0x02, 0xdf60 },
1814 { 0x01, 0x0140 },
1815 { 0x00, 0x0077 },
1816 { 0x04, 0x7800 },
1817 { 0x04, 0x7000 },
1818
1819 { 0x03, 0x802f },
1820 { 0x02, 0x4f02 },
1821 { 0x01, 0x0409 },
1822 { 0x00, 0xf0f9 },
1823 { 0x04, 0x9800 },
1824 { 0x04, 0x9000 },
1825
1826 { 0x03, 0xdf01 },
1827 { 0x02, 0xdf20 },
1828 { 0x01, 0xff95 },
1829 { 0x00, 0xba00 },
1830 { 0x04, 0xa800 },
1831 { 0x04, 0xa000 },
1832
1833 { 0x03, 0xff41 },
1834 { 0x02, 0xdf20 },
1835 { 0x01, 0x0140 },
1836 { 0x00, 0x00bb },
1837 { 0x04, 0xb800 },
1838 { 0x04, 0xb000 },
1839
1840 { 0x03, 0xdf41 },
1841 { 0x02, 0xdc60 },
1842 { 0x01, 0x6340 },
1843 { 0x00, 0x007d },
1844 { 0x04, 0xd800 },
1845 { 0x04, 0xd000 },
1846
1847 { 0x03, 0xdf01 },
1848 { 0x02, 0xdf20 },
1849 { 0x01, 0x100a },
1850 { 0x00, 0xa0ff },
1851 { 0x04, 0xf800 },
1852 { 0x04, 0xf000 },
1853
1854 { 0x1f, 0x0000 },
1855 { 0x0b, 0x0000 },
1856 { 0x00, 0x9200 }
1857 };
1858
1859 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1860 }
1861
1862 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1863 {
1864 static const struct phy_reg phy_reg_init[] = {
1865 { 0x1f, 0x0002 },
1866 { 0x01, 0x90d0 },
1867 { 0x1f, 0x0000 }
1868 };
1869
1870 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1871 }
1872
1873 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1874 {
1875 struct pci_dev *pdev = tp->pci_dev;
1876 u16 vendor_id, device_id;
1877
1878 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1879 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1880
1881 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1882 return;
1883
1884 rtl_writephy(tp, 0x1f, 0x0001);
1885 rtl_writephy(tp, 0x10, 0xf01b);
1886 rtl_writephy(tp, 0x1f, 0x0000);
1887 }
1888
1889 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1890 {
1891 static const struct phy_reg phy_reg_init[] = {
1892 { 0x1f, 0x0001 },
1893 { 0x04, 0x0000 },
1894 { 0x03, 0x00a1 },
1895 { 0x02, 0x0008 },
1896 { 0x01, 0x0120 },
1897 { 0x00, 0x1000 },
1898 { 0x04, 0x0800 },
1899 { 0x04, 0x9000 },
1900 { 0x03, 0x802f },
1901 { 0x02, 0x4f02 },
1902 { 0x01, 0x0409 },
1903 { 0x00, 0xf099 },
1904 { 0x04, 0x9800 },
1905 { 0x04, 0xa000 },
1906 { 0x03, 0xdf01 },
1907 { 0x02, 0xdf20 },
1908 { 0x01, 0xff95 },
1909 { 0x00, 0xba00 },
1910 { 0x04, 0xa800 },
1911 { 0x04, 0xf000 },
1912 { 0x03, 0xdf01 },
1913 { 0x02, 0xdf20 },
1914 { 0x01, 0x101a },
1915 { 0x00, 0xa0ff },
1916 { 0x04, 0xf800 },
1917 { 0x04, 0x0000 },
1918 { 0x1f, 0x0000 },
1919
1920 { 0x1f, 0x0001 },
1921 { 0x10, 0xf41b },
1922 { 0x14, 0xfb54 },
1923 { 0x18, 0xf5c7 },
1924 { 0x1f, 0x0000 },
1925
1926 { 0x1f, 0x0001 },
1927 { 0x17, 0x0cc0 },
1928 { 0x1f, 0x0000 }
1929 };
1930
1931 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1932
1933 rtl8169scd_hw_phy_config_quirk(tp);
1934 }
1935
1936 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1937 {
1938 static const struct phy_reg phy_reg_init[] = {
1939 { 0x1f, 0x0001 },
1940 { 0x04, 0x0000 },
1941 { 0x03, 0x00a1 },
1942 { 0x02, 0x0008 },
1943 { 0x01, 0x0120 },
1944 { 0x00, 0x1000 },
1945 { 0x04, 0x0800 },
1946 { 0x04, 0x9000 },
1947 { 0x03, 0x802f },
1948 { 0x02, 0x4f02 },
1949 { 0x01, 0x0409 },
1950 { 0x00, 0xf099 },
1951 { 0x04, 0x9800 },
1952 { 0x04, 0xa000 },
1953 { 0x03, 0xdf01 },
1954 { 0x02, 0xdf20 },
1955 { 0x01, 0xff95 },
1956 { 0x00, 0xba00 },
1957 { 0x04, 0xa800 },
1958 { 0x04, 0xf000 },
1959 { 0x03, 0xdf01 },
1960 { 0x02, 0xdf20 },
1961 { 0x01, 0x101a },
1962 { 0x00, 0xa0ff },
1963 { 0x04, 0xf800 },
1964 { 0x04, 0x0000 },
1965 { 0x1f, 0x0000 },
1966
1967 { 0x1f, 0x0001 },
1968 { 0x0b, 0x8480 },
1969 { 0x1f, 0x0000 },
1970
1971 { 0x1f, 0x0001 },
1972 { 0x18, 0x67c7 },
1973 { 0x04, 0x2000 },
1974 { 0x03, 0x002f },
1975 { 0x02, 0x4360 },
1976 { 0x01, 0x0109 },
1977 { 0x00, 0x3022 },
1978 { 0x04, 0x2800 },
1979 { 0x1f, 0x0000 },
1980
1981 { 0x1f, 0x0001 },
1982 { 0x17, 0x0cc0 },
1983 { 0x1f, 0x0000 }
1984 };
1985
1986 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1987 }
1988
1989 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1990 {
1991 static const struct phy_reg phy_reg_init[] = {
1992 { 0x10, 0xf41b },
1993 { 0x1f, 0x0000 }
1994 };
1995
1996 rtl_writephy(tp, 0x1f, 0x0001);
1997 rtl_patchphy(tp, 0x16, 1 << 0);
1998
1999 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2000 }
2001
2002 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2003 {
2004 static const struct phy_reg phy_reg_init[] = {
2005 { 0x1f, 0x0001 },
2006 { 0x10, 0xf41b },
2007 { 0x1f, 0x0000 }
2008 };
2009
2010 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2011 }
2012
2013 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2014 {
2015 static const struct phy_reg phy_reg_init[] = {
2016 { 0x1f, 0x0000 },
2017 { 0x1d, 0x0f00 },
2018 { 0x1f, 0x0002 },
2019 { 0x0c, 0x1ec8 },
2020 { 0x1f, 0x0000 }
2021 };
2022
2023 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2024 }
2025
2026 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2027 {
2028 static const struct phy_reg phy_reg_init[] = {
2029 { 0x1f, 0x0001 },
2030 { 0x1d, 0x3d98 },
2031 { 0x1f, 0x0000 }
2032 };
2033
2034 rtl_writephy(tp, 0x1f, 0x0000);
2035 rtl_patchphy(tp, 0x14, 1 << 5);
2036 rtl_patchphy(tp, 0x0d, 1 << 5);
2037
2038 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2039 }
2040
2041 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2042 {
2043 static const struct phy_reg phy_reg_init[] = {
2044 { 0x1f, 0x0001 },
2045 { 0x12, 0x2300 },
2046 { 0x1f, 0x0002 },
2047 { 0x00, 0x88d4 },
2048 { 0x01, 0x82b1 },
2049 { 0x03, 0x7002 },
2050 { 0x08, 0x9e30 },
2051 { 0x09, 0x01f0 },
2052 { 0x0a, 0x5500 },
2053 { 0x0c, 0x00c8 },
2054 { 0x1f, 0x0003 },
2055 { 0x12, 0xc096 },
2056 { 0x16, 0x000a },
2057 { 0x1f, 0x0000 },
2058 { 0x1f, 0x0000 },
2059 { 0x09, 0x2000 },
2060 { 0x09, 0x0000 }
2061 };
2062
2063 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2064
2065 rtl_patchphy(tp, 0x14, 1 << 5);
2066 rtl_patchphy(tp, 0x0d, 1 << 5);
2067 rtl_writephy(tp, 0x1f, 0x0000);
2068 }
2069
2070 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2071 {
2072 static const struct phy_reg phy_reg_init[] = {
2073 { 0x1f, 0x0001 },
2074 { 0x12, 0x2300 },
2075 { 0x03, 0x802f },
2076 { 0x02, 0x4f02 },
2077 { 0x01, 0x0409 },
2078 { 0x00, 0xf099 },
2079 { 0x04, 0x9800 },
2080 { 0x04, 0x9000 },
2081 { 0x1d, 0x3d98 },
2082 { 0x1f, 0x0002 },
2083 { 0x0c, 0x7eb8 },
2084 { 0x06, 0x0761 },
2085 { 0x1f, 0x0003 },
2086 { 0x16, 0x0f0a },
2087 { 0x1f, 0x0000 }
2088 };
2089
2090 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2091
2092 rtl_patchphy(tp, 0x16, 1 << 0);
2093 rtl_patchphy(tp, 0x14, 1 << 5);
2094 rtl_patchphy(tp, 0x0d, 1 << 5);
2095 rtl_writephy(tp, 0x1f, 0x0000);
2096 }
2097
2098 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2099 {
2100 static const struct phy_reg phy_reg_init[] = {
2101 { 0x1f, 0x0001 },
2102 { 0x12, 0x2300 },
2103 { 0x1d, 0x3d98 },
2104 { 0x1f, 0x0002 },
2105 { 0x0c, 0x7eb8 },
2106 { 0x06, 0x5461 },
2107 { 0x1f, 0x0003 },
2108 { 0x16, 0x0f0a },
2109 { 0x1f, 0x0000 }
2110 };
2111
2112 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2113
2114 rtl_patchphy(tp, 0x16, 1 << 0);
2115 rtl_patchphy(tp, 0x14, 1 << 5);
2116 rtl_patchphy(tp, 0x0d, 1 << 5);
2117 rtl_writephy(tp, 0x1f, 0x0000);
2118 }
2119
2120 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2121 {
2122 rtl8168c_3_hw_phy_config(tp);
2123 }
2124
2125 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2126 {
2127 static const struct phy_reg phy_reg_init_0[] = {
2128 /* Channel Estimation */
2129 { 0x1f, 0x0001 },
2130 { 0x06, 0x4064 },
2131 { 0x07, 0x2863 },
2132 { 0x08, 0x059c },
2133 { 0x09, 0x26b4 },
2134 { 0x0a, 0x6a19 },
2135 { 0x0b, 0xdcc8 },
2136 { 0x10, 0xf06d },
2137 { 0x14, 0x7f68 },
2138 { 0x18, 0x7fd9 },
2139 { 0x1c, 0xf0ff },
2140 { 0x1d, 0x3d9c },
2141 { 0x1f, 0x0003 },
2142 { 0x12, 0xf49f },
2143 { 0x13, 0x070b },
2144 { 0x1a, 0x05ad },
2145 { 0x14, 0x94c0 },
2146
2147 /*
2148 * Tx Error Issue
2149 * enhance line driver power
2150 */
2151 { 0x1f, 0x0002 },
2152 { 0x06, 0x5561 },
2153 { 0x1f, 0x0005 },
2154 { 0x05, 0x8332 },
2155 { 0x06, 0x5561 },
2156
2157 /*
2158 * Can not link to 1Gbps with bad cable
2159 * Decrease SNR threshold form 21.07dB to 19.04dB
2160 */
2161 { 0x1f, 0x0001 },
2162 { 0x17, 0x0cc0 },
2163
2164 { 0x1f, 0x0000 },
2165 { 0x0d, 0xf880 }
2166 };
2167 void __iomem *ioaddr = tp->mmio_addr;
2168
2169 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2170
2171 /*
2172 * Rx Error Issue
2173 * Fine Tune Switching regulator parameter
2174 */
2175 rtl_writephy(tp, 0x1f, 0x0002);
2176 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2177 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2178
2179 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2180 static const struct phy_reg phy_reg_init[] = {
2181 { 0x1f, 0x0002 },
2182 { 0x05, 0x669a },
2183 { 0x1f, 0x0005 },
2184 { 0x05, 0x8330 },
2185 { 0x06, 0x669a },
2186 { 0x1f, 0x0002 }
2187 };
2188 int val;
2189
2190 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2191
2192 val = rtl_readphy(tp, 0x0d);
2193
2194 if ((val & 0x00ff) != 0x006c) {
2195 static const u32 set[] = {
2196 0x0065, 0x0066, 0x0067, 0x0068,
2197 0x0069, 0x006a, 0x006b, 0x006c
2198 };
2199 int i;
2200
2201 rtl_writephy(tp, 0x1f, 0x0002);
2202
2203 val &= 0xff00;
2204 for (i = 0; i < ARRAY_SIZE(set); i++)
2205 rtl_writephy(tp, 0x0d, val | set[i]);
2206 }
2207 } else {
2208 static const struct phy_reg phy_reg_init[] = {
2209 { 0x1f, 0x0002 },
2210 { 0x05, 0x6662 },
2211 { 0x1f, 0x0005 },
2212 { 0x05, 0x8330 },
2213 { 0x06, 0x6662 }
2214 };
2215
2216 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2217 }
2218
2219 /* RSET couple improve */
2220 rtl_writephy(tp, 0x1f, 0x0002);
2221 rtl_patchphy(tp, 0x0d, 0x0300);
2222 rtl_patchphy(tp, 0x0f, 0x0010);
2223
2224 /* Fine tune PLL performance */
2225 rtl_writephy(tp, 0x1f, 0x0002);
2226 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2227 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2228
2229 rtl_writephy(tp, 0x1f, 0x0005);
2230 rtl_writephy(tp, 0x05, 0x001b);
2231 if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2232 (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2233 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2234 }
2235
2236 rtl_writephy(tp, 0x1f, 0x0000);
2237 }
2238
2239 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2240 {
2241 static const struct phy_reg phy_reg_init_0[] = {
2242 /* Channel Estimation */
2243 { 0x1f, 0x0001 },
2244 { 0x06, 0x4064 },
2245 { 0x07, 0x2863 },
2246 { 0x08, 0x059c },
2247 { 0x09, 0x26b4 },
2248 { 0x0a, 0x6a19 },
2249 { 0x0b, 0xdcc8 },
2250 { 0x10, 0xf06d },
2251 { 0x14, 0x7f68 },
2252 { 0x18, 0x7fd9 },
2253 { 0x1c, 0xf0ff },
2254 { 0x1d, 0x3d9c },
2255 { 0x1f, 0x0003 },
2256 { 0x12, 0xf49f },
2257 { 0x13, 0x070b },
2258 { 0x1a, 0x05ad },
2259 { 0x14, 0x94c0 },
2260
2261 /*
2262 * Tx Error Issue
2263 * enhance line driver power
2264 */
2265 { 0x1f, 0x0002 },
2266 { 0x06, 0x5561 },
2267 { 0x1f, 0x0005 },
2268 { 0x05, 0x8332 },
2269 { 0x06, 0x5561 },
2270
2271 /*
2272 * Can not link to 1Gbps with bad cable
2273 * Decrease SNR threshold form 21.07dB to 19.04dB
2274 */
2275 { 0x1f, 0x0001 },
2276 { 0x17, 0x0cc0 },
2277
2278 { 0x1f, 0x0000 },
2279 { 0x0d, 0xf880 }
2280 };
2281 void __iomem *ioaddr = tp->mmio_addr;
2282
2283 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2284
2285 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2286 static const struct phy_reg phy_reg_init[] = {
2287 { 0x1f, 0x0002 },
2288 { 0x05, 0x669a },
2289 { 0x1f, 0x0005 },
2290 { 0x05, 0x8330 },
2291 { 0x06, 0x669a },
2292
2293 { 0x1f, 0x0002 }
2294 };
2295 int val;
2296
2297 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2298
2299 val = rtl_readphy(tp, 0x0d);
2300 if ((val & 0x00ff) != 0x006c) {
2301 static const u32 set[] = {
2302 0x0065, 0x0066, 0x0067, 0x0068,
2303 0x0069, 0x006a, 0x006b, 0x006c
2304 };
2305 int i;
2306
2307 rtl_writephy(tp, 0x1f, 0x0002);
2308
2309 val &= 0xff00;
2310 for (i = 0; i < ARRAY_SIZE(set); i++)
2311 rtl_writephy(tp, 0x0d, val | set[i]);
2312 }
2313 } else {
2314 static const struct phy_reg phy_reg_init[] = {
2315 { 0x1f, 0x0002 },
2316 { 0x05, 0x2642 },
2317 { 0x1f, 0x0005 },
2318 { 0x05, 0x8330 },
2319 { 0x06, 0x2642 }
2320 };
2321
2322 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2323 }
2324
2325 /* Fine tune PLL performance */
2326 rtl_writephy(tp, 0x1f, 0x0002);
2327 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2328 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2329
2330 /* Switching regulator Slew rate */
2331 rtl_writephy(tp, 0x1f, 0x0002);
2332 rtl_patchphy(tp, 0x0f, 0x0017);
2333
2334 rtl_writephy(tp, 0x1f, 0x0005);
2335 rtl_writephy(tp, 0x05, 0x001b);
2336 if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2337 (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2338 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2339 }
2340
2341 rtl_writephy(tp, 0x1f, 0x0000);
2342 }
2343
2344 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2345 {
2346 static const struct phy_reg phy_reg_init[] = {
2347 { 0x1f, 0x0002 },
2348 { 0x10, 0x0008 },
2349 { 0x0d, 0x006c },
2350
2351 { 0x1f, 0x0000 },
2352 { 0x0d, 0xf880 },
2353
2354 { 0x1f, 0x0001 },
2355 { 0x17, 0x0cc0 },
2356
2357 { 0x1f, 0x0001 },
2358 { 0x0b, 0xa4d8 },
2359 { 0x09, 0x281c },
2360 { 0x07, 0x2883 },
2361 { 0x0a, 0x6b35 },
2362 { 0x1d, 0x3da4 },
2363 { 0x1c, 0xeffd },
2364 { 0x14, 0x7f52 },
2365 { 0x18, 0x7fc6 },
2366 { 0x08, 0x0601 },
2367 { 0x06, 0x4063 },
2368 { 0x10, 0xf074 },
2369 { 0x1f, 0x0003 },
2370 { 0x13, 0x0789 },
2371 { 0x12, 0xf4bd },
2372 { 0x1a, 0x04fd },
2373 { 0x14, 0x84b0 },
2374 { 0x1f, 0x0000 },
2375 { 0x00, 0x9200 },
2376
2377 { 0x1f, 0x0005 },
2378 { 0x01, 0x0340 },
2379 { 0x1f, 0x0001 },
2380 { 0x04, 0x4000 },
2381 { 0x03, 0x1d21 },
2382 { 0x02, 0x0c32 },
2383 { 0x01, 0x0200 },
2384 { 0x00, 0x5554 },
2385 { 0x04, 0x4800 },
2386 { 0x04, 0x4000 },
2387 { 0x04, 0xf000 },
2388 { 0x03, 0xdf01 },
2389 { 0x02, 0xdf20 },
2390 { 0x01, 0x101a },
2391 { 0x00, 0xa0ff },
2392 { 0x04, 0xf800 },
2393 { 0x04, 0xf000 },
2394 { 0x1f, 0x0000 },
2395
2396 { 0x1f, 0x0007 },
2397 { 0x1e, 0x0023 },
2398 { 0x16, 0x0000 },
2399 { 0x1f, 0x0000 }
2400 };
2401
2402 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2403 }
2404
2405 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2406 {
2407 static const struct phy_reg phy_reg_init[] = {
2408 { 0x1f, 0x0001 },
2409 { 0x17, 0x0cc0 },
2410
2411 { 0x1f, 0x0007 },
2412 { 0x1e, 0x002d },
2413 { 0x18, 0x0040 },
2414 { 0x1f, 0x0000 }
2415 };
2416
2417 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2418 rtl_patchphy(tp, 0x0d, 1 << 5);
2419 }
2420
2421 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2422 {
2423 static const struct phy_reg phy_reg_init[] = {
2424 { 0x1f, 0x0003 },
2425 { 0x08, 0x441d },
2426 { 0x01, 0x9100 },
2427 { 0x1f, 0x0000 }
2428 };
2429
2430 rtl_writephy(tp, 0x1f, 0x0000);
2431 rtl_patchphy(tp, 0x11, 1 << 12);
2432 rtl_patchphy(tp, 0x19, 1 << 13);
2433 rtl_patchphy(tp, 0x10, 1 << 15);
2434
2435 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2436 }
2437
2438 static void rtl_hw_phy_config(struct net_device *dev)
2439 {
2440 struct rtl8169_private *tp = netdev_priv(dev);
2441
2442 rtl8169_print_mac_version(tp);
2443
2444 switch (tp->mac_version) {
2445 case RTL_GIGA_MAC_VER_01:
2446 break;
2447 case RTL_GIGA_MAC_VER_02:
2448 case RTL_GIGA_MAC_VER_03:
2449 rtl8169s_hw_phy_config(tp);
2450 break;
2451 case RTL_GIGA_MAC_VER_04:
2452 rtl8169sb_hw_phy_config(tp);
2453 break;
2454 case RTL_GIGA_MAC_VER_05:
2455 rtl8169scd_hw_phy_config(tp);
2456 break;
2457 case RTL_GIGA_MAC_VER_06:
2458 rtl8169sce_hw_phy_config(tp);
2459 break;
2460 case RTL_GIGA_MAC_VER_07:
2461 case RTL_GIGA_MAC_VER_08:
2462 case RTL_GIGA_MAC_VER_09:
2463 rtl8102e_hw_phy_config(tp);
2464 break;
2465 case RTL_GIGA_MAC_VER_11:
2466 rtl8168bb_hw_phy_config(tp);
2467 break;
2468 case RTL_GIGA_MAC_VER_12:
2469 rtl8168bef_hw_phy_config(tp);
2470 break;
2471 case RTL_GIGA_MAC_VER_17:
2472 rtl8168bef_hw_phy_config(tp);
2473 break;
2474 case RTL_GIGA_MAC_VER_18:
2475 rtl8168cp_1_hw_phy_config(tp);
2476 break;
2477 case RTL_GIGA_MAC_VER_19:
2478 rtl8168c_1_hw_phy_config(tp);
2479 break;
2480 case RTL_GIGA_MAC_VER_20:
2481 rtl8168c_2_hw_phy_config(tp);
2482 break;
2483 case RTL_GIGA_MAC_VER_21:
2484 rtl8168c_3_hw_phy_config(tp);
2485 break;
2486 case RTL_GIGA_MAC_VER_22:
2487 rtl8168c_4_hw_phy_config(tp);
2488 break;
2489 case RTL_GIGA_MAC_VER_23:
2490 case RTL_GIGA_MAC_VER_24:
2491 rtl8168cp_2_hw_phy_config(tp);
2492 break;
2493 case RTL_GIGA_MAC_VER_25:
2494 rtl8168d_1_hw_phy_config(tp);
2495 break;
2496 case RTL_GIGA_MAC_VER_26:
2497 rtl8168d_2_hw_phy_config(tp);
2498 break;
2499 case RTL_GIGA_MAC_VER_27:
2500 rtl8168d_3_hw_phy_config(tp);
2501 break;
2502 case RTL_GIGA_MAC_VER_28:
2503 rtl8168d_4_hw_phy_config(tp);
2504 break;
2505
2506 default:
2507 break;
2508 }
2509 }
2510
2511 static void rtl8169_phy_timer(unsigned long __opaque)
2512 {
2513 struct net_device *dev = (struct net_device *)__opaque;
2514 struct rtl8169_private *tp = netdev_priv(dev);
2515 struct timer_list *timer = &tp->timer;
2516 void __iomem *ioaddr = tp->mmio_addr;
2517 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2518
2519 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2520
2521 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2522 return;
2523
2524 spin_lock_irq(&tp->lock);
2525
2526 if (tp->phy_reset_pending(tp)) {
2527 /*
2528 * A busy loop could burn quite a few cycles on nowadays CPU.
2529 * Let's delay the execution of the timer for a few ticks.
2530 */
2531 timeout = HZ/10;
2532 goto out_mod_timer;
2533 }
2534
2535 if (tp->link_ok(ioaddr))
2536 goto out_unlock;
2537
2538 netif_warn(tp, link, dev, "PHY reset until link up\n");
2539
2540 tp->phy_reset_enable(tp);
2541
2542 out_mod_timer:
2543 mod_timer(timer, jiffies + timeout);
2544 out_unlock:
2545 spin_unlock_irq(&tp->lock);
2546 }
2547
2548 static inline void rtl8169_delete_timer(struct net_device *dev)
2549 {
2550 struct rtl8169_private *tp = netdev_priv(dev);
2551 struct timer_list *timer = &tp->timer;
2552
2553 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2554 return;
2555
2556 del_timer_sync(timer);
2557 }
2558
2559 static inline void rtl8169_request_timer(struct net_device *dev)
2560 {
2561 struct rtl8169_private *tp = netdev_priv(dev);
2562 struct timer_list *timer = &tp->timer;
2563
2564 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2565 return;
2566
2567 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2568 }
2569
2570 #ifdef CONFIG_NET_POLL_CONTROLLER
2571 /*
2572 * Polling 'interrupt' - used by things like netconsole to send skbs
2573 * without having to re-enable interrupts. It's not called while
2574 * the interrupt routine is executing.
2575 */
2576 static void rtl8169_netpoll(struct net_device *dev)
2577 {
2578 struct rtl8169_private *tp = netdev_priv(dev);
2579 struct pci_dev *pdev = tp->pci_dev;
2580
2581 disable_irq(pdev->irq);
2582 rtl8169_interrupt(pdev->irq, dev);
2583 enable_irq(pdev->irq);
2584 }
2585 #endif
2586
2587 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2588 void __iomem *ioaddr)
2589 {
2590 iounmap(ioaddr);
2591 pci_release_regions(pdev);
2592 pci_clear_mwi(pdev);
2593 pci_disable_device(pdev);
2594 free_netdev(dev);
2595 }
2596
2597 static void rtl8169_phy_reset(struct net_device *dev,
2598 struct rtl8169_private *tp)
2599 {
2600 unsigned int i;
2601
2602 tp->phy_reset_enable(tp);
2603 for (i = 0; i < 100; i++) {
2604 if (!tp->phy_reset_pending(tp))
2605 return;
2606 msleep(1);
2607 }
2608 netif_err(tp, link, dev, "PHY reset failed\n");
2609 }
2610
2611 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2612 {
2613 void __iomem *ioaddr = tp->mmio_addr;
2614
2615 rtl_hw_phy_config(dev);
2616
2617 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2618 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2619 RTL_W8(0x82, 0x01);
2620 }
2621
2622 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2623
2624 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2625 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2626
2627 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2628 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2629 RTL_W8(0x82, 0x01);
2630 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2631 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2632 }
2633
2634 rtl8169_phy_reset(dev, tp);
2635
2636 /*
2637 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2638 * only 8101. Don't panic.
2639 */
2640 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2641
2642 if (RTL_R8(PHYstatus) & TBI_Enable)
2643 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2644 }
2645
2646 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2647 {
2648 void __iomem *ioaddr = tp->mmio_addr;
2649 u32 high;
2650 u32 low;
2651
2652 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2653 high = addr[4] | (addr[5] << 8);
2654
2655 spin_lock_irq(&tp->lock);
2656
2657 RTL_W8(Cfg9346, Cfg9346_Unlock);
2658
2659 RTL_W32(MAC4, high);
2660 RTL_R32(MAC4);
2661
2662 RTL_W32(MAC0, low);
2663 RTL_R32(MAC0);
2664
2665 RTL_W8(Cfg9346, Cfg9346_Lock);
2666
2667 spin_unlock_irq(&tp->lock);
2668 }
2669
2670 static int rtl_set_mac_address(struct net_device *dev, void *p)
2671 {
2672 struct rtl8169_private *tp = netdev_priv(dev);
2673 struct sockaddr *addr = p;
2674
2675 if (!is_valid_ether_addr(addr->sa_data))
2676 return -EADDRNOTAVAIL;
2677
2678 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2679
2680 rtl_rar_set(tp, dev->dev_addr);
2681
2682 return 0;
2683 }
2684
2685 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2686 {
2687 struct rtl8169_private *tp = netdev_priv(dev);
2688 struct mii_ioctl_data *data = if_mii(ifr);
2689
2690 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2691 }
2692
2693 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2694 {
2695 switch (cmd) {
2696 case SIOCGMIIPHY:
2697 data->phy_id = 32; /* Internal PHY */
2698 return 0;
2699
2700 case SIOCGMIIREG:
2701 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2702 return 0;
2703
2704 case SIOCSMIIREG:
2705 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2706 return 0;
2707 }
2708 return -EOPNOTSUPP;
2709 }
2710
2711 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2712 {
2713 return -EOPNOTSUPP;
2714 }
2715
2716 static const struct rtl_cfg_info {
2717 void (*hw_start)(struct net_device *);
2718 unsigned int region;
2719 unsigned int align;
2720 u16 intr_event;
2721 u16 napi_event;
2722 unsigned features;
2723 u8 default_ver;
2724 } rtl_cfg_infos [] = {
2725 [RTL_CFG_0] = {
2726 .hw_start = rtl_hw_start_8169,
2727 .region = 1,
2728 .align = 0,
2729 .intr_event = SYSErr | LinkChg | RxOverflow |
2730 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2731 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2732 .features = RTL_FEATURE_GMII,
2733 .default_ver = RTL_GIGA_MAC_VER_01,
2734 },
2735 [RTL_CFG_1] = {
2736 .hw_start = rtl_hw_start_8168,
2737 .region = 2,
2738 .align = 8,
2739 .intr_event = SYSErr | LinkChg | RxOverflow |
2740 TxErr | TxOK | RxOK | RxErr,
2741 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2742 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2743 .default_ver = RTL_GIGA_MAC_VER_11,
2744 },
2745 [RTL_CFG_2] = {
2746 .hw_start = rtl_hw_start_8101,
2747 .region = 2,
2748 .align = 8,
2749 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2750 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2751 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2752 .features = RTL_FEATURE_MSI,
2753 .default_ver = RTL_GIGA_MAC_VER_13,
2754 }
2755 };
2756
2757 /* Cfg9346_Unlock assumed. */
2758 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2759 const struct rtl_cfg_info *cfg)
2760 {
2761 unsigned msi = 0;
2762 u8 cfg2;
2763
2764 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2765 if (cfg->features & RTL_FEATURE_MSI) {
2766 if (pci_enable_msi(pdev)) {
2767 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2768 } else {
2769 cfg2 |= MSIEnable;
2770 msi = RTL_FEATURE_MSI;
2771 }
2772 }
2773 RTL_W8(Config2, cfg2);
2774 return msi;
2775 }
2776
2777 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2778 {
2779 if (tp->features & RTL_FEATURE_MSI) {
2780 pci_disable_msi(pdev);
2781 tp->features &= ~RTL_FEATURE_MSI;
2782 }
2783 }
2784
2785 static const struct net_device_ops rtl8169_netdev_ops = {
2786 .ndo_open = rtl8169_open,
2787 .ndo_stop = rtl8169_close,
2788 .ndo_get_stats = rtl8169_get_stats,
2789 .ndo_start_xmit = rtl8169_start_xmit,
2790 .ndo_tx_timeout = rtl8169_tx_timeout,
2791 .ndo_validate_addr = eth_validate_addr,
2792 .ndo_change_mtu = rtl8169_change_mtu,
2793 .ndo_set_mac_address = rtl_set_mac_address,
2794 .ndo_do_ioctl = rtl8169_ioctl,
2795 .ndo_set_multicast_list = rtl_set_rx_mode,
2796 #ifdef CONFIG_R8169_VLAN
2797 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2798 #endif
2799 #ifdef CONFIG_NET_POLL_CONTROLLER
2800 .ndo_poll_controller = rtl8169_netpoll,
2801 #endif
2802
2803 };
2804
2805 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2806 {
2807 struct mdio_ops *ops = &tp->mdio_ops;
2808
2809 switch (tp->mac_version) {
2810 case RTL_GIGA_MAC_VER_27:
2811 ops->write = r8168dp_1_mdio_write;
2812 ops->read = r8168dp_1_mdio_read;
2813 break;
2814 case RTL_GIGA_MAC_VER_28:
2815 ops->write = r8168dp_2_mdio_write;
2816 ops->read = r8168dp_2_mdio_read;
2817 break;
2818 default:
2819 ops->write = r8169_mdio_write;
2820 ops->read = r8169_mdio_read;
2821 break;
2822 }
2823 }
2824
2825 static void r810x_phy_power_down(struct rtl8169_private *tp)
2826 {
2827 rtl_writephy(tp, 0x1f, 0x0000);
2828 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2829 }
2830
2831 static void r810x_phy_power_up(struct rtl8169_private *tp)
2832 {
2833 rtl_writephy(tp, 0x1f, 0x0000);
2834 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2835 }
2836
2837 static void r810x_pll_power_down(struct rtl8169_private *tp)
2838 {
2839 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2840 rtl_writephy(tp, 0x1f, 0x0000);
2841 rtl_writephy(tp, MII_BMCR, 0x0000);
2842 return;
2843 }
2844
2845 r810x_phy_power_down(tp);
2846 }
2847
2848 static void r810x_pll_power_up(struct rtl8169_private *tp)
2849 {
2850 r810x_phy_power_up(tp);
2851 }
2852
2853 static void r8168_phy_power_up(struct rtl8169_private *tp)
2854 {
2855 rtl_writephy(tp, 0x1f, 0x0000);
2856 rtl_writephy(tp, 0x0e, 0x0000);
2857 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2858 }
2859
2860 static void r8168_phy_power_down(struct rtl8169_private *tp)
2861 {
2862 rtl_writephy(tp, 0x1f, 0x0000);
2863 rtl_writephy(tp, 0x0e, 0x0200);
2864 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2865 }
2866
2867 static void r8168_pll_power_down(struct rtl8169_private *tp)
2868 {
2869 void __iomem *ioaddr = tp->mmio_addr;
2870
2871 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2872 return;
2873
2874 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2875 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2876 (RTL_R16(CPlusCmd) & ASF)) {
2877 return;
2878 }
2879
2880 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2881 rtl_writephy(tp, 0x1f, 0x0000);
2882 rtl_writephy(tp, MII_BMCR, 0x0000);
2883
2884 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2885 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2886 return;
2887 }
2888
2889 r8168_phy_power_down(tp);
2890
2891 switch (tp->mac_version) {
2892 case RTL_GIGA_MAC_VER_25:
2893 case RTL_GIGA_MAC_VER_26:
2894 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2895 break;
2896 }
2897 }
2898
2899 static void r8168_pll_power_up(struct rtl8169_private *tp)
2900 {
2901 void __iomem *ioaddr = tp->mmio_addr;
2902
2903 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2904 return;
2905
2906 switch (tp->mac_version) {
2907 case RTL_GIGA_MAC_VER_25:
2908 case RTL_GIGA_MAC_VER_26:
2909 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2910 break;
2911 }
2912
2913 r8168_phy_power_up(tp);
2914 }
2915
2916 static void rtl_pll_power_op(struct rtl8169_private *tp,
2917 void (*op)(struct rtl8169_private *))
2918 {
2919 if (op)
2920 op(tp);
2921 }
2922
2923 static void rtl_pll_power_down(struct rtl8169_private *tp)
2924 {
2925 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2926 }
2927
2928 static void rtl_pll_power_up(struct rtl8169_private *tp)
2929 {
2930 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2931 }
2932
2933 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2934 {
2935 struct pll_power_ops *ops = &tp->pll_power_ops;
2936
2937 switch (tp->mac_version) {
2938 case RTL_GIGA_MAC_VER_07:
2939 case RTL_GIGA_MAC_VER_08:
2940 case RTL_GIGA_MAC_VER_09:
2941 case RTL_GIGA_MAC_VER_10:
2942 case RTL_GIGA_MAC_VER_16:
2943 ops->down = r810x_pll_power_down;
2944 ops->up = r810x_pll_power_up;
2945 break;
2946
2947 case RTL_GIGA_MAC_VER_11:
2948 case RTL_GIGA_MAC_VER_12:
2949 case RTL_GIGA_MAC_VER_17:
2950 case RTL_GIGA_MAC_VER_18:
2951 case RTL_GIGA_MAC_VER_19:
2952 case RTL_GIGA_MAC_VER_20:
2953 case RTL_GIGA_MAC_VER_21:
2954 case RTL_GIGA_MAC_VER_22:
2955 case RTL_GIGA_MAC_VER_23:
2956 case RTL_GIGA_MAC_VER_24:
2957 case RTL_GIGA_MAC_VER_25:
2958 case RTL_GIGA_MAC_VER_26:
2959 case RTL_GIGA_MAC_VER_27:
2960 case RTL_GIGA_MAC_VER_28:
2961 ops->down = r8168_pll_power_down;
2962 ops->up = r8168_pll_power_up;
2963 break;
2964
2965 default:
2966 ops->down = NULL;
2967 ops->up = NULL;
2968 break;
2969 }
2970 }
2971
2972 static int __devinit
2973 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2974 {
2975 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2976 const unsigned int region = cfg->region;
2977 struct rtl8169_private *tp;
2978 struct mii_if_info *mii;
2979 struct net_device *dev;
2980 void __iomem *ioaddr;
2981 unsigned int i;
2982 int rc;
2983
2984 if (netif_msg_drv(&debug)) {
2985 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2986 MODULENAME, RTL8169_VERSION);
2987 }
2988
2989 dev = alloc_etherdev(sizeof (*tp));
2990 if (!dev) {
2991 if (netif_msg_drv(&debug))
2992 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2993 rc = -ENOMEM;
2994 goto out;
2995 }
2996
2997 SET_NETDEV_DEV(dev, &pdev->dev);
2998 dev->netdev_ops = &rtl8169_netdev_ops;
2999 tp = netdev_priv(dev);
3000 tp->dev = dev;
3001 tp->pci_dev = pdev;
3002 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3003
3004 mii = &tp->mii;
3005 mii->dev = dev;
3006 mii->mdio_read = rtl_mdio_read;
3007 mii->mdio_write = rtl_mdio_write;
3008 mii->phy_id_mask = 0x1f;
3009 mii->reg_num_mask = 0x1f;
3010 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3011
3012 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3013 rc = pci_enable_device(pdev);
3014 if (rc < 0) {
3015 netif_err(tp, probe, dev, "enable failure\n");
3016 goto err_out_free_dev_1;
3017 }
3018
3019 if (pci_set_mwi(pdev) < 0)
3020 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3021
3022 /* make sure PCI base addr 1 is MMIO */
3023 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3024 netif_err(tp, probe, dev,
3025 "region #%d not an MMIO resource, aborting\n",
3026 region);
3027 rc = -ENODEV;
3028 goto err_out_mwi_2;
3029 }
3030
3031 /* check for weird/broken PCI region reporting */
3032 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3033 netif_err(tp, probe, dev,
3034 "Invalid PCI region size(s), aborting\n");
3035 rc = -ENODEV;
3036 goto err_out_mwi_2;
3037 }
3038
3039 rc = pci_request_regions(pdev, MODULENAME);
3040 if (rc < 0) {
3041 netif_err(tp, probe, dev, "could not request regions\n");
3042 goto err_out_mwi_2;
3043 }
3044
3045 tp->cp_cmd = PCIMulRW | RxChkSum;
3046
3047 if ((sizeof(dma_addr_t) > 4) &&
3048 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3049 tp->cp_cmd |= PCIDAC;
3050 dev->features |= NETIF_F_HIGHDMA;
3051 } else {
3052 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3053 if (rc < 0) {
3054 netif_err(tp, probe, dev, "DMA configuration failed\n");
3055 goto err_out_free_res_3;
3056 }
3057 }
3058
3059 /* ioremap MMIO region */
3060 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3061 if (!ioaddr) {
3062 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3063 rc = -EIO;
3064 goto err_out_free_res_3;
3065 }
3066
3067 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3068 if (!tp->pcie_cap)
3069 netif_info(tp, probe, dev, "no PCI Express capability\n");
3070
3071 RTL_W16(IntrMask, 0x0000);
3072
3073 /* Soft reset the chip. */
3074 RTL_W8(ChipCmd, CmdReset);
3075
3076 /* Check that the chip has finished the reset. */
3077 for (i = 0; i < 100; i++) {
3078 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3079 break;
3080 msleep_interruptible(1);
3081 }
3082
3083 RTL_W16(IntrStatus, 0xffff);
3084
3085 pci_set_master(pdev);
3086
3087 /* Identify chip attached to board */
3088 rtl8169_get_mac_version(tp, ioaddr);
3089
3090 rtl_init_mdio_ops(tp);
3091 rtl_init_pll_power_ops(tp);
3092
3093 /* Use appropriate default if unknown */
3094 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3095 netif_notice(tp, probe, dev,
3096 "unknown MAC, using family default\n");
3097 tp->mac_version = cfg->default_ver;
3098 }
3099
3100 rtl8169_print_mac_version(tp);
3101
3102 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3103 if (tp->mac_version == rtl_chip_info[i].mac_version)
3104 break;
3105 }
3106 if (i == ARRAY_SIZE(rtl_chip_info)) {
3107 dev_err(&pdev->dev,
3108 "driver bug, MAC version not found in rtl_chip_info\n");
3109 goto err_out_msi_4;
3110 }
3111 tp->chipset = i;
3112
3113 RTL_W8(Cfg9346, Cfg9346_Unlock);
3114 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3115 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3116 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3117 tp->features |= RTL_FEATURE_WOL;
3118 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3119 tp->features |= RTL_FEATURE_WOL;
3120 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3121 RTL_W8(Cfg9346, Cfg9346_Lock);
3122
3123 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3124 (RTL_R8(PHYstatus) & TBI_Enable)) {
3125 tp->set_speed = rtl8169_set_speed_tbi;
3126 tp->get_settings = rtl8169_gset_tbi;
3127 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3128 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3129 tp->link_ok = rtl8169_tbi_link_ok;
3130 tp->do_ioctl = rtl_tbi_ioctl;
3131
3132 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3133 } else {
3134 tp->set_speed = rtl8169_set_speed_xmii;
3135 tp->get_settings = rtl8169_gset_xmii;
3136 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3137 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3138 tp->link_ok = rtl8169_xmii_link_ok;
3139 tp->do_ioctl = rtl_xmii_ioctl;
3140 }
3141
3142 spin_lock_init(&tp->lock);
3143
3144 tp->mmio_addr = ioaddr;
3145
3146 /* Get MAC address */
3147 for (i = 0; i < MAC_ADDR_LEN; i++)
3148 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3149 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3150
3151 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3152 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3153 dev->irq = pdev->irq;
3154 dev->base_addr = (unsigned long) ioaddr;
3155
3156 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3157
3158 #ifdef CONFIG_R8169_VLAN
3159 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3160 #endif
3161 dev->features |= NETIF_F_GRO;
3162
3163 tp->intr_mask = 0xffff;
3164 tp->hw_start = cfg->hw_start;
3165 tp->intr_event = cfg->intr_event;
3166 tp->napi_event = cfg->napi_event;
3167
3168 init_timer(&tp->timer);
3169 tp->timer.data = (unsigned long) dev;
3170 tp->timer.function = rtl8169_phy_timer;
3171
3172 rc = register_netdev(dev);
3173 if (rc < 0)
3174 goto err_out_msi_4;
3175
3176 pci_set_drvdata(pdev, dev);
3177
3178 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3179 rtl_chip_info[tp->chipset].name,
3180 dev->base_addr, dev->dev_addr,
3181 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3182
3183 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3184 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3185 rtl8168_driver_start(tp);
3186 }
3187
3188 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3189
3190 if (pci_dev_run_wake(pdev))
3191 pm_runtime_put_noidle(&pdev->dev);
3192
3193 netif_carrier_off(dev);
3194
3195 out:
3196 return rc;
3197
3198 err_out_msi_4:
3199 rtl_disable_msi(pdev, tp);
3200 iounmap(ioaddr);
3201 err_out_free_res_3:
3202 pci_release_regions(pdev);
3203 err_out_mwi_2:
3204 pci_clear_mwi(pdev);
3205 pci_disable_device(pdev);
3206 err_out_free_dev_1:
3207 free_netdev(dev);
3208 goto out;
3209 }
3210
3211 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3212 {
3213 struct net_device *dev = pci_get_drvdata(pdev);
3214 struct rtl8169_private *tp = netdev_priv(dev);
3215
3216 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3217 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3218 rtl8168_driver_stop(tp);
3219 }
3220
3221 cancel_delayed_work_sync(&tp->task);
3222
3223 rtl_release_firmware(tp);
3224
3225 unregister_netdev(dev);
3226
3227 if (pci_dev_run_wake(pdev))
3228 pm_runtime_get_noresume(&pdev->dev);
3229
3230 /* restore original MAC address */
3231 rtl_rar_set(tp, dev->perm_addr);
3232
3233 rtl_disable_msi(pdev, tp);
3234 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3235 pci_set_drvdata(pdev, NULL);
3236 }
3237
3238 static int rtl8169_open(struct net_device *dev)
3239 {
3240 struct rtl8169_private *tp = netdev_priv(dev);
3241 void __iomem *ioaddr = tp->mmio_addr;
3242 struct pci_dev *pdev = tp->pci_dev;
3243 int retval = -ENOMEM;
3244
3245 pm_runtime_get_sync(&pdev->dev);
3246
3247 /*
3248 * Rx and Tx desscriptors needs 256 bytes alignment.
3249 * dma_alloc_coherent provides more.
3250 */
3251 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3252 &tp->TxPhyAddr, GFP_KERNEL);
3253 if (!tp->TxDescArray)
3254 goto err_pm_runtime_put;
3255
3256 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3257 &tp->RxPhyAddr, GFP_KERNEL);
3258 if (!tp->RxDescArray)
3259 goto err_free_tx_0;
3260
3261 retval = rtl8169_init_ring(dev);
3262 if (retval < 0)
3263 goto err_free_rx_1;
3264
3265 INIT_DELAYED_WORK(&tp->task, NULL);
3266
3267 smp_mb();
3268
3269 retval = request_irq(dev->irq, rtl8169_interrupt,
3270 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3271 dev->name, dev);
3272 if (retval < 0)
3273 goto err_release_ring_2;
3274
3275 napi_enable(&tp->napi);
3276
3277 rtl8169_init_phy(dev, tp);
3278
3279 /*
3280 * Pretend we are using VLANs; This bypasses a nasty bug where
3281 * Interrupts stop flowing on high load on 8110SCd controllers.
3282 */
3283 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3284 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3285
3286 rtl_pll_power_up(tp);
3287
3288 rtl_hw_start(dev);
3289
3290 rtl8169_request_timer(dev);
3291
3292 tp->saved_wolopts = 0;
3293 pm_runtime_put_noidle(&pdev->dev);
3294
3295 rtl8169_check_link_status(dev, tp, ioaddr);
3296 out:
3297 return retval;
3298
3299 err_release_ring_2:
3300 rtl8169_rx_clear(tp);
3301 err_free_rx_1:
3302 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3303 tp->RxPhyAddr);
3304 tp->RxDescArray = NULL;
3305 err_free_tx_0:
3306 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3307 tp->TxPhyAddr);
3308 tp->TxDescArray = NULL;
3309 err_pm_runtime_put:
3310 pm_runtime_put_noidle(&pdev->dev);
3311 goto out;
3312 }
3313
3314 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3315 {
3316 void __iomem *ioaddr = tp->mmio_addr;
3317
3318 /* Disable interrupts */
3319 rtl8169_irq_mask_and_ack(ioaddr);
3320
3321 if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3322 while (RTL_R8(TxPoll) & NPQ)
3323 udelay(20);
3324
3325 }
3326
3327 /* Reset the chipset */
3328 RTL_W8(ChipCmd, CmdReset);
3329
3330 /* PCI commit */
3331 RTL_R8(ChipCmd);
3332 }
3333
3334 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3335 {
3336 void __iomem *ioaddr = tp->mmio_addr;
3337 u32 cfg = rtl8169_rx_config;
3338
3339 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3340 RTL_W32(RxConfig, cfg);
3341
3342 /* Set DMA burst size and Interframe Gap Time */
3343 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3344 (InterFrameGap << TxInterFrameGapShift));
3345 }
3346
3347 static void rtl_hw_start(struct net_device *dev)
3348 {
3349 struct rtl8169_private *tp = netdev_priv(dev);
3350 void __iomem *ioaddr = tp->mmio_addr;
3351 unsigned int i;
3352
3353 /* Soft reset the chip. */
3354 RTL_W8(ChipCmd, CmdReset);
3355
3356 /* Check that the chip has finished the reset. */
3357 for (i = 0; i < 100; i++) {
3358 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3359 break;
3360 msleep_interruptible(1);
3361 }
3362
3363 tp->hw_start(dev);
3364
3365 netif_start_queue(dev);
3366 }
3367
3368
3369 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3370 void __iomem *ioaddr)
3371 {
3372 /*
3373 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3374 * register to be written before TxDescAddrLow to work.
3375 * Switching from MMIO to I/O access fixes the issue as well.
3376 */
3377 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3378 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3379 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3380 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3381 }
3382
3383 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3384 {
3385 u16 cmd;
3386
3387 cmd = RTL_R16(CPlusCmd);
3388 RTL_W16(CPlusCmd, cmd);
3389 return cmd;
3390 }
3391
3392 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3393 {
3394 /* Low hurts. Let's disable the filtering. */
3395 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3396 }
3397
3398 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3399 {
3400 static const struct {
3401 u32 mac_version;
3402 u32 clk;
3403 u32 val;
3404 } cfg2_info [] = {
3405 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3406 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3407 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3408 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3409 }, *p = cfg2_info;
3410 unsigned int i;
3411 u32 clk;
3412
3413 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3414 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3415 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3416 RTL_W32(0x7c, p->val);
3417 break;
3418 }
3419 }
3420 }
3421
3422 static void rtl_hw_start_8169(struct net_device *dev)
3423 {
3424 struct rtl8169_private *tp = netdev_priv(dev);
3425 void __iomem *ioaddr = tp->mmio_addr;
3426 struct pci_dev *pdev = tp->pci_dev;
3427
3428 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3429 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3430 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3431 }
3432
3433 RTL_W8(Cfg9346, Cfg9346_Unlock);
3434 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3435 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3436 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3437 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3438 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3439
3440 RTL_W8(EarlyTxThres, NoEarlyTx);
3441
3442 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3443
3444 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3445 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3446 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3447 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3448 rtl_set_rx_tx_config_registers(tp);
3449
3450 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3451
3452 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3453 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3454 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3455 "Bit-3 and bit-14 MUST be 1\n");
3456 tp->cp_cmd |= (1 << 14);
3457 }
3458
3459 RTL_W16(CPlusCmd, tp->cp_cmd);
3460
3461 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3462
3463 /*
3464 * Undocumented corner. Supposedly:
3465 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3466 */
3467 RTL_W16(IntrMitigate, 0x0000);
3468
3469 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3470
3471 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3472 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3473 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3474 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3475 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3476 rtl_set_rx_tx_config_registers(tp);
3477 }
3478
3479 RTL_W8(Cfg9346, Cfg9346_Lock);
3480
3481 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3482 RTL_R8(IntrMask);
3483
3484 RTL_W32(RxMissed, 0);
3485
3486 rtl_set_rx_mode(dev);
3487
3488 /* no early-rx interrupts */
3489 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3490
3491 /* Enable all known interrupts by setting the interrupt mask. */
3492 RTL_W16(IntrMask, tp->intr_event);
3493 }
3494
3495 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3496 {
3497 struct net_device *dev = pci_get_drvdata(pdev);
3498 struct rtl8169_private *tp = netdev_priv(dev);
3499 int cap = tp->pcie_cap;
3500
3501 if (cap) {
3502 u16 ctl;
3503
3504 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3505 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3506 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3507 }
3508 }
3509
3510 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3511 {
3512 u32 csi;
3513
3514 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3515 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3516 }
3517
3518 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3519 {
3520 rtl_csi_access_enable(ioaddr, 0x17000000);
3521 }
3522
3523 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3524 {
3525 rtl_csi_access_enable(ioaddr, 0x27000000);
3526 }
3527
3528 struct ephy_info {
3529 unsigned int offset;
3530 u16 mask;
3531 u16 bits;
3532 };
3533
3534 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3535 {
3536 u16 w;
3537
3538 while (len-- > 0) {
3539 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3540 rtl_ephy_write(ioaddr, e->offset, w);
3541 e++;
3542 }
3543 }
3544
3545 static void rtl_disable_clock_request(struct pci_dev *pdev)
3546 {
3547 struct net_device *dev = pci_get_drvdata(pdev);
3548 struct rtl8169_private *tp = netdev_priv(dev);
3549 int cap = tp->pcie_cap;
3550
3551 if (cap) {
3552 u16 ctl;
3553
3554 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3555 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3556 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3557 }
3558 }
3559
3560 static void rtl_enable_clock_request(struct pci_dev *pdev)
3561 {
3562 struct net_device *dev = pci_get_drvdata(pdev);
3563 struct rtl8169_private *tp = netdev_priv(dev);
3564 int cap = tp->pcie_cap;
3565
3566 if (cap) {
3567 u16 ctl;
3568
3569 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3570 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3571 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3572 }
3573 }
3574
3575 #define R8168_CPCMD_QUIRK_MASK (\
3576 EnableBist | \
3577 Mac_dbgo_oe | \
3578 Force_half_dup | \
3579 Force_rxflow_en | \
3580 Force_txflow_en | \
3581 Cxpl_dbg_sel | \
3582 ASF | \
3583 PktCntrDisable | \
3584 Mac_dbgo_sel)
3585
3586 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3587 {
3588 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3589
3590 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3591
3592 rtl_tx_performance_tweak(pdev,
3593 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3594 }
3595
3596 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3597 {
3598 rtl_hw_start_8168bb(ioaddr, pdev);
3599
3600 RTL_W8(MaxTxPacketSize, TxPacketMax);
3601
3602 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3603 }
3604
3605 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3606 {
3607 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3608
3609 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3610
3611 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3612
3613 rtl_disable_clock_request(pdev);
3614
3615 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3616 }
3617
3618 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3619 {
3620 static const struct ephy_info e_info_8168cp[] = {
3621 { 0x01, 0, 0x0001 },
3622 { 0x02, 0x0800, 0x1000 },
3623 { 0x03, 0, 0x0042 },
3624 { 0x06, 0x0080, 0x0000 },
3625 { 0x07, 0, 0x2000 }
3626 };
3627
3628 rtl_csi_access_enable_2(ioaddr);
3629
3630 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3631
3632 __rtl_hw_start_8168cp(ioaddr, pdev);
3633 }
3634
3635 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3636 {
3637 rtl_csi_access_enable_2(ioaddr);
3638
3639 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3640
3641 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3642
3643 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3644 }
3645
3646 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3647 {
3648 rtl_csi_access_enable_2(ioaddr);
3649
3650 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3651
3652 /* Magic. */
3653 RTL_W8(DBG_REG, 0x20);
3654
3655 RTL_W8(MaxTxPacketSize, TxPacketMax);
3656
3657 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3658
3659 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3660 }
3661
3662 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3663 {
3664 static const struct ephy_info e_info_8168c_1[] = {
3665 { 0x02, 0x0800, 0x1000 },
3666 { 0x03, 0, 0x0002 },
3667 { 0x06, 0x0080, 0x0000 }
3668 };
3669
3670 rtl_csi_access_enable_2(ioaddr);
3671
3672 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3673
3674 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3675
3676 __rtl_hw_start_8168cp(ioaddr, pdev);
3677 }
3678
3679 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3680 {
3681 static const struct ephy_info e_info_8168c_2[] = {
3682 { 0x01, 0, 0x0001 },
3683 { 0x03, 0x0400, 0x0220 }
3684 };
3685
3686 rtl_csi_access_enable_2(ioaddr);
3687
3688 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3689
3690 __rtl_hw_start_8168cp(ioaddr, pdev);
3691 }
3692
3693 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3694 {
3695 rtl_hw_start_8168c_2(ioaddr, pdev);
3696 }
3697
3698 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3699 {
3700 rtl_csi_access_enable_2(ioaddr);
3701
3702 __rtl_hw_start_8168cp(ioaddr, pdev);
3703 }
3704
3705 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3706 {
3707 rtl_csi_access_enable_2(ioaddr);
3708
3709 rtl_disable_clock_request(pdev);
3710
3711 RTL_W8(MaxTxPacketSize, TxPacketMax);
3712
3713 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3714
3715 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3716 }
3717
3718 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3719 {
3720 static const struct ephy_info e_info_8168d_4[] = {
3721 { 0x0b, ~0, 0x48 },
3722 { 0x19, 0x20, 0x50 },
3723 { 0x0c, ~0, 0x20 }
3724 };
3725 int i;
3726
3727 rtl_csi_access_enable_1(ioaddr);
3728
3729 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3730
3731 RTL_W8(MaxTxPacketSize, TxPacketMax);
3732
3733 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3734 const struct ephy_info *e = e_info_8168d_4 + i;
3735 u16 w;
3736
3737 w = rtl_ephy_read(ioaddr, e->offset);
3738 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3739 }
3740
3741 rtl_enable_clock_request(pdev);
3742 }
3743
3744 static void rtl_hw_start_8168(struct net_device *dev)
3745 {
3746 struct rtl8169_private *tp = netdev_priv(dev);
3747 void __iomem *ioaddr = tp->mmio_addr;
3748 struct pci_dev *pdev = tp->pci_dev;
3749
3750 RTL_W8(Cfg9346, Cfg9346_Unlock);
3751
3752 RTL_W8(MaxTxPacketSize, TxPacketMax);
3753
3754 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3755
3756 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3757
3758 RTL_W16(CPlusCmd, tp->cp_cmd);
3759
3760 RTL_W16(IntrMitigate, 0x5151);
3761
3762 /* Work around for RxFIFO overflow. */
3763 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3764 tp->mac_version == RTL_GIGA_MAC_VER_22) {
3765 tp->intr_event |= RxFIFOOver | PCSTimeout;
3766 tp->intr_event &= ~RxOverflow;
3767 }
3768
3769 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3770
3771 rtl_set_rx_mode(dev);
3772
3773 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3774 (InterFrameGap << TxInterFrameGapShift));
3775
3776 RTL_R8(IntrMask);
3777
3778 switch (tp->mac_version) {
3779 case RTL_GIGA_MAC_VER_11:
3780 rtl_hw_start_8168bb(ioaddr, pdev);
3781 break;
3782
3783 case RTL_GIGA_MAC_VER_12:
3784 case RTL_GIGA_MAC_VER_17:
3785 rtl_hw_start_8168bef(ioaddr, pdev);
3786 break;
3787
3788 case RTL_GIGA_MAC_VER_18:
3789 rtl_hw_start_8168cp_1(ioaddr, pdev);
3790 break;
3791
3792 case RTL_GIGA_MAC_VER_19:
3793 rtl_hw_start_8168c_1(ioaddr, pdev);
3794 break;
3795
3796 case RTL_GIGA_MAC_VER_20:
3797 rtl_hw_start_8168c_2(ioaddr, pdev);
3798 break;
3799
3800 case RTL_GIGA_MAC_VER_21:
3801 rtl_hw_start_8168c_3(ioaddr, pdev);
3802 break;
3803
3804 case RTL_GIGA_MAC_VER_22:
3805 rtl_hw_start_8168c_4(ioaddr, pdev);
3806 break;
3807
3808 case RTL_GIGA_MAC_VER_23:
3809 rtl_hw_start_8168cp_2(ioaddr, pdev);
3810 break;
3811
3812 case RTL_GIGA_MAC_VER_24:
3813 rtl_hw_start_8168cp_3(ioaddr, pdev);
3814 break;
3815
3816 case RTL_GIGA_MAC_VER_25:
3817 case RTL_GIGA_MAC_VER_26:
3818 case RTL_GIGA_MAC_VER_27:
3819 rtl_hw_start_8168d(ioaddr, pdev);
3820 break;
3821
3822 case RTL_GIGA_MAC_VER_28:
3823 rtl_hw_start_8168d_4(ioaddr, pdev);
3824 break;
3825
3826 default:
3827 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3828 dev->name, tp->mac_version);
3829 break;
3830 }
3831
3832 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3833
3834 RTL_W8(Cfg9346, Cfg9346_Lock);
3835
3836 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3837
3838 RTL_W16(IntrMask, tp->intr_event);
3839 }
3840
3841 #define R810X_CPCMD_QUIRK_MASK (\
3842 EnableBist | \
3843 Mac_dbgo_oe | \
3844 Force_half_dup | \
3845 Force_rxflow_en | \
3846 Force_txflow_en | \
3847 Cxpl_dbg_sel | \
3848 ASF | \
3849 PktCntrDisable | \
3850 PCIDAC | \
3851 PCIMulRW)
3852
3853 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3854 {
3855 static const struct ephy_info e_info_8102e_1[] = {
3856 { 0x01, 0, 0x6e65 },
3857 { 0x02, 0, 0x091f },
3858 { 0x03, 0, 0xc2f9 },
3859 { 0x06, 0, 0xafb5 },
3860 { 0x07, 0, 0x0e00 },
3861 { 0x19, 0, 0xec80 },
3862 { 0x01, 0, 0x2e65 },
3863 { 0x01, 0, 0x6e65 }
3864 };
3865 u8 cfg1;
3866
3867 rtl_csi_access_enable_2(ioaddr);
3868
3869 RTL_W8(DBG_REG, FIX_NAK_1);
3870
3871 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3872
3873 RTL_W8(Config1,
3874 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3875 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3876
3877 cfg1 = RTL_R8(Config1);
3878 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3879 RTL_W8(Config1, cfg1 & ~LEDS0);
3880
3881 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3882
3883 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3884 }
3885
3886 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3887 {
3888 rtl_csi_access_enable_2(ioaddr);
3889
3890 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3891
3892 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3893 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3894
3895 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3896 }
3897
3898 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3899 {
3900 rtl_hw_start_8102e_2(ioaddr, pdev);
3901
3902 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3903 }
3904
3905 static void rtl_hw_start_8101(struct net_device *dev)
3906 {
3907 struct rtl8169_private *tp = netdev_priv(dev);
3908 void __iomem *ioaddr = tp->mmio_addr;
3909 struct pci_dev *pdev = tp->pci_dev;
3910
3911 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3912 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3913 int cap = tp->pcie_cap;
3914
3915 if (cap) {
3916 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3917 PCI_EXP_DEVCTL_NOSNOOP_EN);
3918 }
3919 }
3920
3921 switch (tp->mac_version) {
3922 case RTL_GIGA_MAC_VER_07:
3923 rtl_hw_start_8102e_1(ioaddr, pdev);
3924 break;
3925
3926 case RTL_GIGA_MAC_VER_08:
3927 rtl_hw_start_8102e_3(ioaddr, pdev);
3928 break;
3929
3930 case RTL_GIGA_MAC_VER_09:
3931 rtl_hw_start_8102e_2(ioaddr, pdev);
3932 break;
3933 }
3934
3935 RTL_W8(Cfg9346, Cfg9346_Unlock);
3936
3937 RTL_W8(MaxTxPacketSize, TxPacketMax);
3938
3939 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3940
3941 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3942
3943 RTL_W16(CPlusCmd, tp->cp_cmd);
3944
3945 RTL_W16(IntrMitigate, 0x0000);
3946
3947 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3948
3949 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3950 rtl_set_rx_tx_config_registers(tp);
3951
3952 RTL_W8(Cfg9346, Cfg9346_Lock);
3953
3954 RTL_R8(IntrMask);
3955
3956 rtl_set_rx_mode(dev);
3957
3958 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3959
3960 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3961
3962 RTL_W16(IntrMask, tp->intr_event);
3963 }
3964
3965 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3966 {
3967 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3968 return -EINVAL;
3969
3970 dev->mtu = new_mtu;
3971 return 0;
3972 }
3973
3974 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3975 {
3976 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3977 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3978 }
3979
3980 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3981 void **data_buff, struct RxDesc *desc)
3982 {
3983 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3984 DMA_FROM_DEVICE);
3985
3986 kfree(*data_buff);
3987 *data_buff = NULL;
3988 rtl8169_make_unusable_by_asic(desc);
3989 }
3990
3991 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3992 {
3993 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3994
3995 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3996 }
3997
3998 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3999 u32 rx_buf_sz)
4000 {
4001 desc->addr = cpu_to_le64(mapping);
4002 wmb();
4003 rtl8169_mark_to_asic(desc, rx_buf_sz);
4004 }
4005
4006 static inline void *rtl8169_align(void *data)
4007 {
4008 return (void *)ALIGN((long)data, 16);
4009 }
4010
4011 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4012 struct RxDesc *desc)
4013 {
4014 void *data;
4015 dma_addr_t mapping;
4016 struct device *d = &tp->pci_dev->dev;
4017 struct net_device *dev = tp->dev;
4018 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4019
4020 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4021 if (!data)
4022 return NULL;
4023
4024 if (rtl8169_align(data) != data) {
4025 kfree(data);
4026 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4027 if (!data)
4028 return NULL;
4029 }
4030
4031 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4032 DMA_FROM_DEVICE);
4033 if (unlikely(dma_mapping_error(d, mapping))) {
4034 if (net_ratelimit())
4035 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4036 goto err_out;
4037 }
4038
4039 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4040 return data;
4041
4042 err_out:
4043 kfree(data);
4044 return NULL;
4045 }
4046
4047 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4048 {
4049 unsigned int i;
4050
4051 for (i = 0; i < NUM_RX_DESC; i++) {
4052 if (tp->Rx_databuff[i]) {
4053 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4054 tp->RxDescArray + i);
4055 }
4056 }
4057 }
4058
4059 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4060 {
4061 desc->opts1 |= cpu_to_le32(RingEnd);
4062 }
4063
4064 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4065 {
4066 unsigned int i;
4067
4068 for (i = 0; i < NUM_RX_DESC; i++) {
4069 void *data;
4070
4071 if (tp->Rx_databuff[i])
4072 continue;
4073
4074 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4075 if (!data) {
4076 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4077 goto err_out;
4078 }
4079 tp->Rx_databuff[i] = data;
4080 }
4081
4082 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4083 return 0;
4084
4085 err_out:
4086 rtl8169_rx_clear(tp);
4087 return -ENOMEM;
4088 }
4089
4090 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4091 {
4092 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4093 }
4094
4095 static int rtl8169_init_ring(struct net_device *dev)
4096 {
4097 struct rtl8169_private *tp = netdev_priv(dev);
4098
4099 rtl8169_init_ring_indexes(tp);
4100
4101 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4102 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4103
4104 return rtl8169_rx_fill(tp);
4105 }
4106
4107 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4108 struct TxDesc *desc)
4109 {
4110 unsigned int len = tx_skb->len;
4111
4112 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4113
4114 desc->opts1 = 0x00;
4115 desc->opts2 = 0x00;
4116 desc->addr = 0x00;
4117 tx_skb->len = 0;
4118 }
4119
4120 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4121 unsigned int n)
4122 {
4123 unsigned int i;
4124
4125 for (i = 0; i < n; i++) {
4126 unsigned int entry = (start + i) % NUM_TX_DESC;
4127 struct ring_info *tx_skb = tp->tx_skb + entry;
4128 unsigned int len = tx_skb->len;
4129
4130 if (len) {
4131 struct sk_buff *skb = tx_skb->skb;
4132
4133 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4134 tp->TxDescArray + entry);
4135 if (skb) {
4136 tp->dev->stats.tx_dropped++;
4137 dev_kfree_skb(skb);
4138 tx_skb->skb = NULL;
4139 }
4140 }
4141 }
4142 }
4143
4144 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4145 {
4146 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4147 tp->cur_tx = tp->dirty_tx = 0;
4148 }
4149
4150 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4151 {
4152 struct rtl8169_private *tp = netdev_priv(dev);
4153
4154 PREPARE_DELAYED_WORK(&tp->task, task);
4155 schedule_delayed_work(&tp->task, 4);
4156 }
4157
4158 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4159 {
4160 struct rtl8169_private *tp = netdev_priv(dev);
4161 void __iomem *ioaddr = tp->mmio_addr;
4162
4163 synchronize_irq(dev->irq);
4164
4165 /* Wait for any pending NAPI task to complete */
4166 napi_disable(&tp->napi);
4167
4168 rtl8169_irq_mask_and_ack(ioaddr);
4169
4170 tp->intr_mask = 0xffff;
4171 RTL_W16(IntrMask, tp->intr_event);
4172 napi_enable(&tp->napi);
4173 }
4174
4175 static void rtl8169_reinit_task(struct work_struct *work)
4176 {
4177 struct rtl8169_private *tp =
4178 container_of(work, struct rtl8169_private, task.work);
4179 struct net_device *dev = tp->dev;
4180 int ret;
4181
4182 rtnl_lock();
4183
4184 if (!netif_running(dev))
4185 goto out_unlock;
4186
4187 rtl8169_wait_for_quiescence(dev);
4188 rtl8169_close(dev);
4189
4190 ret = rtl8169_open(dev);
4191 if (unlikely(ret < 0)) {
4192 if (net_ratelimit())
4193 netif_err(tp, drv, dev,
4194 "reinit failure (status = %d). Rescheduling\n",
4195 ret);
4196 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4197 }
4198
4199 out_unlock:
4200 rtnl_unlock();
4201 }
4202
4203 static void rtl8169_reset_task(struct work_struct *work)
4204 {
4205 struct rtl8169_private *tp =
4206 container_of(work, struct rtl8169_private, task.work);
4207 struct net_device *dev = tp->dev;
4208
4209 rtnl_lock();
4210
4211 if (!netif_running(dev))
4212 goto out_unlock;
4213
4214 rtl8169_wait_for_quiescence(dev);
4215
4216 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4217 rtl8169_tx_clear(tp);
4218
4219 if (tp->dirty_rx == tp->cur_rx) {
4220 rtl8169_init_ring_indexes(tp);
4221 rtl_hw_start(dev);
4222 netif_wake_queue(dev);
4223 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4224 } else {
4225 if (net_ratelimit())
4226 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4227 rtl8169_schedule_work(dev, rtl8169_reset_task);
4228 }
4229
4230 out_unlock:
4231 rtnl_unlock();
4232 }
4233
4234 static void rtl8169_tx_timeout(struct net_device *dev)
4235 {
4236 struct rtl8169_private *tp = netdev_priv(dev);
4237
4238 rtl8169_hw_reset(tp);
4239
4240 /* Let's wait a bit while any (async) irq lands on */
4241 rtl8169_schedule_work(dev, rtl8169_reset_task);
4242 }
4243
4244 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4245 u32 opts1)
4246 {
4247 struct skb_shared_info *info = skb_shinfo(skb);
4248 unsigned int cur_frag, entry;
4249 struct TxDesc * uninitialized_var(txd);
4250 struct device *d = &tp->pci_dev->dev;
4251
4252 entry = tp->cur_tx;
4253 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4254 skb_frag_t *frag = info->frags + cur_frag;
4255 dma_addr_t mapping;
4256 u32 status, len;
4257 void *addr;
4258
4259 entry = (entry + 1) % NUM_TX_DESC;
4260
4261 txd = tp->TxDescArray + entry;
4262 len = frag->size;
4263 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4264 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4265 if (unlikely(dma_mapping_error(d, mapping))) {
4266 if (net_ratelimit())
4267 netif_err(tp, drv, tp->dev,
4268 "Failed to map TX fragments DMA!\n");
4269 goto err_out;
4270 }
4271
4272 /* anti gcc 2.95.3 bugware (sic) */
4273 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4274
4275 txd->opts1 = cpu_to_le32(status);
4276 txd->addr = cpu_to_le64(mapping);
4277
4278 tp->tx_skb[entry].len = len;
4279 }
4280
4281 if (cur_frag) {
4282 tp->tx_skb[entry].skb = skb;
4283 txd->opts1 |= cpu_to_le32(LastFrag);
4284 }
4285
4286 return cur_frag;
4287
4288 err_out:
4289 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4290 return -EIO;
4291 }
4292
4293 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4294 {
4295 if (dev->features & NETIF_F_TSO) {
4296 u32 mss = skb_shinfo(skb)->gso_size;
4297
4298 if (mss)
4299 return LargeSend | ((mss & MSSMask) << MSSShift);
4300 }
4301 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4302 const struct iphdr *ip = ip_hdr(skb);
4303
4304 if (ip->protocol == IPPROTO_TCP)
4305 return IPCS | TCPCS;
4306 else if (ip->protocol == IPPROTO_UDP)
4307 return IPCS | UDPCS;
4308 WARN_ON(1); /* we need a WARN() */
4309 }
4310 return 0;
4311 }
4312
4313 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4314 struct net_device *dev)
4315 {
4316 struct rtl8169_private *tp = netdev_priv(dev);
4317 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4318 struct TxDesc *txd = tp->TxDescArray + entry;
4319 void __iomem *ioaddr = tp->mmio_addr;
4320 struct device *d = &tp->pci_dev->dev;
4321 dma_addr_t mapping;
4322 u32 status, len;
4323 u32 opts1;
4324 int frags;
4325
4326 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4327 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4328 goto err_stop_0;
4329 }
4330
4331 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4332 goto err_stop_0;
4333
4334 len = skb_headlen(skb);
4335 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4336 if (unlikely(dma_mapping_error(d, mapping))) {
4337 if (net_ratelimit())
4338 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4339 goto err_dma_0;
4340 }
4341
4342 tp->tx_skb[entry].len = len;
4343 txd->addr = cpu_to_le64(mapping);
4344 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4345
4346 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4347
4348 frags = rtl8169_xmit_frags(tp, skb, opts1);
4349 if (frags < 0)
4350 goto err_dma_1;
4351 else if (frags)
4352 opts1 |= FirstFrag;
4353 else {
4354 opts1 |= FirstFrag | LastFrag;
4355 tp->tx_skb[entry].skb = skb;
4356 }
4357
4358 wmb();
4359
4360 /* anti gcc 2.95.3 bugware (sic) */
4361 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4362 txd->opts1 = cpu_to_le32(status);
4363
4364 tp->cur_tx += frags + 1;
4365
4366 wmb();
4367
4368 RTL_W8(TxPoll, NPQ); /* set polling bit */
4369
4370 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4371 netif_stop_queue(dev);
4372 smp_rmb();
4373 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4374 netif_wake_queue(dev);
4375 }
4376
4377 return NETDEV_TX_OK;
4378
4379 err_dma_1:
4380 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4381 err_dma_0:
4382 dev_kfree_skb(skb);
4383 dev->stats.tx_dropped++;
4384 return NETDEV_TX_OK;
4385
4386 err_stop_0:
4387 netif_stop_queue(dev);
4388 dev->stats.tx_dropped++;
4389 return NETDEV_TX_BUSY;
4390 }
4391
4392 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4393 {
4394 struct rtl8169_private *tp = netdev_priv(dev);
4395 struct pci_dev *pdev = tp->pci_dev;
4396 u16 pci_status, pci_cmd;
4397
4398 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4399 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4400
4401 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4402 pci_cmd, pci_status);
4403
4404 /*
4405 * The recovery sequence below admits a very elaborated explanation:
4406 * - it seems to work;
4407 * - I did not see what else could be done;
4408 * - it makes iop3xx happy.
4409 *
4410 * Feel free to adjust to your needs.
4411 */
4412 if (pdev->broken_parity_status)
4413 pci_cmd &= ~PCI_COMMAND_PARITY;
4414 else
4415 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4416
4417 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4418
4419 pci_write_config_word(pdev, PCI_STATUS,
4420 pci_status & (PCI_STATUS_DETECTED_PARITY |
4421 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4422 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4423
4424 /* The infamous DAC f*ckup only happens at boot time */
4425 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4426 void __iomem *ioaddr = tp->mmio_addr;
4427
4428 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4429 tp->cp_cmd &= ~PCIDAC;
4430 RTL_W16(CPlusCmd, tp->cp_cmd);
4431 dev->features &= ~NETIF_F_HIGHDMA;
4432 }
4433
4434 rtl8169_hw_reset(tp);
4435
4436 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4437 }
4438
4439 static void rtl8169_tx_interrupt(struct net_device *dev,
4440 struct rtl8169_private *tp,
4441 void __iomem *ioaddr)
4442 {
4443 unsigned int dirty_tx, tx_left;
4444
4445 dirty_tx = tp->dirty_tx;
4446 smp_rmb();
4447 tx_left = tp->cur_tx - dirty_tx;
4448
4449 while (tx_left > 0) {
4450 unsigned int entry = dirty_tx % NUM_TX_DESC;
4451 struct ring_info *tx_skb = tp->tx_skb + entry;
4452 u32 status;
4453
4454 rmb();
4455 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4456 if (status & DescOwn)
4457 break;
4458
4459 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4460 tp->TxDescArray + entry);
4461 if (status & LastFrag) {
4462 dev->stats.tx_packets++;
4463 dev->stats.tx_bytes += tx_skb->skb->len;
4464 dev_kfree_skb(tx_skb->skb);
4465 tx_skb->skb = NULL;
4466 }
4467 dirty_tx++;
4468 tx_left--;
4469 }
4470
4471 if (tp->dirty_tx != dirty_tx) {
4472 tp->dirty_tx = dirty_tx;
4473 smp_wmb();
4474 if (netif_queue_stopped(dev) &&
4475 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4476 netif_wake_queue(dev);
4477 }
4478 /*
4479 * 8168 hack: TxPoll requests are lost when the Tx packets are
4480 * too close. Let's kick an extra TxPoll request when a burst
4481 * of start_xmit activity is detected (if it is not detected,
4482 * it is slow enough). -- FR
4483 */
4484 smp_rmb();
4485 if (tp->cur_tx != dirty_tx)
4486 RTL_W8(TxPoll, NPQ);
4487 }
4488 }
4489
4490 static inline int rtl8169_fragmented_frame(u32 status)
4491 {
4492 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4493 }
4494
4495 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4496 {
4497 u32 status = opts1 & RxProtoMask;
4498
4499 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4500 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4501 skb->ip_summed = CHECKSUM_UNNECESSARY;
4502 else
4503 skb_checksum_none_assert(skb);
4504 }
4505
4506 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4507 struct rtl8169_private *tp,
4508 int pkt_size,
4509 dma_addr_t addr)
4510 {
4511 struct sk_buff *skb;
4512 struct device *d = &tp->pci_dev->dev;
4513
4514 data = rtl8169_align(data);
4515 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4516 prefetch(data);
4517 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4518 if (skb)
4519 memcpy(skb->data, data, pkt_size);
4520 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4521
4522 return skb;
4523 }
4524
4525 /*
4526 * Warning : rtl8169_rx_interrupt() might be called :
4527 * 1) from NAPI (softirq) context
4528 * (polling = 1 : we should call netif_receive_skb())
4529 * 2) from process context (rtl8169_reset_task())
4530 * (polling = 0 : we must call netif_rx() instead)
4531 */
4532 static int rtl8169_rx_interrupt(struct net_device *dev,
4533 struct rtl8169_private *tp,
4534 void __iomem *ioaddr, u32 budget)
4535 {
4536 unsigned int cur_rx, rx_left;
4537 unsigned int count;
4538 int polling = (budget != ~(u32)0) ? 1 : 0;
4539
4540 cur_rx = tp->cur_rx;
4541 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4542 rx_left = min(rx_left, budget);
4543
4544 for (; rx_left > 0; rx_left--, cur_rx++) {
4545 unsigned int entry = cur_rx % NUM_RX_DESC;
4546 struct RxDesc *desc = tp->RxDescArray + entry;
4547 u32 status;
4548
4549 rmb();
4550 status = le32_to_cpu(desc->opts1);
4551
4552 if (status & DescOwn)
4553 break;
4554 if (unlikely(status & RxRES)) {
4555 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4556 status);
4557 dev->stats.rx_errors++;
4558 if (status & (RxRWT | RxRUNT))
4559 dev->stats.rx_length_errors++;
4560 if (status & RxCRC)
4561 dev->stats.rx_crc_errors++;
4562 if (status & RxFOVF) {
4563 rtl8169_schedule_work(dev, rtl8169_reset_task);
4564 dev->stats.rx_fifo_errors++;
4565 }
4566 rtl8169_mark_to_asic(desc, rx_buf_sz);
4567 } else {
4568 struct sk_buff *skb;
4569 dma_addr_t addr = le64_to_cpu(desc->addr);
4570 int pkt_size = (status & 0x00001FFF) - 4;
4571
4572 /*
4573 * The driver does not support incoming fragmented
4574 * frames. They are seen as a symptom of over-mtu
4575 * sized frames.
4576 */
4577 if (unlikely(rtl8169_fragmented_frame(status))) {
4578 dev->stats.rx_dropped++;
4579 dev->stats.rx_length_errors++;
4580 rtl8169_mark_to_asic(desc, rx_buf_sz);
4581 continue;
4582 }
4583
4584 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4585 tp, pkt_size, addr);
4586 rtl8169_mark_to_asic(desc, rx_buf_sz);
4587 if (!skb) {
4588 dev->stats.rx_dropped++;
4589 continue;
4590 }
4591
4592 rtl8169_rx_csum(skb, status);
4593 skb_put(skb, pkt_size);
4594 skb->protocol = eth_type_trans(skb, dev);
4595
4596 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4597 if (likely(polling))
4598 napi_gro_receive(&tp->napi, skb);
4599 else
4600 netif_rx(skb);
4601 }
4602
4603 dev->stats.rx_bytes += pkt_size;
4604 dev->stats.rx_packets++;
4605 }
4606
4607 /* Work around for AMD plateform. */
4608 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4609 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4610 desc->opts2 = 0;
4611 cur_rx++;
4612 }
4613 }
4614
4615 count = cur_rx - tp->cur_rx;
4616 tp->cur_rx = cur_rx;
4617
4618 tp->dirty_rx += count;
4619
4620 return count;
4621 }
4622
4623 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4624 {
4625 struct net_device *dev = dev_instance;
4626 struct rtl8169_private *tp = netdev_priv(dev);
4627 void __iomem *ioaddr = tp->mmio_addr;
4628 int handled = 0;
4629 int status;
4630
4631 /* loop handling interrupts until we have no new ones or
4632 * we hit a invalid/hotplug case.
4633 */
4634 status = RTL_R16(IntrStatus);
4635 while (status && status != 0xffff) {
4636 handled = 1;
4637
4638 /* Handle all of the error cases first. These will reset
4639 * the chip, so just exit the loop.
4640 */
4641 if (unlikely(!netif_running(dev))) {
4642 rtl8169_asic_down(ioaddr);
4643 break;
4644 }
4645
4646 if (unlikely(status & RxFIFOOver)) {
4647 switch (tp->mac_version) {
4648 /* Work around for rx fifo overflow */
4649 case RTL_GIGA_MAC_VER_11:
4650 case RTL_GIGA_MAC_VER_22:
4651 case RTL_GIGA_MAC_VER_26:
4652 netif_stop_queue(dev);
4653 rtl8169_tx_timeout(dev);
4654 goto done;
4655 /* Testers needed. */
4656 case RTL_GIGA_MAC_VER_17:
4657 case RTL_GIGA_MAC_VER_19:
4658 case RTL_GIGA_MAC_VER_20:
4659 case RTL_GIGA_MAC_VER_21:
4660 case RTL_GIGA_MAC_VER_23:
4661 case RTL_GIGA_MAC_VER_24:
4662 case RTL_GIGA_MAC_VER_27:
4663 case RTL_GIGA_MAC_VER_28:
4664 /* Experimental science. Pktgen proof. */
4665 case RTL_GIGA_MAC_VER_12:
4666 case RTL_GIGA_MAC_VER_25:
4667 if (status == RxFIFOOver)
4668 goto done;
4669 break;
4670 default:
4671 break;
4672 }
4673 }
4674
4675 if (unlikely(status & SYSErr)) {
4676 rtl8169_pcierr_interrupt(dev);
4677 break;
4678 }
4679
4680 if (status & LinkChg)
4681 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4682
4683 /* We need to see the lastest version of tp->intr_mask to
4684 * avoid ignoring an MSI interrupt and having to wait for
4685 * another event which may never come.
4686 */
4687 smp_rmb();
4688 if (status & tp->intr_mask & tp->napi_event) {
4689 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4690 tp->intr_mask = ~tp->napi_event;
4691
4692 if (likely(napi_schedule_prep(&tp->napi)))
4693 __napi_schedule(&tp->napi);
4694 else
4695 netif_info(tp, intr, dev,
4696 "interrupt %04x in poll\n", status);
4697 }
4698
4699 /* We only get a new MSI interrupt when all active irq
4700 * sources on the chip have been acknowledged. So, ack
4701 * everything we've seen and check if new sources have become
4702 * active to avoid blocking all interrupts from the chip.
4703 */
4704 RTL_W16(IntrStatus,
4705 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4706 status = RTL_R16(IntrStatus);
4707 }
4708 done:
4709 return IRQ_RETVAL(handled);
4710 }
4711
4712 static int rtl8169_poll(struct napi_struct *napi, int budget)
4713 {
4714 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4715 struct net_device *dev = tp->dev;
4716 void __iomem *ioaddr = tp->mmio_addr;
4717 int work_done;
4718
4719 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4720 rtl8169_tx_interrupt(dev, tp, ioaddr);
4721
4722 if (work_done < budget) {
4723 napi_complete(napi);
4724
4725 /* We need for force the visibility of tp->intr_mask
4726 * for other CPUs, as we can loose an MSI interrupt
4727 * and potentially wait for a retransmit timeout if we don't.
4728 * The posted write to IntrMask is safe, as it will
4729 * eventually make it to the chip and we won't loose anything
4730 * until it does.
4731 */
4732 tp->intr_mask = 0xffff;
4733 wmb();
4734 RTL_W16(IntrMask, tp->intr_event);
4735 }
4736
4737 return work_done;
4738 }
4739
4740 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4741 {
4742 struct rtl8169_private *tp = netdev_priv(dev);
4743
4744 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4745 return;
4746
4747 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4748 RTL_W32(RxMissed, 0);
4749 }
4750
4751 static void rtl8169_down(struct net_device *dev)
4752 {
4753 struct rtl8169_private *tp = netdev_priv(dev);
4754 void __iomem *ioaddr = tp->mmio_addr;
4755
4756 rtl8169_delete_timer(dev);
4757
4758 netif_stop_queue(dev);
4759
4760 napi_disable(&tp->napi);
4761
4762 spin_lock_irq(&tp->lock);
4763
4764 rtl8169_asic_down(ioaddr);
4765 /*
4766 * At this point device interrupts can not be enabled in any function,
4767 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4768 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4769 */
4770 rtl8169_rx_missed(dev, ioaddr);
4771
4772 spin_unlock_irq(&tp->lock);
4773
4774 synchronize_irq(dev->irq);
4775
4776 /* Give a racing hard_start_xmit a few cycles to complete. */
4777 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4778
4779 rtl8169_tx_clear(tp);
4780
4781 rtl8169_rx_clear(tp);
4782
4783 rtl_pll_power_down(tp);
4784 }
4785
4786 static int rtl8169_close(struct net_device *dev)
4787 {
4788 struct rtl8169_private *tp = netdev_priv(dev);
4789 struct pci_dev *pdev = tp->pci_dev;
4790
4791 pm_runtime_get_sync(&pdev->dev);
4792
4793 /* update counters before going down */
4794 rtl8169_update_counters(dev);
4795
4796 rtl8169_down(dev);
4797
4798 free_irq(dev->irq, dev);
4799
4800 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4801 tp->RxPhyAddr);
4802 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4803 tp->TxPhyAddr);
4804 tp->TxDescArray = NULL;
4805 tp->RxDescArray = NULL;
4806
4807 pm_runtime_put_sync(&pdev->dev);
4808
4809 return 0;
4810 }
4811
4812 static void rtl_set_rx_mode(struct net_device *dev)
4813 {
4814 struct rtl8169_private *tp = netdev_priv(dev);
4815 void __iomem *ioaddr = tp->mmio_addr;
4816 unsigned long flags;
4817 u32 mc_filter[2]; /* Multicast hash filter */
4818 int rx_mode;
4819 u32 tmp = 0;
4820
4821 if (dev->flags & IFF_PROMISC) {
4822 /* Unconditionally log net taps. */
4823 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4824 rx_mode =
4825 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4826 AcceptAllPhys;
4827 mc_filter[1] = mc_filter[0] = 0xffffffff;
4828 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4829 (dev->flags & IFF_ALLMULTI)) {
4830 /* Too many to filter perfectly -- accept all multicasts. */
4831 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4832 mc_filter[1] = mc_filter[0] = 0xffffffff;
4833 } else {
4834 struct netdev_hw_addr *ha;
4835
4836 rx_mode = AcceptBroadcast | AcceptMyPhys;
4837 mc_filter[1] = mc_filter[0] = 0;
4838 netdev_for_each_mc_addr(ha, dev) {
4839 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4840 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4841 rx_mode |= AcceptMulticast;
4842 }
4843 }
4844
4845 spin_lock_irqsave(&tp->lock, flags);
4846
4847 tmp = rtl8169_rx_config | rx_mode |
4848 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4849
4850 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4851 u32 data = mc_filter[0];
4852
4853 mc_filter[0] = swab32(mc_filter[1]);
4854 mc_filter[1] = swab32(data);
4855 }
4856
4857 RTL_W32(MAR0 + 4, mc_filter[1]);
4858 RTL_W32(MAR0 + 0, mc_filter[0]);
4859
4860 RTL_W32(RxConfig, tmp);
4861
4862 spin_unlock_irqrestore(&tp->lock, flags);
4863 }
4864
4865 /**
4866 * rtl8169_get_stats - Get rtl8169 read/write statistics
4867 * @dev: The Ethernet Device to get statistics for
4868 *
4869 * Get TX/RX statistics for rtl8169
4870 */
4871 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4872 {
4873 struct rtl8169_private *tp = netdev_priv(dev);
4874 void __iomem *ioaddr = tp->mmio_addr;
4875 unsigned long flags;
4876
4877 if (netif_running(dev)) {
4878 spin_lock_irqsave(&tp->lock, flags);
4879 rtl8169_rx_missed(dev, ioaddr);
4880 spin_unlock_irqrestore(&tp->lock, flags);
4881 }
4882
4883 return &dev->stats;
4884 }
4885
4886 static void rtl8169_net_suspend(struct net_device *dev)
4887 {
4888 struct rtl8169_private *tp = netdev_priv(dev);
4889
4890 if (!netif_running(dev))
4891 return;
4892
4893 rtl_pll_power_down(tp);
4894
4895 netif_device_detach(dev);
4896 netif_stop_queue(dev);
4897 }
4898
4899 #ifdef CONFIG_PM
4900
4901 static int rtl8169_suspend(struct device *device)
4902 {
4903 struct pci_dev *pdev = to_pci_dev(device);
4904 struct net_device *dev = pci_get_drvdata(pdev);
4905
4906 rtl8169_net_suspend(dev);
4907
4908 return 0;
4909 }
4910
4911 static void __rtl8169_resume(struct net_device *dev)
4912 {
4913 struct rtl8169_private *tp = netdev_priv(dev);
4914
4915 netif_device_attach(dev);
4916
4917 rtl_pll_power_up(tp);
4918
4919 rtl8169_schedule_work(dev, rtl8169_reset_task);
4920 }
4921
4922 static int rtl8169_resume(struct device *device)
4923 {
4924 struct pci_dev *pdev = to_pci_dev(device);
4925 struct net_device *dev = pci_get_drvdata(pdev);
4926 struct rtl8169_private *tp = netdev_priv(dev);
4927
4928 rtl8169_init_phy(dev, tp);
4929
4930 if (netif_running(dev))
4931 __rtl8169_resume(dev);
4932
4933 return 0;
4934 }
4935
4936 static int rtl8169_runtime_suspend(struct device *device)
4937 {
4938 struct pci_dev *pdev = to_pci_dev(device);
4939 struct net_device *dev = pci_get_drvdata(pdev);
4940 struct rtl8169_private *tp = netdev_priv(dev);
4941
4942 if (!tp->TxDescArray)
4943 return 0;
4944
4945 spin_lock_irq(&tp->lock);
4946 tp->saved_wolopts = __rtl8169_get_wol(tp);
4947 __rtl8169_set_wol(tp, WAKE_ANY);
4948 spin_unlock_irq(&tp->lock);
4949
4950 rtl8169_net_suspend(dev);
4951
4952 return 0;
4953 }
4954
4955 static int rtl8169_runtime_resume(struct device *device)
4956 {
4957 struct pci_dev *pdev = to_pci_dev(device);
4958 struct net_device *dev = pci_get_drvdata(pdev);
4959 struct rtl8169_private *tp = netdev_priv(dev);
4960
4961 if (!tp->TxDescArray)
4962 return 0;
4963
4964 spin_lock_irq(&tp->lock);
4965 __rtl8169_set_wol(tp, tp->saved_wolopts);
4966 tp->saved_wolopts = 0;
4967 spin_unlock_irq(&tp->lock);
4968
4969 rtl8169_init_phy(dev, tp);
4970
4971 __rtl8169_resume(dev);
4972
4973 return 0;
4974 }
4975
4976 static int rtl8169_runtime_idle(struct device *device)
4977 {
4978 struct pci_dev *pdev = to_pci_dev(device);
4979 struct net_device *dev = pci_get_drvdata(pdev);
4980 struct rtl8169_private *tp = netdev_priv(dev);
4981
4982 return tp->TxDescArray ? -EBUSY : 0;
4983 }
4984
4985 static const struct dev_pm_ops rtl8169_pm_ops = {
4986 .suspend = rtl8169_suspend,
4987 .resume = rtl8169_resume,
4988 .freeze = rtl8169_suspend,
4989 .thaw = rtl8169_resume,
4990 .poweroff = rtl8169_suspend,
4991 .restore = rtl8169_resume,
4992 .runtime_suspend = rtl8169_runtime_suspend,
4993 .runtime_resume = rtl8169_runtime_resume,
4994 .runtime_idle = rtl8169_runtime_idle,
4995 };
4996
4997 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4998
4999 #else /* !CONFIG_PM */
5000
5001 #define RTL8169_PM_OPS NULL
5002
5003 #endif /* !CONFIG_PM */
5004
5005 static void rtl_shutdown(struct pci_dev *pdev)
5006 {
5007 struct net_device *dev = pci_get_drvdata(pdev);
5008 struct rtl8169_private *tp = netdev_priv(dev);
5009 void __iomem *ioaddr = tp->mmio_addr;
5010
5011 rtl8169_net_suspend(dev);
5012
5013 /* restore original MAC address */
5014 rtl_rar_set(tp, dev->perm_addr);
5015
5016 spin_lock_irq(&tp->lock);
5017
5018 rtl8169_asic_down(ioaddr);
5019
5020 spin_unlock_irq(&tp->lock);
5021
5022 if (system_state == SYSTEM_POWER_OFF) {
5023 /* WoL fails with some 8168 when the receiver is disabled. */
5024 if (tp->features & RTL_FEATURE_WOL) {
5025 pci_clear_master(pdev);
5026
5027 RTL_W8(ChipCmd, CmdRxEnb);
5028 /* PCI commit */
5029 RTL_R8(ChipCmd);
5030 }
5031
5032 pci_wake_from_d3(pdev, true);
5033 pci_set_power_state(pdev, PCI_D3hot);
5034 }
5035 }
5036
5037 static struct pci_driver rtl8169_pci_driver = {
5038 .name = MODULENAME,
5039 .id_table = rtl8169_pci_tbl,
5040 .probe = rtl8169_init_one,
5041 .remove = __devexit_p(rtl8169_remove_one),
5042 .shutdown = rtl_shutdown,
5043 .driver.pm = RTL8169_PM_OPS,
5044 };
5045
5046 static int __init rtl8169_init_module(void)
5047 {
5048 return pci_register_driver(&rtl8169_pci_driver);
5049 }
5050
5051 static void __exit rtl8169_cleanup_module(void)
5052 {
5053 pci_unregister_driver(&rtl8169_pci_driver);
5054 }
5055
5056 module_init(rtl8169_init_module);
5057 module_exit(rtl8169_cleanup_module);
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