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r8169: delay phy init until device opens.
[mirror_ubuntu-bionic-kernel.git] / drivers / net / r8169.c
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28
29 #include <asm/system.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
36
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
40 #ifdef RTL8169_DEBUG
41 #define assert(expr) \
42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
44 #expr,__FILE__,__func__,__LINE__); \
45 }
46 #define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
48 #else
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
52
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
55
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
62
63 /* MAC address length */
64 #define MAC_ADDR_LEN 6
65
66 #define MAX_READ_REQUEST_SHIFT 12
67 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
83
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
87
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) readl (ioaddr + (reg))
95
96 enum mac_version {
97 RTL_GIGA_MAC_NONE = 0x00,
98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
126 };
127
128 #define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
130
131 static const struct {
132 const char *name;
133 u8 mac_version;
134 u32 RxConfigMask; /* Clears the bits supported by this chip */
135 } rtl_chip_info[] = {
136 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
142 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
150 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
164 };
165 #undef _R
166
167 enum cfg_version {
168 RTL_CFG_0 = 0x00,
169 RTL_CFG_1,
170 RTL_CFG_2
171 };
172
173 static void rtl_hw_start_8169(struct net_device *);
174 static void rtl_hw_start_8168(struct net_device *);
175 static void rtl_hw_start_8101(struct net_device *);
176
177 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
184 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
186 { PCI_VENDOR_ID_LINKSYS, 0x1032,
187 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
188 { 0x0001, 0x8168,
189 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
190 {0,},
191 };
192
193 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
195 static int rx_buf_sz = 16383;
196 static int use_dac;
197 static struct {
198 u32 msg_enable;
199 } debug = { -1 };
200
201 enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
203 MAC4 = 4,
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
236
237 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
238
239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
240
241 #define TxPacketMax (8064 >> 7)
242
243 FuncEvent = 0xf0,
244 FuncEventMask = 0xf4,
245 FuncPresetState = 0xf8,
246 FuncForceEvent = 0xfc,
247 };
248
249 enum rtl8110_registers {
250 TBICSR = 0x64,
251 TBI_ANAR = 0x68,
252 TBI_LPAR = 0x6a,
253 };
254
255 enum rtl8168_8101_registers {
256 CSIDR = 0x64,
257 CSIAR = 0x68,
258 #define CSIAR_FLAG 0x80000000
259 #define CSIAR_WRITE_CMD 0x80000000
260 #define CSIAR_BYTE_ENABLE 0x0f
261 #define CSIAR_BYTE_ENABLE_SHIFT 12
262 #define CSIAR_ADDR_MASK 0x0fff
263 PMCH = 0x6f,
264 EPHYAR = 0x80,
265 #define EPHYAR_FLAG 0x80000000
266 #define EPHYAR_WRITE_CMD 0x80000000
267 #define EPHYAR_REG_MASK 0x1f
268 #define EPHYAR_REG_SHIFT 16
269 #define EPHYAR_DATA_MASK 0xffff
270 DBG_REG = 0xd1,
271 #define FIX_NAK_1 (1 << 4)
272 #define FIX_NAK_2 (1 << 3)
273 EFUSEAR = 0xdc,
274 #define EFUSEAR_FLAG 0x80000000
275 #define EFUSEAR_WRITE_CMD 0x80000000
276 #define EFUSEAR_READ_CMD 0x00000000
277 #define EFUSEAR_REG_MASK 0x03ff
278 #define EFUSEAR_REG_SHIFT 8
279 #define EFUSEAR_DATA_MASK 0xff
280 };
281
282 enum rtl8168_registers {
283 ERIDR = 0x70,
284 ERIAR = 0x74,
285 #define ERIAR_FLAG 0x80000000
286 #define ERIAR_WRITE_CMD 0x80000000
287 #define ERIAR_READ_CMD 0x00000000
288 #define ERIAR_ADDR_BYTE_ALIGN 4
289 #define ERIAR_EXGMAC 0
290 #define ERIAR_MSIX 1
291 #define ERIAR_ASF 2
292 #define ERIAR_TYPE_SHIFT 16
293 #define ERIAR_BYTEEN 0x0f
294 #define ERIAR_BYTEEN_SHIFT 12
295 EPHY_RXER_NUM = 0x7c,
296 OCPDR = 0xb0, /* OCP GPHY access */
297 #define OCPDR_WRITE_CMD 0x80000000
298 #define OCPDR_READ_CMD 0x00000000
299 #define OCPDR_REG_MASK 0x7f
300 #define OCPDR_GPHY_REG_SHIFT 16
301 #define OCPDR_DATA_MASK 0xffff
302 OCPAR = 0xb4,
303 #define OCPAR_FLAG 0x80000000
304 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
305 #define OCPAR_GPHY_READ_CMD 0x0000f060
306 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
307 };
308
309 enum rtl_register_content {
310 /* InterruptStatusBits */
311 SYSErr = 0x8000,
312 PCSTimeout = 0x4000,
313 SWInt = 0x0100,
314 TxDescUnavail = 0x0080,
315 RxFIFOOver = 0x0040,
316 LinkChg = 0x0020,
317 RxOverflow = 0x0010,
318 TxErr = 0x0008,
319 TxOK = 0x0004,
320 RxErr = 0x0002,
321 RxOK = 0x0001,
322
323 /* RxStatusDesc */
324 RxFOVF = (1 << 23),
325 RxRWT = (1 << 22),
326 RxRES = (1 << 21),
327 RxRUNT = (1 << 20),
328 RxCRC = (1 << 19),
329
330 /* ChipCmdBits */
331 CmdReset = 0x10,
332 CmdRxEnb = 0x08,
333 CmdTxEnb = 0x04,
334 RxBufEmpty = 0x01,
335
336 /* TXPoll register p.5 */
337 HPQ = 0x80, /* Poll cmd on the high prio queue */
338 NPQ = 0x40, /* Poll cmd on the low prio queue */
339 FSWInt = 0x01, /* Forced software interrupt */
340
341 /* Cfg9346Bits */
342 Cfg9346_Lock = 0x00,
343 Cfg9346_Unlock = 0xc0,
344
345 /* rx_mode_bits */
346 AcceptErr = 0x20,
347 AcceptRunt = 0x10,
348 AcceptBroadcast = 0x08,
349 AcceptMulticast = 0x04,
350 AcceptMyPhys = 0x02,
351 AcceptAllPhys = 0x01,
352
353 /* RxConfigBits */
354 RxCfgFIFOShift = 13,
355 RxCfgDMAShift = 8,
356
357 /* TxConfigBits */
358 TxInterFrameGapShift = 24,
359 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
360
361 /* Config1 register p.24 */
362 LEDS1 = (1 << 7),
363 LEDS0 = (1 << 6),
364 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
365 Speed_down = (1 << 4),
366 MEMMAP = (1 << 3),
367 IOMAP = (1 << 2),
368 VPD = (1 << 1),
369 PMEnable = (1 << 0), /* Power Management Enable */
370
371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz = 0x01,
373 PCI_Clock_33MHz = 0x00,
374
375 /* Config3 register p.25 */
376 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
378 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
379
380 /* Config5 register p.27 */
381 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF = (1 << 5), /* Accept Multicast wakeup frame */
383 UWF = (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake = (1 << 1), /* LanWake enable/disable */
385 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
386
387 /* TBICSR p.28 */
388 TBIReset = 0x80000000,
389 TBILoopback = 0x40000000,
390 TBINwEnable = 0x20000000,
391 TBINwRestart = 0x10000000,
392 TBILinkOk = 0x02000000,
393 TBINwComplete = 0x01000000,
394
395 /* CPlusCmd p.31 */
396 EnableBist = (1 << 15), // 8168 8101
397 Mac_dbgo_oe = (1 << 14), // 8168 8101
398 Normal_mode = (1 << 13), // unused
399 Force_half_dup = (1 << 12), // 8168 8101
400 Force_rxflow_en = (1 << 11), // 8168 8101
401 Force_txflow_en = (1 << 10), // 8168 8101
402 Cxpl_dbg_sel = (1 << 9), // 8168 8101
403 ASF = (1 << 8), // 8168 8101
404 PktCntrDisable = (1 << 7), // 8168 8101
405 Mac_dbgo_sel = 0x001c, // 8168
406 RxVlan = (1 << 6),
407 RxChkSum = (1 << 5),
408 PCIDAC = (1 << 4),
409 PCIMulRW = (1 << 3),
410 INTT_0 = 0x0000, // 8168
411 INTT_1 = 0x0001, // 8168
412 INTT_2 = 0x0002, // 8168
413 INTT_3 = 0x0003, // 8168
414
415 /* rtl8169_PHYstatus */
416 TBI_Enable = 0x80,
417 TxFlowCtrl = 0x40,
418 RxFlowCtrl = 0x20,
419 _1000bpsF = 0x10,
420 _100bps = 0x08,
421 _10bps = 0x04,
422 LinkStatus = 0x02,
423 FullDup = 0x01,
424
425 /* _TBICSRBit */
426 TBILinkOK = 0x02000000,
427
428 /* DumpCounterCommand */
429 CounterDump = 0x8,
430 };
431
432 enum desc_status_bit {
433 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd = (1 << 30), /* End of descriptor ring */
435 FirstFrag = (1 << 29), /* First segment of a packet */
436 LastFrag = (1 << 28), /* Final segment of a packet */
437
438 /* Tx private */
439 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift = 16, /* MSS value position */
441 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS = (1 << 18), /* Calculate IP checksum */
443 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag = (1 << 17), /* Add VLAN tag */
446
447 /* Rx private */
448 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
449 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
450
451 #define RxProtoUDP (PID1)
452 #define RxProtoTCP (PID0)
453 #define RxProtoIP (PID1 | PID0)
454 #define RxProtoMask RxProtoIP
455
456 IPFail = (1 << 16), /* IP checksum failed */
457 UDPFail = (1 << 15), /* UDP/IP checksum failed */
458 TCPFail = (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag = (1 << 16), /* VLAN tag available */
460 };
461
462 #define RsvdMask 0x3fffc000
463
464 struct TxDesc {
465 __le32 opts1;
466 __le32 opts2;
467 __le64 addr;
468 };
469
470 struct RxDesc {
471 __le32 opts1;
472 __le32 opts2;
473 __le64 addr;
474 };
475
476 struct ring_info {
477 struct sk_buff *skb;
478 u32 len;
479 u8 __pad[sizeof(void *) - sizeof(u32)];
480 };
481
482 enum features {
483 RTL_FEATURE_WOL = (1 << 0),
484 RTL_FEATURE_MSI = (1 << 1),
485 RTL_FEATURE_GMII = (1 << 2),
486 };
487
488 struct rtl8169_counters {
489 __le64 tx_packets;
490 __le64 rx_packets;
491 __le64 tx_errors;
492 __le32 rx_errors;
493 __le16 rx_missed;
494 __le16 align_errors;
495 __le32 tx_one_collision;
496 __le32 tx_multi_collision;
497 __le64 rx_unicast;
498 __le64 rx_broadcast;
499 __le32 rx_multicast;
500 __le16 tx_aborted;
501 __le16 tx_underun;
502 };
503
504 struct rtl8169_private {
505 void __iomem *mmio_addr; /* memory map physical address */
506 struct pci_dev *pci_dev; /* Index of PCI device */
507 struct net_device *dev;
508 struct napi_struct napi;
509 spinlock_t lock; /* spin lock flag */
510 u32 msg_enable;
511 int chipset;
512 int mac_version;
513 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
515 u32 dirty_rx;
516 u32 dirty_tx;
517 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
518 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr;
520 dma_addr_t RxPhyAddr;
521 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
522 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
523 struct timer_list timer;
524 u16 cp_cmd;
525 u16 intr_event;
526 u16 napi_event;
527 u16 intr_mask;
528 int phy_1000_ctrl_reg;
529 #ifdef CONFIG_R8169_VLAN
530 struct vlan_group *vlgrp;
531 #endif
532
533 struct mdio_ops {
534 void (*write)(void __iomem *, int, int);
535 int (*read)(void __iomem *, int);
536 } mdio_ops;
537
538 struct pll_power_ops {
539 void (*down)(struct rtl8169_private *);
540 void (*up)(struct rtl8169_private *);
541 } pll_power_ops;
542
543 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
544 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
545 void (*phy_reset_enable)(struct rtl8169_private *tp);
546 void (*hw_start)(struct net_device *);
547 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
548 unsigned int (*link_ok)(void __iomem *);
549 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
550 int pcie_cap;
551 struct delayed_work task;
552 unsigned features;
553
554 struct mii_if_info mii;
555 struct rtl8169_counters counters;
556 u32 saved_wolopts;
557 };
558
559 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
560 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
561 module_param(use_dac, int, 0);
562 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
563 module_param_named(debug, debug.msg_enable, int, 0);
564 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
565 MODULE_LICENSE("GPL");
566 MODULE_VERSION(RTL8169_VERSION);
567 MODULE_FIRMWARE(FIRMWARE_8168D_1);
568 MODULE_FIRMWARE(FIRMWARE_8168D_2);
569
570 static int rtl8169_open(struct net_device *dev);
571 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
572 struct net_device *dev);
573 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
574 static int rtl8169_init_ring(struct net_device *dev);
575 static void rtl_hw_start(struct net_device *dev);
576 static int rtl8169_close(struct net_device *dev);
577 static void rtl_set_rx_mode(struct net_device *dev);
578 static void rtl8169_tx_timeout(struct net_device *dev);
579 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
580 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
581 void __iomem *, u32 budget);
582 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
583 static void rtl8169_down(struct net_device *dev);
584 static void rtl8169_rx_clear(struct rtl8169_private *tp);
585 static int rtl8169_poll(struct napi_struct *napi, int budget);
586
587 static const unsigned int rtl8169_rx_config =
588 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
589
590 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
591 {
592 void __iomem *ioaddr = tp->mmio_addr;
593 int i;
594
595 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
596 for (i = 0; i < 20; i++) {
597 udelay(100);
598 if (RTL_R32(OCPAR) & OCPAR_FLAG)
599 break;
600 }
601 return RTL_R32(OCPDR);
602 }
603
604 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
605 {
606 void __iomem *ioaddr = tp->mmio_addr;
607 int i;
608
609 RTL_W32(OCPDR, data);
610 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
611 for (i = 0; i < 20; i++) {
612 udelay(100);
613 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
614 break;
615 }
616 }
617
618 static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
619 {
620 int i;
621
622 RTL_W8(ERIDR, cmd);
623 RTL_W32(ERIAR, 0x800010e8);
624 msleep(2);
625 for (i = 0; i < 5; i++) {
626 udelay(100);
627 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
628 break;
629 }
630
631 ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
632 }
633
634 #define OOB_CMD_RESET 0x00
635 #define OOB_CMD_DRIVER_START 0x05
636 #define OOB_CMD_DRIVER_STOP 0x06
637
638 static void rtl8168_driver_start(struct rtl8169_private *tp)
639 {
640 int i;
641
642 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
643
644 for (i = 0; i < 10; i++) {
645 msleep(10);
646 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
647 break;
648 }
649 }
650
651 static void rtl8168_driver_stop(struct rtl8169_private *tp)
652 {
653 int i;
654
655 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
656
657 for (i = 0; i < 10; i++) {
658 msleep(10);
659 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
660 break;
661 }
662 }
663
664
665 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
666 {
667 int i;
668
669 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
670
671 for (i = 20; i > 0; i--) {
672 /*
673 * Check if the RTL8169 has completed writing to the specified
674 * MII register.
675 */
676 if (!(RTL_R32(PHYAR) & 0x80000000))
677 break;
678 udelay(25);
679 }
680 /*
681 * According to hardware specs a 20us delay is required after write
682 * complete indication, but before sending next command.
683 */
684 udelay(20);
685 }
686
687 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
688 {
689 int i, value = -1;
690
691 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
692
693 for (i = 20; i > 0; i--) {
694 /*
695 * Check if the RTL8169 has completed retrieving data from
696 * the specified MII register.
697 */
698 if (RTL_R32(PHYAR) & 0x80000000) {
699 value = RTL_R32(PHYAR) & 0xffff;
700 break;
701 }
702 udelay(25);
703 }
704 /*
705 * According to hardware specs a 20us delay is required after read
706 * complete indication, but before sending next command.
707 */
708 udelay(20);
709
710 return value;
711 }
712
713 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
714 {
715 int i;
716
717 RTL_W32(OCPDR, data |
718 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
719 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
720 RTL_W32(EPHY_RXER_NUM, 0);
721
722 for (i = 0; i < 100; i++) {
723 mdelay(1);
724 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
725 break;
726 }
727 }
728
729 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
730 {
731 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
732 (value & OCPDR_DATA_MASK));
733 }
734
735 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
736 {
737 int i;
738
739 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
740
741 mdelay(1);
742 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
743 RTL_W32(EPHY_RXER_NUM, 0);
744
745 for (i = 0; i < 100; i++) {
746 mdelay(1);
747 if (RTL_R32(OCPAR) & OCPAR_FLAG)
748 break;
749 }
750
751 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
752 }
753
754 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
755
756 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
757 {
758 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
759 }
760
761 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
762 {
763 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
764 }
765
766 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
767 {
768 r8168dp_2_mdio_start(ioaddr);
769
770 r8169_mdio_write(ioaddr, reg_addr, value);
771
772 r8168dp_2_mdio_stop(ioaddr);
773 }
774
775 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
776 {
777 int value;
778
779 r8168dp_2_mdio_start(ioaddr);
780
781 value = r8169_mdio_read(ioaddr, reg_addr);
782
783 r8168dp_2_mdio_stop(ioaddr);
784
785 return value;
786 }
787
788 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
789 {
790 tp->mdio_ops.write(tp->mmio_addr, location, val);
791 }
792
793 static int rtl_readphy(struct rtl8169_private *tp, int location)
794 {
795 return tp->mdio_ops.read(tp->mmio_addr, location);
796 }
797
798 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
799 {
800 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
801 }
802
803 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
804 {
805 int val;
806
807 val = rtl_readphy(tp, reg_addr);
808 rtl_writephy(tp, reg_addr, (val | p) & ~m);
809 }
810
811 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
812 int val)
813 {
814 struct rtl8169_private *tp = netdev_priv(dev);
815
816 rtl_writephy(tp, location, val);
817 }
818
819 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
820 {
821 struct rtl8169_private *tp = netdev_priv(dev);
822
823 return rtl_readphy(tp, location);
824 }
825
826 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
827 {
828 unsigned int i;
829
830 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
831 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
832
833 for (i = 0; i < 100; i++) {
834 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
835 break;
836 udelay(10);
837 }
838 }
839
840 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
841 {
842 u16 value = 0xffff;
843 unsigned int i;
844
845 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
846
847 for (i = 0; i < 100; i++) {
848 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
849 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
850 break;
851 }
852 udelay(10);
853 }
854
855 return value;
856 }
857
858 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
859 {
860 unsigned int i;
861
862 RTL_W32(CSIDR, value);
863 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
864 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
865
866 for (i = 0; i < 100; i++) {
867 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
868 break;
869 udelay(10);
870 }
871 }
872
873 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
874 {
875 u32 value = ~0x00;
876 unsigned int i;
877
878 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
879 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
880
881 for (i = 0; i < 100; i++) {
882 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
883 value = RTL_R32(CSIDR);
884 break;
885 }
886 udelay(10);
887 }
888
889 return value;
890 }
891
892 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
893 {
894 u8 value = 0xff;
895 unsigned int i;
896
897 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
898
899 for (i = 0; i < 300; i++) {
900 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
901 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
902 break;
903 }
904 udelay(100);
905 }
906
907 return value;
908 }
909
910 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
911 {
912 RTL_W16(IntrMask, 0x0000);
913
914 RTL_W16(IntrStatus, 0xffff);
915 }
916
917 static void rtl8169_asic_down(void __iomem *ioaddr)
918 {
919 RTL_W8(ChipCmd, 0x00);
920 rtl8169_irq_mask_and_ack(ioaddr);
921 RTL_R16(CPlusCmd);
922 }
923
924 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
925 {
926 void __iomem *ioaddr = tp->mmio_addr;
927
928 return RTL_R32(TBICSR) & TBIReset;
929 }
930
931 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
932 {
933 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
934 }
935
936 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
937 {
938 return RTL_R32(TBICSR) & TBILinkOk;
939 }
940
941 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
942 {
943 return RTL_R8(PHYstatus) & LinkStatus;
944 }
945
946 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
947 {
948 void __iomem *ioaddr = tp->mmio_addr;
949
950 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
951 }
952
953 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
954 {
955 unsigned int val;
956
957 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
958 rtl_writephy(tp, MII_BMCR, val & 0xffff);
959 }
960
961 static void __rtl8169_check_link_status(struct net_device *dev,
962 struct rtl8169_private *tp,
963 void __iomem *ioaddr,
964 bool pm)
965 {
966 unsigned long flags;
967
968 spin_lock_irqsave(&tp->lock, flags);
969 if (tp->link_ok(ioaddr)) {
970 /* This is to cancel a scheduled suspend if there's one. */
971 if (pm)
972 pm_request_resume(&tp->pci_dev->dev);
973 netif_carrier_on(dev);
974 netif_info(tp, ifup, dev, "link up\n");
975 } else {
976 netif_carrier_off(dev);
977 netif_info(tp, ifdown, dev, "link down\n");
978 if (pm)
979 pm_schedule_suspend(&tp->pci_dev->dev, 100);
980 }
981 spin_unlock_irqrestore(&tp->lock, flags);
982 }
983
984 static void rtl8169_check_link_status(struct net_device *dev,
985 struct rtl8169_private *tp,
986 void __iomem *ioaddr)
987 {
988 __rtl8169_check_link_status(dev, tp, ioaddr, false);
989 }
990
991 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
992
993 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
994 {
995 void __iomem *ioaddr = tp->mmio_addr;
996 u8 options;
997 u32 wolopts = 0;
998
999 options = RTL_R8(Config1);
1000 if (!(options & PMEnable))
1001 return 0;
1002
1003 options = RTL_R8(Config3);
1004 if (options & LinkUp)
1005 wolopts |= WAKE_PHY;
1006 if (options & MagicPacket)
1007 wolopts |= WAKE_MAGIC;
1008
1009 options = RTL_R8(Config5);
1010 if (options & UWF)
1011 wolopts |= WAKE_UCAST;
1012 if (options & BWF)
1013 wolopts |= WAKE_BCAST;
1014 if (options & MWF)
1015 wolopts |= WAKE_MCAST;
1016
1017 return wolopts;
1018 }
1019
1020 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1021 {
1022 struct rtl8169_private *tp = netdev_priv(dev);
1023
1024 spin_lock_irq(&tp->lock);
1025
1026 wol->supported = WAKE_ANY;
1027 wol->wolopts = __rtl8169_get_wol(tp);
1028
1029 spin_unlock_irq(&tp->lock);
1030 }
1031
1032 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1033 {
1034 void __iomem *ioaddr = tp->mmio_addr;
1035 unsigned int i;
1036 static const struct {
1037 u32 opt;
1038 u16 reg;
1039 u8 mask;
1040 } cfg[] = {
1041 { WAKE_ANY, Config1, PMEnable },
1042 { WAKE_PHY, Config3, LinkUp },
1043 { WAKE_MAGIC, Config3, MagicPacket },
1044 { WAKE_UCAST, Config5, UWF },
1045 { WAKE_BCAST, Config5, BWF },
1046 { WAKE_MCAST, Config5, MWF },
1047 { WAKE_ANY, Config5, LanWake }
1048 };
1049
1050 RTL_W8(Cfg9346, Cfg9346_Unlock);
1051
1052 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1053 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1054 if (wolopts & cfg[i].opt)
1055 options |= cfg[i].mask;
1056 RTL_W8(cfg[i].reg, options);
1057 }
1058
1059 RTL_W8(Cfg9346, Cfg9346_Lock);
1060 }
1061
1062 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1063 {
1064 struct rtl8169_private *tp = netdev_priv(dev);
1065
1066 spin_lock_irq(&tp->lock);
1067
1068 if (wol->wolopts)
1069 tp->features |= RTL_FEATURE_WOL;
1070 else
1071 tp->features &= ~RTL_FEATURE_WOL;
1072 __rtl8169_set_wol(tp, wol->wolopts);
1073 spin_unlock_irq(&tp->lock);
1074
1075 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1076
1077 return 0;
1078 }
1079
1080 static void rtl8169_get_drvinfo(struct net_device *dev,
1081 struct ethtool_drvinfo *info)
1082 {
1083 struct rtl8169_private *tp = netdev_priv(dev);
1084
1085 strcpy(info->driver, MODULENAME);
1086 strcpy(info->version, RTL8169_VERSION);
1087 strcpy(info->bus_info, pci_name(tp->pci_dev));
1088 }
1089
1090 static int rtl8169_get_regs_len(struct net_device *dev)
1091 {
1092 return R8169_REGS_SIZE;
1093 }
1094
1095 static int rtl8169_set_speed_tbi(struct net_device *dev,
1096 u8 autoneg, u16 speed, u8 duplex)
1097 {
1098 struct rtl8169_private *tp = netdev_priv(dev);
1099 void __iomem *ioaddr = tp->mmio_addr;
1100 int ret = 0;
1101 u32 reg;
1102
1103 reg = RTL_R32(TBICSR);
1104 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1105 (duplex == DUPLEX_FULL)) {
1106 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1107 } else if (autoneg == AUTONEG_ENABLE)
1108 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1109 else {
1110 netif_warn(tp, link, dev,
1111 "incorrect speed setting refused in TBI mode\n");
1112 ret = -EOPNOTSUPP;
1113 }
1114
1115 return ret;
1116 }
1117
1118 static int rtl8169_set_speed_xmii(struct net_device *dev,
1119 u8 autoneg, u16 speed, u8 duplex)
1120 {
1121 struct rtl8169_private *tp = netdev_priv(dev);
1122 int giga_ctrl, bmcr;
1123
1124 if (autoneg == AUTONEG_ENABLE) {
1125 int auto_nego;
1126
1127 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1128 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1129 ADVERTISE_100HALF | ADVERTISE_100FULL);
1130 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1131
1132 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1133 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1134
1135 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1136 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1137 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1138 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1139 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1140 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1141 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1142 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1143 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1144 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1145 } else {
1146 netif_info(tp, link, dev,
1147 "PHY does not support 1000Mbps\n");
1148 }
1149
1150 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1151
1152 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1153 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1154 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1155 /*
1156 * Wake up the PHY.
1157 * Vendor specific (0x1f) and reserved (0x0e) MII
1158 * registers.
1159 */
1160 rtl_writephy(tp, 0x1f, 0x0000);
1161 rtl_writephy(tp, 0x0e, 0x0000);
1162 }
1163
1164 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1165 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1166 } else {
1167 giga_ctrl = 0;
1168
1169 if (speed == SPEED_10)
1170 bmcr = 0;
1171 else if (speed == SPEED_100)
1172 bmcr = BMCR_SPEED100;
1173 else
1174 return -EINVAL;
1175
1176 if (duplex == DUPLEX_FULL)
1177 bmcr |= BMCR_FULLDPLX;
1178
1179 rtl_writephy(tp, 0x1f, 0x0000);
1180 }
1181
1182 tp->phy_1000_ctrl_reg = giga_ctrl;
1183
1184 rtl_writephy(tp, MII_BMCR, bmcr);
1185
1186 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1187 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1188 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1189 rtl_writephy(tp, 0x17, 0x2138);
1190 rtl_writephy(tp, 0x0e, 0x0260);
1191 } else {
1192 rtl_writephy(tp, 0x17, 0x2108);
1193 rtl_writephy(tp, 0x0e, 0x0000);
1194 }
1195 }
1196
1197 return 0;
1198 }
1199
1200 static int rtl8169_set_speed(struct net_device *dev,
1201 u8 autoneg, u16 speed, u8 duplex)
1202 {
1203 struct rtl8169_private *tp = netdev_priv(dev);
1204 int ret;
1205
1206 ret = tp->set_speed(dev, autoneg, speed, duplex);
1207
1208 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1209 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1210
1211 return ret;
1212 }
1213
1214 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1215 {
1216 struct rtl8169_private *tp = netdev_priv(dev);
1217 unsigned long flags;
1218 int ret;
1219
1220 spin_lock_irqsave(&tp->lock, flags);
1221 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1222 spin_unlock_irqrestore(&tp->lock, flags);
1223
1224 return ret;
1225 }
1226
1227 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1228 {
1229 struct rtl8169_private *tp = netdev_priv(dev);
1230
1231 return tp->cp_cmd & RxChkSum;
1232 }
1233
1234 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1235 {
1236 struct rtl8169_private *tp = netdev_priv(dev);
1237 void __iomem *ioaddr = tp->mmio_addr;
1238 unsigned long flags;
1239
1240 spin_lock_irqsave(&tp->lock, flags);
1241
1242 if (data)
1243 tp->cp_cmd |= RxChkSum;
1244 else
1245 tp->cp_cmd &= ~RxChkSum;
1246
1247 RTL_W16(CPlusCmd, tp->cp_cmd);
1248 RTL_R16(CPlusCmd);
1249
1250 spin_unlock_irqrestore(&tp->lock, flags);
1251
1252 return 0;
1253 }
1254
1255 #ifdef CONFIG_R8169_VLAN
1256
1257 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1258 struct sk_buff *skb)
1259 {
1260 return (vlan_tx_tag_present(skb)) ?
1261 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1262 }
1263
1264 static void rtl8169_vlan_rx_register(struct net_device *dev,
1265 struct vlan_group *grp)
1266 {
1267 struct rtl8169_private *tp = netdev_priv(dev);
1268 void __iomem *ioaddr = tp->mmio_addr;
1269 unsigned long flags;
1270
1271 spin_lock_irqsave(&tp->lock, flags);
1272 tp->vlgrp = grp;
1273 /*
1274 * Do not disable RxVlan on 8110SCd.
1275 */
1276 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1277 tp->cp_cmd |= RxVlan;
1278 else
1279 tp->cp_cmd &= ~RxVlan;
1280 RTL_W16(CPlusCmd, tp->cp_cmd);
1281 RTL_R16(CPlusCmd);
1282 spin_unlock_irqrestore(&tp->lock, flags);
1283 }
1284
1285 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1286 struct sk_buff *skb, int polling)
1287 {
1288 u32 opts2 = le32_to_cpu(desc->opts2);
1289 struct vlan_group *vlgrp = tp->vlgrp;
1290 int ret;
1291
1292 if (vlgrp && (opts2 & RxVlanTag)) {
1293 u16 vtag = swab16(opts2 & 0xffff);
1294
1295 if (likely(polling))
1296 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1297 else
1298 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1299 ret = 0;
1300 } else
1301 ret = -1;
1302 desc->opts2 = 0;
1303 return ret;
1304 }
1305
1306 #else /* !CONFIG_R8169_VLAN */
1307
1308 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1309 struct sk_buff *skb)
1310 {
1311 return 0;
1312 }
1313
1314 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1315 struct sk_buff *skb, int polling)
1316 {
1317 return -1;
1318 }
1319
1320 #endif
1321
1322 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1323 {
1324 struct rtl8169_private *tp = netdev_priv(dev);
1325 void __iomem *ioaddr = tp->mmio_addr;
1326 u32 status;
1327
1328 cmd->supported =
1329 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1330 cmd->port = PORT_FIBRE;
1331 cmd->transceiver = XCVR_INTERNAL;
1332
1333 status = RTL_R32(TBICSR);
1334 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1335 cmd->autoneg = !!(status & TBINwEnable);
1336
1337 cmd->speed = SPEED_1000;
1338 cmd->duplex = DUPLEX_FULL; /* Always set */
1339
1340 return 0;
1341 }
1342
1343 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1344 {
1345 struct rtl8169_private *tp = netdev_priv(dev);
1346
1347 return mii_ethtool_gset(&tp->mii, cmd);
1348 }
1349
1350 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1351 {
1352 struct rtl8169_private *tp = netdev_priv(dev);
1353 unsigned long flags;
1354 int rc;
1355
1356 spin_lock_irqsave(&tp->lock, flags);
1357
1358 rc = tp->get_settings(dev, cmd);
1359
1360 spin_unlock_irqrestore(&tp->lock, flags);
1361 return rc;
1362 }
1363
1364 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1365 void *p)
1366 {
1367 struct rtl8169_private *tp = netdev_priv(dev);
1368 unsigned long flags;
1369
1370 if (regs->len > R8169_REGS_SIZE)
1371 regs->len = R8169_REGS_SIZE;
1372
1373 spin_lock_irqsave(&tp->lock, flags);
1374 memcpy_fromio(p, tp->mmio_addr, regs->len);
1375 spin_unlock_irqrestore(&tp->lock, flags);
1376 }
1377
1378 static u32 rtl8169_get_msglevel(struct net_device *dev)
1379 {
1380 struct rtl8169_private *tp = netdev_priv(dev);
1381
1382 return tp->msg_enable;
1383 }
1384
1385 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1386 {
1387 struct rtl8169_private *tp = netdev_priv(dev);
1388
1389 tp->msg_enable = value;
1390 }
1391
1392 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1393 "tx_packets",
1394 "rx_packets",
1395 "tx_errors",
1396 "rx_errors",
1397 "rx_missed",
1398 "align_errors",
1399 "tx_single_collisions",
1400 "tx_multi_collisions",
1401 "unicast",
1402 "broadcast",
1403 "multicast",
1404 "tx_aborted",
1405 "tx_underrun",
1406 };
1407
1408 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1409 {
1410 switch (sset) {
1411 case ETH_SS_STATS:
1412 return ARRAY_SIZE(rtl8169_gstrings);
1413 default:
1414 return -EOPNOTSUPP;
1415 }
1416 }
1417
1418 static void rtl8169_update_counters(struct net_device *dev)
1419 {
1420 struct rtl8169_private *tp = netdev_priv(dev);
1421 void __iomem *ioaddr = tp->mmio_addr;
1422 struct rtl8169_counters *counters;
1423 dma_addr_t paddr;
1424 u32 cmd;
1425 int wait = 1000;
1426 struct device *d = &tp->pci_dev->dev;
1427
1428 /*
1429 * Some chips are unable to dump tally counters when the receiver
1430 * is disabled.
1431 */
1432 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1433 return;
1434
1435 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1436 if (!counters)
1437 return;
1438
1439 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1440 cmd = (u64)paddr & DMA_BIT_MASK(32);
1441 RTL_W32(CounterAddrLow, cmd);
1442 RTL_W32(CounterAddrLow, cmd | CounterDump);
1443
1444 while (wait--) {
1445 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1446 /* copy updated counters */
1447 memcpy(&tp->counters, counters, sizeof(*counters));
1448 break;
1449 }
1450 udelay(10);
1451 }
1452
1453 RTL_W32(CounterAddrLow, 0);
1454 RTL_W32(CounterAddrHigh, 0);
1455
1456 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1457 }
1458
1459 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1460 struct ethtool_stats *stats, u64 *data)
1461 {
1462 struct rtl8169_private *tp = netdev_priv(dev);
1463
1464 ASSERT_RTNL();
1465
1466 rtl8169_update_counters(dev);
1467
1468 data[0] = le64_to_cpu(tp->counters.tx_packets);
1469 data[1] = le64_to_cpu(tp->counters.rx_packets);
1470 data[2] = le64_to_cpu(tp->counters.tx_errors);
1471 data[3] = le32_to_cpu(tp->counters.rx_errors);
1472 data[4] = le16_to_cpu(tp->counters.rx_missed);
1473 data[5] = le16_to_cpu(tp->counters.align_errors);
1474 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1475 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1476 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1477 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1478 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1479 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1480 data[12] = le16_to_cpu(tp->counters.tx_underun);
1481 }
1482
1483 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1484 {
1485 switch(stringset) {
1486 case ETH_SS_STATS:
1487 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1488 break;
1489 }
1490 }
1491
1492 static const struct ethtool_ops rtl8169_ethtool_ops = {
1493 .get_drvinfo = rtl8169_get_drvinfo,
1494 .get_regs_len = rtl8169_get_regs_len,
1495 .get_link = ethtool_op_get_link,
1496 .get_settings = rtl8169_get_settings,
1497 .set_settings = rtl8169_set_settings,
1498 .get_msglevel = rtl8169_get_msglevel,
1499 .set_msglevel = rtl8169_set_msglevel,
1500 .get_rx_csum = rtl8169_get_rx_csum,
1501 .set_rx_csum = rtl8169_set_rx_csum,
1502 .set_tx_csum = ethtool_op_set_tx_csum,
1503 .set_sg = ethtool_op_set_sg,
1504 .set_tso = ethtool_op_set_tso,
1505 .get_regs = rtl8169_get_regs,
1506 .get_wol = rtl8169_get_wol,
1507 .set_wol = rtl8169_set_wol,
1508 .get_strings = rtl8169_get_strings,
1509 .get_sset_count = rtl8169_get_sset_count,
1510 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1511 };
1512
1513 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1514 void __iomem *ioaddr)
1515 {
1516 /*
1517 * The driver currently handles the 8168Bf and the 8168Be identically
1518 * but they can be identified more specifically through the test below
1519 * if needed:
1520 *
1521 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1522 *
1523 * Same thing for the 8101Eb and the 8101Ec:
1524 *
1525 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1526 */
1527 static const struct {
1528 u32 mask;
1529 u32 val;
1530 int mac_version;
1531 } mac_info[] = {
1532 /* 8168D family. */
1533 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1534 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1535 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1536
1537 /* 8168DP family. */
1538 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1539 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1540
1541 /* 8168C family. */
1542 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1543 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1544 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1545 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1546 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1547 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1548 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1549 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1550 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1551
1552 /* 8168B family. */
1553 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1554 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1555 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1556 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1557
1558 /* 8101 family. */
1559 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1560 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1561 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1562 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1563 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1564 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1565 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1566 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1567 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1568 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1569 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1570 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1571 /* FIXME: where did these entries come from ? -- FR */
1572 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1573 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1574
1575 /* 8110 family. */
1576 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1577 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1578 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1579 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1580 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1581 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1582
1583 /* Catch-all */
1584 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1585 }, *p = mac_info;
1586 u32 reg;
1587
1588 reg = RTL_R32(TxConfig);
1589 while ((reg & p->mask) != p->val)
1590 p++;
1591 tp->mac_version = p->mac_version;
1592 }
1593
1594 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1595 {
1596 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1597 }
1598
1599 struct phy_reg {
1600 u16 reg;
1601 u16 val;
1602 };
1603
1604 static void rtl_writephy_batch(struct rtl8169_private *tp,
1605 const struct phy_reg *regs, int len)
1606 {
1607 while (len-- > 0) {
1608 rtl_writephy(tp, regs->reg, regs->val);
1609 regs++;
1610 }
1611 }
1612
1613 #define PHY_READ 0x00000000
1614 #define PHY_DATA_OR 0x10000000
1615 #define PHY_DATA_AND 0x20000000
1616 #define PHY_BJMPN 0x30000000
1617 #define PHY_READ_EFUSE 0x40000000
1618 #define PHY_READ_MAC_BYTE 0x50000000
1619 #define PHY_WRITE_MAC_BYTE 0x60000000
1620 #define PHY_CLEAR_READCOUNT 0x70000000
1621 #define PHY_WRITE 0x80000000
1622 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1623 #define PHY_COMP_EQ_SKIPN 0xa0000000
1624 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1625 #define PHY_WRITE_PREVIOUS 0xc0000000
1626 #define PHY_SKIPN 0xd0000000
1627 #define PHY_DELAY_MS 0xe0000000
1628 #define PHY_WRITE_ERI_WORD 0xf0000000
1629
1630 static void
1631 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1632 {
1633 __le32 *phytable = (__le32 *)fw->data;
1634 struct net_device *dev = tp->dev;
1635 size_t i;
1636
1637 if (fw->size % sizeof(*phytable)) {
1638 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1639 return;
1640 }
1641
1642 for (i = 0; i < fw->size / sizeof(*phytable); i++) {
1643 u32 action = le32_to_cpu(phytable[i]);
1644
1645 if (!action)
1646 break;
1647
1648 if ((action & 0xf0000000) != PHY_WRITE) {
1649 netif_err(tp, probe, dev,
1650 "unknown action 0x%08x\n", action);
1651 return;
1652 }
1653 }
1654
1655 while (i-- != 0) {
1656 u32 action = le32_to_cpu(*phytable);
1657 u32 data = action & 0x0000ffff;
1658 u32 reg = (action & 0x0fff0000) >> 16;
1659
1660 switch(action & 0xf0000000) {
1661 case PHY_WRITE:
1662 rtl_writephy(tp, reg, data);
1663 phytable++;
1664 break;
1665 default:
1666 BUG();
1667 }
1668 }
1669 }
1670
1671 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1672 {
1673 static const struct phy_reg phy_reg_init[] = {
1674 { 0x1f, 0x0001 },
1675 { 0x06, 0x006e },
1676 { 0x08, 0x0708 },
1677 { 0x15, 0x4000 },
1678 { 0x18, 0x65c7 },
1679
1680 { 0x1f, 0x0001 },
1681 { 0x03, 0x00a1 },
1682 { 0x02, 0x0008 },
1683 { 0x01, 0x0120 },
1684 { 0x00, 0x1000 },
1685 { 0x04, 0x0800 },
1686 { 0x04, 0x0000 },
1687
1688 { 0x03, 0xff41 },
1689 { 0x02, 0xdf60 },
1690 { 0x01, 0x0140 },
1691 { 0x00, 0x0077 },
1692 { 0x04, 0x7800 },
1693 { 0x04, 0x7000 },
1694
1695 { 0x03, 0x802f },
1696 { 0x02, 0x4f02 },
1697 { 0x01, 0x0409 },
1698 { 0x00, 0xf0f9 },
1699 { 0x04, 0x9800 },
1700 { 0x04, 0x9000 },
1701
1702 { 0x03, 0xdf01 },
1703 { 0x02, 0xdf20 },
1704 { 0x01, 0xff95 },
1705 { 0x00, 0xba00 },
1706 { 0x04, 0xa800 },
1707 { 0x04, 0xa000 },
1708
1709 { 0x03, 0xff41 },
1710 { 0x02, 0xdf20 },
1711 { 0x01, 0x0140 },
1712 { 0x00, 0x00bb },
1713 { 0x04, 0xb800 },
1714 { 0x04, 0xb000 },
1715
1716 { 0x03, 0xdf41 },
1717 { 0x02, 0xdc60 },
1718 { 0x01, 0x6340 },
1719 { 0x00, 0x007d },
1720 { 0x04, 0xd800 },
1721 { 0x04, 0xd000 },
1722
1723 { 0x03, 0xdf01 },
1724 { 0x02, 0xdf20 },
1725 { 0x01, 0x100a },
1726 { 0x00, 0xa0ff },
1727 { 0x04, 0xf800 },
1728 { 0x04, 0xf000 },
1729
1730 { 0x1f, 0x0000 },
1731 { 0x0b, 0x0000 },
1732 { 0x00, 0x9200 }
1733 };
1734
1735 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1736 }
1737
1738 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1739 {
1740 static const struct phy_reg phy_reg_init[] = {
1741 { 0x1f, 0x0002 },
1742 { 0x01, 0x90d0 },
1743 { 0x1f, 0x0000 }
1744 };
1745
1746 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1747 }
1748
1749 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1750 {
1751 struct pci_dev *pdev = tp->pci_dev;
1752 u16 vendor_id, device_id;
1753
1754 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1755 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1756
1757 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1758 return;
1759
1760 rtl_writephy(tp, 0x1f, 0x0001);
1761 rtl_writephy(tp, 0x10, 0xf01b);
1762 rtl_writephy(tp, 0x1f, 0x0000);
1763 }
1764
1765 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1766 {
1767 static const struct phy_reg phy_reg_init[] = {
1768 { 0x1f, 0x0001 },
1769 { 0x04, 0x0000 },
1770 { 0x03, 0x00a1 },
1771 { 0x02, 0x0008 },
1772 { 0x01, 0x0120 },
1773 { 0x00, 0x1000 },
1774 { 0x04, 0x0800 },
1775 { 0x04, 0x9000 },
1776 { 0x03, 0x802f },
1777 { 0x02, 0x4f02 },
1778 { 0x01, 0x0409 },
1779 { 0x00, 0xf099 },
1780 { 0x04, 0x9800 },
1781 { 0x04, 0xa000 },
1782 { 0x03, 0xdf01 },
1783 { 0x02, 0xdf20 },
1784 { 0x01, 0xff95 },
1785 { 0x00, 0xba00 },
1786 { 0x04, 0xa800 },
1787 { 0x04, 0xf000 },
1788 { 0x03, 0xdf01 },
1789 { 0x02, 0xdf20 },
1790 { 0x01, 0x101a },
1791 { 0x00, 0xa0ff },
1792 { 0x04, 0xf800 },
1793 { 0x04, 0x0000 },
1794 { 0x1f, 0x0000 },
1795
1796 { 0x1f, 0x0001 },
1797 { 0x10, 0xf41b },
1798 { 0x14, 0xfb54 },
1799 { 0x18, 0xf5c7 },
1800 { 0x1f, 0x0000 },
1801
1802 { 0x1f, 0x0001 },
1803 { 0x17, 0x0cc0 },
1804 { 0x1f, 0x0000 }
1805 };
1806
1807 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1808
1809 rtl8169scd_hw_phy_config_quirk(tp);
1810 }
1811
1812 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1813 {
1814 static const struct phy_reg phy_reg_init[] = {
1815 { 0x1f, 0x0001 },
1816 { 0x04, 0x0000 },
1817 { 0x03, 0x00a1 },
1818 { 0x02, 0x0008 },
1819 { 0x01, 0x0120 },
1820 { 0x00, 0x1000 },
1821 { 0x04, 0x0800 },
1822 { 0x04, 0x9000 },
1823 { 0x03, 0x802f },
1824 { 0x02, 0x4f02 },
1825 { 0x01, 0x0409 },
1826 { 0x00, 0xf099 },
1827 { 0x04, 0x9800 },
1828 { 0x04, 0xa000 },
1829 { 0x03, 0xdf01 },
1830 { 0x02, 0xdf20 },
1831 { 0x01, 0xff95 },
1832 { 0x00, 0xba00 },
1833 { 0x04, 0xa800 },
1834 { 0x04, 0xf000 },
1835 { 0x03, 0xdf01 },
1836 { 0x02, 0xdf20 },
1837 { 0x01, 0x101a },
1838 { 0x00, 0xa0ff },
1839 { 0x04, 0xf800 },
1840 { 0x04, 0x0000 },
1841 { 0x1f, 0x0000 },
1842
1843 { 0x1f, 0x0001 },
1844 { 0x0b, 0x8480 },
1845 { 0x1f, 0x0000 },
1846
1847 { 0x1f, 0x0001 },
1848 { 0x18, 0x67c7 },
1849 { 0x04, 0x2000 },
1850 { 0x03, 0x002f },
1851 { 0x02, 0x4360 },
1852 { 0x01, 0x0109 },
1853 { 0x00, 0x3022 },
1854 { 0x04, 0x2800 },
1855 { 0x1f, 0x0000 },
1856
1857 { 0x1f, 0x0001 },
1858 { 0x17, 0x0cc0 },
1859 { 0x1f, 0x0000 }
1860 };
1861
1862 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1863 }
1864
1865 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1866 {
1867 static const struct phy_reg phy_reg_init[] = {
1868 { 0x10, 0xf41b },
1869 { 0x1f, 0x0000 }
1870 };
1871
1872 rtl_writephy(tp, 0x1f, 0x0001);
1873 rtl_patchphy(tp, 0x16, 1 << 0);
1874
1875 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1876 }
1877
1878 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
1879 {
1880 static const struct phy_reg phy_reg_init[] = {
1881 { 0x1f, 0x0001 },
1882 { 0x10, 0xf41b },
1883 { 0x1f, 0x0000 }
1884 };
1885
1886 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1887 }
1888
1889 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
1890 {
1891 static const struct phy_reg phy_reg_init[] = {
1892 { 0x1f, 0x0000 },
1893 { 0x1d, 0x0f00 },
1894 { 0x1f, 0x0002 },
1895 { 0x0c, 0x1ec8 },
1896 { 0x1f, 0x0000 }
1897 };
1898
1899 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1900 }
1901
1902 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
1903 {
1904 static const struct phy_reg phy_reg_init[] = {
1905 { 0x1f, 0x0001 },
1906 { 0x1d, 0x3d98 },
1907 { 0x1f, 0x0000 }
1908 };
1909
1910 rtl_writephy(tp, 0x1f, 0x0000);
1911 rtl_patchphy(tp, 0x14, 1 << 5);
1912 rtl_patchphy(tp, 0x0d, 1 << 5);
1913
1914 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1915 }
1916
1917 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
1918 {
1919 static const struct phy_reg phy_reg_init[] = {
1920 { 0x1f, 0x0001 },
1921 { 0x12, 0x2300 },
1922 { 0x1f, 0x0002 },
1923 { 0x00, 0x88d4 },
1924 { 0x01, 0x82b1 },
1925 { 0x03, 0x7002 },
1926 { 0x08, 0x9e30 },
1927 { 0x09, 0x01f0 },
1928 { 0x0a, 0x5500 },
1929 { 0x0c, 0x00c8 },
1930 { 0x1f, 0x0003 },
1931 { 0x12, 0xc096 },
1932 { 0x16, 0x000a },
1933 { 0x1f, 0x0000 },
1934 { 0x1f, 0x0000 },
1935 { 0x09, 0x2000 },
1936 { 0x09, 0x0000 }
1937 };
1938
1939 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1940
1941 rtl_patchphy(tp, 0x14, 1 << 5);
1942 rtl_patchphy(tp, 0x0d, 1 << 5);
1943 rtl_writephy(tp, 0x1f, 0x0000);
1944 }
1945
1946 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
1947 {
1948 static const struct phy_reg phy_reg_init[] = {
1949 { 0x1f, 0x0001 },
1950 { 0x12, 0x2300 },
1951 { 0x03, 0x802f },
1952 { 0x02, 0x4f02 },
1953 { 0x01, 0x0409 },
1954 { 0x00, 0xf099 },
1955 { 0x04, 0x9800 },
1956 { 0x04, 0x9000 },
1957 { 0x1d, 0x3d98 },
1958 { 0x1f, 0x0002 },
1959 { 0x0c, 0x7eb8 },
1960 { 0x06, 0x0761 },
1961 { 0x1f, 0x0003 },
1962 { 0x16, 0x0f0a },
1963 { 0x1f, 0x0000 }
1964 };
1965
1966 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1967
1968 rtl_patchphy(tp, 0x16, 1 << 0);
1969 rtl_patchphy(tp, 0x14, 1 << 5);
1970 rtl_patchphy(tp, 0x0d, 1 << 5);
1971 rtl_writephy(tp, 0x1f, 0x0000);
1972 }
1973
1974 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
1975 {
1976 static const struct phy_reg phy_reg_init[] = {
1977 { 0x1f, 0x0001 },
1978 { 0x12, 0x2300 },
1979 { 0x1d, 0x3d98 },
1980 { 0x1f, 0x0002 },
1981 { 0x0c, 0x7eb8 },
1982 { 0x06, 0x5461 },
1983 { 0x1f, 0x0003 },
1984 { 0x16, 0x0f0a },
1985 { 0x1f, 0x0000 }
1986 };
1987
1988 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1989
1990 rtl_patchphy(tp, 0x16, 1 << 0);
1991 rtl_patchphy(tp, 0x14, 1 << 5);
1992 rtl_patchphy(tp, 0x0d, 1 << 5);
1993 rtl_writephy(tp, 0x1f, 0x0000);
1994 }
1995
1996 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
1997 {
1998 rtl8168c_3_hw_phy_config(tp);
1999 }
2000
2001 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2002 {
2003 static const struct phy_reg phy_reg_init_0[] = {
2004 /* Channel Estimation */
2005 { 0x1f, 0x0001 },
2006 { 0x06, 0x4064 },
2007 { 0x07, 0x2863 },
2008 { 0x08, 0x059c },
2009 { 0x09, 0x26b4 },
2010 { 0x0a, 0x6a19 },
2011 { 0x0b, 0xdcc8 },
2012 { 0x10, 0xf06d },
2013 { 0x14, 0x7f68 },
2014 { 0x18, 0x7fd9 },
2015 { 0x1c, 0xf0ff },
2016 { 0x1d, 0x3d9c },
2017 { 0x1f, 0x0003 },
2018 { 0x12, 0xf49f },
2019 { 0x13, 0x070b },
2020 { 0x1a, 0x05ad },
2021 { 0x14, 0x94c0 },
2022
2023 /*
2024 * Tx Error Issue
2025 * enhance line driver power
2026 */
2027 { 0x1f, 0x0002 },
2028 { 0x06, 0x5561 },
2029 { 0x1f, 0x0005 },
2030 { 0x05, 0x8332 },
2031 { 0x06, 0x5561 },
2032
2033 /*
2034 * Can not link to 1Gbps with bad cable
2035 * Decrease SNR threshold form 21.07dB to 19.04dB
2036 */
2037 { 0x1f, 0x0001 },
2038 { 0x17, 0x0cc0 },
2039
2040 { 0x1f, 0x0000 },
2041 { 0x0d, 0xf880 }
2042 };
2043 void __iomem *ioaddr = tp->mmio_addr;
2044 const struct firmware *fw;
2045
2046 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2047
2048 /*
2049 * Rx Error Issue
2050 * Fine Tune Switching regulator parameter
2051 */
2052 rtl_writephy(tp, 0x1f, 0x0002);
2053 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2054 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2055
2056 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2057 static const struct phy_reg phy_reg_init[] = {
2058 { 0x1f, 0x0002 },
2059 { 0x05, 0x669a },
2060 { 0x1f, 0x0005 },
2061 { 0x05, 0x8330 },
2062 { 0x06, 0x669a },
2063 { 0x1f, 0x0002 }
2064 };
2065 int val;
2066
2067 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2068
2069 val = rtl_readphy(tp, 0x0d);
2070
2071 if ((val & 0x00ff) != 0x006c) {
2072 static const u32 set[] = {
2073 0x0065, 0x0066, 0x0067, 0x0068,
2074 0x0069, 0x006a, 0x006b, 0x006c
2075 };
2076 int i;
2077
2078 rtl_writephy(tp, 0x1f, 0x0002);
2079
2080 val &= 0xff00;
2081 for (i = 0; i < ARRAY_SIZE(set); i++)
2082 rtl_writephy(tp, 0x0d, val | set[i]);
2083 }
2084 } else {
2085 static const struct phy_reg phy_reg_init[] = {
2086 { 0x1f, 0x0002 },
2087 { 0x05, 0x6662 },
2088 { 0x1f, 0x0005 },
2089 { 0x05, 0x8330 },
2090 { 0x06, 0x6662 }
2091 };
2092
2093 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2094 }
2095
2096 /* RSET couple improve */
2097 rtl_writephy(tp, 0x1f, 0x0002);
2098 rtl_patchphy(tp, 0x0d, 0x0300);
2099 rtl_patchphy(tp, 0x0f, 0x0010);
2100
2101 /* Fine tune PLL performance */
2102 rtl_writephy(tp, 0x1f, 0x0002);
2103 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2104 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2105
2106 rtl_writephy(tp, 0x1f, 0x0005);
2107 rtl_writephy(tp, 0x05, 0x001b);
2108 if (rtl_readphy(tp, 0x06) == 0xbf00 &&
2109 request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
2110 rtl_phy_write_fw(tp, fw);
2111 release_firmware(fw);
2112 } else {
2113 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2114 }
2115
2116 rtl_writephy(tp, 0x1f, 0x0000);
2117 }
2118
2119 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2120 {
2121 static const struct phy_reg phy_reg_init_0[] = {
2122 /* Channel Estimation */
2123 { 0x1f, 0x0001 },
2124 { 0x06, 0x4064 },
2125 { 0x07, 0x2863 },
2126 { 0x08, 0x059c },
2127 { 0x09, 0x26b4 },
2128 { 0x0a, 0x6a19 },
2129 { 0x0b, 0xdcc8 },
2130 { 0x10, 0xf06d },
2131 { 0x14, 0x7f68 },
2132 { 0x18, 0x7fd9 },
2133 { 0x1c, 0xf0ff },
2134 { 0x1d, 0x3d9c },
2135 { 0x1f, 0x0003 },
2136 { 0x12, 0xf49f },
2137 { 0x13, 0x070b },
2138 { 0x1a, 0x05ad },
2139 { 0x14, 0x94c0 },
2140
2141 /*
2142 * Tx Error Issue
2143 * enhance line driver power
2144 */
2145 { 0x1f, 0x0002 },
2146 { 0x06, 0x5561 },
2147 { 0x1f, 0x0005 },
2148 { 0x05, 0x8332 },
2149 { 0x06, 0x5561 },
2150
2151 /*
2152 * Can not link to 1Gbps with bad cable
2153 * Decrease SNR threshold form 21.07dB to 19.04dB
2154 */
2155 { 0x1f, 0x0001 },
2156 { 0x17, 0x0cc0 },
2157
2158 { 0x1f, 0x0000 },
2159 { 0x0d, 0xf880 }
2160 };
2161 void __iomem *ioaddr = tp->mmio_addr;
2162 const struct firmware *fw;
2163
2164 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2165
2166 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2167 static const struct phy_reg phy_reg_init[] = {
2168 { 0x1f, 0x0002 },
2169 { 0x05, 0x669a },
2170 { 0x1f, 0x0005 },
2171 { 0x05, 0x8330 },
2172 { 0x06, 0x669a },
2173
2174 { 0x1f, 0x0002 }
2175 };
2176 int val;
2177
2178 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2179
2180 val = rtl_readphy(tp, 0x0d);
2181 if ((val & 0x00ff) != 0x006c) {
2182 static const u32 set[] = {
2183 0x0065, 0x0066, 0x0067, 0x0068,
2184 0x0069, 0x006a, 0x006b, 0x006c
2185 };
2186 int i;
2187
2188 rtl_writephy(tp, 0x1f, 0x0002);
2189
2190 val &= 0xff00;
2191 for (i = 0; i < ARRAY_SIZE(set); i++)
2192 rtl_writephy(tp, 0x0d, val | set[i]);
2193 }
2194 } else {
2195 static const struct phy_reg phy_reg_init[] = {
2196 { 0x1f, 0x0002 },
2197 { 0x05, 0x2642 },
2198 { 0x1f, 0x0005 },
2199 { 0x05, 0x8330 },
2200 { 0x06, 0x2642 }
2201 };
2202
2203 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2204 }
2205
2206 /* Fine tune PLL performance */
2207 rtl_writephy(tp, 0x1f, 0x0002);
2208 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2209 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2210
2211 /* Switching regulator Slew rate */
2212 rtl_writephy(tp, 0x1f, 0x0002);
2213 rtl_patchphy(tp, 0x0f, 0x0017);
2214
2215 rtl_writephy(tp, 0x1f, 0x0005);
2216 rtl_writephy(tp, 0x05, 0x001b);
2217 if (rtl_readphy(tp, 0x06) == 0xb300 &&
2218 request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2219 rtl_phy_write_fw(tp, fw);
2220 release_firmware(fw);
2221 } else {
2222 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2223 }
2224
2225 rtl_writephy(tp, 0x1f, 0x0000);
2226 }
2227
2228 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2229 {
2230 static const struct phy_reg phy_reg_init[] = {
2231 { 0x1f, 0x0002 },
2232 { 0x10, 0x0008 },
2233 { 0x0d, 0x006c },
2234
2235 { 0x1f, 0x0000 },
2236 { 0x0d, 0xf880 },
2237
2238 { 0x1f, 0x0001 },
2239 { 0x17, 0x0cc0 },
2240
2241 { 0x1f, 0x0001 },
2242 { 0x0b, 0xa4d8 },
2243 { 0x09, 0x281c },
2244 { 0x07, 0x2883 },
2245 { 0x0a, 0x6b35 },
2246 { 0x1d, 0x3da4 },
2247 { 0x1c, 0xeffd },
2248 { 0x14, 0x7f52 },
2249 { 0x18, 0x7fc6 },
2250 { 0x08, 0x0601 },
2251 { 0x06, 0x4063 },
2252 { 0x10, 0xf074 },
2253 { 0x1f, 0x0003 },
2254 { 0x13, 0x0789 },
2255 { 0x12, 0xf4bd },
2256 { 0x1a, 0x04fd },
2257 { 0x14, 0x84b0 },
2258 { 0x1f, 0x0000 },
2259 { 0x00, 0x9200 },
2260
2261 { 0x1f, 0x0005 },
2262 { 0x01, 0x0340 },
2263 { 0x1f, 0x0001 },
2264 { 0x04, 0x4000 },
2265 { 0x03, 0x1d21 },
2266 { 0x02, 0x0c32 },
2267 { 0x01, 0x0200 },
2268 { 0x00, 0x5554 },
2269 { 0x04, 0x4800 },
2270 { 0x04, 0x4000 },
2271 { 0x04, 0xf000 },
2272 { 0x03, 0xdf01 },
2273 { 0x02, 0xdf20 },
2274 { 0x01, 0x101a },
2275 { 0x00, 0xa0ff },
2276 { 0x04, 0xf800 },
2277 { 0x04, 0xf000 },
2278 { 0x1f, 0x0000 },
2279
2280 { 0x1f, 0x0007 },
2281 { 0x1e, 0x0023 },
2282 { 0x16, 0x0000 },
2283 { 0x1f, 0x0000 }
2284 };
2285
2286 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2287 }
2288
2289 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2290 {
2291 static const struct phy_reg phy_reg_init[] = {
2292 { 0x1f, 0x0001 },
2293 { 0x17, 0x0cc0 },
2294
2295 { 0x1f, 0x0007 },
2296 { 0x1e, 0x002d },
2297 { 0x18, 0x0040 },
2298 { 0x1f, 0x0000 }
2299 };
2300
2301 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2302 rtl_patchphy(tp, 0x0d, 1 << 5);
2303 }
2304
2305 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2306 {
2307 static const struct phy_reg phy_reg_init[] = {
2308 { 0x1f, 0x0003 },
2309 { 0x08, 0x441d },
2310 { 0x01, 0x9100 },
2311 { 0x1f, 0x0000 }
2312 };
2313
2314 rtl_writephy(tp, 0x1f, 0x0000);
2315 rtl_patchphy(tp, 0x11, 1 << 12);
2316 rtl_patchphy(tp, 0x19, 1 << 13);
2317 rtl_patchphy(tp, 0x10, 1 << 15);
2318
2319 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2320 }
2321
2322 static void rtl_hw_phy_config(struct net_device *dev)
2323 {
2324 struct rtl8169_private *tp = netdev_priv(dev);
2325
2326 rtl8169_print_mac_version(tp);
2327
2328 switch (tp->mac_version) {
2329 case RTL_GIGA_MAC_VER_01:
2330 break;
2331 case RTL_GIGA_MAC_VER_02:
2332 case RTL_GIGA_MAC_VER_03:
2333 rtl8169s_hw_phy_config(tp);
2334 break;
2335 case RTL_GIGA_MAC_VER_04:
2336 rtl8169sb_hw_phy_config(tp);
2337 break;
2338 case RTL_GIGA_MAC_VER_05:
2339 rtl8169scd_hw_phy_config(tp);
2340 break;
2341 case RTL_GIGA_MAC_VER_06:
2342 rtl8169sce_hw_phy_config(tp);
2343 break;
2344 case RTL_GIGA_MAC_VER_07:
2345 case RTL_GIGA_MAC_VER_08:
2346 case RTL_GIGA_MAC_VER_09:
2347 rtl8102e_hw_phy_config(tp);
2348 break;
2349 case RTL_GIGA_MAC_VER_11:
2350 rtl8168bb_hw_phy_config(tp);
2351 break;
2352 case RTL_GIGA_MAC_VER_12:
2353 rtl8168bef_hw_phy_config(tp);
2354 break;
2355 case RTL_GIGA_MAC_VER_17:
2356 rtl8168bef_hw_phy_config(tp);
2357 break;
2358 case RTL_GIGA_MAC_VER_18:
2359 rtl8168cp_1_hw_phy_config(tp);
2360 break;
2361 case RTL_GIGA_MAC_VER_19:
2362 rtl8168c_1_hw_phy_config(tp);
2363 break;
2364 case RTL_GIGA_MAC_VER_20:
2365 rtl8168c_2_hw_phy_config(tp);
2366 break;
2367 case RTL_GIGA_MAC_VER_21:
2368 rtl8168c_3_hw_phy_config(tp);
2369 break;
2370 case RTL_GIGA_MAC_VER_22:
2371 rtl8168c_4_hw_phy_config(tp);
2372 break;
2373 case RTL_GIGA_MAC_VER_23:
2374 case RTL_GIGA_MAC_VER_24:
2375 rtl8168cp_2_hw_phy_config(tp);
2376 break;
2377 case RTL_GIGA_MAC_VER_25:
2378 rtl8168d_1_hw_phy_config(tp);
2379 break;
2380 case RTL_GIGA_MAC_VER_26:
2381 rtl8168d_2_hw_phy_config(tp);
2382 break;
2383 case RTL_GIGA_MAC_VER_27:
2384 rtl8168d_3_hw_phy_config(tp);
2385 break;
2386 case RTL_GIGA_MAC_VER_28:
2387 rtl8168d_4_hw_phy_config(tp);
2388 break;
2389
2390 default:
2391 break;
2392 }
2393 }
2394
2395 static void rtl8169_phy_timer(unsigned long __opaque)
2396 {
2397 struct net_device *dev = (struct net_device *)__opaque;
2398 struct rtl8169_private *tp = netdev_priv(dev);
2399 struct timer_list *timer = &tp->timer;
2400 void __iomem *ioaddr = tp->mmio_addr;
2401 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2402
2403 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2404
2405 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2406 return;
2407
2408 spin_lock_irq(&tp->lock);
2409
2410 if (tp->phy_reset_pending(tp)) {
2411 /*
2412 * A busy loop could burn quite a few cycles on nowadays CPU.
2413 * Let's delay the execution of the timer for a few ticks.
2414 */
2415 timeout = HZ/10;
2416 goto out_mod_timer;
2417 }
2418
2419 if (tp->link_ok(ioaddr))
2420 goto out_unlock;
2421
2422 netif_warn(tp, link, dev, "PHY reset until link up\n");
2423
2424 tp->phy_reset_enable(tp);
2425
2426 out_mod_timer:
2427 mod_timer(timer, jiffies + timeout);
2428 out_unlock:
2429 spin_unlock_irq(&tp->lock);
2430 }
2431
2432 static inline void rtl8169_delete_timer(struct net_device *dev)
2433 {
2434 struct rtl8169_private *tp = netdev_priv(dev);
2435 struct timer_list *timer = &tp->timer;
2436
2437 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2438 return;
2439
2440 del_timer_sync(timer);
2441 }
2442
2443 static inline void rtl8169_request_timer(struct net_device *dev)
2444 {
2445 struct rtl8169_private *tp = netdev_priv(dev);
2446 struct timer_list *timer = &tp->timer;
2447
2448 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2449 return;
2450
2451 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2452 }
2453
2454 #ifdef CONFIG_NET_POLL_CONTROLLER
2455 /*
2456 * Polling 'interrupt' - used by things like netconsole to send skbs
2457 * without having to re-enable interrupts. It's not called while
2458 * the interrupt routine is executing.
2459 */
2460 static void rtl8169_netpoll(struct net_device *dev)
2461 {
2462 struct rtl8169_private *tp = netdev_priv(dev);
2463 struct pci_dev *pdev = tp->pci_dev;
2464
2465 disable_irq(pdev->irq);
2466 rtl8169_interrupt(pdev->irq, dev);
2467 enable_irq(pdev->irq);
2468 }
2469 #endif
2470
2471 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2472 void __iomem *ioaddr)
2473 {
2474 iounmap(ioaddr);
2475 pci_release_regions(pdev);
2476 pci_clear_mwi(pdev);
2477 pci_disable_device(pdev);
2478 free_netdev(dev);
2479 }
2480
2481 static void rtl8169_phy_reset(struct net_device *dev,
2482 struct rtl8169_private *tp)
2483 {
2484 unsigned int i;
2485
2486 tp->phy_reset_enable(tp);
2487 for (i = 0; i < 100; i++) {
2488 if (!tp->phy_reset_pending(tp))
2489 return;
2490 msleep(1);
2491 }
2492 netif_err(tp, link, dev, "PHY reset failed\n");
2493 }
2494
2495 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2496 {
2497 void __iomem *ioaddr = tp->mmio_addr;
2498
2499 rtl_hw_phy_config(dev);
2500
2501 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2502 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2503 RTL_W8(0x82, 0x01);
2504 }
2505
2506 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2507
2508 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2509 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2510
2511 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2512 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2513 RTL_W8(0x82, 0x01);
2514 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2515 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2516 }
2517
2518 rtl8169_phy_reset(dev, tp);
2519
2520 /*
2521 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2522 * only 8101. Don't panic.
2523 */
2524 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2525
2526 if (RTL_R8(PHYstatus) & TBI_Enable)
2527 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2528 }
2529
2530 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2531 {
2532 void __iomem *ioaddr = tp->mmio_addr;
2533 u32 high;
2534 u32 low;
2535
2536 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2537 high = addr[4] | (addr[5] << 8);
2538
2539 spin_lock_irq(&tp->lock);
2540
2541 RTL_W8(Cfg9346, Cfg9346_Unlock);
2542
2543 RTL_W32(MAC4, high);
2544 RTL_R32(MAC4);
2545
2546 RTL_W32(MAC0, low);
2547 RTL_R32(MAC0);
2548
2549 RTL_W8(Cfg9346, Cfg9346_Lock);
2550
2551 spin_unlock_irq(&tp->lock);
2552 }
2553
2554 static int rtl_set_mac_address(struct net_device *dev, void *p)
2555 {
2556 struct rtl8169_private *tp = netdev_priv(dev);
2557 struct sockaddr *addr = p;
2558
2559 if (!is_valid_ether_addr(addr->sa_data))
2560 return -EADDRNOTAVAIL;
2561
2562 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2563
2564 rtl_rar_set(tp, dev->dev_addr);
2565
2566 return 0;
2567 }
2568
2569 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2570 {
2571 struct rtl8169_private *tp = netdev_priv(dev);
2572 struct mii_ioctl_data *data = if_mii(ifr);
2573
2574 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2575 }
2576
2577 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2578 {
2579 switch (cmd) {
2580 case SIOCGMIIPHY:
2581 data->phy_id = 32; /* Internal PHY */
2582 return 0;
2583
2584 case SIOCGMIIREG:
2585 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2586 return 0;
2587
2588 case SIOCSMIIREG:
2589 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2590 return 0;
2591 }
2592 return -EOPNOTSUPP;
2593 }
2594
2595 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2596 {
2597 return -EOPNOTSUPP;
2598 }
2599
2600 static const struct rtl_cfg_info {
2601 void (*hw_start)(struct net_device *);
2602 unsigned int region;
2603 unsigned int align;
2604 u16 intr_event;
2605 u16 napi_event;
2606 unsigned features;
2607 u8 default_ver;
2608 } rtl_cfg_infos [] = {
2609 [RTL_CFG_0] = {
2610 .hw_start = rtl_hw_start_8169,
2611 .region = 1,
2612 .align = 0,
2613 .intr_event = SYSErr | LinkChg | RxOverflow |
2614 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2615 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2616 .features = RTL_FEATURE_GMII,
2617 .default_ver = RTL_GIGA_MAC_VER_01,
2618 },
2619 [RTL_CFG_1] = {
2620 .hw_start = rtl_hw_start_8168,
2621 .region = 2,
2622 .align = 8,
2623 .intr_event = SYSErr | LinkChg | RxOverflow |
2624 TxErr | TxOK | RxOK | RxErr,
2625 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2626 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2627 .default_ver = RTL_GIGA_MAC_VER_11,
2628 },
2629 [RTL_CFG_2] = {
2630 .hw_start = rtl_hw_start_8101,
2631 .region = 2,
2632 .align = 8,
2633 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2634 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2635 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2636 .features = RTL_FEATURE_MSI,
2637 .default_ver = RTL_GIGA_MAC_VER_13,
2638 }
2639 };
2640
2641 /* Cfg9346_Unlock assumed. */
2642 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2643 const struct rtl_cfg_info *cfg)
2644 {
2645 unsigned msi = 0;
2646 u8 cfg2;
2647
2648 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2649 if (cfg->features & RTL_FEATURE_MSI) {
2650 if (pci_enable_msi(pdev)) {
2651 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2652 } else {
2653 cfg2 |= MSIEnable;
2654 msi = RTL_FEATURE_MSI;
2655 }
2656 }
2657 RTL_W8(Config2, cfg2);
2658 return msi;
2659 }
2660
2661 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2662 {
2663 if (tp->features & RTL_FEATURE_MSI) {
2664 pci_disable_msi(pdev);
2665 tp->features &= ~RTL_FEATURE_MSI;
2666 }
2667 }
2668
2669 static const struct net_device_ops rtl8169_netdev_ops = {
2670 .ndo_open = rtl8169_open,
2671 .ndo_stop = rtl8169_close,
2672 .ndo_get_stats = rtl8169_get_stats,
2673 .ndo_start_xmit = rtl8169_start_xmit,
2674 .ndo_tx_timeout = rtl8169_tx_timeout,
2675 .ndo_validate_addr = eth_validate_addr,
2676 .ndo_change_mtu = rtl8169_change_mtu,
2677 .ndo_set_mac_address = rtl_set_mac_address,
2678 .ndo_do_ioctl = rtl8169_ioctl,
2679 .ndo_set_multicast_list = rtl_set_rx_mode,
2680 #ifdef CONFIG_R8169_VLAN
2681 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2682 #endif
2683 #ifdef CONFIG_NET_POLL_CONTROLLER
2684 .ndo_poll_controller = rtl8169_netpoll,
2685 #endif
2686
2687 };
2688
2689 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2690 {
2691 struct mdio_ops *ops = &tp->mdio_ops;
2692
2693 switch (tp->mac_version) {
2694 case RTL_GIGA_MAC_VER_27:
2695 ops->write = r8168dp_1_mdio_write;
2696 ops->read = r8168dp_1_mdio_read;
2697 break;
2698 case RTL_GIGA_MAC_VER_28:
2699 ops->write = r8168dp_2_mdio_write;
2700 ops->read = r8168dp_2_mdio_read;
2701 break;
2702 default:
2703 ops->write = r8169_mdio_write;
2704 ops->read = r8169_mdio_read;
2705 break;
2706 }
2707 }
2708
2709 static void r810x_phy_power_down(struct rtl8169_private *tp)
2710 {
2711 rtl_writephy(tp, 0x1f, 0x0000);
2712 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2713 }
2714
2715 static void r810x_phy_power_up(struct rtl8169_private *tp)
2716 {
2717 rtl_writephy(tp, 0x1f, 0x0000);
2718 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2719 }
2720
2721 static void r810x_pll_power_down(struct rtl8169_private *tp)
2722 {
2723 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2724 rtl_writephy(tp, 0x1f, 0x0000);
2725 rtl_writephy(tp, MII_BMCR, 0x0000);
2726 return;
2727 }
2728
2729 r810x_phy_power_down(tp);
2730 }
2731
2732 static void r810x_pll_power_up(struct rtl8169_private *tp)
2733 {
2734 r810x_phy_power_up(tp);
2735 }
2736
2737 static void r8168_phy_power_up(struct rtl8169_private *tp)
2738 {
2739 rtl_writephy(tp, 0x1f, 0x0000);
2740 rtl_writephy(tp, 0x0e, 0x0000);
2741 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2742 }
2743
2744 static void r8168_phy_power_down(struct rtl8169_private *tp)
2745 {
2746 rtl_writephy(tp, 0x1f, 0x0000);
2747 rtl_writephy(tp, 0x0e, 0x0200);
2748 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2749 }
2750
2751 static void r8168_pll_power_down(struct rtl8169_private *tp)
2752 {
2753 void __iomem *ioaddr = tp->mmio_addr;
2754
2755 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2756 return;
2757
2758 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2759 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2760 (RTL_R16(CPlusCmd) & ASF)) {
2761 return;
2762 }
2763
2764 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2765 rtl_writephy(tp, 0x1f, 0x0000);
2766 rtl_writephy(tp, MII_BMCR, 0x0000);
2767
2768 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2769 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2770 return;
2771 }
2772
2773 r8168_phy_power_down(tp);
2774
2775 switch (tp->mac_version) {
2776 case RTL_GIGA_MAC_VER_25:
2777 case RTL_GIGA_MAC_VER_26:
2778 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2779 break;
2780 }
2781 }
2782
2783 static void r8168_pll_power_up(struct rtl8169_private *tp)
2784 {
2785 void __iomem *ioaddr = tp->mmio_addr;
2786
2787 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2788 return;
2789
2790 switch (tp->mac_version) {
2791 case RTL_GIGA_MAC_VER_25:
2792 case RTL_GIGA_MAC_VER_26:
2793 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2794 break;
2795 }
2796
2797 r8168_phy_power_up(tp);
2798 }
2799
2800 static void rtl_pll_power_op(struct rtl8169_private *tp,
2801 void (*op)(struct rtl8169_private *))
2802 {
2803 if (op)
2804 op(tp);
2805 }
2806
2807 static void rtl_pll_power_down(struct rtl8169_private *tp)
2808 {
2809 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2810 }
2811
2812 static void rtl_pll_power_up(struct rtl8169_private *tp)
2813 {
2814 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2815 }
2816
2817 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2818 {
2819 struct pll_power_ops *ops = &tp->pll_power_ops;
2820
2821 switch (tp->mac_version) {
2822 case RTL_GIGA_MAC_VER_07:
2823 case RTL_GIGA_MAC_VER_08:
2824 case RTL_GIGA_MAC_VER_09:
2825 case RTL_GIGA_MAC_VER_10:
2826 case RTL_GIGA_MAC_VER_16:
2827 ops->down = r810x_pll_power_down;
2828 ops->up = r810x_pll_power_up;
2829 break;
2830
2831 case RTL_GIGA_MAC_VER_11:
2832 case RTL_GIGA_MAC_VER_12:
2833 case RTL_GIGA_MAC_VER_17:
2834 case RTL_GIGA_MAC_VER_18:
2835 case RTL_GIGA_MAC_VER_19:
2836 case RTL_GIGA_MAC_VER_20:
2837 case RTL_GIGA_MAC_VER_21:
2838 case RTL_GIGA_MAC_VER_22:
2839 case RTL_GIGA_MAC_VER_23:
2840 case RTL_GIGA_MAC_VER_24:
2841 case RTL_GIGA_MAC_VER_25:
2842 case RTL_GIGA_MAC_VER_26:
2843 case RTL_GIGA_MAC_VER_27:
2844 case RTL_GIGA_MAC_VER_28:
2845 ops->down = r8168_pll_power_down;
2846 ops->up = r8168_pll_power_up;
2847 break;
2848
2849 default:
2850 ops->down = NULL;
2851 ops->up = NULL;
2852 break;
2853 }
2854 }
2855
2856 static int __devinit
2857 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2858 {
2859 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2860 const unsigned int region = cfg->region;
2861 struct rtl8169_private *tp;
2862 struct mii_if_info *mii;
2863 struct net_device *dev;
2864 void __iomem *ioaddr;
2865 unsigned int i;
2866 int rc;
2867
2868 if (netif_msg_drv(&debug)) {
2869 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2870 MODULENAME, RTL8169_VERSION);
2871 }
2872
2873 dev = alloc_etherdev(sizeof (*tp));
2874 if (!dev) {
2875 if (netif_msg_drv(&debug))
2876 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2877 rc = -ENOMEM;
2878 goto out;
2879 }
2880
2881 SET_NETDEV_DEV(dev, &pdev->dev);
2882 dev->netdev_ops = &rtl8169_netdev_ops;
2883 tp = netdev_priv(dev);
2884 tp->dev = dev;
2885 tp->pci_dev = pdev;
2886 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2887
2888 mii = &tp->mii;
2889 mii->dev = dev;
2890 mii->mdio_read = rtl_mdio_read;
2891 mii->mdio_write = rtl_mdio_write;
2892 mii->phy_id_mask = 0x1f;
2893 mii->reg_num_mask = 0x1f;
2894 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2895
2896 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2897 rc = pci_enable_device(pdev);
2898 if (rc < 0) {
2899 netif_err(tp, probe, dev, "enable failure\n");
2900 goto err_out_free_dev_1;
2901 }
2902
2903 if (pci_set_mwi(pdev) < 0)
2904 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
2905
2906 /* make sure PCI base addr 1 is MMIO */
2907 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2908 netif_err(tp, probe, dev,
2909 "region #%d not an MMIO resource, aborting\n",
2910 region);
2911 rc = -ENODEV;
2912 goto err_out_mwi_2;
2913 }
2914
2915 /* check for weird/broken PCI region reporting */
2916 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2917 netif_err(tp, probe, dev,
2918 "Invalid PCI region size(s), aborting\n");
2919 rc = -ENODEV;
2920 goto err_out_mwi_2;
2921 }
2922
2923 rc = pci_request_regions(pdev, MODULENAME);
2924 if (rc < 0) {
2925 netif_err(tp, probe, dev, "could not request regions\n");
2926 goto err_out_mwi_2;
2927 }
2928
2929 tp->cp_cmd = PCIMulRW | RxChkSum;
2930
2931 if ((sizeof(dma_addr_t) > 4) &&
2932 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2933 tp->cp_cmd |= PCIDAC;
2934 dev->features |= NETIF_F_HIGHDMA;
2935 } else {
2936 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2937 if (rc < 0) {
2938 netif_err(tp, probe, dev, "DMA configuration failed\n");
2939 goto err_out_free_res_3;
2940 }
2941 }
2942
2943 /* ioremap MMIO region */
2944 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2945 if (!ioaddr) {
2946 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
2947 rc = -EIO;
2948 goto err_out_free_res_3;
2949 }
2950
2951 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2952 if (!tp->pcie_cap)
2953 netif_info(tp, probe, dev, "no PCI Express capability\n");
2954
2955 RTL_W16(IntrMask, 0x0000);
2956
2957 /* Soft reset the chip. */
2958 RTL_W8(ChipCmd, CmdReset);
2959
2960 /* Check that the chip has finished the reset. */
2961 for (i = 0; i < 100; i++) {
2962 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2963 break;
2964 msleep_interruptible(1);
2965 }
2966
2967 RTL_W16(IntrStatus, 0xffff);
2968
2969 pci_set_master(pdev);
2970
2971 /* Identify chip attached to board */
2972 rtl8169_get_mac_version(tp, ioaddr);
2973
2974 rtl_init_mdio_ops(tp);
2975 rtl_init_pll_power_ops(tp);
2976
2977 /* Use appropriate default if unknown */
2978 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2979 netif_notice(tp, probe, dev,
2980 "unknown MAC, using family default\n");
2981 tp->mac_version = cfg->default_ver;
2982 }
2983
2984 rtl8169_print_mac_version(tp);
2985
2986 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2987 if (tp->mac_version == rtl_chip_info[i].mac_version)
2988 break;
2989 }
2990 if (i == ARRAY_SIZE(rtl_chip_info)) {
2991 dev_err(&pdev->dev,
2992 "driver bug, MAC version not found in rtl_chip_info\n");
2993 goto err_out_msi_4;
2994 }
2995 tp->chipset = i;
2996
2997 RTL_W8(Cfg9346, Cfg9346_Unlock);
2998 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2999 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3000 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3001 tp->features |= RTL_FEATURE_WOL;
3002 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3003 tp->features |= RTL_FEATURE_WOL;
3004 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3005 RTL_W8(Cfg9346, Cfg9346_Lock);
3006
3007 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3008 (RTL_R8(PHYstatus) & TBI_Enable)) {
3009 tp->set_speed = rtl8169_set_speed_tbi;
3010 tp->get_settings = rtl8169_gset_tbi;
3011 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3012 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3013 tp->link_ok = rtl8169_tbi_link_ok;
3014 tp->do_ioctl = rtl_tbi_ioctl;
3015
3016 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3017 } else {
3018 tp->set_speed = rtl8169_set_speed_xmii;
3019 tp->get_settings = rtl8169_gset_xmii;
3020 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3021 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3022 tp->link_ok = rtl8169_xmii_link_ok;
3023 tp->do_ioctl = rtl_xmii_ioctl;
3024 }
3025
3026 spin_lock_init(&tp->lock);
3027
3028 tp->mmio_addr = ioaddr;
3029
3030 /* Get MAC address */
3031 for (i = 0; i < MAC_ADDR_LEN; i++)
3032 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3033 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3034
3035 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3036 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3037 dev->irq = pdev->irq;
3038 dev->base_addr = (unsigned long) ioaddr;
3039
3040 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3041
3042 #ifdef CONFIG_R8169_VLAN
3043 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3044 #endif
3045 dev->features |= NETIF_F_GRO;
3046
3047 tp->intr_mask = 0xffff;
3048 tp->hw_start = cfg->hw_start;
3049 tp->intr_event = cfg->intr_event;
3050 tp->napi_event = cfg->napi_event;
3051
3052 init_timer(&tp->timer);
3053 tp->timer.data = (unsigned long) dev;
3054 tp->timer.function = rtl8169_phy_timer;
3055
3056 rc = register_netdev(dev);
3057 if (rc < 0)
3058 goto err_out_msi_4;
3059
3060 pci_set_drvdata(pdev, dev);
3061
3062 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3063 rtl_chip_info[tp->chipset].name,
3064 dev->base_addr, dev->dev_addr,
3065 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3066
3067 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3068 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3069 rtl8168_driver_start(tp);
3070 }
3071
3072 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3073
3074 if (pci_dev_run_wake(pdev))
3075 pm_runtime_put_noidle(&pdev->dev);
3076
3077 out:
3078 return rc;
3079
3080 err_out_msi_4:
3081 rtl_disable_msi(pdev, tp);
3082 iounmap(ioaddr);
3083 err_out_free_res_3:
3084 pci_release_regions(pdev);
3085 err_out_mwi_2:
3086 pci_clear_mwi(pdev);
3087 pci_disable_device(pdev);
3088 err_out_free_dev_1:
3089 free_netdev(dev);
3090 goto out;
3091 }
3092
3093 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3094 {
3095 struct net_device *dev = pci_get_drvdata(pdev);
3096 struct rtl8169_private *tp = netdev_priv(dev);
3097
3098 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3099 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3100 rtl8168_driver_stop(tp);
3101 }
3102
3103 cancel_delayed_work_sync(&tp->task);
3104
3105 unregister_netdev(dev);
3106
3107 if (pci_dev_run_wake(pdev))
3108 pm_runtime_get_noresume(&pdev->dev);
3109
3110 /* restore original MAC address */
3111 rtl_rar_set(tp, dev->perm_addr);
3112
3113 rtl_disable_msi(pdev, tp);
3114 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3115 pci_set_drvdata(pdev, NULL);
3116 }
3117
3118 static int rtl8169_open(struct net_device *dev)
3119 {
3120 struct rtl8169_private *tp = netdev_priv(dev);
3121 void __iomem *ioaddr = tp->mmio_addr;
3122 struct pci_dev *pdev = tp->pci_dev;
3123 int retval = -ENOMEM;
3124
3125 pm_runtime_get_sync(&pdev->dev);
3126
3127 /*
3128 * Rx and Tx desscriptors needs 256 bytes alignment.
3129 * dma_alloc_coherent provides more.
3130 */
3131 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3132 &tp->TxPhyAddr, GFP_KERNEL);
3133 if (!tp->TxDescArray)
3134 goto err_pm_runtime_put;
3135
3136 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3137 &tp->RxPhyAddr, GFP_KERNEL);
3138 if (!tp->RxDescArray)
3139 goto err_free_tx_0;
3140
3141 retval = rtl8169_init_ring(dev);
3142 if (retval < 0)
3143 goto err_free_rx_1;
3144
3145 INIT_DELAYED_WORK(&tp->task, NULL);
3146
3147 smp_mb();
3148
3149 retval = request_irq(dev->irq, rtl8169_interrupt,
3150 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3151 dev->name, dev);
3152 if (retval < 0)
3153 goto err_release_ring_2;
3154
3155 napi_enable(&tp->napi);
3156
3157 rtl8169_init_phy(dev, tp);
3158
3159 /*
3160 * Pretend we are using VLANs; This bypasses a nasty bug where
3161 * Interrupts stop flowing on high load on 8110SCd controllers.
3162 */
3163 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3164 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3165
3166 rtl_pll_power_up(tp);
3167
3168 rtl_hw_start(dev);
3169
3170 rtl8169_request_timer(dev);
3171
3172 tp->saved_wolopts = 0;
3173 pm_runtime_put_noidle(&pdev->dev);
3174
3175 rtl8169_check_link_status(dev, tp, ioaddr);
3176 out:
3177 return retval;
3178
3179 err_release_ring_2:
3180 rtl8169_rx_clear(tp);
3181 err_free_rx_1:
3182 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3183 tp->RxPhyAddr);
3184 tp->RxDescArray = NULL;
3185 err_free_tx_0:
3186 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3187 tp->TxPhyAddr);
3188 tp->TxDescArray = NULL;
3189 err_pm_runtime_put:
3190 pm_runtime_put_noidle(&pdev->dev);
3191 goto out;
3192 }
3193
3194 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3195 {
3196 void __iomem *ioaddr = tp->mmio_addr;
3197
3198 /* Disable interrupts */
3199 rtl8169_irq_mask_and_ack(ioaddr);
3200
3201 if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3202 while (RTL_R8(TxPoll) & NPQ)
3203 udelay(20);
3204
3205 }
3206
3207 /* Reset the chipset */
3208 RTL_W8(ChipCmd, CmdReset);
3209
3210 /* PCI commit */
3211 RTL_R8(ChipCmd);
3212 }
3213
3214 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3215 {
3216 void __iomem *ioaddr = tp->mmio_addr;
3217 u32 cfg = rtl8169_rx_config;
3218
3219 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3220 RTL_W32(RxConfig, cfg);
3221
3222 /* Set DMA burst size and Interframe Gap Time */
3223 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3224 (InterFrameGap << TxInterFrameGapShift));
3225 }
3226
3227 static void rtl_hw_start(struct net_device *dev)
3228 {
3229 struct rtl8169_private *tp = netdev_priv(dev);
3230 void __iomem *ioaddr = tp->mmio_addr;
3231 unsigned int i;
3232
3233 /* Soft reset the chip. */
3234 RTL_W8(ChipCmd, CmdReset);
3235
3236 /* Check that the chip has finished the reset. */
3237 for (i = 0; i < 100; i++) {
3238 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3239 break;
3240 msleep_interruptible(1);
3241 }
3242
3243 tp->hw_start(dev);
3244
3245 netif_start_queue(dev);
3246 }
3247
3248
3249 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3250 void __iomem *ioaddr)
3251 {
3252 /*
3253 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3254 * register to be written before TxDescAddrLow to work.
3255 * Switching from MMIO to I/O access fixes the issue as well.
3256 */
3257 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3258 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3259 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3260 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3261 }
3262
3263 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3264 {
3265 u16 cmd;
3266
3267 cmd = RTL_R16(CPlusCmd);
3268 RTL_W16(CPlusCmd, cmd);
3269 return cmd;
3270 }
3271
3272 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3273 {
3274 /* Low hurts. Let's disable the filtering. */
3275 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3276 }
3277
3278 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3279 {
3280 static const struct {
3281 u32 mac_version;
3282 u32 clk;
3283 u32 val;
3284 } cfg2_info [] = {
3285 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3286 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3287 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3288 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3289 }, *p = cfg2_info;
3290 unsigned int i;
3291 u32 clk;
3292
3293 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3294 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3295 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3296 RTL_W32(0x7c, p->val);
3297 break;
3298 }
3299 }
3300 }
3301
3302 static void rtl_hw_start_8169(struct net_device *dev)
3303 {
3304 struct rtl8169_private *tp = netdev_priv(dev);
3305 void __iomem *ioaddr = tp->mmio_addr;
3306 struct pci_dev *pdev = tp->pci_dev;
3307
3308 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3309 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3310 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3311 }
3312
3313 RTL_W8(Cfg9346, Cfg9346_Unlock);
3314 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3315 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3316 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3317 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3318 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3319
3320 RTL_W8(EarlyTxThres, NoEarlyTx);
3321
3322 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3323
3324 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3325 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3326 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3327 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3328 rtl_set_rx_tx_config_registers(tp);
3329
3330 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3331
3332 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3333 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3334 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3335 "Bit-3 and bit-14 MUST be 1\n");
3336 tp->cp_cmd |= (1 << 14);
3337 }
3338
3339 RTL_W16(CPlusCmd, tp->cp_cmd);
3340
3341 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3342
3343 /*
3344 * Undocumented corner. Supposedly:
3345 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3346 */
3347 RTL_W16(IntrMitigate, 0x0000);
3348
3349 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3350
3351 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3352 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3353 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3354 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3355 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3356 rtl_set_rx_tx_config_registers(tp);
3357 }
3358
3359 RTL_W8(Cfg9346, Cfg9346_Lock);
3360
3361 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3362 RTL_R8(IntrMask);
3363
3364 RTL_W32(RxMissed, 0);
3365
3366 rtl_set_rx_mode(dev);
3367
3368 /* no early-rx interrupts */
3369 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3370
3371 /* Enable all known interrupts by setting the interrupt mask. */
3372 RTL_W16(IntrMask, tp->intr_event);
3373 }
3374
3375 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3376 {
3377 struct net_device *dev = pci_get_drvdata(pdev);
3378 struct rtl8169_private *tp = netdev_priv(dev);
3379 int cap = tp->pcie_cap;
3380
3381 if (cap) {
3382 u16 ctl;
3383
3384 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3385 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3386 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3387 }
3388 }
3389
3390 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3391 {
3392 u32 csi;
3393
3394 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3395 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3396 }
3397
3398 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3399 {
3400 rtl_csi_access_enable(ioaddr, 0x17000000);
3401 }
3402
3403 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3404 {
3405 rtl_csi_access_enable(ioaddr, 0x27000000);
3406 }
3407
3408 struct ephy_info {
3409 unsigned int offset;
3410 u16 mask;
3411 u16 bits;
3412 };
3413
3414 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3415 {
3416 u16 w;
3417
3418 while (len-- > 0) {
3419 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3420 rtl_ephy_write(ioaddr, e->offset, w);
3421 e++;
3422 }
3423 }
3424
3425 static void rtl_disable_clock_request(struct pci_dev *pdev)
3426 {
3427 struct net_device *dev = pci_get_drvdata(pdev);
3428 struct rtl8169_private *tp = netdev_priv(dev);
3429 int cap = tp->pcie_cap;
3430
3431 if (cap) {
3432 u16 ctl;
3433
3434 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3435 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3436 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3437 }
3438 }
3439
3440 static void rtl_enable_clock_request(struct pci_dev *pdev)
3441 {
3442 struct net_device *dev = pci_get_drvdata(pdev);
3443 struct rtl8169_private *tp = netdev_priv(dev);
3444 int cap = tp->pcie_cap;
3445
3446 if (cap) {
3447 u16 ctl;
3448
3449 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3450 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3451 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3452 }
3453 }
3454
3455 #define R8168_CPCMD_QUIRK_MASK (\
3456 EnableBist | \
3457 Mac_dbgo_oe | \
3458 Force_half_dup | \
3459 Force_rxflow_en | \
3460 Force_txflow_en | \
3461 Cxpl_dbg_sel | \
3462 ASF | \
3463 PktCntrDisable | \
3464 Mac_dbgo_sel)
3465
3466 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3467 {
3468 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3469
3470 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3471
3472 rtl_tx_performance_tweak(pdev,
3473 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3474 }
3475
3476 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3477 {
3478 rtl_hw_start_8168bb(ioaddr, pdev);
3479
3480 RTL_W8(MaxTxPacketSize, TxPacketMax);
3481
3482 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3483 }
3484
3485 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3486 {
3487 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3488
3489 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3490
3491 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3492
3493 rtl_disable_clock_request(pdev);
3494
3495 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3496 }
3497
3498 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3499 {
3500 static const struct ephy_info e_info_8168cp[] = {
3501 { 0x01, 0, 0x0001 },
3502 { 0x02, 0x0800, 0x1000 },
3503 { 0x03, 0, 0x0042 },
3504 { 0x06, 0x0080, 0x0000 },
3505 { 0x07, 0, 0x2000 }
3506 };
3507
3508 rtl_csi_access_enable_2(ioaddr);
3509
3510 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3511
3512 __rtl_hw_start_8168cp(ioaddr, pdev);
3513 }
3514
3515 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3516 {
3517 rtl_csi_access_enable_2(ioaddr);
3518
3519 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3520
3521 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3522
3523 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3524 }
3525
3526 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3527 {
3528 rtl_csi_access_enable_2(ioaddr);
3529
3530 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3531
3532 /* Magic. */
3533 RTL_W8(DBG_REG, 0x20);
3534
3535 RTL_W8(MaxTxPacketSize, TxPacketMax);
3536
3537 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3538
3539 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3540 }
3541
3542 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3543 {
3544 static const struct ephy_info e_info_8168c_1[] = {
3545 { 0x02, 0x0800, 0x1000 },
3546 { 0x03, 0, 0x0002 },
3547 { 0x06, 0x0080, 0x0000 }
3548 };
3549
3550 rtl_csi_access_enable_2(ioaddr);
3551
3552 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3553
3554 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3555
3556 __rtl_hw_start_8168cp(ioaddr, pdev);
3557 }
3558
3559 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3560 {
3561 static const struct ephy_info e_info_8168c_2[] = {
3562 { 0x01, 0, 0x0001 },
3563 { 0x03, 0x0400, 0x0220 }
3564 };
3565
3566 rtl_csi_access_enable_2(ioaddr);
3567
3568 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3569
3570 __rtl_hw_start_8168cp(ioaddr, pdev);
3571 }
3572
3573 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3574 {
3575 rtl_hw_start_8168c_2(ioaddr, pdev);
3576 }
3577
3578 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3579 {
3580 rtl_csi_access_enable_2(ioaddr);
3581
3582 __rtl_hw_start_8168cp(ioaddr, pdev);
3583 }
3584
3585 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3586 {
3587 rtl_csi_access_enable_2(ioaddr);
3588
3589 rtl_disable_clock_request(pdev);
3590
3591 RTL_W8(MaxTxPacketSize, TxPacketMax);
3592
3593 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3594
3595 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3596 }
3597
3598 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3599 {
3600 static const struct ephy_info e_info_8168d_4[] = {
3601 { 0x0b, ~0, 0x48 },
3602 { 0x19, 0x20, 0x50 },
3603 { 0x0c, ~0, 0x20 }
3604 };
3605 int i;
3606
3607 rtl_csi_access_enable_1(ioaddr);
3608
3609 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3610
3611 RTL_W8(MaxTxPacketSize, TxPacketMax);
3612
3613 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3614 const struct ephy_info *e = e_info_8168d_4 + i;
3615 u16 w;
3616
3617 w = rtl_ephy_read(ioaddr, e->offset);
3618 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3619 }
3620
3621 rtl_enable_clock_request(pdev);
3622 }
3623
3624 static void rtl_hw_start_8168(struct net_device *dev)
3625 {
3626 struct rtl8169_private *tp = netdev_priv(dev);
3627 void __iomem *ioaddr = tp->mmio_addr;
3628 struct pci_dev *pdev = tp->pci_dev;
3629
3630 RTL_W8(Cfg9346, Cfg9346_Unlock);
3631
3632 RTL_W8(MaxTxPacketSize, TxPacketMax);
3633
3634 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3635
3636 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3637
3638 RTL_W16(CPlusCmd, tp->cp_cmd);
3639
3640 RTL_W16(IntrMitigate, 0x5151);
3641
3642 /* Work around for RxFIFO overflow. */
3643 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3644 tp->intr_event |= RxFIFOOver | PCSTimeout;
3645 tp->intr_event &= ~RxOverflow;
3646 }
3647
3648 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3649
3650 rtl_set_rx_mode(dev);
3651
3652 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3653 (InterFrameGap << TxInterFrameGapShift));
3654
3655 RTL_R8(IntrMask);
3656
3657 switch (tp->mac_version) {
3658 case RTL_GIGA_MAC_VER_11:
3659 rtl_hw_start_8168bb(ioaddr, pdev);
3660 break;
3661
3662 case RTL_GIGA_MAC_VER_12:
3663 case RTL_GIGA_MAC_VER_17:
3664 rtl_hw_start_8168bef(ioaddr, pdev);
3665 break;
3666
3667 case RTL_GIGA_MAC_VER_18:
3668 rtl_hw_start_8168cp_1(ioaddr, pdev);
3669 break;
3670
3671 case RTL_GIGA_MAC_VER_19:
3672 rtl_hw_start_8168c_1(ioaddr, pdev);
3673 break;
3674
3675 case RTL_GIGA_MAC_VER_20:
3676 rtl_hw_start_8168c_2(ioaddr, pdev);
3677 break;
3678
3679 case RTL_GIGA_MAC_VER_21:
3680 rtl_hw_start_8168c_3(ioaddr, pdev);
3681 break;
3682
3683 case RTL_GIGA_MAC_VER_22:
3684 rtl_hw_start_8168c_4(ioaddr, pdev);
3685 break;
3686
3687 case RTL_GIGA_MAC_VER_23:
3688 rtl_hw_start_8168cp_2(ioaddr, pdev);
3689 break;
3690
3691 case RTL_GIGA_MAC_VER_24:
3692 rtl_hw_start_8168cp_3(ioaddr, pdev);
3693 break;
3694
3695 case RTL_GIGA_MAC_VER_25:
3696 case RTL_GIGA_MAC_VER_26:
3697 case RTL_GIGA_MAC_VER_27:
3698 rtl_hw_start_8168d(ioaddr, pdev);
3699 break;
3700
3701 case RTL_GIGA_MAC_VER_28:
3702 rtl_hw_start_8168d_4(ioaddr, pdev);
3703 break;
3704
3705 default:
3706 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3707 dev->name, tp->mac_version);
3708 break;
3709 }
3710
3711 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3712
3713 RTL_W8(Cfg9346, Cfg9346_Lock);
3714
3715 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3716
3717 RTL_W16(IntrMask, tp->intr_event);
3718 }
3719
3720 #define R810X_CPCMD_QUIRK_MASK (\
3721 EnableBist | \
3722 Mac_dbgo_oe | \
3723 Force_half_dup | \
3724 Force_rxflow_en | \
3725 Force_txflow_en | \
3726 Cxpl_dbg_sel | \
3727 ASF | \
3728 PktCntrDisable | \
3729 PCIDAC | \
3730 PCIMulRW)
3731
3732 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3733 {
3734 static const struct ephy_info e_info_8102e_1[] = {
3735 { 0x01, 0, 0x6e65 },
3736 { 0x02, 0, 0x091f },
3737 { 0x03, 0, 0xc2f9 },
3738 { 0x06, 0, 0xafb5 },
3739 { 0x07, 0, 0x0e00 },
3740 { 0x19, 0, 0xec80 },
3741 { 0x01, 0, 0x2e65 },
3742 { 0x01, 0, 0x6e65 }
3743 };
3744 u8 cfg1;
3745
3746 rtl_csi_access_enable_2(ioaddr);
3747
3748 RTL_W8(DBG_REG, FIX_NAK_1);
3749
3750 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3751
3752 RTL_W8(Config1,
3753 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3754 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3755
3756 cfg1 = RTL_R8(Config1);
3757 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3758 RTL_W8(Config1, cfg1 & ~LEDS0);
3759
3760 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3761
3762 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3763 }
3764
3765 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3766 {
3767 rtl_csi_access_enable_2(ioaddr);
3768
3769 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3770
3771 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3772 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3773
3774 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3775 }
3776
3777 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3778 {
3779 rtl_hw_start_8102e_2(ioaddr, pdev);
3780
3781 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3782 }
3783
3784 static void rtl_hw_start_8101(struct net_device *dev)
3785 {
3786 struct rtl8169_private *tp = netdev_priv(dev);
3787 void __iomem *ioaddr = tp->mmio_addr;
3788 struct pci_dev *pdev = tp->pci_dev;
3789
3790 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3791 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3792 int cap = tp->pcie_cap;
3793
3794 if (cap) {
3795 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3796 PCI_EXP_DEVCTL_NOSNOOP_EN);
3797 }
3798 }
3799
3800 switch (tp->mac_version) {
3801 case RTL_GIGA_MAC_VER_07:
3802 rtl_hw_start_8102e_1(ioaddr, pdev);
3803 break;
3804
3805 case RTL_GIGA_MAC_VER_08:
3806 rtl_hw_start_8102e_3(ioaddr, pdev);
3807 break;
3808
3809 case RTL_GIGA_MAC_VER_09:
3810 rtl_hw_start_8102e_2(ioaddr, pdev);
3811 break;
3812 }
3813
3814 RTL_W8(Cfg9346, Cfg9346_Unlock);
3815
3816 RTL_W8(MaxTxPacketSize, TxPacketMax);
3817
3818 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3819
3820 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3821
3822 RTL_W16(CPlusCmd, tp->cp_cmd);
3823
3824 RTL_W16(IntrMitigate, 0x0000);
3825
3826 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3827
3828 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3829 rtl_set_rx_tx_config_registers(tp);
3830
3831 RTL_W8(Cfg9346, Cfg9346_Lock);
3832
3833 RTL_R8(IntrMask);
3834
3835 rtl_set_rx_mode(dev);
3836
3837 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3838
3839 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3840
3841 RTL_W16(IntrMask, tp->intr_event);
3842 }
3843
3844 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3845 {
3846 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3847 return -EINVAL;
3848
3849 dev->mtu = new_mtu;
3850 return 0;
3851 }
3852
3853 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3854 {
3855 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3856 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3857 }
3858
3859 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3860 void **data_buff, struct RxDesc *desc)
3861 {
3862 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3863 DMA_FROM_DEVICE);
3864
3865 kfree(*data_buff);
3866 *data_buff = NULL;
3867 rtl8169_make_unusable_by_asic(desc);
3868 }
3869
3870 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3871 {
3872 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3873
3874 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3875 }
3876
3877 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3878 u32 rx_buf_sz)
3879 {
3880 desc->addr = cpu_to_le64(mapping);
3881 wmb();
3882 rtl8169_mark_to_asic(desc, rx_buf_sz);
3883 }
3884
3885 static inline void *rtl8169_align(void *data)
3886 {
3887 return (void *)ALIGN((long)data, 16);
3888 }
3889
3890 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3891 struct RxDesc *desc)
3892 {
3893 void *data;
3894 dma_addr_t mapping;
3895 struct device *d = &tp->pci_dev->dev;
3896 struct net_device *dev = tp->dev;
3897 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
3898
3899 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3900 if (!data)
3901 return NULL;
3902
3903 if (rtl8169_align(data) != data) {
3904 kfree(data);
3905 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3906 if (!data)
3907 return NULL;
3908 }
3909
3910 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
3911 DMA_FROM_DEVICE);
3912 if (unlikely(dma_mapping_error(d, mapping))) {
3913 if (net_ratelimit())
3914 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3915 goto err_out;
3916 }
3917
3918 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3919 return data;
3920
3921 err_out:
3922 kfree(data);
3923 return NULL;
3924 }
3925
3926 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3927 {
3928 unsigned int i;
3929
3930 for (i = 0; i < NUM_RX_DESC; i++) {
3931 if (tp->Rx_databuff[i]) {
3932 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
3933 tp->RxDescArray + i);
3934 }
3935 }
3936 }
3937
3938 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3939 {
3940 desc->opts1 |= cpu_to_le32(RingEnd);
3941 }
3942
3943 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3944 {
3945 unsigned int i;
3946
3947 for (i = 0; i < NUM_RX_DESC; i++) {
3948 void *data;
3949
3950 if (tp->Rx_databuff[i])
3951 continue;
3952
3953 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3954 if (!data) {
3955 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
3956 goto err_out;
3957 }
3958 tp->Rx_databuff[i] = data;
3959 }
3960
3961 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3962 return 0;
3963
3964 err_out:
3965 rtl8169_rx_clear(tp);
3966 return -ENOMEM;
3967 }
3968
3969 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3970 {
3971 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3972 }
3973
3974 static int rtl8169_init_ring(struct net_device *dev)
3975 {
3976 struct rtl8169_private *tp = netdev_priv(dev);
3977
3978 rtl8169_init_ring_indexes(tp);
3979
3980 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3981 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
3982
3983 return rtl8169_rx_fill(tp);
3984 }
3985
3986 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
3987 struct TxDesc *desc)
3988 {
3989 unsigned int len = tx_skb->len;
3990
3991 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3992
3993 desc->opts1 = 0x00;
3994 desc->opts2 = 0x00;
3995 desc->addr = 0x00;
3996 tx_skb->len = 0;
3997 }
3998
3999 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4000 unsigned int n)
4001 {
4002 unsigned int i;
4003
4004 for (i = 0; i < n; i++) {
4005 unsigned int entry = (start + i) % NUM_TX_DESC;
4006 struct ring_info *tx_skb = tp->tx_skb + entry;
4007 unsigned int len = tx_skb->len;
4008
4009 if (len) {
4010 struct sk_buff *skb = tx_skb->skb;
4011
4012 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4013 tp->TxDescArray + entry);
4014 if (skb) {
4015 tp->dev->stats.tx_dropped++;
4016 dev_kfree_skb(skb);
4017 tx_skb->skb = NULL;
4018 }
4019 }
4020 }
4021 }
4022
4023 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4024 {
4025 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4026 tp->cur_tx = tp->dirty_tx = 0;
4027 }
4028
4029 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4030 {
4031 struct rtl8169_private *tp = netdev_priv(dev);
4032
4033 PREPARE_DELAYED_WORK(&tp->task, task);
4034 schedule_delayed_work(&tp->task, 4);
4035 }
4036
4037 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4038 {
4039 struct rtl8169_private *tp = netdev_priv(dev);
4040 void __iomem *ioaddr = tp->mmio_addr;
4041
4042 synchronize_irq(dev->irq);
4043
4044 /* Wait for any pending NAPI task to complete */
4045 napi_disable(&tp->napi);
4046
4047 rtl8169_irq_mask_and_ack(ioaddr);
4048
4049 tp->intr_mask = 0xffff;
4050 RTL_W16(IntrMask, tp->intr_event);
4051 napi_enable(&tp->napi);
4052 }
4053
4054 static void rtl8169_reinit_task(struct work_struct *work)
4055 {
4056 struct rtl8169_private *tp =
4057 container_of(work, struct rtl8169_private, task.work);
4058 struct net_device *dev = tp->dev;
4059 int ret;
4060
4061 rtnl_lock();
4062
4063 if (!netif_running(dev))
4064 goto out_unlock;
4065
4066 rtl8169_wait_for_quiescence(dev);
4067 rtl8169_close(dev);
4068
4069 ret = rtl8169_open(dev);
4070 if (unlikely(ret < 0)) {
4071 if (net_ratelimit())
4072 netif_err(tp, drv, dev,
4073 "reinit failure (status = %d). Rescheduling\n",
4074 ret);
4075 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4076 }
4077
4078 out_unlock:
4079 rtnl_unlock();
4080 }
4081
4082 static void rtl8169_reset_task(struct work_struct *work)
4083 {
4084 struct rtl8169_private *tp =
4085 container_of(work, struct rtl8169_private, task.work);
4086 struct net_device *dev = tp->dev;
4087
4088 rtnl_lock();
4089
4090 if (!netif_running(dev))
4091 goto out_unlock;
4092
4093 rtl8169_wait_for_quiescence(dev);
4094
4095 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4096 rtl8169_tx_clear(tp);
4097
4098 if (tp->dirty_rx == tp->cur_rx) {
4099 rtl8169_init_ring_indexes(tp);
4100 rtl_hw_start(dev);
4101 netif_wake_queue(dev);
4102 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4103 } else {
4104 if (net_ratelimit())
4105 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4106 rtl8169_schedule_work(dev, rtl8169_reset_task);
4107 }
4108
4109 out_unlock:
4110 rtnl_unlock();
4111 }
4112
4113 static void rtl8169_tx_timeout(struct net_device *dev)
4114 {
4115 struct rtl8169_private *tp = netdev_priv(dev);
4116
4117 rtl8169_hw_reset(tp);
4118
4119 /* Let's wait a bit while any (async) irq lands on */
4120 rtl8169_schedule_work(dev, rtl8169_reset_task);
4121 }
4122
4123 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4124 u32 opts1)
4125 {
4126 struct skb_shared_info *info = skb_shinfo(skb);
4127 unsigned int cur_frag, entry;
4128 struct TxDesc * uninitialized_var(txd);
4129 struct device *d = &tp->pci_dev->dev;
4130
4131 entry = tp->cur_tx;
4132 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4133 skb_frag_t *frag = info->frags + cur_frag;
4134 dma_addr_t mapping;
4135 u32 status, len;
4136 void *addr;
4137
4138 entry = (entry + 1) % NUM_TX_DESC;
4139
4140 txd = tp->TxDescArray + entry;
4141 len = frag->size;
4142 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4143 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4144 if (unlikely(dma_mapping_error(d, mapping))) {
4145 if (net_ratelimit())
4146 netif_err(tp, drv, tp->dev,
4147 "Failed to map TX fragments DMA!\n");
4148 goto err_out;
4149 }
4150
4151 /* anti gcc 2.95.3 bugware (sic) */
4152 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4153
4154 txd->opts1 = cpu_to_le32(status);
4155 txd->addr = cpu_to_le64(mapping);
4156
4157 tp->tx_skb[entry].len = len;
4158 }
4159
4160 if (cur_frag) {
4161 tp->tx_skb[entry].skb = skb;
4162 txd->opts1 |= cpu_to_le32(LastFrag);
4163 }
4164
4165 return cur_frag;
4166
4167 err_out:
4168 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4169 return -EIO;
4170 }
4171
4172 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4173 {
4174 if (dev->features & NETIF_F_TSO) {
4175 u32 mss = skb_shinfo(skb)->gso_size;
4176
4177 if (mss)
4178 return LargeSend | ((mss & MSSMask) << MSSShift);
4179 }
4180 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4181 const struct iphdr *ip = ip_hdr(skb);
4182
4183 if (ip->protocol == IPPROTO_TCP)
4184 return IPCS | TCPCS;
4185 else if (ip->protocol == IPPROTO_UDP)
4186 return IPCS | UDPCS;
4187 WARN_ON(1); /* we need a WARN() */
4188 }
4189 return 0;
4190 }
4191
4192 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4193 struct net_device *dev)
4194 {
4195 struct rtl8169_private *tp = netdev_priv(dev);
4196 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4197 struct TxDesc *txd = tp->TxDescArray + entry;
4198 void __iomem *ioaddr = tp->mmio_addr;
4199 struct device *d = &tp->pci_dev->dev;
4200 dma_addr_t mapping;
4201 u32 status, len;
4202 u32 opts1;
4203 int frags;
4204
4205 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4206 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4207 goto err_stop_0;
4208 }
4209
4210 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4211 goto err_stop_0;
4212
4213 len = skb_headlen(skb);
4214 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4215 if (unlikely(dma_mapping_error(d, mapping))) {
4216 if (net_ratelimit())
4217 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4218 goto err_dma_0;
4219 }
4220
4221 tp->tx_skb[entry].len = len;
4222 txd->addr = cpu_to_le64(mapping);
4223 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4224
4225 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4226
4227 frags = rtl8169_xmit_frags(tp, skb, opts1);
4228 if (frags < 0)
4229 goto err_dma_1;
4230 else if (frags)
4231 opts1 |= FirstFrag;
4232 else {
4233 opts1 |= FirstFrag | LastFrag;
4234 tp->tx_skb[entry].skb = skb;
4235 }
4236
4237 wmb();
4238
4239 /* anti gcc 2.95.3 bugware (sic) */
4240 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4241 txd->opts1 = cpu_to_le32(status);
4242
4243 tp->cur_tx += frags + 1;
4244
4245 wmb();
4246
4247 RTL_W8(TxPoll, NPQ); /* set polling bit */
4248
4249 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4250 netif_stop_queue(dev);
4251 smp_rmb();
4252 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4253 netif_wake_queue(dev);
4254 }
4255
4256 return NETDEV_TX_OK;
4257
4258 err_dma_1:
4259 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4260 err_dma_0:
4261 dev_kfree_skb(skb);
4262 dev->stats.tx_dropped++;
4263 return NETDEV_TX_OK;
4264
4265 err_stop_0:
4266 netif_stop_queue(dev);
4267 dev->stats.tx_dropped++;
4268 return NETDEV_TX_BUSY;
4269 }
4270
4271 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4272 {
4273 struct rtl8169_private *tp = netdev_priv(dev);
4274 struct pci_dev *pdev = tp->pci_dev;
4275 u16 pci_status, pci_cmd;
4276
4277 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4278 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4279
4280 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4281 pci_cmd, pci_status);
4282
4283 /*
4284 * The recovery sequence below admits a very elaborated explanation:
4285 * - it seems to work;
4286 * - I did not see what else could be done;
4287 * - it makes iop3xx happy.
4288 *
4289 * Feel free to adjust to your needs.
4290 */
4291 if (pdev->broken_parity_status)
4292 pci_cmd &= ~PCI_COMMAND_PARITY;
4293 else
4294 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4295
4296 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4297
4298 pci_write_config_word(pdev, PCI_STATUS,
4299 pci_status & (PCI_STATUS_DETECTED_PARITY |
4300 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4301 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4302
4303 /* The infamous DAC f*ckup only happens at boot time */
4304 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4305 void __iomem *ioaddr = tp->mmio_addr;
4306
4307 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4308 tp->cp_cmd &= ~PCIDAC;
4309 RTL_W16(CPlusCmd, tp->cp_cmd);
4310 dev->features &= ~NETIF_F_HIGHDMA;
4311 }
4312
4313 rtl8169_hw_reset(tp);
4314
4315 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4316 }
4317
4318 static void rtl8169_tx_interrupt(struct net_device *dev,
4319 struct rtl8169_private *tp,
4320 void __iomem *ioaddr)
4321 {
4322 unsigned int dirty_tx, tx_left;
4323
4324 dirty_tx = tp->dirty_tx;
4325 smp_rmb();
4326 tx_left = tp->cur_tx - dirty_tx;
4327
4328 while (tx_left > 0) {
4329 unsigned int entry = dirty_tx % NUM_TX_DESC;
4330 struct ring_info *tx_skb = tp->tx_skb + entry;
4331 u32 status;
4332
4333 rmb();
4334 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4335 if (status & DescOwn)
4336 break;
4337
4338 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4339 tp->TxDescArray + entry);
4340 if (status & LastFrag) {
4341 dev->stats.tx_packets++;
4342 dev->stats.tx_bytes += tx_skb->skb->len;
4343 dev_kfree_skb(tx_skb->skb);
4344 tx_skb->skb = NULL;
4345 }
4346 dirty_tx++;
4347 tx_left--;
4348 }
4349
4350 if (tp->dirty_tx != dirty_tx) {
4351 tp->dirty_tx = dirty_tx;
4352 smp_wmb();
4353 if (netif_queue_stopped(dev) &&
4354 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4355 netif_wake_queue(dev);
4356 }
4357 /*
4358 * 8168 hack: TxPoll requests are lost when the Tx packets are
4359 * too close. Let's kick an extra TxPoll request when a burst
4360 * of start_xmit activity is detected (if it is not detected,
4361 * it is slow enough). -- FR
4362 */
4363 smp_rmb();
4364 if (tp->cur_tx != dirty_tx)
4365 RTL_W8(TxPoll, NPQ);
4366 }
4367 }
4368
4369 static inline int rtl8169_fragmented_frame(u32 status)
4370 {
4371 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4372 }
4373
4374 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4375 {
4376 u32 status = opts1 & RxProtoMask;
4377
4378 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4379 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4380 skb->ip_summed = CHECKSUM_UNNECESSARY;
4381 else
4382 skb_checksum_none_assert(skb);
4383 }
4384
4385 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4386 struct rtl8169_private *tp,
4387 int pkt_size,
4388 dma_addr_t addr)
4389 {
4390 struct sk_buff *skb;
4391 struct device *d = &tp->pci_dev->dev;
4392
4393 data = rtl8169_align(data);
4394 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4395 prefetch(data);
4396 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4397 if (skb)
4398 memcpy(skb->data, data, pkt_size);
4399 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4400
4401 return skb;
4402 }
4403
4404 /*
4405 * Warning : rtl8169_rx_interrupt() might be called :
4406 * 1) from NAPI (softirq) context
4407 * (polling = 1 : we should call netif_receive_skb())
4408 * 2) from process context (rtl8169_reset_task())
4409 * (polling = 0 : we must call netif_rx() instead)
4410 */
4411 static int rtl8169_rx_interrupt(struct net_device *dev,
4412 struct rtl8169_private *tp,
4413 void __iomem *ioaddr, u32 budget)
4414 {
4415 unsigned int cur_rx, rx_left;
4416 unsigned int count;
4417 int polling = (budget != ~(u32)0) ? 1 : 0;
4418
4419 cur_rx = tp->cur_rx;
4420 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4421 rx_left = min(rx_left, budget);
4422
4423 for (; rx_left > 0; rx_left--, cur_rx++) {
4424 unsigned int entry = cur_rx % NUM_RX_DESC;
4425 struct RxDesc *desc = tp->RxDescArray + entry;
4426 u32 status;
4427
4428 rmb();
4429 status = le32_to_cpu(desc->opts1);
4430
4431 if (status & DescOwn)
4432 break;
4433 if (unlikely(status & RxRES)) {
4434 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4435 status);
4436 dev->stats.rx_errors++;
4437 if (status & (RxRWT | RxRUNT))
4438 dev->stats.rx_length_errors++;
4439 if (status & RxCRC)
4440 dev->stats.rx_crc_errors++;
4441 if (status & RxFOVF) {
4442 rtl8169_schedule_work(dev, rtl8169_reset_task);
4443 dev->stats.rx_fifo_errors++;
4444 }
4445 rtl8169_mark_to_asic(desc, rx_buf_sz);
4446 } else {
4447 struct sk_buff *skb;
4448 dma_addr_t addr = le64_to_cpu(desc->addr);
4449 int pkt_size = (status & 0x00001FFF) - 4;
4450
4451 /*
4452 * The driver does not support incoming fragmented
4453 * frames. They are seen as a symptom of over-mtu
4454 * sized frames.
4455 */
4456 if (unlikely(rtl8169_fragmented_frame(status))) {
4457 dev->stats.rx_dropped++;
4458 dev->stats.rx_length_errors++;
4459 rtl8169_mark_to_asic(desc, rx_buf_sz);
4460 continue;
4461 }
4462
4463 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4464 tp, pkt_size, addr);
4465 rtl8169_mark_to_asic(desc, rx_buf_sz);
4466 if (!skb) {
4467 dev->stats.rx_dropped++;
4468 continue;
4469 }
4470
4471 rtl8169_rx_csum(skb, status);
4472 skb_put(skb, pkt_size);
4473 skb->protocol = eth_type_trans(skb, dev);
4474
4475 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4476 if (likely(polling))
4477 napi_gro_receive(&tp->napi, skb);
4478 else
4479 netif_rx(skb);
4480 }
4481
4482 dev->stats.rx_bytes += pkt_size;
4483 dev->stats.rx_packets++;
4484 }
4485
4486 /* Work around for AMD plateform. */
4487 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4488 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4489 desc->opts2 = 0;
4490 cur_rx++;
4491 }
4492 }
4493
4494 count = cur_rx - tp->cur_rx;
4495 tp->cur_rx = cur_rx;
4496
4497 tp->dirty_rx += count;
4498
4499 return count;
4500 }
4501
4502 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4503 {
4504 struct net_device *dev = dev_instance;
4505 struct rtl8169_private *tp = netdev_priv(dev);
4506 void __iomem *ioaddr = tp->mmio_addr;
4507 int handled = 0;
4508 int status;
4509
4510 /* loop handling interrupts until we have no new ones or
4511 * we hit a invalid/hotplug case.
4512 */
4513 status = RTL_R16(IntrStatus);
4514 while (status && status != 0xffff) {
4515 handled = 1;
4516
4517 /* Handle all of the error cases first. These will reset
4518 * the chip, so just exit the loop.
4519 */
4520 if (unlikely(!netif_running(dev))) {
4521 rtl8169_asic_down(ioaddr);
4522 break;
4523 }
4524
4525 /* Work around for rx fifo overflow */
4526 if (unlikely(status & RxFIFOOver) &&
4527 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4528 netif_stop_queue(dev);
4529 rtl8169_tx_timeout(dev);
4530 break;
4531 }
4532
4533 if (unlikely(status & SYSErr)) {
4534 rtl8169_pcierr_interrupt(dev);
4535 break;
4536 }
4537
4538 if (status & LinkChg)
4539 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4540
4541 /* We need to see the lastest version of tp->intr_mask to
4542 * avoid ignoring an MSI interrupt and having to wait for
4543 * another event which may never come.
4544 */
4545 smp_rmb();
4546 if (status & tp->intr_mask & tp->napi_event) {
4547 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4548 tp->intr_mask = ~tp->napi_event;
4549
4550 if (likely(napi_schedule_prep(&tp->napi)))
4551 __napi_schedule(&tp->napi);
4552 else
4553 netif_info(tp, intr, dev,
4554 "interrupt %04x in poll\n", status);
4555 }
4556
4557 /* We only get a new MSI interrupt when all active irq
4558 * sources on the chip have been acknowledged. So, ack
4559 * everything we've seen and check if new sources have become
4560 * active to avoid blocking all interrupts from the chip.
4561 */
4562 RTL_W16(IntrStatus,
4563 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4564 status = RTL_R16(IntrStatus);
4565 }
4566
4567 return IRQ_RETVAL(handled);
4568 }
4569
4570 static int rtl8169_poll(struct napi_struct *napi, int budget)
4571 {
4572 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4573 struct net_device *dev = tp->dev;
4574 void __iomem *ioaddr = tp->mmio_addr;
4575 int work_done;
4576
4577 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4578 rtl8169_tx_interrupt(dev, tp, ioaddr);
4579
4580 if (work_done < budget) {
4581 napi_complete(napi);
4582
4583 /* We need for force the visibility of tp->intr_mask
4584 * for other CPUs, as we can loose an MSI interrupt
4585 * and potentially wait for a retransmit timeout if we don't.
4586 * The posted write to IntrMask is safe, as it will
4587 * eventually make it to the chip and we won't loose anything
4588 * until it does.
4589 */
4590 tp->intr_mask = 0xffff;
4591 wmb();
4592 RTL_W16(IntrMask, tp->intr_event);
4593 }
4594
4595 return work_done;
4596 }
4597
4598 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4599 {
4600 struct rtl8169_private *tp = netdev_priv(dev);
4601
4602 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4603 return;
4604
4605 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4606 RTL_W32(RxMissed, 0);
4607 }
4608
4609 static void rtl8169_down(struct net_device *dev)
4610 {
4611 struct rtl8169_private *tp = netdev_priv(dev);
4612 void __iomem *ioaddr = tp->mmio_addr;
4613
4614 rtl8169_delete_timer(dev);
4615
4616 netif_stop_queue(dev);
4617
4618 napi_disable(&tp->napi);
4619
4620 spin_lock_irq(&tp->lock);
4621
4622 rtl8169_asic_down(ioaddr);
4623 /*
4624 * At this point device interrupts can not be enabled in any function,
4625 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4626 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4627 */
4628 rtl8169_rx_missed(dev, ioaddr);
4629
4630 spin_unlock_irq(&tp->lock);
4631
4632 synchronize_irq(dev->irq);
4633
4634 /* Give a racing hard_start_xmit a few cycles to complete. */
4635 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4636
4637 rtl8169_tx_clear(tp);
4638
4639 rtl8169_rx_clear(tp);
4640
4641 rtl_pll_power_down(tp);
4642 }
4643
4644 static int rtl8169_close(struct net_device *dev)
4645 {
4646 struct rtl8169_private *tp = netdev_priv(dev);
4647 struct pci_dev *pdev = tp->pci_dev;
4648
4649 pm_runtime_get_sync(&pdev->dev);
4650
4651 /* update counters before going down */
4652 rtl8169_update_counters(dev);
4653
4654 rtl8169_down(dev);
4655
4656 free_irq(dev->irq, dev);
4657
4658 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4659 tp->RxPhyAddr);
4660 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4661 tp->TxPhyAddr);
4662 tp->TxDescArray = NULL;
4663 tp->RxDescArray = NULL;
4664
4665 pm_runtime_put_sync(&pdev->dev);
4666
4667 return 0;
4668 }
4669
4670 static void rtl_set_rx_mode(struct net_device *dev)
4671 {
4672 struct rtl8169_private *tp = netdev_priv(dev);
4673 void __iomem *ioaddr = tp->mmio_addr;
4674 unsigned long flags;
4675 u32 mc_filter[2]; /* Multicast hash filter */
4676 int rx_mode;
4677 u32 tmp = 0;
4678
4679 if (dev->flags & IFF_PROMISC) {
4680 /* Unconditionally log net taps. */
4681 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4682 rx_mode =
4683 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4684 AcceptAllPhys;
4685 mc_filter[1] = mc_filter[0] = 0xffffffff;
4686 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4687 (dev->flags & IFF_ALLMULTI)) {
4688 /* Too many to filter perfectly -- accept all multicasts. */
4689 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4690 mc_filter[1] = mc_filter[0] = 0xffffffff;
4691 } else {
4692 struct netdev_hw_addr *ha;
4693
4694 rx_mode = AcceptBroadcast | AcceptMyPhys;
4695 mc_filter[1] = mc_filter[0] = 0;
4696 netdev_for_each_mc_addr(ha, dev) {
4697 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4698 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4699 rx_mode |= AcceptMulticast;
4700 }
4701 }
4702
4703 spin_lock_irqsave(&tp->lock, flags);
4704
4705 tmp = rtl8169_rx_config | rx_mode |
4706 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4707
4708 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4709 u32 data = mc_filter[0];
4710
4711 mc_filter[0] = swab32(mc_filter[1]);
4712 mc_filter[1] = swab32(data);
4713 }
4714
4715 RTL_W32(MAR0 + 4, mc_filter[1]);
4716 RTL_W32(MAR0 + 0, mc_filter[0]);
4717
4718 RTL_W32(RxConfig, tmp);
4719
4720 spin_unlock_irqrestore(&tp->lock, flags);
4721 }
4722
4723 /**
4724 * rtl8169_get_stats - Get rtl8169 read/write statistics
4725 * @dev: The Ethernet Device to get statistics for
4726 *
4727 * Get TX/RX statistics for rtl8169
4728 */
4729 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4730 {
4731 struct rtl8169_private *tp = netdev_priv(dev);
4732 void __iomem *ioaddr = tp->mmio_addr;
4733 unsigned long flags;
4734
4735 if (netif_running(dev)) {
4736 spin_lock_irqsave(&tp->lock, flags);
4737 rtl8169_rx_missed(dev, ioaddr);
4738 spin_unlock_irqrestore(&tp->lock, flags);
4739 }
4740
4741 return &dev->stats;
4742 }
4743
4744 static void rtl8169_net_suspend(struct net_device *dev)
4745 {
4746 struct rtl8169_private *tp = netdev_priv(dev);
4747
4748 if (!netif_running(dev))
4749 return;
4750
4751 rtl_pll_power_down(tp);
4752
4753 netif_device_detach(dev);
4754 netif_stop_queue(dev);
4755 }
4756
4757 #ifdef CONFIG_PM
4758
4759 static int rtl8169_suspend(struct device *device)
4760 {
4761 struct pci_dev *pdev = to_pci_dev(device);
4762 struct net_device *dev = pci_get_drvdata(pdev);
4763
4764 rtl8169_net_suspend(dev);
4765
4766 return 0;
4767 }
4768
4769 static void __rtl8169_resume(struct net_device *dev)
4770 {
4771 struct rtl8169_private *tp = netdev_priv(dev);
4772
4773 netif_device_attach(dev);
4774
4775 rtl_pll_power_up(tp);
4776
4777 rtl8169_schedule_work(dev, rtl8169_reset_task);
4778 }
4779
4780 static int rtl8169_resume(struct device *device)
4781 {
4782 struct pci_dev *pdev = to_pci_dev(device);
4783 struct net_device *dev = pci_get_drvdata(pdev);
4784 struct rtl8169_private *tp = netdev_priv(dev);
4785
4786 rtl8169_init_phy(dev, tp);
4787
4788 if (netif_running(dev))
4789 __rtl8169_resume(dev);
4790
4791 return 0;
4792 }
4793
4794 static int rtl8169_runtime_suspend(struct device *device)
4795 {
4796 struct pci_dev *pdev = to_pci_dev(device);
4797 struct net_device *dev = pci_get_drvdata(pdev);
4798 struct rtl8169_private *tp = netdev_priv(dev);
4799
4800 if (!tp->TxDescArray)
4801 return 0;
4802
4803 spin_lock_irq(&tp->lock);
4804 tp->saved_wolopts = __rtl8169_get_wol(tp);
4805 __rtl8169_set_wol(tp, WAKE_ANY);
4806 spin_unlock_irq(&tp->lock);
4807
4808 rtl8169_net_suspend(dev);
4809
4810 return 0;
4811 }
4812
4813 static int rtl8169_runtime_resume(struct device *device)
4814 {
4815 struct pci_dev *pdev = to_pci_dev(device);
4816 struct net_device *dev = pci_get_drvdata(pdev);
4817 struct rtl8169_private *tp = netdev_priv(dev);
4818
4819 if (!tp->TxDescArray)
4820 return 0;
4821
4822 spin_lock_irq(&tp->lock);
4823 __rtl8169_set_wol(tp, tp->saved_wolopts);
4824 tp->saved_wolopts = 0;
4825 spin_unlock_irq(&tp->lock);
4826
4827 rtl8169_init_phy(dev, tp);
4828
4829 __rtl8169_resume(dev);
4830
4831 return 0;
4832 }
4833
4834 static int rtl8169_runtime_idle(struct device *device)
4835 {
4836 struct pci_dev *pdev = to_pci_dev(device);
4837 struct net_device *dev = pci_get_drvdata(pdev);
4838 struct rtl8169_private *tp = netdev_priv(dev);
4839
4840 return tp->TxDescArray ? -EBUSY : 0;
4841 }
4842
4843 static const struct dev_pm_ops rtl8169_pm_ops = {
4844 .suspend = rtl8169_suspend,
4845 .resume = rtl8169_resume,
4846 .freeze = rtl8169_suspend,
4847 .thaw = rtl8169_resume,
4848 .poweroff = rtl8169_suspend,
4849 .restore = rtl8169_resume,
4850 .runtime_suspend = rtl8169_runtime_suspend,
4851 .runtime_resume = rtl8169_runtime_resume,
4852 .runtime_idle = rtl8169_runtime_idle,
4853 };
4854
4855 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4856
4857 #else /* !CONFIG_PM */
4858
4859 #define RTL8169_PM_OPS NULL
4860
4861 #endif /* !CONFIG_PM */
4862
4863 static void rtl_shutdown(struct pci_dev *pdev)
4864 {
4865 struct net_device *dev = pci_get_drvdata(pdev);
4866 struct rtl8169_private *tp = netdev_priv(dev);
4867 void __iomem *ioaddr = tp->mmio_addr;
4868
4869 rtl8169_net_suspend(dev);
4870
4871 /* restore original MAC address */
4872 rtl_rar_set(tp, dev->perm_addr);
4873
4874 spin_lock_irq(&tp->lock);
4875
4876 rtl8169_asic_down(ioaddr);
4877
4878 spin_unlock_irq(&tp->lock);
4879
4880 if (system_state == SYSTEM_POWER_OFF) {
4881 /* WoL fails with some 8168 when the receiver is disabled. */
4882 if (tp->features & RTL_FEATURE_WOL) {
4883 pci_clear_master(pdev);
4884
4885 RTL_W8(ChipCmd, CmdRxEnb);
4886 /* PCI commit */
4887 RTL_R8(ChipCmd);
4888 }
4889
4890 pci_wake_from_d3(pdev, true);
4891 pci_set_power_state(pdev, PCI_D3hot);
4892 }
4893 }
4894
4895 static struct pci_driver rtl8169_pci_driver = {
4896 .name = MODULENAME,
4897 .id_table = rtl8169_pci_tbl,
4898 .probe = rtl8169_init_one,
4899 .remove = __devexit_p(rtl8169_remove_one),
4900 .shutdown = rtl_shutdown,
4901 .driver.pm = RTL8169_PM_OPS,
4902 };
4903
4904 static int __init rtl8169_init_module(void)
4905 {
4906 return pci_register_driver(&rtl8169_pci_driver);
4907 }
4908
4909 static void __exit rtl8169_cleanup_module(void)
4910 {
4911 pci_unregister_driver(&rtl8169_pci_driver);
4912 }
4913
4914 module_init(rtl8169_init_module);
4915 module_exit(rtl8169_cleanup_module);
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