2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
30 #include <asm/system.h>
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45 #define assert(expr) \
47 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
48 #expr,__FILE__,__func__,__LINE__); \
50 #define dprintk(fmt, args...) \
51 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
53 #define assert(expr) do {} while (0)
54 #define dprintk(fmt, args...) do {} while (0)
55 #endif /* RTL8169_DEBUG */
57 #define R8169_MSG_DEFAULT \
58 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
60 #define TX_BUFFS_AVAIL(tp) \
61 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
65 static const int multicast_filter_limit
= 32;
67 /* MAC address length */
68 #define MAC_ADDR_LEN 6
70 #define MAX_READ_REQUEST_SHIFT 12
71 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77 #define R8169_REGS_SIZE 256
78 #define R8169_NAPI_WEIGHT 64
79 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85 #define RTL8169_TX_TIMEOUT (6*HZ)
86 #define RTL8169_PHY_TIMEOUT (10*HZ)
88 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR 0x0000
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg) readb (ioaddr + (reg))
97 #define RTL_R16(reg) readw (ioaddr + (reg))
98 #define RTL_R32(reg) readl (ioaddr + (reg))
101 RTL_GIGA_MAC_VER_01
= 0,
134 RTL_GIGA_MAC_NONE
= 0xff,
137 enum rtl_tx_desc_version
{
142 #define _R(NAME,TD,FW) \
143 { .name = NAME, .txd_version = TD, .fw_name = FW }
145 static const struct {
147 enum rtl_tx_desc_version txd_version
;
149 } rtl_chip_infos
[] = {
151 [RTL_GIGA_MAC_VER_01
] =
152 _R("RTL8169", RTL_TD_0
, NULL
),
153 [RTL_GIGA_MAC_VER_02
] =
154 _R("RTL8169s", RTL_TD_0
, NULL
),
155 [RTL_GIGA_MAC_VER_03
] =
156 _R("RTL8110s", RTL_TD_0
, NULL
),
157 [RTL_GIGA_MAC_VER_04
] =
158 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
),
159 [RTL_GIGA_MAC_VER_05
] =
160 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
161 [RTL_GIGA_MAC_VER_06
] =
162 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
164 [RTL_GIGA_MAC_VER_07
] =
165 _R("RTL8102e", RTL_TD_1
, NULL
),
166 [RTL_GIGA_MAC_VER_08
] =
167 _R("RTL8102e", RTL_TD_1
, NULL
),
168 [RTL_GIGA_MAC_VER_09
] =
169 _R("RTL8102e", RTL_TD_1
, NULL
),
170 [RTL_GIGA_MAC_VER_10
] =
171 _R("RTL8101e", RTL_TD_0
, NULL
),
172 [RTL_GIGA_MAC_VER_11
] =
173 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
174 [RTL_GIGA_MAC_VER_12
] =
175 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
176 [RTL_GIGA_MAC_VER_13
] =
177 _R("RTL8101e", RTL_TD_0
, NULL
),
178 [RTL_GIGA_MAC_VER_14
] =
179 _R("RTL8100e", RTL_TD_0
, NULL
),
180 [RTL_GIGA_MAC_VER_15
] =
181 _R("RTL8100e", RTL_TD_0
, NULL
),
182 [RTL_GIGA_MAC_VER_16
] =
183 _R("RTL8101e", RTL_TD_0
, NULL
),
184 [RTL_GIGA_MAC_VER_17
] =
185 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
186 [RTL_GIGA_MAC_VER_18
] =
187 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
188 [RTL_GIGA_MAC_VER_19
] =
189 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
190 [RTL_GIGA_MAC_VER_20
] =
191 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
192 [RTL_GIGA_MAC_VER_21
] =
193 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
194 [RTL_GIGA_MAC_VER_22
] =
195 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
196 [RTL_GIGA_MAC_VER_23
] =
197 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
198 [RTL_GIGA_MAC_VER_24
] =
199 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
200 [RTL_GIGA_MAC_VER_25
] =
201 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
),
202 [RTL_GIGA_MAC_VER_26
] =
203 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
),
204 [RTL_GIGA_MAC_VER_27
] =
205 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
206 [RTL_GIGA_MAC_VER_28
] =
207 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
208 [RTL_GIGA_MAC_VER_29
] =
209 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
210 [RTL_GIGA_MAC_VER_30
] =
211 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
212 [RTL_GIGA_MAC_VER_31
] =
213 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
214 [RTL_GIGA_MAC_VER_32
] =
215 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
),
216 [RTL_GIGA_MAC_VER_33
] =
217 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
)
227 static void rtl_hw_start_8169(struct net_device
*);
228 static void rtl_hw_start_8168(struct net_device
*);
229 static void rtl_hw_start_8101(struct net_device
*);
231 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
232 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
233 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
234 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
235 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
237 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
238 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
239 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
240 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
241 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
243 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
247 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
249 static int rx_buf_sz
= 16383;
256 MAC0
= 0, /* Ethernet hardware address. */
258 MAR0
= 8, /* Multicast filter. */
259 CounterAddrLow
= 0x10,
260 CounterAddrHigh
= 0x14,
261 TxDescStartAddrLow
= 0x20,
262 TxDescStartAddrHigh
= 0x24,
263 TxHDescStartAddrLow
= 0x28,
264 TxHDescStartAddrHigh
= 0x2c,
274 #define RTL_RX_CONFIG_MASK 0xff7e1880u
290 RxDescAddrLow
= 0xe4,
291 RxDescAddrHigh
= 0xe8,
292 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
294 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
296 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
298 #define TxPacketMax (8064 >> 7)
301 FuncEventMask
= 0xf4,
302 FuncPresetState
= 0xf8,
303 FuncForceEvent
= 0xfc,
306 enum rtl8110_registers
{
312 enum rtl8168_8101_registers
{
315 #define CSIAR_FLAG 0x80000000
316 #define CSIAR_WRITE_CMD 0x80000000
317 #define CSIAR_BYTE_ENABLE 0x0f
318 #define CSIAR_BYTE_ENABLE_SHIFT 12
319 #define CSIAR_ADDR_MASK 0x0fff
322 #define EPHYAR_FLAG 0x80000000
323 #define EPHYAR_WRITE_CMD 0x80000000
324 #define EPHYAR_REG_MASK 0x1f
325 #define EPHYAR_REG_SHIFT 16
326 #define EPHYAR_DATA_MASK 0xffff
328 #define PM_SWITCH (1 << 6)
330 #define FIX_NAK_1 (1 << 4)
331 #define FIX_NAK_2 (1 << 3)
334 #define EN_NDP (1 << 3)
335 #define EN_OOB_RESET (1 << 2)
337 #define EFUSEAR_FLAG 0x80000000
338 #define EFUSEAR_WRITE_CMD 0x80000000
339 #define EFUSEAR_READ_CMD 0x00000000
340 #define EFUSEAR_REG_MASK 0x03ff
341 #define EFUSEAR_REG_SHIFT 8
342 #define EFUSEAR_DATA_MASK 0xff
345 enum rtl8168_registers
{
348 #define ERIAR_FLAG 0x80000000
349 #define ERIAR_WRITE_CMD 0x80000000
350 #define ERIAR_READ_CMD 0x00000000
351 #define ERIAR_ADDR_BYTE_ALIGN 4
352 #define ERIAR_EXGMAC 0
355 #define ERIAR_TYPE_SHIFT 16
356 #define ERIAR_BYTEEN 0x0f
357 #define ERIAR_BYTEEN_SHIFT 12
358 EPHY_RXER_NUM
= 0x7c,
359 OCPDR
= 0xb0, /* OCP GPHY access */
360 #define OCPDR_WRITE_CMD 0x80000000
361 #define OCPDR_READ_CMD 0x00000000
362 #define OCPDR_REG_MASK 0x7f
363 #define OCPDR_GPHY_REG_SHIFT 16
364 #define OCPDR_DATA_MASK 0xffff
366 #define OCPAR_FLAG 0x80000000
367 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
368 #define OCPAR_GPHY_READ_CMD 0x0000f060
369 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
370 MISC
= 0xf0, /* 8168e only. */
371 #define TXPLA_RST (1 << 29)
374 enum rtl_register_content
{
375 /* InterruptStatusBits */
379 TxDescUnavail
= 0x0080,
401 /* TXPoll register p.5 */
402 HPQ
= 0x80, /* Poll cmd on the high prio queue */
403 NPQ
= 0x40, /* Poll cmd on the low prio queue */
404 FSWInt
= 0x01, /* Forced software interrupt */
408 Cfg9346_Unlock
= 0xc0,
413 AcceptBroadcast
= 0x08,
414 AcceptMulticast
= 0x04,
416 AcceptAllPhys
= 0x01,
423 TxInterFrameGapShift
= 24,
424 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
426 /* Config1 register p.24 */
429 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
430 Speed_down
= (1 << 4),
434 PMEnable
= (1 << 0), /* Power Management Enable */
436 /* Config2 register p. 25 */
437 PCI_Clock_66MHz
= 0x01,
438 PCI_Clock_33MHz
= 0x00,
440 /* Config3 register p.25 */
441 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
442 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
443 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
445 /* Config5 register p.27 */
446 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
447 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
448 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
450 LanWake
= (1 << 1), /* LanWake enable/disable */
451 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
454 TBIReset
= 0x80000000,
455 TBILoopback
= 0x40000000,
456 TBINwEnable
= 0x20000000,
457 TBINwRestart
= 0x10000000,
458 TBILinkOk
= 0x02000000,
459 TBINwComplete
= 0x01000000,
462 EnableBist
= (1 << 15), // 8168 8101
463 Mac_dbgo_oe
= (1 << 14), // 8168 8101
464 Normal_mode
= (1 << 13), // unused
465 Force_half_dup
= (1 << 12), // 8168 8101
466 Force_rxflow_en
= (1 << 11), // 8168 8101
467 Force_txflow_en
= (1 << 10), // 8168 8101
468 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
469 ASF
= (1 << 8), // 8168 8101
470 PktCntrDisable
= (1 << 7), // 8168 8101
471 Mac_dbgo_sel
= 0x001c, // 8168
476 INTT_0
= 0x0000, // 8168
477 INTT_1
= 0x0001, // 8168
478 INTT_2
= 0x0002, // 8168
479 INTT_3
= 0x0003, // 8168
481 /* rtl8169_PHYstatus */
492 TBILinkOK
= 0x02000000,
494 /* DumpCounterCommand */
499 /* First doubleword. */
500 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
501 RingEnd
= (1 << 30), /* End of descriptor ring */
502 FirstFrag
= (1 << 29), /* First segment of a packet */
503 LastFrag
= (1 << 28), /* Final segment of a packet */
507 enum rtl_tx_desc_bit
{
508 /* First doubleword. */
509 TD_LSO
= (1 << 27), /* Large Send Offload */
510 #define TD_MSS_MAX 0x07ffu /* MSS value */
512 /* Second doubleword. */
513 TxVlanTag
= (1 << 17), /* Add VLAN tag */
516 /* 8169, 8168b and 810x except 8102e. */
517 enum rtl_tx_desc_bit_0
{
518 /* First doubleword. */
519 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
520 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
521 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
522 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
525 /* 8102e, 8168c and beyond. */
526 enum rtl_tx_desc_bit_1
{
527 /* Second doubleword. */
528 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
529 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
530 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
531 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
534 static const struct rtl_tx_desc_info
{
541 } tx_desc_info
[] = {
544 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
545 .tcp
= TD0_IP_CS
| TD0_TCP_CS
547 .mss_shift
= TD0_MSS_SHIFT
,
552 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
553 .tcp
= TD1_IP_CS
| TD1_TCP_CS
555 .mss_shift
= TD1_MSS_SHIFT
,
560 enum rtl_rx_desc_bit
{
562 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
563 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
565 #define RxProtoUDP (PID1)
566 #define RxProtoTCP (PID0)
567 #define RxProtoIP (PID1 | PID0)
568 #define RxProtoMask RxProtoIP
570 IPFail
= (1 << 16), /* IP checksum failed */
571 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
572 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
573 RxVlanTag
= (1 << 16), /* VLAN tag available */
576 #define RsvdMask 0x3fffc000
593 u8 __pad
[sizeof(void *) - sizeof(u32
)];
597 RTL_FEATURE_WOL
= (1 << 0),
598 RTL_FEATURE_MSI
= (1 << 1),
599 RTL_FEATURE_GMII
= (1 << 2),
602 struct rtl8169_counters
{
609 __le32 tx_one_collision
;
610 __le32 tx_multi_collision
;
618 struct rtl8169_private
{
619 void __iomem
*mmio_addr
; /* memory map physical address */
620 struct pci_dev
*pci_dev
;
621 struct net_device
*dev
;
622 struct napi_struct napi
;
627 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
628 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
631 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
632 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
633 dma_addr_t TxPhyAddr
;
634 dma_addr_t RxPhyAddr
;
635 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
636 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
637 struct timer_list timer
;
644 void (*write
)(void __iomem
*, int, int);
645 int (*read
)(void __iomem
*, int);
648 struct pll_power_ops
{
649 void (*down
)(struct rtl8169_private
*);
650 void (*up
)(struct rtl8169_private
*);
653 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
654 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
655 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
656 void (*hw_start
)(struct net_device
*);
657 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
658 unsigned int (*link_ok
)(void __iomem
*);
659 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
661 struct delayed_work task
;
664 struct mii_if_info mii
;
665 struct rtl8169_counters counters
;
668 const struct firmware
*fw
;
669 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
672 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
673 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
674 module_param(use_dac
, int, 0);
675 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
676 module_param_named(debug
, debug
.msg_enable
, int, 0);
677 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
678 MODULE_LICENSE("GPL");
679 MODULE_VERSION(RTL8169_VERSION
);
680 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
681 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
682 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
683 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
684 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
686 static int rtl8169_open(struct net_device
*dev
);
687 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
688 struct net_device
*dev
);
689 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
690 static int rtl8169_init_ring(struct net_device
*dev
);
691 static void rtl_hw_start(struct net_device
*dev
);
692 static int rtl8169_close(struct net_device
*dev
);
693 static void rtl_set_rx_mode(struct net_device
*dev
);
694 static void rtl8169_tx_timeout(struct net_device
*dev
);
695 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
696 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
697 void __iomem
*, u32 budget
);
698 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
699 static void rtl8169_down(struct net_device
*dev
);
700 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
701 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
703 static const unsigned int rtl8169_rx_config
=
704 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
706 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
708 void __iomem
*ioaddr
= tp
->mmio_addr
;
711 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
712 for (i
= 0; i
< 20; i
++) {
714 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
717 return RTL_R32(OCPDR
);
720 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
722 void __iomem
*ioaddr
= tp
->mmio_addr
;
725 RTL_W32(OCPDR
, data
);
726 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
727 for (i
= 0; i
< 20; i
++) {
729 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
734 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
736 void __iomem
*ioaddr
= tp
->mmio_addr
;
740 RTL_W32(ERIAR
, 0x800010e8);
742 for (i
= 0; i
< 5; i
++) {
744 if (!(RTL_R32(ERIDR
) & ERIAR_FLAG
))
748 ocp_write(tp
, 0x1, 0x30, 0x00000001);
751 #define OOB_CMD_RESET 0x00
752 #define OOB_CMD_DRIVER_START 0x05
753 #define OOB_CMD_DRIVER_STOP 0x06
755 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
757 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
760 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
765 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
767 reg
= rtl8168_get_ocp_reg(tp
);
769 for (i
= 0; i
< 10; i
++) {
771 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
776 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
781 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
783 reg
= rtl8168_get_ocp_reg(tp
);
785 for (i
= 0; i
< 10; i
++) {
787 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
792 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
794 u16 reg
= rtl8168_get_ocp_reg(tp
);
796 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
799 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
803 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
805 for (i
= 20; i
> 0; i
--) {
807 * Check if the RTL8169 has completed writing to the specified
810 if (!(RTL_R32(PHYAR
) & 0x80000000))
815 * According to hardware specs a 20us delay is required after write
816 * complete indication, but before sending next command.
821 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
825 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
827 for (i
= 20; i
> 0; i
--) {
829 * Check if the RTL8169 has completed retrieving data from
830 * the specified MII register.
832 if (RTL_R32(PHYAR
) & 0x80000000) {
833 value
= RTL_R32(PHYAR
) & 0xffff;
839 * According to hardware specs a 20us delay is required after read
840 * complete indication, but before sending next command.
847 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
851 RTL_W32(OCPDR
, data
|
852 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
853 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
854 RTL_W32(EPHY_RXER_NUM
, 0);
856 for (i
= 0; i
< 100; i
++) {
858 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
863 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
865 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
866 (value
& OCPDR_DATA_MASK
));
869 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
873 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
876 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
877 RTL_W32(EPHY_RXER_NUM
, 0);
879 for (i
= 0; i
< 100; i
++) {
881 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
885 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
888 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
890 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
892 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
895 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
897 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
900 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
902 r8168dp_2_mdio_start(ioaddr
);
904 r8169_mdio_write(ioaddr
, reg_addr
, value
);
906 r8168dp_2_mdio_stop(ioaddr
);
909 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
913 r8168dp_2_mdio_start(ioaddr
);
915 value
= r8169_mdio_read(ioaddr
, reg_addr
);
917 r8168dp_2_mdio_stop(ioaddr
);
922 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
924 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
927 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
929 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
932 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
934 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
937 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
941 val
= rtl_readphy(tp
, reg_addr
);
942 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
945 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
948 struct rtl8169_private
*tp
= netdev_priv(dev
);
950 rtl_writephy(tp
, location
, val
);
953 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
955 struct rtl8169_private
*tp
= netdev_priv(dev
);
957 return rtl_readphy(tp
, location
);
960 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
964 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
965 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
967 for (i
= 0; i
< 100; i
++) {
968 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
974 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
979 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
981 for (i
= 0; i
< 100; i
++) {
982 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
983 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
992 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
996 RTL_W32(CSIDR
, value
);
997 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
998 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1000 for (i
= 0; i
< 100; i
++) {
1001 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
1007 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
1012 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1013 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1015 for (i
= 0; i
< 100; i
++) {
1016 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1017 value
= RTL_R32(CSIDR
);
1026 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1031 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1033 for (i
= 0; i
< 300; i
++) {
1034 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1035 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1044 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
1046 RTL_W16(IntrMask
, 0x0000);
1048 RTL_W16(IntrStatus
, 0xffff);
1051 static void rtl8169_asic_down(void __iomem
*ioaddr
)
1053 RTL_W8(ChipCmd
, 0x00);
1054 rtl8169_irq_mask_and_ack(ioaddr
);
1058 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1060 void __iomem
*ioaddr
= tp
->mmio_addr
;
1062 return RTL_R32(TBICSR
) & TBIReset
;
1065 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1067 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1070 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1072 return RTL_R32(TBICSR
) & TBILinkOk
;
1075 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1077 return RTL_R8(PHYstatus
) & LinkStatus
;
1080 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1082 void __iomem
*ioaddr
= tp
->mmio_addr
;
1084 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1087 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1091 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1092 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1095 static void __rtl8169_check_link_status(struct net_device
*dev
,
1096 struct rtl8169_private
*tp
,
1097 void __iomem
*ioaddr
, bool pm
)
1099 unsigned long flags
;
1101 spin_lock_irqsave(&tp
->lock
, flags
);
1102 if (tp
->link_ok(ioaddr
)) {
1103 /* This is to cancel a scheduled suspend if there's one. */
1105 pm_request_resume(&tp
->pci_dev
->dev
);
1106 netif_carrier_on(dev
);
1107 if (net_ratelimit())
1108 netif_info(tp
, ifup
, dev
, "link up\n");
1110 netif_carrier_off(dev
);
1111 netif_info(tp
, ifdown
, dev
, "link down\n");
1113 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
1115 spin_unlock_irqrestore(&tp
->lock
, flags
);
1118 static void rtl8169_check_link_status(struct net_device
*dev
,
1119 struct rtl8169_private
*tp
,
1120 void __iomem
*ioaddr
)
1122 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1125 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1127 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1129 void __iomem
*ioaddr
= tp
->mmio_addr
;
1133 options
= RTL_R8(Config1
);
1134 if (!(options
& PMEnable
))
1137 options
= RTL_R8(Config3
);
1138 if (options
& LinkUp
)
1139 wolopts
|= WAKE_PHY
;
1140 if (options
& MagicPacket
)
1141 wolopts
|= WAKE_MAGIC
;
1143 options
= RTL_R8(Config5
);
1145 wolopts
|= WAKE_UCAST
;
1147 wolopts
|= WAKE_BCAST
;
1149 wolopts
|= WAKE_MCAST
;
1154 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1156 struct rtl8169_private
*tp
= netdev_priv(dev
);
1158 spin_lock_irq(&tp
->lock
);
1160 wol
->supported
= WAKE_ANY
;
1161 wol
->wolopts
= __rtl8169_get_wol(tp
);
1163 spin_unlock_irq(&tp
->lock
);
1166 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1168 void __iomem
*ioaddr
= tp
->mmio_addr
;
1170 static const struct {
1175 { WAKE_ANY
, Config1
, PMEnable
},
1176 { WAKE_PHY
, Config3
, LinkUp
},
1177 { WAKE_MAGIC
, Config3
, MagicPacket
},
1178 { WAKE_UCAST
, Config5
, UWF
},
1179 { WAKE_BCAST
, Config5
, BWF
},
1180 { WAKE_MCAST
, Config5
, MWF
},
1181 { WAKE_ANY
, Config5
, LanWake
}
1184 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1186 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1187 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1188 if (wolopts
& cfg
[i
].opt
)
1189 options
|= cfg
[i
].mask
;
1190 RTL_W8(cfg
[i
].reg
, options
);
1193 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1196 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1198 struct rtl8169_private
*tp
= netdev_priv(dev
);
1200 spin_lock_irq(&tp
->lock
);
1203 tp
->features
|= RTL_FEATURE_WOL
;
1205 tp
->features
&= ~RTL_FEATURE_WOL
;
1206 __rtl8169_set_wol(tp
, wol
->wolopts
);
1207 spin_unlock_irq(&tp
->lock
);
1209 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1214 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1216 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1219 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1220 struct ethtool_drvinfo
*info
)
1222 struct rtl8169_private
*tp
= netdev_priv(dev
);
1224 strcpy(info
->driver
, MODULENAME
);
1225 strcpy(info
->version
, RTL8169_VERSION
);
1226 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
1227 strncpy(info
->fw_version
, IS_ERR_OR_NULL(tp
->fw
) ? "N/A" :
1228 rtl_lookup_firmware_name(tp
), sizeof(info
->fw_version
) - 1);
1231 static int rtl8169_get_regs_len(struct net_device
*dev
)
1233 return R8169_REGS_SIZE
;
1236 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1237 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1239 struct rtl8169_private
*tp
= netdev_priv(dev
);
1240 void __iomem
*ioaddr
= tp
->mmio_addr
;
1244 reg
= RTL_R32(TBICSR
);
1245 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1246 (duplex
== DUPLEX_FULL
)) {
1247 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1248 } else if (autoneg
== AUTONEG_ENABLE
)
1249 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1251 netif_warn(tp
, link
, dev
,
1252 "incorrect speed setting refused in TBI mode\n");
1259 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1260 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1262 struct rtl8169_private
*tp
= netdev_priv(dev
);
1263 int giga_ctrl
, bmcr
;
1266 rtl_writephy(tp
, 0x1f, 0x0000);
1268 if (autoneg
== AUTONEG_ENABLE
) {
1271 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1272 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1273 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1275 if (adv
& ADVERTISED_10baseT_Half
)
1276 auto_nego
|= ADVERTISE_10HALF
;
1277 if (adv
& ADVERTISED_10baseT_Full
)
1278 auto_nego
|= ADVERTISE_10FULL
;
1279 if (adv
& ADVERTISED_100baseT_Half
)
1280 auto_nego
|= ADVERTISE_100HALF
;
1281 if (adv
& ADVERTISED_100baseT_Full
)
1282 auto_nego
|= ADVERTISE_100FULL
;
1284 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1286 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1287 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1289 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1290 if (tp
->mii
.supports_gmii
) {
1291 if (adv
& ADVERTISED_1000baseT_Half
)
1292 giga_ctrl
|= ADVERTISE_1000HALF
;
1293 if (adv
& ADVERTISED_1000baseT_Full
)
1294 giga_ctrl
|= ADVERTISE_1000FULL
;
1295 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1296 ADVERTISED_1000baseT_Full
)) {
1297 netif_info(tp
, link
, dev
,
1298 "PHY does not support 1000Mbps\n");
1302 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1304 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1305 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1309 if (speed
== SPEED_10
)
1311 else if (speed
== SPEED_100
)
1312 bmcr
= BMCR_SPEED100
;
1316 if (duplex
== DUPLEX_FULL
)
1317 bmcr
|= BMCR_FULLDPLX
;
1320 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1322 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1323 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1324 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1325 rtl_writephy(tp
, 0x17, 0x2138);
1326 rtl_writephy(tp
, 0x0e, 0x0260);
1328 rtl_writephy(tp
, 0x17, 0x2108);
1329 rtl_writephy(tp
, 0x0e, 0x0000);
1338 static int rtl8169_set_speed(struct net_device
*dev
,
1339 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1341 struct rtl8169_private
*tp
= netdev_priv(dev
);
1344 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1348 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1349 (advertising
& ADVERTISED_1000baseT_Full
)) {
1350 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1356 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1358 struct rtl8169_private
*tp
= netdev_priv(dev
);
1359 unsigned long flags
;
1362 del_timer_sync(&tp
->timer
);
1364 spin_lock_irqsave(&tp
->lock
, flags
);
1365 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1366 cmd
->duplex
, cmd
->advertising
);
1367 spin_unlock_irqrestore(&tp
->lock
, flags
);
1372 static u32
rtl8169_fix_features(struct net_device
*dev
, u32 features
)
1374 if (dev
->mtu
> TD_MSS_MAX
)
1375 features
&= ~NETIF_F_ALL_TSO
;
1380 static int rtl8169_set_features(struct net_device
*dev
, u32 features
)
1382 struct rtl8169_private
*tp
= netdev_priv(dev
);
1383 void __iomem
*ioaddr
= tp
->mmio_addr
;
1384 unsigned long flags
;
1386 spin_lock_irqsave(&tp
->lock
, flags
);
1388 if (features
& NETIF_F_RXCSUM
)
1389 tp
->cp_cmd
|= RxChkSum
;
1391 tp
->cp_cmd
&= ~RxChkSum
;
1393 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1394 tp
->cp_cmd
|= RxVlan
;
1396 tp
->cp_cmd
&= ~RxVlan
;
1398 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1401 spin_unlock_irqrestore(&tp
->lock
, flags
);
1406 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1407 struct sk_buff
*skb
)
1409 return (vlan_tx_tag_present(skb
)) ?
1410 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1413 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1415 u32 opts2
= le32_to_cpu(desc
->opts2
);
1417 if (opts2
& RxVlanTag
)
1418 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1423 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1425 struct rtl8169_private
*tp
= netdev_priv(dev
);
1426 void __iomem
*ioaddr
= tp
->mmio_addr
;
1430 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1431 cmd
->port
= PORT_FIBRE
;
1432 cmd
->transceiver
= XCVR_INTERNAL
;
1434 status
= RTL_R32(TBICSR
);
1435 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1436 cmd
->autoneg
= !!(status
& TBINwEnable
);
1438 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1439 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1444 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1446 struct rtl8169_private
*tp
= netdev_priv(dev
);
1448 return mii_ethtool_gset(&tp
->mii
, cmd
);
1451 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1453 struct rtl8169_private
*tp
= netdev_priv(dev
);
1454 unsigned long flags
;
1457 spin_lock_irqsave(&tp
->lock
, flags
);
1459 rc
= tp
->get_settings(dev
, cmd
);
1461 spin_unlock_irqrestore(&tp
->lock
, flags
);
1465 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1468 struct rtl8169_private
*tp
= netdev_priv(dev
);
1469 unsigned long flags
;
1471 if (regs
->len
> R8169_REGS_SIZE
)
1472 regs
->len
= R8169_REGS_SIZE
;
1474 spin_lock_irqsave(&tp
->lock
, flags
);
1475 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1476 spin_unlock_irqrestore(&tp
->lock
, flags
);
1479 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1481 struct rtl8169_private
*tp
= netdev_priv(dev
);
1483 return tp
->msg_enable
;
1486 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1488 struct rtl8169_private
*tp
= netdev_priv(dev
);
1490 tp
->msg_enable
= value
;
1493 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1500 "tx_single_collisions",
1501 "tx_multi_collisions",
1509 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1513 return ARRAY_SIZE(rtl8169_gstrings
);
1519 static void rtl8169_update_counters(struct net_device
*dev
)
1521 struct rtl8169_private
*tp
= netdev_priv(dev
);
1522 void __iomem
*ioaddr
= tp
->mmio_addr
;
1523 struct device
*d
= &tp
->pci_dev
->dev
;
1524 struct rtl8169_counters
*counters
;
1530 * Some chips are unable to dump tally counters when the receiver
1533 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1536 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1540 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1541 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1542 RTL_W32(CounterAddrLow
, cmd
);
1543 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1546 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1547 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1553 RTL_W32(CounterAddrLow
, 0);
1554 RTL_W32(CounterAddrHigh
, 0);
1556 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1559 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1560 struct ethtool_stats
*stats
, u64
*data
)
1562 struct rtl8169_private
*tp
= netdev_priv(dev
);
1566 rtl8169_update_counters(dev
);
1568 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1569 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1570 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1571 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1572 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1573 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1574 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1575 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1576 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1577 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1578 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1579 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1580 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1583 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1587 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1592 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1593 .get_drvinfo
= rtl8169_get_drvinfo
,
1594 .get_regs_len
= rtl8169_get_regs_len
,
1595 .get_link
= ethtool_op_get_link
,
1596 .get_settings
= rtl8169_get_settings
,
1597 .set_settings
= rtl8169_set_settings
,
1598 .get_msglevel
= rtl8169_get_msglevel
,
1599 .set_msglevel
= rtl8169_set_msglevel
,
1600 .get_regs
= rtl8169_get_regs
,
1601 .get_wol
= rtl8169_get_wol
,
1602 .set_wol
= rtl8169_set_wol
,
1603 .get_strings
= rtl8169_get_strings
,
1604 .get_sset_count
= rtl8169_get_sset_count
,
1605 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1608 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1609 struct net_device
*dev
, u8 default_version
)
1611 void __iomem
*ioaddr
= tp
->mmio_addr
;
1613 * The driver currently handles the 8168Bf and the 8168Be identically
1614 * but they can be identified more specifically through the test below
1617 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1619 * Same thing for the 8101Eb and the 8101Ec:
1621 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1623 static const struct {
1629 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1630 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1631 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1634 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1635 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1636 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1638 /* 8168DP family. */
1639 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1640 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1641 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1644 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1645 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1646 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1647 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1648 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1649 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1650 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1651 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1652 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1655 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1656 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1657 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1658 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1661 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1662 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1663 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1664 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1665 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1666 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1667 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1668 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1669 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1670 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1671 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1672 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1673 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1674 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1675 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1676 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1677 /* FIXME: where did these entries come from ? -- FR */
1678 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1679 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1682 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1683 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1684 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1685 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1686 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1687 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1690 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1694 reg
= RTL_R32(TxConfig
);
1695 while ((reg
& p
->mask
) != p
->val
)
1697 tp
->mac_version
= p
->mac_version
;
1699 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1700 netif_notice(tp
, probe
, dev
,
1701 "unknown MAC, using family default\n");
1702 tp
->mac_version
= default_version
;
1706 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1708 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1716 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1717 const struct phy_reg
*regs
, int len
)
1720 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1725 #define PHY_READ 0x00000000
1726 #define PHY_DATA_OR 0x10000000
1727 #define PHY_DATA_AND 0x20000000
1728 #define PHY_BJMPN 0x30000000
1729 #define PHY_READ_EFUSE 0x40000000
1730 #define PHY_READ_MAC_BYTE 0x50000000
1731 #define PHY_WRITE_MAC_BYTE 0x60000000
1732 #define PHY_CLEAR_READCOUNT 0x70000000
1733 #define PHY_WRITE 0x80000000
1734 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1735 #define PHY_COMP_EQ_SKIPN 0xa0000000
1736 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1737 #define PHY_WRITE_PREVIOUS 0xc0000000
1738 #define PHY_SKIPN 0xd0000000
1739 #define PHY_DELAY_MS 0xe0000000
1740 #define PHY_WRITE_ERI_WORD 0xf0000000
1743 rtl_phy_write_fw(struct rtl8169_private
*tp
, const struct firmware
*fw
)
1745 __le32
*phytable
= (__le32
*)fw
->data
;
1746 struct net_device
*dev
= tp
->dev
;
1747 size_t index
, fw_size
= fw
->size
/ sizeof(*phytable
);
1750 if (fw
->size
% sizeof(*phytable
)) {
1751 netif_err(tp
, probe
, dev
, "odd sized firmware %zd\n", fw
->size
);
1755 for (index
= 0; index
< fw_size
; index
++) {
1756 u32 action
= le32_to_cpu(phytable
[index
]);
1757 u32 regno
= (action
& 0x0fff0000) >> 16;
1759 switch(action
& 0xf0000000) {
1763 case PHY_READ_EFUSE
:
1764 case PHY_CLEAR_READCOUNT
:
1766 case PHY_WRITE_PREVIOUS
:
1771 if (regno
> index
) {
1772 netif_err(tp
, probe
, tp
->dev
,
1773 "Out of range of firmware\n");
1777 case PHY_READCOUNT_EQ_SKIP
:
1778 if (index
+ 2 >= fw_size
) {
1779 netif_err(tp
, probe
, tp
->dev
,
1780 "Out of range of firmware\n");
1784 case PHY_COMP_EQ_SKIPN
:
1785 case PHY_COMP_NEQ_SKIPN
:
1787 if (index
+ 1 + regno
>= fw_size
) {
1788 netif_err(tp
, probe
, tp
->dev
,
1789 "Out of range of firmware\n");
1794 case PHY_READ_MAC_BYTE
:
1795 case PHY_WRITE_MAC_BYTE
:
1796 case PHY_WRITE_ERI_WORD
:
1798 netif_err(tp
, probe
, tp
->dev
,
1799 "Invalid action 0x%08x\n", action
);
1807 for (index
= 0; index
< fw_size
; ) {
1808 u32 action
= le32_to_cpu(phytable
[index
]);
1809 u32 data
= action
& 0x0000ffff;
1810 u32 regno
= (action
& 0x0fff0000) >> 16;
1815 switch(action
& 0xf0000000) {
1817 predata
= rtl_readphy(tp
, regno
);
1832 case PHY_READ_EFUSE
:
1833 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
1836 case PHY_CLEAR_READCOUNT
:
1841 rtl_writephy(tp
, regno
, data
);
1844 case PHY_READCOUNT_EQ_SKIP
:
1845 index
+= (count
== data
) ? 2 : 1;
1847 case PHY_COMP_EQ_SKIPN
:
1848 if (predata
== data
)
1852 case PHY_COMP_NEQ_SKIPN
:
1853 if (predata
!= data
)
1857 case PHY_WRITE_PREVIOUS
:
1858 rtl_writephy(tp
, regno
, predata
);
1869 case PHY_READ_MAC_BYTE
:
1870 case PHY_WRITE_MAC_BYTE
:
1871 case PHY_WRITE_ERI_WORD
:
1878 static void rtl_release_firmware(struct rtl8169_private
*tp
)
1880 if (!IS_ERR_OR_NULL(tp
->fw
))
1881 release_firmware(tp
->fw
);
1882 tp
->fw
= RTL_FIRMWARE_UNKNOWN
;
1885 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
1887 const struct firmware
*fw
= tp
->fw
;
1889 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1890 if (!IS_ERR_OR_NULL(fw
))
1891 rtl_phy_write_fw(tp
, fw
);
1894 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
1896 if (rtl_readphy(tp
, reg
) != val
)
1897 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
1899 rtl_apply_firmware(tp
);
1902 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
1904 static const struct phy_reg phy_reg_init
[] = {
1966 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1969 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
1971 static const struct phy_reg phy_reg_init
[] = {
1977 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1980 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
1982 struct pci_dev
*pdev
= tp
->pci_dev
;
1983 u16 vendor_id
, device_id
;
1985 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1986 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1988 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1991 rtl_writephy(tp
, 0x1f, 0x0001);
1992 rtl_writephy(tp
, 0x10, 0xf01b);
1993 rtl_writephy(tp
, 0x1f, 0x0000);
1996 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
1998 static const struct phy_reg phy_reg_init
[] = {
2038 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2040 rtl8169scd_hw_phy_config_quirk(tp
);
2043 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2045 static const struct phy_reg phy_reg_init
[] = {
2093 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2096 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2098 static const struct phy_reg phy_reg_init
[] = {
2103 rtl_writephy(tp
, 0x1f, 0x0001);
2104 rtl_patchphy(tp
, 0x16, 1 << 0);
2106 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2109 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2111 static const struct phy_reg phy_reg_init
[] = {
2117 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2120 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2122 static const struct phy_reg phy_reg_init
[] = {
2130 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2133 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2135 static const struct phy_reg phy_reg_init
[] = {
2141 rtl_writephy(tp
, 0x1f, 0x0000);
2142 rtl_patchphy(tp
, 0x14, 1 << 5);
2143 rtl_patchphy(tp
, 0x0d, 1 << 5);
2145 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2148 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2150 static const struct phy_reg phy_reg_init
[] = {
2170 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2172 rtl_patchphy(tp
, 0x14, 1 << 5);
2173 rtl_patchphy(tp
, 0x0d, 1 << 5);
2174 rtl_writephy(tp
, 0x1f, 0x0000);
2177 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2179 static const struct phy_reg phy_reg_init
[] = {
2197 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2199 rtl_patchphy(tp
, 0x16, 1 << 0);
2200 rtl_patchphy(tp
, 0x14, 1 << 5);
2201 rtl_patchphy(tp
, 0x0d, 1 << 5);
2202 rtl_writephy(tp
, 0x1f, 0x0000);
2205 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2207 static const struct phy_reg phy_reg_init
[] = {
2219 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2221 rtl_patchphy(tp
, 0x16, 1 << 0);
2222 rtl_patchphy(tp
, 0x14, 1 << 5);
2223 rtl_patchphy(tp
, 0x0d, 1 << 5);
2224 rtl_writephy(tp
, 0x1f, 0x0000);
2227 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2229 rtl8168c_3_hw_phy_config(tp
);
2232 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2234 static const struct phy_reg phy_reg_init_0
[] = {
2235 /* Channel Estimation */
2256 * Enhance line driver power
2265 * Can not link to 1Gbps with bad cable
2266 * Decrease SNR threshold form 21.07dB to 19.04dB
2274 void __iomem
*ioaddr
= tp
->mmio_addr
;
2276 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2280 * Fine Tune Switching regulator parameter
2282 rtl_writephy(tp
, 0x1f, 0x0002);
2283 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2284 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2286 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2287 static const struct phy_reg phy_reg_init
[] = {
2297 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2299 val
= rtl_readphy(tp
, 0x0d);
2301 if ((val
& 0x00ff) != 0x006c) {
2302 static const u32 set
[] = {
2303 0x0065, 0x0066, 0x0067, 0x0068,
2304 0x0069, 0x006a, 0x006b, 0x006c
2308 rtl_writephy(tp
, 0x1f, 0x0002);
2311 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2312 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2315 static const struct phy_reg phy_reg_init
[] = {
2323 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2326 /* RSET couple improve */
2327 rtl_writephy(tp
, 0x1f, 0x0002);
2328 rtl_patchphy(tp
, 0x0d, 0x0300);
2329 rtl_patchphy(tp
, 0x0f, 0x0010);
2331 /* Fine tune PLL performance */
2332 rtl_writephy(tp
, 0x1f, 0x0002);
2333 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2334 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2336 rtl_writephy(tp
, 0x1f, 0x0005);
2337 rtl_writephy(tp
, 0x05, 0x001b);
2339 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2341 rtl_writephy(tp
, 0x1f, 0x0000);
2344 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2346 static const struct phy_reg phy_reg_init_0
[] = {
2347 /* Channel Estimation */
2368 * Enhance line driver power
2377 * Can not link to 1Gbps with bad cable
2378 * Decrease SNR threshold form 21.07dB to 19.04dB
2386 void __iomem
*ioaddr
= tp
->mmio_addr
;
2388 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2390 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2391 static const struct phy_reg phy_reg_init
[] = {
2402 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2404 val
= rtl_readphy(tp
, 0x0d);
2405 if ((val
& 0x00ff) != 0x006c) {
2406 static const u32 set
[] = {
2407 0x0065, 0x0066, 0x0067, 0x0068,
2408 0x0069, 0x006a, 0x006b, 0x006c
2412 rtl_writephy(tp
, 0x1f, 0x0002);
2415 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2416 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2419 static const struct phy_reg phy_reg_init
[] = {
2427 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2430 /* Fine tune PLL performance */
2431 rtl_writephy(tp
, 0x1f, 0x0002);
2432 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2433 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2435 /* Switching regulator Slew rate */
2436 rtl_writephy(tp
, 0x1f, 0x0002);
2437 rtl_patchphy(tp
, 0x0f, 0x0017);
2439 rtl_writephy(tp
, 0x1f, 0x0005);
2440 rtl_writephy(tp
, 0x05, 0x001b);
2442 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2444 rtl_writephy(tp
, 0x1f, 0x0000);
2447 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2449 static const struct phy_reg phy_reg_init
[] = {
2505 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2508 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2510 static const struct phy_reg phy_reg_init
[] = {
2520 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2521 rtl_patchphy(tp
, 0x0d, 1 << 5);
2524 static void rtl8168e_hw_phy_config(struct rtl8169_private
*tp
)
2526 static const struct phy_reg phy_reg_init
[] = {
2527 /* Enable Delay cap */
2533 /* Channel estimation fine tune */
2542 /* Update PFM & 10M TX idle timer */
2554 rtl_apply_firmware(tp
);
2556 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2558 /* DCO enable for 10M IDLE Power */
2559 rtl_writephy(tp
, 0x1f, 0x0007);
2560 rtl_writephy(tp
, 0x1e, 0x0023);
2561 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2562 rtl_writephy(tp
, 0x1f, 0x0000);
2564 /* For impedance matching */
2565 rtl_writephy(tp
, 0x1f, 0x0002);
2566 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2567 rtl_writephy(tp
, 0x1f, 0x0000);
2569 /* PHY auto speed down */
2570 rtl_writephy(tp
, 0x1f, 0x0007);
2571 rtl_writephy(tp
, 0x1e, 0x002d);
2572 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2573 rtl_writephy(tp
, 0x1f, 0x0000);
2574 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2576 rtl_writephy(tp
, 0x1f, 0x0005);
2577 rtl_writephy(tp
, 0x05, 0x8b86);
2578 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2579 rtl_writephy(tp
, 0x1f, 0x0000);
2581 rtl_writephy(tp
, 0x1f, 0x0005);
2582 rtl_writephy(tp
, 0x05, 0x8b85);
2583 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2584 rtl_writephy(tp
, 0x1f, 0x0007);
2585 rtl_writephy(tp
, 0x1e, 0x0020);
2586 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2587 rtl_writephy(tp
, 0x1f, 0x0006);
2588 rtl_writephy(tp
, 0x00, 0x5a00);
2589 rtl_writephy(tp
, 0x1f, 0x0000);
2590 rtl_writephy(tp
, 0x0d, 0x0007);
2591 rtl_writephy(tp
, 0x0e, 0x003c);
2592 rtl_writephy(tp
, 0x0d, 0x4007);
2593 rtl_writephy(tp
, 0x0e, 0x0000);
2594 rtl_writephy(tp
, 0x0d, 0x0000);
2597 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
2599 static const struct phy_reg phy_reg_init
[] = {
2606 rtl_writephy(tp
, 0x1f, 0x0000);
2607 rtl_patchphy(tp
, 0x11, 1 << 12);
2608 rtl_patchphy(tp
, 0x19, 1 << 13);
2609 rtl_patchphy(tp
, 0x10, 1 << 15);
2611 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2614 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
2616 static const struct phy_reg phy_reg_init
[] = {
2630 /* Disable ALDPS before ram code */
2631 rtl_writephy(tp
, 0x1f, 0x0000);
2632 rtl_writephy(tp
, 0x18, 0x0310);
2635 rtl_apply_firmware(tp
);
2637 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2640 static void rtl_hw_phy_config(struct net_device
*dev
)
2642 struct rtl8169_private
*tp
= netdev_priv(dev
);
2644 rtl8169_print_mac_version(tp
);
2646 switch (tp
->mac_version
) {
2647 case RTL_GIGA_MAC_VER_01
:
2649 case RTL_GIGA_MAC_VER_02
:
2650 case RTL_GIGA_MAC_VER_03
:
2651 rtl8169s_hw_phy_config(tp
);
2653 case RTL_GIGA_MAC_VER_04
:
2654 rtl8169sb_hw_phy_config(tp
);
2656 case RTL_GIGA_MAC_VER_05
:
2657 rtl8169scd_hw_phy_config(tp
);
2659 case RTL_GIGA_MAC_VER_06
:
2660 rtl8169sce_hw_phy_config(tp
);
2662 case RTL_GIGA_MAC_VER_07
:
2663 case RTL_GIGA_MAC_VER_08
:
2664 case RTL_GIGA_MAC_VER_09
:
2665 rtl8102e_hw_phy_config(tp
);
2667 case RTL_GIGA_MAC_VER_11
:
2668 rtl8168bb_hw_phy_config(tp
);
2670 case RTL_GIGA_MAC_VER_12
:
2671 rtl8168bef_hw_phy_config(tp
);
2673 case RTL_GIGA_MAC_VER_17
:
2674 rtl8168bef_hw_phy_config(tp
);
2676 case RTL_GIGA_MAC_VER_18
:
2677 rtl8168cp_1_hw_phy_config(tp
);
2679 case RTL_GIGA_MAC_VER_19
:
2680 rtl8168c_1_hw_phy_config(tp
);
2682 case RTL_GIGA_MAC_VER_20
:
2683 rtl8168c_2_hw_phy_config(tp
);
2685 case RTL_GIGA_MAC_VER_21
:
2686 rtl8168c_3_hw_phy_config(tp
);
2688 case RTL_GIGA_MAC_VER_22
:
2689 rtl8168c_4_hw_phy_config(tp
);
2691 case RTL_GIGA_MAC_VER_23
:
2692 case RTL_GIGA_MAC_VER_24
:
2693 rtl8168cp_2_hw_phy_config(tp
);
2695 case RTL_GIGA_MAC_VER_25
:
2696 rtl8168d_1_hw_phy_config(tp
);
2698 case RTL_GIGA_MAC_VER_26
:
2699 rtl8168d_2_hw_phy_config(tp
);
2701 case RTL_GIGA_MAC_VER_27
:
2702 rtl8168d_3_hw_phy_config(tp
);
2704 case RTL_GIGA_MAC_VER_28
:
2705 rtl8168d_4_hw_phy_config(tp
);
2707 case RTL_GIGA_MAC_VER_29
:
2708 case RTL_GIGA_MAC_VER_30
:
2709 rtl8105e_hw_phy_config(tp
);
2711 case RTL_GIGA_MAC_VER_31
:
2714 case RTL_GIGA_MAC_VER_32
:
2715 case RTL_GIGA_MAC_VER_33
:
2716 rtl8168e_hw_phy_config(tp
);
2724 static void rtl8169_phy_timer(unsigned long __opaque
)
2726 struct net_device
*dev
= (struct net_device
*)__opaque
;
2727 struct rtl8169_private
*tp
= netdev_priv(dev
);
2728 struct timer_list
*timer
= &tp
->timer
;
2729 void __iomem
*ioaddr
= tp
->mmio_addr
;
2730 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2732 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2734 spin_lock_irq(&tp
->lock
);
2736 if (tp
->phy_reset_pending(tp
)) {
2738 * A busy loop could burn quite a few cycles on nowadays CPU.
2739 * Let's delay the execution of the timer for a few ticks.
2745 if (tp
->link_ok(ioaddr
))
2748 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
2750 tp
->phy_reset_enable(tp
);
2753 mod_timer(timer
, jiffies
+ timeout
);
2755 spin_unlock_irq(&tp
->lock
);
2758 #ifdef CONFIG_NET_POLL_CONTROLLER
2760 * Polling 'interrupt' - used by things like netconsole to send skbs
2761 * without having to re-enable interrupts. It's not called while
2762 * the interrupt routine is executing.
2764 static void rtl8169_netpoll(struct net_device
*dev
)
2766 struct rtl8169_private
*tp
= netdev_priv(dev
);
2767 struct pci_dev
*pdev
= tp
->pci_dev
;
2769 disable_irq(pdev
->irq
);
2770 rtl8169_interrupt(pdev
->irq
, dev
);
2771 enable_irq(pdev
->irq
);
2775 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2776 void __iomem
*ioaddr
)
2779 pci_release_regions(pdev
);
2780 pci_clear_mwi(pdev
);
2781 pci_disable_device(pdev
);
2785 static void rtl8169_phy_reset(struct net_device
*dev
,
2786 struct rtl8169_private
*tp
)
2790 tp
->phy_reset_enable(tp
);
2791 for (i
= 0; i
< 100; i
++) {
2792 if (!tp
->phy_reset_pending(tp
))
2796 netif_err(tp
, link
, dev
, "PHY reset failed\n");
2799 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2801 void __iomem
*ioaddr
= tp
->mmio_addr
;
2803 rtl_hw_phy_config(dev
);
2805 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2806 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2810 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2812 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2813 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2815 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2816 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2818 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2819 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
2822 rtl8169_phy_reset(dev
, tp
);
2824 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
2825 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
2826 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
2827 (tp
->mii
.supports_gmii
?
2828 ADVERTISED_1000baseT_Half
|
2829 ADVERTISED_1000baseT_Full
: 0));
2831 if (RTL_R8(PHYstatus
) & TBI_Enable
)
2832 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
2835 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2837 void __iomem
*ioaddr
= tp
->mmio_addr
;
2841 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2842 high
= addr
[4] | (addr
[5] << 8);
2844 spin_lock_irq(&tp
->lock
);
2846 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2848 RTL_W32(MAC4
, high
);
2854 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2856 spin_unlock_irq(&tp
->lock
);
2859 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2861 struct rtl8169_private
*tp
= netdev_priv(dev
);
2862 struct sockaddr
*addr
= p
;
2864 if (!is_valid_ether_addr(addr
->sa_data
))
2865 return -EADDRNOTAVAIL
;
2867 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2869 rtl_rar_set(tp
, dev
->dev_addr
);
2874 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2876 struct rtl8169_private
*tp
= netdev_priv(dev
);
2877 struct mii_ioctl_data
*data
= if_mii(ifr
);
2879 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2882 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
2883 struct mii_ioctl_data
*data
, int cmd
)
2887 data
->phy_id
= 32; /* Internal PHY */
2891 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
2895 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
2901 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2906 static const struct rtl_cfg_info
{
2907 void (*hw_start
)(struct net_device
*);
2908 unsigned int region
;
2914 } rtl_cfg_infos
[] = {
2916 .hw_start
= rtl_hw_start_8169
,
2919 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2920 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2921 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2922 .features
= RTL_FEATURE_GMII
,
2923 .default_ver
= RTL_GIGA_MAC_VER_01
,
2926 .hw_start
= rtl_hw_start_8168
,
2929 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2930 TxErr
| TxOK
| RxOK
| RxErr
,
2931 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2932 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2933 .default_ver
= RTL_GIGA_MAC_VER_11
,
2936 .hw_start
= rtl_hw_start_8101
,
2939 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2940 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2941 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2942 .features
= RTL_FEATURE_MSI
,
2943 .default_ver
= RTL_GIGA_MAC_VER_13
,
2947 /* Cfg9346_Unlock assumed. */
2948 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2949 const struct rtl_cfg_info
*cfg
)
2954 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2955 if (cfg
->features
& RTL_FEATURE_MSI
) {
2956 if (pci_enable_msi(pdev
)) {
2957 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2960 msi
= RTL_FEATURE_MSI
;
2963 RTL_W8(Config2
, cfg2
);
2967 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2969 if (tp
->features
& RTL_FEATURE_MSI
) {
2970 pci_disable_msi(pdev
);
2971 tp
->features
&= ~RTL_FEATURE_MSI
;
2975 static const struct net_device_ops rtl8169_netdev_ops
= {
2976 .ndo_open
= rtl8169_open
,
2977 .ndo_stop
= rtl8169_close
,
2978 .ndo_get_stats
= rtl8169_get_stats
,
2979 .ndo_start_xmit
= rtl8169_start_xmit
,
2980 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2981 .ndo_validate_addr
= eth_validate_addr
,
2982 .ndo_change_mtu
= rtl8169_change_mtu
,
2983 .ndo_fix_features
= rtl8169_fix_features
,
2984 .ndo_set_features
= rtl8169_set_features
,
2985 .ndo_set_mac_address
= rtl_set_mac_address
,
2986 .ndo_do_ioctl
= rtl8169_ioctl
,
2987 .ndo_set_multicast_list
= rtl_set_rx_mode
,
2988 #ifdef CONFIG_NET_POLL_CONTROLLER
2989 .ndo_poll_controller
= rtl8169_netpoll
,
2994 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
2996 struct mdio_ops
*ops
= &tp
->mdio_ops
;
2998 switch (tp
->mac_version
) {
2999 case RTL_GIGA_MAC_VER_27
:
3000 ops
->write
= r8168dp_1_mdio_write
;
3001 ops
->read
= r8168dp_1_mdio_read
;
3003 case RTL_GIGA_MAC_VER_28
:
3004 case RTL_GIGA_MAC_VER_31
:
3005 ops
->write
= r8168dp_2_mdio_write
;
3006 ops
->read
= r8168dp_2_mdio_read
;
3009 ops
->write
= r8169_mdio_write
;
3010 ops
->read
= r8169_mdio_read
;
3015 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3017 rtl_writephy(tp
, 0x1f, 0x0000);
3018 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3021 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3023 rtl_writephy(tp
, 0x1f, 0x0000);
3024 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3027 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3029 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3030 rtl_writephy(tp
, 0x1f, 0x0000);
3031 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3035 r810x_phy_power_down(tp
);
3038 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3040 r810x_phy_power_up(tp
);
3043 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3045 rtl_writephy(tp
, 0x1f, 0x0000);
3046 switch (tp
->mac_version
) {
3047 case RTL_GIGA_MAC_VER_11
:
3048 case RTL_GIGA_MAC_VER_12
:
3049 case RTL_GIGA_MAC_VER_17
:
3050 case RTL_GIGA_MAC_VER_18
:
3051 case RTL_GIGA_MAC_VER_19
:
3052 case RTL_GIGA_MAC_VER_20
:
3053 case RTL_GIGA_MAC_VER_21
:
3054 case RTL_GIGA_MAC_VER_22
:
3055 case RTL_GIGA_MAC_VER_23
:
3056 case RTL_GIGA_MAC_VER_24
:
3057 case RTL_GIGA_MAC_VER_25
:
3058 case RTL_GIGA_MAC_VER_26
:
3059 case RTL_GIGA_MAC_VER_27
:
3060 case RTL_GIGA_MAC_VER_28
:
3061 case RTL_GIGA_MAC_VER_31
:
3062 rtl_writephy(tp
, 0x0e, 0x0000);
3067 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3070 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3072 rtl_writephy(tp
, 0x1f, 0x0000);
3073 switch (tp
->mac_version
) {
3074 case RTL_GIGA_MAC_VER_32
:
3075 case RTL_GIGA_MAC_VER_33
:
3076 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3079 case RTL_GIGA_MAC_VER_11
:
3080 case RTL_GIGA_MAC_VER_12
:
3081 case RTL_GIGA_MAC_VER_17
:
3082 case RTL_GIGA_MAC_VER_18
:
3083 case RTL_GIGA_MAC_VER_19
:
3084 case RTL_GIGA_MAC_VER_20
:
3085 case RTL_GIGA_MAC_VER_21
:
3086 case RTL_GIGA_MAC_VER_22
:
3087 case RTL_GIGA_MAC_VER_23
:
3088 case RTL_GIGA_MAC_VER_24
:
3089 case RTL_GIGA_MAC_VER_25
:
3090 case RTL_GIGA_MAC_VER_26
:
3091 case RTL_GIGA_MAC_VER_27
:
3092 case RTL_GIGA_MAC_VER_28
:
3093 case RTL_GIGA_MAC_VER_31
:
3094 rtl_writephy(tp
, 0x0e, 0x0200);
3096 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3101 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3103 void __iomem
*ioaddr
= tp
->mmio_addr
;
3105 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3106 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3107 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3108 r8168dp_check_dash(tp
)) {
3112 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3113 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3114 (RTL_R16(CPlusCmd
) & ASF
)) {
3118 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3119 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3120 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3122 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3123 rtl_writephy(tp
, 0x1f, 0x0000);
3124 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3126 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
3127 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
3131 r8168_phy_power_down(tp
);
3133 switch (tp
->mac_version
) {
3134 case RTL_GIGA_MAC_VER_25
:
3135 case RTL_GIGA_MAC_VER_26
:
3136 case RTL_GIGA_MAC_VER_27
:
3137 case RTL_GIGA_MAC_VER_28
:
3138 case RTL_GIGA_MAC_VER_31
:
3139 case RTL_GIGA_MAC_VER_32
:
3140 case RTL_GIGA_MAC_VER_33
:
3141 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3146 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3148 void __iomem
*ioaddr
= tp
->mmio_addr
;
3150 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3151 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3152 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3153 r8168dp_check_dash(tp
)) {
3157 switch (tp
->mac_version
) {
3158 case RTL_GIGA_MAC_VER_25
:
3159 case RTL_GIGA_MAC_VER_26
:
3160 case RTL_GIGA_MAC_VER_27
:
3161 case RTL_GIGA_MAC_VER_28
:
3162 case RTL_GIGA_MAC_VER_31
:
3163 case RTL_GIGA_MAC_VER_32
:
3164 case RTL_GIGA_MAC_VER_33
:
3165 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3169 r8168_phy_power_up(tp
);
3172 static void rtl_pll_power_op(struct rtl8169_private
*tp
,
3173 void (*op
)(struct rtl8169_private
*))
3179 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3181 rtl_pll_power_op(tp
, tp
->pll_power_ops
.down
);
3184 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3186 rtl_pll_power_op(tp
, tp
->pll_power_ops
.up
);
3189 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3191 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3193 switch (tp
->mac_version
) {
3194 case RTL_GIGA_MAC_VER_07
:
3195 case RTL_GIGA_MAC_VER_08
:
3196 case RTL_GIGA_MAC_VER_09
:
3197 case RTL_GIGA_MAC_VER_10
:
3198 case RTL_GIGA_MAC_VER_16
:
3199 case RTL_GIGA_MAC_VER_29
:
3200 case RTL_GIGA_MAC_VER_30
:
3201 ops
->down
= r810x_pll_power_down
;
3202 ops
->up
= r810x_pll_power_up
;
3205 case RTL_GIGA_MAC_VER_11
:
3206 case RTL_GIGA_MAC_VER_12
:
3207 case RTL_GIGA_MAC_VER_17
:
3208 case RTL_GIGA_MAC_VER_18
:
3209 case RTL_GIGA_MAC_VER_19
:
3210 case RTL_GIGA_MAC_VER_20
:
3211 case RTL_GIGA_MAC_VER_21
:
3212 case RTL_GIGA_MAC_VER_22
:
3213 case RTL_GIGA_MAC_VER_23
:
3214 case RTL_GIGA_MAC_VER_24
:
3215 case RTL_GIGA_MAC_VER_25
:
3216 case RTL_GIGA_MAC_VER_26
:
3217 case RTL_GIGA_MAC_VER_27
:
3218 case RTL_GIGA_MAC_VER_28
:
3219 case RTL_GIGA_MAC_VER_31
:
3220 case RTL_GIGA_MAC_VER_32
:
3221 case RTL_GIGA_MAC_VER_33
:
3222 ops
->down
= r8168_pll_power_down
;
3223 ops
->up
= r8168_pll_power_up
;
3233 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3235 void __iomem
*ioaddr
= tp
->mmio_addr
;
3238 /* Soft reset the chip. */
3239 RTL_W8(ChipCmd
, CmdReset
);
3241 /* Check that the chip has finished the reset. */
3242 for (i
= 0; i
< 100; i
++) {
3243 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3245 msleep_interruptible(1);
3249 static int __devinit
3250 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3252 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3253 const unsigned int region
= cfg
->region
;
3254 struct rtl8169_private
*tp
;
3255 struct mii_if_info
*mii
;
3256 struct net_device
*dev
;
3257 void __iomem
*ioaddr
;
3261 if (netif_msg_drv(&debug
)) {
3262 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3263 MODULENAME
, RTL8169_VERSION
);
3266 dev
= alloc_etherdev(sizeof (*tp
));
3268 if (netif_msg_drv(&debug
))
3269 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3274 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3275 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3276 tp
= netdev_priv(dev
);
3279 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3283 mii
->mdio_read
= rtl_mdio_read
;
3284 mii
->mdio_write
= rtl_mdio_write
;
3285 mii
->phy_id_mask
= 0x1f;
3286 mii
->reg_num_mask
= 0x1f;
3287 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3289 /* disable ASPM completely as that cause random device stop working
3290 * problems as well as full system hangs for some PCIe devices users */
3291 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3292 PCIE_LINK_STATE_CLKPM
);
3294 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3295 rc
= pci_enable_device(pdev
);
3297 netif_err(tp
, probe
, dev
, "enable failure\n");
3298 goto err_out_free_dev_1
;
3301 if (pci_set_mwi(pdev
) < 0)
3302 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3304 /* make sure PCI base addr 1 is MMIO */
3305 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3306 netif_err(tp
, probe
, dev
,
3307 "region #%d not an MMIO resource, aborting\n",
3313 /* check for weird/broken PCI region reporting */
3314 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3315 netif_err(tp
, probe
, dev
,
3316 "Invalid PCI region size(s), aborting\n");
3321 rc
= pci_request_regions(pdev
, MODULENAME
);
3323 netif_err(tp
, probe
, dev
, "could not request regions\n");
3327 tp
->cp_cmd
= RxChkSum
;
3329 if ((sizeof(dma_addr_t
) > 4) &&
3330 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3331 tp
->cp_cmd
|= PCIDAC
;
3332 dev
->features
|= NETIF_F_HIGHDMA
;
3334 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3336 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3337 goto err_out_free_res_3
;
3341 /* ioremap MMIO region */
3342 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3344 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3346 goto err_out_free_res_3
;
3348 tp
->mmio_addr
= ioaddr
;
3350 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3352 netif_info(tp
, probe
, dev
, "no PCI Express capability\n");
3354 RTL_W16(IntrMask
, 0x0000);
3358 RTL_W16(IntrStatus
, 0xffff);
3360 pci_set_master(pdev
);
3362 /* Identify chip attached to board */
3363 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
3366 * Pretend we are using VLANs; This bypasses a nasty bug where
3367 * Interrupts stop flowing on high load on 8110SCd controllers.
3369 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3370 tp
->cp_cmd
|= RxVlan
;
3372 rtl_init_mdio_ops(tp
);
3373 rtl_init_pll_power_ops(tp
);
3375 rtl8169_print_mac_version(tp
);
3377 chipset
= tp
->mac_version
;
3378 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
3380 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3381 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3382 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3383 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3384 tp
->features
|= RTL_FEATURE_WOL
;
3385 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3386 tp
->features
|= RTL_FEATURE_WOL
;
3387 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3388 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3390 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3391 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3392 tp
->set_speed
= rtl8169_set_speed_tbi
;
3393 tp
->get_settings
= rtl8169_gset_tbi
;
3394 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3395 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3396 tp
->link_ok
= rtl8169_tbi_link_ok
;
3397 tp
->do_ioctl
= rtl_tbi_ioctl
;
3399 tp
->set_speed
= rtl8169_set_speed_xmii
;
3400 tp
->get_settings
= rtl8169_gset_xmii
;
3401 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3402 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3403 tp
->link_ok
= rtl8169_xmii_link_ok
;
3404 tp
->do_ioctl
= rtl_xmii_ioctl
;
3407 spin_lock_init(&tp
->lock
);
3409 /* Get MAC address */
3410 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3411 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3412 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3414 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3415 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3416 dev
->irq
= pdev
->irq
;
3417 dev
->base_addr
= (unsigned long) ioaddr
;
3419 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3421 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3422 * properly for all devices */
3423 dev
->features
|= NETIF_F_RXCSUM
|
3424 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3426 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3427 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3428 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3431 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3432 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3433 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
3435 tp
->intr_mask
= 0xffff;
3436 tp
->hw_start
= cfg
->hw_start
;
3437 tp
->intr_event
= cfg
->intr_event
;
3438 tp
->napi_event
= cfg
->napi_event
;
3440 init_timer(&tp
->timer
);
3441 tp
->timer
.data
= (unsigned long) dev
;
3442 tp
->timer
.function
= rtl8169_phy_timer
;
3444 tp
->fw
= RTL_FIRMWARE_UNKNOWN
;
3446 rc
= register_netdev(dev
);
3450 pci_set_drvdata(pdev
, dev
);
3452 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3453 rtl_chip_infos
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
3454 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3456 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3457 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3458 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3459 rtl8168_driver_start(tp
);
3462 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3464 if (pci_dev_run_wake(pdev
))
3465 pm_runtime_put_noidle(&pdev
->dev
);
3467 netif_carrier_off(dev
);
3473 rtl_disable_msi(pdev
, tp
);
3476 pci_release_regions(pdev
);
3478 pci_clear_mwi(pdev
);
3479 pci_disable_device(pdev
);
3485 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3487 struct net_device
*dev
= pci_get_drvdata(pdev
);
3488 struct rtl8169_private
*tp
= netdev_priv(dev
);
3490 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3491 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3492 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3493 rtl8168_driver_stop(tp
);
3496 cancel_delayed_work_sync(&tp
->task
);
3498 unregister_netdev(dev
);
3500 rtl_release_firmware(tp
);
3502 if (pci_dev_run_wake(pdev
))
3503 pm_runtime_get_noresume(&pdev
->dev
);
3505 /* restore original MAC address */
3506 rtl_rar_set(tp
, dev
->perm_addr
);
3508 rtl_disable_msi(pdev
, tp
);
3509 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3510 pci_set_drvdata(pdev
, NULL
);
3513 static void rtl_request_firmware(struct rtl8169_private
*tp
)
3515 /* Return early if the firmware is already loaded / cached. */
3516 if (IS_ERR(tp
->fw
)) {
3519 name
= rtl_lookup_firmware_name(tp
);
3523 rc
= request_firmware(&tp
->fw
, name
, &tp
->pci_dev
->dev
);
3527 netif_warn(tp
, ifup
, tp
->dev
, "unable to load "
3528 "firmware patch %s (%d)\n", name
, rc
);
3534 static int rtl8169_open(struct net_device
*dev
)
3536 struct rtl8169_private
*tp
= netdev_priv(dev
);
3537 void __iomem
*ioaddr
= tp
->mmio_addr
;
3538 struct pci_dev
*pdev
= tp
->pci_dev
;
3539 int retval
= -ENOMEM
;
3541 pm_runtime_get_sync(&pdev
->dev
);
3544 * Rx and Tx desscriptors needs 256 bytes alignment.
3545 * dma_alloc_coherent provides more.
3547 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
3548 &tp
->TxPhyAddr
, GFP_KERNEL
);
3549 if (!tp
->TxDescArray
)
3550 goto err_pm_runtime_put
;
3552 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
3553 &tp
->RxPhyAddr
, GFP_KERNEL
);
3554 if (!tp
->RxDescArray
)
3557 retval
= rtl8169_init_ring(dev
);
3561 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3565 rtl_request_firmware(tp
);
3567 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3568 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3571 goto err_release_fw_2
;
3573 napi_enable(&tp
->napi
);
3575 rtl8169_init_phy(dev
, tp
);
3577 rtl8169_set_features(dev
, dev
->features
);
3579 rtl_pll_power_up(tp
);
3583 tp
->saved_wolopts
= 0;
3584 pm_runtime_put_noidle(&pdev
->dev
);
3586 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3591 rtl_release_firmware(tp
);
3592 rtl8169_rx_clear(tp
);
3594 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3596 tp
->RxDescArray
= NULL
;
3598 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3600 tp
->TxDescArray
= NULL
;
3602 pm_runtime_put_noidle(&pdev
->dev
);
3606 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
3608 void __iomem
*ioaddr
= tp
->mmio_addr
;
3610 /* Disable interrupts */
3611 rtl8169_irq_mask_and_ack(ioaddr
);
3613 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3614 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3615 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3616 while (RTL_R8(TxPoll
) & NPQ
)
3621 /* Reset the chipset */
3622 RTL_W8(ChipCmd
, CmdReset
);
3628 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3630 void __iomem
*ioaddr
= tp
->mmio_addr
;
3631 u32 cfg
= rtl8169_rx_config
;
3633 cfg
|= (RTL_R32(RxConfig
) & RTL_RX_CONFIG_MASK
);
3634 RTL_W32(RxConfig
, cfg
);
3636 /* Set DMA burst size and Interframe Gap Time */
3637 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3638 (InterFrameGap
<< TxInterFrameGapShift
));
3641 static void rtl_hw_start(struct net_device
*dev
)
3643 struct rtl8169_private
*tp
= netdev_priv(dev
);
3649 netif_start_queue(dev
);
3652 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3653 void __iomem
*ioaddr
)
3656 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3657 * register to be written before TxDescAddrLow to work.
3658 * Switching from MMIO to I/O access fixes the issue as well.
3660 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3661 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3662 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3663 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3666 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3670 cmd
= RTL_R16(CPlusCmd
);
3671 RTL_W16(CPlusCmd
, cmd
);
3675 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3677 /* Low hurts. Let's disable the filtering. */
3678 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3681 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3683 static const struct {
3688 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3689 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3690 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3691 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3696 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3697 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3698 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3699 RTL_W32(0x7c, p
->val
);
3705 static void rtl_hw_start_8169(struct net_device
*dev
)
3707 struct rtl8169_private
*tp
= netdev_priv(dev
);
3708 void __iomem
*ioaddr
= tp
->mmio_addr
;
3709 struct pci_dev
*pdev
= tp
->pci_dev
;
3711 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3712 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3713 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3716 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3717 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
3718 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
3719 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
3720 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
3721 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3723 RTL_W8(EarlyTxThres
, NoEarlyTx
);
3725 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3727 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
3728 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
3729 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
3730 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
3731 rtl_set_rx_tx_config_registers(tp
);
3733 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3735 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
3736 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
3737 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3738 "Bit-3 and bit-14 MUST be 1\n");
3739 tp
->cp_cmd
|= (1 << 14);
3742 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3744 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3747 * Undocumented corner. Supposedly:
3748 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3750 RTL_W16(IntrMitigate
, 0x0000);
3752 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3754 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
3755 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
3756 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
3757 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
3758 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3759 rtl_set_rx_tx_config_registers(tp
);
3762 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3764 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3767 RTL_W32(RxMissed
, 0);
3769 rtl_set_rx_mode(dev
);
3771 /* no early-rx interrupts */
3772 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3774 /* Enable all known interrupts by setting the interrupt mask. */
3775 RTL_W16(IntrMask
, tp
->intr_event
);
3778 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3780 struct net_device
*dev
= pci_get_drvdata(pdev
);
3781 struct rtl8169_private
*tp
= netdev_priv(dev
);
3782 int cap
= tp
->pcie_cap
;
3787 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3788 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3789 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3793 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
3797 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3798 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
3801 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
3803 rtl_csi_access_enable(ioaddr
, 0x17000000);
3806 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
3808 rtl_csi_access_enable(ioaddr
, 0x27000000);
3812 unsigned int offset
;
3817 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
3822 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3823 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3828 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3830 struct net_device
*dev
= pci_get_drvdata(pdev
);
3831 struct rtl8169_private
*tp
= netdev_priv(dev
);
3832 int cap
= tp
->pcie_cap
;
3837 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3838 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3839 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3843 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
3845 struct net_device
*dev
= pci_get_drvdata(pdev
);
3846 struct rtl8169_private
*tp
= netdev_priv(dev
);
3847 int cap
= tp
->pcie_cap
;
3852 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3853 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
3854 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3858 #define R8168_CPCMD_QUIRK_MASK (\
3869 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3871 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3873 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3875 rtl_tx_performance_tweak(pdev
,
3876 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3879 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3881 rtl_hw_start_8168bb(ioaddr
, pdev
);
3883 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3885 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3888 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3890 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
3892 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3894 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3896 rtl_disable_clock_request(pdev
);
3898 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3901 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3903 static const struct ephy_info e_info_8168cp
[] = {
3904 { 0x01, 0, 0x0001 },
3905 { 0x02, 0x0800, 0x1000 },
3906 { 0x03, 0, 0x0042 },
3907 { 0x06, 0x0080, 0x0000 },
3911 rtl_csi_access_enable_2(ioaddr
);
3913 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
3915 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3918 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3920 rtl_csi_access_enable_2(ioaddr
);
3922 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3924 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3926 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3929 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3931 rtl_csi_access_enable_2(ioaddr
);
3933 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3936 RTL_W8(DBG_REG
, 0x20);
3938 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3940 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3942 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3945 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3947 static const struct ephy_info e_info_8168c_1
[] = {
3948 { 0x02, 0x0800, 0x1000 },
3949 { 0x03, 0, 0x0002 },
3950 { 0x06, 0x0080, 0x0000 }
3953 rtl_csi_access_enable_2(ioaddr
);
3955 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
3957 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
3959 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3962 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3964 static const struct ephy_info e_info_8168c_2
[] = {
3965 { 0x01, 0, 0x0001 },
3966 { 0x03, 0x0400, 0x0220 }
3969 rtl_csi_access_enable_2(ioaddr
);
3971 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
3973 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3976 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3978 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3981 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3983 rtl_csi_access_enable_2(ioaddr
);
3985 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3988 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3990 rtl_csi_access_enable_2(ioaddr
);
3992 rtl_disable_clock_request(pdev
);
3994 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3996 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3998 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4001 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4003 rtl_csi_access_enable_1(ioaddr
);
4005 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4007 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4009 rtl_disable_clock_request(pdev
);
4012 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4014 static const struct ephy_info e_info_8168d_4
[] = {
4016 { 0x19, 0x20, 0x50 },
4021 rtl_csi_access_enable_1(ioaddr
);
4023 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4025 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4027 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4028 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4031 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4032 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4035 rtl_enable_clock_request(pdev
);
4038 static void rtl_hw_start_8168e(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4040 static const struct ephy_info e_info_8168e
[] = {
4041 { 0x00, 0x0200, 0x0100 },
4042 { 0x00, 0x0000, 0x0004 },
4043 { 0x06, 0x0002, 0x0001 },
4044 { 0x06, 0x0000, 0x0030 },
4045 { 0x07, 0x0000, 0x2000 },
4046 { 0x00, 0x0000, 0x0020 },
4047 { 0x03, 0x5800, 0x2000 },
4048 { 0x03, 0x0000, 0x0001 },
4049 { 0x01, 0x0800, 0x1000 },
4050 { 0x07, 0x0000, 0x4000 },
4051 { 0x1e, 0x0000, 0x2000 },
4052 { 0x19, 0xffff, 0xfe6c },
4053 { 0x0a, 0x0000, 0x0040 }
4056 rtl_csi_access_enable_2(ioaddr
);
4058 rtl_ephy_init(ioaddr
, e_info_8168e
, ARRAY_SIZE(e_info_8168e
));
4060 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4062 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4064 rtl_disable_clock_request(pdev
);
4066 /* Reset tx FIFO pointer */
4067 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4068 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4070 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4073 static void rtl_hw_start_8168(struct net_device
*dev
)
4075 struct rtl8169_private
*tp
= netdev_priv(dev
);
4076 void __iomem
*ioaddr
= tp
->mmio_addr
;
4077 struct pci_dev
*pdev
= tp
->pci_dev
;
4079 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4081 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4083 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4085 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4087 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4089 RTL_W16(IntrMitigate
, 0x5151);
4091 /* Work around for RxFIFO overflow. */
4092 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
4093 tp
->mac_version
== RTL_GIGA_MAC_VER_22
) {
4094 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
4095 tp
->intr_event
&= ~RxOverflow
;
4098 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4100 rtl_set_rx_mode(dev
);
4102 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4103 (InterFrameGap
<< TxInterFrameGapShift
));
4107 switch (tp
->mac_version
) {
4108 case RTL_GIGA_MAC_VER_11
:
4109 rtl_hw_start_8168bb(ioaddr
, pdev
);
4112 case RTL_GIGA_MAC_VER_12
:
4113 case RTL_GIGA_MAC_VER_17
:
4114 rtl_hw_start_8168bef(ioaddr
, pdev
);
4117 case RTL_GIGA_MAC_VER_18
:
4118 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4121 case RTL_GIGA_MAC_VER_19
:
4122 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4125 case RTL_GIGA_MAC_VER_20
:
4126 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4129 case RTL_GIGA_MAC_VER_21
:
4130 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4133 case RTL_GIGA_MAC_VER_22
:
4134 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4137 case RTL_GIGA_MAC_VER_23
:
4138 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4141 case RTL_GIGA_MAC_VER_24
:
4142 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4145 case RTL_GIGA_MAC_VER_25
:
4146 case RTL_GIGA_MAC_VER_26
:
4147 case RTL_GIGA_MAC_VER_27
:
4148 rtl_hw_start_8168d(ioaddr
, pdev
);
4151 case RTL_GIGA_MAC_VER_28
:
4152 rtl_hw_start_8168d_4(ioaddr
, pdev
);
4155 case RTL_GIGA_MAC_VER_31
:
4156 rtl_hw_start_8168dp(ioaddr
, pdev
);
4159 case RTL_GIGA_MAC_VER_32
:
4160 case RTL_GIGA_MAC_VER_33
:
4161 rtl_hw_start_8168e(ioaddr
, pdev
);
4165 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4166 dev
->name
, tp
->mac_version
);
4170 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4172 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4174 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4176 RTL_W16(IntrMask
, tp
->intr_event
);
4179 #define R810X_CPCMD_QUIRK_MASK (\
4190 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4192 static const struct ephy_info e_info_8102e_1
[] = {
4193 { 0x01, 0, 0x6e65 },
4194 { 0x02, 0, 0x091f },
4195 { 0x03, 0, 0xc2f9 },
4196 { 0x06, 0, 0xafb5 },
4197 { 0x07, 0, 0x0e00 },
4198 { 0x19, 0, 0xec80 },
4199 { 0x01, 0, 0x2e65 },
4204 rtl_csi_access_enable_2(ioaddr
);
4206 RTL_W8(DBG_REG
, FIX_NAK_1
);
4208 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4211 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
4212 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4214 cfg1
= RTL_R8(Config1
);
4215 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
4216 RTL_W8(Config1
, cfg1
& ~LEDS0
);
4218 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
4221 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4223 rtl_csi_access_enable_2(ioaddr
);
4225 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4227 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
4228 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4231 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4233 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4235 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
4238 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4240 static const struct ephy_info e_info_8105e_1
[] = {
4241 { 0x07, 0, 0x4000 },
4242 { 0x19, 0, 0x0200 },
4243 { 0x19, 0, 0x0020 },
4244 { 0x1e, 0, 0x2000 },
4245 { 0x03, 0, 0x0001 },
4246 { 0x19, 0, 0x0100 },
4247 { 0x19, 0, 0x0004 },
4251 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4252 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
4254 /* Disable Early Tally Counter */
4255 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
4257 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
4258 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PM_SWITCH
);
4260 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
4263 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4265 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4266 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
4269 static void rtl_hw_start_8101(struct net_device
*dev
)
4271 struct rtl8169_private
*tp
= netdev_priv(dev
);
4272 void __iomem
*ioaddr
= tp
->mmio_addr
;
4273 struct pci_dev
*pdev
= tp
->pci_dev
;
4275 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
4276 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
4277 int cap
= tp
->pcie_cap
;
4280 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
4281 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4285 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4287 switch (tp
->mac_version
) {
4288 case RTL_GIGA_MAC_VER_07
:
4289 rtl_hw_start_8102e_1(ioaddr
, pdev
);
4292 case RTL_GIGA_MAC_VER_08
:
4293 rtl_hw_start_8102e_3(ioaddr
, pdev
);
4296 case RTL_GIGA_MAC_VER_09
:
4297 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4300 case RTL_GIGA_MAC_VER_29
:
4301 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4303 case RTL_GIGA_MAC_VER_30
:
4304 rtl_hw_start_8105e_2(ioaddr
, pdev
);
4308 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4310 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4312 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4314 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
4315 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4317 RTL_W16(IntrMitigate
, 0x0000);
4319 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4321 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4322 rtl_set_rx_tx_config_registers(tp
);
4326 rtl_set_rx_mode(dev
);
4328 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
4330 RTL_W16(IntrMask
, tp
->intr_event
);
4333 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
4335 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
4339 netdev_update_features(dev
);
4344 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
4346 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
4347 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
4350 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
4351 void **data_buff
, struct RxDesc
*desc
)
4353 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
4358 rtl8169_make_unusable_by_asic(desc
);
4361 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
4363 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
4365 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
4368 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
4371 desc
->addr
= cpu_to_le64(mapping
);
4373 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4376 static inline void *rtl8169_align(void *data
)
4378 return (void *)ALIGN((long)data
, 16);
4381 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
4382 struct RxDesc
*desc
)
4386 struct device
*d
= &tp
->pci_dev
->dev
;
4387 struct net_device
*dev
= tp
->dev
;
4388 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
4390 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
4394 if (rtl8169_align(data
) != data
) {
4396 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
4401 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
4403 if (unlikely(dma_mapping_error(d
, mapping
))) {
4404 if (net_ratelimit())
4405 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
4409 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4417 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4421 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4422 if (tp
->Rx_databuff
[i
]) {
4423 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
4424 tp
->RxDescArray
+ i
);
4429 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4431 desc
->opts1
|= cpu_to_le32(RingEnd
);
4434 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
4438 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4441 if (tp
->Rx_databuff
[i
])
4444 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
4446 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
4449 tp
->Rx_databuff
[i
] = data
;
4452 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4456 rtl8169_rx_clear(tp
);
4460 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4462 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4465 static int rtl8169_init_ring(struct net_device
*dev
)
4467 struct rtl8169_private
*tp
= netdev_priv(dev
);
4469 rtl8169_init_ring_indexes(tp
);
4471 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4472 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
4474 return rtl8169_rx_fill(tp
);
4477 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
4478 struct TxDesc
*desc
)
4480 unsigned int len
= tx_skb
->len
;
4482 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
4490 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
4495 for (i
= 0; i
< n
; i
++) {
4496 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
4497 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4498 unsigned int len
= tx_skb
->len
;
4501 struct sk_buff
*skb
= tx_skb
->skb
;
4503 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4504 tp
->TxDescArray
+ entry
);
4506 tp
->dev
->stats
.tx_dropped
++;
4514 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4516 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
4517 tp
->cur_tx
= tp
->dirty_tx
= 0;
4520 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4522 struct rtl8169_private
*tp
= netdev_priv(dev
);
4524 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4525 schedule_delayed_work(&tp
->task
, 4);
4528 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4530 struct rtl8169_private
*tp
= netdev_priv(dev
);
4531 void __iomem
*ioaddr
= tp
->mmio_addr
;
4533 synchronize_irq(dev
->irq
);
4535 /* Wait for any pending NAPI task to complete */
4536 napi_disable(&tp
->napi
);
4538 rtl8169_irq_mask_and_ack(ioaddr
);
4540 tp
->intr_mask
= 0xffff;
4541 RTL_W16(IntrMask
, tp
->intr_event
);
4542 napi_enable(&tp
->napi
);
4545 static void rtl8169_reinit_task(struct work_struct
*work
)
4547 struct rtl8169_private
*tp
=
4548 container_of(work
, struct rtl8169_private
, task
.work
);
4549 struct net_device
*dev
= tp
->dev
;
4554 if (!netif_running(dev
))
4557 rtl8169_wait_for_quiescence(dev
);
4560 ret
= rtl8169_open(dev
);
4561 if (unlikely(ret
< 0)) {
4562 if (net_ratelimit())
4563 netif_err(tp
, drv
, dev
,
4564 "reinit failure (status = %d). Rescheduling\n",
4566 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4573 static void rtl8169_reset_task(struct work_struct
*work
)
4575 struct rtl8169_private
*tp
=
4576 container_of(work
, struct rtl8169_private
, task
.work
);
4577 struct net_device
*dev
= tp
->dev
;
4582 if (!netif_running(dev
))
4585 rtl8169_wait_for_quiescence(dev
);
4587 for (i
= 0; i
< NUM_RX_DESC
; i
++)
4588 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
4590 rtl8169_tx_clear(tp
);
4592 rtl8169_init_ring_indexes(tp
);
4594 netif_wake_queue(dev
);
4595 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4601 static void rtl8169_tx_timeout(struct net_device
*dev
)
4603 struct rtl8169_private
*tp
= netdev_priv(dev
);
4605 rtl8169_hw_reset(tp
);
4607 /* Let's wait a bit while any (async) irq lands on */
4608 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4611 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4614 struct skb_shared_info
*info
= skb_shinfo(skb
);
4615 unsigned int cur_frag
, entry
;
4616 struct TxDesc
* uninitialized_var(txd
);
4617 struct device
*d
= &tp
->pci_dev
->dev
;
4620 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4621 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4626 entry
= (entry
+ 1) % NUM_TX_DESC
;
4628 txd
= tp
->TxDescArray
+ entry
;
4630 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4631 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
4632 if (unlikely(dma_mapping_error(d
, mapping
))) {
4633 if (net_ratelimit())
4634 netif_err(tp
, drv
, tp
->dev
,
4635 "Failed to map TX fragments DMA!\n");
4639 /* Anti gcc 2.95.3 bugware (sic) */
4640 status
= opts
[0] | len
|
4641 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4643 txd
->opts1
= cpu_to_le32(status
);
4644 txd
->opts2
= cpu_to_le32(opts
[1]);
4645 txd
->addr
= cpu_to_le64(mapping
);
4647 tp
->tx_skb
[entry
].len
= len
;
4651 tp
->tx_skb
[entry
].skb
= skb
;
4652 txd
->opts1
|= cpu_to_le32(LastFrag
);
4658 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
4662 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
4663 struct sk_buff
*skb
, u32
*opts
)
4665 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
4666 u32 mss
= skb_shinfo(skb
)->gso_size
;
4667 int offset
= info
->opts_offset
;
4671 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
4672 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4673 const struct iphdr
*ip
= ip_hdr(skb
);
4675 if (ip
->protocol
== IPPROTO_TCP
)
4676 opts
[offset
] |= info
->checksum
.tcp
;
4677 else if (ip
->protocol
== IPPROTO_UDP
)
4678 opts
[offset
] |= info
->checksum
.udp
;
4684 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4685 struct net_device
*dev
)
4687 struct rtl8169_private
*tp
= netdev_priv(dev
);
4688 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
4689 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4690 void __iomem
*ioaddr
= tp
->mmio_addr
;
4691 struct device
*d
= &tp
->pci_dev
->dev
;
4697 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4698 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
4702 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4705 len
= skb_headlen(skb
);
4706 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
4707 if (unlikely(dma_mapping_error(d
, mapping
))) {
4708 if (net_ratelimit())
4709 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
4713 tp
->tx_skb
[entry
].len
= len
;
4714 txd
->addr
= cpu_to_le64(mapping
);
4716 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4719 rtl8169_tso_csum(tp
, skb
, opts
);
4721 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
4725 opts
[0] |= FirstFrag
;
4727 opts
[0] |= FirstFrag
| LastFrag
;
4728 tp
->tx_skb
[entry
].skb
= skb
;
4731 txd
->opts2
= cpu_to_le32(opts
[1]);
4735 /* Anti gcc 2.95.3 bugware (sic) */
4736 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4737 txd
->opts1
= cpu_to_le32(status
);
4739 tp
->cur_tx
+= frags
+ 1;
4743 RTL_W8(TxPoll
, NPQ
);
4745 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4746 netif_stop_queue(dev
);
4748 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4749 netif_wake_queue(dev
);
4752 return NETDEV_TX_OK
;
4755 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
4758 dev
->stats
.tx_dropped
++;
4759 return NETDEV_TX_OK
;
4762 netif_stop_queue(dev
);
4763 dev
->stats
.tx_dropped
++;
4764 return NETDEV_TX_BUSY
;
4767 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4769 struct rtl8169_private
*tp
= netdev_priv(dev
);
4770 struct pci_dev
*pdev
= tp
->pci_dev
;
4771 u16 pci_status
, pci_cmd
;
4773 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4774 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4776 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4777 pci_cmd
, pci_status
);
4780 * The recovery sequence below admits a very elaborated explanation:
4781 * - it seems to work;
4782 * - I did not see what else could be done;
4783 * - it makes iop3xx happy.
4785 * Feel free to adjust to your needs.
4787 if (pdev
->broken_parity_status
)
4788 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4790 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4792 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4794 pci_write_config_word(pdev
, PCI_STATUS
,
4795 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4796 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4797 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4799 /* The infamous DAC f*ckup only happens at boot time */
4800 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4801 void __iomem
*ioaddr
= tp
->mmio_addr
;
4803 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
4804 tp
->cp_cmd
&= ~PCIDAC
;
4805 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4806 dev
->features
&= ~NETIF_F_HIGHDMA
;
4809 rtl8169_hw_reset(tp
);
4811 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4814 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4815 struct rtl8169_private
*tp
,
4816 void __iomem
*ioaddr
)
4818 unsigned int dirty_tx
, tx_left
;
4820 dirty_tx
= tp
->dirty_tx
;
4822 tx_left
= tp
->cur_tx
- dirty_tx
;
4824 while (tx_left
> 0) {
4825 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4826 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4830 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4831 if (status
& DescOwn
)
4834 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4835 tp
->TxDescArray
+ entry
);
4836 if (status
& LastFrag
) {
4837 dev
->stats
.tx_packets
++;
4838 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
4839 dev_kfree_skb(tx_skb
->skb
);
4846 if (tp
->dirty_tx
!= dirty_tx
) {
4847 tp
->dirty_tx
= dirty_tx
;
4849 if (netif_queue_stopped(dev
) &&
4850 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4851 netif_wake_queue(dev
);
4854 * 8168 hack: TxPoll requests are lost when the Tx packets are
4855 * too close. Let's kick an extra TxPoll request when a burst
4856 * of start_xmit activity is detected (if it is not detected,
4857 * it is slow enough). -- FR
4860 if (tp
->cur_tx
!= dirty_tx
)
4861 RTL_W8(TxPoll
, NPQ
);
4865 static inline int rtl8169_fragmented_frame(u32 status
)
4867 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4870 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
4872 u32 status
= opts1
& RxProtoMask
;
4874 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4875 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
4876 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4878 skb_checksum_none_assert(skb
);
4881 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
4882 struct rtl8169_private
*tp
,
4886 struct sk_buff
*skb
;
4887 struct device
*d
= &tp
->pci_dev
->dev
;
4889 data
= rtl8169_align(data
);
4890 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4892 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
4894 memcpy(skb
->data
, data
, pkt_size
);
4895 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4900 static int rtl8169_rx_interrupt(struct net_device
*dev
,
4901 struct rtl8169_private
*tp
,
4902 void __iomem
*ioaddr
, u32 budget
)
4904 unsigned int cur_rx
, rx_left
;
4907 cur_rx
= tp
->cur_rx
;
4908 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
4909 rx_left
= min(rx_left
, budget
);
4911 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
4912 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
4913 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4917 status
= le32_to_cpu(desc
->opts1
);
4919 if (status
& DescOwn
)
4921 if (unlikely(status
& RxRES
)) {
4922 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
4924 dev
->stats
.rx_errors
++;
4925 if (status
& (RxRWT
| RxRUNT
))
4926 dev
->stats
.rx_length_errors
++;
4928 dev
->stats
.rx_crc_errors
++;
4929 if (status
& RxFOVF
) {
4930 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4931 dev
->stats
.rx_fifo_errors
++;
4933 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4935 struct sk_buff
*skb
;
4936 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
4937 int pkt_size
= (status
& 0x00001FFF) - 4;
4940 * The driver does not support incoming fragmented
4941 * frames. They are seen as a symptom of over-mtu
4944 if (unlikely(rtl8169_fragmented_frame(status
))) {
4945 dev
->stats
.rx_dropped
++;
4946 dev
->stats
.rx_length_errors
++;
4947 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4951 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
4952 tp
, pkt_size
, addr
);
4953 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4955 dev
->stats
.rx_dropped
++;
4959 rtl8169_rx_csum(skb
, status
);
4960 skb_put(skb
, pkt_size
);
4961 skb
->protocol
= eth_type_trans(skb
, dev
);
4963 rtl8169_rx_vlan_tag(desc
, skb
);
4965 napi_gro_receive(&tp
->napi
, skb
);
4967 dev
->stats
.rx_bytes
+= pkt_size
;
4968 dev
->stats
.rx_packets
++;
4971 /* Work around for AMD plateform. */
4972 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
4973 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
4979 count
= cur_rx
- tp
->cur_rx
;
4980 tp
->cur_rx
= cur_rx
;
4982 tp
->dirty_rx
+= count
;
4987 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
4989 struct net_device
*dev
= dev_instance
;
4990 struct rtl8169_private
*tp
= netdev_priv(dev
);
4991 void __iomem
*ioaddr
= tp
->mmio_addr
;
4995 /* loop handling interrupts until we have no new ones or
4996 * we hit a invalid/hotplug case.
4998 status
= RTL_R16(IntrStatus
);
4999 while (status
&& status
!= 0xffff) {
5002 /* Handle all of the error cases first. These will reset
5003 * the chip, so just exit the loop.
5005 if (unlikely(!netif_running(dev
))) {
5006 rtl8169_asic_down(ioaddr
);
5010 if (unlikely(status
& RxFIFOOver
)) {
5011 switch (tp
->mac_version
) {
5012 /* Work around for rx fifo overflow */
5013 case RTL_GIGA_MAC_VER_11
:
5014 case RTL_GIGA_MAC_VER_22
:
5015 case RTL_GIGA_MAC_VER_26
:
5016 netif_stop_queue(dev
);
5017 rtl8169_tx_timeout(dev
);
5019 /* Testers needed. */
5020 case RTL_GIGA_MAC_VER_17
:
5021 case RTL_GIGA_MAC_VER_19
:
5022 case RTL_GIGA_MAC_VER_20
:
5023 case RTL_GIGA_MAC_VER_21
:
5024 case RTL_GIGA_MAC_VER_23
:
5025 case RTL_GIGA_MAC_VER_24
:
5026 case RTL_GIGA_MAC_VER_27
:
5027 case RTL_GIGA_MAC_VER_28
:
5028 case RTL_GIGA_MAC_VER_31
:
5029 /* Experimental science. Pktgen proof. */
5030 case RTL_GIGA_MAC_VER_12
:
5031 case RTL_GIGA_MAC_VER_25
:
5032 if (status
== RxFIFOOver
)
5040 if (unlikely(status
& SYSErr
)) {
5041 rtl8169_pcierr_interrupt(dev
);
5045 if (status
& LinkChg
)
5046 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
5048 /* We need to see the lastest version of tp->intr_mask to
5049 * avoid ignoring an MSI interrupt and having to wait for
5050 * another event which may never come.
5053 if (status
& tp
->intr_mask
& tp
->napi_event
) {
5054 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
5055 tp
->intr_mask
= ~tp
->napi_event
;
5057 if (likely(napi_schedule_prep(&tp
->napi
)))
5058 __napi_schedule(&tp
->napi
);
5060 netif_info(tp
, intr
, dev
,
5061 "interrupt %04x in poll\n", status
);
5064 /* We only get a new MSI interrupt when all active irq
5065 * sources on the chip have been acknowledged. So, ack
5066 * everything we've seen and check if new sources have become
5067 * active to avoid blocking all interrupts from the chip.
5070 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
5071 status
= RTL_R16(IntrStatus
);
5074 return IRQ_RETVAL(handled
);
5077 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5079 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5080 struct net_device
*dev
= tp
->dev
;
5081 void __iomem
*ioaddr
= tp
->mmio_addr
;
5084 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
5085 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
5087 if (work_done
< budget
) {
5088 napi_complete(napi
);
5090 /* We need for force the visibility of tp->intr_mask
5091 * for other CPUs, as we can loose an MSI interrupt
5092 * and potentially wait for a retransmit timeout if we don't.
5093 * The posted write to IntrMask is safe, as it will
5094 * eventually make it to the chip and we won't loose anything
5097 tp
->intr_mask
= 0xffff;
5099 RTL_W16(IntrMask
, tp
->intr_event
);
5105 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5107 struct rtl8169_private
*tp
= netdev_priv(dev
);
5109 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5112 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5113 RTL_W32(RxMissed
, 0);
5116 static void rtl8169_down(struct net_device
*dev
)
5118 struct rtl8169_private
*tp
= netdev_priv(dev
);
5119 void __iomem
*ioaddr
= tp
->mmio_addr
;
5121 del_timer_sync(&tp
->timer
);
5123 netif_stop_queue(dev
);
5125 napi_disable(&tp
->napi
);
5127 spin_lock_irq(&tp
->lock
);
5129 rtl8169_asic_down(ioaddr
);
5131 * At this point device interrupts can not be enabled in any function,
5132 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5133 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5135 rtl8169_rx_missed(dev
, ioaddr
);
5137 spin_unlock_irq(&tp
->lock
);
5139 synchronize_irq(dev
->irq
);
5141 /* Give a racing hard_start_xmit a few cycles to complete. */
5142 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5144 rtl8169_tx_clear(tp
);
5146 rtl8169_rx_clear(tp
);
5148 rtl_pll_power_down(tp
);
5151 static int rtl8169_close(struct net_device
*dev
)
5153 struct rtl8169_private
*tp
= netdev_priv(dev
);
5154 struct pci_dev
*pdev
= tp
->pci_dev
;
5156 pm_runtime_get_sync(&pdev
->dev
);
5158 /* Update counters before going down */
5159 rtl8169_update_counters(dev
);
5163 free_irq(dev
->irq
, dev
);
5165 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5167 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5169 tp
->TxDescArray
= NULL
;
5170 tp
->RxDescArray
= NULL
;
5172 pm_runtime_put_sync(&pdev
->dev
);
5177 static void rtl_set_rx_mode(struct net_device
*dev
)
5179 struct rtl8169_private
*tp
= netdev_priv(dev
);
5180 void __iomem
*ioaddr
= tp
->mmio_addr
;
5181 unsigned long flags
;
5182 u32 mc_filter
[2]; /* Multicast hash filter */
5186 if (dev
->flags
& IFF_PROMISC
) {
5187 /* Unconditionally log net taps. */
5188 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5190 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5192 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5193 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5194 (dev
->flags
& IFF_ALLMULTI
)) {
5195 /* Too many to filter perfectly -- accept all multicasts. */
5196 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5197 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5199 struct netdev_hw_addr
*ha
;
5201 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5202 mc_filter
[1] = mc_filter
[0] = 0;
5203 netdev_for_each_mc_addr(ha
, dev
) {
5204 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5205 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5206 rx_mode
|= AcceptMulticast
;
5210 spin_lock_irqsave(&tp
->lock
, flags
);
5212 tmp
= rtl8169_rx_config
| rx_mode
|
5213 (RTL_R32(RxConfig
) & RTL_RX_CONFIG_MASK
);
5215 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5216 u32 data
= mc_filter
[0];
5218 mc_filter
[0] = swab32(mc_filter
[1]);
5219 mc_filter
[1] = swab32(data
);
5222 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5223 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5225 RTL_W32(RxConfig
, tmp
);
5227 spin_unlock_irqrestore(&tp
->lock
, flags
);
5231 * rtl8169_get_stats - Get rtl8169 read/write statistics
5232 * @dev: The Ethernet Device to get statistics for
5234 * Get TX/RX statistics for rtl8169
5236 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
5238 struct rtl8169_private
*tp
= netdev_priv(dev
);
5239 void __iomem
*ioaddr
= tp
->mmio_addr
;
5240 unsigned long flags
;
5242 if (netif_running(dev
)) {
5243 spin_lock_irqsave(&tp
->lock
, flags
);
5244 rtl8169_rx_missed(dev
, ioaddr
);
5245 spin_unlock_irqrestore(&tp
->lock
, flags
);
5251 static void rtl8169_net_suspend(struct net_device
*dev
)
5253 struct rtl8169_private
*tp
= netdev_priv(dev
);
5255 if (!netif_running(dev
))
5258 rtl_pll_power_down(tp
);
5260 netif_device_detach(dev
);
5261 netif_stop_queue(dev
);
5266 static int rtl8169_suspend(struct device
*device
)
5268 struct pci_dev
*pdev
= to_pci_dev(device
);
5269 struct net_device
*dev
= pci_get_drvdata(pdev
);
5271 rtl8169_net_suspend(dev
);
5276 static void __rtl8169_resume(struct net_device
*dev
)
5278 struct rtl8169_private
*tp
= netdev_priv(dev
);
5280 netif_device_attach(dev
);
5282 rtl_pll_power_up(tp
);
5284 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5287 static int rtl8169_resume(struct device
*device
)
5289 struct pci_dev
*pdev
= to_pci_dev(device
);
5290 struct net_device
*dev
= pci_get_drvdata(pdev
);
5291 struct rtl8169_private
*tp
= netdev_priv(dev
);
5293 rtl8169_init_phy(dev
, tp
);
5295 if (netif_running(dev
))
5296 __rtl8169_resume(dev
);
5301 static int rtl8169_runtime_suspend(struct device
*device
)
5303 struct pci_dev
*pdev
= to_pci_dev(device
);
5304 struct net_device
*dev
= pci_get_drvdata(pdev
);
5305 struct rtl8169_private
*tp
= netdev_priv(dev
);
5307 if (!tp
->TxDescArray
)
5310 spin_lock_irq(&tp
->lock
);
5311 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
5312 __rtl8169_set_wol(tp
, WAKE_ANY
);
5313 spin_unlock_irq(&tp
->lock
);
5315 rtl8169_net_suspend(dev
);
5320 static int rtl8169_runtime_resume(struct device
*device
)
5322 struct pci_dev
*pdev
= to_pci_dev(device
);
5323 struct net_device
*dev
= pci_get_drvdata(pdev
);
5324 struct rtl8169_private
*tp
= netdev_priv(dev
);
5326 if (!tp
->TxDescArray
)
5329 spin_lock_irq(&tp
->lock
);
5330 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
5331 tp
->saved_wolopts
= 0;
5332 spin_unlock_irq(&tp
->lock
);
5334 rtl8169_init_phy(dev
, tp
);
5336 __rtl8169_resume(dev
);
5341 static int rtl8169_runtime_idle(struct device
*device
)
5343 struct pci_dev
*pdev
= to_pci_dev(device
);
5344 struct net_device
*dev
= pci_get_drvdata(pdev
);
5345 struct rtl8169_private
*tp
= netdev_priv(dev
);
5347 return tp
->TxDescArray
? -EBUSY
: 0;
5350 static const struct dev_pm_ops rtl8169_pm_ops
= {
5351 .suspend
= rtl8169_suspend
,
5352 .resume
= rtl8169_resume
,
5353 .freeze
= rtl8169_suspend
,
5354 .thaw
= rtl8169_resume
,
5355 .poweroff
= rtl8169_suspend
,
5356 .restore
= rtl8169_resume
,
5357 .runtime_suspend
= rtl8169_runtime_suspend
,
5358 .runtime_resume
= rtl8169_runtime_resume
,
5359 .runtime_idle
= rtl8169_runtime_idle
,
5362 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5364 #else /* !CONFIG_PM */
5366 #define RTL8169_PM_OPS NULL
5368 #endif /* !CONFIG_PM */
5370 static void rtl_shutdown(struct pci_dev
*pdev
)
5372 struct net_device
*dev
= pci_get_drvdata(pdev
);
5373 struct rtl8169_private
*tp
= netdev_priv(dev
);
5374 void __iomem
*ioaddr
= tp
->mmio_addr
;
5376 rtl8169_net_suspend(dev
);
5378 /* Restore original MAC address */
5379 rtl_rar_set(tp
, dev
->perm_addr
);
5381 spin_lock_irq(&tp
->lock
);
5383 rtl8169_asic_down(ioaddr
);
5385 spin_unlock_irq(&tp
->lock
);
5387 if (system_state
== SYSTEM_POWER_OFF
) {
5388 /* WoL fails with some 8168 when the receiver is disabled. */
5389 if (tp
->features
& RTL_FEATURE_WOL
) {
5390 pci_clear_master(pdev
);
5392 RTL_W8(ChipCmd
, CmdRxEnb
);
5397 pci_wake_from_d3(pdev
, true);
5398 pci_set_power_state(pdev
, PCI_D3hot
);
5402 static struct pci_driver rtl8169_pci_driver
= {
5404 .id_table
= rtl8169_pci_tbl
,
5405 .probe
= rtl8169_init_one
,
5406 .remove
= __devexit_p(rtl8169_remove_one
),
5407 .shutdown
= rtl_shutdown
,
5408 .driver
.pm
= RTL8169_PM_OPS
,
5411 static int __init
rtl8169_init_module(void)
5413 return pci_register_driver(&rtl8169_pci_driver
);
5416 static void __exit
rtl8169_cleanup_module(void)
5418 pci_unregister_driver(&rtl8169_pci_driver
);
5421 module_init(rtl8169_init_module
);
5422 module_exit(rtl8169_cleanup_module
);