2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work
= 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit
= 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
94 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
103 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
104 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20
= 0x14 // 8168C
115 #define _R(NAME,MAC,MASK) \
116 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
118 static const struct {
121 u32 RxConfigMask
; /* Clears the bits supported by this chip */
122 } rtl_chip_info
[] = {
123 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
124 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
125 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
126 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
127 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
128 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
129 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
130 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
131 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
132 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
133 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
134 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
135 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
136 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
137 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
139 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
140 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
141 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
142 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880) // PCI-E
152 static void rtl_hw_start_8169(struct net_device
*);
153 static void rtl_hw_start_8168(struct net_device
*);
154 static void rtl_hw_start_8101(struct net_device
*);
156 static struct pci_device_id rtl8169_pci_tbl
[] = {
157 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
158 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
159 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
160 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
161 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
162 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
163 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
164 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
165 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
166 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
168 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
172 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
174 static int rx_copybreak
= 200;
181 MAC0
= 0, /* Ethernet hardware address. */
183 MAR0
= 8, /* Multicast filter. */
184 CounterAddrLow
= 0x10,
185 CounterAddrHigh
= 0x14,
186 TxDescStartAddrLow
= 0x20,
187 TxDescStartAddrHigh
= 0x24,
188 TxHDescStartAddrLow
= 0x28,
189 TxHDescStartAddrHigh
= 0x2c,
212 RxDescAddrLow
= 0xe4,
213 RxDescAddrHigh
= 0xe8,
216 FuncEventMask
= 0xf4,
217 FuncPresetState
= 0xf8,
218 FuncForceEvent
= 0xfc,
221 enum rtl8110_registers
{
227 enum rtl8168_8101_registers
{
230 #define CSIAR_FLAG 0x80000000
231 #define CSIAR_WRITE_CMD 0x80000000
232 #define CSIAR_BYTE_ENABLE 0x0f
233 #define CSIAR_BYTE_ENABLE_SHIFT 12
234 #define CSIAR_ADDR_MASK 0x0fff
237 #define EPHYAR_FLAG 0x80000000
238 #define EPHYAR_WRITE_CMD 0x80000000
239 #define EPHYAR_REG_MASK 0x1f
240 #define EPHYAR_REG_SHIFT 16
241 #define EPHYAR_DATA_MASK 0xffff
243 #define FIX_NAK_1 (1 << 4)
244 #define FIX_NAK_2 (1 << 3)
247 enum rtl_register_content
{
248 /* InterruptStatusBits */
252 TxDescUnavail
= 0x0080,
274 /* TXPoll register p.5 */
275 HPQ
= 0x80, /* Poll cmd on the high prio queue */
276 NPQ
= 0x40, /* Poll cmd on the low prio queue */
277 FSWInt
= 0x01, /* Forced software interrupt */
281 Cfg9346_Unlock
= 0xc0,
286 AcceptBroadcast
= 0x08,
287 AcceptMulticast
= 0x04,
289 AcceptAllPhys
= 0x01,
296 TxInterFrameGapShift
= 24,
297 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
299 /* Config1 register p.24 */
302 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
303 Speed_down
= (1 << 4),
307 PMEnable
= (1 << 0), /* Power Management Enable */
309 /* Config2 register p. 25 */
310 PCI_Clock_66MHz
= 0x01,
311 PCI_Clock_33MHz
= 0x00,
313 /* Config3 register p.25 */
314 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
315 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
316 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
318 /* Config5 register p.27 */
319 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
320 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
321 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
322 LanWake
= (1 << 1), /* LanWake enable/disable */
323 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
326 TBIReset
= 0x80000000,
327 TBILoopback
= 0x40000000,
328 TBINwEnable
= 0x20000000,
329 TBINwRestart
= 0x10000000,
330 TBILinkOk
= 0x02000000,
331 TBINwComplete
= 0x01000000,
334 EnableBist
= (1 << 15), // 8168 8101
335 Mac_dbgo_oe
= (1 << 14), // 8168 8101
336 Normal_mode
= (1 << 13), // unused
337 Force_half_dup
= (1 << 12), // 8168 8101
338 Force_rxflow_en
= (1 << 11), // 8168 8101
339 Force_txflow_en
= (1 << 10), // 8168 8101
340 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
341 ASF
= (1 << 8), // 8168 8101
342 PktCntrDisable
= (1 << 7), // 8168 8101
343 Mac_dbgo_sel
= 0x001c, // 8168
348 INTT_0
= 0x0000, // 8168
349 INTT_1
= 0x0001, // 8168
350 INTT_2
= 0x0002, // 8168
351 INTT_3
= 0x0003, // 8168
353 /* rtl8169_PHYstatus */
364 TBILinkOK
= 0x02000000,
366 /* DumpCounterCommand */
370 enum desc_status_bit
{
371 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
372 RingEnd
= (1 << 30), /* End of descriptor ring */
373 FirstFrag
= (1 << 29), /* First segment of a packet */
374 LastFrag
= (1 << 28), /* Final segment of a packet */
377 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
378 MSSShift
= 16, /* MSS value position */
379 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
380 IPCS
= (1 << 18), /* Calculate IP checksum */
381 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
382 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
383 TxVlanTag
= (1 << 17), /* Add VLAN tag */
386 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
387 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
389 #define RxProtoUDP (PID1)
390 #define RxProtoTCP (PID0)
391 #define RxProtoIP (PID1 | PID0)
392 #define RxProtoMask RxProtoIP
394 IPFail
= (1 << 16), /* IP checksum failed */
395 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
396 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
397 RxVlanTag
= (1 << 16), /* VLAN tag available */
400 #define RsvdMask 0x3fffc000
417 u8 __pad
[sizeof(void *) - sizeof(u32
)];
421 RTL_FEATURE_WOL
= (1 << 0),
422 RTL_FEATURE_MSI
= (1 << 1),
423 RTL_FEATURE_GMII
= (1 << 2),
426 struct rtl8169_private
{
427 void __iomem
*mmio_addr
; /* memory map physical address */
428 struct pci_dev
*pci_dev
; /* Index of PCI device */
429 struct net_device
*dev
;
430 struct napi_struct napi
;
431 spinlock_t lock
; /* spin lock flag */
435 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
436 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
439 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
440 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
441 dma_addr_t TxPhyAddr
;
442 dma_addr_t RxPhyAddr
;
443 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
444 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
447 struct timer_list timer
;
452 int phy_auto_nego_reg
;
453 int phy_1000_ctrl_reg
;
454 #ifdef CONFIG_R8169_VLAN
455 struct vlan_group
*vlgrp
;
457 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
458 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
459 void (*phy_reset_enable
)(void __iomem
*);
460 void (*hw_start
)(struct net_device
*);
461 unsigned int (*phy_reset_pending
)(void __iomem
*);
462 unsigned int (*link_ok
)(void __iomem
*);
464 struct delayed_work task
;
467 struct mii_if_info mii
;
470 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
471 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
472 module_param(rx_copybreak
, int, 0);
473 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
474 module_param(use_dac
, int, 0);
475 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
476 module_param_named(debug
, debug
.msg_enable
, int, 0);
477 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
478 MODULE_LICENSE("GPL");
479 MODULE_VERSION(RTL8169_VERSION
);
481 static int rtl8169_open(struct net_device
*dev
);
482 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
483 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
484 static int rtl8169_init_ring(struct net_device
*dev
);
485 static void rtl_hw_start(struct net_device
*dev
);
486 static int rtl8169_close(struct net_device
*dev
);
487 static void rtl_set_rx_mode(struct net_device
*dev
);
488 static void rtl8169_tx_timeout(struct net_device
*dev
);
489 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
490 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
491 void __iomem
*, u32 budget
);
492 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
493 static void rtl8169_down(struct net_device
*dev
);
494 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
495 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
497 static const unsigned int rtl8169_rx_config
=
498 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
500 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
504 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
506 for (i
= 20; i
> 0; i
--) {
508 * Check if the RTL8169 has completed writing to the specified
511 if (!(RTL_R32(PHYAR
) & 0x80000000))
517 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
521 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
523 for (i
= 20; i
> 0; i
--) {
525 * Check if the RTL8169 has completed retrieving data from
526 * the specified MII register.
528 if (RTL_R32(PHYAR
) & 0x80000000) {
529 value
= RTL_R32(PHYAR
) & 0xffff;
537 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
539 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
542 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
545 struct rtl8169_private
*tp
= netdev_priv(dev
);
546 void __iomem
*ioaddr
= tp
->mmio_addr
;
548 mdio_write(ioaddr
, location
, val
);
551 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
553 struct rtl8169_private
*tp
= netdev_priv(dev
);
554 void __iomem
*ioaddr
= tp
->mmio_addr
;
556 return mdio_read(ioaddr
, location
);
559 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
563 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
564 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
566 for (i
= 0; i
< 100; i
++) {
567 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
573 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
578 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
580 for (i
= 0; i
< 100; i
++) {
581 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
582 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
591 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
595 RTL_W32(CSIDR
, value
);
596 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
597 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
599 for (i
= 0; i
< 100; i
++) {
600 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
606 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
611 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
612 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
614 for (i
= 0; i
< 100; i
++) {
615 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
616 value
= RTL_R32(CSIDR
);
625 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
627 RTL_W16(IntrMask
, 0x0000);
629 RTL_W16(IntrStatus
, 0xffff);
632 static void rtl8169_asic_down(void __iomem
*ioaddr
)
634 RTL_W8(ChipCmd
, 0x00);
635 rtl8169_irq_mask_and_ack(ioaddr
);
639 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
641 return RTL_R32(TBICSR
) & TBIReset
;
644 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
646 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
649 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
651 return RTL_R32(TBICSR
) & TBILinkOk
;
654 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
656 return RTL_R8(PHYstatus
) & LinkStatus
;
659 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
661 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
664 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
668 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
669 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
672 static void rtl8169_check_link_status(struct net_device
*dev
,
673 struct rtl8169_private
*tp
,
674 void __iomem
*ioaddr
)
678 spin_lock_irqsave(&tp
->lock
, flags
);
679 if (tp
->link_ok(ioaddr
)) {
680 netif_carrier_on(dev
);
681 if (netif_msg_ifup(tp
))
682 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
684 if (netif_msg_ifdown(tp
))
685 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
686 netif_carrier_off(dev
);
688 spin_unlock_irqrestore(&tp
->lock
, flags
);
691 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
693 struct rtl8169_private
*tp
= netdev_priv(dev
);
694 void __iomem
*ioaddr
= tp
->mmio_addr
;
699 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
700 wol
->supported
= WAKE_ANY
;
702 spin_lock_irq(&tp
->lock
);
704 options
= RTL_R8(Config1
);
705 if (!(options
& PMEnable
))
708 options
= RTL_R8(Config3
);
709 if (options
& LinkUp
)
710 wol
->wolopts
|= WAKE_PHY
;
711 if (options
& MagicPacket
)
712 wol
->wolopts
|= WAKE_MAGIC
;
714 options
= RTL_R8(Config5
);
716 wol
->wolopts
|= WAKE_UCAST
;
718 wol
->wolopts
|= WAKE_BCAST
;
720 wol
->wolopts
|= WAKE_MCAST
;
723 spin_unlock_irq(&tp
->lock
);
726 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
728 struct rtl8169_private
*tp
= netdev_priv(dev
);
729 void __iomem
*ioaddr
= tp
->mmio_addr
;
736 { WAKE_ANY
, Config1
, PMEnable
},
737 { WAKE_PHY
, Config3
, LinkUp
},
738 { WAKE_MAGIC
, Config3
, MagicPacket
},
739 { WAKE_UCAST
, Config5
, UWF
},
740 { WAKE_BCAST
, Config5
, BWF
},
741 { WAKE_MCAST
, Config5
, MWF
},
742 { WAKE_ANY
, Config5
, LanWake
}
745 spin_lock_irq(&tp
->lock
);
747 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
749 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
750 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
751 if (wol
->wolopts
& cfg
[i
].opt
)
752 options
|= cfg
[i
].mask
;
753 RTL_W8(cfg
[i
].reg
, options
);
756 RTL_W8(Cfg9346
, Cfg9346_Lock
);
759 tp
->features
|= RTL_FEATURE_WOL
;
761 tp
->features
&= ~RTL_FEATURE_WOL
;
763 spin_unlock_irq(&tp
->lock
);
768 static void rtl8169_get_drvinfo(struct net_device
*dev
,
769 struct ethtool_drvinfo
*info
)
771 struct rtl8169_private
*tp
= netdev_priv(dev
);
773 strcpy(info
->driver
, MODULENAME
);
774 strcpy(info
->version
, RTL8169_VERSION
);
775 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
778 static int rtl8169_get_regs_len(struct net_device
*dev
)
780 return R8169_REGS_SIZE
;
783 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
784 u8 autoneg
, u16 speed
, u8 duplex
)
786 struct rtl8169_private
*tp
= netdev_priv(dev
);
787 void __iomem
*ioaddr
= tp
->mmio_addr
;
791 reg
= RTL_R32(TBICSR
);
792 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
793 (duplex
== DUPLEX_FULL
)) {
794 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
795 } else if (autoneg
== AUTONEG_ENABLE
)
796 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
798 if (netif_msg_link(tp
)) {
799 printk(KERN_WARNING
"%s: "
800 "incorrect speed setting refused in TBI mode\n",
809 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
810 u8 autoneg
, u16 speed
, u8 duplex
)
812 struct rtl8169_private
*tp
= netdev_priv(dev
);
813 void __iomem
*ioaddr
= tp
->mmio_addr
;
814 int auto_nego
, giga_ctrl
;
816 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
817 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
818 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
819 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
820 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
822 if (autoneg
== AUTONEG_ENABLE
) {
823 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
824 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
825 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
827 if (speed
== SPEED_10
)
828 auto_nego
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
829 else if (speed
== SPEED_100
)
830 auto_nego
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
831 else if (speed
== SPEED_1000
)
832 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
834 if (duplex
== DUPLEX_HALF
)
835 auto_nego
&= ~(ADVERTISE_10FULL
| ADVERTISE_100FULL
);
837 if (duplex
== DUPLEX_FULL
)
838 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_100HALF
);
840 /* This tweak comes straight from Realtek's driver. */
841 if ((speed
== SPEED_100
) && (duplex
== DUPLEX_HALF
) &&
842 ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
843 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
))) {
844 auto_nego
= ADVERTISE_100HALF
| ADVERTISE_CSMA
;
848 /* The 8100e/8101e/8102e do Fast Ethernet only. */
849 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_07
) ||
850 (tp
->mac_version
== RTL_GIGA_MAC_VER_08
) ||
851 (tp
->mac_version
== RTL_GIGA_MAC_VER_09
) ||
852 (tp
->mac_version
== RTL_GIGA_MAC_VER_10
) ||
853 (tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
854 (tp
->mac_version
== RTL_GIGA_MAC_VER_14
) ||
855 (tp
->mac_version
== RTL_GIGA_MAC_VER_15
) ||
856 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
857 if ((giga_ctrl
& (ADVERTISE_1000FULL
| ADVERTISE_1000HALF
)) &&
858 netif_msg_link(tp
)) {
859 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
862 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
865 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
867 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
868 (tp
->mac_version
== RTL_GIGA_MAC_VER_17
)) {
869 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
870 mdio_write(ioaddr
, 0x1f, 0x0000);
871 mdio_write(ioaddr
, 0x0e, 0x0000);
874 tp
->phy_auto_nego_reg
= auto_nego
;
875 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
877 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
878 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
879 mdio_write(ioaddr
, MII_BMCR
, BMCR_ANENABLE
| BMCR_ANRESTART
);
883 static int rtl8169_set_speed(struct net_device
*dev
,
884 u8 autoneg
, u16 speed
, u8 duplex
)
886 struct rtl8169_private
*tp
= netdev_priv(dev
);
889 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
891 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
892 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
897 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
899 struct rtl8169_private
*tp
= netdev_priv(dev
);
903 spin_lock_irqsave(&tp
->lock
, flags
);
904 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
905 spin_unlock_irqrestore(&tp
->lock
, flags
);
910 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
912 struct rtl8169_private
*tp
= netdev_priv(dev
);
914 return tp
->cp_cmd
& RxChkSum
;
917 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
919 struct rtl8169_private
*tp
= netdev_priv(dev
);
920 void __iomem
*ioaddr
= tp
->mmio_addr
;
923 spin_lock_irqsave(&tp
->lock
, flags
);
926 tp
->cp_cmd
|= RxChkSum
;
928 tp
->cp_cmd
&= ~RxChkSum
;
930 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
933 spin_unlock_irqrestore(&tp
->lock
, flags
);
938 #ifdef CONFIG_R8169_VLAN
940 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
943 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
944 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
947 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
948 struct vlan_group
*grp
)
950 struct rtl8169_private
*tp
= netdev_priv(dev
);
951 void __iomem
*ioaddr
= tp
->mmio_addr
;
954 spin_lock_irqsave(&tp
->lock
, flags
);
957 tp
->cp_cmd
|= RxVlan
;
959 tp
->cp_cmd
&= ~RxVlan
;
960 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
962 spin_unlock_irqrestore(&tp
->lock
, flags
);
965 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
968 u32 opts2
= le32_to_cpu(desc
->opts2
);
969 struct vlan_group
*vlgrp
= tp
->vlgrp
;
972 if (vlgrp
&& (opts2
& RxVlanTag
)) {
973 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
981 #else /* !CONFIG_R8169_VLAN */
983 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
989 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
997 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
999 struct rtl8169_private
*tp
= netdev_priv(dev
);
1000 void __iomem
*ioaddr
= tp
->mmio_addr
;
1004 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1005 cmd
->port
= PORT_FIBRE
;
1006 cmd
->transceiver
= XCVR_INTERNAL
;
1008 status
= RTL_R32(TBICSR
);
1009 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1010 cmd
->autoneg
= !!(status
& TBINwEnable
);
1012 cmd
->speed
= SPEED_1000
;
1013 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1018 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1020 struct rtl8169_private
*tp
= netdev_priv(dev
);
1022 return mii_ethtool_gset(&tp
->mii
, cmd
);
1025 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1027 struct rtl8169_private
*tp
= netdev_priv(dev
);
1028 unsigned long flags
;
1031 spin_lock_irqsave(&tp
->lock
, flags
);
1033 rc
= tp
->get_settings(dev
, cmd
);
1035 spin_unlock_irqrestore(&tp
->lock
, flags
);
1039 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1042 struct rtl8169_private
*tp
= netdev_priv(dev
);
1043 unsigned long flags
;
1045 if (regs
->len
> R8169_REGS_SIZE
)
1046 regs
->len
= R8169_REGS_SIZE
;
1048 spin_lock_irqsave(&tp
->lock
, flags
);
1049 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1050 spin_unlock_irqrestore(&tp
->lock
, flags
);
1053 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1055 struct rtl8169_private
*tp
= netdev_priv(dev
);
1057 return tp
->msg_enable
;
1060 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1062 struct rtl8169_private
*tp
= netdev_priv(dev
);
1064 tp
->msg_enable
= value
;
1067 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1074 "tx_single_collisions",
1075 "tx_multi_collisions",
1083 struct rtl8169_counters
{
1089 __le16 align_errors
;
1090 __le32 tx_one_collision
;
1091 __le32 tx_multi_collision
;
1093 __le64 rx_broadcast
;
1094 __le32 rx_multicast
;
1099 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1103 return ARRAY_SIZE(rtl8169_gstrings
);
1109 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1110 struct ethtool_stats
*stats
, u64
*data
)
1112 struct rtl8169_private
*tp
= netdev_priv(dev
);
1113 void __iomem
*ioaddr
= tp
->mmio_addr
;
1114 struct rtl8169_counters
*counters
;
1120 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1124 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1125 cmd
= (u64
)paddr
& DMA_32BIT_MASK
;
1126 RTL_W32(CounterAddrLow
, cmd
);
1127 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1129 while (RTL_R32(CounterAddrLow
) & CounterDump
) {
1130 if (msleep_interruptible(1))
1134 RTL_W32(CounterAddrLow
, 0);
1135 RTL_W32(CounterAddrHigh
, 0);
1137 data
[0] = le64_to_cpu(counters
->tx_packets
);
1138 data
[1] = le64_to_cpu(counters
->rx_packets
);
1139 data
[2] = le64_to_cpu(counters
->tx_errors
);
1140 data
[3] = le32_to_cpu(counters
->rx_errors
);
1141 data
[4] = le16_to_cpu(counters
->rx_missed
);
1142 data
[5] = le16_to_cpu(counters
->align_errors
);
1143 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1144 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1145 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1146 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1147 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1148 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1149 data
[12] = le16_to_cpu(counters
->tx_underun
);
1151 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1154 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1158 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1163 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1164 .get_drvinfo
= rtl8169_get_drvinfo
,
1165 .get_regs_len
= rtl8169_get_regs_len
,
1166 .get_link
= ethtool_op_get_link
,
1167 .get_settings
= rtl8169_get_settings
,
1168 .set_settings
= rtl8169_set_settings
,
1169 .get_msglevel
= rtl8169_get_msglevel
,
1170 .set_msglevel
= rtl8169_set_msglevel
,
1171 .get_rx_csum
= rtl8169_get_rx_csum
,
1172 .set_rx_csum
= rtl8169_set_rx_csum
,
1173 .set_tx_csum
= ethtool_op_set_tx_csum
,
1174 .set_sg
= ethtool_op_set_sg
,
1175 .set_tso
= ethtool_op_set_tso
,
1176 .get_regs
= rtl8169_get_regs
,
1177 .get_wol
= rtl8169_get_wol
,
1178 .set_wol
= rtl8169_set_wol
,
1179 .get_strings
= rtl8169_get_strings
,
1180 .get_sset_count
= rtl8169_get_sset_count
,
1181 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1184 static void rtl8169_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
,
1185 int bitnum
, int bitval
)
1189 val
= mdio_read(ioaddr
, reg
);
1190 val
= (bitval
== 1) ?
1191 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1192 mdio_write(ioaddr
, reg
, val
& 0xffff);
1195 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1196 void __iomem
*ioaddr
)
1199 * The driver currently handles the 8168Bf and the 8168Be identically
1200 * but they can be identified more specifically through the test below
1203 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1205 * Same thing for the 8101Eb and the 8101Ec:
1207 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1215 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1216 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1217 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1218 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20
},
1221 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1222 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1223 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1224 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1227 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1228 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1229 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1230 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1231 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1232 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1233 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1234 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1235 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1236 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1237 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1238 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1239 /* FIXME: where did these entries come from ? -- FR */
1240 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1241 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1244 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1245 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1246 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1247 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1248 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1249 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1251 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01
} /* Catch-all */
1255 reg
= RTL_R32(TxConfig
);
1256 while ((reg
& p
->mask
) != p
->val
)
1258 tp
->mac_version
= p
->mac_version
;
1260 if (p
->mask
== 0x00000000) {
1261 struct pci_dev
*pdev
= tp
->pci_dev
;
1263 dev_info(&pdev
->dev
, "unknown MAC (%08x)\n", reg
);
1267 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1269 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1277 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1280 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1285 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1288 u16 regs
[5]; /* Beware of bit-sign propagation */
1289 } phy_magic
[5] = { {
1290 { 0x0000, //w 4 15 12 0
1291 0x00a1, //w 3 15 0 00a1
1292 0x0008, //w 2 15 0 0008
1293 0x1020, //w 1 15 0 1020
1294 0x1000 } },{ //w 0 15 0 1000
1295 { 0x7000, //w 4 15 12 7
1296 0xff41, //w 3 15 0 ff41
1297 0xde60, //w 2 15 0 de60
1298 0x0140, //w 1 15 0 0140
1299 0x0077 } },{ //w 0 15 0 0077
1300 { 0xa000, //w 4 15 12 a
1301 0xdf01, //w 3 15 0 df01
1302 0xdf20, //w 2 15 0 df20
1303 0xff95, //w 1 15 0 ff95
1304 0xfa00 } },{ //w 0 15 0 fa00
1305 { 0xb000, //w 4 15 12 b
1306 0xff41, //w 3 15 0 ff41
1307 0xde20, //w 2 15 0 de20
1308 0x0140, //w 1 15 0 0140
1309 0x00bb } },{ //w 0 15 0 00bb
1310 { 0xf000, //w 4 15 12 f
1311 0xdf01, //w 3 15 0 df01
1312 0xdf20, //w 2 15 0 df20
1313 0xff95, //w 1 15 0 ff95
1314 0xbf00 } //w 0 15 0 bf00
1319 mdio_write(ioaddr
, 0x1f, 0x0001); //w 31 2 0 1
1320 mdio_write(ioaddr
, 0x15, 0x1000); //w 21 15 0 1000
1321 mdio_write(ioaddr
, 0x18, 0x65c7); //w 24 15 0 65c7
1322 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1324 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1327 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1328 mdio_write(ioaddr
, pos
, val
);
1330 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1331 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1332 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1334 mdio_write(ioaddr
, 0x1f, 0x0000); //w 31 2 0 0
1337 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1339 struct phy_reg phy_reg_init
[] = {
1345 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1348 static void rtl8168cp_hw_phy_config(void __iomem
*ioaddr
)
1350 struct phy_reg phy_reg_init
[] = {
1358 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1361 static void rtl8168c_hw_phy_config(void __iomem
*ioaddr
)
1363 struct phy_reg phy_reg_init
[] = {
1380 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1383 static void rtl8168cx_hw_phy_config(void __iomem
*ioaddr
)
1385 struct phy_reg phy_reg_init
[] = {
1396 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1399 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
1401 struct phy_reg phy_reg_init
[] = {
1408 mdio_write(ioaddr
, 0x1f, 0x0000);
1409 mdio_patch(ioaddr
, 0x11, 1 << 12);
1410 mdio_patch(ioaddr
, 0x19, 1 << 13);
1412 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1415 static void rtl_hw_phy_config(struct net_device
*dev
)
1417 struct rtl8169_private
*tp
= netdev_priv(dev
);
1418 void __iomem
*ioaddr
= tp
->mmio_addr
;
1420 rtl8169_print_mac_version(tp
);
1422 switch (tp
->mac_version
) {
1423 case RTL_GIGA_MAC_VER_01
:
1425 case RTL_GIGA_MAC_VER_02
:
1426 case RTL_GIGA_MAC_VER_03
:
1427 rtl8169s_hw_phy_config(ioaddr
);
1429 case RTL_GIGA_MAC_VER_04
:
1430 rtl8169sb_hw_phy_config(ioaddr
);
1432 case RTL_GIGA_MAC_VER_07
:
1433 case RTL_GIGA_MAC_VER_08
:
1434 case RTL_GIGA_MAC_VER_09
:
1435 rtl8102e_hw_phy_config(ioaddr
);
1437 case RTL_GIGA_MAC_VER_18
:
1438 rtl8168cp_hw_phy_config(ioaddr
);
1440 case RTL_GIGA_MAC_VER_19
:
1441 rtl8168c_hw_phy_config(ioaddr
);
1443 case RTL_GIGA_MAC_VER_20
:
1444 rtl8168cx_hw_phy_config(ioaddr
);
1451 static void rtl8169_phy_timer(unsigned long __opaque
)
1453 struct net_device
*dev
= (struct net_device
*)__opaque
;
1454 struct rtl8169_private
*tp
= netdev_priv(dev
);
1455 struct timer_list
*timer
= &tp
->timer
;
1456 void __iomem
*ioaddr
= tp
->mmio_addr
;
1457 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1459 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1461 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1464 spin_lock_irq(&tp
->lock
);
1466 if (tp
->phy_reset_pending(ioaddr
)) {
1468 * A busy loop could burn quite a few cycles on nowadays CPU.
1469 * Let's delay the execution of the timer for a few ticks.
1475 if (tp
->link_ok(ioaddr
))
1478 if (netif_msg_link(tp
))
1479 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1481 tp
->phy_reset_enable(ioaddr
);
1484 mod_timer(timer
, jiffies
+ timeout
);
1486 spin_unlock_irq(&tp
->lock
);
1489 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1491 struct rtl8169_private
*tp
= netdev_priv(dev
);
1492 struct timer_list
*timer
= &tp
->timer
;
1494 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1497 del_timer_sync(timer
);
1500 static inline void rtl8169_request_timer(struct net_device
*dev
)
1502 struct rtl8169_private
*tp
= netdev_priv(dev
);
1503 struct timer_list
*timer
= &tp
->timer
;
1505 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1508 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1511 #ifdef CONFIG_NET_POLL_CONTROLLER
1513 * Polling 'interrupt' - used by things like netconsole to send skbs
1514 * without having to re-enable interrupts. It's not called while
1515 * the interrupt routine is executing.
1517 static void rtl8169_netpoll(struct net_device
*dev
)
1519 struct rtl8169_private
*tp
= netdev_priv(dev
);
1520 struct pci_dev
*pdev
= tp
->pci_dev
;
1522 disable_irq(pdev
->irq
);
1523 rtl8169_interrupt(pdev
->irq
, dev
);
1524 enable_irq(pdev
->irq
);
1528 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1529 void __iomem
*ioaddr
)
1532 pci_release_regions(pdev
);
1533 pci_disable_device(pdev
);
1537 static void rtl8169_phy_reset(struct net_device
*dev
,
1538 struct rtl8169_private
*tp
)
1540 void __iomem
*ioaddr
= tp
->mmio_addr
;
1543 tp
->phy_reset_enable(ioaddr
);
1544 for (i
= 0; i
< 100; i
++) {
1545 if (!tp
->phy_reset_pending(ioaddr
))
1549 if (netif_msg_link(tp
))
1550 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1553 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1555 void __iomem
*ioaddr
= tp
->mmio_addr
;
1557 rtl_hw_phy_config(dev
);
1559 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1560 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1564 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1566 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1567 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1569 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1570 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1572 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1573 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1576 rtl8169_phy_reset(dev
, tp
);
1579 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1580 * only 8101. Don't panic.
1582 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1584 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1585 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1588 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
1590 void __iomem
*ioaddr
= tp
->mmio_addr
;
1594 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1595 high
= addr
[4] | (addr
[5] << 8);
1597 spin_lock_irq(&tp
->lock
);
1599 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1601 RTL_W32(MAC4
, high
);
1602 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1604 spin_unlock_irq(&tp
->lock
);
1607 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1609 struct rtl8169_private
*tp
= netdev_priv(dev
);
1610 struct sockaddr
*addr
= p
;
1612 if (!is_valid_ether_addr(addr
->sa_data
))
1613 return -EADDRNOTAVAIL
;
1615 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1617 rtl_rar_set(tp
, dev
->dev_addr
);
1622 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1624 struct rtl8169_private
*tp
= netdev_priv(dev
);
1625 struct mii_ioctl_data
*data
= if_mii(ifr
);
1627 if (!netif_running(dev
))
1632 data
->phy_id
= 32; /* Internal PHY */
1636 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1640 if (!capable(CAP_NET_ADMIN
))
1642 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1648 static const struct rtl_cfg_info
{
1649 void (*hw_start
)(struct net_device
*);
1650 unsigned int region
;
1655 } rtl_cfg_infos
[] = {
1657 .hw_start
= rtl_hw_start_8169
,
1660 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1661 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1662 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1663 .features
= RTL_FEATURE_GMII
1666 .hw_start
= rtl_hw_start_8168
,
1669 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1670 TxErr
| TxOK
| RxOK
| RxErr
,
1671 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
1672 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
1675 .hw_start
= rtl_hw_start_8101
,
1678 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1679 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1680 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1681 .features
= RTL_FEATURE_MSI
1685 /* Cfg9346_Unlock assumed. */
1686 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
1687 const struct rtl_cfg_info
*cfg
)
1692 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
1693 if (cfg
->features
& RTL_FEATURE_MSI
) {
1694 if (pci_enable_msi(pdev
)) {
1695 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
1698 msi
= RTL_FEATURE_MSI
;
1701 RTL_W8(Config2
, cfg2
);
1705 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
1707 if (tp
->features
& RTL_FEATURE_MSI
) {
1708 pci_disable_msi(pdev
);
1709 tp
->features
&= ~RTL_FEATURE_MSI
;
1713 static int rtl_eeprom_read(struct pci_dev
*pdev
, int cap
, int addr
, __le32
*val
)
1715 int ret
, count
= 100;
1719 ret
= pci_write_config_word(pdev
, cap
+ PCI_VPD_ADDR
, addr
);
1725 ret
= pci_read_config_word(pdev
, cap
+ PCI_VPD_ADDR
, &status
);
1728 } while (!(status
& PCI_VPD_ADDR_F
) && --count
);
1730 if (!(status
& PCI_VPD_ADDR_F
))
1733 ret
= pci_read_config_dword(pdev
, cap
+ PCI_VPD_DATA
, &value
);
1737 *val
= cpu_to_le32(value
);
1742 static void rtl_init_mac_address(struct rtl8169_private
*tp
,
1743 void __iomem
*ioaddr
)
1745 struct pci_dev
*pdev
= tp
->pci_dev
;
1749 DECLARE_MAC_BUF(buf
);
1751 cfg1
= RTL_R8(Config1
);
1752 if (!(cfg1
& VPD
)) {
1753 dprintk("VPD access not enabled, enabling\n");
1754 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1755 RTL_W8(Config1
, cfg1
| VPD
);
1756 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1759 vpd_cap
= pci_find_capability(pdev
, PCI_CAP_ID_VPD
);
1763 /* MAC address is stored in EEPROM at offset 0x0e
1764 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1765 * address as defined in the PCI 2.2 Specifications, but the VPD data
1766 * is always consecutive 4-byte data starting from the VPD address
1769 if (rtl_eeprom_read(pdev
, vpd_cap
, 0x000e, (__le32
*)&mac
[0]) < 0 ||
1770 rtl_eeprom_read(pdev
, vpd_cap
, 0x0012, (__le32
*)&mac
[4]) < 0) {
1771 dprintk("Reading MAC address from EEPROM failed\n");
1775 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf
, mac
));
1777 /* Write MAC address */
1778 rtl_rar_set(tp
, mac
);
1781 static int __devinit
1782 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1784 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
1785 const unsigned int region
= cfg
->region
;
1786 struct rtl8169_private
*tp
;
1787 struct mii_if_info
*mii
;
1788 struct net_device
*dev
;
1789 void __iomem
*ioaddr
;
1793 if (netif_msg_drv(&debug
)) {
1794 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
1795 MODULENAME
, RTL8169_VERSION
);
1798 dev
= alloc_etherdev(sizeof (*tp
));
1800 if (netif_msg_drv(&debug
))
1801 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
1806 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1807 tp
= netdev_priv(dev
);
1810 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
1814 mii
->mdio_read
= rtl_mdio_read
;
1815 mii
->mdio_write
= rtl_mdio_write
;
1816 mii
->phy_id_mask
= 0x1f;
1817 mii
->reg_num_mask
= 0x1f;
1818 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
1820 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1821 rc
= pci_enable_device(pdev
);
1823 if (netif_msg_probe(tp
))
1824 dev_err(&pdev
->dev
, "enable failure\n");
1825 goto err_out_free_dev_1
;
1828 rc
= pci_set_mwi(pdev
);
1830 goto err_out_disable_2
;
1832 /* make sure PCI base addr 1 is MMIO */
1833 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
1834 if (netif_msg_probe(tp
)) {
1836 "region #%d not an MMIO resource, aborting\n",
1843 /* check for weird/broken PCI region reporting */
1844 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
1845 if (netif_msg_probe(tp
)) {
1847 "Invalid PCI region size(s), aborting\n");
1853 rc
= pci_request_regions(pdev
, MODULENAME
);
1855 if (netif_msg_probe(tp
))
1856 dev_err(&pdev
->dev
, "could not request regions.\n");
1860 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
1862 if ((sizeof(dma_addr_t
) > 4) &&
1863 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) && use_dac
) {
1864 tp
->cp_cmd
|= PCIDAC
;
1865 dev
->features
|= NETIF_F_HIGHDMA
;
1867 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1869 if (netif_msg_probe(tp
)) {
1871 "DMA configuration failed.\n");
1873 goto err_out_free_res_4
;
1877 pci_set_master(pdev
);
1879 /* ioremap MMIO region */
1880 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
1882 if (netif_msg_probe(tp
))
1883 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
1885 goto err_out_free_res_4
;
1888 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1889 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
1890 dev_info(&pdev
->dev
, "no PCI Express capability\n");
1892 /* Unneeded ? Don't mess with Mrs. Murphy. */
1893 rtl8169_irq_mask_and_ack(ioaddr
);
1895 /* Soft reset the chip. */
1896 RTL_W8(ChipCmd
, CmdReset
);
1898 /* Check that the chip has finished the reset. */
1899 for (i
= 0; i
< 100; i
++) {
1900 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
1902 msleep_interruptible(1);
1905 /* Identify chip attached to board */
1906 rtl8169_get_mac_version(tp
, ioaddr
);
1908 rtl8169_print_mac_version(tp
);
1910 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
1911 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
1914 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
1915 /* Unknown chip: assume array element #0, original RTL-8169 */
1916 if (netif_msg_probe(tp
)) {
1917 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1918 "unknown chip version, assuming %s\n",
1919 rtl_chip_info
[0].name
);
1925 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1926 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
1927 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
1928 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
1929 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1931 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
1932 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
1933 tp
->set_speed
= rtl8169_set_speed_tbi
;
1934 tp
->get_settings
= rtl8169_gset_tbi
;
1935 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
1936 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
1937 tp
->link_ok
= rtl8169_tbi_link_ok
;
1939 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
1941 tp
->set_speed
= rtl8169_set_speed_xmii
;
1942 tp
->get_settings
= rtl8169_gset_xmii
;
1943 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
1944 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
1945 tp
->link_ok
= rtl8169_xmii_link_ok
;
1947 dev
->do_ioctl
= rtl8169_ioctl
;
1950 /* Read MAC address from EEPROM */
1951 rtl_init_mac_address(tp
, ioaddr
);
1953 /* Get MAC address */
1954 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
1955 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
1956 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1958 dev
->open
= rtl8169_open
;
1959 dev
->hard_start_xmit
= rtl8169_start_xmit
;
1960 dev
->get_stats
= rtl8169_get_stats
;
1961 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
1962 dev
->stop
= rtl8169_close
;
1963 dev
->tx_timeout
= rtl8169_tx_timeout
;
1964 dev
->set_multicast_list
= rtl_set_rx_mode
;
1965 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
1966 dev
->irq
= pdev
->irq
;
1967 dev
->base_addr
= (unsigned long) ioaddr
;
1968 dev
->change_mtu
= rtl8169_change_mtu
;
1969 dev
->set_mac_address
= rtl_set_mac_address
;
1971 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
1973 #ifdef CONFIG_R8169_VLAN
1974 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1975 dev
->vlan_rx_register
= rtl8169_vlan_rx_register
;
1978 #ifdef CONFIG_NET_POLL_CONTROLLER
1979 dev
->poll_controller
= rtl8169_netpoll
;
1982 tp
->intr_mask
= 0xffff;
1983 tp
->mmio_addr
= ioaddr
;
1984 tp
->align
= cfg
->align
;
1985 tp
->hw_start
= cfg
->hw_start
;
1986 tp
->intr_event
= cfg
->intr_event
;
1987 tp
->napi_event
= cfg
->napi_event
;
1989 init_timer(&tp
->timer
);
1990 tp
->timer
.data
= (unsigned long) dev
;
1991 tp
->timer
.function
= rtl8169_phy_timer
;
1993 spin_lock_init(&tp
->lock
);
1995 rc
= register_netdev(dev
);
1999 pci_set_drvdata(pdev
, dev
);
2001 if (netif_msg_probe(tp
)) {
2002 u32 xid
= RTL_R32(TxConfig
) & 0x7cf0f8ff;
2004 printk(KERN_INFO
"%s: %s at 0x%lx, "
2005 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2006 "XID %08x IRQ %d\n",
2008 rtl_chip_info
[tp
->chipset
].name
,
2010 dev
->dev_addr
[0], dev
->dev_addr
[1],
2011 dev
->dev_addr
[2], dev
->dev_addr
[3],
2012 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
2015 rtl8169_init_phy(dev
, tp
);
2021 rtl_disable_msi(pdev
, tp
);
2024 pci_release_regions(pdev
);
2026 pci_clear_mwi(pdev
);
2028 pci_disable_device(pdev
);
2034 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
2036 struct net_device
*dev
= pci_get_drvdata(pdev
);
2037 struct rtl8169_private
*tp
= netdev_priv(dev
);
2039 flush_scheduled_work();
2041 unregister_netdev(dev
);
2042 rtl_disable_msi(pdev
, tp
);
2043 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
2044 pci_set_drvdata(pdev
, NULL
);
2047 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
2048 struct net_device
*dev
)
2050 unsigned int mtu
= dev
->mtu
;
2052 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
2055 static int rtl8169_open(struct net_device
*dev
)
2057 struct rtl8169_private
*tp
= netdev_priv(dev
);
2058 struct pci_dev
*pdev
= tp
->pci_dev
;
2059 int retval
= -ENOMEM
;
2062 rtl8169_set_rxbufsize(tp
, dev
);
2065 * Rx and Tx desscriptors needs 256 bytes alignment.
2066 * pci_alloc_consistent provides more.
2068 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
2070 if (!tp
->TxDescArray
)
2073 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
2075 if (!tp
->RxDescArray
)
2078 retval
= rtl8169_init_ring(dev
);
2082 INIT_DELAYED_WORK(&tp
->task
, NULL
);
2086 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
2087 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
2090 goto err_release_ring_2
;
2092 napi_enable(&tp
->napi
);
2096 rtl8169_request_timer(dev
);
2098 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2103 rtl8169_rx_clear(tp
);
2105 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
2108 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
2113 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
2115 /* Disable interrupts */
2116 rtl8169_irq_mask_and_ack(ioaddr
);
2118 /* Reset the chipset */
2119 RTL_W8(ChipCmd
, CmdReset
);
2125 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
2127 void __iomem
*ioaddr
= tp
->mmio_addr
;
2128 u32 cfg
= rtl8169_rx_config
;
2130 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
2131 RTL_W32(RxConfig
, cfg
);
2133 /* Set DMA burst size and Interframe Gap Time */
2134 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2135 (InterFrameGap
<< TxInterFrameGapShift
));
2138 static void rtl_hw_start(struct net_device
*dev
)
2140 struct rtl8169_private
*tp
= netdev_priv(dev
);
2141 void __iomem
*ioaddr
= tp
->mmio_addr
;
2144 /* Soft reset the chip. */
2145 RTL_W8(ChipCmd
, CmdReset
);
2147 /* Check that the chip has finished the reset. */
2148 for (i
= 0; i
< 100; i
++) {
2149 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2151 msleep_interruptible(1);
2156 netif_start_queue(dev
);
2160 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
2161 void __iomem
*ioaddr
)
2164 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2165 * register to be written before TxDescAddrLow to work.
2166 * Switching from MMIO to I/O access fixes the issue as well.
2168 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
2169 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_32BIT_MASK
);
2170 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
2171 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_32BIT_MASK
);
2174 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
2178 cmd
= RTL_R16(CPlusCmd
);
2179 RTL_W16(CPlusCmd
, cmd
);
2183 static void rtl_set_rx_max_size(void __iomem
*ioaddr
)
2185 /* Low hurts. Let's disable the filtering. */
2186 RTL_W16(RxMaxSize
, 16383);
2189 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
2196 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
2197 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
2198 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
2199 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
2204 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
2205 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
2206 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
2207 RTL_W32(0x7c, p
->val
);
2213 static void rtl_hw_start_8169(struct net_device
*dev
)
2215 struct rtl8169_private
*tp
= netdev_priv(dev
);
2216 void __iomem
*ioaddr
= tp
->mmio_addr
;
2217 struct pci_dev
*pdev
= tp
->pci_dev
;
2219 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
2220 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
2221 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
2224 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2225 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2226 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2227 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2228 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2229 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2231 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2233 rtl_set_rx_max_size(ioaddr
);
2235 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2236 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2237 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2238 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2239 rtl_set_rx_tx_config_registers(tp
);
2241 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2243 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2244 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2245 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2246 "Bit-3 and bit-14 MUST be 1\n");
2247 tp
->cp_cmd
|= (1 << 14);
2250 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2252 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
2255 * Undocumented corner. Supposedly:
2256 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2258 RTL_W16(IntrMitigate
, 0x0000);
2260 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2262 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2263 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2264 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2265 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2266 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2267 rtl_set_rx_tx_config_registers(tp
);
2270 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2272 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2275 RTL_W32(RxMissed
, 0);
2277 rtl_set_rx_mode(dev
);
2279 /* no early-rx interrupts */
2280 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2282 /* Enable all known interrupts by setting the interrupt mask. */
2283 RTL_W16(IntrMask
, tp
->intr_event
);
2286 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
2288 struct net_device
*dev
= pci_get_drvdata(pdev
);
2289 struct rtl8169_private
*tp
= netdev_priv(dev
);
2290 int cap
= tp
->pcie_cap
;
2295 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2296 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
2297 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2301 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
2305 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
2306 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
2310 unsigned int offset
;
2315 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
2320 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
2321 rtl_ephy_write(ioaddr
, e
->offset
, w
);
2326 static void rtl_hw_start_8168(struct net_device
*dev
)
2328 struct rtl8169_private
*tp
= netdev_priv(dev
);
2329 void __iomem
*ioaddr
= tp
->mmio_addr
;
2330 struct pci_dev
*pdev
= tp
->pci_dev
;
2332 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2334 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2336 rtl_set_rx_max_size(ioaddr
);
2338 rtl_set_rx_tx_config_registers(tp
);
2340 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2342 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2344 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2346 RTL_W16(IntrMitigate
, 0x5151);
2348 /* Work around for RxFIFO overflow. */
2349 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2350 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2351 tp
->intr_event
&= ~RxOverflow
;
2354 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2356 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2360 rtl_set_rx_mode(dev
);
2362 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2364 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2366 RTL_W16(IntrMask
, tp
->intr_event
);
2369 #define R810X_CPCMD_QUIRK_MASK (\
2381 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2383 static struct ephy_info e_info_8102e_1
[] = {
2384 { 0x01, 0, 0x6e65 },
2385 { 0x02, 0, 0x091f },
2386 { 0x03, 0, 0xc2f9 },
2387 { 0x06, 0, 0xafb5 },
2388 { 0x07, 0, 0x0e00 },
2389 { 0x19, 0, 0xec80 },
2390 { 0x01, 0, 0x2e65 },
2395 rtl_csi_access_enable(ioaddr
);
2397 RTL_W8(DBG_REG
, FIX_NAK_1
);
2399 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2402 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
2403 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2405 cfg1
= RTL_R8(Config1
);
2406 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
2407 RTL_W8(Config1
, cfg1
& ~LEDS0
);
2409 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2411 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
2414 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2416 rtl_csi_access_enable(ioaddr
);
2418 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2420 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
2421 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2423 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2426 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2428 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2430 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
2433 static void rtl_hw_start_8101(struct net_device
*dev
)
2435 struct rtl8169_private
*tp
= netdev_priv(dev
);
2436 void __iomem
*ioaddr
= tp
->mmio_addr
;
2437 struct pci_dev
*pdev
= tp
->pci_dev
;
2439 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2440 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2441 int cap
= tp
->pcie_cap
;
2444 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
2445 PCI_EXP_DEVCTL_NOSNOOP_EN
);
2449 switch (tp
->mac_version
) {
2450 case RTL_GIGA_MAC_VER_07
:
2451 rtl_hw_start_8102e_1(ioaddr
, pdev
);
2454 case RTL_GIGA_MAC_VER_08
:
2455 rtl_hw_start_8102e_3(ioaddr
, pdev
);
2458 case RTL_GIGA_MAC_VER_09
:
2459 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2463 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2465 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2467 rtl_set_rx_max_size(ioaddr
);
2469 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2471 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2473 RTL_W16(IntrMitigate
, 0x0000);
2475 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2477 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2478 rtl_set_rx_tx_config_registers(tp
);
2480 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2484 rtl_set_rx_mode(dev
);
2486 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2488 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2490 RTL_W16(IntrMask
, tp
->intr_event
);
2493 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
2495 struct rtl8169_private
*tp
= netdev_priv(dev
);
2498 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2503 if (!netif_running(dev
))
2508 rtl8169_set_rxbufsize(tp
, dev
);
2510 ret
= rtl8169_init_ring(dev
);
2514 napi_enable(&tp
->napi
);
2518 rtl8169_request_timer(dev
);
2524 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
2526 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
2527 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2530 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
2531 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2533 struct pci_dev
*pdev
= tp
->pci_dev
;
2535 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2536 PCI_DMA_FROMDEVICE
);
2537 dev_kfree_skb(*sk_buff
);
2539 rtl8169_make_unusable_by_asic(desc
);
2542 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2544 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2546 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2549 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2552 desc
->addr
= cpu_to_le64(mapping
);
2554 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
2557 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
2558 struct net_device
*dev
,
2559 struct RxDesc
*desc
, int rx_buf_sz
,
2562 struct sk_buff
*skb
;
2566 pad
= align
? align
: NET_IP_ALIGN
;
2568 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
2572 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
2574 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
2575 PCI_DMA_FROMDEVICE
);
2577 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
2582 rtl8169_make_unusable_by_asic(desc
);
2586 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
2590 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
2591 if (tp
->Rx_skbuff
[i
]) {
2592 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
2593 tp
->RxDescArray
+ i
);
2598 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
2603 for (cur
= start
; end
- cur
!= 0; cur
++) {
2604 struct sk_buff
*skb
;
2605 unsigned int i
= cur
% NUM_RX_DESC
;
2607 WARN_ON((s32
)(end
- cur
) < 0);
2609 if (tp
->Rx_skbuff
[i
])
2612 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
2613 tp
->RxDescArray
+ i
,
2614 tp
->rx_buf_sz
, tp
->align
);
2618 tp
->Rx_skbuff
[i
] = skb
;
2623 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
2625 desc
->opts1
|= cpu_to_le32(RingEnd
);
2628 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
2630 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
2633 static int rtl8169_init_ring(struct net_device
*dev
)
2635 struct rtl8169_private
*tp
= netdev_priv(dev
);
2637 rtl8169_init_ring_indexes(tp
);
2639 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
2640 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
2642 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
2645 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
2650 rtl8169_rx_clear(tp
);
2654 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
2655 struct TxDesc
*desc
)
2657 unsigned int len
= tx_skb
->len
;
2659 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
2666 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
2670 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
2671 unsigned int entry
= i
% NUM_TX_DESC
;
2672 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2673 unsigned int len
= tx_skb
->len
;
2676 struct sk_buff
*skb
= tx_skb
->skb
;
2678 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
2679 tp
->TxDescArray
+ entry
);
2684 tp
->dev
->stats
.tx_dropped
++;
2687 tp
->cur_tx
= tp
->dirty_tx
= 0;
2690 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
2692 struct rtl8169_private
*tp
= netdev_priv(dev
);
2694 PREPARE_DELAYED_WORK(&tp
->task
, task
);
2695 schedule_delayed_work(&tp
->task
, 4);
2698 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
2700 struct rtl8169_private
*tp
= netdev_priv(dev
);
2701 void __iomem
*ioaddr
= tp
->mmio_addr
;
2703 synchronize_irq(dev
->irq
);
2705 /* Wait for any pending NAPI task to complete */
2706 napi_disable(&tp
->napi
);
2708 rtl8169_irq_mask_and_ack(ioaddr
);
2710 tp
->intr_mask
= 0xffff;
2711 RTL_W16(IntrMask
, tp
->intr_event
);
2712 napi_enable(&tp
->napi
);
2715 static void rtl8169_reinit_task(struct work_struct
*work
)
2717 struct rtl8169_private
*tp
=
2718 container_of(work
, struct rtl8169_private
, task
.work
);
2719 struct net_device
*dev
= tp
->dev
;
2724 if (!netif_running(dev
))
2727 rtl8169_wait_for_quiescence(dev
);
2730 ret
= rtl8169_open(dev
);
2731 if (unlikely(ret
< 0)) {
2732 if (net_ratelimit() && netif_msg_drv(tp
)) {
2733 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
2734 " Rescheduling.\n", dev
->name
, ret
);
2736 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
2743 static void rtl8169_reset_task(struct work_struct
*work
)
2745 struct rtl8169_private
*tp
=
2746 container_of(work
, struct rtl8169_private
, task
.work
);
2747 struct net_device
*dev
= tp
->dev
;
2751 if (!netif_running(dev
))
2754 rtl8169_wait_for_quiescence(dev
);
2756 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
2757 rtl8169_tx_clear(tp
);
2759 if (tp
->dirty_rx
== tp
->cur_rx
) {
2760 rtl8169_init_ring_indexes(tp
);
2762 netif_wake_queue(dev
);
2763 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2765 if (net_ratelimit() && netif_msg_intr(tp
)) {
2766 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
2769 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2776 static void rtl8169_tx_timeout(struct net_device
*dev
)
2778 struct rtl8169_private
*tp
= netdev_priv(dev
);
2780 rtl8169_hw_reset(tp
->mmio_addr
);
2782 /* Let's wait a bit while any (async) irq lands on */
2783 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2786 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
2789 struct skb_shared_info
*info
= skb_shinfo(skb
);
2790 unsigned int cur_frag
, entry
;
2791 struct TxDesc
* uninitialized_var(txd
);
2794 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
2795 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
2800 entry
= (entry
+ 1) % NUM_TX_DESC
;
2802 txd
= tp
->TxDescArray
+ entry
;
2804 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
2805 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
2807 /* anti gcc 2.95.3 bugware (sic) */
2808 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2810 txd
->opts1
= cpu_to_le32(status
);
2811 txd
->addr
= cpu_to_le64(mapping
);
2813 tp
->tx_skb
[entry
].len
= len
;
2817 tp
->tx_skb
[entry
].skb
= skb
;
2818 txd
->opts1
|= cpu_to_le32(LastFrag
);
2824 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
2826 if (dev
->features
& NETIF_F_TSO
) {
2827 u32 mss
= skb_shinfo(skb
)->gso_size
;
2830 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
2832 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2833 const struct iphdr
*ip
= ip_hdr(skb
);
2835 if (ip
->protocol
== IPPROTO_TCP
)
2836 return IPCS
| TCPCS
;
2837 else if (ip
->protocol
== IPPROTO_UDP
)
2838 return IPCS
| UDPCS
;
2839 WARN_ON(1); /* we need a WARN() */
2844 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2846 struct rtl8169_private
*tp
= netdev_priv(dev
);
2847 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
2848 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
2849 void __iomem
*ioaddr
= tp
->mmio_addr
;
2853 int ret
= NETDEV_TX_OK
;
2855 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
2856 if (netif_msg_drv(tp
)) {
2858 "%s: BUG! Tx Ring full when queue awake!\n",
2864 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
2867 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
2869 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
2871 len
= skb_headlen(skb
);
2876 if (unlikely(len
< ETH_ZLEN
)) {
2877 if (skb_padto(skb
, ETH_ZLEN
))
2878 goto err_update_stats
;
2882 opts1
|= FirstFrag
| LastFrag
;
2883 tp
->tx_skb
[entry
].skb
= skb
;
2886 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2888 tp
->tx_skb
[entry
].len
= len
;
2889 txd
->addr
= cpu_to_le64(mapping
);
2890 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
2894 /* anti gcc 2.95.3 bugware (sic) */
2895 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2896 txd
->opts1
= cpu_to_le32(status
);
2898 dev
->trans_start
= jiffies
;
2900 tp
->cur_tx
+= frags
+ 1;
2904 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
2906 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
2907 netif_stop_queue(dev
);
2909 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
2910 netif_wake_queue(dev
);
2917 netif_stop_queue(dev
);
2918 ret
= NETDEV_TX_BUSY
;
2920 dev
->stats
.tx_dropped
++;
2924 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
2926 struct rtl8169_private
*tp
= netdev_priv(dev
);
2927 struct pci_dev
*pdev
= tp
->pci_dev
;
2928 void __iomem
*ioaddr
= tp
->mmio_addr
;
2929 u16 pci_status
, pci_cmd
;
2931 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2932 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
2934 if (netif_msg_intr(tp
)) {
2936 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2937 dev
->name
, pci_cmd
, pci_status
);
2941 * The recovery sequence below admits a very elaborated explanation:
2942 * - it seems to work;
2943 * - I did not see what else could be done;
2944 * - it makes iop3xx happy.
2946 * Feel free to adjust to your needs.
2948 if (pdev
->broken_parity_status
)
2949 pci_cmd
&= ~PCI_COMMAND_PARITY
;
2951 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
2953 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2955 pci_write_config_word(pdev
, PCI_STATUS
,
2956 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
2957 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
2958 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
2960 /* The infamous DAC f*ckup only happens at boot time */
2961 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
2962 if (netif_msg_intr(tp
))
2963 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
2964 tp
->cp_cmd
&= ~PCIDAC
;
2965 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2966 dev
->features
&= ~NETIF_F_HIGHDMA
;
2969 rtl8169_hw_reset(ioaddr
);
2971 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
2974 static void rtl8169_tx_interrupt(struct net_device
*dev
,
2975 struct rtl8169_private
*tp
,
2976 void __iomem
*ioaddr
)
2978 unsigned int dirty_tx
, tx_left
;
2980 dirty_tx
= tp
->dirty_tx
;
2982 tx_left
= tp
->cur_tx
- dirty_tx
;
2984 while (tx_left
> 0) {
2985 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
2986 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2987 u32 len
= tx_skb
->len
;
2991 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
2992 if (status
& DescOwn
)
2995 dev
->stats
.tx_bytes
+= len
;
2996 dev
->stats
.tx_packets
++;
2998 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
3000 if (status
& LastFrag
) {
3001 dev_kfree_skb_irq(tx_skb
->skb
);
3008 if (tp
->dirty_tx
!= dirty_tx
) {
3009 tp
->dirty_tx
= dirty_tx
;
3011 if (netif_queue_stopped(dev
) &&
3012 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
3013 netif_wake_queue(dev
);
3016 * 8168 hack: TxPoll requests are lost when the Tx packets are
3017 * too close. Let's kick an extra TxPoll request when a burst
3018 * of start_xmit activity is detected (if it is not detected,
3019 * it is slow enough). -- FR
3022 if (tp
->cur_tx
!= dirty_tx
)
3023 RTL_W8(TxPoll
, NPQ
);
3027 static inline int rtl8169_fragmented_frame(u32 status
)
3029 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
3032 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
3034 u32 opts1
= le32_to_cpu(desc
->opts1
);
3035 u32 status
= opts1
& RxProtoMask
;
3037 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
3038 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
3039 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
3040 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3042 skb
->ip_summed
= CHECKSUM_NONE
;
3045 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
3046 struct rtl8169_private
*tp
, int pkt_size
,
3049 struct sk_buff
*skb
;
3052 if (pkt_size
>= rx_copybreak
)
3055 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
3059 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
3060 PCI_DMA_FROMDEVICE
);
3061 skb_reserve(skb
, NET_IP_ALIGN
);
3062 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
3069 static int rtl8169_rx_interrupt(struct net_device
*dev
,
3070 struct rtl8169_private
*tp
,
3071 void __iomem
*ioaddr
, u32 budget
)
3073 unsigned int cur_rx
, rx_left
;
3074 unsigned int delta
, count
;
3076 cur_rx
= tp
->cur_rx
;
3077 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
3078 rx_left
= min(rx_left
, budget
);
3080 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
3081 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
3082 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
3086 status
= le32_to_cpu(desc
->opts1
);
3088 if (status
& DescOwn
)
3090 if (unlikely(status
& RxRES
)) {
3091 if (netif_msg_rx_err(tp
)) {
3093 "%s: Rx ERROR. status = %08x\n",
3096 dev
->stats
.rx_errors
++;
3097 if (status
& (RxRWT
| RxRUNT
))
3098 dev
->stats
.rx_length_errors
++;
3100 dev
->stats
.rx_crc_errors
++;
3101 if (status
& RxFOVF
) {
3102 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3103 dev
->stats
.rx_fifo_errors
++;
3105 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3107 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
3108 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
3109 int pkt_size
= (status
& 0x00001FFF) - 4;
3110 struct pci_dev
*pdev
= tp
->pci_dev
;
3113 * The driver does not support incoming fragmented
3114 * frames. They are seen as a symptom of over-mtu
3117 if (unlikely(rtl8169_fragmented_frame(status
))) {
3118 dev
->stats
.rx_dropped
++;
3119 dev
->stats
.rx_length_errors
++;
3120 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3124 rtl8169_rx_csum(skb
, desc
);
3126 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
3127 pci_dma_sync_single_for_device(pdev
, addr
,
3128 pkt_size
, PCI_DMA_FROMDEVICE
);
3129 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3131 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
3132 PCI_DMA_FROMDEVICE
);
3133 tp
->Rx_skbuff
[entry
] = NULL
;
3136 skb_put(skb
, pkt_size
);
3137 skb
->protocol
= eth_type_trans(skb
, dev
);
3139 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
3140 netif_receive_skb(skb
);
3142 dev
->last_rx
= jiffies
;
3143 dev
->stats
.rx_bytes
+= pkt_size
;
3144 dev
->stats
.rx_packets
++;
3147 /* Work around for AMD plateform. */
3148 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
3149 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
3155 count
= cur_rx
- tp
->cur_rx
;
3156 tp
->cur_rx
= cur_rx
;
3158 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
3159 if (!delta
&& count
&& netif_msg_intr(tp
))
3160 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
3161 tp
->dirty_rx
+= delta
;
3164 * FIXME: until there is periodic timer to try and refill the ring,
3165 * a temporary shortage may definitely kill the Rx process.
3166 * - disable the asic to try and avoid an overflow and kick it again
3168 * - how do others driver handle this condition (Uh oh...).
3170 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
3171 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
3176 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
3178 struct net_device
*dev
= dev_instance
;
3179 struct rtl8169_private
*tp
= netdev_priv(dev
);
3180 void __iomem
*ioaddr
= tp
->mmio_addr
;
3184 status
= RTL_R16(IntrStatus
);
3186 /* hotplug/major error/no more work/shared irq */
3187 if ((status
== 0xffff) || !status
)
3192 if (unlikely(!netif_running(dev
))) {
3193 rtl8169_asic_down(ioaddr
);
3197 status
&= tp
->intr_mask
;
3199 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
3201 if (!(status
& tp
->intr_event
))
3204 /* Work around for rx fifo overflow */
3205 if (unlikely(status
& RxFIFOOver
) &&
3206 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
3207 netif_stop_queue(dev
);
3208 rtl8169_tx_timeout(dev
);
3212 if (unlikely(status
& SYSErr
)) {
3213 rtl8169_pcierr_interrupt(dev
);
3217 if (status
& LinkChg
)
3218 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3220 if (status
& tp
->napi_event
) {
3221 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
3222 tp
->intr_mask
= ~tp
->napi_event
;
3224 if (likely(netif_rx_schedule_prep(dev
, &tp
->napi
)))
3225 __netif_rx_schedule(dev
, &tp
->napi
);
3226 else if (netif_msg_intr(tp
)) {
3227 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
3232 return IRQ_RETVAL(handled
);
3235 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
3237 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
3238 struct net_device
*dev
= tp
->dev
;
3239 void __iomem
*ioaddr
= tp
->mmio_addr
;
3242 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
3243 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
3245 if (work_done
< budget
) {
3246 netif_rx_complete(dev
, napi
);
3247 tp
->intr_mask
= 0xffff;
3249 * 20040426: the barrier is not strictly required but the
3250 * behavior of the irq handler could be less predictable
3251 * without it. Btw, the lack of flush for the posted pci
3252 * write is safe - FR
3255 RTL_W16(IntrMask
, tp
->intr_event
);
3261 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
3263 struct rtl8169_private
*tp
= netdev_priv(dev
);
3265 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
3268 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
3269 RTL_W32(RxMissed
, 0);
3272 static void rtl8169_down(struct net_device
*dev
)
3274 struct rtl8169_private
*tp
= netdev_priv(dev
);
3275 void __iomem
*ioaddr
= tp
->mmio_addr
;
3276 unsigned int intrmask
;
3278 rtl8169_delete_timer(dev
);
3280 netif_stop_queue(dev
);
3282 napi_disable(&tp
->napi
);
3285 spin_lock_irq(&tp
->lock
);
3287 rtl8169_asic_down(ioaddr
);
3289 rtl8169_rx_missed(dev
, ioaddr
);
3291 spin_unlock_irq(&tp
->lock
);
3293 synchronize_irq(dev
->irq
);
3295 /* Give a racing hard_start_xmit a few cycles to complete. */
3296 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3299 * And now for the 50k$ question: are IRQ disabled or not ?
3301 * Two paths lead here:
3303 * -> netif_running() is available to sync the current code and the
3304 * IRQ handler. See rtl8169_interrupt for details.
3305 * 2) dev->change_mtu
3306 * -> rtl8169_poll can not be issued again and re-enable the
3307 * interruptions. Let's simply issue the IRQ down sequence again.
3309 * No loop if hotpluged or major error (0xffff).
3311 intrmask
= RTL_R16(IntrMask
);
3312 if (intrmask
&& (intrmask
!= 0xffff))
3315 rtl8169_tx_clear(tp
);
3317 rtl8169_rx_clear(tp
);
3320 static int rtl8169_close(struct net_device
*dev
)
3322 struct rtl8169_private
*tp
= netdev_priv(dev
);
3323 struct pci_dev
*pdev
= tp
->pci_dev
;
3327 free_irq(dev
->irq
, dev
);
3329 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3331 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3333 tp
->TxDescArray
= NULL
;
3334 tp
->RxDescArray
= NULL
;
3339 static void rtl_set_rx_mode(struct net_device
*dev
)
3341 struct rtl8169_private
*tp
= netdev_priv(dev
);
3342 void __iomem
*ioaddr
= tp
->mmio_addr
;
3343 unsigned long flags
;
3344 u32 mc_filter
[2]; /* Multicast hash filter */
3348 if (dev
->flags
& IFF_PROMISC
) {
3349 /* Unconditionally log net taps. */
3350 if (netif_msg_link(tp
)) {
3351 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3355 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3357 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3358 } else if ((dev
->mc_count
> multicast_filter_limit
)
3359 || (dev
->flags
& IFF_ALLMULTI
)) {
3360 /* Too many to filter perfectly -- accept all multicasts. */
3361 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3362 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3364 struct dev_mc_list
*mclist
;
3367 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3368 mc_filter
[1] = mc_filter
[0] = 0;
3369 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3370 i
++, mclist
= mclist
->next
) {
3371 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3372 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3373 rx_mode
|= AcceptMulticast
;
3377 spin_lock_irqsave(&tp
->lock
, flags
);
3379 tmp
= rtl8169_rx_config
| rx_mode
|
3380 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3382 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3383 u32 data
= mc_filter
[0];
3385 mc_filter
[0] = swab32(mc_filter
[1]);
3386 mc_filter
[1] = swab32(data
);
3389 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3390 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3392 RTL_W32(RxConfig
, tmp
);
3394 spin_unlock_irqrestore(&tp
->lock
, flags
);
3398 * rtl8169_get_stats - Get rtl8169 read/write statistics
3399 * @dev: The Ethernet Device to get statistics for
3401 * Get TX/RX statistics for rtl8169
3403 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3405 struct rtl8169_private
*tp
= netdev_priv(dev
);
3406 void __iomem
*ioaddr
= tp
->mmio_addr
;
3407 unsigned long flags
;
3409 if (netif_running(dev
)) {
3410 spin_lock_irqsave(&tp
->lock
, flags
);
3411 rtl8169_rx_missed(dev
, ioaddr
);
3412 spin_unlock_irqrestore(&tp
->lock
, flags
);
3420 static int rtl8169_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3422 struct net_device
*dev
= pci_get_drvdata(pdev
);
3423 struct rtl8169_private
*tp
= netdev_priv(dev
);
3424 void __iomem
*ioaddr
= tp
->mmio_addr
;
3426 if (!netif_running(dev
))
3427 goto out_pci_suspend
;
3429 netif_device_detach(dev
);
3430 netif_stop_queue(dev
);
3432 spin_lock_irq(&tp
->lock
);
3434 rtl8169_asic_down(ioaddr
);
3436 rtl8169_rx_missed(dev
, ioaddr
);
3438 spin_unlock_irq(&tp
->lock
);
3441 pci_save_state(pdev
);
3442 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
),
3443 (tp
->features
& RTL_FEATURE_WOL
) ? 1 : 0);
3444 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3449 static int rtl8169_resume(struct pci_dev
*pdev
)
3451 struct net_device
*dev
= pci_get_drvdata(pdev
);
3453 pci_set_power_state(pdev
, PCI_D0
);
3454 pci_restore_state(pdev
);
3455 pci_enable_wake(pdev
, PCI_D0
, 0);
3457 if (!netif_running(dev
))
3460 netif_device_attach(dev
);
3462 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3467 #endif /* CONFIG_PM */
3469 static struct pci_driver rtl8169_pci_driver
= {
3471 .id_table
= rtl8169_pci_tbl
,
3472 .probe
= rtl8169_init_one
,
3473 .remove
= __devexit_p(rtl8169_remove_one
),
3475 .suspend
= rtl8169_suspend
,
3476 .resume
= rtl8169_resume
,
3480 static int __init
rtl8169_init_module(void)
3482 return pci_register_driver(&rtl8169_pci_driver
);
3485 static void __exit
rtl8169_cleanup_module(void)
3487 pci_unregister_driver(&rtl8169_pci_driver
);
3490 module_init(rtl8169_init_module
);
3491 module_exit(rtl8169_cleanup_module
);