2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__FUNCTION__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work
= 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit
= 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
94 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
100 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
101 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
102 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
103 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
104 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
105 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
106 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
107 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
108 RTL_GIGA_MAC_VER_20
= 0x14 // 8168C
111 #define _R(NAME,MAC,MASK) \
112 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
114 static const struct {
117 u32 RxConfigMask
; /* Clears the bits supported by this chip */
118 } rtl_chip_info
[] = {
119 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
120 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
121 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
122 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
123 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
124 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
125 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
126 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
127 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
128 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
129 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
130 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
131 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
132 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
133 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
134 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880) // PCI-E
144 static void rtl_hw_start_8169(struct net_device
*);
145 static void rtl_hw_start_8168(struct net_device
*);
146 static void rtl_hw_start_8101(struct net_device
*);
148 static struct pci_device_id rtl8169_pci_tbl
[] = {
149 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
150 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
151 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
152 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
153 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
154 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
155 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
156 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
157 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
158 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
160 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
164 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
166 static int rx_copybreak
= 200;
173 MAC0
= 0, /* Ethernet hardware address. */
175 MAR0
= 8, /* Multicast filter. */
176 CounterAddrLow
= 0x10,
177 CounterAddrHigh
= 0x14,
178 TxDescStartAddrLow
= 0x20,
179 TxDescStartAddrHigh
= 0x24,
180 TxHDescStartAddrLow
= 0x28,
181 TxHDescStartAddrHigh
= 0x2c,
207 RxDescAddrLow
= 0xe4,
208 RxDescAddrHigh
= 0xe8,
211 FuncEventMask
= 0xf4,
212 FuncPresetState
= 0xf8,
213 FuncForceEvent
= 0xfc,
216 enum rtl_register_content
{
217 /* InterruptStatusBits */
221 TxDescUnavail
= 0x0080,
243 /* TXPoll register p.5 */
244 HPQ
= 0x80, /* Poll cmd on the high prio queue */
245 NPQ
= 0x40, /* Poll cmd on the low prio queue */
246 FSWInt
= 0x01, /* Forced software interrupt */
250 Cfg9346_Unlock
= 0xc0,
255 AcceptBroadcast
= 0x08,
256 AcceptMulticast
= 0x04,
258 AcceptAllPhys
= 0x01,
265 TxInterFrameGapShift
= 24,
266 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
268 /* Config1 register p.24 */
269 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
270 PMEnable
= (1 << 0), /* Power Management Enable */
272 /* Config2 register p. 25 */
273 PCI_Clock_66MHz
= 0x01,
274 PCI_Clock_33MHz
= 0x00,
276 /* Config3 register p.25 */
277 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
278 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
280 /* Config5 register p.27 */
281 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
282 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
283 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
284 LanWake
= (1 << 1), /* LanWake enable/disable */
285 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
288 TBIReset
= 0x80000000,
289 TBILoopback
= 0x40000000,
290 TBINwEnable
= 0x20000000,
291 TBINwRestart
= 0x10000000,
292 TBILinkOk
= 0x02000000,
293 TBINwComplete
= 0x01000000,
296 PktCntrDisable
= (1 << 7), // 8168
301 INTT_0
= 0x0000, // 8168
302 INTT_1
= 0x0001, // 8168
303 INTT_2
= 0x0002, // 8168
304 INTT_3
= 0x0003, // 8168
306 /* rtl8169_PHYstatus */
317 TBILinkOK
= 0x02000000,
319 /* DumpCounterCommand */
323 enum desc_status_bit
{
324 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
325 RingEnd
= (1 << 30), /* End of descriptor ring */
326 FirstFrag
= (1 << 29), /* First segment of a packet */
327 LastFrag
= (1 << 28), /* Final segment of a packet */
330 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
331 MSSShift
= 16, /* MSS value position */
332 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
333 IPCS
= (1 << 18), /* Calculate IP checksum */
334 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
335 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
336 TxVlanTag
= (1 << 17), /* Add VLAN tag */
339 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
340 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
342 #define RxProtoUDP (PID1)
343 #define RxProtoTCP (PID0)
344 #define RxProtoIP (PID1 | PID0)
345 #define RxProtoMask RxProtoIP
347 IPFail
= (1 << 16), /* IP checksum failed */
348 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
349 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
350 RxVlanTag
= (1 << 16), /* VLAN tag available */
353 #define RsvdMask 0x3fffc000
370 u8 __pad
[sizeof(void *) - sizeof(u32
)];
374 RTL_FEATURE_WOL
= (1 << 0),
375 RTL_FEATURE_MSI
= (1 << 1),
376 RTL_FEATURE_GMII
= (1 << 2),
379 struct rtl8169_private
{
380 void __iomem
*mmio_addr
; /* memory map physical address */
381 struct pci_dev
*pci_dev
; /* Index of PCI device */
382 struct net_device
*dev
;
383 struct napi_struct napi
;
384 spinlock_t lock
; /* spin lock flag */
388 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
389 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
392 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
393 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
394 dma_addr_t TxPhyAddr
;
395 dma_addr_t RxPhyAddr
;
396 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
397 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
400 struct timer_list timer
;
405 int phy_auto_nego_reg
;
406 int phy_1000_ctrl_reg
;
407 #ifdef CONFIG_R8169_VLAN
408 struct vlan_group
*vlgrp
;
410 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
411 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
412 void (*phy_reset_enable
)(void __iomem
*);
413 void (*hw_start
)(struct net_device
*);
414 unsigned int (*phy_reset_pending
)(void __iomem
*);
415 unsigned int (*link_ok
)(void __iomem
*);
417 struct delayed_work task
;
420 struct mii_if_info mii
;
423 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
424 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
425 module_param(rx_copybreak
, int, 0);
426 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
427 module_param(use_dac
, int, 0);
428 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
429 module_param_named(debug
, debug
.msg_enable
, int, 0);
430 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
431 MODULE_LICENSE("GPL");
432 MODULE_VERSION(RTL8169_VERSION
);
434 static int rtl8169_open(struct net_device
*dev
);
435 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
436 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
437 static int rtl8169_init_ring(struct net_device
*dev
);
438 static void rtl_hw_start(struct net_device
*dev
);
439 static int rtl8169_close(struct net_device
*dev
);
440 static void rtl_set_rx_mode(struct net_device
*dev
);
441 static void rtl8169_tx_timeout(struct net_device
*dev
);
442 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
443 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
444 void __iomem
*, u32 budget
);
445 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
446 static void rtl8169_down(struct net_device
*dev
);
447 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
448 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
450 static const unsigned int rtl8169_rx_config
=
451 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
453 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
457 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
459 for (i
= 20; i
> 0; i
--) {
461 * Check if the RTL8169 has completed writing to the specified
464 if (!(RTL_R32(PHYAR
) & 0x80000000))
470 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
474 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
476 for (i
= 20; i
> 0; i
--) {
478 * Check if the RTL8169 has completed retrieving data from
479 * the specified MII register.
481 if (RTL_R32(PHYAR
) & 0x80000000) {
482 value
= RTL_R32(PHYAR
) & 0xffff;
490 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
493 struct rtl8169_private
*tp
= netdev_priv(dev
);
494 void __iomem
*ioaddr
= tp
->mmio_addr
;
496 mdio_write(ioaddr
, location
, val
);
499 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
501 struct rtl8169_private
*tp
= netdev_priv(dev
);
502 void __iomem
*ioaddr
= tp
->mmio_addr
;
504 return mdio_read(ioaddr
, location
);
507 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
509 RTL_W16(IntrMask
, 0x0000);
511 RTL_W16(IntrStatus
, 0xffff);
514 static void rtl8169_asic_down(void __iomem
*ioaddr
)
516 RTL_W8(ChipCmd
, 0x00);
517 rtl8169_irq_mask_and_ack(ioaddr
);
521 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
523 return RTL_R32(TBICSR
) & TBIReset
;
526 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
528 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
531 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
533 return RTL_R32(TBICSR
) & TBILinkOk
;
536 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
538 return RTL_R8(PHYstatus
) & LinkStatus
;
541 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
543 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
546 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
550 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
551 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
554 static void rtl8169_check_link_status(struct net_device
*dev
,
555 struct rtl8169_private
*tp
,
556 void __iomem
*ioaddr
)
560 spin_lock_irqsave(&tp
->lock
, flags
);
561 if (tp
->link_ok(ioaddr
)) {
562 netif_carrier_on(dev
);
563 if (netif_msg_ifup(tp
))
564 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
566 if (netif_msg_ifdown(tp
))
567 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
568 netif_carrier_off(dev
);
570 spin_unlock_irqrestore(&tp
->lock
, flags
);
573 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
575 struct rtl8169_private
*tp
= netdev_priv(dev
);
576 void __iomem
*ioaddr
= tp
->mmio_addr
;
581 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
582 wol
->supported
= WAKE_ANY
;
584 spin_lock_irq(&tp
->lock
);
586 options
= RTL_R8(Config1
);
587 if (!(options
& PMEnable
))
590 options
= RTL_R8(Config3
);
591 if (options
& LinkUp
)
592 wol
->wolopts
|= WAKE_PHY
;
593 if (options
& MagicPacket
)
594 wol
->wolopts
|= WAKE_MAGIC
;
596 options
= RTL_R8(Config5
);
598 wol
->wolopts
|= WAKE_UCAST
;
600 wol
->wolopts
|= WAKE_BCAST
;
602 wol
->wolopts
|= WAKE_MCAST
;
605 spin_unlock_irq(&tp
->lock
);
608 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
610 struct rtl8169_private
*tp
= netdev_priv(dev
);
611 void __iomem
*ioaddr
= tp
->mmio_addr
;
618 { WAKE_ANY
, Config1
, PMEnable
},
619 { WAKE_PHY
, Config3
, LinkUp
},
620 { WAKE_MAGIC
, Config3
, MagicPacket
},
621 { WAKE_UCAST
, Config5
, UWF
},
622 { WAKE_BCAST
, Config5
, BWF
},
623 { WAKE_MCAST
, Config5
, MWF
},
624 { WAKE_ANY
, Config5
, LanWake
}
627 spin_lock_irq(&tp
->lock
);
629 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
631 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
632 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
633 if (wol
->wolopts
& cfg
[i
].opt
)
634 options
|= cfg
[i
].mask
;
635 RTL_W8(cfg
[i
].reg
, options
);
638 RTL_W8(Cfg9346
, Cfg9346_Lock
);
641 tp
->features
|= RTL_FEATURE_WOL
;
643 tp
->features
&= ~RTL_FEATURE_WOL
;
645 spin_unlock_irq(&tp
->lock
);
650 static void rtl8169_get_drvinfo(struct net_device
*dev
,
651 struct ethtool_drvinfo
*info
)
653 struct rtl8169_private
*tp
= netdev_priv(dev
);
655 strcpy(info
->driver
, MODULENAME
);
656 strcpy(info
->version
, RTL8169_VERSION
);
657 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
660 static int rtl8169_get_regs_len(struct net_device
*dev
)
662 return R8169_REGS_SIZE
;
665 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
666 u8 autoneg
, u16 speed
, u8 duplex
)
668 struct rtl8169_private
*tp
= netdev_priv(dev
);
669 void __iomem
*ioaddr
= tp
->mmio_addr
;
673 reg
= RTL_R32(TBICSR
);
674 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
675 (duplex
== DUPLEX_FULL
)) {
676 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
677 } else if (autoneg
== AUTONEG_ENABLE
)
678 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
680 if (netif_msg_link(tp
)) {
681 printk(KERN_WARNING
"%s: "
682 "incorrect speed setting refused in TBI mode\n",
691 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
692 u8 autoneg
, u16 speed
, u8 duplex
)
694 struct rtl8169_private
*tp
= netdev_priv(dev
);
695 void __iomem
*ioaddr
= tp
->mmio_addr
;
696 int auto_nego
, giga_ctrl
;
698 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
699 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
700 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
701 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
702 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
704 if (autoneg
== AUTONEG_ENABLE
) {
705 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
706 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
707 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
709 if (speed
== SPEED_10
)
710 auto_nego
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
711 else if (speed
== SPEED_100
)
712 auto_nego
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
713 else if (speed
== SPEED_1000
)
714 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
716 if (duplex
== DUPLEX_HALF
)
717 auto_nego
&= ~(ADVERTISE_10FULL
| ADVERTISE_100FULL
);
719 if (duplex
== DUPLEX_FULL
)
720 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_100HALF
);
722 /* This tweak comes straight from Realtek's driver. */
723 if ((speed
== SPEED_100
) && (duplex
== DUPLEX_HALF
) &&
724 ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
725 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
))) {
726 auto_nego
= ADVERTISE_100HALF
| ADVERTISE_CSMA
;
730 /* The 8100e/8101e do Fast Ethernet only. */
731 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
732 (tp
->mac_version
== RTL_GIGA_MAC_VER_14
) ||
733 (tp
->mac_version
== RTL_GIGA_MAC_VER_15
) ||
734 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
735 if ((giga_ctrl
& (ADVERTISE_1000FULL
| ADVERTISE_1000HALF
)) &&
736 netif_msg_link(tp
)) {
737 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
740 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
743 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
745 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
746 (tp
->mac_version
== RTL_GIGA_MAC_VER_17
)) {
747 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
748 mdio_write(ioaddr
, 0x1f, 0x0000);
749 mdio_write(ioaddr
, 0x0e, 0x0000);
752 tp
->phy_auto_nego_reg
= auto_nego
;
753 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
755 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
756 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
757 mdio_write(ioaddr
, MII_BMCR
, BMCR_ANENABLE
| BMCR_ANRESTART
);
761 static int rtl8169_set_speed(struct net_device
*dev
,
762 u8 autoneg
, u16 speed
, u8 duplex
)
764 struct rtl8169_private
*tp
= netdev_priv(dev
);
767 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
769 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
770 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
775 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
777 struct rtl8169_private
*tp
= netdev_priv(dev
);
781 spin_lock_irqsave(&tp
->lock
, flags
);
782 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
783 spin_unlock_irqrestore(&tp
->lock
, flags
);
788 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
790 struct rtl8169_private
*tp
= netdev_priv(dev
);
792 return tp
->cp_cmd
& RxChkSum
;
795 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
797 struct rtl8169_private
*tp
= netdev_priv(dev
);
798 void __iomem
*ioaddr
= tp
->mmio_addr
;
801 spin_lock_irqsave(&tp
->lock
, flags
);
804 tp
->cp_cmd
|= RxChkSum
;
806 tp
->cp_cmd
&= ~RxChkSum
;
808 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
811 spin_unlock_irqrestore(&tp
->lock
, flags
);
816 #ifdef CONFIG_R8169_VLAN
818 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
821 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
822 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
825 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
826 struct vlan_group
*grp
)
828 struct rtl8169_private
*tp
= netdev_priv(dev
);
829 void __iomem
*ioaddr
= tp
->mmio_addr
;
832 spin_lock_irqsave(&tp
->lock
, flags
);
835 tp
->cp_cmd
|= RxVlan
;
837 tp
->cp_cmd
&= ~RxVlan
;
838 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
840 spin_unlock_irqrestore(&tp
->lock
, flags
);
843 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
846 u32 opts2
= le32_to_cpu(desc
->opts2
);
847 struct vlan_group
*vlgrp
= tp
->vlgrp
;
850 if (vlgrp
&& (opts2
& RxVlanTag
)) {
851 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
859 #else /* !CONFIG_R8169_VLAN */
861 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
867 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
875 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
877 struct rtl8169_private
*tp
= netdev_priv(dev
);
878 void __iomem
*ioaddr
= tp
->mmio_addr
;
882 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
883 cmd
->port
= PORT_FIBRE
;
884 cmd
->transceiver
= XCVR_INTERNAL
;
886 status
= RTL_R32(TBICSR
);
887 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
888 cmd
->autoneg
= !!(status
& TBINwEnable
);
890 cmd
->speed
= SPEED_1000
;
891 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
896 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
898 struct rtl8169_private
*tp
= netdev_priv(dev
);
900 return mii_ethtool_gset(&tp
->mii
, cmd
);
903 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
905 struct rtl8169_private
*tp
= netdev_priv(dev
);
909 spin_lock_irqsave(&tp
->lock
, flags
);
911 rc
= tp
->get_settings(dev
, cmd
);
913 spin_unlock_irqrestore(&tp
->lock
, flags
);
917 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
920 struct rtl8169_private
*tp
= netdev_priv(dev
);
923 if (regs
->len
> R8169_REGS_SIZE
)
924 regs
->len
= R8169_REGS_SIZE
;
926 spin_lock_irqsave(&tp
->lock
, flags
);
927 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
928 spin_unlock_irqrestore(&tp
->lock
, flags
);
931 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
933 struct rtl8169_private
*tp
= netdev_priv(dev
);
935 return tp
->msg_enable
;
938 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
940 struct rtl8169_private
*tp
= netdev_priv(dev
);
942 tp
->msg_enable
= value
;
945 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
952 "tx_single_collisions",
953 "tx_multi_collisions",
961 struct rtl8169_counters
{
968 __le32 tx_one_collision
;
969 __le32 tx_multi_collision
;
977 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
981 return ARRAY_SIZE(rtl8169_gstrings
);
987 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
988 struct ethtool_stats
*stats
, u64
*data
)
990 struct rtl8169_private
*tp
= netdev_priv(dev
);
991 void __iomem
*ioaddr
= tp
->mmio_addr
;
992 struct rtl8169_counters
*counters
;
998 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1002 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1003 cmd
= (u64
)paddr
& DMA_32BIT_MASK
;
1004 RTL_W32(CounterAddrLow
, cmd
);
1005 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1007 while (RTL_R32(CounterAddrLow
) & CounterDump
) {
1008 if (msleep_interruptible(1))
1012 RTL_W32(CounterAddrLow
, 0);
1013 RTL_W32(CounterAddrHigh
, 0);
1015 data
[0] = le64_to_cpu(counters
->tx_packets
);
1016 data
[1] = le64_to_cpu(counters
->rx_packets
);
1017 data
[2] = le64_to_cpu(counters
->tx_errors
);
1018 data
[3] = le32_to_cpu(counters
->rx_errors
);
1019 data
[4] = le16_to_cpu(counters
->rx_missed
);
1020 data
[5] = le16_to_cpu(counters
->align_errors
);
1021 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1022 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1023 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1024 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1025 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1026 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1027 data
[12] = le16_to_cpu(counters
->tx_underun
);
1029 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1032 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1036 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1041 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1042 .get_drvinfo
= rtl8169_get_drvinfo
,
1043 .get_regs_len
= rtl8169_get_regs_len
,
1044 .get_link
= ethtool_op_get_link
,
1045 .get_settings
= rtl8169_get_settings
,
1046 .set_settings
= rtl8169_set_settings
,
1047 .get_msglevel
= rtl8169_get_msglevel
,
1048 .set_msglevel
= rtl8169_set_msglevel
,
1049 .get_rx_csum
= rtl8169_get_rx_csum
,
1050 .set_rx_csum
= rtl8169_set_rx_csum
,
1051 .set_tx_csum
= ethtool_op_set_tx_csum
,
1052 .set_sg
= ethtool_op_set_sg
,
1053 .set_tso
= ethtool_op_set_tso
,
1054 .get_regs
= rtl8169_get_regs
,
1055 .get_wol
= rtl8169_get_wol
,
1056 .set_wol
= rtl8169_set_wol
,
1057 .get_strings
= rtl8169_get_strings
,
1058 .get_sset_count
= rtl8169_get_sset_count
,
1059 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1062 static void rtl8169_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
,
1063 int bitnum
, int bitval
)
1067 val
= mdio_read(ioaddr
, reg
);
1068 val
= (bitval
== 1) ?
1069 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1070 mdio_write(ioaddr
, reg
, val
& 0xffff);
1073 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1074 void __iomem
*ioaddr
)
1077 * The driver currently handles the 8168Bf and the 8168Be identically
1078 * but they can be identified more specifically through the test below
1081 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1083 * Same thing for the 8101Eb and the 8101Ec:
1085 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1093 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1094 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1095 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1096 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20
},
1099 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1100 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1101 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1102 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1105 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1106 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1107 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1108 /* FIXME: where did these entries come from ? -- FR */
1109 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1110 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1113 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1114 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1115 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1116 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1117 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1118 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1120 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01
} /* Catch-all */
1124 reg
= RTL_R32(TxConfig
);
1125 while ((reg
& p
->mask
) != p
->val
)
1127 tp
->mac_version
= p
->mac_version
;
1129 if (p
->mask
== 0x00000000) {
1130 struct pci_dev
*pdev
= tp
->pci_dev
;
1132 dev_info(&pdev
->dev
, "unknown MAC (%08x)\n", reg
);
1136 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1138 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1146 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1149 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1154 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1157 u16 regs
[5]; /* Beware of bit-sign propagation */
1158 } phy_magic
[5] = { {
1159 { 0x0000, //w 4 15 12 0
1160 0x00a1, //w 3 15 0 00a1
1161 0x0008, //w 2 15 0 0008
1162 0x1020, //w 1 15 0 1020
1163 0x1000 } },{ //w 0 15 0 1000
1164 { 0x7000, //w 4 15 12 7
1165 0xff41, //w 3 15 0 ff41
1166 0xde60, //w 2 15 0 de60
1167 0x0140, //w 1 15 0 0140
1168 0x0077 } },{ //w 0 15 0 0077
1169 { 0xa000, //w 4 15 12 a
1170 0xdf01, //w 3 15 0 df01
1171 0xdf20, //w 2 15 0 df20
1172 0xff95, //w 1 15 0 ff95
1173 0xfa00 } },{ //w 0 15 0 fa00
1174 { 0xb000, //w 4 15 12 b
1175 0xff41, //w 3 15 0 ff41
1176 0xde20, //w 2 15 0 de20
1177 0x0140, //w 1 15 0 0140
1178 0x00bb } },{ //w 0 15 0 00bb
1179 { 0xf000, //w 4 15 12 f
1180 0xdf01, //w 3 15 0 df01
1181 0xdf20, //w 2 15 0 df20
1182 0xff95, //w 1 15 0 ff95
1183 0xbf00 } //w 0 15 0 bf00
1188 mdio_write(ioaddr
, 0x1f, 0x0001); //w 31 2 0 1
1189 mdio_write(ioaddr
, 0x15, 0x1000); //w 21 15 0 1000
1190 mdio_write(ioaddr
, 0x18, 0x65c7); //w 24 15 0 65c7
1191 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1193 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1196 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1197 mdio_write(ioaddr
, pos
, val
);
1199 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1200 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1201 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1203 mdio_write(ioaddr
, 0x1f, 0x0000); //w 31 2 0 0
1206 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1208 struct phy_reg phy_reg_init
[] = {
1214 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1217 static void rtl8168cp_hw_phy_config(void __iomem
*ioaddr
)
1219 struct phy_reg phy_reg_init
[] = {
1227 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1230 static void rtl8168c_hw_phy_config(void __iomem
*ioaddr
)
1232 struct phy_reg phy_reg_init
[] = {
1249 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1252 static void rtl8168cx_hw_phy_config(void __iomem
*ioaddr
)
1254 struct phy_reg phy_reg_init
[] = {
1265 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1268 static void rtl_hw_phy_config(struct net_device
*dev
)
1270 struct rtl8169_private
*tp
= netdev_priv(dev
);
1271 void __iomem
*ioaddr
= tp
->mmio_addr
;
1273 rtl8169_print_mac_version(tp
);
1275 switch (tp
->mac_version
) {
1276 case RTL_GIGA_MAC_VER_01
:
1278 case RTL_GIGA_MAC_VER_02
:
1279 case RTL_GIGA_MAC_VER_03
:
1280 rtl8169s_hw_phy_config(ioaddr
);
1282 case RTL_GIGA_MAC_VER_04
:
1283 rtl8169sb_hw_phy_config(ioaddr
);
1285 case RTL_GIGA_MAC_VER_18
:
1286 rtl8168cp_hw_phy_config(ioaddr
);
1288 case RTL_GIGA_MAC_VER_19
:
1289 rtl8168c_hw_phy_config(ioaddr
);
1291 case RTL_GIGA_MAC_VER_20
:
1292 rtl8168cx_hw_phy_config(ioaddr
);
1299 static void rtl8169_phy_timer(unsigned long __opaque
)
1301 struct net_device
*dev
= (struct net_device
*)__opaque
;
1302 struct rtl8169_private
*tp
= netdev_priv(dev
);
1303 struct timer_list
*timer
= &tp
->timer
;
1304 void __iomem
*ioaddr
= tp
->mmio_addr
;
1305 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1307 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1309 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1312 spin_lock_irq(&tp
->lock
);
1314 if (tp
->phy_reset_pending(ioaddr
)) {
1316 * A busy loop could burn quite a few cycles on nowadays CPU.
1317 * Let's delay the execution of the timer for a few ticks.
1323 if (tp
->link_ok(ioaddr
))
1326 if (netif_msg_link(tp
))
1327 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1329 tp
->phy_reset_enable(ioaddr
);
1332 mod_timer(timer
, jiffies
+ timeout
);
1334 spin_unlock_irq(&tp
->lock
);
1337 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1339 struct rtl8169_private
*tp
= netdev_priv(dev
);
1340 struct timer_list
*timer
= &tp
->timer
;
1342 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1345 del_timer_sync(timer
);
1348 static inline void rtl8169_request_timer(struct net_device
*dev
)
1350 struct rtl8169_private
*tp
= netdev_priv(dev
);
1351 struct timer_list
*timer
= &tp
->timer
;
1353 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1356 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1359 #ifdef CONFIG_NET_POLL_CONTROLLER
1361 * Polling 'interrupt' - used by things like netconsole to send skbs
1362 * without having to re-enable interrupts. It's not called while
1363 * the interrupt routine is executing.
1365 static void rtl8169_netpoll(struct net_device
*dev
)
1367 struct rtl8169_private
*tp
= netdev_priv(dev
);
1368 struct pci_dev
*pdev
= tp
->pci_dev
;
1370 disable_irq(pdev
->irq
);
1371 rtl8169_interrupt(pdev
->irq
, dev
);
1372 enable_irq(pdev
->irq
);
1376 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1377 void __iomem
*ioaddr
)
1380 pci_release_regions(pdev
);
1381 pci_disable_device(pdev
);
1385 static void rtl8169_phy_reset(struct net_device
*dev
,
1386 struct rtl8169_private
*tp
)
1388 void __iomem
*ioaddr
= tp
->mmio_addr
;
1391 tp
->phy_reset_enable(ioaddr
);
1392 for (i
= 0; i
< 100; i
++) {
1393 if (!tp
->phy_reset_pending(ioaddr
))
1397 if (netif_msg_link(tp
))
1398 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1401 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1403 void __iomem
*ioaddr
= tp
->mmio_addr
;
1405 rtl_hw_phy_config(dev
);
1407 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1408 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1412 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1414 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1415 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1417 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1418 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1420 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1421 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1424 rtl8169_phy_reset(dev
, tp
);
1427 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1428 * only 8101. Don't panic.
1430 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1432 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1433 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1436 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
1438 void __iomem
*ioaddr
= tp
->mmio_addr
;
1442 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1443 high
= addr
[4] | (addr
[5] << 8);
1445 spin_lock_irq(&tp
->lock
);
1447 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1449 RTL_W32(MAC4
, high
);
1450 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1452 spin_unlock_irq(&tp
->lock
);
1455 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1457 struct rtl8169_private
*tp
= netdev_priv(dev
);
1458 struct sockaddr
*addr
= p
;
1460 if (!is_valid_ether_addr(addr
->sa_data
))
1461 return -EADDRNOTAVAIL
;
1463 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1465 rtl_rar_set(tp
, dev
->dev_addr
);
1470 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1472 struct rtl8169_private
*tp
= netdev_priv(dev
);
1473 struct mii_ioctl_data
*data
= if_mii(ifr
);
1475 if (!netif_running(dev
))
1480 data
->phy_id
= 32; /* Internal PHY */
1484 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1488 if (!capable(CAP_NET_ADMIN
))
1490 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1496 static const struct rtl_cfg_info
{
1497 void (*hw_start
)(struct net_device
*);
1498 unsigned int region
;
1503 } rtl_cfg_infos
[] = {
1505 .hw_start
= rtl_hw_start_8169
,
1508 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1509 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1510 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1511 .features
= RTL_FEATURE_GMII
1514 .hw_start
= rtl_hw_start_8168
,
1517 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1518 TxErr
| TxOK
| RxOK
| RxErr
,
1519 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
1520 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
1523 .hw_start
= rtl_hw_start_8101
,
1526 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1527 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1528 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1529 .features
= RTL_FEATURE_MSI
1533 /* Cfg9346_Unlock assumed. */
1534 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
1535 const struct rtl_cfg_info
*cfg
)
1540 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
1541 if (cfg
->features
& RTL_FEATURE_MSI
) {
1542 if (pci_enable_msi(pdev
)) {
1543 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
1546 msi
= RTL_FEATURE_MSI
;
1549 RTL_W8(Config2
, cfg2
);
1553 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
1555 if (tp
->features
& RTL_FEATURE_MSI
) {
1556 pci_disable_msi(pdev
);
1557 tp
->features
&= ~RTL_FEATURE_MSI
;
1561 static int __devinit
1562 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1564 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
1565 const unsigned int region
= cfg
->region
;
1566 struct rtl8169_private
*tp
;
1567 struct mii_if_info
*mii
;
1568 struct net_device
*dev
;
1569 void __iomem
*ioaddr
;
1573 if (netif_msg_drv(&debug
)) {
1574 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
1575 MODULENAME
, RTL8169_VERSION
);
1578 dev
= alloc_etherdev(sizeof (*tp
));
1580 if (netif_msg_drv(&debug
))
1581 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
1586 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1587 tp
= netdev_priv(dev
);
1590 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
1594 mii
->mdio_read
= rtl_mdio_read
;
1595 mii
->mdio_write
= rtl_mdio_write
;
1596 mii
->phy_id_mask
= 0x1f;
1597 mii
->reg_num_mask
= 0x1f;
1598 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
1600 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1601 rc
= pci_enable_device(pdev
);
1603 if (netif_msg_probe(tp
))
1604 dev_err(&pdev
->dev
, "enable failure\n");
1605 goto err_out_free_dev_1
;
1608 rc
= pci_set_mwi(pdev
);
1610 goto err_out_disable_2
;
1612 /* make sure PCI base addr 1 is MMIO */
1613 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
1614 if (netif_msg_probe(tp
)) {
1616 "region #%d not an MMIO resource, aborting\n",
1623 /* check for weird/broken PCI region reporting */
1624 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
1625 if (netif_msg_probe(tp
)) {
1627 "Invalid PCI region size(s), aborting\n");
1633 rc
= pci_request_regions(pdev
, MODULENAME
);
1635 if (netif_msg_probe(tp
))
1636 dev_err(&pdev
->dev
, "could not request regions.\n");
1640 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
1642 if ((sizeof(dma_addr_t
) > 4) &&
1643 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) && use_dac
) {
1644 tp
->cp_cmd
|= PCIDAC
;
1645 dev
->features
|= NETIF_F_HIGHDMA
;
1647 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1649 if (netif_msg_probe(tp
)) {
1651 "DMA configuration failed.\n");
1653 goto err_out_free_res_4
;
1657 pci_set_master(pdev
);
1659 /* ioremap MMIO region */
1660 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
1662 if (netif_msg_probe(tp
))
1663 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
1665 goto err_out_free_res_4
;
1668 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1669 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
1670 dev_info(&pdev
->dev
, "no PCI Express capability\n");
1672 /* Unneeded ? Don't mess with Mrs. Murphy. */
1673 rtl8169_irq_mask_and_ack(ioaddr
);
1675 /* Soft reset the chip. */
1676 RTL_W8(ChipCmd
, CmdReset
);
1678 /* Check that the chip has finished the reset. */
1679 for (i
= 0; i
< 100; i
++) {
1680 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
1682 msleep_interruptible(1);
1685 /* Identify chip attached to board */
1686 rtl8169_get_mac_version(tp
, ioaddr
);
1688 rtl8169_print_mac_version(tp
);
1690 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
1691 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
1694 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
1695 /* Unknown chip: assume array element #0, original RTL-8169 */
1696 if (netif_msg_probe(tp
)) {
1697 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1698 "unknown chip version, assuming %s\n",
1699 rtl_chip_info
[0].name
);
1705 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1706 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
1707 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
1708 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
1709 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1711 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
1712 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
1713 tp
->set_speed
= rtl8169_set_speed_tbi
;
1714 tp
->get_settings
= rtl8169_gset_tbi
;
1715 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
1716 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
1717 tp
->link_ok
= rtl8169_tbi_link_ok
;
1719 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
1721 tp
->set_speed
= rtl8169_set_speed_xmii
;
1722 tp
->get_settings
= rtl8169_gset_xmii
;
1723 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
1724 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
1725 tp
->link_ok
= rtl8169_xmii_link_ok
;
1727 dev
->do_ioctl
= rtl8169_ioctl
;
1730 /* Get MAC address. FIXME: read EEPROM */
1731 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
1732 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
1733 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1735 dev
->open
= rtl8169_open
;
1736 dev
->hard_start_xmit
= rtl8169_start_xmit
;
1737 dev
->get_stats
= rtl8169_get_stats
;
1738 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
1739 dev
->stop
= rtl8169_close
;
1740 dev
->tx_timeout
= rtl8169_tx_timeout
;
1741 dev
->set_multicast_list
= rtl_set_rx_mode
;
1742 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
1743 dev
->irq
= pdev
->irq
;
1744 dev
->base_addr
= (unsigned long) ioaddr
;
1745 dev
->change_mtu
= rtl8169_change_mtu
;
1746 dev
->set_mac_address
= rtl_set_mac_address
;
1748 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
1750 #ifdef CONFIG_R8169_VLAN
1751 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1752 dev
->vlan_rx_register
= rtl8169_vlan_rx_register
;
1755 #ifdef CONFIG_NET_POLL_CONTROLLER
1756 dev
->poll_controller
= rtl8169_netpoll
;
1759 tp
->intr_mask
= 0xffff;
1760 tp
->mmio_addr
= ioaddr
;
1761 tp
->align
= cfg
->align
;
1762 tp
->hw_start
= cfg
->hw_start
;
1763 tp
->intr_event
= cfg
->intr_event
;
1764 tp
->napi_event
= cfg
->napi_event
;
1766 init_timer(&tp
->timer
);
1767 tp
->timer
.data
= (unsigned long) dev
;
1768 tp
->timer
.function
= rtl8169_phy_timer
;
1770 spin_lock_init(&tp
->lock
);
1772 rc
= register_netdev(dev
);
1776 pci_set_drvdata(pdev
, dev
);
1778 if (netif_msg_probe(tp
)) {
1779 u32 xid
= RTL_R32(TxConfig
) & 0x7cf0f8ff;
1781 printk(KERN_INFO
"%s: %s at 0x%lx, "
1782 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1783 "XID %08x IRQ %d\n",
1785 rtl_chip_info
[tp
->chipset
].name
,
1787 dev
->dev_addr
[0], dev
->dev_addr
[1],
1788 dev
->dev_addr
[2], dev
->dev_addr
[3],
1789 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
1792 rtl8169_init_phy(dev
, tp
);
1798 rtl_disable_msi(pdev
, tp
);
1801 pci_release_regions(pdev
);
1803 pci_clear_mwi(pdev
);
1805 pci_disable_device(pdev
);
1811 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
1813 struct net_device
*dev
= pci_get_drvdata(pdev
);
1814 struct rtl8169_private
*tp
= netdev_priv(dev
);
1816 flush_scheduled_work();
1818 unregister_netdev(dev
);
1819 rtl_disable_msi(pdev
, tp
);
1820 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
1821 pci_set_drvdata(pdev
, NULL
);
1824 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
1825 struct net_device
*dev
)
1827 unsigned int mtu
= dev
->mtu
;
1829 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
1832 static int rtl8169_open(struct net_device
*dev
)
1834 struct rtl8169_private
*tp
= netdev_priv(dev
);
1835 struct pci_dev
*pdev
= tp
->pci_dev
;
1836 int retval
= -ENOMEM
;
1839 rtl8169_set_rxbufsize(tp
, dev
);
1842 * Rx and Tx desscriptors needs 256 bytes alignment.
1843 * pci_alloc_consistent provides more.
1845 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
1847 if (!tp
->TxDescArray
)
1850 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
1852 if (!tp
->RxDescArray
)
1855 retval
= rtl8169_init_ring(dev
);
1859 INIT_DELAYED_WORK(&tp
->task
, NULL
);
1863 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
1864 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
1867 goto err_release_ring_2
;
1869 napi_enable(&tp
->napi
);
1873 rtl8169_request_timer(dev
);
1875 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
1880 rtl8169_rx_clear(tp
);
1882 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
1885 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
1890 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
1892 /* Disable interrupts */
1893 rtl8169_irq_mask_and_ack(ioaddr
);
1895 /* Reset the chipset */
1896 RTL_W8(ChipCmd
, CmdReset
);
1902 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
1904 void __iomem
*ioaddr
= tp
->mmio_addr
;
1905 u32 cfg
= rtl8169_rx_config
;
1907 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
1908 RTL_W32(RxConfig
, cfg
);
1910 /* Set DMA burst size and Interframe Gap Time */
1911 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
1912 (InterFrameGap
<< TxInterFrameGapShift
));
1915 static void rtl_hw_start(struct net_device
*dev
)
1917 struct rtl8169_private
*tp
= netdev_priv(dev
);
1918 void __iomem
*ioaddr
= tp
->mmio_addr
;
1921 /* Soft reset the chip. */
1922 RTL_W8(ChipCmd
, CmdReset
);
1924 /* Check that the chip has finished the reset. */
1925 for (i
= 0; i
< 100; i
++) {
1926 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
1928 msleep_interruptible(1);
1933 netif_start_queue(dev
);
1937 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
1938 void __iomem
*ioaddr
)
1941 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1942 * register to be written before TxDescAddrLow to work.
1943 * Switching from MMIO to I/O access fixes the issue as well.
1945 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
1946 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_32BIT_MASK
);
1947 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
1948 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_32BIT_MASK
);
1951 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
1955 cmd
= RTL_R16(CPlusCmd
);
1956 RTL_W16(CPlusCmd
, cmd
);
1960 static void rtl_set_rx_max_size(void __iomem
*ioaddr
)
1962 /* Low hurts. Let's disable the filtering. */
1963 RTL_W16(RxMaxSize
, 16383);
1966 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
1973 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
1974 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
1975 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
1976 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
1981 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
1982 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
1983 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
1984 RTL_W32(0x7c, p
->val
);
1990 static void rtl_hw_start_8169(struct net_device
*dev
)
1992 struct rtl8169_private
*tp
= netdev_priv(dev
);
1993 void __iomem
*ioaddr
= tp
->mmio_addr
;
1994 struct pci_dev
*pdev
= tp
->pci_dev
;
1996 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
1997 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
1998 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
2001 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2002 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2003 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2004 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2005 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2006 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2008 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2010 rtl_set_rx_max_size(ioaddr
);
2012 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2013 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2014 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2015 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2016 rtl_set_rx_tx_config_registers(tp
);
2018 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2020 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2021 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2022 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2023 "Bit-3 and bit-14 MUST be 1\n");
2024 tp
->cp_cmd
|= (1 << 14);
2027 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2029 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
2032 * Undocumented corner. Supposedly:
2033 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2035 RTL_W16(IntrMitigate
, 0x0000);
2037 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2039 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2040 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2041 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2042 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2043 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2044 rtl_set_rx_tx_config_registers(tp
);
2047 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2049 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2052 RTL_W32(RxMissed
, 0);
2054 rtl_set_rx_mode(dev
);
2056 /* no early-rx interrupts */
2057 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2059 /* Enable all known interrupts by setting the interrupt mask. */
2060 RTL_W16(IntrMask
, tp
->intr_event
);
2063 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
2065 struct net_device
*dev
= pci_get_drvdata(pdev
);
2066 struct rtl8169_private
*tp
= netdev_priv(dev
);
2067 int cap
= tp
->pcie_cap
;
2072 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2073 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
2074 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2078 static void rtl_hw_start_8168(struct net_device
*dev
)
2080 struct rtl8169_private
*tp
= netdev_priv(dev
);
2081 void __iomem
*ioaddr
= tp
->mmio_addr
;
2082 struct pci_dev
*pdev
= tp
->pci_dev
;
2084 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2086 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2088 rtl_set_rx_max_size(ioaddr
);
2090 rtl_set_rx_tx_config_registers(tp
);
2092 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2094 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2096 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2098 RTL_W16(IntrMitigate
, 0x5151);
2100 /* Work around for RxFIFO overflow. */
2101 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2102 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2103 tp
->intr_event
&= ~RxOverflow
;
2106 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2108 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2112 RTL_W32(RxMissed
, 0);
2114 rtl_set_rx_mode(dev
);
2116 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2118 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2120 RTL_W16(IntrMask
, tp
->intr_event
);
2123 static void rtl_hw_start_8101(struct net_device
*dev
)
2125 struct rtl8169_private
*tp
= netdev_priv(dev
);
2126 void __iomem
*ioaddr
= tp
->mmio_addr
;
2127 struct pci_dev
*pdev
= tp
->pci_dev
;
2129 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2130 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2131 int cap
= tp
->pcie_cap
;
2134 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
2135 PCI_EXP_DEVCTL_NOSNOOP_EN
);
2139 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2141 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2143 rtl_set_rx_max_size(ioaddr
);
2145 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2147 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2149 RTL_W16(IntrMitigate
, 0x0000);
2151 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2153 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2154 rtl_set_rx_tx_config_registers(tp
);
2156 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2160 RTL_W32(RxMissed
, 0);
2162 rtl_set_rx_mode(dev
);
2164 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2166 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2168 RTL_W16(IntrMask
, tp
->intr_event
);
2171 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
2173 struct rtl8169_private
*tp
= netdev_priv(dev
);
2176 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2181 if (!netif_running(dev
))
2186 rtl8169_set_rxbufsize(tp
, dev
);
2188 ret
= rtl8169_init_ring(dev
);
2192 napi_enable(&tp
->napi
);
2196 rtl8169_request_timer(dev
);
2202 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
2204 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
2205 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2208 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
2209 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2211 struct pci_dev
*pdev
= tp
->pci_dev
;
2213 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2214 PCI_DMA_FROMDEVICE
);
2215 dev_kfree_skb(*sk_buff
);
2217 rtl8169_make_unusable_by_asic(desc
);
2220 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2222 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2224 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2227 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2230 desc
->addr
= cpu_to_le64(mapping
);
2232 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
2235 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
2236 struct net_device
*dev
,
2237 struct RxDesc
*desc
, int rx_buf_sz
,
2240 struct sk_buff
*skb
;
2244 pad
= align
? align
: NET_IP_ALIGN
;
2246 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
2250 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
2252 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
2253 PCI_DMA_FROMDEVICE
);
2255 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
2260 rtl8169_make_unusable_by_asic(desc
);
2264 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
2268 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
2269 if (tp
->Rx_skbuff
[i
]) {
2270 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
2271 tp
->RxDescArray
+ i
);
2276 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
2281 for (cur
= start
; end
- cur
!= 0; cur
++) {
2282 struct sk_buff
*skb
;
2283 unsigned int i
= cur
% NUM_RX_DESC
;
2285 WARN_ON((s32
)(end
- cur
) < 0);
2287 if (tp
->Rx_skbuff
[i
])
2290 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
2291 tp
->RxDescArray
+ i
,
2292 tp
->rx_buf_sz
, tp
->align
);
2296 tp
->Rx_skbuff
[i
] = skb
;
2301 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
2303 desc
->opts1
|= cpu_to_le32(RingEnd
);
2306 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
2308 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
2311 static int rtl8169_init_ring(struct net_device
*dev
)
2313 struct rtl8169_private
*tp
= netdev_priv(dev
);
2315 rtl8169_init_ring_indexes(tp
);
2317 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
2318 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
2320 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
2323 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
2328 rtl8169_rx_clear(tp
);
2332 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
2333 struct TxDesc
*desc
)
2335 unsigned int len
= tx_skb
->len
;
2337 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
2344 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
2348 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
2349 unsigned int entry
= i
% NUM_TX_DESC
;
2350 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2351 unsigned int len
= tx_skb
->len
;
2354 struct sk_buff
*skb
= tx_skb
->skb
;
2356 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
2357 tp
->TxDescArray
+ entry
);
2362 tp
->dev
->stats
.tx_dropped
++;
2365 tp
->cur_tx
= tp
->dirty_tx
= 0;
2368 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
2370 struct rtl8169_private
*tp
= netdev_priv(dev
);
2372 PREPARE_DELAYED_WORK(&tp
->task
, task
);
2373 schedule_delayed_work(&tp
->task
, 4);
2376 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
2378 struct rtl8169_private
*tp
= netdev_priv(dev
);
2379 void __iomem
*ioaddr
= tp
->mmio_addr
;
2381 synchronize_irq(dev
->irq
);
2383 /* Wait for any pending NAPI task to complete */
2384 napi_disable(&tp
->napi
);
2386 rtl8169_irq_mask_and_ack(ioaddr
);
2388 tp
->intr_mask
= 0xffff;
2389 RTL_W16(IntrMask
, tp
->intr_event
);
2390 napi_enable(&tp
->napi
);
2393 static void rtl8169_reinit_task(struct work_struct
*work
)
2395 struct rtl8169_private
*tp
=
2396 container_of(work
, struct rtl8169_private
, task
.work
);
2397 struct net_device
*dev
= tp
->dev
;
2402 if (!netif_running(dev
))
2405 rtl8169_wait_for_quiescence(dev
);
2408 ret
= rtl8169_open(dev
);
2409 if (unlikely(ret
< 0)) {
2410 if (net_ratelimit() && netif_msg_drv(tp
)) {
2411 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
2412 " Rescheduling.\n", dev
->name
, ret
);
2414 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
2421 static void rtl8169_reset_task(struct work_struct
*work
)
2423 struct rtl8169_private
*tp
=
2424 container_of(work
, struct rtl8169_private
, task
.work
);
2425 struct net_device
*dev
= tp
->dev
;
2429 if (!netif_running(dev
))
2432 rtl8169_wait_for_quiescence(dev
);
2434 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
2435 rtl8169_tx_clear(tp
);
2437 if (tp
->dirty_rx
== tp
->cur_rx
) {
2438 rtl8169_init_ring_indexes(tp
);
2440 netif_wake_queue(dev
);
2441 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2443 if (net_ratelimit() && netif_msg_intr(tp
)) {
2444 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
2447 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2454 static void rtl8169_tx_timeout(struct net_device
*dev
)
2456 struct rtl8169_private
*tp
= netdev_priv(dev
);
2458 rtl8169_hw_reset(tp
->mmio_addr
);
2460 /* Let's wait a bit while any (async) irq lands on */
2461 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2464 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
2467 struct skb_shared_info
*info
= skb_shinfo(skb
);
2468 unsigned int cur_frag
, entry
;
2469 struct TxDesc
* uninitialized_var(txd
);
2472 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
2473 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
2478 entry
= (entry
+ 1) % NUM_TX_DESC
;
2480 txd
= tp
->TxDescArray
+ entry
;
2482 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
2483 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
2485 /* anti gcc 2.95.3 bugware (sic) */
2486 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2488 txd
->opts1
= cpu_to_le32(status
);
2489 txd
->addr
= cpu_to_le64(mapping
);
2491 tp
->tx_skb
[entry
].len
= len
;
2495 tp
->tx_skb
[entry
].skb
= skb
;
2496 txd
->opts1
|= cpu_to_le32(LastFrag
);
2502 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
2504 if (dev
->features
& NETIF_F_TSO
) {
2505 u32 mss
= skb_shinfo(skb
)->gso_size
;
2508 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
2510 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2511 const struct iphdr
*ip
= ip_hdr(skb
);
2513 if (ip
->protocol
== IPPROTO_TCP
)
2514 return IPCS
| TCPCS
;
2515 else if (ip
->protocol
== IPPROTO_UDP
)
2516 return IPCS
| UDPCS
;
2517 WARN_ON(1); /* we need a WARN() */
2522 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2524 struct rtl8169_private
*tp
= netdev_priv(dev
);
2525 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
2526 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
2527 void __iomem
*ioaddr
= tp
->mmio_addr
;
2531 int ret
= NETDEV_TX_OK
;
2533 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
2534 if (netif_msg_drv(tp
)) {
2536 "%s: BUG! Tx Ring full when queue awake!\n",
2542 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
2545 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
2547 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
2549 len
= skb_headlen(skb
);
2554 if (unlikely(len
< ETH_ZLEN
)) {
2555 if (skb_padto(skb
, ETH_ZLEN
))
2556 goto err_update_stats
;
2560 opts1
|= FirstFrag
| LastFrag
;
2561 tp
->tx_skb
[entry
].skb
= skb
;
2564 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2566 tp
->tx_skb
[entry
].len
= len
;
2567 txd
->addr
= cpu_to_le64(mapping
);
2568 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
2572 /* anti gcc 2.95.3 bugware (sic) */
2573 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2574 txd
->opts1
= cpu_to_le32(status
);
2576 dev
->trans_start
= jiffies
;
2578 tp
->cur_tx
+= frags
+ 1;
2582 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
2584 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
2585 netif_stop_queue(dev
);
2587 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
2588 netif_wake_queue(dev
);
2595 netif_stop_queue(dev
);
2596 ret
= NETDEV_TX_BUSY
;
2598 dev
->stats
.tx_dropped
++;
2602 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
2604 struct rtl8169_private
*tp
= netdev_priv(dev
);
2605 struct pci_dev
*pdev
= tp
->pci_dev
;
2606 void __iomem
*ioaddr
= tp
->mmio_addr
;
2607 u16 pci_status
, pci_cmd
;
2609 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2610 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
2612 if (netif_msg_intr(tp
)) {
2614 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2615 dev
->name
, pci_cmd
, pci_status
);
2619 * The recovery sequence below admits a very elaborated explanation:
2620 * - it seems to work;
2621 * - I did not see what else could be done;
2622 * - it makes iop3xx happy.
2624 * Feel free to adjust to your needs.
2626 if (pdev
->broken_parity_status
)
2627 pci_cmd
&= ~PCI_COMMAND_PARITY
;
2629 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
2631 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2633 pci_write_config_word(pdev
, PCI_STATUS
,
2634 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
2635 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
2636 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
2638 /* The infamous DAC f*ckup only happens at boot time */
2639 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
2640 if (netif_msg_intr(tp
))
2641 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
2642 tp
->cp_cmd
&= ~PCIDAC
;
2643 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2644 dev
->features
&= ~NETIF_F_HIGHDMA
;
2647 rtl8169_hw_reset(ioaddr
);
2649 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
2652 static void rtl8169_tx_interrupt(struct net_device
*dev
,
2653 struct rtl8169_private
*tp
,
2654 void __iomem
*ioaddr
)
2656 unsigned int dirty_tx
, tx_left
;
2658 dirty_tx
= tp
->dirty_tx
;
2660 tx_left
= tp
->cur_tx
- dirty_tx
;
2662 while (tx_left
> 0) {
2663 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
2664 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2665 u32 len
= tx_skb
->len
;
2669 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
2670 if (status
& DescOwn
)
2673 dev
->stats
.tx_bytes
+= len
;
2674 dev
->stats
.tx_packets
++;
2676 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
2678 if (status
& LastFrag
) {
2679 dev_kfree_skb_irq(tx_skb
->skb
);
2686 if (tp
->dirty_tx
!= dirty_tx
) {
2687 tp
->dirty_tx
= dirty_tx
;
2689 if (netif_queue_stopped(dev
) &&
2690 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
2691 netif_wake_queue(dev
);
2694 * 8168 hack: TxPoll requests are lost when the Tx packets are
2695 * too close. Let's kick an extra TxPoll request when a burst
2696 * of start_xmit activity is detected (if it is not detected,
2697 * it is slow enough). -- FR
2700 if (tp
->cur_tx
!= dirty_tx
)
2701 RTL_W8(TxPoll
, NPQ
);
2705 static inline int rtl8169_fragmented_frame(u32 status
)
2707 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
2710 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
2712 u32 opts1
= le32_to_cpu(desc
->opts1
);
2713 u32 status
= opts1
& RxProtoMask
;
2715 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
2716 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
2717 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
2718 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2720 skb
->ip_summed
= CHECKSUM_NONE
;
2723 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
2724 struct rtl8169_private
*tp
, int pkt_size
,
2727 struct sk_buff
*skb
;
2730 if (pkt_size
>= rx_copybreak
)
2733 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
2737 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
2738 PCI_DMA_FROMDEVICE
);
2739 skb_reserve(skb
, NET_IP_ALIGN
);
2740 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
2747 static int rtl8169_rx_interrupt(struct net_device
*dev
,
2748 struct rtl8169_private
*tp
,
2749 void __iomem
*ioaddr
, u32 budget
)
2751 unsigned int cur_rx
, rx_left
;
2752 unsigned int delta
, count
;
2754 cur_rx
= tp
->cur_rx
;
2755 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
2756 rx_left
= min(rx_left
, budget
);
2758 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
2759 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
2760 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
2764 status
= le32_to_cpu(desc
->opts1
);
2766 if (status
& DescOwn
)
2768 if (unlikely(status
& RxRES
)) {
2769 if (netif_msg_rx_err(tp
)) {
2771 "%s: Rx ERROR. status = %08x\n",
2774 dev
->stats
.rx_errors
++;
2775 if (status
& (RxRWT
| RxRUNT
))
2776 dev
->stats
.rx_length_errors
++;
2778 dev
->stats
.rx_crc_errors
++;
2779 if (status
& RxFOVF
) {
2780 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2781 dev
->stats
.rx_fifo_errors
++;
2783 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
2785 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
2786 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
2787 int pkt_size
= (status
& 0x00001FFF) - 4;
2788 struct pci_dev
*pdev
= tp
->pci_dev
;
2791 * The driver does not support incoming fragmented
2792 * frames. They are seen as a symptom of over-mtu
2795 if (unlikely(rtl8169_fragmented_frame(status
))) {
2796 dev
->stats
.rx_dropped
++;
2797 dev
->stats
.rx_length_errors
++;
2798 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
2802 rtl8169_rx_csum(skb
, desc
);
2804 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
2805 pci_dma_sync_single_for_device(pdev
, addr
,
2806 pkt_size
, PCI_DMA_FROMDEVICE
);
2807 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
2809 pci_unmap_single(pdev
, addr
, pkt_size
,
2810 PCI_DMA_FROMDEVICE
);
2811 tp
->Rx_skbuff
[entry
] = NULL
;
2814 skb_put(skb
, pkt_size
);
2815 skb
->protocol
= eth_type_trans(skb
, dev
);
2817 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
2818 netif_receive_skb(skb
);
2820 dev
->last_rx
= jiffies
;
2821 dev
->stats
.rx_bytes
+= pkt_size
;
2822 dev
->stats
.rx_packets
++;
2825 /* Work around for AMD plateform. */
2826 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
2827 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
2833 count
= cur_rx
- tp
->cur_rx
;
2834 tp
->cur_rx
= cur_rx
;
2836 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
2837 if (!delta
&& count
&& netif_msg_intr(tp
))
2838 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
2839 tp
->dirty_rx
+= delta
;
2842 * FIXME: until there is periodic timer to try and refill the ring,
2843 * a temporary shortage may definitely kill the Rx process.
2844 * - disable the asic to try and avoid an overflow and kick it again
2846 * - how do others driver handle this condition (Uh oh...).
2848 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
2849 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
2854 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
2856 struct net_device
*dev
= dev_instance
;
2857 struct rtl8169_private
*tp
= netdev_priv(dev
);
2858 void __iomem
*ioaddr
= tp
->mmio_addr
;
2862 status
= RTL_R16(IntrStatus
);
2864 /* hotplug/major error/no more work/shared irq */
2865 if ((status
== 0xffff) || !status
)
2870 if (unlikely(!netif_running(dev
))) {
2871 rtl8169_asic_down(ioaddr
);
2875 status
&= tp
->intr_mask
;
2877 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
2879 if (!(status
& tp
->intr_event
))
2882 /* Work around for rx fifo overflow */
2883 if (unlikely(status
& RxFIFOOver
) &&
2884 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
2885 netif_stop_queue(dev
);
2886 rtl8169_tx_timeout(dev
);
2890 if (unlikely(status
& SYSErr
)) {
2891 rtl8169_pcierr_interrupt(dev
);
2895 if (status
& LinkChg
)
2896 rtl8169_check_link_status(dev
, tp
, ioaddr
);
2898 if (status
& tp
->napi_event
) {
2899 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
2900 tp
->intr_mask
= ~tp
->napi_event
;
2902 if (likely(netif_rx_schedule_prep(dev
, &tp
->napi
)))
2903 __netif_rx_schedule(dev
, &tp
->napi
);
2904 else if (netif_msg_intr(tp
)) {
2905 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
2910 return IRQ_RETVAL(handled
);
2913 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
2915 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
2916 struct net_device
*dev
= tp
->dev
;
2917 void __iomem
*ioaddr
= tp
->mmio_addr
;
2920 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
2921 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
2923 if (work_done
< budget
) {
2924 netif_rx_complete(dev
, napi
);
2925 tp
->intr_mask
= 0xffff;
2927 * 20040426: the barrier is not strictly required but the
2928 * behavior of the irq handler could be less predictable
2929 * without it. Btw, the lack of flush for the posted pci
2930 * write is safe - FR
2933 RTL_W16(IntrMask
, tp
->intr_event
);
2939 static void rtl8169_down(struct net_device
*dev
)
2941 struct rtl8169_private
*tp
= netdev_priv(dev
);
2942 void __iomem
*ioaddr
= tp
->mmio_addr
;
2943 unsigned int intrmask
;
2945 rtl8169_delete_timer(dev
);
2947 netif_stop_queue(dev
);
2949 napi_disable(&tp
->napi
);
2952 spin_lock_irq(&tp
->lock
);
2954 rtl8169_asic_down(ioaddr
);
2956 /* Update the error counts. */
2957 dev
->stats
.rx_missed_errors
+= RTL_R32(RxMissed
);
2958 RTL_W32(RxMissed
, 0);
2960 spin_unlock_irq(&tp
->lock
);
2962 synchronize_irq(dev
->irq
);
2964 /* Give a racing hard_start_xmit a few cycles to complete. */
2965 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2968 * And now for the 50k$ question: are IRQ disabled or not ?
2970 * Two paths lead here:
2972 * -> netif_running() is available to sync the current code and the
2973 * IRQ handler. See rtl8169_interrupt for details.
2974 * 2) dev->change_mtu
2975 * -> rtl8169_poll can not be issued again and re-enable the
2976 * interruptions. Let's simply issue the IRQ down sequence again.
2978 * No loop if hotpluged or major error (0xffff).
2980 intrmask
= RTL_R16(IntrMask
);
2981 if (intrmask
&& (intrmask
!= 0xffff))
2984 rtl8169_tx_clear(tp
);
2986 rtl8169_rx_clear(tp
);
2989 static int rtl8169_close(struct net_device
*dev
)
2991 struct rtl8169_private
*tp
= netdev_priv(dev
);
2992 struct pci_dev
*pdev
= tp
->pci_dev
;
2996 free_irq(dev
->irq
, dev
);
2998 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3000 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3002 tp
->TxDescArray
= NULL
;
3003 tp
->RxDescArray
= NULL
;
3008 static void rtl_set_rx_mode(struct net_device
*dev
)
3010 struct rtl8169_private
*tp
= netdev_priv(dev
);
3011 void __iomem
*ioaddr
= tp
->mmio_addr
;
3012 unsigned long flags
;
3013 u32 mc_filter
[2]; /* Multicast hash filter */
3017 if (dev
->flags
& IFF_PROMISC
) {
3018 /* Unconditionally log net taps. */
3019 if (netif_msg_link(tp
)) {
3020 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3024 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3026 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3027 } else if ((dev
->mc_count
> multicast_filter_limit
)
3028 || (dev
->flags
& IFF_ALLMULTI
)) {
3029 /* Too many to filter perfectly -- accept all multicasts. */
3030 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3031 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3033 struct dev_mc_list
*mclist
;
3036 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3037 mc_filter
[1] = mc_filter
[0] = 0;
3038 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3039 i
++, mclist
= mclist
->next
) {
3040 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3041 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3042 rx_mode
|= AcceptMulticast
;
3046 spin_lock_irqsave(&tp
->lock
, flags
);
3048 tmp
= rtl8169_rx_config
| rx_mode
|
3049 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3051 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3052 u32 data
= mc_filter
[0];
3054 mc_filter
[0] = swab32(mc_filter
[1]);
3055 mc_filter
[1] = swab32(data
);
3058 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3059 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3061 RTL_W32(RxConfig
, tmp
);
3063 spin_unlock_irqrestore(&tp
->lock
, flags
);
3067 * rtl8169_get_stats - Get rtl8169 read/write statistics
3068 * @dev: The Ethernet Device to get statistics for
3070 * Get TX/RX statistics for rtl8169
3072 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3074 struct rtl8169_private
*tp
= netdev_priv(dev
);
3075 void __iomem
*ioaddr
= tp
->mmio_addr
;
3076 unsigned long flags
;
3078 if (netif_running(dev
)) {
3079 spin_lock_irqsave(&tp
->lock
, flags
);
3080 dev
->stats
.rx_missed_errors
+= RTL_R32(RxMissed
);
3081 RTL_W32(RxMissed
, 0);
3082 spin_unlock_irqrestore(&tp
->lock
, flags
);
3090 static int rtl8169_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3092 struct net_device
*dev
= pci_get_drvdata(pdev
);
3093 struct rtl8169_private
*tp
= netdev_priv(dev
);
3094 void __iomem
*ioaddr
= tp
->mmio_addr
;
3096 if (!netif_running(dev
))
3097 goto out_pci_suspend
;
3099 netif_device_detach(dev
);
3100 netif_stop_queue(dev
);
3102 spin_lock_irq(&tp
->lock
);
3104 rtl8169_asic_down(ioaddr
);
3106 dev
->stats
.rx_missed_errors
+= RTL_R32(RxMissed
);
3107 RTL_W32(RxMissed
, 0);
3109 spin_unlock_irq(&tp
->lock
);
3112 pci_save_state(pdev
);
3113 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
),
3114 (tp
->features
& RTL_FEATURE_WOL
) ? 1 : 0);
3115 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3120 static int rtl8169_resume(struct pci_dev
*pdev
)
3122 struct net_device
*dev
= pci_get_drvdata(pdev
);
3124 pci_set_power_state(pdev
, PCI_D0
);
3125 pci_restore_state(pdev
);
3126 pci_enable_wake(pdev
, PCI_D0
, 0);
3128 if (!netif_running(dev
))
3131 netif_device_attach(dev
);
3133 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3138 #endif /* CONFIG_PM */
3140 static struct pci_driver rtl8169_pci_driver
= {
3142 .id_table
= rtl8169_pci_tbl
,
3143 .probe
= rtl8169_init_one
,
3144 .remove
= __devexit_p(rtl8169_remove_one
),
3146 .suspend
= rtl8169_suspend
,
3147 .resume
= rtl8169_resume
,
3151 static int __init
rtl8169_init_module(void)
3153 return pci_register_driver(&rtl8169_pci_driver
);
3156 static void __exit
rtl8169_cleanup_module(void)
3158 pci_unregister_driver(&rtl8169_pci_driver
);
3161 module_init(rtl8169_init_module
);
3162 module_exit(rtl8169_cleanup_module
);