1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/skbuff.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/stddef.h>
70 #include <linux/ioctl.h>
71 #include <linux/timex.h>
72 #include <linux/ethtool.h>
73 #include <linux/workqueue.h>
74 #include <linux/if_vlan.h>
76 #include <linux/tcp.h>
79 #include <asm/system.h>
80 #include <asm/uaccess.h>
82 #include <asm/div64.h>
87 #include "s2io-regs.h"
89 #define DRV_VERSION "2.0.26.25"
91 /* S2io Driver name & version. */
92 static char s2io_driver_name
[] = "Neterion";
93 static char s2io_driver_version
[] = DRV_VERSION
;
95 static int rxd_size
[2] = {32,48};
96 static int rxd_count
[2] = {127,85};
98 static inline int RXD_IS_UP2DT(struct RxD_t
*rxdp
)
102 ret
= ((!(rxdp
->Control_1
& RXD_OWN_XENA
)) &&
103 (GET_RXD_MARKER(rxdp
->Control_2
) != THE_RXD_MARK
));
109 * Cards with following subsystem_id have a link state indication
110 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
111 * macro below identifies these cards given the subsystem_id.
113 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
114 (dev_type == XFRAME_I_DEVICE) ? \
115 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
116 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
118 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
119 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
121 static inline int is_s2io_card_up(const struct s2io_nic
* sp
)
123 return test_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings
[][ETH_GSTRING_LEN
] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
135 static char ethtool_xena_stats_keys
[][ETH_GSTRING_LEN
] = {
137 {"tmac_data_octets"},
141 {"tmac_pause_ctrl_frms"},
145 {"tmac_any_err_frms"},
146 {"tmac_ttl_less_fb_octets"},
147 {"tmac_vld_ip_octets"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
161 {"rmac_out_rng_len_err_frms"},
163 {"rmac_pause_ctrl_frms"},
164 {"rmac_unsup_ctrl_frms"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
168 {"rmac_discarded_frms"},
169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
175 {"rmac_jabber_frms"},
176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
189 {"rmac_err_drp_udp"},
190 {"rmac_xgmii_err_sym"},
208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
210 {"rmac_accepted_ip"},
214 {"new_rd_req_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
219 {"new_wr_req_rtry_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
232 static char ethtool_enhanced_stats_keys
[][ETH_GSTRING_LEN
] = {
233 {"rmac_ttl_1519_4095_frms"},
234 {"rmac_ttl_4096_8191_frms"},
235 {"rmac_ttl_8192_max_frms"},
236 {"rmac_ttl_gt_max_frms"},
237 {"rmac_osized_alt_frms"},
238 {"rmac_jabber_alt_frms"},
239 {"rmac_gt_max_alt_frms"},
241 {"rmac_len_discard"},
242 {"rmac_fcs_discard"},
245 {"rmac_red_discard"},
246 {"rmac_rts_discard"},
247 {"rmac_ingm_full_discard"},
251 static char ethtool_driver_stats_keys
[][ETH_GSTRING_LEN
] = {
252 {"\n DRIVER STATISTICS"},
253 {"single_bit_ecc_errs"},
254 {"double_bit_ecc_errs"},
267 {"alarm_transceiver_temp_high"},
268 {"alarm_transceiver_temp_low"},
269 {"alarm_laser_bias_current_high"},
270 {"alarm_laser_bias_current_low"},
271 {"alarm_laser_output_power_high"},
272 {"alarm_laser_output_power_low"},
273 {"warn_transceiver_temp_high"},
274 {"warn_transceiver_temp_low"},
275 {"warn_laser_bias_current_high"},
276 {"warn_laser_bias_current_low"},
277 {"warn_laser_output_power_high"},
278 {"warn_laser_output_power_low"},
279 {"lro_aggregated_pkts"},
280 {"lro_flush_both_count"},
281 {"lro_out_of_sequence_pkts"},
282 {"lro_flush_due_to_max_pkts"},
283 {"lro_avg_aggr_pkts"},
284 {"mem_alloc_fail_cnt"},
285 {"pci_map_fail_cnt"},
286 {"watchdog_timer_cnt"},
293 {"tx_tcode_buf_abort_cnt"},
294 {"tx_tcode_desc_abort_cnt"},
295 {"tx_tcode_parity_err_cnt"},
296 {"tx_tcode_link_loss_cnt"},
297 {"tx_tcode_list_proc_err_cnt"},
298 {"rx_tcode_parity_err_cnt"},
299 {"rx_tcode_abort_cnt"},
300 {"rx_tcode_parity_abort_cnt"},
301 {"rx_tcode_rda_fail_cnt"},
302 {"rx_tcode_unkn_prot_cnt"},
303 {"rx_tcode_fcs_err_cnt"},
304 {"rx_tcode_buf_size_err_cnt"},
305 {"rx_tcode_rxd_corrupt_cnt"},
306 {"rx_tcode_unkn_err_cnt"},
314 {"mac_tmac_err_cnt"},
315 {"mac_rmac_err_cnt"},
316 {"xgxs_txgxs_err_cnt"},
317 {"xgxs_rxgxs_err_cnt"},
319 {"prc_pcix_err_cnt"},
326 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
327 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
328 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
330 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
331 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
333 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
334 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
336 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
337 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
339 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
340 init_timer(&timer); \
341 timer.function = handle; \
342 timer.data = (unsigned long) arg; \
343 mod_timer(&timer, (jiffies + exp)) \
345 /* copy mac addr to def_mac_addr array */
346 static void do_s2io_copy_mac_addr(struct s2io_nic
*sp
, int offset
, u64 mac_addr
)
348 sp
->def_mac_addr
[offset
].mac_addr
[5] = (u8
) (mac_addr
);
349 sp
->def_mac_addr
[offset
].mac_addr
[4] = (u8
) (mac_addr
>> 8);
350 sp
->def_mac_addr
[offset
].mac_addr
[3] = (u8
) (mac_addr
>> 16);
351 sp
->def_mac_addr
[offset
].mac_addr
[2] = (u8
) (mac_addr
>> 24);
352 sp
->def_mac_addr
[offset
].mac_addr
[1] = (u8
) (mac_addr
>> 32);
353 sp
->def_mac_addr
[offset
].mac_addr
[0] = (u8
) (mac_addr
>> 40);
356 static void s2io_vlan_rx_register(struct net_device
*dev
,
357 struct vlan_group
*grp
)
360 struct s2io_nic
*nic
= dev
->priv
;
361 unsigned long flags
[MAX_TX_FIFOS
];
362 struct mac_info
*mac_control
= &nic
->mac_control
;
363 struct config_param
*config
= &nic
->config
;
365 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
366 spin_lock_irqsave(&mac_control
->fifos
[i
].tx_lock
, flags
[i
]);
369 for (i
= config
->tx_fifo_num
- 1; i
>= 0; i
--)
370 spin_unlock_irqrestore(&mac_control
->fifos
[i
].tx_lock
,
374 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
375 static int vlan_strip_flag
;
377 /* Unregister the vlan */
378 static void s2io_vlan_rx_kill_vid(struct net_device
*dev
, unsigned long vid
)
381 struct s2io_nic
*nic
= dev
->priv
;
382 unsigned long flags
[MAX_TX_FIFOS
];
383 struct mac_info
*mac_control
= &nic
->mac_control
;
384 struct config_param
*config
= &nic
->config
;
386 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
387 spin_lock_irqsave(&mac_control
->fifos
[i
].tx_lock
, flags
[i
]);
390 vlan_group_set_device(nic
->vlgrp
, vid
, NULL
);
392 for (i
= config
->tx_fifo_num
- 1; i
>= 0; i
--)
393 spin_unlock_irqrestore(&mac_control
->fifos
[i
].tx_lock
,
398 * Constants to be programmed into the Xena's registers, to configure
403 static const u64 herc_act_dtx_cfg
[] = {
405 0x8000051536750000ULL
, 0x80000515367500E0ULL
,
407 0x8000051536750004ULL
, 0x80000515367500E4ULL
,
409 0x80010515003F0000ULL
, 0x80010515003F00E0ULL
,
411 0x80010515003F0004ULL
, 0x80010515003F00E4ULL
,
413 0x801205150D440000ULL
, 0x801205150D4400E0ULL
,
415 0x801205150D440004ULL
, 0x801205150D4400E4ULL
,
417 0x80020515F2100000ULL
, 0x80020515F21000E0ULL
,
419 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
424 static const u64 xena_dtx_cfg
[] = {
426 0x8000051500000000ULL
, 0x80000515000000E0ULL
,
428 0x80000515D9350004ULL
, 0x80000515D93500E4ULL
,
430 0x8001051500000000ULL
, 0x80010515000000E0ULL
,
432 0x80010515001E0004ULL
, 0x80010515001E00E4ULL
,
434 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
436 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
441 * Constants for Fixing the MacAddress problem seen mostly on
444 static const u64 fix_mac
[] = {
445 0x0060000000000000ULL
, 0x0060600000000000ULL
,
446 0x0040600000000000ULL
, 0x0000600000000000ULL
,
447 0x0020600000000000ULL
, 0x0060600000000000ULL
,
448 0x0020600000000000ULL
, 0x0060600000000000ULL
,
449 0x0020600000000000ULL
, 0x0060600000000000ULL
,
450 0x0020600000000000ULL
, 0x0060600000000000ULL
,
451 0x0020600000000000ULL
, 0x0060600000000000ULL
,
452 0x0020600000000000ULL
, 0x0060600000000000ULL
,
453 0x0020600000000000ULL
, 0x0060600000000000ULL
,
454 0x0020600000000000ULL
, 0x0060600000000000ULL
,
455 0x0020600000000000ULL
, 0x0060600000000000ULL
,
456 0x0020600000000000ULL
, 0x0060600000000000ULL
,
457 0x0020600000000000ULL
, 0x0000600000000000ULL
,
458 0x0040600000000000ULL
, 0x0060600000000000ULL
,
462 MODULE_LICENSE("GPL");
463 MODULE_VERSION(DRV_VERSION
);
466 /* Module Loadable parameters. */
467 S2IO_PARM_INT(tx_fifo_num
, FIFO_DEFAULT_NUM
);
468 S2IO_PARM_INT(rx_ring_num
, 1);
469 S2IO_PARM_INT(multiq
, 0);
470 S2IO_PARM_INT(rx_ring_mode
, 1);
471 S2IO_PARM_INT(use_continuous_tx_intrs
, 1);
472 S2IO_PARM_INT(rmac_pause_time
, 0x100);
473 S2IO_PARM_INT(mc_pause_threshold_q0q3
, 187);
474 S2IO_PARM_INT(mc_pause_threshold_q4q7
, 187);
475 S2IO_PARM_INT(shared_splits
, 0);
476 S2IO_PARM_INT(tmac_util_period
, 5);
477 S2IO_PARM_INT(rmac_util_period
, 5);
478 S2IO_PARM_INT(l3l4hdr_size
, 128);
479 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
480 S2IO_PARM_INT(tx_steering_type
, TX_DEFAULT_STEERING
);
481 /* Frequency of Rx desc syncs expressed as power of 2 */
482 S2IO_PARM_INT(rxsync_frequency
, 3);
483 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
484 S2IO_PARM_INT(intr_type
, 2);
485 /* Large receive offload feature */
486 static unsigned int lro_enable
;
487 module_param_named(lro
, lro_enable
, uint
, 0);
489 /* Max pkts to be aggregated by LRO at one time. If not specified,
490 * aggregation happens until we hit max IP pkt size(64K)
492 S2IO_PARM_INT(lro_max_pkts
, 0xFFFF);
493 S2IO_PARM_INT(indicate_max_pkts
, 0);
495 S2IO_PARM_INT(napi
, 1);
496 S2IO_PARM_INT(ufo
, 0);
497 S2IO_PARM_INT(vlan_tag_strip
, NO_STRIP_IN_PROMISC
);
499 static unsigned int tx_fifo_len
[MAX_TX_FIFOS
] =
500 {DEFAULT_FIFO_0_LEN
, [1 ...(MAX_TX_FIFOS
- 1)] = DEFAULT_FIFO_1_7_LEN
};
501 static unsigned int rx_ring_sz
[MAX_RX_RINGS
] =
502 {[0 ...(MAX_RX_RINGS
- 1)] = SMALL_BLK_CNT
};
503 static unsigned int rts_frm_len
[MAX_RX_RINGS
] =
504 {[0 ...(MAX_RX_RINGS
- 1)] = 0 };
506 module_param_array(tx_fifo_len
, uint
, NULL
, 0);
507 module_param_array(rx_ring_sz
, uint
, NULL
, 0);
508 module_param_array(rts_frm_len
, uint
, NULL
, 0);
512 * This table lists all the devices that this driver supports.
514 static struct pci_device_id s2io_tbl
[] __devinitdata
= {
515 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_WIN
,
516 PCI_ANY_ID
, PCI_ANY_ID
},
517 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_UNI
,
518 PCI_ANY_ID
, PCI_ANY_ID
},
519 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_WIN
,
520 PCI_ANY_ID
, PCI_ANY_ID
},
521 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_UNI
,
522 PCI_ANY_ID
, PCI_ANY_ID
},
526 MODULE_DEVICE_TABLE(pci
, s2io_tbl
);
528 static struct pci_error_handlers s2io_err_handler
= {
529 .error_detected
= s2io_io_error_detected
,
530 .slot_reset
= s2io_io_slot_reset
,
531 .resume
= s2io_io_resume
,
534 static struct pci_driver s2io_driver
= {
536 .id_table
= s2io_tbl
,
537 .probe
= s2io_init_nic
,
538 .remove
= __devexit_p(s2io_rem_nic
),
539 .err_handler
= &s2io_err_handler
,
542 /* A simplifier macro used both by init and free shared_mem Fns(). */
543 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
545 /* netqueue manipulation helper functions */
546 static inline void s2io_stop_all_tx_queue(struct s2io_nic
*sp
)
548 if (!sp
->config
.multiq
) {
551 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
552 sp
->mac_control
.fifos
[i
].queue_state
= FIFO_QUEUE_STOP
;
554 netif_tx_stop_all_queues(sp
->dev
);
557 static inline void s2io_stop_tx_queue(struct s2io_nic
*sp
, int fifo_no
)
559 if (!sp
->config
.multiq
)
560 sp
->mac_control
.fifos
[fifo_no
].queue_state
=
563 netif_tx_stop_all_queues(sp
->dev
);
566 static inline void s2io_start_all_tx_queue(struct s2io_nic
*sp
)
568 if (!sp
->config
.multiq
) {
571 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
572 sp
->mac_control
.fifos
[i
].queue_state
= FIFO_QUEUE_START
;
574 netif_tx_start_all_queues(sp
->dev
);
577 static inline void s2io_start_tx_queue(struct s2io_nic
*sp
, int fifo_no
)
579 if (!sp
->config
.multiq
)
580 sp
->mac_control
.fifos
[fifo_no
].queue_state
=
583 netif_tx_start_all_queues(sp
->dev
);
586 static inline void s2io_wake_all_tx_queue(struct s2io_nic
*sp
)
588 if (!sp
->config
.multiq
) {
591 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
592 sp
->mac_control
.fifos
[i
].queue_state
= FIFO_QUEUE_START
;
594 netif_tx_wake_all_queues(sp
->dev
);
597 static inline void s2io_wake_tx_queue(
598 struct fifo_info
*fifo
, int cnt
, u8 multiq
)
602 if (cnt
&& __netif_subqueue_stopped(fifo
->dev
, fifo
->fifo_no
))
603 netif_wake_subqueue(fifo
->dev
, fifo
->fifo_no
);
604 } else if (cnt
&& (fifo
->queue_state
== FIFO_QUEUE_STOP
)) {
605 if (netif_queue_stopped(fifo
->dev
)) {
606 fifo
->queue_state
= FIFO_QUEUE_START
;
607 netif_wake_queue(fifo
->dev
);
613 * init_shared_mem - Allocation and Initialization of Memory
614 * @nic: Device private variable.
615 * Description: The function allocates all the memory areas shared
616 * between the NIC and the driver. This includes Tx descriptors,
617 * Rx descriptors and the statistics block.
620 static int init_shared_mem(struct s2io_nic
*nic
)
623 void *tmp_v_addr
, *tmp_v_addr_next
;
624 dma_addr_t tmp_p_addr
, tmp_p_addr_next
;
625 struct RxD_block
*pre_rxd_blk
= NULL
;
627 int lst_size
, lst_per_page
;
628 struct net_device
*dev
= nic
->dev
;
632 struct mac_info
*mac_control
;
633 struct config_param
*config
;
634 unsigned long long mem_allocated
= 0;
636 mac_control
= &nic
->mac_control
;
637 config
= &nic
->config
;
640 /* Allocation and initialization of TXDLs in FIOFs */
642 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
643 size
+= config
->tx_cfg
[i
].fifo_len
;
645 if (size
> MAX_AVAILABLE_TXDS
) {
646 DBG_PRINT(ERR_DBG
, "s2io: Requested TxDs too high, ");
647 DBG_PRINT(ERR_DBG
, "Requested: %d, max supported: 8192\n", size
);
652 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
653 size
= config
->tx_cfg
[i
].fifo_len
;
655 * Legal values are from 2 to 8192
658 DBG_PRINT(ERR_DBG
, "s2io: Invalid fifo len (%d)", size
);
659 DBG_PRINT(ERR_DBG
, "for fifo %d\n", i
);
660 DBG_PRINT(ERR_DBG
, "s2io: Legal values for fifo len"
666 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
667 lst_per_page
= PAGE_SIZE
/ lst_size
;
669 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
670 int fifo_len
= config
->tx_cfg
[i
].fifo_len
;
671 int list_holder_size
= fifo_len
* sizeof(struct list_info_hold
);
672 mac_control
->fifos
[i
].list_info
= kzalloc(list_holder_size
,
674 if (!mac_control
->fifos
[i
].list_info
) {
676 "Malloc failed for list_info\n");
679 mem_allocated
+= list_holder_size
;
681 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
682 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
684 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
685 mac_control
->fifos
[i
].tx_curr_put_info
.fifo_len
=
686 config
->tx_cfg
[i
].fifo_len
- 1;
687 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
688 mac_control
->fifos
[i
].tx_curr_get_info
.fifo_len
=
689 config
->tx_cfg
[i
].fifo_len
- 1;
690 mac_control
->fifos
[i
].fifo_no
= i
;
691 mac_control
->fifos
[i
].nic
= nic
;
692 mac_control
->fifos
[i
].max_txds
= MAX_SKB_FRAGS
+ 2;
693 mac_control
->fifos
[i
].dev
= dev
;
695 for (j
= 0; j
< page_num
; j
++) {
699 tmp_v
= pci_alloc_consistent(nic
->pdev
,
703 "pci_alloc_consistent ");
704 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
707 /* If we got a zero DMA address(can happen on
708 * certain platforms like PPC), reallocate.
709 * Store virtual address of page we don't want,
713 mac_control
->zerodma_virt_addr
= tmp_v
;
715 "%s: Zero DMA address for TxDL. ", dev
->name
);
717 "Virtual address %p\n", tmp_v
);
718 tmp_v
= pci_alloc_consistent(nic
->pdev
,
722 "pci_alloc_consistent ");
723 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
726 mem_allocated
+= PAGE_SIZE
;
728 while (k
< lst_per_page
) {
729 int l
= (j
* lst_per_page
) + k
;
730 if (l
== config
->tx_cfg
[i
].fifo_len
)
732 mac_control
->fifos
[i
].list_info
[l
].list_virt_addr
=
733 tmp_v
+ (k
* lst_size
);
734 mac_control
->fifos
[i
].list_info
[l
].list_phy_addr
=
735 tmp_p
+ (k
* lst_size
);
741 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
742 size
= config
->tx_cfg
[i
].fifo_len
;
743 mac_control
->fifos
[i
].ufo_in_band_v
744 = kcalloc(size
, sizeof(u64
), GFP_KERNEL
);
745 if (!mac_control
->fifos
[i
].ufo_in_band_v
)
747 mem_allocated
+= (size
* sizeof(u64
));
750 /* Allocation and initialization of RXDs in Rings */
752 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
753 if (config
->rx_cfg
[i
].num_rxd
%
754 (rxd_count
[nic
->rxd_mode
] + 1)) {
755 DBG_PRINT(ERR_DBG
, "%s: RxD count of ", dev
->name
);
756 DBG_PRINT(ERR_DBG
, "Ring%d is not a multiple of ",
758 DBG_PRINT(ERR_DBG
, "RxDs per Block");
761 size
+= config
->rx_cfg
[i
].num_rxd
;
762 mac_control
->rings
[i
].block_count
=
763 config
->rx_cfg
[i
].num_rxd
/
764 (rxd_count
[nic
->rxd_mode
] + 1 );
765 mac_control
->rings
[i
].pkt_cnt
= config
->rx_cfg
[i
].num_rxd
-
766 mac_control
->rings
[i
].block_count
;
768 if (nic
->rxd_mode
== RXD_MODE_1
)
769 size
= (size
* (sizeof(struct RxD1
)));
771 size
= (size
* (sizeof(struct RxD3
)));
773 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
774 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
775 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
776 mac_control
->rings
[i
].rx_curr_get_info
.ring_len
=
777 config
->rx_cfg
[i
].num_rxd
- 1;
778 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
779 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
780 mac_control
->rings
[i
].rx_curr_put_info
.ring_len
=
781 config
->rx_cfg
[i
].num_rxd
- 1;
782 mac_control
->rings
[i
].nic
= nic
;
783 mac_control
->rings
[i
].ring_no
= i
;
784 mac_control
->rings
[i
].lro
= lro_enable
;
786 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
787 (rxd_count
[nic
->rxd_mode
] + 1);
788 /* Allocating all the Rx blocks */
789 for (j
= 0; j
< blk_cnt
; j
++) {
790 struct rx_block_info
*rx_blocks
;
793 rx_blocks
= &mac_control
->rings
[i
].rx_blocks
[j
];
794 size
= SIZE_OF_BLOCK
; //size is always page size
795 tmp_v_addr
= pci_alloc_consistent(nic
->pdev
, size
,
797 if (tmp_v_addr
== NULL
) {
799 * In case of failure, free_shared_mem()
800 * is called, which should free any
801 * memory that was alloced till the
804 rx_blocks
->block_virt_addr
= tmp_v_addr
;
807 mem_allocated
+= size
;
808 memset(tmp_v_addr
, 0, size
);
809 rx_blocks
->block_virt_addr
= tmp_v_addr
;
810 rx_blocks
->block_dma_addr
= tmp_p_addr
;
811 rx_blocks
->rxds
= kmalloc(sizeof(struct rxd_info
)*
812 rxd_count
[nic
->rxd_mode
],
814 if (!rx_blocks
->rxds
)
817 (sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
818 for (l
=0; l
<rxd_count
[nic
->rxd_mode
];l
++) {
819 rx_blocks
->rxds
[l
].virt_addr
=
820 rx_blocks
->block_virt_addr
+
821 (rxd_size
[nic
->rxd_mode
] * l
);
822 rx_blocks
->rxds
[l
].dma_addr
=
823 rx_blocks
->block_dma_addr
+
824 (rxd_size
[nic
->rxd_mode
] * l
);
827 /* Interlinking all Rx Blocks */
828 for (j
= 0; j
< blk_cnt
; j
++) {
830 mac_control
->rings
[i
].rx_blocks
[j
].block_virt_addr
;
832 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
833 blk_cnt
].block_virt_addr
;
835 mac_control
->rings
[i
].rx_blocks
[j
].block_dma_addr
;
837 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
838 blk_cnt
].block_dma_addr
;
840 pre_rxd_blk
= (struct RxD_block
*) tmp_v_addr
;
841 pre_rxd_blk
->reserved_2_pNext_RxD_block
=
842 (unsigned long) tmp_v_addr_next
;
843 pre_rxd_blk
->pNext_RxD_Blk_physical
=
844 (u64
) tmp_p_addr_next
;
847 if (nic
->rxd_mode
== RXD_MODE_3B
) {
849 * Allocation of Storages for buffer addresses in 2BUFF mode
850 * and the buffers as well.
852 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
853 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
854 (rxd_count
[nic
->rxd_mode
]+ 1);
855 mac_control
->rings
[i
].ba
=
856 kmalloc((sizeof(struct buffAdd
*) * blk_cnt
),
858 if (!mac_control
->rings
[i
].ba
)
860 mem_allocated
+=(sizeof(struct buffAdd
*) * blk_cnt
);
861 for (j
= 0; j
< blk_cnt
; j
++) {
863 mac_control
->rings
[i
].ba
[j
] =
864 kmalloc((sizeof(struct buffAdd
) *
865 (rxd_count
[nic
->rxd_mode
] + 1)),
867 if (!mac_control
->rings
[i
].ba
[j
])
869 mem_allocated
+= (sizeof(struct buffAdd
) * \
870 (rxd_count
[nic
->rxd_mode
] + 1));
871 while (k
!= rxd_count
[nic
->rxd_mode
]) {
872 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
874 ba
->ba_0_org
= (void *) kmalloc
875 (BUF0_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
879 (BUF0_LEN
+ ALIGN_SIZE
);
880 tmp
= (unsigned long)ba
->ba_0_org
;
882 tmp
&= ~((unsigned long) ALIGN_SIZE
);
883 ba
->ba_0
= (void *) tmp
;
885 ba
->ba_1_org
= (void *) kmalloc
886 (BUF1_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
890 += (BUF1_LEN
+ ALIGN_SIZE
);
891 tmp
= (unsigned long) ba
->ba_1_org
;
893 tmp
&= ~((unsigned long) ALIGN_SIZE
);
894 ba
->ba_1
= (void *) tmp
;
901 /* Allocation and initialization of Statistics block */
902 size
= sizeof(struct stat_block
);
903 mac_control
->stats_mem
= pci_alloc_consistent
904 (nic
->pdev
, size
, &mac_control
->stats_mem_phy
);
906 if (!mac_control
->stats_mem
) {
908 * In case of failure, free_shared_mem() is called, which
909 * should free any memory that was alloced till the
914 mem_allocated
+= size
;
915 mac_control
->stats_mem_sz
= size
;
917 tmp_v_addr
= mac_control
->stats_mem
;
918 mac_control
->stats_info
= (struct stat_block
*) tmp_v_addr
;
919 memset(tmp_v_addr
, 0, size
);
920 DBG_PRINT(INIT_DBG
, "%s:Ring Mem PHY: 0x%llx\n", dev
->name
,
921 (unsigned long long) tmp_p_addr
);
922 mac_control
->stats_info
->sw_stat
.mem_allocated
+= mem_allocated
;
927 * free_shared_mem - Free the allocated Memory
928 * @nic: Device private variable.
929 * Description: This function is to free all memory locations allocated by
930 * the init_shared_mem() function and return it to the kernel.
933 static void free_shared_mem(struct s2io_nic
*nic
)
935 int i
, j
, blk_cnt
, size
;
937 dma_addr_t tmp_p_addr
;
938 struct mac_info
*mac_control
;
939 struct config_param
*config
;
940 int lst_size
, lst_per_page
;
941 struct net_device
*dev
;
949 mac_control
= &nic
->mac_control
;
950 config
= &nic
->config
;
952 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
953 lst_per_page
= PAGE_SIZE
/ lst_size
;
955 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
956 page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
958 for (j
= 0; j
< page_num
; j
++) {
959 int mem_blks
= (j
* lst_per_page
);
960 if (!mac_control
->fifos
[i
].list_info
)
962 if (!mac_control
->fifos
[i
].list_info
[mem_blks
].
965 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
966 mac_control
->fifos
[i
].
969 mac_control
->fifos
[i
].
972 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
975 /* If we got a zero DMA address during allocation,
978 if (mac_control
->zerodma_virt_addr
) {
979 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
980 mac_control
->zerodma_virt_addr
,
983 "%s: Freeing TxDL with zero DMA addr. ",
985 DBG_PRINT(INIT_DBG
, "Virtual address %p\n",
986 mac_control
->zerodma_virt_addr
);
987 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
990 kfree(mac_control
->fifos
[i
].list_info
);
991 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
992 (nic
->config
.tx_cfg
[i
].fifo_len
*sizeof(struct list_info_hold
));
995 size
= SIZE_OF_BLOCK
;
996 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
997 blk_cnt
= mac_control
->rings
[i
].block_count
;
998 for (j
= 0; j
< blk_cnt
; j
++) {
999 tmp_v_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
1001 tmp_p_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
1003 if (tmp_v_addr
== NULL
)
1005 pci_free_consistent(nic
->pdev
, size
,
1006 tmp_v_addr
, tmp_p_addr
);
1007 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= size
;
1008 kfree(mac_control
->rings
[i
].rx_blocks
[j
].rxds
);
1009 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
1010 ( sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
1014 if (nic
->rxd_mode
== RXD_MODE_3B
) {
1015 /* Freeing buffer storage addresses in 2BUFF mode. */
1016 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1017 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
1018 (rxd_count
[nic
->rxd_mode
] + 1);
1019 for (j
= 0; j
< blk_cnt
; j
++) {
1021 if (!mac_control
->rings
[i
].ba
[j
])
1023 while (k
!= rxd_count
[nic
->rxd_mode
]) {
1024 struct buffAdd
*ba
=
1025 &mac_control
->rings
[i
].ba
[j
][k
];
1026 kfree(ba
->ba_0_org
);
1027 nic
->mac_control
.stats_info
->sw_stat
.\
1028 mem_freed
+= (BUF0_LEN
+ ALIGN_SIZE
);
1029 kfree(ba
->ba_1_org
);
1030 nic
->mac_control
.stats_info
->sw_stat
.\
1031 mem_freed
+= (BUF1_LEN
+ ALIGN_SIZE
);
1034 kfree(mac_control
->rings
[i
].ba
[j
]);
1035 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
1036 (sizeof(struct buffAdd
) *
1037 (rxd_count
[nic
->rxd_mode
] + 1));
1039 kfree(mac_control
->rings
[i
].ba
);
1040 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
1041 (sizeof(struct buffAdd
*) * blk_cnt
);
1045 for (i
= 0; i
< nic
->config
.tx_fifo_num
; i
++) {
1046 if (mac_control
->fifos
[i
].ufo_in_band_v
) {
1047 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
1048 += (config
->tx_cfg
[i
].fifo_len
* sizeof(u64
));
1049 kfree(mac_control
->fifos
[i
].ufo_in_band_v
);
1053 if (mac_control
->stats_mem
) {
1054 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
1055 mac_control
->stats_mem_sz
;
1056 pci_free_consistent(nic
->pdev
,
1057 mac_control
->stats_mem_sz
,
1058 mac_control
->stats_mem
,
1059 mac_control
->stats_mem_phy
);
1064 * s2io_verify_pci_mode -
1067 static int s2io_verify_pci_mode(struct s2io_nic
*nic
)
1069 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1070 register u64 val64
= 0;
1073 val64
= readq(&bar0
->pci_mode
);
1074 mode
= (u8
)GET_PCI_MODE(val64
);
1076 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
1077 return -1; /* Unknown PCI mode */
1081 #define NEC_VENID 0x1033
1082 #define NEC_DEVID 0x0125
1083 static int s2io_on_nec_bridge(struct pci_dev
*s2io_pdev
)
1085 struct pci_dev
*tdev
= NULL
;
1086 while ((tdev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, tdev
)) != NULL
) {
1087 if (tdev
->vendor
== NEC_VENID
&& tdev
->device
== NEC_DEVID
) {
1088 if (tdev
->bus
== s2io_pdev
->bus
->parent
) {
1097 static int bus_speed
[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1099 * s2io_print_pci_mode -
1101 static int s2io_print_pci_mode(struct s2io_nic
*nic
)
1103 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1104 register u64 val64
= 0;
1106 struct config_param
*config
= &nic
->config
;
1108 val64
= readq(&bar0
->pci_mode
);
1109 mode
= (u8
)GET_PCI_MODE(val64
);
1111 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
1112 return -1; /* Unknown PCI mode */
1114 config
->bus_speed
= bus_speed
[mode
];
1116 if (s2io_on_nec_bridge(nic
->pdev
)) {
1117 DBG_PRINT(ERR_DBG
, "%s: Device is on PCI-E bus\n",
1122 if (val64
& PCI_MODE_32_BITS
) {
1123 DBG_PRINT(ERR_DBG
, "%s: Device is on 32 bit ", nic
->dev
->name
);
1125 DBG_PRINT(ERR_DBG
, "%s: Device is on 64 bit ", nic
->dev
->name
);
1129 case PCI_MODE_PCI_33
:
1130 DBG_PRINT(ERR_DBG
, "33MHz PCI bus\n");
1132 case PCI_MODE_PCI_66
:
1133 DBG_PRINT(ERR_DBG
, "66MHz PCI bus\n");
1135 case PCI_MODE_PCIX_M1_66
:
1136 DBG_PRINT(ERR_DBG
, "66MHz PCIX(M1) bus\n");
1138 case PCI_MODE_PCIX_M1_100
:
1139 DBG_PRINT(ERR_DBG
, "100MHz PCIX(M1) bus\n");
1141 case PCI_MODE_PCIX_M1_133
:
1142 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M1) bus\n");
1144 case PCI_MODE_PCIX_M2_66
:
1145 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M2) bus\n");
1147 case PCI_MODE_PCIX_M2_100
:
1148 DBG_PRINT(ERR_DBG
, "200MHz PCIX(M2) bus\n");
1150 case PCI_MODE_PCIX_M2_133
:
1151 DBG_PRINT(ERR_DBG
, "266MHz PCIX(M2) bus\n");
1154 return -1; /* Unsupported bus speed */
1161 * init_tti - Initialization transmit traffic interrupt scheme
1162 * @nic: device private variable
1163 * @link: link status (UP/DOWN) used to enable/disable continuous
1164 * transmit interrupts
1165 * Description: The function configures transmit traffic interrupts
1166 * Return Value: SUCCESS on success and
1170 static int init_tti(struct s2io_nic
*nic
, int link
)
1172 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1173 register u64 val64
= 0;
1175 struct config_param
*config
;
1177 config
= &nic
->config
;
1179 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
1181 * TTI Initialization. Default Tx timer gets us about
1182 * 250 interrupts per sec. Continuous interrupts are enabled
1185 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1186 int count
= (nic
->config
.bus_speed
* 125)/2;
1187 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(count
);
1189 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1191 val64
|= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1192 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1193 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1194 TTI_DATA1_MEM_TX_TIMER_AC_EN
;
1196 if (use_continuous_tx_intrs
&& (link
== LINK_UP
))
1197 val64
|= TTI_DATA1_MEM_TX_TIMER_CI_EN
;
1198 writeq(val64
, &bar0
->tti_data1_mem
);
1200 if (nic
->config
.intr_type
== MSI_X
) {
1201 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1202 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1203 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1204 TTI_DATA2_MEM_TX_UFC_D(0x300);
1206 if ((nic
->config
.tx_steering_type
==
1207 TX_DEFAULT_STEERING
) &&
1208 (config
->tx_fifo_num
> 1) &&
1209 (i
>= nic
->udp_fifo_idx
) &&
1210 (i
< (nic
->udp_fifo_idx
+
1211 nic
->total_udp_fifos
)))
1212 val64
= TTI_DATA2_MEM_TX_UFC_A(0x50) |
1213 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1214 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1215 TTI_DATA2_MEM_TX_UFC_D(0x120);
1217 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1218 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1219 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1220 TTI_DATA2_MEM_TX_UFC_D(0x80);
1223 writeq(val64
, &bar0
->tti_data2_mem
);
1225 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
|
1226 TTI_CMD_MEM_OFFSET(i
);
1227 writeq(val64
, &bar0
->tti_command_mem
);
1229 if (wait_for_cmd_complete(&bar0
->tti_command_mem
,
1230 TTI_CMD_MEM_STROBE_NEW_CMD
, S2IO_BIT_RESET
) != SUCCESS
)
1238 * init_nic - Initialization of hardware
1239 * @nic: device private variable
1240 * Description: The function sequentially configures every block
1241 * of the H/W from their reset values.
1242 * Return Value: SUCCESS on success and
1243 * '-1' on failure (endian settings incorrect).
1246 static int init_nic(struct s2io_nic
*nic
)
1248 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1249 struct net_device
*dev
= nic
->dev
;
1250 register u64 val64
= 0;
1254 struct mac_info
*mac_control
;
1255 struct config_param
*config
;
1257 unsigned long long mem_share
;
1260 mac_control
= &nic
->mac_control
;
1261 config
= &nic
->config
;
1263 /* to set the swapper controle on the card */
1264 if(s2io_set_swapper(nic
)) {
1265 DBG_PRINT(ERR_DBG
,"ERROR: Setting Swapper failed\n");
1270 * Herc requires EOI to be removed from reset before XGXS, so..
1272 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1273 val64
= 0xA500000000ULL
;
1274 writeq(val64
, &bar0
->sw_reset
);
1276 val64
= readq(&bar0
->sw_reset
);
1279 /* Remove XGXS from reset state */
1281 writeq(val64
, &bar0
->sw_reset
);
1283 val64
= readq(&bar0
->sw_reset
);
1285 /* Ensure that it's safe to access registers by checking
1286 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1288 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1289 for (i
= 0; i
< 50; i
++) {
1290 val64
= readq(&bar0
->adapter_status
);
1291 if (!(val64
& ADAPTER_STATUS_RIC_RUNNING
))
1299 /* Enable Receiving broadcasts */
1300 add
= &bar0
->mac_cfg
;
1301 val64
= readq(&bar0
->mac_cfg
);
1302 val64
|= MAC_RMAC_BCAST_ENABLE
;
1303 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1304 writel((u32
) val64
, add
);
1305 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1306 writel((u32
) (val64
>> 32), (add
+ 4));
1308 /* Read registers in all blocks */
1309 val64
= readq(&bar0
->mac_int_mask
);
1310 val64
= readq(&bar0
->mc_int_mask
);
1311 val64
= readq(&bar0
->xgxs_int_mask
);
1315 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
1317 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1318 while (herc_act_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1319 SPECIAL_REG_WRITE(herc_act_dtx_cfg
[dtx_cnt
],
1320 &bar0
->dtx_control
, UF
);
1322 msleep(1); /* Necessary!! */
1326 while (xena_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1327 SPECIAL_REG_WRITE(xena_dtx_cfg
[dtx_cnt
],
1328 &bar0
->dtx_control
, UF
);
1329 val64
= readq(&bar0
->dtx_control
);
1334 /* Tx DMA Initialization */
1336 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1337 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1338 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1339 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1342 for (i
= 0, j
= 0; i
< config
->tx_fifo_num
; i
++) {
1344 vBIT(config
->tx_cfg
[i
].fifo_len
- 1, ((j
* 32) + 19),
1345 13) | vBIT(config
->tx_cfg
[i
].fifo_priority
,
1348 if (i
== (config
->tx_fifo_num
- 1)) {
1355 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1360 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1365 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1370 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1381 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1382 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1384 if ((nic
->device_type
== XFRAME_I_DEVICE
) &&
1385 (nic
->pdev
->revision
< 4))
1386 writeq(PCC_ENABLE_FOUR
, &bar0
->pcc_enable
);
1388 val64
= readq(&bar0
->tx_fifo_partition_0
);
1389 DBG_PRINT(INIT_DBG
, "Fifo partition at: 0x%p is: 0x%llx\n",
1390 &bar0
->tx_fifo_partition_0
, (unsigned long long) val64
);
1393 * Initialization of Tx_PA_CONFIG register to ignore packet
1394 * integrity checking.
1396 val64
= readq(&bar0
->tx_pa_cfg
);
1397 val64
|= TX_PA_CFG_IGNORE_FRM_ERR
| TX_PA_CFG_IGNORE_SNAP_OUI
|
1398 TX_PA_CFG_IGNORE_LLC_CTRL
| TX_PA_CFG_IGNORE_L2_ERR
;
1399 writeq(val64
, &bar0
->tx_pa_cfg
);
1401 /* Rx DMA intialization. */
1403 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1405 vBIT(config
->rx_cfg
[i
].ring_priority
, (5 + (i
* 8)),
1408 writeq(val64
, &bar0
->rx_queue_priority
);
1411 * Allocating equal share of memory to all the
1415 if (nic
->device_type
& XFRAME_II_DEVICE
)
1420 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1423 mem_share
= (mem_size
/ config
->rx_ring_num
+
1424 mem_size
% config
->rx_ring_num
);
1425 val64
|= RX_QUEUE_CFG_Q0_SZ(mem_share
);
1428 mem_share
= (mem_size
/ config
->rx_ring_num
);
1429 val64
|= RX_QUEUE_CFG_Q1_SZ(mem_share
);
1432 mem_share
= (mem_size
/ config
->rx_ring_num
);
1433 val64
|= RX_QUEUE_CFG_Q2_SZ(mem_share
);
1436 mem_share
= (mem_size
/ config
->rx_ring_num
);
1437 val64
|= RX_QUEUE_CFG_Q3_SZ(mem_share
);
1440 mem_share
= (mem_size
/ config
->rx_ring_num
);
1441 val64
|= RX_QUEUE_CFG_Q4_SZ(mem_share
);
1444 mem_share
= (mem_size
/ config
->rx_ring_num
);
1445 val64
|= RX_QUEUE_CFG_Q5_SZ(mem_share
);
1448 mem_share
= (mem_size
/ config
->rx_ring_num
);
1449 val64
|= RX_QUEUE_CFG_Q6_SZ(mem_share
);
1452 mem_share
= (mem_size
/ config
->rx_ring_num
);
1453 val64
|= RX_QUEUE_CFG_Q7_SZ(mem_share
);
1457 writeq(val64
, &bar0
->rx_queue_cfg
);
1460 * Filling Tx round robin registers
1461 * as per the number of FIFOs for equal scheduling priority
1463 switch (config
->tx_fifo_num
) {
1466 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1467 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1468 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1469 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1470 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1473 val64
= 0x0001000100010001ULL
;
1474 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1475 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1476 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1477 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1478 val64
= 0x0001000100000000ULL
;
1479 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1482 val64
= 0x0001020001020001ULL
;
1483 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1484 val64
= 0x0200010200010200ULL
;
1485 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1486 val64
= 0x0102000102000102ULL
;
1487 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1488 val64
= 0x0001020001020001ULL
;
1489 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1490 val64
= 0x0200010200000000ULL
;
1491 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1494 val64
= 0x0001020300010203ULL
;
1495 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1496 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1497 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1498 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1499 val64
= 0x0001020300000000ULL
;
1500 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1503 val64
= 0x0001020304000102ULL
;
1504 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1505 val64
= 0x0304000102030400ULL
;
1506 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1507 val64
= 0x0102030400010203ULL
;
1508 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1509 val64
= 0x0400010203040001ULL
;
1510 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1511 val64
= 0x0203040000000000ULL
;
1512 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1515 val64
= 0x0001020304050001ULL
;
1516 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1517 val64
= 0x0203040500010203ULL
;
1518 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1519 val64
= 0x0405000102030405ULL
;
1520 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1521 val64
= 0x0001020304050001ULL
;
1522 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1523 val64
= 0x0203040500000000ULL
;
1524 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1527 val64
= 0x0001020304050600ULL
;
1528 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1529 val64
= 0x0102030405060001ULL
;
1530 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1531 val64
= 0x0203040506000102ULL
;
1532 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1533 val64
= 0x0304050600010203ULL
;
1534 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1535 val64
= 0x0405060000000000ULL
;
1536 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1539 val64
= 0x0001020304050607ULL
;
1540 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1541 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1542 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1543 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1544 val64
= 0x0001020300000000ULL
;
1545 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1549 /* Enable all configured Tx FIFO partitions */
1550 val64
= readq(&bar0
->tx_fifo_partition_0
);
1551 val64
|= (TX_FIFO_PARTITION_EN
);
1552 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1554 /* Filling the Rx round robin registers as per the
1555 * number of Rings and steering based on QoS with
1558 switch (config
->rx_ring_num
) {
1561 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1562 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1563 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1564 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1565 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1567 val64
= 0x8080808080808080ULL
;
1568 writeq(val64
, &bar0
->rts_qos_steering
);
1571 val64
= 0x0001000100010001ULL
;
1572 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1573 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1574 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1575 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1576 val64
= 0x0001000100000000ULL
;
1577 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1579 val64
= 0x8080808040404040ULL
;
1580 writeq(val64
, &bar0
->rts_qos_steering
);
1583 val64
= 0x0001020001020001ULL
;
1584 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1585 val64
= 0x0200010200010200ULL
;
1586 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1587 val64
= 0x0102000102000102ULL
;
1588 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1589 val64
= 0x0001020001020001ULL
;
1590 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1591 val64
= 0x0200010200000000ULL
;
1592 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1594 val64
= 0x8080804040402020ULL
;
1595 writeq(val64
, &bar0
->rts_qos_steering
);
1598 val64
= 0x0001020300010203ULL
;
1599 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1600 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1601 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1602 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1603 val64
= 0x0001020300000000ULL
;
1604 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1606 val64
= 0x8080404020201010ULL
;
1607 writeq(val64
, &bar0
->rts_qos_steering
);
1610 val64
= 0x0001020304000102ULL
;
1611 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1612 val64
= 0x0304000102030400ULL
;
1613 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1614 val64
= 0x0102030400010203ULL
;
1615 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1616 val64
= 0x0400010203040001ULL
;
1617 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1618 val64
= 0x0203040000000000ULL
;
1619 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1621 val64
= 0x8080404020201008ULL
;
1622 writeq(val64
, &bar0
->rts_qos_steering
);
1625 val64
= 0x0001020304050001ULL
;
1626 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1627 val64
= 0x0203040500010203ULL
;
1628 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1629 val64
= 0x0405000102030405ULL
;
1630 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1631 val64
= 0x0001020304050001ULL
;
1632 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1633 val64
= 0x0203040500000000ULL
;
1634 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1636 val64
= 0x8080404020100804ULL
;
1637 writeq(val64
, &bar0
->rts_qos_steering
);
1640 val64
= 0x0001020304050600ULL
;
1641 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1642 val64
= 0x0102030405060001ULL
;
1643 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1644 val64
= 0x0203040506000102ULL
;
1645 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1646 val64
= 0x0304050600010203ULL
;
1647 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1648 val64
= 0x0405060000000000ULL
;
1649 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1651 val64
= 0x8080402010080402ULL
;
1652 writeq(val64
, &bar0
->rts_qos_steering
);
1655 val64
= 0x0001020304050607ULL
;
1656 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1657 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1658 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1659 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1660 val64
= 0x0001020300000000ULL
;
1661 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1663 val64
= 0x8040201008040201ULL
;
1664 writeq(val64
, &bar0
->rts_qos_steering
);
1670 for (i
= 0; i
< 8; i
++)
1671 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1673 /* Set the default rts frame length for the rings configured */
1674 val64
= MAC_RTS_FRM_LEN_SET(dev
->mtu
+22);
1675 for (i
= 0 ; i
< config
->rx_ring_num
; i
++)
1676 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1678 /* Set the frame length for the configured rings
1679 * desired by the user
1681 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1682 /* If rts_frm_len[i] == 0 then it is assumed that user not
1683 * specified frame length steering.
1684 * If the user provides the frame length then program
1685 * the rts_frm_len register for those values or else
1686 * leave it as it is.
1688 if (rts_frm_len
[i
] != 0) {
1689 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len
[i
]),
1690 &bar0
->rts_frm_len_n
[i
]);
1694 /* Disable differentiated services steering logic */
1695 for (i
= 0; i
< 64; i
++) {
1696 if (rts_ds_steer(nic
, i
, 0) == FAILURE
) {
1697 DBG_PRINT(ERR_DBG
, "%s: failed rts ds steering",
1699 DBG_PRINT(ERR_DBG
, "set on codepoint %d\n", i
);
1704 /* Program statistics memory */
1705 writeq(mac_control
->stats_mem_phy
, &bar0
->stat_addr
);
1707 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1708 val64
= STAT_BC(0x320);
1709 writeq(val64
, &bar0
->stat_byte_cnt
);
1713 * Initializing the sampling rate for the device to calculate the
1714 * bandwidth utilization.
1716 val64
= MAC_TX_LINK_UTIL_VAL(tmac_util_period
) |
1717 MAC_RX_LINK_UTIL_VAL(rmac_util_period
);
1718 writeq(val64
, &bar0
->mac_link_util
);
1721 * Initializing the Transmit and Receive Traffic Interrupt
1725 /* Initialize TTI */
1726 if (SUCCESS
!= init_tti(nic
, nic
->last_link_state
))
1729 /* RTI Initialization */
1730 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1732 * Programmed to generate Apprx 500 Intrs per
1735 int count
= (nic
->config
.bus_speed
* 125)/4;
1736 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(count
);
1738 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1739 val64
|= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1740 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1741 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN
;
1743 writeq(val64
, &bar0
->rti_data1_mem
);
1745 val64
= RTI_DATA2_MEM_RX_UFC_A(0x1) |
1746 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1747 if (nic
->config
.intr_type
== MSI_X
)
1748 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1749 RTI_DATA2_MEM_RX_UFC_D(0x40));
1751 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1752 RTI_DATA2_MEM_RX_UFC_D(0x80));
1753 writeq(val64
, &bar0
->rti_data2_mem
);
1755 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1756 val64
= RTI_CMD_MEM_WE
| RTI_CMD_MEM_STROBE_NEW_CMD
1757 | RTI_CMD_MEM_OFFSET(i
);
1758 writeq(val64
, &bar0
->rti_command_mem
);
1761 * Once the operation completes, the Strobe bit of the
1762 * command register will be reset. We poll for this
1763 * particular condition. We wait for a maximum of 500ms
1764 * for the operation to complete, if it's not complete
1765 * by then we return error.
1769 val64
= readq(&bar0
->rti_command_mem
);
1770 if (!(val64
& RTI_CMD_MEM_STROBE_NEW_CMD
))
1774 DBG_PRINT(ERR_DBG
, "%s: RTI init Failed\n",
1784 * Initializing proper values as Pause threshold into all
1785 * the 8 Queues on Rx side.
1787 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q0q3
);
1788 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q4q7
);
1790 /* Disable RMAC PAD STRIPPING */
1791 add
= &bar0
->mac_cfg
;
1792 val64
= readq(&bar0
->mac_cfg
);
1793 val64
&= ~(MAC_CFG_RMAC_STRIP_PAD
);
1794 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1795 writel((u32
) (val64
), add
);
1796 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1797 writel((u32
) (val64
>> 32), (add
+ 4));
1798 val64
= readq(&bar0
->mac_cfg
);
1800 /* Enable FCS stripping by adapter */
1801 add
= &bar0
->mac_cfg
;
1802 val64
= readq(&bar0
->mac_cfg
);
1803 val64
|= MAC_CFG_RMAC_STRIP_FCS
;
1804 if (nic
->device_type
== XFRAME_II_DEVICE
)
1805 writeq(val64
, &bar0
->mac_cfg
);
1807 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1808 writel((u32
) (val64
), add
);
1809 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1810 writel((u32
) (val64
>> 32), (add
+ 4));
1814 * Set the time value to be inserted in the pause frame
1815 * generated by xena.
1817 val64
= readq(&bar0
->rmac_pause_cfg
);
1818 val64
&= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1819 val64
|= RMAC_PAUSE_HG_PTIME(nic
->mac_control
.rmac_pause_time
);
1820 writeq(val64
, &bar0
->rmac_pause_cfg
);
1823 * Set the Threshold Limit for Generating the pause frame
1824 * If the amount of data in any Queue exceeds ratio of
1825 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1826 * pause frame is generated
1829 for (i
= 0; i
< 4; i
++) {
1831 (((u64
) 0xFF00 | nic
->mac_control
.
1832 mc_pause_threshold_q0q3
)
1835 writeq(val64
, &bar0
->mc_pause_thresh_q0q3
);
1838 for (i
= 0; i
< 4; i
++) {
1840 (((u64
) 0xFF00 | nic
->mac_control
.
1841 mc_pause_threshold_q4q7
)
1844 writeq(val64
, &bar0
->mc_pause_thresh_q4q7
);
1847 * TxDMA will stop Read request if the number of read split has
1848 * exceeded the limit pointed by shared_splits
1850 val64
= readq(&bar0
->pic_control
);
1851 val64
|= PIC_CNTL_SHARED_SPLITS(shared_splits
);
1852 writeq(val64
, &bar0
->pic_control
);
1854 if (nic
->config
.bus_speed
== 266) {
1855 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN
, &bar0
->txreqtimeout
);
1856 writeq(0x0, &bar0
->read_retry_delay
);
1857 writeq(0x0, &bar0
->write_retry_delay
);
1861 * Programming the Herc to split every write transaction
1862 * that does not start on an ADB to reduce disconnects.
1864 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1865 val64
= FAULT_BEHAVIOUR
| EXT_REQ_EN
|
1866 MISC_LINK_STABILITY_PRD(3);
1867 writeq(val64
, &bar0
->misc_control
);
1868 val64
= readq(&bar0
->pic_control2
);
1869 val64
&= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1870 writeq(val64
, &bar0
->pic_control2
);
1872 if (strstr(nic
->product_name
, "CX4")) {
1873 val64
= TMAC_AVG_IPG(0x17);
1874 writeq(val64
, &bar0
->tmac_avg_ipg
);
1879 #define LINK_UP_DOWN_INTERRUPT 1
1880 #define MAC_RMAC_ERR_TIMER 2
1882 static int s2io_link_fault_indication(struct s2io_nic
*nic
)
1884 if (nic
->device_type
== XFRAME_II_DEVICE
)
1885 return LINK_UP_DOWN_INTERRUPT
;
1887 return MAC_RMAC_ERR_TIMER
;
1891 * do_s2io_write_bits - update alarm bits in alarm register
1892 * @value: alarm bits
1893 * @flag: interrupt status
1894 * @addr: address value
1895 * Description: update alarm bits in alarm register
1899 static void do_s2io_write_bits(u64 value
, int flag
, void __iomem
*addr
)
1903 temp64
= readq(addr
);
1905 if(flag
== ENABLE_INTRS
)
1906 temp64
&= ~((u64
) value
);
1908 temp64
|= ((u64
) value
);
1909 writeq(temp64
, addr
);
1912 static void en_dis_err_alarms(struct s2io_nic
*nic
, u16 mask
, int flag
)
1914 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1915 register u64 gen_int_mask
= 0;
1918 writeq(DISABLE_ALL_INTRS
, &bar0
->general_int_mask
);
1919 if (mask
& TX_DMA_INTR
) {
1921 gen_int_mask
|= TXDMA_INT_M
;
1923 do_s2io_write_bits(TXDMA_TDA_INT
| TXDMA_PFC_INT
|
1924 TXDMA_PCC_INT
| TXDMA_TTI_INT
|
1925 TXDMA_LSO_INT
| TXDMA_TPA_INT
|
1926 TXDMA_SM_INT
, flag
, &bar0
->txdma_int_mask
);
1928 do_s2io_write_bits(PFC_ECC_DB_ERR
| PFC_SM_ERR_ALARM
|
1929 PFC_MISC_0_ERR
| PFC_MISC_1_ERR
|
1930 PFC_PCIX_ERR
| PFC_ECC_SG_ERR
, flag
,
1931 &bar0
->pfc_err_mask
);
1933 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR
| TDA_SM0_ERR_ALARM
|
1934 TDA_SM1_ERR_ALARM
| TDA_Fn_ECC_SG_ERR
|
1935 TDA_PCIX_ERR
, flag
, &bar0
->tda_err_mask
);
1937 do_s2io_write_bits(PCC_FB_ECC_DB_ERR
| PCC_TXB_ECC_DB_ERR
|
1938 PCC_SM_ERR_ALARM
| PCC_WR_ERR_ALARM
|
1939 PCC_N_SERR
| PCC_6_COF_OV_ERR
|
1940 PCC_7_COF_OV_ERR
| PCC_6_LSO_OV_ERR
|
1941 PCC_7_LSO_OV_ERR
| PCC_FB_ECC_SG_ERR
|
1942 PCC_TXB_ECC_SG_ERR
, flag
, &bar0
->pcc_err_mask
);
1944 do_s2io_write_bits(TTI_SM_ERR_ALARM
| TTI_ECC_SG_ERR
|
1945 TTI_ECC_DB_ERR
, flag
, &bar0
->tti_err_mask
);
1947 do_s2io_write_bits(LSO6_ABORT
| LSO7_ABORT
|
1948 LSO6_SM_ERR_ALARM
| LSO7_SM_ERR_ALARM
|
1949 LSO6_SEND_OFLOW
| LSO7_SEND_OFLOW
,
1950 flag
, &bar0
->lso_err_mask
);
1952 do_s2io_write_bits(TPA_SM_ERR_ALARM
| TPA_TX_FRM_DROP
,
1953 flag
, &bar0
->tpa_err_mask
);
1955 do_s2io_write_bits(SM_SM_ERR_ALARM
, flag
, &bar0
->sm_err_mask
);
1959 if (mask
& TX_MAC_INTR
) {
1960 gen_int_mask
|= TXMAC_INT_M
;
1961 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT
, flag
,
1962 &bar0
->mac_int_mask
);
1963 do_s2io_write_bits(TMAC_TX_BUF_OVRN
| TMAC_TX_SM_ERR
|
1964 TMAC_ECC_SG_ERR
| TMAC_ECC_DB_ERR
|
1965 TMAC_DESC_ECC_SG_ERR
| TMAC_DESC_ECC_DB_ERR
,
1966 flag
, &bar0
->mac_tmac_err_mask
);
1969 if (mask
& TX_XGXS_INTR
) {
1970 gen_int_mask
|= TXXGXS_INT_M
;
1971 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS
, flag
,
1972 &bar0
->xgxs_int_mask
);
1973 do_s2io_write_bits(TXGXS_ESTORE_UFLOW
| TXGXS_TX_SM_ERR
|
1974 TXGXS_ECC_SG_ERR
| TXGXS_ECC_DB_ERR
,
1975 flag
, &bar0
->xgxs_txgxs_err_mask
);
1978 if (mask
& RX_DMA_INTR
) {
1979 gen_int_mask
|= RXDMA_INT_M
;
1980 do_s2io_write_bits(RXDMA_INT_RC_INT_M
| RXDMA_INT_RPA_INT_M
|
1981 RXDMA_INT_RDA_INT_M
| RXDMA_INT_RTI_INT_M
,
1982 flag
, &bar0
->rxdma_int_mask
);
1983 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR
| RC_FTC_ECC_DB_ERR
|
1984 RC_PRCn_SM_ERR_ALARM
| RC_FTC_SM_ERR_ALARM
|
1985 RC_PRCn_ECC_SG_ERR
| RC_FTC_ECC_SG_ERR
|
1986 RC_RDA_FAIL_WR_Rn
, flag
, &bar0
->rc_err_mask
);
1987 do_s2io_write_bits(PRC_PCI_AB_RD_Rn
| PRC_PCI_AB_WR_Rn
|
1988 PRC_PCI_AB_F_WR_Rn
| PRC_PCI_DP_RD_Rn
|
1989 PRC_PCI_DP_WR_Rn
| PRC_PCI_DP_F_WR_Rn
, flag
,
1990 &bar0
->prc_pcix_err_mask
);
1991 do_s2io_write_bits(RPA_SM_ERR_ALARM
| RPA_CREDIT_ERR
|
1992 RPA_ECC_SG_ERR
| RPA_ECC_DB_ERR
, flag
,
1993 &bar0
->rpa_err_mask
);
1994 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR
| RDA_FRM_ECC_DB_N_AERR
|
1995 RDA_SM1_ERR_ALARM
| RDA_SM0_ERR_ALARM
|
1996 RDA_RXD_ECC_DB_SERR
| RDA_RXDn_ECC_SG_ERR
|
1997 RDA_FRM_ECC_SG_ERR
| RDA_MISC_ERR
|RDA_PCIX_ERR
,
1998 flag
, &bar0
->rda_err_mask
);
1999 do_s2io_write_bits(RTI_SM_ERR_ALARM
|
2000 RTI_ECC_SG_ERR
| RTI_ECC_DB_ERR
,
2001 flag
, &bar0
->rti_err_mask
);
2004 if (mask
& RX_MAC_INTR
) {
2005 gen_int_mask
|= RXMAC_INT_M
;
2006 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT
, flag
,
2007 &bar0
->mac_int_mask
);
2008 interruptible
= RMAC_RX_BUFF_OVRN
| RMAC_RX_SM_ERR
|
2009 RMAC_UNUSED_INT
| RMAC_SINGLE_ECC_ERR
|
2010 RMAC_DOUBLE_ECC_ERR
;
2011 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
)
2012 interruptible
|= RMAC_LINK_STATE_CHANGE_INT
;
2013 do_s2io_write_bits(interruptible
,
2014 flag
, &bar0
->mac_rmac_err_mask
);
2017 if (mask
& RX_XGXS_INTR
)
2019 gen_int_mask
|= RXXGXS_INT_M
;
2020 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS
, flag
,
2021 &bar0
->xgxs_int_mask
);
2022 do_s2io_write_bits(RXGXS_ESTORE_OFLOW
| RXGXS_RX_SM_ERR
, flag
,
2023 &bar0
->xgxs_rxgxs_err_mask
);
2026 if (mask
& MC_INTR
) {
2027 gen_int_mask
|= MC_INT_M
;
2028 do_s2io_write_bits(MC_INT_MASK_MC_INT
, flag
, &bar0
->mc_int_mask
);
2029 do_s2io_write_bits(MC_ERR_REG_SM_ERR
| MC_ERR_REG_ECC_ALL_SNG
|
2030 MC_ERR_REG_ECC_ALL_DBL
| PLL_LOCK_N
, flag
,
2031 &bar0
->mc_err_mask
);
2033 nic
->general_int_mask
= gen_int_mask
;
2035 /* Remove this line when alarm interrupts are enabled */
2036 nic
->general_int_mask
= 0;
2039 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2040 * @nic: device private variable,
2041 * @mask: A mask indicating which Intr block must be modified and,
2042 * @flag: A flag indicating whether to enable or disable the Intrs.
2043 * Description: This function will either disable or enable the interrupts
2044 * depending on the flag argument. The mask argument can be used to
2045 * enable/disable any Intr block.
2046 * Return Value: NONE.
2049 static void en_dis_able_nic_intrs(struct s2io_nic
*nic
, u16 mask
, int flag
)
2051 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2052 register u64 temp64
= 0, intr_mask
= 0;
2054 intr_mask
= nic
->general_int_mask
;
2056 /* Top level interrupt classification */
2057 /* PIC Interrupts */
2058 if (mask
& TX_PIC_INTR
) {
2059 /* Enable PIC Intrs in the general intr mask register */
2060 intr_mask
|= TXPIC_INT_M
;
2061 if (flag
== ENABLE_INTRS
) {
2063 * If Hercules adapter enable GPIO otherwise
2064 * disable all PCIX, Flash, MDIO, IIC and GPIO
2065 * interrupts for now.
2068 if (s2io_link_fault_indication(nic
) ==
2069 LINK_UP_DOWN_INTERRUPT
) {
2070 do_s2io_write_bits(PIC_INT_GPIO
, flag
,
2071 &bar0
->pic_int_mask
);
2072 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP
, flag
,
2073 &bar0
->gpio_int_mask
);
2075 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
2076 } else if (flag
== DISABLE_INTRS
) {
2078 * Disable PIC Intrs in the general
2079 * intr mask register
2081 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
2085 /* Tx traffic interrupts */
2086 if (mask
& TX_TRAFFIC_INTR
) {
2087 intr_mask
|= TXTRAFFIC_INT_M
;
2088 if (flag
== ENABLE_INTRS
) {
2090 * Enable all the Tx side interrupts
2091 * writing 0 Enables all 64 TX interrupt levels
2093 writeq(0x0, &bar0
->tx_traffic_mask
);
2094 } else if (flag
== DISABLE_INTRS
) {
2096 * Disable Tx Traffic Intrs in the general intr mask
2099 writeq(DISABLE_ALL_INTRS
, &bar0
->tx_traffic_mask
);
2103 /* Rx traffic interrupts */
2104 if (mask
& RX_TRAFFIC_INTR
) {
2105 intr_mask
|= RXTRAFFIC_INT_M
;
2106 if (flag
== ENABLE_INTRS
) {
2107 /* writing 0 Enables all 8 RX interrupt levels */
2108 writeq(0x0, &bar0
->rx_traffic_mask
);
2109 } else if (flag
== DISABLE_INTRS
) {
2111 * Disable Rx Traffic Intrs in the general intr mask
2114 writeq(DISABLE_ALL_INTRS
, &bar0
->rx_traffic_mask
);
2118 temp64
= readq(&bar0
->general_int_mask
);
2119 if (flag
== ENABLE_INTRS
)
2120 temp64
&= ~((u64
) intr_mask
);
2122 temp64
= DISABLE_ALL_INTRS
;
2123 writeq(temp64
, &bar0
->general_int_mask
);
2125 nic
->general_int_mask
= readq(&bar0
->general_int_mask
);
2129 * verify_pcc_quiescent- Checks for PCC quiescent state
2130 * Return: 1 If PCC is quiescence
2131 * 0 If PCC is not quiescence
2133 static int verify_pcc_quiescent(struct s2io_nic
*sp
, int flag
)
2136 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2137 u64 val64
= readq(&bar0
->adapter_status
);
2139 herc
= (sp
->device_type
== XFRAME_II_DEVICE
);
2141 if (flag
== FALSE
) {
2142 if ((!herc
&& (sp
->pdev
->revision
>= 4)) || herc
) {
2143 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
))
2146 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
2150 if ((!herc
&& (sp
->pdev
->revision
>= 4)) || herc
) {
2151 if (((val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) ==
2152 ADAPTER_STATUS_RMAC_PCC_IDLE
))
2155 if (((val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) ==
2156 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
2164 * verify_xena_quiescence - Checks whether the H/W is ready
2165 * Description: Returns whether the H/W is ready to go or not. Depending
2166 * on whether adapter enable bit was written or not the comparison
2167 * differs and the calling function passes the input argument flag to
2169 * Return: 1 If xena is quiescence
2170 * 0 If Xena is not quiescence
2173 static int verify_xena_quiescence(struct s2io_nic
*sp
)
2176 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2177 u64 val64
= readq(&bar0
->adapter_status
);
2178 mode
= s2io_verify_pci_mode(sp
);
2180 if (!(val64
& ADAPTER_STATUS_TDMA_READY
)) {
2181 DBG_PRINT(ERR_DBG
, "%s", "TDMA is not ready!");
2184 if (!(val64
& ADAPTER_STATUS_RDMA_READY
)) {
2185 DBG_PRINT(ERR_DBG
, "%s", "RDMA is not ready!");
2188 if (!(val64
& ADAPTER_STATUS_PFC_READY
)) {
2189 DBG_PRINT(ERR_DBG
, "%s", "PFC is not ready!");
2192 if (!(val64
& ADAPTER_STATUS_TMAC_BUF_EMPTY
)) {
2193 DBG_PRINT(ERR_DBG
, "%s", "TMAC BUF is not empty!");
2196 if (!(val64
& ADAPTER_STATUS_PIC_QUIESCENT
)) {
2197 DBG_PRINT(ERR_DBG
, "%s", "PIC is not QUIESCENT!");
2200 if (!(val64
& ADAPTER_STATUS_MC_DRAM_READY
)) {
2201 DBG_PRINT(ERR_DBG
, "%s", "MC_DRAM is not ready!");
2204 if (!(val64
& ADAPTER_STATUS_MC_QUEUES_READY
)) {
2205 DBG_PRINT(ERR_DBG
, "%s", "MC_QUEUES is not ready!");
2208 if (!(val64
& ADAPTER_STATUS_M_PLL_LOCK
)) {
2209 DBG_PRINT(ERR_DBG
, "%s", "M_PLL is not locked!");
2214 * In PCI 33 mode, the P_PLL is not used, and therefore,
2215 * the the P_PLL_LOCK bit in the adapter_status register will
2218 if (!(val64
& ADAPTER_STATUS_P_PLL_LOCK
) &&
2219 sp
->device_type
== XFRAME_II_DEVICE
&& mode
!=
2221 DBG_PRINT(ERR_DBG
, "%s", "P_PLL is not locked!");
2224 if (!((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
2225 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
2226 DBG_PRINT(ERR_DBG
, "%s", "RC_PRC is not QUIESCENT!");
2233 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2234 * @sp: Pointer to device specifc structure
2236 * New procedure to clear mac address reading problems on Alpha platforms
2240 static void fix_mac_address(struct s2io_nic
* sp
)
2242 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2246 while (fix_mac
[i
] != END_SIGN
) {
2247 writeq(fix_mac
[i
++], &bar0
->gpio_control
);
2249 val64
= readq(&bar0
->gpio_control
);
2254 * start_nic - Turns the device on
2255 * @nic : device private variable.
2257 * This function actually turns the device on. Before this function is
2258 * called,all Registers are configured from their reset states
2259 * and shared memory is allocated but the NIC is still quiescent. On
2260 * calling this function, the device interrupts are cleared and the NIC is
2261 * literally switched on by writing into the adapter control register.
2263 * SUCCESS on success and -1 on failure.
2266 static int start_nic(struct s2io_nic
*nic
)
2268 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2269 struct net_device
*dev
= nic
->dev
;
2270 register u64 val64
= 0;
2272 struct mac_info
*mac_control
;
2273 struct config_param
*config
;
2275 mac_control
= &nic
->mac_control
;
2276 config
= &nic
->config
;
2278 /* PRC Initialization and configuration */
2279 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2280 writeq((u64
) mac_control
->rings
[i
].rx_blocks
[0].block_dma_addr
,
2281 &bar0
->prc_rxd0_n
[i
]);
2283 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
2284 if (nic
->rxd_mode
== RXD_MODE_1
)
2285 val64
|= PRC_CTRL_RC_ENABLED
;
2287 val64
|= PRC_CTRL_RC_ENABLED
| PRC_CTRL_RING_MODE_3
;
2288 if (nic
->device_type
== XFRAME_II_DEVICE
)
2289 val64
|= PRC_CTRL_GROUP_READS
;
2290 val64
&= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2291 val64
|= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2292 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
2295 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2296 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2297 val64
= readq(&bar0
->rx_pa_cfg
);
2298 val64
|= RX_PA_CFG_IGNORE_L2_ERR
;
2299 writeq(val64
, &bar0
->rx_pa_cfg
);
2302 if (vlan_tag_strip
== 0) {
2303 val64
= readq(&bar0
->rx_pa_cfg
);
2304 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
2305 writeq(val64
, &bar0
->rx_pa_cfg
);
2306 vlan_strip_flag
= 0;
2310 * Enabling MC-RLDRAM. After enabling the device, we timeout
2311 * for around 100ms, which is approximately the time required
2312 * for the device to be ready for operation.
2314 val64
= readq(&bar0
->mc_rldram_mrs
);
2315 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
| MC_RLDRAM_MRS_ENABLE
;
2316 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
2317 val64
= readq(&bar0
->mc_rldram_mrs
);
2319 msleep(100); /* Delay by around 100 ms. */
2321 /* Enabling ECC Protection. */
2322 val64
= readq(&bar0
->adapter_control
);
2323 val64
&= ~ADAPTER_ECC_EN
;
2324 writeq(val64
, &bar0
->adapter_control
);
2327 * Verify if the device is ready to be enabled, if so enable
2330 val64
= readq(&bar0
->adapter_status
);
2331 if (!verify_xena_quiescence(nic
)) {
2332 DBG_PRINT(ERR_DBG
, "%s: device is not ready, ", dev
->name
);
2333 DBG_PRINT(ERR_DBG
, "Adapter status reads: 0x%llx\n",
2334 (unsigned long long) val64
);
2339 * With some switches, link might be already up at this point.
2340 * Because of this weird behavior, when we enable laser,
2341 * we may not get link. We need to handle this. We cannot
2342 * figure out which switch is misbehaving. So we are forced to
2343 * make a global change.
2346 /* Enabling Laser. */
2347 val64
= readq(&bar0
->adapter_control
);
2348 val64
|= ADAPTER_EOI_TX_ON
;
2349 writeq(val64
, &bar0
->adapter_control
);
2351 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
2353 * Dont see link state interrupts initally on some switches,
2354 * so directly scheduling the link state task here.
2356 schedule_work(&nic
->set_link_task
);
2358 /* SXE-002: Initialize link and activity LED */
2359 subid
= nic
->pdev
->subsystem_device
;
2360 if (((subid
& 0xFF) >= 0x07) &&
2361 (nic
->device_type
== XFRAME_I_DEVICE
)) {
2362 val64
= readq(&bar0
->gpio_control
);
2363 val64
|= 0x0000800000000000ULL
;
2364 writeq(val64
, &bar0
->gpio_control
);
2365 val64
= 0x0411040400000000ULL
;
2366 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
2372 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2374 static struct sk_buff
*s2io_txdl_getskb(struct fifo_info
*fifo_data
, struct \
2375 TxD
*txdlp
, int get_off
)
2377 struct s2io_nic
*nic
= fifo_data
->nic
;
2378 struct sk_buff
*skb
;
2383 if (txds
->Host_Control
== (u64
)(long)fifo_data
->ufo_in_band_v
) {
2384 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2385 txds
->Buffer_Pointer
, sizeof(u64
),
2390 skb
= (struct sk_buff
*) ((unsigned long)
2391 txds
->Host_Control
);
2393 memset(txdlp
, 0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2396 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2397 txds
->Buffer_Pointer
,
2398 skb
->len
- skb
->data_len
,
2400 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2403 for (j
= 0; j
< frg_cnt
; j
++, txds
++) {
2404 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
2405 if (!txds
->Buffer_Pointer
)
2407 pci_unmap_page(nic
->pdev
, (dma_addr_t
)
2408 txds
->Buffer_Pointer
,
2409 frag
->size
, PCI_DMA_TODEVICE
);
2412 memset(txdlp
,0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2417 * free_tx_buffers - Free all queued Tx buffers
2418 * @nic : device private variable.
2420 * Free all queued Tx buffers.
2421 * Return Value: void
2424 static void free_tx_buffers(struct s2io_nic
*nic
)
2426 struct net_device
*dev
= nic
->dev
;
2427 struct sk_buff
*skb
;
2430 struct mac_info
*mac_control
;
2431 struct config_param
*config
;
2434 mac_control
= &nic
->mac_control
;
2435 config
= &nic
->config
;
2437 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
2438 unsigned long flags
;
2439 spin_lock_irqsave(&mac_control
->fifos
[i
].tx_lock
, flags
);
2440 for (j
= 0; j
< config
->tx_cfg
[i
].fifo_len
; j
++) {
2441 txdp
= (struct TxD
*) \
2442 mac_control
->fifos
[i
].list_info
[j
].list_virt_addr
;
2443 skb
= s2io_txdl_getskb(&mac_control
->fifos
[i
], txdp
, j
);
2445 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
2452 "%s:forcibly freeing %d skbs on FIFO%d\n",
2454 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
2455 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
2456 spin_unlock_irqrestore(&mac_control
->fifos
[i
].tx_lock
, flags
);
2461 * stop_nic - To stop the nic
2462 * @nic ; device private variable.
2464 * This function does exactly the opposite of what the start_nic()
2465 * function does. This function is called to stop the device.
2470 static void stop_nic(struct s2io_nic
*nic
)
2472 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2473 register u64 val64
= 0;
2475 struct mac_info
*mac_control
;
2476 struct config_param
*config
;
2478 mac_control
= &nic
->mac_control
;
2479 config
= &nic
->config
;
2481 /* Disable all interrupts */
2482 en_dis_err_alarms(nic
, ENA_ALL_INTRS
, DISABLE_INTRS
);
2483 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
2484 interruptible
|= TX_PIC_INTR
;
2485 en_dis_able_nic_intrs(nic
, interruptible
, DISABLE_INTRS
);
2487 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2488 val64
= readq(&bar0
->adapter_control
);
2489 val64
&= ~(ADAPTER_CNTL_EN
);
2490 writeq(val64
, &bar0
->adapter_control
);
2494 * fill_rx_buffers - Allocates the Rx side skbs
2495 * @ring_info: per ring structure
2496 * @from_card_up: If this is true, we will map the buffer to get
2497 * the dma address for buf0 and buf1 to give it to the card.
2498 * Else we will sync the already mapped buffer to give it to the card.
2500 * The function allocates Rx side skbs and puts the physical
2501 * address of these buffers into the RxD buffer pointers, so that the NIC
2502 * can DMA the received frame into these locations.
2503 * The NIC supports 3 receive modes, viz
2505 * 2. three buffer and
2506 * 3. Five buffer modes.
2507 * Each mode defines how many fragments the received frame will be split
2508 * up into by the NIC. The frame is split into L3 header, L4 Header,
2509 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2510 * is split into 3 fragments. As of now only single buffer mode is
2513 * SUCCESS on success or an appropriate -ve value on failure.
2515 static int fill_rx_buffers(struct s2io_nic
*nic
, struct ring_info
*ring
,
2518 struct sk_buff
*skb
;
2520 int off
, size
, block_no
, block_no1
;
2525 struct RxD_t
*first_rxdp
= NULL
;
2526 u64 Buffer0_ptr
= 0, Buffer1_ptr
= 0;
2530 struct swStat
*stats
= &ring
->nic
->mac_control
.stats_info
->sw_stat
;
2532 alloc_cnt
= ring
->pkt_cnt
- ring
->rx_bufs_left
;
2534 block_no1
= ring
->rx_curr_get_info
.block_index
;
2535 while (alloc_tab
< alloc_cnt
) {
2536 block_no
= ring
->rx_curr_put_info
.block_index
;
2538 off
= ring
->rx_curr_put_info
.offset
;
2540 rxdp
= ring
->rx_blocks
[block_no
].rxds
[off
].virt_addr
;
2542 rxd_index
= off
+ 1;
2544 rxd_index
+= (block_no
* ring
->rxd_count
);
2546 if ((block_no
== block_no1
) &&
2547 (off
== ring
->rx_curr_get_info
.offset
) &&
2548 (rxdp
->Host_Control
)) {
2549 DBG_PRINT(INTR_DBG
, "%s: Get and Put",
2551 DBG_PRINT(INTR_DBG
, " info equated\n");
2554 if (off
&& (off
== ring
->rxd_count
)) {
2555 ring
->rx_curr_put_info
.block_index
++;
2556 if (ring
->rx_curr_put_info
.block_index
==
2558 ring
->rx_curr_put_info
.block_index
= 0;
2559 block_no
= ring
->rx_curr_put_info
.block_index
;
2561 ring
->rx_curr_put_info
.offset
= off
;
2562 rxdp
= ring
->rx_blocks
[block_no
].block_virt_addr
;
2563 DBG_PRINT(INTR_DBG
, "%s: Next block at: %p\n",
2564 ring
->dev
->name
, rxdp
);
2568 if ((rxdp
->Control_1
& RXD_OWN_XENA
) &&
2569 ((ring
->rxd_mode
== RXD_MODE_3B
) &&
2570 (rxdp
->Control_2
& s2BIT(0)))) {
2571 ring
->rx_curr_put_info
.offset
= off
;
2574 /* calculate size of skb based on ring mode */
2575 size
= ring
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
2576 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
2577 if (ring
->rxd_mode
== RXD_MODE_1
)
2578 size
+= NET_IP_ALIGN
;
2580 size
= ring
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2583 skb
= dev_alloc_skb(size
);
2585 DBG_PRINT(INFO_DBG
, "%s: Out of ", ring
->dev
->name
);
2586 DBG_PRINT(INFO_DBG
, "memory to allocate SKBs\n");
2589 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2591 stats
->mem_alloc_fail_cnt
++;
2595 stats
->mem_allocated
+= skb
->truesize
;
2597 if (ring
->rxd_mode
== RXD_MODE_1
) {
2598 /* 1 buffer mode - normal operation mode */
2599 rxdp1
= (struct RxD1
*)rxdp
;
2600 memset(rxdp
, 0, sizeof(struct RxD1
));
2601 skb_reserve(skb
, NET_IP_ALIGN
);
2602 rxdp1
->Buffer0_ptr
= pci_map_single
2603 (ring
->pdev
, skb
->data
, size
- NET_IP_ALIGN
,
2604 PCI_DMA_FROMDEVICE
);
2605 if (pci_dma_mapping_error(nic
->pdev
,
2606 rxdp1
->Buffer0_ptr
))
2607 goto pci_map_failed
;
2610 SET_BUFFER0_SIZE_1(size
- NET_IP_ALIGN
);
2611 rxdp
->Host_Control
= (unsigned long) (skb
);
2612 } else if (ring
->rxd_mode
== RXD_MODE_3B
) {
2615 * 2 buffer mode provides 128
2616 * byte aligned receive buffers.
2619 rxdp3
= (struct RxD3
*)rxdp
;
2620 /* save buffer pointers to avoid frequent dma mapping */
2621 Buffer0_ptr
= rxdp3
->Buffer0_ptr
;
2622 Buffer1_ptr
= rxdp3
->Buffer1_ptr
;
2623 memset(rxdp
, 0, sizeof(struct RxD3
));
2624 /* restore the buffer pointers for dma sync*/
2625 rxdp3
->Buffer0_ptr
= Buffer0_ptr
;
2626 rxdp3
->Buffer1_ptr
= Buffer1_ptr
;
2628 ba
= &ring
->ba
[block_no
][off
];
2629 skb_reserve(skb
, BUF0_LEN
);
2630 tmp
= (u64
)(unsigned long) skb
->data
;
2633 skb
->data
= (void *) (unsigned long)tmp
;
2634 skb_reset_tail_pointer(skb
);
2637 rxdp3
->Buffer0_ptr
=
2638 pci_map_single(ring
->pdev
, ba
->ba_0
,
2639 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2640 if (pci_dma_mapping_error(nic
->pdev
,
2641 rxdp3
->Buffer0_ptr
))
2642 goto pci_map_failed
;
2644 pci_dma_sync_single_for_device(ring
->pdev
,
2645 (dma_addr_t
) rxdp3
->Buffer0_ptr
,
2646 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2648 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
2649 if (ring
->rxd_mode
== RXD_MODE_3B
) {
2650 /* Two buffer mode */
2653 * Buffer2 will have L3/L4 header plus
2656 rxdp3
->Buffer2_ptr
= pci_map_single
2657 (ring
->pdev
, skb
->data
, ring
->mtu
+ 4,
2658 PCI_DMA_FROMDEVICE
);
2660 if (pci_dma_mapping_error(nic
->pdev
,
2661 rxdp3
->Buffer2_ptr
))
2662 goto pci_map_failed
;
2665 rxdp3
->Buffer1_ptr
=
2666 pci_map_single(ring
->pdev
,
2668 PCI_DMA_FROMDEVICE
);
2670 if (pci_dma_mapping_error(nic
->pdev
,
2671 rxdp3
->Buffer1_ptr
)) {
2674 (dma_addr_t
)(unsigned long)
2677 PCI_DMA_FROMDEVICE
);
2678 goto pci_map_failed
;
2681 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
2682 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3
2685 rxdp
->Control_2
|= s2BIT(0);
2686 rxdp
->Host_Control
= (unsigned long) (skb
);
2688 if (alloc_tab
& ((1 << rxsync_frequency
) - 1))
2689 rxdp
->Control_1
|= RXD_OWN_XENA
;
2691 if (off
== (ring
->rxd_count
+ 1))
2693 ring
->rx_curr_put_info
.offset
= off
;
2695 rxdp
->Control_2
|= SET_RXD_MARKER
;
2696 if (!(alloc_tab
& ((1 << rxsync_frequency
) - 1))) {
2699 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2703 ring
->rx_bufs_left
+= 1;
2708 /* Transfer ownership of first descriptor to adapter just before
2709 * exiting. Before that, use memory barrier so that ownership
2710 * and other fields are seen by adapter correctly.
2714 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2719 stats
->pci_map_fail_cnt
++;
2720 stats
->mem_freed
+= skb
->truesize
;
2721 dev_kfree_skb_irq(skb
);
2725 static void free_rxd_blk(struct s2io_nic
*sp
, int ring_no
, int blk
)
2727 struct net_device
*dev
= sp
->dev
;
2729 struct sk_buff
*skb
;
2731 struct mac_info
*mac_control
;
2736 mac_control
= &sp
->mac_control
;
2737 for (j
= 0 ; j
< rxd_count
[sp
->rxd_mode
]; j
++) {
2738 rxdp
= mac_control
->rings
[ring_no
].
2739 rx_blocks
[blk
].rxds
[j
].virt_addr
;
2740 skb
= (struct sk_buff
*)
2741 ((unsigned long) rxdp
->Host_Control
);
2745 if (sp
->rxd_mode
== RXD_MODE_1
) {
2746 rxdp1
= (struct RxD1
*)rxdp
;
2747 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2750 HEADER_ETHERNET_II_802_3_SIZE
2751 + HEADER_802_2_SIZE
+
2753 PCI_DMA_FROMDEVICE
);
2754 memset(rxdp
, 0, sizeof(struct RxD1
));
2755 } else if(sp
->rxd_mode
== RXD_MODE_3B
) {
2756 rxdp3
= (struct RxD3
*)rxdp
;
2757 ba
= &mac_control
->rings
[ring_no
].
2759 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2762 PCI_DMA_FROMDEVICE
);
2763 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2766 PCI_DMA_FROMDEVICE
);
2767 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2770 PCI_DMA_FROMDEVICE
);
2771 memset(rxdp
, 0, sizeof(struct RxD3
));
2773 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
2775 mac_control
->rings
[ring_no
].rx_bufs_left
-= 1;
2780 * free_rx_buffers - Frees all Rx buffers
2781 * @sp: device private variable.
2783 * This function will free all Rx buffers allocated by host.
2788 static void free_rx_buffers(struct s2io_nic
*sp
)
2790 struct net_device
*dev
= sp
->dev
;
2791 int i
, blk
= 0, buf_cnt
= 0;
2792 struct mac_info
*mac_control
;
2793 struct config_param
*config
;
2795 mac_control
= &sp
->mac_control
;
2796 config
= &sp
->config
;
2798 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2799 for (blk
= 0; blk
< rx_ring_sz
[i
]; blk
++)
2800 free_rxd_blk(sp
,i
,blk
);
2802 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
2803 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
2804 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
2805 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
2806 mac_control
->rings
[i
].rx_bufs_left
= 0;
2807 DBG_PRINT(INIT_DBG
, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2808 dev
->name
, buf_cnt
, i
);
2812 static int s2io_chk_rx_buffers(struct s2io_nic
*nic
, struct ring_info
*ring
)
2814 if (fill_rx_buffers(nic
, ring
, 0) == -ENOMEM
) {
2815 DBG_PRINT(INFO_DBG
, "%s:Out of memory", ring
->dev
->name
);
2816 DBG_PRINT(INFO_DBG
, " in Rx Intr!!\n");
2822 * s2io_poll - Rx interrupt handler for NAPI support
2823 * @napi : pointer to the napi structure.
2824 * @budget : The number of packets that were budgeted to be processed
2825 * during one pass through the 'Poll" function.
2827 * Comes into picture only if NAPI support has been incorporated. It does
2828 * the same thing that rx_intr_handler does, but not in a interrupt context
2829 * also It will process only a given number of packets.
2831 * 0 on success and 1 if there are No Rx packets to be processed.
2834 static int s2io_poll_msix(struct napi_struct
*napi
, int budget
)
2836 struct ring_info
*ring
= container_of(napi
, struct ring_info
, napi
);
2837 struct net_device
*dev
= ring
->dev
;
2838 struct config_param
*config
;
2839 struct mac_info
*mac_control
;
2840 int pkts_processed
= 0;
2841 u8 __iomem
*addr
= NULL
;
2843 struct s2io_nic
*nic
= dev
->priv
;
2844 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2845 int budget_org
= budget
;
2847 config
= &nic
->config
;
2848 mac_control
= &nic
->mac_control
;
2850 if (unlikely(!is_s2io_card_up(nic
)))
2853 pkts_processed
= rx_intr_handler(ring
, budget
);
2854 s2io_chk_rx_buffers(nic
, ring
);
2856 if (pkts_processed
< budget_org
) {
2857 netif_rx_complete(dev
, napi
);
2858 /*Re Enable MSI-Rx Vector*/
2859 addr
= (u8 __iomem
*)&bar0
->xmsi_mask_reg
;
2860 addr
+= 7 - ring
->ring_no
;
2861 val8
= (ring
->ring_no
== 0) ? 0x3f : 0xbf;
2865 return pkts_processed
;
2867 static int s2io_poll_inta(struct napi_struct
*napi
, int budget
)
2869 struct s2io_nic
*nic
= container_of(napi
, struct s2io_nic
, napi
);
2870 struct ring_info
*ring
;
2871 struct net_device
*dev
= nic
->dev
;
2872 struct config_param
*config
;
2873 struct mac_info
*mac_control
;
2874 int pkts_processed
= 0;
2875 int ring_pkts_processed
, i
;
2876 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2877 int budget_org
= budget
;
2879 config
= &nic
->config
;
2880 mac_control
= &nic
->mac_control
;
2882 if (unlikely(!is_s2io_card_up(nic
)))
2885 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2886 ring
= &mac_control
->rings
[i
];
2887 ring_pkts_processed
= rx_intr_handler(ring
, budget
);
2888 s2io_chk_rx_buffers(nic
, ring
);
2889 pkts_processed
+= ring_pkts_processed
;
2890 budget
-= ring_pkts_processed
;
2894 if (pkts_processed
< budget_org
) {
2895 netif_rx_complete(dev
, napi
);
2896 /* Re enable the Rx interrupts for the ring */
2897 writeq(0, &bar0
->rx_traffic_mask
);
2898 readl(&bar0
->rx_traffic_mask
);
2900 return pkts_processed
;
2903 #ifdef CONFIG_NET_POLL_CONTROLLER
2905 * s2io_netpoll - netpoll event handler entry point
2906 * @dev : pointer to the device structure.
2908 * This function will be called by upper layer to check for events on the
2909 * interface in situations where interrupts are disabled. It is used for
2910 * specific in-kernel networking tasks, such as remote consoles and kernel
2911 * debugging over the network (example netdump in RedHat).
2913 static void s2io_netpoll(struct net_device
*dev
)
2915 struct s2io_nic
*nic
= dev
->priv
;
2916 struct mac_info
*mac_control
;
2917 struct config_param
*config
;
2918 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2919 u64 val64
= 0xFFFFFFFFFFFFFFFFULL
;
2922 if (pci_channel_offline(nic
->pdev
))
2925 disable_irq(dev
->irq
);
2927 mac_control
= &nic
->mac_control
;
2928 config
= &nic
->config
;
2930 writeq(val64
, &bar0
->rx_traffic_int
);
2931 writeq(val64
, &bar0
->tx_traffic_int
);
2933 /* we need to free up the transmitted skbufs or else netpoll will
2934 * run out of skbs and will fail and eventually netpoll application such
2935 * as netdump will fail.
2937 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
2938 tx_intr_handler(&mac_control
->fifos
[i
]);
2940 /* check for received packet and indicate up to network */
2941 for (i
= 0; i
< config
->rx_ring_num
; i
++)
2942 rx_intr_handler(&mac_control
->rings
[i
], 0);
2944 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2945 if (fill_rx_buffers(nic
, &mac_control
->rings
[i
], 0) ==
2947 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2948 DBG_PRINT(INFO_DBG
, " in Rx Netpoll!!\n");
2952 enable_irq(dev
->irq
);
2958 * rx_intr_handler - Rx interrupt handler
2959 * @ring_info: per ring structure.
2960 * @budget: budget for napi processing.
2962 * If the interrupt is because of a received frame or if the
2963 * receive ring contains fresh as yet un-processed frames,this function is
2964 * called. It picks out the RxD at which place the last Rx processing had
2965 * stopped and sends the skb to the OSM's Rx handler and then increments
2968 * No. of napi packets processed.
2970 static int rx_intr_handler(struct ring_info
*ring_data
, int budget
)
2972 int get_block
, put_block
;
2973 struct rx_curr_get_info get_info
, put_info
;
2975 struct sk_buff
*skb
;
2976 int pkt_cnt
= 0, napi_pkts
= 0;
2981 get_info
= ring_data
->rx_curr_get_info
;
2982 get_block
= get_info
.block_index
;
2983 memcpy(&put_info
, &ring_data
->rx_curr_put_info
, sizeof(put_info
));
2984 put_block
= put_info
.block_index
;
2985 rxdp
= ring_data
->rx_blocks
[get_block
].rxds
[get_info
.offset
].virt_addr
;
2987 while (RXD_IS_UP2DT(rxdp
)) {
2989 * If your are next to put index then it's
2990 * FIFO full condition
2992 if ((get_block
== put_block
) &&
2993 (get_info
.offset
+ 1) == put_info
.offset
) {
2994 DBG_PRINT(INTR_DBG
, "%s: Ring Full\n",
2995 ring_data
->dev
->name
);
2998 skb
= (struct sk_buff
*) ((unsigned long)rxdp
->Host_Control
);
3000 DBG_PRINT(ERR_DBG
, "%s: The skb is ",
3001 ring_data
->dev
->name
);
3002 DBG_PRINT(ERR_DBG
, "Null in Rx Intr\n");
3005 if (ring_data
->rxd_mode
== RXD_MODE_1
) {
3006 rxdp1
= (struct RxD1
*)rxdp
;
3007 pci_unmap_single(ring_data
->pdev
, (dma_addr_t
)
3010 HEADER_ETHERNET_II_802_3_SIZE
+
3013 PCI_DMA_FROMDEVICE
);
3014 } else if (ring_data
->rxd_mode
== RXD_MODE_3B
) {
3015 rxdp3
= (struct RxD3
*)rxdp
;
3016 pci_dma_sync_single_for_cpu(ring_data
->pdev
, (dma_addr_t
)
3018 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
3019 pci_unmap_single(ring_data
->pdev
, (dma_addr_t
)
3022 PCI_DMA_FROMDEVICE
);
3024 prefetch(skb
->data
);
3025 rx_osm_handler(ring_data
, rxdp
);
3027 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
3028 rxdp
= ring_data
->rx_blocks
[get_block
].
3029 rxds
[get_info
.offset
].virt_addr
;
3030 if (get_info
.offset
== rxd_count
[ring_data
->rxd_mode
]) {
3031 get_info
.offset
= 0;
3032 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
3034 if (get_block
== ring_data
->block_count
)
3036 ring_data
->rx_curr_get_info
.block_index
= get_block
;
3037 rxdp
= ring_data
->rx_blocks
[get_block
].block_virt_addr
;
3040 if (ring_data
->nic
->config
.napi
) {
3047 if ((indicate_max_pkts
) && (pkt_cnt
> indicate_max_pkts
))
3050 if (ring_data
->lro
) {
3051 /* Clear all LRO sessions before exiting */
3052 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
3053 struct lro
*lro
= &ring_data
->lro0_n
[i
];
3055 update_L3L4_header(ring_data
->nic
, lro
);
3056 queue_rx_frame(lro
->parent
, lro
->vlan_tag
);
3057 clear_lro_session(lro
);
3065 * tx_intr_handler - Transmit interrupt handler
3066 * @nic : device private variable
3068 * If an interrupt was raised to indicate DMA complete of the
3069 * Tx packet, this function is called. It identifies the last TxD
3070 * whose buffer was freed and frees all skbs whose data have already
3071 * DMA'ed into the NICs internal memory.
3076 static void tx_intr_handler(struct fifo_info
*fifo_data
)
3078 struct s2io_nic
*nic
= fifo_data
->nic
;
3079 struct tx_curr_get_info get_info
, put_info
;
3080 struct sk_buff
*skb
= NULL
;
3083 unsigned long flags
= 0;
3086 if (!spin_trylock_irqsave(&fifo_data
->tx_lock
, flags
))
3089 get_info
= fifo_data
->tx_curr_get_info
;
3090 memcpy(&put_info
, &fifo_data
->tx_curr_put_info
, sizeof(put_info
));
3091 txdlp
= (struct TxD
*) fifo_data
->list_info
[get_info
.offset
].
3093 while ((!(txdlp
->Control_1
& TXD_LIST_OWN_XENA
)) &&
3094 (get_info
.offset
!= put_info
.offset
) &&
3095 (txdlp
->Host_Control
)) {
3096 /* Check for TxD errors */
3097 if (txdlp
->Control_1
& TXD_T_CODE
) {
3098 unsigned long long err
;
3099 err
= txdlp
->Control_1
& TXD_T_CODE
;
3101 nic
->mac_control
.stats_info
->sw_stat
.
3105 /* update t_code statistics */
3106 err_mask
= err
>> 48;
3109 nic
->mac_control
.stats_info
->sw_stat
.
3114 nic
->mac_control
.stats_info
->sw_stat
.
3115 tx_desc_abort_cnt
++;
3119 nic
->mac_control
.stats_info
->sw_stat
.
3120 tx_parity_err_cnt
++;
3124 nic
->mac_control
.stats_info
->sw_stat
.
3129 nic
->mac_control
.stats_info
->sw_stat
.
3130 tx_list_proc_err_cnt
++;
3135 skb
= s2io_txdl_getskb(fifo_data
, txdlp
, get_info
.offset
);
3137 spin_unlock_irqrestore(&fifo_data
->tx_lock
, flags
);
3138 DBG_PRINT(ERR_DBG
, "%s: Null skb ",
3140 DBG_PRINT(ERR_DBG
, "in Tx Free Intr\n");
3145 /* Updating the statistics block */
3146 nic
->dev
->stats
.tx_bytes
+= skb
->len
;
3147 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
3148 dev_kfree_skb_irq(skb
);
3151 if (get_info
.offset
== get_info
.fifo_len
+ 1)
3152 get_info
.offset
= 0;
3153 txdlp
= (struct TxD
*) fifo_data
->list_info
3154 [get_info
.offset
].list_virt_addr
;
3155 fifo_data
->tx_curr_get_info
.offset
=
3159 s2io_wake_tx_queue(fifo_data
, pkt_cnt
, nic
->config
.multiq
);
3161 spin_unlock_irqrestore(&fifo_data
->tx_lock
, flags
);
3165 * s2io_mdio_write - Function to write in to MDIO registers
3166 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3167 * @addr : address value
3168 * @value : data value
3169 * @dev : pointer to net_device structure
3171 * This function is used to write values to the MDIO registers
3174 static void s2io_mdio_write(u32 mmd_type
, u64 addr
, u16 value
, struct net_device
*dev
)
3177 struct s2io_nic
*sp
= dev
->priv
;
3178 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3180 //address transaction
3181 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3182 | MDIO_MMD_DEV_ADDR(mmd_type
)
3183 | MDIO_MMS_PRT_ADDR(0x0);
3184 writeq(val64
, &bar0
->mdio_control
);
3185 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3186 writeq(val64
, &bar0
->mdio_control
);
3191 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3192 | MDIO_MMD_DEV_ADDR(mmd_type
)
3193 | MDIO_MMS_PRT_ADDR(0x0)
3194 | MDIO_MDIO_DATA(value
)
3195 | MDIO_OP(MDIO_OP_WRITE_TRANS
);
3196 writeq(val64
, &bar0
->mdio_control
);
3197 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3198 writeq(val64
, &bar0
->mdio_control
);
3202 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3203 | MDIO_MMD_DEV_ADDR(mmd_type
)
3204 | MDIO_MMS_PRT_ADDR(0x0)
3205 | MDIO_OP(MDIO_OP_READ_TRANS
);
3206 writeq(val64
, &bar0
->mdio_control
);
3207 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3208 writeq(val64
, &bar0
->mdio_control
);
3214 * s2io_mdio_read - Function to write in to MDIO registers
3215 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3216 * @addr : address value
3217 * @dev : pointer to net_device structure
3219 * This function is used to read values to the MDIO registers
3222 static u64
s2io_mdio_read(u32 mmd_type
, u64 addr
, struct net_device
*dev
)
3226 struct s2io_nic
*sp
= dev
->priv
;
3227 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3229 /* address transaction */
3230 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3231 | MDIO_MMD_DEV_ADDR(mmd_type
)
3232 | MDIO_MMS_PRT_ADDR(0x0);
3233 writeq(val64
, &bar0
->mdio_control
);
3234 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3235 writeq(val64
, &bar0
->mdio_control
);
3238 /* Data transaction */
3240 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3241 | MDIO_MMD_DEV_ADDR(mmd_type
)
3242 | MDIO_MMS_PRT_ADDR(0x0)
3243 | MDIO_OP(MDIO_OP_READ_TRANS
);
3244 writeq(val64
, &bar0
->mdio_control
);
3245 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3246 writeq(val64
, &bar0
->mdio_control
);
3249 /* Read the value from regs */
3250 rval64
= readq(&bar0
->mdio_control
);
3251 rval64
= rval64
& 0xFFFF0000;
3252 rval64
= rval64
>> 16;
3256 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3257 * @counter : couter value to be updated
3258 * @flag : flag to indicate the status
3259 * @type : counter type
3261 * This function is to check the status of the xpak counters value
3265 static void s2io_chk_xpak_counter(u64
*counter
, u64
* regs_stat
, u32 index
, u16 flag
, u16 type
)
3270 for(i
= 0; i
<index
; i
++)
3275 *counter
= *counter
+ 1;
3276 val64
= *regs_stat
& mask
;
3277 val64
= val64
>> (index
* 0x2);
3284 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3285 "service. Excessive temperatures may "
3286 "result in premature transceiver "
3290 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3291 "service Excessive bias currents may "
3292 "indicate imminent laser diode "
3296 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3297 "service Excessive laser output "
3298 "power may saturate far-end "
3302 DBG_PRINT(ERR_DBG
, "Incorrect XPAK Alarm "
3307 val64
= val64
<< (index
* 0x2);
3308 *regs_stat
= (*regs_stat
& (~mask
)) | (val64
);
3311 *regs_stat
= *regs_stat
& (~mask
);
3316 * s2io_updt_xpak_counter - Function to update the xpak counters
3317 * @dev : pointer to net_device struct
3319 * This function is to upate the status of the xpak counters value
3322 static void s2io_updt_xpak_counter(struct net_device
*dev
)
3330 struct s2io_nic
*sp
= dev
->priv
;
3331 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
3333 /* Check the communication with the MDIO slave */
3336 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3337 if((val64
== 0xFFFF) || (val64
== 0x0000))
3339 DBG_PRINT(ERR_DBG
, "ERR: MDIO slave access failed - "
3340 "Returned %llx\n", (unsigned long long)val64
);
3344 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3347 DBG_PRINT(ERR_DBG
, "Incorrect value at PMA address 0x0000 - ");
3348 DBG_PRINT(ERR_DBG
, "Returned: %llx- Expected: 0x2040\n",
3349 (unsigned long long)val64
);
3353 /* Loading the DOM register to MDIO register */
3355 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR
, addr
, val16
, dev
);
3356 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3358 /* Reading the Alarm flags */
3361 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3363 flag
= CHECKBIT(val64
, 0x7);
3365 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_transceiver_temp_high
,
3366 &stat_info
->xpak_stat
.xpak_regs_stat
,
3369 if(CHECKBIT(val64
, 0x6))
3370 stat_info
->xpak_stat
.alarm_transceiver_temp_low
++;
3372 flag
= CHECKBIT(val64
, 0x3);
3374 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_bias_current_high
,
3375 &stat_info
->xpak_stat
.xpak_regs_stat
,
3378 if(CHECKBIT(val64
, 0x2))
3379 stat_info
->xpak_stat
.alarm_laser_bias_current_low
++;
3381 flag
= CHECKBIT(val64
, 0x1);
3383 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_output_power_high
,
3384 &stat_info
->xpak_stat
.xpak_regs_stat
,
3387 if(CHECKBIT(val64
, 0x0))
3388 stat_info
->xpak_stat
.alarm_laser_output_power_low
++;
3390 /* Reading the Warning flags */
3393 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3395 if(CHECKBIT(val64
, 0x7))
3396 stat_info
->xpak_stat
.warn_transceiver_temp_high
++;
3398 if(CHECKBIT(val64
, 0x6))
3399 stat_info
->xpak_stat
.warn_transceiver_temp_low
++;
3401 if(CHECKBIT(val64
, 0x3))
3402 stat_info
->xpak_stat
.warn_laser_bias_current_high
++;
3404 if(CHECKBIT(val64
, 0x2))
3405 stat_info
->xpak_stat
.warn_laser_bias_current_low
++;
3407 if(CHECKBIT(val64
, 0x1))
3408 stat_info
->xpak_stat
.warn_laser_output_power_high
++;
3410 if(CHECKBIT(val64
, 0x0))
3411 stat_info
->xpak_stat
.warn_laser_output_power_low
++;
3415 * wait_for_cmd_complete - waits for a command to complete.
3416 * @sp : private member of the device structure, which is a pointer to the
3417 * s2io_nic structure.
3418 * Description: Function that waits for a command to Write into RMAC
3419 * ADDR DATA registers to be completed and returns either success or
3420 * error depending on whether the command was complete or not.
3422 * SUCCESS on success and FAILURE on failure.
3425 static int wait_for_cmd_complete(void __iomem
*addr
, u64 busy_bit
,
3428 int ret
= FAILURE
, cnt
= 0, delay
= 1;
3431 if ((bit_state
!= S2IO_BIT_RESET
) && (bit_state
!= S2IO_BIT_SET
))
3435 val64
= readq(addr
);
3436 if (bit_state
== S2IO_BIT_RESET
) {
3437 if (!(val64
& busy_bit
)) {
3442 if (!(val64
& busy_bit
)) {
3459 * check_pci_device_id - Checks if the device id is supported
3461 * Description: Function to check if the pci device id is supported by driver.
3462 * Return value: Actual device id if supported else PCI_ANY_ID
3464 static u16
check_pci_device_id(u16 id
)
3467 case PCI_DEVICE_ID_HERC_WIN
:
3468 case PCI_DEVICE_ID_HERC_UNI
:
3469 return XFRAME_II_DEVICE
;
3470 case PCI_DEVICE_ID_S2IO_UNI
:
3471 case PCI_DEVICE_ID_S2IO_WIN
:
3472 return XFRAME_I_DEVICE
;
3479 * s2io_reset - Resets the card.
3480 * @sp : private member of the device structure.
3481 * Description: Function to Reset the card. This function then also
3482 * restores the previously saved PCI configuration space registers as
3483 * the card reset also resets the configuration space.
3488 static void s2io_reset(struct s2io_nic
* sp
)
3490 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3495 unsigned long long up_cnt
, down_cnt
, up_time
, down_time
, reset_cnt
;
3496 unsigned long long mem_alloc_cnt
, mem_free_cnt
, watchdog_cnt
;
3498 DBG_PRINT(INIT_DBG
,"%s - Resetting XFrame card %s\n",
3499 __FUNCTION__
, sp
->dev
->name
);
3501 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3502 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, &(pci_cmd
));
3504 val64
= SW_RESET_ALL
;
3505 writeq(val64
, &bar0
->sw_reset
);
3506 if (strstr(sp
->product_name
, "CX4")) {
3510 for (i
= 0; i
< S2IO_MAX_PCI_CONFIG_SPACE_REINIT
; i
++) {
3512 /* Restore the PCI state saved during initialization. */
3513 pci_restore_state(sp
->pdev
);
3514 pci_read_config_word(sp
->pdev
, 0x2, &val16
);
3515 if (check_pci_device_id(val16
) != (u16
)PCI_ANY_ID
)
3520 if (check_pci_device_id(val16
) == (u16
)PCI_ANY_ID
) {
3521 DBG_PRINT(ERR_DBG
,"%s SW_Reset failed!\n", __FUNCTION__
);
3524 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, pci_cmd
);
3528 /* Set swapper to enable I/O register access */
3529 s2io_set_swapper(sp
);
3531 /* restore mac_addr entries */
3532 do_s2io_restore_unicast_mc(sp
);
3534 /* Restore the MSIX table entries from local variables */
3535 restore_xmsi_data(sp
);
3537 /* Clear certain PCI/PCI-X fields after reset */
3538 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3539 /* Clear "detected parity error" bit */
3540 pci_write_config_word(sp
->pdev
, PCI_STATUS
, 0x8000);
3542 /* Clearing PCIX Ecc status register */
3543 pci_write_config_dword(sp
->pdev
, 0x68, 0x7C);
3545 /* Clearing PCI_STATUS error reflected here */
3546 writeq(s2BIT(62), &bar0
->txpic_int_reg
);
3549 /* Reset device statistics maintained by OS */
3550 memset(&sp
->stats
, 0, sizeof (struct net_device_stats
));
3552 up_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
;
3553 down_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
;
3554 up_time
= sp
->mac_control
.stats_info
->sw_stat
.link_up_time
;
3555 down_time
= sp
->mac_control
.stats_info
->sw_stat
.link_down_time
;
3556 reset_cnt
= sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
;
3557 mem_alloc_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
;
3558 mem_free_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_freed
;
3559 watchdog_cnt
= sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
;
3560 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3561 memset(sp
->mac_control
.stats_info
, 0, sizeof(struct stat_block
));
3562 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3563 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
= up_cnt
;
3564 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
= down_cnt
;
3565 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
= up_time
;
3566 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
= down_time
;
3567 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
= reset_cnt
;
3568 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
= mem_alloc_cnt
;
3569 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
= mem_free_cnt
;
3570 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
= watchdog_cnt
;
3572 /* SXE-002: Configure link and activity LED to turn it off */
3573 subid
= sp
->pdev
->subsystem_device
;
3574 if (((subid
& 0xFF) >= 0x07) &&
3575 (sp
->device_type
== XFRAME_I_DEVICE
)) {
3576 val64
= readq(&bar0
->gpio_control
);
3577 val64
|= 0x0000800000000000ULL
;
3578 writeq(val64
, &bar0
->gpio_control
);
3579 val64
= 0x0411040400000000ULL
;
3580 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
3584 * Clear spurious ECC interrupts that would have occured on
3585 * XFRAME II cards after reset.
3587 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3588 val64
= readq(&bar0
->pcc_err_reg
);
3589 writeq(val64
, &bar0
->pcc_err_reg
);
3592 sp
->device_enabled_once
= FALSE
;
3596 * s2io_set_swapper - to set the swapper controle on the card
3597 * @sp : private member of the device structure,
3598 * pointer to the s2io_nic structure.
3599 * Description: Function to set the swapper control on the card
3600 * correctly depending on the 'endianness' of the system.
3602 * SUCCESS on success and FAILURE on failure.
3605 static int s2io_set_swapper(struct s2io_nic
* sp
)
3607 struct net_device
*dev
= sp
->dev
;
3608 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3609 u64 val64
, valt
, valr
;
3612 * Set proper endian settings and verify the same by reading
3613 * the PIF Feed-back register.
3616 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3617 if (val64
!= 0x0123456789ABCDEFULL
) {
3619 u64 value
[] = { 0xC30000C3C30000C3ULL
, /* FE=1, SE=1 */
3620 0x8100008181000081ULL
, /* FE=1, SE=0 */
3621 0x4200004242000042ULL
, /* FE=0, SE=1 */
3622 0}; /* FE=0, SE=0 */
3625 writeq(value
[i
], &bar0
->swapper_ctrl
);
3626 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3627 if (val64
== 0x0123456789ABCDEFULL
)
3632 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3634 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3635 (unsigned long long) val64
);
3640 valr
= readq(&bar0
->swapper_ctrl
);
3643 valt
= 0x0123456789ABCDEFULL
;
3644 writeq(valt
, &bar0
->xmsi_address
);
3645 val64
= readq(&bar0
->xmsi_address
);
3649 u64 value
[] = { 0x00C3C30000C3C300ULL
, /* FE=1, SE=1 */
3650 0x0081810000818100ULL
, /* FE=1, SE=0 */
3651 0x0042420000424200ULL
, /* FE=0, SE=1 */
3652 0}; /* FE=0, SE=0 */
3655 writeq((value
[i
] | valr
), &bar0
->swapper_ctrl
);
3656 writeq(valt
, &bar0
->xmsi_address
);
3657 val64
= readq(&bar0
->xmsi_address
);
3663 unsigned long long x
= val64
;
3664 DBG_PRINT(ERR_DBG
, "Write failed, Xmsi_addr ");
3665 DBG_PRINT(ERR_DBG
, "reads:0x%llx\n", x
);
3669 val64
= readq(&bar0
->swapper_ctrl
);
3670 val64
&= 0xFFFF000000000000ULL
;
3674 * The device by default set to a big endian format, so a
3675 * big endian driver need not set anything.
3677 val64
|= (SWAPPER_CTRL_TXP_FE
|
3678 SWAPPER_CTRL_TXP_SE
|
3679 SWAPPER_CTRL_TXD_R_FE
|
3680 SWAPPER_CTRL_TXD_W_FE
|
3681 SWAPPER_CTRL_TXF_R_FE
|
3682 SWAPPER_CTRL_RXD_R_FE
|
3683 SWAPPER_CTRL_RXD_W_FE
|
3684 SWAPPER_CTRL_RXF_W_FE
|
3685 SWAPPER_CTRL_XMSI_FE
|
3686 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3687 if (sp
->config
.intr_type
== INTA
)
3688 val64
|= SWAPPER_CTRL_XMSI_SE
;
3689 writeq(val64
, &bar0
->swapper_ctrl
);
3692 * Initially we enable all bits to make it accessible by the
3693 * driver, then we selectively enable only those bits that
3696 val64
|= (SWAPPER_CTRL_TXP_FE
|
3697 SWAPPER_CTRL_TXP_SE
|
3698 SWAPPER_CTRL_TXD_R_FE
|
3699 SWAPPER_CTRL_TXD_R_SE
|
3700 SWAPPER_CTRL_TXD_W_FE
|
3701 SWAPPER_CTRL_TXD_W_SE
|
3702 SWAPPER_CTRL_TXF_R_FE
|
3703 SWAPPER_CTRL_RXD_R_FE
|
3704 SWAPPER_CTRL_RXD_R_SE
|
3705 SWAPPER_CTRL_RXD_W_FE
|
3706 SWAPPER_CTRL_RXD_W_SE
|
3707 SWAPPER_CTRL_RXF_W_FE
|
3708 SWAPPER_CTRL_XMSI_FE
|
3709 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3710 if (sp
->config
.intr_type
== INTA
)
3711 val64
|= SWAPPER_CTRL_XMSI_SE
;
3712 writeq(val64
, &bar0
->swapper_ctrl
);
3714 val64
= readq(&bar0
->swapper_ctrl
);
3717 * Verifying if endian settings are accurate by reading a
3718 * feedback register.
3720 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3721 if (val64
!= 0x0123456789ABCDEFULL
) {
3722 /* Endian settings are incorrect, calls for another dekko. */
3723 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3725 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3726 (unsigned long long) val64
);
3733 static int wait_for_msix_trans(struct s2io_nic
*nic
, int i
)
3735 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3737 int ret
= 0, cnt
= 0;
3740 val64
= readq(&bar0
->xmsi_access
);
3741 if (!(val64
& s2BIT(15)))
3747 DBG_PRINT(ERR_DBG
, "XMSI # %d Access failed\n", i
);
3754 static void restore_xmsi_data(struct s2io_nic
*nic
)
3756 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3761 if (nic
->device_type
== XFRAME_I_DEVICE
)
3764 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3765 msix_index
= (i
) ? ((i
-1) * 8 + 1): 0;
3766 writeq(nic
->msix_info
[i
].addr
, &bar0
->xmsi_address
);
3767 writeq(nic
->msix_info
[i
].data
, &bar0
->xmsi_data
);
3768 val64
= (s2BIT(7) | s2BIT(15) | vBIT(msix_index
, 26, 6));
3769 writeq(val64
, &bar0
->xmsi_access
);
3770 if (wait_for_msix_trans(nic
, msix_index
)) {
3771 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3777 static void store_xmsi_data(struct s2io_nic
*nic
)
3779 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3780 u64 val64
, addr
, data
;
3783 if (nic
->device_type
== XFRAME_I_DEVICE
)
3786 /* Store and display */
3787 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3788 msix_index
= (i
) ? ((i
-1) * 8 + 1): 0;
3789 val64
= (s2BIT(15) | vBIT(msix_index
, 26, 6));
3790 writeq(val64
, &bar0
->xmsi_access
);
3791 if (wait_for_msix_trans(nic
, msix_index
)) {
3792 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3795 addr
= readq(&bar0
->xmsi_address
);
3796 data
= readq(&bar0
->xmsi_data
);
3798 nic
->msix_info
[i
].addr
= addr
;
3799 nic
->msix_info
[i
].data
= data
;
3804 static int s2io_enable_msi_x(struct s2io_nic
*nic
)
3806 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3808 u16 msi_control
; /* Temp variable */
3809 int ret
, i
, j
, msix_indx
= 1;
3811 nic
->entries
= kmalloc(nic
->num_entries
* sizeof(struct msix_entry
),
3813 if (!nic
->entries
) {
3814 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n", \
3816 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3819 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3820 += (nic
->num_entries
* sizeof(struct msix_entry
));
3822 memset(nic
->entries
, 0, nic
->num_entries
* sizeof(struct msix_entry
));
3825 kmalloc(nic
->num_entries
* sizeof(struct s2io_msix_entry
),
3827 if (!nic
->s2io_entries
) {
3828 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n",
3830 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3831 kfree(nic
->entries
);
3832 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3833 += (nic
->num_entries
* sizeof(struct msix_entry
));
3836 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3837 += (nic
->num_entries
* sizeof(struct s2io_msix_entry
));
3838 memset(nic
->s2io_entries
, 0,
3839 nic
->num_entries
* sizeof(struct s2io_msix_entry
));
3841 nic
->entries
[0].entry
= 0;
3842 nic
->s2io_entries
[0].entry
= 0;
3843 nic
->s2io_entries
[0].in_use
= MSIX_FLG
;
3844 nic
->s2io_entries
[0].type
= MSIX_ALARM_TYPE
;
3845 nic
->s2io_entries
[0].arg
= &nic
->mac_control
.fifos
;
3847 for (i
= 1; i
< nic
->num_entries
; i
++) {
3848 nic
->entries
[i
].entry
= ((i
- 1) * 8) + 1;
3849 nic
->s2io_entries
[i
].entry
= ((i
- 1) * 8) + 1;
3850 nic
->s2io_entries
[i
].arg
= NULL
;
3851 nic
->s2io_entries
[i
].in_use
= 0;
3854 rx_mat
= readq(&bar0
->rx_mat
);
3855 for (j
= 0; j
< nic
->config
.rx_ring_num
; j
++) {
3856 rx_mat
|= RX_MAT_SET(j
, msix_indx
);
3857 nic
->s2io_entries
[j
+1].arg
= &nic
->mac_control
.rings
[j
];
3858 nic
->s2io_entries
[j
+1].type
= MSIX_RING_TYPE
;
3859 nic
->s2io_entries
[j
+1].in_use
= MSIX_FLG
;
3862 writeq(rx_mat
, &bar0
->rx_mat
);
3863 readq(&bar0
->rx_mat
);
3865 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, nic
->num_entries
);
3866 /* We fail init if error or we get less vectors than min required */
3868 DBG_PRINT(ERR_DBG
, "%s: Enabling MSIX failed\n", nic
->dev
->name
);
3869 kfree(nic
->entries
);
3870 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3871 += (nic
->num_entries
* sizeof(struct msix_entry
));
3872 kfree(nic
->s2io_entries
);
3873 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3874 += (nic
->num_entries
* sizeof(struct s2io_msix_entry
));
3875 nic
->entries
= NULL
;
3876 nic
->s2io_entries
= NULL
;
3881 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3882 * in the herc NIC. (Temp change, needs to be removed later)
3884 pci_read_config_word(nic
->pdev
, 0x42, &msi_control
);
3885 msi_control
|= 0x1; /* Enable MSI */
3886 pci_write_config_word(nic
->pdev
, 0x42, msi_control
);
3891 /* Handle software interrupt used during MSI(X) test */
3892 static irqreturn_t
s2io_test_intr(int irq
, void *dev_id
)
3894 struct s2io_nic
*sp
= dev_id
;
3896 sp
->msi_detected
= 1;
3897 wake_up(&sp
->msi_wait
);
3902 /* Test interrupt path by forcing a a software IRQ */
3903 static int s2io_test_msi(struct s2io_nic
*sp
)
3905 struct pci_dev
*pdev
= sp
->pdev
;
3906 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3910 err
= request_irq(sp
->entries
[1].vector
, s2io_test_intr
, 0,
3913 DBG_PRINT(ERR_DBG
, "%s: PCI %s: cannot assign irq %d\n",
3914 sp
->dev
->name
, pci_name(pdev
), pdev
->irq
);
3918 init_waitqueue_head (&sp
->msi_wait
);
3919 sp
->msi_detected
= 0;
3921 saved64
= val64
= readq(&bar0
->scheduled_int_ctrl
);
3922 val64
|= SCHED_INT_CTRL_ONE_SHOT
;
3923 val64
|= SCHED_INT_CTRL_TIMER_EN
;
3924 val64
|= SCHED_INT_CTRL_INT2MSI(1);
3925 writeq(val64
, &bar0
->scheduled_int_ctrl
);
3927 wait_event_timeout(sp
->msi_wait
, sp
->msi_detected
, HZ
/10);
3929 if (!sp
->msi_detected
) {
3930 /* MSI(X) test failed, go back to INTx mode */
3931 DBG_PRINT(ERR_DBG
, "%s: PCI %s: No interrupt was generated "
3932 "using MSI(X) during test\n", sp
->dev
->name
,
3938 free_irq(sp
->entries
[1].vector
, sp
);
3940 writeq(saved64
, &bar0
->scheduled_int_ctrl
);
3945 static void remove_msix_isr(struct s2io_nic
*sp
)
3950 for (i
= 0; i
< sp
->num_entries
; i
++) {
3951 if (sp
->s2io_entries
[i
].in_use
==
3952 MSIX_REGISTERED_SUCCESS
) {
3953 int vector
= sp
->entries
[i
].vector
;
3954 void *arg
= sp
->s2io_entries
[i
].arg
;
3955 free_irq(vector
, arg
);
3960 kfree(sp
->s2io_entries
);
3962 sp
->s2io_entries
= NULL
;
3964 pci_read_config_word(sp
->pdev
, 0x42, &msi_control
);
3965 msi_control
&= 0xFFFE; /* Disable MSI */
3966 pci_write_config_word(sp
->pdev
, 0x42, msi_control
);
3968 pci_disable_msix(sp
->pdev
);
3971 static void remove_inta_isr(struct s2io_nic
*sp
)
3973 struct net_device
*dev
= sp
->dev
;
3975 free_irq(sp
->pdev
->irq
, dev
);
3978 /* ********************************************************* *
3979 * Functions defined below concern the OS part of the driver *
3980 * ********************************************************* */
3983 * s2io_open - open entry point of the driver
3984 * @dev : pointer to the device structure.
3986 * This function is the open entry point of the driver. It mainly calls a
3987 * function to allocate Rx buffers and inserts them into the buffer
3988 * descriptors and then enables the Rx part of the NIC.
3990 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3994 static int s2io_open(struct net_device
*dev
)
3996 struct s2io_nic
*sp
= dev
->priv
;
4000 * Make sure you have link off by default every time
4001 * Nic is initialized
4003 netif_carrier_off(dev
);
4004 sp
->last_link_state
= 0;
4006 /* Initialize H/W and enable interrupts */
4007 err
= s2io_card_up(sp
);
4009 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
4011 goto hw_init_failed
;
4014 if (do_s2io_prog_unicast(dev
, dev
->dev_addr
) == FAILURE
) {
4015 DBG_PRINT(ERR_DBG
, "Set Mac Address Failed\n");
4018 goto hw_init_failed
;
4020 s2io_start_all_tx_queue(sp
);
4024 if (sp
->config
.intr_type
== MSI_X
) {
4027 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
4028 += (sp
->num_entries
* sizeof(struct msix_entry
));
4030 if (sp
->s2io_entries
) {
4031 kfree(sp
->s2io_entries
);
4032 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
4033 += (sp
->num_entries
* sizeof(struct s2io_msix_entry
));
4040 * s2io_close -close entry point of the driver
4041 * @dev : device pointer.
4043 * This is the stop entry point of the driver. It needs to undo exactly
4044 * whatever was done by the open entry point,thus it's usually referred to
4045 * as the close function.Among other things this function mainly stops the
4046 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4048 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4052 static int s2io_close(struct net_device
*dev
)
4054 struct s2io_nic
*sp
= dev
->priv
;
4055 struct config_param
*config
= &sp
->config
;
4059 /* Return if the device is already closed *
4060 * Can happen when s2io_card_up failed in change_mtu *
4062 if (!is_s2io_card_up(sp
))
4065 s2io_stop_all_tx_queue(sp
);
4066 /* delete all populated mac entries */
4067 for (offset
= 1; offset
< config
->max_mc_addr
; offset
++) {
4068 tmp64
= do_s2io_read_unicast_mc(sp
, offset
);
4069 if (tmp64
!= S2IO_DISABLE_MAC_ENTRY
)
4070 do_s2io_delete_unicast_mc(sp
, tmp64
);
4079 * s2io_xmit - Tx entry point of te driver
4080 * @skb : the socket buffer containing the Tx data.
4081 * @dev : device pointer.
4083 * This function is the Tx entry point of the driver. S2IO NIC supports
4084 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4085 * NOTE: when device cant queue the pkt,just the trans_start variable will
4088 * 0 on success & 1 on failure.
4091 static int s2io_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
4093 struct s2io_nic
*sp
= dev
->priv
;
4094 u16 frg_cnt
, frg_len
, i
, queue
, queue_len
, put_off
, get_off
;
4097 struct TxFIFO_element __iomem
*tx_fifo
;
4098 unsigned long flags
= 0;
4100 struct fifo_info
*fifo
= NULL
;
4101 struct mac_info
*mac_control
;
4102 struct config_param
*config
;
4103 int do_spin_lock
= 1;
4105 int enable_per_list_interrupt
= 0;
4106 struct swStat
*stats
= &sp
->mac_control
.stats_info
->sw_stat
;
4108 mac_control
= &sp
->mac_control
;
4109 config
= &sp
->config
;
4111 DBG_PRINT(TX_DBG
, "%s: In Neterion Tx routine\n", dev
->name
);
4113 if (unlikely(skb
->len
<= 0)) {
4114 DBG_PRINT(TX_DBG
, "%s:Buffer has no data..\n", dev
->name
);
4115 dev_kfree_skb_any(skb
);
4119 if (!is_s2io_card_up(sp
)) {
4120 DBG_PRINT(TX_DBG
, "%s: Card going down for reset\n",
4127 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
))
4128 vlan_tag
= vlan_tx_tag_get(skb
);
4129 if (sp
->config
.tx_steering_type
== TX_DEFAULT_STEERING
) {
4130 if (skb
->protocol
== htons(ETH_P_IP
)) {
4135 if ((ip
->frag_off
& htons(IP_OFFSET
|IP_MF
)) == 0) {
4136 th
= (struct tcphdr
*)(((unsigned char *)ip
) +
4139 if (ip
->protocol
== IPPROTO_TCP
) {
4140 queue_len
= sp
->total_tcp_fifos
;
4141 queue
= (ntohs(th
->source
) +
4143 sp
->fifo_selector
[queue_len
- 1];
4144 if (queue
>= queue_len
)
4145 queue
= queue_len
- 1;
4146 } else if (ip
->protocol
== IPPROTO_UDP
) {
4147 queue_len
= sp
->total_udp_fifos
;
4148 queue
= (ntohs(th
->source
) +
4150 sp
->fifo_selector
[queue_len
- 1];
4151 if (queue
>= queue_len
)
4152 queue
= queue_len
- 1;
4153 queue
+= sp
->udp_fifo_idx
;
4154 if (skb
->len
> 1024)
4155 enable_per_list_interrupt
= 1;
4160 } else if (sp
->config
.tx_steering_type
== TX_PRIORITY_STEERING
)
4161 /* get fifo number based on skb->priority value */
4162 queue
= config
->fifo_mapping
4163 [skb
->priority
& (MAX_TX_FIFOS
- 1)];
4164 fifo
= &mac_control
->fifos
[queue
];
4167 spin_lock_irqsave(&fifo
->tx_lock
, flags
);
4169 if (unlikely(!spin_trylock_irqsave(&fifo
->tx_lock
, flags
)))
4170 return NETDEV_TX_LOCKED
;
4173 if (sp
->config
.multiq
) {
4174 if (__netif_subqueue_stopped(dev
, fifo
->fifo_no
)) {
4175 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4176 return NETDEV_TX_BUSY
;
4178 } else if (unlikely(fifo
->queue_state
== FIFO_QUEUE_STOP
)) {
4179 if (netif_queue_stopped(dev
)) {
4180 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4181 return NETDEV_TX_BUSY
;
4185 put_off
= (u16
) fifo
->tx_curr_put_info
.offset
;
4186 get_off
= (u16
) fifo
->tx_curr_get_info
.offset
;
4187 txdp
= (struct TxD
*) fifo
->list_info
[put_off
].list_virt_addr
;
4189 queue_len
= fifo
->tx_curr_put_info
.fifo_len
+ 1;
4190 /* Avoid "put" pointer going beyond "get" pointer */
4191 if (txdp
->Host_Control
||
4192 ((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4193 DBG_PRINT(TX_DBG
, "Error in xmit, No free TXDs.\n");
4194 s2io_stop_tx_queue(sp
, fifo
->fifo_no
);
4196 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4200 offload_type
= s2io_offload_type(skb
);
4201 if (offload_type
& (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
4202 txdp
->Control_1
|= TXD_TCP_LSO_EN
;
4203 txdp
->Control_1
|= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb
));
4205 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4207 (TXD_TX_CKO_IPV4_EN
| TXD_TX_CKO_TCP_EN
|
4210 txdp
->Control_1
|= TXD_GATHER_CODE_FIRST
;
4211 txdp
->Control_1
|= TXD_LIST_OWN_XENA
;
4212 txdp
->Control_2
|= TXD_INT_NUMBER(fifo
->fifo_no
);
4213 if (enable_per_list_interrupt
)
4214 if (put_off
& (queue_len
>> 5))
4215 txdp
->Control_2
|= TXD_INT_TYPE_PER_LIST
;
4217 txdp
->Control_2
|= TXD_VLAN_ENABLE
;
4218 txdp
->Control_2
|= TXD_VLAN_TAG(vlan_tag
);
4221 frg_len
= skb
->len
- skb
->data_len
;
4222 if (offload_type
== SKB_GSO_UDP
) {
4225 ufo_size
= s2io_udp_mss(skb
);
4227 txdp
->Control_1
|= TXD_UFO_EN
;
4228 txdp
->Control_1
|= TXD_UFO_MSS(ufo_size
);
4229 txdp
->Control_1
|= TXD_BUFFER0_SIZE(8);
4231 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4232 fifo
->ufo_in_band_v
[put_off
] =
4233 (__force u64
)skb_shinfo(skb
)->ip6_frag_id
;
4235 fifo
->ufo_in_band_v
[put_off
] =
4236 (__force u64
)skb_shinfo(skb
)->ip6_frag_id
<< 32;
4238 txdp
->Host_Control
= (unsigned long)fifo
->ufo_in_band_v
;
4239 txdp
->Buffer_Pointer
= pci_map_single(sp
->pdev
,
4240 fifo
->ufo_in_band_v
,
4241 sizeof(u64
), PCI_DMA_TODEVICE
);
4242 if (pci_dma_mapping_error(sp
->pdev
, txdp
->Buffer_Pointer
))
4243 goto pci_map_failed
;
4247 txdp
->Buffer_Pointer
= pci_map_single
4248 (sp
->pdev
, skb
->data
, frg_len
, PCI_DMA_TODEVICE
);
4249 if (pci_dma_mapping_error(sp
->pdev
, txdp
->Buffer_Pointer
))
4250 goto pci_map_failed
;
4252 txdp
->Host_Control
= (unsigned long) skb
;
4253 txdp
->Control_1
|= TXD_BUFFER0_SIZE(frg_len
);
4254 if (offload_type
== SKB_GSO_UDP
)
4255 txdp
->Control_1
|= TXD_UFO_EN
;
4257 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
4258 /* For fragmented SKB. */
4259 for (i
= 0; i
< frg_cnt
; i
++) {
4260 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
4261 /* A '0' length fragment will be ignored */
4265 txdp
->Buffer_Pointer
= (u64
) pci_map_page
4266 (sp
->pdev
, frag
->page
, frag
->page_offset
,
4267 frag
->size
, PCI_DMA_TODEVICE
);
4268 txdp
->Control_1
= TXD_BUFFER0_SIZE(frag
->size
);
4269 if (offload_type
== SKB_GSO_UDP
)
4270 txdp
->Control_1
|= TXD_UFO_EN
;
4272 txdp
->Control_1
|= TXD_GATHER_CODE_LAST
;
4274 if (offload_type
== SKB_GSO_UDP
)
4275 frg_cnt
++; /* as Txd0 was used for inband header */
4277 tx_fifo
= mac_control
->tx_FIFO_start
[queue
];
4278 val64
= fifo
->list_info
[put_off
].list_phy_addr
;
4279 writeq(val64
, &tx_fifo
->TxDL_Pointer
);
4281 val64
= (TX_FIFO_LAST_TXD_NUM(frg_cnt
) | TX_FIFO_FIRST_LIST
|
4284 val64
|= TX_FIFO_SPECIAL_FUNC
;
4286 writeq(val64
, &tx_fifo
->List_Control
);
4291 if (put_off
== fifo
->tx_curr_put_info
.fifo_len
+ 1)
4293 fifo
->tx_curr_put_info
.offset
= put_off
;
4295 /* Avoid "put" pointer going beyond "get" pointer */
4296 if (((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4297 sp
->mac_control
.stats_info
->sw_stat
.fifo_full_cnt
++;
4299 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4301 s2io_stop_tx_queue(sp
, fifo
->fifo_no
);
4303 mac_control
->stats_info
->sw_stat
.mem_allocated
+= skb
->truesize
;
4304 dev
->trans_start
= jiffies
;
4305 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4307 if (sp
->config
.intr_type
== MSI_X
)
4308 tx_intr_handler(fifo
);
4312 stats
->pci_map_fail_cnt
++;
4313 s2io_stop_tx_queue(sp
, fifo
->fifo_no
);
4314 stats
->mem_freed
+= skb
->truesize
;
4316 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4321 s2io_alarm_handle(unsigned long data
)
4323 struct s2io_nic
*sp
= (struct s2io_nic
*)data
;
4324 struct net_device
*dev
= sp
->dev
;
4326 s2io_handle_errors(dev
);
4327 mod_timer(&sp
->alarm_timer
, jiffies
+ HZ
/ 2);
4330 static irqreturn_t
s2io_msix_ring_handle(int irq
, void *dev_id
)
4332 struct ring_info
*ring
= (struct ring_info
*)dev_id
;
4333 struct s2io_nic
*sp
= ring
->nic
;
4334 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4335 struct net_device
*dev
= sp
->dev
;
4337 if (unlikely(!is_s2io_card_up(sp
)))
4340 if (sp
->config
.napi
) {
4341 u8 __iomem
*addr
= NULL
;
4344 addr
= (u8 __iomem
*)&bar0
->xmsi_mask_reg
;
4345 addr
+= (7 - ring
->ring_no
);
4346 val8
= (ring
->ring_no
== 0) ? 0x7f : 0xff;
4349 netif_rx_schedule(dev
, &ring
->napi
);
4351 rx_intr_handler(ring
, 0);
4352 s2io_chk_rx_buffers(sp
, ring
);
4358 static irqreturn_t
s2io_msix_fifo_handle(int irq
, void *dev_id
)
4361 struct fifo_info
*fifos
= (struct fifo_info
*)dev_id
;
4362 struct s2io_nic
*sp
= fifos
->nic
;
4363 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4364 struct config_param
*config
= &sp
->config
;
4367 if (unlikely(!is_s2io_card_up(sp
)))
4370 reason
= readq(&bar0
->general_int_status
);
4371 if (unlikely(reason
== S2IO_MINUS_ONE
))
4372 /* Nothing much can be done. Get out */
4375 if (reason
& (GEN_INTR_TXPIC
| GEN_INTR_TXTRAFFIC
)) {
4376 writeq(S2IO_MINUS_ONE
, &bar0
->general_int_mask
);
4378 if (reason
& GEN_INTR_TXPIC
)
4379 s2io_txpic_intr_handle(sp
);
4381 if (reason
& GEN_INTR_TXTRAFFIC
)
4382 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4384 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4385 tx_intr_handler(&fifos
[i
]);
4387 writeq(sp
->general_int_mask
, &bar0
->general_int_mask
);
4388 readl(&bar0
->general_int_status
);
4391 /* The interrupt was not raised by us */
4395 static void s2io_txpic_intr_handle(struct s2io_nic
*sp
)
4397 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4400 val64
= readq(&bar0
->pic_int_status
);
4401 if (val64
& PIC_INT_GPIO
) {
4402 val64
= readq(&bar0
->gpio_int_reg
);
4403 if ((val64
& GPIO_INT_REG_LINK_DOWN
) &&
4404 (val64
& GPIO_INT_REG_LINK_UP
)) {
4406 * This is unstable state so clear both up/down
4407 * interrupt and adapter to re-evaluate the link state.
4409 val64
|= GPIO_INT_REG_LINK_DOWN
;
4410 val64
|= GPIO_INT_REG_LINK_UP
;
4411 writeq(val64
, &bar0
->gpio_int_reg
);
4412 val64
= readq(&bar0
->gpio_int_mask
);
4413 val64
&= ~(GPIO_INT_MASK_LINK_UP
|
4414 GPIO_INT_MASK_LINK_DOWN
);
4415 writeq(val64
, &bar0
->gpio_int_mask
);
4417 else if (val64
& GPIO_INT_REG_LINK_UP
) {
4418 val64
= readq(&bar0
->adapter_status
);
4419 /* Enable Adapter */
4420 val64
= readq(&bar0
->adapter_control
);
4421 val64
|= ADAPTER_CNTL_EN
;
4422 writeq(val64
, &bar0
->adapter_control
);
4423 val64
|= ADAPTER_LED_ON
;
4424 writeq(val64
, &bar0
->adapter_control
);
4425 if (!sp
->device_enabled_once
)
4426 sp
->device_enabled_once
= 1;
4428 s2io_link(sp
, LINK_UP
);
4430 * unmask link down interrupt and mask link-up
4433 val64
= readq(&bar0
->gpio_int_mask
);
4434 val64
&= ~GPIO_INT_MASK_LINK_DOWN
;
4435 val64
|= GPIO_INT_MASK_LINK_UP
;
4436 writeq(val64
, &bar0
->gpio_int_mask
);
4438 }else if (val64
& GPIO_INT_REG_LINK_DOWN
) {
4439 val64
= readq(&bar0
->adapter_status
);
4440 s2io_link(sp
, LINK_DOWN
);
4441 /* Link is down so unmaks link up interrupt */
4442 val64
= readq(&bar0
->gpio_int_mask
);
4443 val64
&= ~GPIO_INT_MASK_LINK_UP
;
4444 val64
|= GPIO_INT_MASK_LINK_DOWN
;
4445 writeq(val64
, &bar0
->gpio_int_mask
);
4448 val64
= readq(&bar0
->adapter_control
);
4449 val64
= val64
&(~ADAPTER_LED_ON
);
4450 writeq(val64
, &bar0
->adapter_control
);
4453 val64
= readq(&bar0
->gpio_int_mask
);
4457 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4458 * @value: alarm bits
4459 * @addr: address value
4460 * @cnt: counter variable
4461 * Description: Check for alarm and increment the counter
4463 * 1 - if alarm bit set
4464 * 0 - if alarm bit is not set
4466 static int do_s2io_chk_alarm_bit(u64 value
, void __iomem
* addr
,
4467 unsigned long long *cnt
)
4470 val64
= readq(addr
);
4471 if ( val64
& value
) {
4472 writeq(val64
, addr
);
4481 * s2io_handle_errors - Xframe error indication handler
4482 * @nic: device private variable
4483 * Description: Handle alarms such as loss of link, single or
4484 * double ECC errors, critical and serious errors.
4488 static void s2io_handle_errors(void * dev_id
)
4490 struct net_device
*dev
= (struct net_device
*) dev_id
;
4491 struct s2io_nic
*sp
= dev
->priv
;
4492 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4493 u64 temp64
= 0,val64
=0;
4496 struct swStat
*sw_stat
= &sp
->mac_control
.stats_info
->sw_stat
;
4497 struct xpakStat
*stats
= &sp
->mac_control
.stats_info
->xpak_stat
;
4499 if (!is_s2io_card_up(sp
))
4502 if (pci_channel_offline(sp
->pdev
))
4505 memset(&sw_stat
->ring_full_cnt
, 0,
4506 sizeof(sw_stat
->ring_full_cnt
));
4508 /* Handling the XPAK counters update */
4509 if(stats
->xpak_timer_count
< 72000) {
4510 /* waiting for an hour */
4511 stats
->xpak_timer_count
++;
4513 s2io_updt_xpak_counter(dev
);
4514 /* reset the count to zero */
4515 stats
->xpak_timer_count
= 0;
4518 /* Handling link status change error Intr */
4519 if (s2io_link_fault_indication(sp
) == MAC_RMAC_ERR_TIMER
) {
4520 val64
= readq(&bar0
->mac_rmac_err_reg
);
4521 writeq(val64
, &bar0
->mac_rmac_err_reg
);
4522 if (val64
& RMAC_LINK_STATE_CHANGE_INT
)
4523 schedule_work(&sp
->set_link_task
);
4526 /* In case of a serious error, the device will be Reset. */
4527 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY
, &bar0
->serr_source
,
4528 &sw_stat
->serious_err_cnt
))
4531 /* Check for data parity error */
4532 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT
, &bar0
->gpio_int_reg
,
4533 &sw_stat
->parity_err_cnt
))
4536 /* Check for ring full counter */
4537 if (sp
->device_type
== XFRAME_II_DEVICE
) {
4538 val64
= readq(&bar0
->ring_bump_counter1
);
4539 for (i
=0; i
<4; i
++) {
4540 temp64
= ( val64
& vBIT(0xFFFF,(i
*16),16));
4541 temp64
>>= 64 - ((i
+1)*16);
4542 sw_stat
->ring_full_cnt
[i
] += temp64
;
4545 val64
= readq(&bar0
->ring_bump_counter2
);
4546 for (i
=0; i
<4; i
++) {
4547 temp64
= ( val64
& vBIT(0xFFFF,(i
*16),16));
4548 temp64
>>= 64 - ((i
+1)*16);
4549 sw_stat
->ring_full_cnt
[i
+4] += temp64
;
4553 val64
= readq(&bar0
->txdma_int_status
);
4554 /*check for pfc_err*/
4555 if (val64
& TXDMA_PFC_INT
) {
4556 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR
| PFC_SM_ERR_ALARM
|
4557 PFC_MISC_0_ERR
| PFC_MISC_1_ERR
|
4558 PFC_PCIX_ERR
, &bar0
->pfc_err_reg
,
4559 &sw_stat
->pfc_err_cnt
))
4561 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR
, &bar0
->pfc_err_reg
,
4562 &sw_stat
->pfc_err_cnt
);
4565 /*check for tda_err*/
4566 if (val64
& TXDMA_TDA_INT
) {
4567 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR
| TDA_SM0_ERR_ALARM
|
4568 TDA_SM1_ERR_ALARM
, &bar0
->tda_err_reg
,
4569 &sw_stat
->tda_err_cnt
))
4571 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR
| TDA_PCIX_ERR
,
4572 &bar0
->tda_err_reg
, &sw_stat
->tda_err_cnt
);
4574 /*check for pcc_err*/
4575 if (val64
& TXDMA_PCC_INT
) {
4576 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM
| PCC_WR_ERR_ALARM
4577 | PCC_N_SERR
| PCC_6_COF_OV_ERR
4578 | PCC_7_COF_OV_ERR
| PCC_6_LSO_OV_ERR
4579 | PCC_7_LSO_OV_ERR
| PCC_FB_ECC_DB_ERR
4580 | PCC_TXB_ECC_DB_ERR
, &bar0
->pcc_err_reg
,
4581 &sw_stat
->pcc_err_cnt
))
4583 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR
| PCC_TXB_ECC_SG_ERR
,
4584 &bar0
->pcc_err_reg
, &sw_stat
->pcc_err_cnt
);
4587 /*check for tti_err*/
4588 if (val64
& TXDMA_TTI_INT
) {
4589 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM
, &bar0
->tti_err_reg
,
4590 &sw_stat
->tti_err_cnt
))
4592 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR
| TTI_ECC_DB_ERR
,
4593 &bar0
->tti_err_reg
, &sw_stat
->tti_err_cnt
);
4596 /*check for lso_err*/
4597 if (val64
& TXDMA_LSO_INT
) {
4598 if (do_s2io_chk_alarm_bit(LSO6_ABORT
| LSO7_ABORT
4599 | LSO6_SM_ERR_ALARM
| LSO7_SM_ERR_ALARM
,
4600 &bar0
->lso_err_reg
, &sw_stat
->lso_err_cnt
))
4602 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW
| LSO7_SEND_OFLOW
,
4603 &bar0
->lso_err_reg
, &sw_stat
->lso_err_cnt
);
4606 /*check for tpa_err*/
4607 if (val64
& TXDMA_TPA_INT
) {
4608 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM
, &bar0
->tpa_err_reg
,
4609 &sw_stat
->tpa_err_cnt
))
4611 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP
, &bar0
->tpa_err_reg
,
4612 &sw_stat
->tpa_err_cnt
);
4615 /*check for sm_err*/
4616 if (val64
& TXDMA_SM_INT
) {
4617 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM
, &bar0
->sm_err_reg
,
4618 &sw_stat
->sm_err_cnt
))
4622 val64
= readq(&bar0
->mac_int_status
);
4623 if (val64
& MAC_INT_STATUS_TMAC_INT
) {
4624 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN
| TMAC_TX_SM_ERR
,
4625 &bar0
->mac_tmac_err_reg
,
4626 &sw_stat
->mac_tmac_err_cnt
))
4628 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR
| TMAC_ECC_DB_ERR
4629 | TMAC_DESC_ECC_SG_ERR
| TMAC_DESC_ECC_DB_ERR
,
4630 &bar0
->mac_tmac_err_reg
,
4631 &sw_stat
->mac_tmac_err_cnt
);
4634 val64
= readq(&bar0
->xgxs_int_status
);
4635 if (val64
& XGXS_INT_STATUS_TXGXS
) {
4636 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW
| TXGXS_TX_SM_ERR
,
4637 &bar0
->xgxs_txgxs_err_reg
,
4638 &sw_stat
->xgxs_txgxs_err_cnt
))
4640 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR
| TXGXS_ECC_DB_ERR
,
4641 &bar0
->xgxs_txgxs_err_reg
,
4642 &sw_stat
->xgxs_txgxs_err_cnt
);
4645 val64
= readq(&bar0
->rxdma_int_status
);
4646 if (val64
& RXDMA_INT_RC_INT_M
) {
4647 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR
| RC_FTC_ECC_DB_ERR
4648 | RC_PRCn_SM_ERR_ALARM
|RC_FTC_SM_ERR_ALARM
,
4649 &bar0
->rc_err_reg
, &sw_stat
->rc_err_cnt
))
4651 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR
| RC_FTC_ECC_SG_ERR
4652 | RC_RDA_FAIL_WR_Rn
, &bar0
->rc_err_reg
,
4653 &sw_stat
->rc_err_cnt
);
4654 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn
| PRC_PCI_AB_WR_Rn
4655 | PRC_PCI_AB_F_WR_Rn
, &bar0
->prc_pcix_err_reg
,
4656 &sw_stat
->prc_pcix_err_cnt
))
4658 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn
| PRC_PCI_DP_WR_Rn
4659 | PRC_PCI_DP_F_WR_Rn
, &bar0
->prc_pcix_err_reg
,
4660 &sw_stat
->prc_pcix_err_cnt
);
4663 if (val64
& RXDMA_INT_RPA_INT_M
) {
4664 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM
| RPA_CREDIT_ERR
,
4665 &bar0
->rpa_err_reg
, &sw_stat
->rpa_err_cnt
))
4667 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR
| RPA_ECC_DB_ERR
,
4668 &bar0
->rpa_err_reg
, &sw_stat
->rpa_err_cnt
);
4671 if (val64
& RXDMA_INT_RDA_INT_M
) {
4672 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4673 | RDA_FRM_ECC_DB_N_AERR
| RDA_SM1_ERR_ALARM
4674 | RDA_SM0_ERR_ALARM
| RDA_RXD_ECC_DB_SERR
,
4675 &bar0
->rda_err_reg
, &sw_stat
->rda_err_cnt
))
4677 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR
| RDA_FRM_ECC_SG_ERR
4678 | RDA_MISC_ERR
| RDA_PCIX_ERR
,
4679 &bar0
->rda_err_reg
, &sw_stat
->rda_err_cnt
);
4682 if (val64
& RXDMA_INT_RTI_INT_M
) {
4683 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM
, &bar0
->rti_err_reg
,
4684 &sw_stat
->rti_err_cnt
))
4686 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR
| RTI_ECC_DB_ERR
,
4687 &bar0
->rti_err_reg
, &sw_stat
->rti_err_cnt
);
4690 val64
= readq(&bar0
->mac_int_status
);
4691 if (val64
& MAC_INT_STATUS_RMAC_INT
) {
4692 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN
| RMAC_RX_SM_ERR
,
4693 &bar0
->mac_rmac_err_reg
,
4694 &sw_stat
->mac_rmac_err_cnt
))
4696 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT
|RMAC_SINGLE_ECC_ERR
|
4697 RMAC_DOUBLE_ECC_ERR
, &bar0
->mac_rmac_err_reg
,
4698 &sw_stat
->mac_rmac_err_cnt
);
4701 val64
= readq(&bar0
->xgxs_int_status
);
4702 if (val64
& XGXS_INT_STATUS_RXGXS
) {
4703 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW
| RXGXS_RX_SM_ERR
,
4704 &bar0
->xgxs_rxgxs_err_reg
,
4705 &sw_stat
->xgxs_rxgxs_err_cnt
))
4709 val64
= readq(&bar0
->mc_int_status
);
4710 if(val64
& MC_INT_STATUS_MC_INT
) {
4711 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR
, &bar0
->mc_err_reg
,
4712 &sw_stat
->mc_err_cnt
))
4715 /* Handling Ecc errors */
4716 if (val64
& (MC_ERR_REG_ECC_ALL_SNG
| MC_ERR_REG_ECC_ALL_DBL
)) {
4717 writeq(val64
, &bar0
->mc_err_reg
);
4718 if (val64
& MC_ERR_REG_ECC_ALL_DBL
) {
4719 sw_stat
->double_ecc_errs
++;
4720 if (sp
->device_type
!= XFRAME_II_DEVICE
) {
4722 * Reset XframeI only if critical error
4725 (MC_ERR_REG_MIRI_ECC_DB_ERR_0
|
4726 MC_ERR_REG_MIRI_ECC_DB_ERR_1
))
4730 sw_stat
->single_ecc_errs
++;
4736 s2io_stop_all_tx_queue(sp
);
4737 schedule_work(&sp
->rst_timer_task
);
4738 sw_stat
->soft_reset_cnt
++;
4743 * s2io_isr - ISR handler of the device .
4744 * @irq: the irq of the device.
4745 * @dev_id: a void pointer to the dev structure of the NIC.
4746 * Description: This function is the ISR handler of the device. It
4747 * identifies the reason for the interrupt and calls the relevant
4748 * service routines. As a contongency measure, this ISR allocates the
4749 * recv buffers, if their numbers are below the panic value which is
4750 * presently set to 25% of the original number of rcv buffers allocated.
4752 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4753 * IRQ_NONE: will be returned if interrupt is not from our device
4755 static irqreturn_t
s2io_isr(int irq
, void *dev_id
)
4757 struct net_device
*dev
= (struct net_device
*) dev_id
;
4758 struct s2io_nic
*sp
= dev
->priv
;
4759 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4762 struct mac_info
*mac_control
;
4763 struct config_param
*config
;
4765 /* Pretend we handled any irq's from a disconnected card */
4766 if (pci_channel_offline(sp
->pdev
))
4769 if (!is_s2io_card_up(sp
))
4772 mac_control
= &sp
->mac_control
;
4773 config
= &sp
->config
;
4776 * Identify the cause for interrupt and call the appropriate
4777 * interrupt handler. Causes for the interrupt could be;
4782 reason
= readq(&bar0
->general_int_status
);
4784 if (unlikely(reason
== S2IO_MINUS_ONE
) ) {
4785 /* Nothing much can be done. Get out */
4789 if (reason
& (GEN_INTR_RXTRAFFIC
|
4790 GEN_INTR_TXTRAFFIC
| GEN_INTR_TXPIC
))
4792 writeq(S2IO_MINUS_ONE
, &bar0
->general_int_mask
);
4795 if (reason
& GEN_INTR_RXTRAFFIC
) {
4796 netif_rx_schedule(dev
, &sp
->napi
);
4797 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_mask
);
4798 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4799 readl(&bar0
->rx_traffic_int
);
4803 * rx_traffic_int reg is an R1 register, writing all 1's
4804 * will ensure that the actual interrupt causing bit
4805 * get's cleared and hence a read can be avoided.
4807 if (reason
& GEN_INTR_RXTRAFFIC
)
4808 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4810 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4811 rx_intr_handler(&mac_control
->rings
[i
], 0);
4815 * tx_traffic_int reg is an R1 register, writing all 1's
4816 * will ensure that the actual interrupt causing bit get's
4817 * cleared and hence a read can be avoided.
4819 if (reason
& GEN_INTR_TXTRAFFIC
)
4820 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4822 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4823 tx_intr_handler(&mac_control
->fifos
[i
]);
4825 if (reason
& GEN_INTR_TXPIC
)
4826 s2io_txpic_intr_handle(sp
);
4829 * Reallocate the buffers from the interrupt handler itself.
4831 if (!config
->napi
) {
4832 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4833 s2io_chk_rx_buffers(sp
, &mac_control
->rings
[i
]);
4835 writeq(sp
->general_int_mask
, &bar0
->general_int_mask
);
4836 readl(&bar0
->general_int_status
);
4842 /* The interrupt was not raised by us */
4852 static void s2io_updt_stats(struct s2io_nic
*sp
)
4854 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4858 if (is_s2io_card_up(sp
)) {
4859 /* Apprx 30us on a 133 MHz bus */
4860 val64
= SET_UPDT_CLICKS(10) |
4861 STAT_CFG_ONE_SHOT_EN
| STAT_CFG_STAT_EN
;
4862 writeq(val64
, &bar0
->stat_cfg
);
4865 val64
= readq(&bar0
->stat_cfg
);
4866 if (!(val64
& s2BIT(0)))
4870 break; /* Updt failed */
4876 * s2io_get_stats - Updates the device statistics structure.
4877 * @dev : pointer to the device structure.
4879 * This function updates the device statistics structure in the s2io_nic
4880 * structure and returns a pointer to the same.
4882 * pointer to the updated net_device_stats structure.
4885 static struct net_device_stats
*s2io_get_stats(struct net_device
*dev
)
4887 struct s2io_nic
*sp
= dev
->priv
;
4888 struct mac_info
*mac_control
;
4889 struct config_param
*config
;
4893 mac_control
= &sp
->mac_control
;
4894 config
= &sp
->config
;
4896 /* Configure Stats for immediate updt */
4897 s2io_updt_stats(sp
);
4899 /* Using sp->stats as a staging area, because reset (due to mtu
4900 change, for example) will clear some hardware counters */
4901 dev
->stats
.tx_packets
+=
4902 le32_to_cpu(mac_control
->stats_info
->tmac_frms
) -
4903 sp
->stats
.tx_packets
;
4904 sp
->stats
.tx_packets
=
4905 le32_to_cpu(mac_control
->stats_info
->tmac_frms
);
4906 dev
->stats
.tx_errors
+=
4907 le32_to_cpu(mac_control
->stats_info
->tmac_any_err_frms
) -
4908 sp
->stats
.tx_errors
;
4909 sp
->stats
.tx_errors
=
4910 le32_to_cpu(mac_control
->stats_info
->tmac_any_err_frms
);
4911 dev
->stats
.rx_errors
+=
4912 le64_to_cpu(mac_control
->stats_info
->rmac_drop_frms
) -
4913 sp
->stats
.rx_errors
;
4914 sp
->stats
.rx_errors
=
4915 le64_to_cpu(mac_control
->stats_info
->rmac_drop_frms
);
4916 dev
->stats
.multicast
=
4917 le32_to_cpu(mac_control
->stats_info
->rmac_vld_mcst_frms
) -
4918 sp
->stats
.multicast
;
4919 sp
->stats
.multicast
=
4920 le32_to_cpu(mac_control
->stats_info
->rmac_vld_mcst_frms
);
4921 dev
->stats
.rx_length_errors
=
4922 le64_to_cpu(mac_control
->stats_info
->rmac_long_frms
) -
4923 sp
->stats
.rx_length_errors
;
4924 sp
->stats
.rx_length_errors
=
4925 le64_to_cpu(mac_control
->stats_info
->rmac_long_frms
);
4927 /* collect per-ring rx_packets and rx_bytes */
4928 dev
->stats
.rx_packets
= dev
->stats
.rx_bytes
= 0;
4929 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
4930 dev
->stats
.rx_packets
+= mac_control
->rings
[i
].rx_packets
;
4931 dev
->stats
.rx_bytes
+= mac_control
->rings
[i
].rx_bytes
;
4934 return (&dev
->stats
);
4938 * s2io_set_multicast - entry point for multicast address enable/disable.
4939 * @dev : pointer to the device structure
4941 * This function is a driver entry point which gets called by the kernel
4942 * whenever multicast addresses must be enabled/disabled. This also gets
4943 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4944 * determine, if multicast address must be enabled or if promiscuous mode
4945 * is to be disabled etc.
4950 static void s2io_set_multicast(struct net_device
*dev
)
4953 struct dev_mc_list
*mclist
;
4954 struct s2io_nic
*sp
= dev
->priv
;
4955 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4956 u64 val64
= 0, multi_mac
= 0x010203040506ULL
, mask
=
4958 u64 dis_addr
= S2IO_DISABLE_MAC_ENTRY
, mac_addr
= 0;
4960 struct config_param
*config
= &sp
->config
;
4962 if ((dev
->flags
& IFF_ALLMULTI
) && (!sp
->m_cast_flg
)) {
4963 /* Enable all Multicast addresses */
4964 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac
),
4965 &bar0
->rmac_addr_data0_mem
);
4966 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask
),
4967 &bar0
->rmac_addr_data1_mem
);
4968 val64
= RMAC_ADDR_CMD_MEM_WE
|
4969 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4970 RMAC_ADDR_CMD_MEM_OFFSET(config
->max_mc_addr
- 1);
4971 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4972 /* Wait till command completes */
4973 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4974 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4978 sp
->all_multi_pos
= config
->max_mc_addr
- 1;
4979 } else if ((dev
->flags
& IFF_ALLMULTI
) && (sp
->m_cast_flg
)) {
4980 /* Disable all Multicast addresses */
4981 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4982 &bar0
->rmac_addr_data0_mem
);
4983 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4984 &bar0
->rmac_addr_data1_mem
);
4985 val64
= RMAC_ADDR_CMD_MEM_WE
|
4986 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4987 RMAC_ADDR_CMD_MEM_OFFSET(sp
->all_multi_pos
);
4988 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4989 /* Wait till command completes */
4990 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4991 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4995 sp
->all_multi_pos
= 0;
4998 if ((dev
->flags
& IFF_PROMISC
) && (!sp
->promisc_flg
)) {
4999 /* Put the NIC into promiscuous mode */
5000 add
= &bar0
->mac_cfg
;
5001 val64
= readq(&bar0
->mac_cfg
);
5002 val64
|= MAC_CFG_RMAC_PROM_ENABLE
;
5004 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5005 writel((u32
) val64
, add
);
5006 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5007 writel((u32
) (val64
>> 32), (add
+ 4));
5009 if (vlan_tag_strip
!= 1) {
5010 val64
= readq(&bar0
->rx_pa_cfg
);
5011 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
5012 writeq(val64
, &bar0
->rx_pa_cfg
);
5013 vlan_strip_flag
= 0;
5016 val64
= readq(&bar0
->mac_cfg
);
5017 sp
->promisc_flg
= 1;
5018 DBG_PRINT(INFO_DBG
, "%s: entered promiscuous mode\n",
5020 } else if (!(dev
->flags
& IFF_PROMISC
) && (sp
->promisc_flg
)) {
5021 /* Remove the NIC from promiscuous mode */
5022 add
= &bar0
->mac_cfg
;
5023 val64
= readq(&bar0
->mac_cfg
);
5024 val64
&= ~MAC_CFG_RMAC_PROM_ENABLE
;
5026 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5027 writel((u32
) val64
, add
);
5028 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5029 writel((u32
) (val64
>> 32), (add
+ 4));
5031 if (vlan_tag_strip
!= 0) {
5032 val64
= readq(&bar0
->rx_pa_cfg
);
5033 val64
|= RX_PA_CFG_STRIP_VLAN_TAG
;
5034 writeq(val64
, &bar0
->rx_pa_cfg
);
5035 vlan_strip_flag
= 1;
5038 val64
= readq(&bar0
->mac_cfg
);
5039 sp
->promisc_flg
= 0;
5040 DBG_PRINT(INFO_DBG
, "%s: left promiscuous mode\n",
5044 /* Update individual M_CAST address list */
5045 if ((!sp
->m_cast_flg
) && dev
->mc_count
) {
5047 (config
->max_mc_addr
- config
->max_mac_addr
)) {
5048 DBG_PRINT(ERR_DBG
, "%s: No more Rx filters ",
5050 DBG_PRINT(ERR_DBG
, "can be added, please enable ");
5051 DBG_PRINT(ERR_DBG
, "ALL_MULTI instead\n");
5055 prev_cnt
= sp
->mc_addr_count
;
5056 sp
->mc_addr_count
= dev
->mc_count
;
5058 /* Clear out the previous list of Mc in the H/W. */
5059 for (i
= 0; i
< prev_cnt
; i
++) {
5060 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
5061 &bar0
->rmac_addr_data0_mem
);
5062 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5063 &bar0
->rmac_addr_data1_mem
);
5064 val64
= RMAC_ADDR_CMD_MEM_WE
|
5065 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5066 RMAC_ADDR_CMD_MEM_OFFSET
5067 (config
->mc_start_offset
+ i
);
5068 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5070 /* Wait for command completes */
5071 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5072 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5074 DBG_PRINT(ERR_DBG
, "%s: Adding ",
5076 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
5081 /* Create the new Rx filter list and update the same in H/W. */
5082 for (i
= 0, mclist
= dev
->mc_list
; i
< dev
->mc_count
;
5083 i
++, mclist
= mclist
->next
) {
5084 memcpy(sp
->usr_addrs
[i
].addr
, mclist
->dmi_addr
,
5087 for (j
= 0; j
< ETH_ALEN
; j
++) {
5088 mac_addr
|= mclist
->dmi_addr
[j
];
5092 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
5093 &bar0
->rmac_addr_data0_mem
);
5094 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5095 &bar0
->rmac_addr_data1_mem
);
5096 val64
= RMAC_ADDR_CMD_MEM_WE
|
5097 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5098 RMAC_ADDR_CMD_MEM_OFFSET
5099 (i
+ config
->mc_start_offset
);
5100 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5102 /* Wait for command completes */
5103 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5104 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5106 DBG_PRINT(ERR_DBG
, "%s: Adding ",
5108 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
5115 /* read from CAM unicast & multicast addresses and store it in
5116 * def_mac_addr structure
5118 void do_s2io_store_unicast_mc(struct s2io_nic
*sp
)
5122 struct config_param
*config
= &sp
->config
;
5124 /* store unicast & multicast mac addresses */
5125 for (offset
= 0; offset
< config
->max_mc_addr
; offset
++) {
5126 mac_addr
= do_s2io_read_unicast_mc(sp
, offset
);
5127 /* if read fails disable the entry */
5128 if (mac_addr
== FAILURE
)
5129 mac_addr
= S2IO_DISABLE_MAC_ENTRY
;
5130 do_s2io_copy_mac_addr(sp
, offset
, mac_addr
);
5134 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5135 static void do_s2io_restore_unicast_mc(struct s2io_nic
*sp
)
5138 struct config_param
*config
= &sp
->config
;
5139 /* restore unicast mac address */
5140 for (offset
= 0; offset
< config
->max_mac_addr
; offset
++)
5141 do_s2io_prog_unicast(sp
->dev
,
5142 sp
->def_mac_addr
[offset
].mac_addr
);
5144 /* restore multicast mac address */
5145 for (offset
= config
->mc_start_offset
;
5146 offset
< config
->max_mc_addr
; offset
++)
5147 do_s2io_add_mc(sp
, sp
->def_mac_addr
[offset
].mac_addr
);
5150 /* add a multicast MAC address to CAM */
5151 static int do_s2io_add_mc(struct s2io_nic
*sp
, u8
*addr
)
5155 struct config_param
*config
= &sp
->config
;
5157 for (i
= 0; i
< ETH_ALEN
; i
++) {
5159 mac_addr
|= addr
[i
];
5161 if ((0ULL == mac_addr
) || (mac_addr
== S2IO_DISABLE_MAC_ENTRY
))
5164 /* check if the multicast mac already preset in CAM */
5165 for (i
= config
->mc_start_offset
; i
< config
->max_mc_addr
; i
++) {
5167 tmp64
= do_s2io_read_unicast_mc(sp
, i
);
5168 if (tmp64
== S2IO_DISABLE_MAC_ENTRY
) /* CAM entry is empty */
5171 if (tmp64
== mac_addr
)
5174 if (i
== config
->max_mc_addr
) {
5176 "CAM full no space left for multicast MAC\n");
5179 /* Update the internal structure with this new mac address */
5180 do_s2io_copy_mac_addr(sp
, i
, mac_addr
);
5182 return (do_s2io_add_mac(sp
, mac_addr
, i
));
5185 /* add MAC address to CAM */
5186 static int do_s2io_add_mac(struct s2io_nic
*sp
, u64 addr
, int off
)
5189 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5191 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr
),
5192 &bar0
->rmac_addr_data0_mem
);
5195 RMAC_ADDR_CMD_MEM_WE
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5196 RMAC_ADDR_CMD_MEM_OFFSET(off
);
5197 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5199 /* Wait till command completes */
5200 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5201 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5203 DBG_PRINT(INFO_DBG
, "do_s2io_add_mac failed\n");
5208 /* deletes a specified unicast/multicast mac entry from CAM */
5209 static int do_s2io_delete_unicast_mc(struct s2io_nic
*sp
, u64 addr
)
5212 u64 dis_addr
= S2IO_DISABLE_MAC_ENTRY
, tmp64
;
5213 struct config_param
*config
= &sp
->config
;
5216 offset
< config
->max_mc_addr
; offset
++) {
5217 tmp64
= do_s2io_read_unicast_mc(sp
, offset
);
5218 if (tmp64
== addr
) {
5219 /* disable the entry by writing 0xffffffffffffULL */
5220 if (do_s2io_add_mac(sp
, dis_addr
, offset
) == FAILURE
)
5222 /* store the new mac list from CAM */
5223 do_s2io_store_unicast_mc(sp
);
5227 DBG_PRINT(ERR_DBG
, "MAC address 0x%llx not found in CAM\n",
5228 (unsigned long long)addr
);
5232 /* read mac entries from CAM */
5233 static u64
do_s2io_read_unicast_mc(struct s2io_nic
*sp
, int offset
)
5235 u64 tmp64
= 0xffffffffffff0000ULL
, val64
;
5236 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5240 RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5241 RMAC_ADDR_CMD_MEM_OFFSET(offset
);
5242 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5244 /* Wait till command completes */
5245 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5246 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5248 DBG_PRINT(INFO_DBG
, "do_s2io_read_unicast_mc failed\n");
5251 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
5252 return (tmp64
>> 16);
5256 * s2io_set_mac_addr driver entry point
5259 static int s2io_set_mac_addr(struct net_device
*dev
, void *p
)
5261 struct sockaddr
*addr
= p
;
5263 if (!is_valid_ether_addr(addr
->sa_data
))
5266 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5268 /* store the MAC address in CAM */
5269 return (do_s2io_prog_unicast(dev
, dev
->dev_addr
));
5272 * do_s2io_prog_unicast - Programs the Xframe mac address
5273 * @dev : pointer to the device structure.
5274 * @addr: a uchar pointer to the new mac address which is to be set.
5275 * Description : This procedure will program the Xframe to receive
5276 * frames with new Mac Address
5277 * Return value: SUCCESS on success and an appropriate (-)ve integer
5278 * as defined in errno.h file on failure.
5281 static int do_s2io_prog_unicast(struct net_device
*dev
, u8
*addr
)
5283 struct s2io_nic
*sp
= dev
->priv
;
5284 register u64 mac_addr
= 0, perm_addr
= 0;
5287 struct config_param
*config
= &sp
->config
;
5290 * Set the new MAC address as the new unicast filter and reflect this
5291 * change on the device address registered with the OS. It will be
5294 for (i
= 0; i
< ETH_ALEN
; i
++) {
5296 mac_addr
|= addr
[i
];
5298 perm_addr
|= sp
->def_mac_addr
[0].mac_addr
[i
];
5301 /* check if the dev_addr is different than perm_addr */
5302 if (mac_addr
== perm_addr
)
5305 /* check if the mac already preset in CAM */
5306 for (i
= 1; i
< config
->max_mac_addr
; i
++) {
5307 tmp64
= do_s2io_read_unicast_mc(sp
, i
);
5308 if (tmp64
== S2IO_DISABLE_MAC_ENTRY
) /* CAM entry is empty */
5311 if (tmp64
== mac_addr
) {
5313 "MAC addr:0x%llx already present in CAM\n",
5314 (unsigned long long)mac_addr
);
5318 if (i
== config
->max_mac_addr
) {
5319 DBG_PRINT(ERR_DBG
, "CAM full no space left for Unicast MAC\n");
5322 /* Update the internal structure with this new mac address */
5323 do_s2io_copy_mac_addr(sp
, i
, mac_addr
);
5324 return (do_s2io_add_mac(sp
, mac_addr
, i
));
5328 * s2io_ethtool_sset - Sets different link parameters.
5329 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5330 * @info: pointer to the structure with parameters given by ethtool to set
5333 * The function sets different link parameters provided by the user onto
5339 static int s2io_ethtool_sset(struct net_device
*dev
,
5340 struct ethtool_cmd
*info
)
5342 struct s2io_nic
*sp
= dev
->priv
;
5343 if ((info
->autoneg
== AUTONEG_ENABLE
) ||
5344 (info
->speed
!= SPEED_10000
) || (info
->duplex
!= DUPLEX_FULL
))
5347 s2io_close(sp
->dev
);
5355 * s2io_ethtol_gset - Return link specific information.
5356 * @sp : private member of the device structure, pointer to the
5357 * s2io_nic structure.
5358 * @info : pointer to the structure with parameters given by ethtool
5359 * to return link information.
5361 * Returns link specific information like speed, duplex etc.. to ethtool.
5363 * return 0 on success.
5366 static int s2io_ethtool_gset(struct net_device
*dev
, struct ethtool_cmd
*info
)
5368 struct s2io_nic
*sp
= dev
->priv
;
5369 info
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
5370 info
->advertising
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
5371 info
->port
= PORT_FIBRE
;
5373 /* info->transceiver */
5374 info
->transceiver
= XCVR_EXTERNAL
;
5376 if (netif_carrier_ok(sp
->dev
)) {
5377 info
->speed
= 10000;
5378 info
->duplex
= DUPLEX_FULL
;
5384 info
->autoneg
= AUTONEG_DISABLE
;
5389 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5390 * @sp : private member of the device structure, which is a pointer to the
5391 * s2io_nic structure.
5392 * @info : pointer to the structure with parameters given by ethtool to
5393 * return driver information.
5395 * Returns driver specefic information like name, version etc.. to ethtool.
5400 static void s2io_ethtool_gdrvinfo(struct net_device
*dev
,
5401 struct ethtool_drvinfo
*info
)
5403 struct s2io_nic
*sp
= dev
->priv
;
5405 strncpy(info
->driver
, s2io_driver_name
, sizeof(info
->driver
));
5406 strncpy(info
->version
, s2io_driver_version
, sizeof(info
->version
));
5407 strncpy(info
->fw_version
, "", sizeof(info
->fw_version
));
5408 strncpy(info
->bus_info
, pci_name(sp
->pdev
), sizeof(info
->bus_info
));
5409 info
->regdump_len
= XENA_REG_SPACE
;
5410 info
->eedump_len
= XENA_EEPROM_SPACE
;
5414 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5415 * @sp: private member of the device structure, which is a pointer to the
5416 * s2io_nic structure.
5417 * @regs : pointer to the structure with parameters given by ethtool for
5418 * dumping the registers.
5419 * @reg_space: The input argumnet into which all the registers are dumped.
5421 * Dumps the entire register space of xFrame NIC into the user given
5427 static void s2io_ethtool_gregs(struct net_device
*dev
,
5428 struct ethtool_regs
*regs
, void *space
)
5432 u8
*reg_space
= (u8
*) space
;
5433 struct s2io_nic
*sp
= dev
->priv
;
5435 regs
->len
= XENA_REG_SPACE
;
5436 regs
->version
= sp
->pdev
->subsystem_device
;
5438 for (i
= 0; i
< regs
->len
; i
+= 8) {
5439 reg
= readq(sp
->bar0
+ i
);
5440 memcpy((reg_space
+ i
), ®
, 8);
5445 * s2io_phy_id - timer function that alternates adapter LED.
5446 * @data : address of the private member of the device structure, which
5447 * is a pointer to the s2io_nic structure, provided as an u32.
5448 * Description: This is actually the timer function that alternates the
5449 * adapter LED bit of the adapter control bit to set/reset every time on
5450 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5451 * once every second.
5453 static void s2io_phy_id(unsigned long data
)
5455 struct s2io_nic
*sp
= (struct s2io_nic
*) data
;
5456 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5460 subid
= sp
->pdev
->subsystem_device
;
5461 if ((sp
->device_type
== XFRAME_II_DEVICE
) ||
5462 ((subid
& 0xFF) >= 0x07)) {
5463 val64
= readq(&bar0
->gpio_control
);
5464 val64
^= GPIO_CTRL_GPIO_0
;
5465 writeq(val64
, &bar0
->gpio_control
);
5467 val64
= readq(&bar0
->adapter_control
);
5468 val64
^= ADAPTER_LED_ON
;
5469 writeq(val64
, &bar0
->adapter_control
);
5472 mod_timer(&sp
->id_timer
, jiffies
+ HZ
/ 2);
5476 * s2io_ethtool_idnic - To physically identify the nic on the system.
5477 * @sp : private member of the device structure, which is a pointer to the
5478 * s2io_nic structure.
5479 * @id : pointer to the structure with identification parameters given by
5481 * Description: Used to physically identify the NIC on the system.
5482 * The Link LED will blink for a time specified by the user for
5484 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5485 * identification is possible only if it's link is up.
5487 * int , returns 0 on success
5490 static int s2io_ethtool_idnic(struct net_device
*dev
, u32 data
)
5492 u64 val64
= 0, last_gpio_ctrl_val
;
5493 struct s2io_nic
*sp
= dev
->priv
;
5494 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5497 subid
= sp
->pdev
->subsystem_device
;
5498 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
5499 if ((sp
->device_type
== XFRAME_I_DEVICE
) &&
5500 ((subid
& 0xFF) < 0x07)) {
5501 val64
= readq(&bar0
->adapter_control
);
5502 if (!(val64
& ADAPTER_CNTL_EN
)) {
5504 "Adapter Link down, cannot blink LED\n");
5508 if (sp
->id_timer
.function
== NULL
) {
5509 init_timer(&sp
->id_timer
);
5510 sp
->id_timer
.function
= s2io_phy_id
;
5511 sp
->id_timer
.data
= (unsigned long) sp
;
5513 mod_timer(&sp
->id_timer
, jiffies
);
5515 msleep_interruptible(data
* HZ
);
5517 msleep_interruptible(MAX_FLICKER_TIME
);
5518 del_timer_sync(&sp
->id_timer
);
5520 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp
->device_type
, subid
)) {
5521 writeq(last_gpio_ctrl_val
, &bar0
->gpio_control
);
5522 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
5528 static void s2io_ethtool_gringparam(struct net_device
*dev
,
5529 struct ethtool_ringparam
*ering
)
5531 struct s2io_nic
*sp
= dev
->priv
;
5532 int i
,tx_desc_count
=0,rx_desc_count
=0;
5534 if (sp
->rxd_mode
== RXD_MODE_1
)
5535 ering
->rx_max_pending
= MAX_RX_DESC_1
;
5536 else if (sp
->rxd_mode
== RXD_MODE_3B
)
5537 ering
->rx_max_pending
= MAX_RX_DESC_2
;
5539 ering
->tx_max_pending
= MAX_TX_DESC
;
5540 for (i
= 0 ; i
< sp
->config
.tx_fifo_num
; i
++)
5541 tx_desc_count
+= sp
->config
.tx_cfg
[i
].fifo_len
;
5543 DBG_PRINT(INFO_DBG
,"\nmax txds : %d\n",sp
->config
.max_txds
);
5544 ering
->tx_pending
= tx_desc_count
;
5546 for (i
= 0 ; i
< sp
->config
.rx_ring_num
; i
++)
5547 rx_desc_count
+= sp
->config
.rx_cfg
[i
].num_rxd
;
5549 ering
->rx_pending
= rx_desc_count
;
5551 ering
->rx_mini_max_pending
= 0;
5552 ering
->rx_mini_pending
= 0;
5553 if(sp
->rxd_mode
== RXD_MODE_1
)
5554 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_1
;
5555 else if (sp
->rxd_mode
== RXD_MODE_3B
)
5556 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_2
;
5557 ering
->rx_jumbo_pending
= rx_desc_count
;
5561 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5562 * @sp : private member of the device structure, which is a pointer to the
5563 * s2io_nic structure.
5564 * @ep : pointer to the structure with pause parameters given by ethtool.
5566 * Returns the Pause frame generation and reception capability of the NIC.
5570 static void s2io_ethtool_getpause_data(struct net_device
*dev
,
5571 struct ethtool_pauseparam
*ep
)
5574 struct s2io_nic
*sp
= dev
->priv
;
5575 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5577 val64
= readq(&bar0
->rmac_pause_cfg
);
5578 if (val64
& RMAC_PAUSE_GEN_ENABLE
)
5579 ep
->tx_pause
= TRUE
;
5580 if (val64
& RMAC_PAUSE_RX_ENABLE
)
5581 ep
->rx_pause
= TRUE
;
5582 ep
->autoneg
= FALSE
;
5586 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5587 * @sp : private member of the device structure, which is a pointer to the
5588 * s2io_nic structure.
5589 * @ep : pointer to the structure with pause parameters given by ethtool.
5591 * It can be used to set or reset Pause frame generation or reception
5592 * support of the NIC.
5594 * int, returns 0 on Success
5597 static int s2io_ethtool_setpause_data(struct net_device
*dev
,
5598 struct ethtool_pauseparam
*ep
)
5601 struct s2io_nic
*sp
= dev
->priv
;
5602 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5604 val64
= readq(&bar0
->rmac_pause_cfg
);
5606 val64
|= RMAC_PAUSE_GEN_ENABLE
;
5608 val64
&= ~RMAC_PAUSE_GEN_ENABLE
;
5610 val64
|= RMAC_PAUSE_RX_ENABLE
;
5612 val64
&= ~RMAC_PAUSE_RX_ENABLE
;
5613 writeq(val64
, &bar0
->rmac_pause_cfg
);
5618 * read_eeprom - reads 4 bytes of data from user given offset.
5619 * @sp : private member of the device structure, which is a pointer to the
5620 * s2io_nic structure.
5621 * @off : offset at which the data must be written
5622 * @data : Its an output parameter where the data read at the given
5625 * Will read 4 bytes of data from the user given offset and return the
5627 * NOTE: Will allow to read only part of the EEPROM visible through the
5630 * -1 on failure and 0 on success.
5633 #define S2IO_DEV_ID 5
5634 static int read_eeprom(struct s2io_nic
* sp
, int off
, u64
* data
)
5639 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5641 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5642 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5643 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ
|
5644 I2C_CONTROL_CNTL_START
;
5645 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5647 while (exit_cnt
< 5) {
5648 val64
= readq(&bar0
->i2c_control
);
5649 if (I2C_CONTROL_CNTL_END(val64
)) {
5650 *data
= I2C_CONTROL_GET_DATA(val64
);
5659 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5660 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5661 SPI_CONTROL_BYTECNT(0x3) |
5662 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off
);
5663 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5664 val64
|= SPI_CONTROL_REQ
;
5665 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5666 while (exit_cnt
< 5) {
5667 val64
= readq(&bar0
->spi_control
);
5668 if (val64
& SPI_CONTROL_NACK
) {
5671 } else if (val64
& SPI_CONTROL_DONE
) {
5672 *data
= readq(&bar0
->spi_data
);
5685 * write_eeprom - actually writes the relevant part of the data value.
5686 * @sp : private member of the device structure, which is a pointer to the
5687 * s2io_nic structure.
5688 * @off : offset at which the data must be written
5689 * @data : The data that is to be written
5690 * @cnt : Number of bytes of the data that are actually to be written into
5691 * the Eeprom. (max of 3)
5693 * Actually writes the relevant part of the data value into the Eeprom
5694 * through the I2C bus.
5696 * 0 on success, -1 on failure.
5699 static int write_eeprom(struct s2io_nic
* sp
, int off
, u64 data
, int cnt
)
5701 int exit_cnt
= 0, ret
= -1;
5703 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5705 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5706 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5707 I2C_CONTROL_BYTE_CNT(cnt
) | I2C_CONTROL_SET_DATA((u32
)data
) |
5708 I2C_CONTROL_CNTL_START
;
5709 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5711 while (exit_cnt
< 5) {
5712 val64
= readq(&bar0
->i2c_control
);
5713 if (I2C_CONTROL_CNTL_END(val64
)) {
5714 if (!(val64
& I2C_CONTROL_NACK
))
5723 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5724 int write_cnt
= (cnt
== 8) ? 0 : cnt
;
5725 writeq(SPI_DATA_WRITE(data
,(cnt
<<3)), &bar0
->spi_data
);
5727 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5728 SPI_CONTROL_BYTECNT(write_cnt
) |
5729 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off
);
5730 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5731 val64
|= SPI_CONTROL_REQ
;
5732 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5733 while (exit_cnt
< 5) {
5734 val64
= readq(&bar0
->spi_control
);
5735 if (val64
& SPI_CONTROL_NACK
) {
5738 } else if (val64
& SPI_CONTROL_DONE
) {
5748 static void s2io_vpd_read(struct s2io_nic
*nic
)
5752 int i
=0, cnt
, fail
= 0;
5753 int vpd_addr
= 0x80;
5755 if (nic
->device_type
== XFRAME_II_DEVICE
) {
5756 strcpy(nic
->product_name
, "Xframe II 10GbE network adapter");
5760 strcpy(nic
->product_name
, "Xframe I 10GbE network adapter");
5763 strcpy(nic
->serial_num
, "NOT AVAILABLE");
5765 vpd_data
= kmalloc(256, GFP_KERNEL
);
5767 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
5770 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
+= 256;
5772 for (i
= 0; i
< 256; i
+=4 ) {
5773 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 2), i
);
5774 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 2), &data
);
5775 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 3), 0);
5776 for (cnt
= 0; cnt
<5; cnt
++) {
5778 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 3), &data
);
5783 DBG_PRINT(ERR_DBG
, "Read of VPD data failed\n");
5787 pci_read_config_dword(nic
->pdev
, (vpd_addr
+ 4),
5788 (u32
*)&vpd_data
[i
]);
5792 /* read serial number of adapter */
5793 for (cnt
= 0; cnt
< 256; cnt
++) {
5794 if ((vpd_data
[cnt
] == 'S') &&
5795 (vpd_data
[cnt
+1] == 'N') &&
5796 (vpd_data
[cnt
+2] < VPD_STRING_LEN
)) {
5797 memset(nic
->serial_num
, 0, VPD_STRING_LEN
);
5798 memcpy(nic
->serial_num
, &vpd_data
[cnt
+ 3],
5805 if ((!fail
) && (vpd_data
[1] < VPD_STRING_LEN
)) {
5806 memset(nic
->product_name
, 0, vpd_data
[1]);
5807 memcpy(nic
->product_name
, &vpd_data
[3], vpd_data
[1]);
5810 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= 256;
5814 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5815 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5816 * @eeprom : pointer to the user level structure provided by ethtool,
5817 * containing all relevant information.
5818 * @data_buf : user defined value to be written into Eeprom.
5819 * Description: Reads the values stored in the Eeprom at given offset
5820 * for a given length. Stores these values int the input argument data
5821 * buffer 'data_buf' and returns these to the caller (ethtool.)
5826 static int s2io_ethtool_geeprom(struct net_device
*dev
,
5827 struct ethtool_eeprom
*eeprom
, u8
* data_buf
)
5831 struct s2io_nic
*sp
= dev
->priv
;
5833 eeprom
->magic
= sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16);
5835 if ((eeprom
->offset
+ eeprom
->len
) > (XENA_EEPROM_SPACE
))
5836 eeprom
->len
= XENA_EEPROM_SPACE
- eeprom
->offset
;
5838 for (i
= 0; i
< eeprom
->len
; i
+= 4) {
5839 if (read_eeprom(sp
, (eeprom
->offset
+ i
), &data
)) {
5840 DBG_PRINT(ERR_DBG
, "Read of EEPROM failed\n");
5844 memcpy((data_buf
+ i
), &valid
, 4);
5850 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5851 * @sp : private member of the device structure, which is a pointer to the
5852 * s2io_nic structure.
5853 * @eeprom : pointer to the user level structure provided by ethtool,
5854 * containing all relevant information.
5855 * @data_buf ; user defined value to be written into Eeprom.
5857 * Tries to write the user provided value in the Eeprom, at the offset
5858 * given by the user.
5860 * 0 on success, -EFAULT on failure.
5863 static int s2io_ethtool_seeprom(struct net_device
*dev
,
5864 struct ethtool_eeprom
*eeprom
,
5867 int len
= eeprom
->len
, cnt
= 0;
5868 u64 valid
= 0, data
;
5869 struct s2io_nic
*sp
= dev
->priv
;
5871 if (eeprom
->magic
!= (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16))) {
5873 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5874 DBG_PRINT(ERR_DBG
, "is wrong, Its not 0x%x\n",
5880 data
= (u32
) data_buf
[cnt
] & 0x000000FF;
5882 valid
= (u32
) (data
<< 24);
5886 if (write_eeprom(sp
, (eeprom
->offset
+ cnt
), valid
, 0)) {
5888 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5890 "write into the specified offset\n");
5901 * s2io_register_test - reads and writes into all clock domains.
5902 * @sp : private member of the device structure, which is a pointer to the
5903 * s2io_nic structure.
5904 * @data : variable that returns the result of each of the test conducted b
5907 * Read and write into all clock domains. The NIC has 3 clock domains,
5908 * see that registers in all the three regions are accessible.
5913 static int s2io_register_test(struct s2io_nic
* sp
, uint64_t * data
)
5915 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5916 u64 val64
= 0, exp_val
;
5919 val64
= readq(&bar0
->pif_rd_swapper_fb
);
5920 if (val64
!= 0x123456789abcdefULL
) {
5922 DBG_PRINT(INFO_DBG
, "Read Test level 1 fails\n");
5925 val64
= readq(&bar0
->rmac_pause_cfg
);
5926 if (val64
!= 0xc000ffff00000000ULL
) {
5928 DBG_PRINT(INFO_DBG
, "Read Test level 2 fails\n");
5931 val64
= readq(&bar0
->rx_queue_cfg
);
5932 if (sp
->device_type
== XFRAME_II_DEVICE
)
5933 exp_val
= 0x0404040404040404ULL
;
5935 exp_val
= 0x0808080808080808ULL
;
5936 if (val64
!= exp_val
) {
5938 DBG_PRINT(INFO_DBG
, "Read Test level 3 fails\n");
5941 val64
= readq(&bar0
->xgxs_efifo_cfg
);
5942 if (val64
!= 0x000000001923141EULL
) {
5944 DBG_PRINT(INFO_DBG
, "Read Test level 4 fails\n");
5947 val64
= 0x5A5A5A5A5A5A5A5AULL
;
5948 writeq(val64
, &bar0
->xmsi_data
);
5949 val64
= readq(&bar0
->xmsi_data
);
5950 if (val64
!= 0x5A5A5A5A5A5A5A5AULL
) {
5952 DBG_PRINT(ERR_DBG
, "Write Test level 1 fails\n");
5955 val64
= 0xA5A5A5A5A5A5A5A5ULL
;
5956 writeq(val64
, &bar0
->xmsi_data
);
5957 val64
= readq(&bar0
->xmsi_data
);
5958 if (val64
!= 0xA5A5A5A5A5A5A5A5ULL
) {
5960 DBG_PRINT(ERR_DBG
, "Write Test level 2 fails\n");
5968 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5969 * @sp : private member of the device structure, which is a pointer to the
5970 * s2io_nic structure.
5971 * @data:variable that returns the result of each of the test conducted by
5974 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5980 static int s2io_eeprom_test(struct s2io_nic
* sp
, uint64_t * data
)
5983 u64 ret_data
, org_4F0
, org_7F0
;
5984 u8 saved_4F0
= 0, saved_7F0
= 0;
5985 struct net_device
*dev
= sp
->dev
;
5987 /* Test Write Error at offset 0 */
5988 /* Note that SPI interface allows write access to all areas
5989 * of EEPROM. Hence doing all negative testing only for Xframe I.
5991 if (sp
->device_type
== XFRAME_I_DEVICE
)
5992 if (!write_eeprom(sp
, 0, 0, 3))
5995 /* Save current values at offsets 0x4F0 and 0x7F0 */
5996 if (!read_eeprom(sp
, 0x4F0, &org_4F0
))
5998 if (!read_eeprom(sp
, 0x7F0, &org_7F0
))
6001 /* Test Write at offset 4f0 */
6002 if (write_eeprom(sp
, 0x4F0, 0x012345, 3))
6004 if (read_eeprom(sp
, 0x4F0, &ret_data
))
6007 if (ret_data
!= 0x012345) {
6008 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x4F0. "
6009 "Data written %llx Data read %llx\n",
6010 dev
->name
, (unsigned long long)0x12345,
6011 (unsigned long long)ret_data
);
6015 /* Reset the EEPROM data go FFFF */
6016 write_eeprom(sp
, 0x4F0, 0xFFFFFF, 3);
6018 /* Test Write Request Error at offset 0x7c */
6019 if (sp
->device_type
== XFRAME_I_DEVICE
)
6020 if (!write_eeprom(sp
, 0x07C, 0, 3))
6023 /* Test Write Request at offset 0x7f0 */
6024 if (write_eeprom(sp
, 0x7F0, 0x012345, 3))
6026 if (read_eeprom(sp
, 0x7F0, &ret_data
))
6029 if (ret_data
!= 0x012345) {
6030 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x7F0. "
6031 "Data written %llx Data read %llx\n",
6032 dev
->name
, (unsigned long long)0x12345,
6033 (unsigned long long)ret_data
);
6037 /* Reset the EEPROM data go FFFF */
6038 write_eeprom(sp
, 0x7F0, 0xFFFFFF, 3);
6040 if (sp
->device_type
== XFRAME_I_DEVICE
) {
6041 /* Test Write Error at offset 0x80 */
6042 if (!write_eeprom(sp
, 0x080, 0, 3))
6045 /* Test Write Error at offset 0xfc */
6046 if (!write_eeprom(sp
, 0x0FC, 0, 3))
6049 /* Test Write Error at offset 0x100 */
6050 if (!write_eeprom(sp
, 0x100, 0, 3))
6053 /* Test Write Error at offset 4ec */
6054 if (!write_eeprom(sp
, 0x4EC, 0, 3))
6058 /* Restore values at offsets 0x4F0 and 0x7F0 */
6060 write_eeprom(sp
, 0x4F0, org_4F0
, 3);
6062 write_eeprom(sp
, 0x7F0, org_7F0
, 3);
6069 * s2io_bist_test - invokes the MemBist test of the card .
6070 * @sp : private member of the device structure, which is a pointer to the
6071 * s2io_nic structure.
6072 * @data:variable that returns the result of each of the test conducted by
6075 * This invokes the MemBist test of the card. We give around
6076 * 2 secs time for the Test to complete. If it's still not complete
6077 * within this peiod, we consider that the test failed.
6079 * 0 on success and -1 on failure.
6082 static int s2io_bist_test(struct s2io_nic
* sp
, uint64_t * data
)
6085 int cnt
= 0, ret
= -1;
6087 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
6088 bist
|= PCI_BIST_START
;
6089 pci_write_config_word(sp
->pdev
, PCI_BIST
, bist
);
6092 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
6093 if (!(bist
& PCI_BIST_START
)) {
6094 *data
= (bist
& PCI_BIST_CODE_MASK
);
6106 * s2io-link_test - verifies the link state of the nic
6107 * @sp ; private member of the device structure, which is a pointer to the
6108 * s2io_nic structure.
6109 * @data: variable that returns the result of each of the test conducted by
6112 * The function verifies the link state of the NIC and updates the input
6113 * argument 'data' appropriately.
6118 static int s2io_link_test(struct s2io_nic
* sp
, uint64_t * data
)
6120 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6123 val64
= readq(&bar0
->adapter_status
);
6124 if(!(LINK_IS_UP(val64
)))
6133 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6134 * @sp - private member of the device structure, which is a pointer to the
6135 * s2io_nic structure.
6136 * @data - variable that returns the result of each of the test
6137 * conducted by the driver.
6139 * This is one of the offline test that tests the read and write
6140 * access to the RldRam chip on the NIC.
6145 static int s2io_rldram_test(struct s2io_nic
* sp
, uint64_t * data
)
6147 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6149 int cnt
, iteration
= 0, test_fail
= 0;
6151 val64
= readq(&bar0
->adapter_control
);
6152 val64
&= ~ADAPTER_ECC_EN
;
6153 writeq(val64
, &bar0
->adapter_control
);
6155 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6156 val64
|= MC_RLDRAM_TEST_MODE
;
6157 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
6159 val64
= readq(&bar0
->mc_rldram_mrs
);
6160 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
;
6161 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
6163 val64
|= MC_RLDRAM_MRS_ENABLE
;
6164 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
6166 while (iteration
< 2) {
6167 val64
= 0x55555555aaaa0000ULL
;
6168 if (iteration
== 1) {
6169 val64
^= 0xFFFFFFFFFFFF0000ULL
;
6171 writeq(val64
, &bar0
->mc_rldram_test_d0
);
6173 val64
= 0xaaaa5a5555550000ULL
;
6174 if (iteration
== 1) {
6175 val64
^= 0xFFFFFFFFFFFF0000ULL
;
6177 writeq(val64
, &bar0
->mc_rldram_test_d1
);
6179 val64
= 0x55aaaaaaaa5a0000ULL
;
6180 if (iteration
== 1) {
6181 val64
^= 0xFFFFFFFFFFFF0000ULL
;
6183 writeq(val64
, &bar0
->mc_rldram_test_d2
);
6185 val64
= (u64
) (0x0000003ffffe0100ULL
);
6186 writeq(val64
, &bar0
->mc_rldram_test_add
);
6188 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_WRITE
|
6190 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
6192 for (cnt
= 0; cnt
< 5; cnt
++) {
6193 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6194 if (val64
& MC_RLDRAM_TEST_DONE
)
6202 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_GO
;
6203 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
6205 for (cnt
= 0; cnt
< 5; cnt
++) {
6206 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6207 if (val64
& MC_RLDRAM_TEST_DONE
)
6215 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6216 if (!(val64
& MC_RLDRAM_TEST_PASS
))
6224 /* Bring the adapter out of test mode */
6225 SPECIAL_REG_WRITE(0, &bar0
->mc_rldram_test_ctrl
, LF
);
6231 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6232 * @sp : private member of the device structure, which is a pointer to the
6233 * s2io_nic structure.
6234 * @ethtest : pointer to a ethtool command specific structure that will be
6235 * returned to the user.
6236 * @data : variable that returns the result of each of the test
6237 * conducted by the driver.
6239 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6240 * the health of the card.
6245 static void s2io_ethtool_test(struct net_device
*dev
,
6246 struct ethtool_test
*ethtest
,
6249 struct s2io_nic
*sp
= dev
->priv
;
6250 int orig_state
= netif_running(sp
->dev
);
6252 if (ethtest
->flags
== ETH_TEST_FL_OFFLINE
) {
6253 /* Offline Tests. */
6255 s2io_close(sp
->dev
);
6257 if (s2io_register_test(sp
, &data
[0]))
6258 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6262 if (s2io_rldram_test(sp
, &data
[3]))
6263 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6267 if (s2io_eeprom_test(sp
, &data
[1]))
6268 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6270 if (s2io_bist_test(sp
, &data
[4]))
6271 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6281 "%s: is not up, cannot run test\n",
6290 if (s2io_link_test(sp
, &data
[2]))
6291 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6300 static void s2io_get_ethtool_stats(struct net_device
*dev
,
6301 struct ethtool_stats
*estats
,
6305 struct s2io_nic
*sp
= dev
->priv
;
6306 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
6308 s2io_updt_stats(sp
);
6310 (u64
)le32_to_cpu(stat_info
->tmac_frms_oflow
) << 32 |
6311 le32_to_cpu(stat_info
->tmac_frms
);
6313 (u64
)le32_to_cpu(stat_info
->tmac_data_octets_oflow
) << 32 |
6314 le32_to_cpu(stat_info
->tmac_data_octets
);
6315 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_drop_frms
);
6317 (u64
)le32_to_cpu(stat_info
->tmac_mcst_frms_oflow
) << 32 |
6318 le32_to_cpu(stat_info
->tmac_mcst_frms
);
6320 (u64
)le32_to_cpu(stat_info
->tmac_bcst_frms_oflow
) << 32 |
6321 le32_to_cpu(stat_info
->tmac_bcst_frms
);
6322 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_pause_ctrl_frms
);
6324 (u64
)le32_to_cpu(stat_info
->tmac_ttl_octets_oflow
) << 32 |
6325 le32_to_cpu(stat_info
->tmac_ttl_octets
);
6327 (u64
)le32_to_cpu(stat_info
->tmac_ucst_frms_oflow
) << 32 |
6328 le32_to_cpu(stat_info
->tmac_ucst_frms
);
6330 (u64
)le32_to_cpu(stat_info
->tmac_nucst_frms_oflow
) << 32 |
6331 le32_to_cpu(stat_info
->tmac_nucst_frms
);
6333 (u64
)le32_to_cpu(stat_info
->tmac_any_err_frms_oflow
) << 32 |
6334 le32_to_cpu(stat_info
->tmac_any_err_frms
);
6335 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_ttl_less_fb_octets
);
6336 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_vld_ip_octets
);
6338 (u64
)le32_to_cpu(stat_info
->tmac_vld_ip_oflow
) << 32 |
6339 le32_to_cpu(stat_info
->tmac_vld_ip
);
6341 (u64
)le32_to_cpu(stat_info
->tmac_drop_ip_oflow
) << 32 |
6342 le32_to_cpu(stat_info
->tmac_drop_ip
);
6344 (u64
)le32_to_cpu(stat_info
->tmac_icmp_oflow
) << 32 |
6345 le32_to_cpu(stat_info
->tmac_icmp
);
6347 (u64
)le32_to_cpu(stat_info
->tmac_rst_tcp_oflow
) << 32 |
6348 le32_to_cpu(stat_info
->tmac_rst_tcp
);
6349 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_tcp
);
6350 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->tmac_udp_oflow
) << 32 |
6351 le32_to_cpu(stat_info
->tmac_udp
);
6353 (u64
)le32_to_cpu(stat_info
->rmac_vld_frms_oflow
) << 32 |
6354 le32_to_cpu(stat_info
->rmac_vld_frms
);
6356 (u64
)le32_to_cpu(stat_info
->rmac_data_octets_oflow
) << 32 |
6357 le32_to_cpu(stat_info
->rmac_data_octets
);
6358 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_fcs_err_frms
);
6359 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_drop_frms
);
6361 (u64
)le32_to_cpu(stat_info
->rmac_vld_mcst_frms_oflow
) << 32 |
6362 le32_to_cpu(stat_info
->rmac_vld_mcst_frms
);
6364 (u64
)le32_to_cpu(stat_info
->rmac_vld_bcst_frms_oflow
) << 32 |
6365 le32_to_cpu(stat_info
->rmac_vld_bcst_frms
);
6366 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_in_rng_len_err_frms
);
6367 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_out_rng_len_err_frms
);
6368 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_long_frms
);
6369 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_pause_ctrl_frms
);
6370 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_unsup_ctrl_frms
);
6372 (u64
)le32_to_cpu(stat_info
->rmac_ttl_octets_oflow
) << 32 |
6373 le32_to_cpu(stat_info
->rmac_ttl_octets
);
6375 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ucst_frms_oflow
)
6376 << 32 | le32_to_cpu(stat_info
->rmac_accepted_ucst_frms
);
6378 (u64
)le32_to_cpu(stat_info
->rmac_accepted_nucst_frms_oflow
)
6379 << 32 | le32_to_cpu(stat_info
->rmac_accepted_nucst_frms
);
6381 (u64
)le32_to_cpu(stat_info
->rmac_discarded_frms_oflow
) << 32 |
6382 le32_to_cpu(stat_info
->rmac_discarded_frms
);
6384 (u64
)le32_to_cpu(stat_info
->rmac_drop_events_oflow
)
6385 << 32 | le32_to_cpu(stat_info
->rmac_drop_events
);
6386 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_less_fb_octets
);
6387 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_frms
);
6389 (u64
)le32_to_cpu(stat_info
->rmac_usized_frms_oflow
) << 32 |
6390 le32_to_cpu(stat_info
->rmac_usized_frms
);
6392 (u64
)le32_to_cpu(stat_info
->rmac_osized_frms_oflow
) << 32 |
6393 le32_to_cpu(stat_info
->rmac_osized_frms
);
6395 (u64
)le32_to_cpu(stat_info
->rmac_frag_frms_oflow
) << 32 |
6396 le32_to_cpu(stat_info
->rmac_frag_frms
);
6398 (u64
)le32_to_cpu(stat_info
->rmac_jabber_frms_oflow
) << 32 |
6399 le32_to_cpu(stat_info
->rmac_jabber_frms
);
6400 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_64_frms
);
6401 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_65_127_frms
);
6402 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_128_255_frms
);
6403 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_256_511_frms
);
6404 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_512_1023_frms
);
6405 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_1024_1518_frms
);
6407 (u64
)le32_to_cpu(stat_info
->rmac_ip_oflow
) << 32 |
6408 le32_to_cpu(stat_info
->rmac_ip
);
6409 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ip_octets
);
6410 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_hdr_err_ip
);
6412 (u64
)le32_to_cpu(stat_info
->rmac_drop_ip_oflow
) << 32 |
6413 le32_to_cpu(stat_info
->rmac_drop_ip
);
6415 (u64
)le32_to_cpu(stat_info
->rmac_icmp_oflow
) << 32 |
6416 le32_to_cpu(stat_info
->rmac_icmp
);
6417 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_tcp
);
6419 (u64
)le32_to_cpu(stat_info
->rmac_udp_oflow
) << 32 |
6420 le32_to_cpu(stat_info
->rmac_udp
);
6422 (u64
)le32_to_cpu(stat_info
->rmac_err_drp_udp_oflow
) << 32 |
6423 le32_to_cpu(stat_info
->rmac_err_drp_udp
);
6424 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_err_sym
);
6425 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q0
);
6426 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q1
);
6427 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q2
);
6428 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q3
);
6429 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q4
);
6430 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q5
);
6431 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q6
);
6432 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q7
);
6433 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q0
);
6434 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q1
);
6435 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q2
);
6436 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q3
);
6437 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q4
);
6438 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q5
);
6439 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q6
);
6440 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q7
);
6442 (u64
)le32_to_cpu(stat_info
->rmac_pause_cnt_oflow
) << 32 |
6443 le32_to_cpu(stat_info
->rmac_pause_cnt
);
6444 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_data_err_cnt
);
6445 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_ctrl_err_cnt
);
6447 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ip_oflow
) << 32 |
6448 le32_to_cpu(stat_info
->rmac_accepted_ip
);
6449 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_err_tcp
);
6450 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_req_cnt
);
6451 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_cnt
);
6452 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_rtry_cnt
);
6453 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_cnt
);
6454 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_rd_ack_cnt
);
6455 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_req_cnt
);
6456 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_cnt
);
6457 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_rtry_cnt
);
6458 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_cnt
);
6459 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_disc_cnt
);
6460 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_wr_ack_cnt
);
6461 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txp_wr_cnt
);
6462 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_rd_cnt
);
6463 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_wr_cnt
);
6464 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_rd_cnt
);
6465 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_wr_cnt
);
6466 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txf_rd_cnt
);
6467 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxf_wr_cnt
);
6469 /* Enhanced statistics exist only for Hercules */
6470 if(sp
->device_type
== XFRAME_II_DEVICE
) {
6472 le64_to_cpu(stat_info
->rmac_ttl_1519_4095_frms
);
6474 le64_to_cpu(stat_info
->rmac_ttl_4096_8191_frms
);
6476 le64_to_cpu(stat_info
->rmac_ttl_8192_max_frms
);
6477 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_gt_max_frms
);
6478 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_osized_alt_frms
);
6479 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_jabber_alt_frms
);
6480 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_gt_max_alt_frms
);
6481 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_vlan_frms
);
6482 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_len_discard
);
6483 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_fcs_discard
);
6484 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_pf_discard
);
6485 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_da_discard
);
6486 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_red_discard
);
6487 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_rts_discard
);
6488 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_ingm_full_discard
);
6489 tmp_stats
[i
++] = le32_to_cpu(stat_info
->link_fault_cnt
);
6493 tmp_stats
[i
++] = stat_info
->sw_stat
.single_ecc_errs
;
6494 tmp_stats
[i
++] = stat_info
->sw_stat
.double_ecc_errs
;
6495 tmp_stats
[i
++] = stat_info
->sw_stat
.parity_err_cnt
;
6496 tmp_stats
[i
++] = stat_info
->sw_stat
.serious_err_cnt
;
6497 tmp_stats
[i
++] = stat_info
->sw_stat
.soft_reset_cnt
;
6498 tmp_stats
[i
++] = stat_info
->sw_stat
.fifo_full_cnt
;
6499 for (k
= 0; k
< MAX_RX_RINGS
; k
++)
6500 tmp_stats
[i
++] = stat_info
->sw_stat
.ring_full_cnt
[k
];
6501 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_high
;
6502 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_low
;
6503 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_high
;
6504 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_low
;
6505 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_high
;
6506 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_low
;
6507 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_high
;
6508 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_low
;
6509 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_high
;
6510 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_low
;
6511 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_high
;
6512 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_low
;
6513 tmp_stats
[i
++] = stat_info
->sw_stat
.clubbed_frms_cnt
;
6514 tmp_stats
[i
++] = stat_info
->sw_stat
.sending_both
;
6515 tmp_stats
[i
++] = stat_info
->sw_stat
.outof_sequence_pkts
;
6516 tmp_stats
[i
++] = stat_info
->sw_stat
.flush_max_pkts
;
6517 if (stat_info
->sw_stat
.num_aggregations
) {
6518 u64 tmp
= stat_info
->sw_stat
.sum_avg_pkts_aggregated
;
6521 * Since 64-bit divide does not work on all platforms,
6522 * do repeated subtraction.
6524 while (tmp
>= stat_info
->sw_stat
.num_aggregations
) {
6525 tmp
-= stat_info
->sw_stat
.num_aggregations
;
6528 tmp_stats
[i
++] = count
;
6532 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_alloc_fail_cnt
;
6533 tmp_stats
[i
++] = stat_info
->sw_stat
.pci_map_fail_cnt
;
6534 tmp_stats
[i
++] = stat_info
->sw_stat
.watchdog_timer_cnt
;
6535 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_allocated
;
6536 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_freed
;
6537 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_cnt
;
6538 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_cnt
;
6539 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_time
;
6540 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_time
;
6542 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_buf_abort_cnt
;
6543 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_desc_abort_cnt
;
6544 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_parity_err_cnt
;
6545 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_link_loss_cnt
;
6546 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_list_proc_err_cnt
;
6548 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_err_cnt
;
6549 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_abort_cnt
;
6550 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_abort_cnt
;
6551 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rda_fail_cnt
;
6552 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_prot_cnt
;
6553 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_fcs_err_cnt
;
6554 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_buf_size_err_cnt
;
6555 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rxd_corrupt_cnt
;
6556 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_err_cnt
;
6557 tmp_stats
[i
++] = stat_info
->sw_stat
.tda_err_cnt
;
6558 tmp_stats
[i
++] = stat_info
->sw_stat
.pfc_err_cnt
;
6559 tmp_stats
[i
++] = stat_info
->sw_stat
.pcc_err_cnt
;
6560 tmp_stats
[i
++] = stat_info
->sw_stat
.tti_err_cnt
;
6561 tmp_stats
[i
++] = stat_info
->sw_stat
.tpa_err_cnt
;
6562 tmp_stats
[i
++] = stat_info
->sw_stat
.sm_err_cnt
;
6563 tmp_stats
[i
++] = stat_info
->sw_stat
.lso_err_cnt
;
6564 tmp_stats
[i
++] = stat_info
->sw_stat
.mac_tmac_err_cnt
;
6565 tmp_stats
[i
++] = stat_info
->sw_stat
.mac_rmac_err_cnt
;
6566 tmp_stats
[i
++] = stat_info
->sw_stat
.xgxs_txgxs_err_cnt
;
6567 tmp_stats
[i
++] = stat_info
->sw_stat
.xgxs_rxgxs_err_cnt
;
6568 tmp_stats
[i
++] = stat_info
->sw_stat
.rc_err_cnt
;
6569 tmp_stats
[i
++] = stat_info
->sw_stat
.prc_pcix_err_cnt
;
6570 tmp_stats
[i
++] = stat_info
->sw_stat
.rpa_err_cnt
;
6571 tmp_stats
[i
++] = stat_info
->sw_stat
.rda_err_cnt
;
6572 tmp_stats
[i
++] = stat_info
->sw_stat
.rti_err_cnt
;
6573 tmp_stats
[i
++] = stat_info
->sw_stat
.mc_err_cnt
;
6576 static int s2io_ethtool_get_regs_len(struct net_device
*dev
)
6578 return (XENA_REG_SPACE
);
6582 static u32
s2io_ethtool_get_rx_csum(struct net_device
* dev
)
6584 struct s2io_nic
*sp
= dev
->priv
;
6586 return (sp
->rx_csum
);
6589 static int s2io_ethtool_set_rx_csum(struct net_device
*dev
, u32 data
)
6591 struct s2io_nic
*sp
= dev
->priv
;
6601 static int s2io_get_eeprom_len(struct net_device
*dev
)
6603 return (XENA_EEPROM_SPACE
);
6606 static int s2io_get_sset_count(struct net_device
*dev
, int sset
)
6608 struct s2io_nic
*sp
= dev
->priv
;
6612 return S2IO_TEST_LEN
;
6614 switch(sp
->device_type
) {
6615 case XFRAME_I_DEVICE
:
6616 return XFRAME_I_STAT_LEN
;
6617 case XFRAME_II_DEVICE
:
6618 return XFRAME_II_STAT_LEN
;
6627 static void s2io_ethtool_get_strings(struct net_device
*dev
,
6628 u32 stringset
, u8
* data
)
6631 struct s2io_nic
*sp
= dev
->priv
;
6633 switch (stringset
) {
6635 memcpy(data
, s2io_gstrings
, S2IO_STRINGS_LEN
);
6638 stat_size
= sizeof(ethtool_xena_stats_keys
);
6639 memcpy(data
, ðtool_xena_stats_keys
,stat_size
);
6640 if(sp
->device_type
== XFRAME_II_DEVICE
) {
6641 memcpy(data
+ stat_size
,
6642 ðtool_enhanced_stats_keys
,
6643 sizeof(ethtool_enhanced_stats_keys
));
6644 stat_size
+= sizeof(ethtool_enhanced_stats_keys
);
6647 memcpy(data
+ stat_size
, ðtool_driver_stats_keys
,
6648 sizeof(ethtool_driver_stats_keys
));
6652 static int s2io_ethtool_op_set_tx_csum(struct net_device
*dev
, u32 data
)
6655 dev
->features
|= NETIF_F_IP_CSUM
;
6657 dev
->features
&= ~NETIF_F_IP_CSUM
;
6662 static u32
s2io_ethtool_op_get_tso(struct net_device
*dev
)
6664 return (dev
->features
& NETIF_F_TSO
) != 0;
6666 static int s2io_ethtool_op_set_tso(struct net_device
*dev
, u32 data
)
6669 dev
->features
|= (NETIF_F_TSO
| NETIF_F_TSO6
);
6671 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
);
6676 static const struct ethtool_ops netdev_ethtool_ops
= {
6677 .get_settings
= s2io_ethtool_gset
,
6678 .set_settings
= s2io_ethtool_sset
,
6679 .get_drvinfo
= s2io_ethtool_gdrvinfo
,
6680 .get_regs_len
= s2io_ethtool_get_regs_len
,
6681 .get_regs
= s2io_ethtool_gregs
,
6682 .get_link
= ethtool_op_get_link
,
6683 .get_eeprom_len
= s2io_get_eeprom_len
,
6684 .get_eeprom
= s2io_ethtool_geeprom
,
6685 .set_eeprom
= s2io_ethtool_seeprom
,
6686 .get_ringparam
= s2io_ethtool_gringparam
,
6687 .get_pauseparam
= s2io_ethtool_getpause_data
,
6688 .set_pauseparam
= s2io_ethtool_setpause_data
,
6689 .get_rx_csum
= s2io_ethtool_get_rx_csum
,
6690 .set_rx_csum
= s2io_ethtool_set_rx_csum
,
6691 .set_tx_csum
= s2io_ethtool_op_set_tx_csum
,
6692 .set_sg
= ethtool_op_set_sg
,
6693 .get_tso
= s2io_ethtool_op_get_tso
,
6694 .set_tso
= s2io_ethtool_op_set_tso
,
6695 .set_ufo
= ethtool_op_set_ufo
,
6696 .self_test
= s2io_ethtool_test
,
6697 .get_strings
= s2io_ethtool_get_strings
,
6698 .phys_id
= s2io_ethtool_idnic
,
6699 .get_ethtool_stats
= s2io_get_ethtool_stats
,
6700 .get_sset_count
= s2io_get_sset_count
,
6704 * s2io_ioctl - Entry point for the Ioctl
6705 * @dev : Device pointer.
6706 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6707 * a proprietary structure used to pass information to the driver.
6708 * @cmd : This is used to distinguish between the different commands that
6709 * can be passed to the IOCTL functions.
6711 * Currently there are no special functionality supported in IOCTL, hence
6712 * function always return EOPNOTSUPPORTED
6715 static int s2io_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
6721 * s2io_change_mtu - entry point to change MTU size for the device.
6722 * @dev : device pointer.
6723 * @new_mtu : the new MTU size for the device.
6724 * Description: A driver entry point to change MTU size for the device.
6725 * Before changing the MTU the device must be stopped.
6727 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6731 static int s2io_change_mtu(struct net_device
*dev
, int new_mtu
)
6733 struct s2io_nic
*sp
= dev
->priv
;
6736 if ((new_mtu
< MIN_MTU
) || (new_mtu
> S2IO_JUMBO_SIZE
)) {
6737 DBG_PRINT(ERR_DBG
, "%s: MTU size is invalid.\n",
6743 if (netif_running(dev
)) {
6744 s2io_stop_all_tx_queue(sp
);
6746 ret
= s2io_card_up(sp
);
6748 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6752 s2io_wake_all_tx_queue(sp
);
6753 } else { /* Device is down */
6754 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6755 u64 val64
= new_mtu
;
6757 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
6764 * s2io_set_link - Set the LInk status
6765 * @data: long pointer to device private structue
6766 * Description: Sets the link status for the adapter
6769 static void s2io_set_link(struct work_struct
*work
)
6771 struct s2io_nic
*nic
= container_of(work
, struct s2io_nic
, set_link_task
);
6772 struct net_device
*dev
= nic
->dev
;
6773 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
6779 if (!netif_running(dev
))
6782 if (test_and_set_bit(__S2IO_STATE_LINK_TASK
, &(nic
->state
))) {
6783 /* The card is being reset, no point doing anything */
6787 subid
= nic
->pdev
->subsystem_device
;
6788 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
6790 * Allow a small delay for the NICs self initiated
6791 * cleanup to complete.
6796 val64
= readq(&bar0
->adapter_status
);
6797 if (LINK_IS_UP(val64
)) {
6798 if (!(readq(&bar0
->adapter_control
) & ADAPTER_CNTL_EN
)) {
6799 if (verify_xena_quiescence(nic
)) {
6800 val64
= readq(&bar0
->adapter_control
);
6801 val64
|= ADAPTER_CNTL_EN
;
6802 writeq(val64
, &bar0
->adapter_control
);
6803 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6804 nic
->device_type
, subid
)) {
6805 val64
= readq(&bar0
->gpio_control
);
6806 val64
|= GPIO_CTRL_GPIO_0
;
6807 writeq(val64
, &bar0
->gpio_control
);
6808 val64
= readq(&bar0
->gpio_control
);
6810 val64
|= ADAPTER_LED_ON
;
6811 writeq(val64
, &bar0
->adapter_control
);
6813 nic
->device_enabled_once
= TRUE
;
6815 DBG_PRINT(ERR_DBG
, "%s: Error: ", dev
->name
);
6816 DBG_PRINT(ERR_DBG
, "device is not Quiescent\n");
6817 s2io_stop_all_tx_queue(nic
);
6820 val64
= readq(&bar0
->adapter_control
);
6821 val64
|= ADAPTER_LED_ON
;
6822 writeq(val64
, &bar0
->adapter_control
);
6823 s2io_link(nic
, LINK_UP
);
6825 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic
->device_type
,
6827 val64
= readq(&bar0
->gpio_control
);
6828 val64
&= ~GPIO_CTRL_GPIO_0
;
6829 writeq(val64
, &bar0
->gpio_control
);
6830 val64
= readq(&bar0
->gpio_control
);
6833 val64
= readq(&bar0
->adapter_control
);
6834 val64
= val64
&(~ADAPTER_LED_ON
);
6835 writeq(val64
, &bar0
->adapter_control
);
6836 s2io_link(nic
, LINK_DOWN
);
6838 clear_bit(__S2IO_STATE_LINK_TASK
, &(nic
->state
));
6844 static int set_rxd_buffer_pointer(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6846 struct sk_buff
**skb
, u64
*temp0
, u64
*temp1
,
6847 u64
*temp2
, int size
)
6849 struct net_device
*dev
= sp
->dev
;
6850 struct swStat
*stats
= &sp
->mac_control
.stats_info
->sw_stat
;
6852 if ((sp
->rxd_mode
== RXD_MODE_1
) && (rxdp
->Host_Control
== 0)) {
6853 struct RxD1
*rxdp1
= (struct RxD1
*)rxdp
;
6856 DBG_PRINT(INFO_DBG
, "SKB is not NULL\n");
6858 * As Rx frame are not going to be processed,
6859 * using same mapped address for the Rxd
6862 rxdp1
->Buffer0_ptr
= *temp0
;
6864 *skb
= dev_alloc_skb(size
);
6866 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6867 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6868 DBG_PRINT(INFO_DBG
, "1 buf mode SKBs\n");
6869 sp
->mac_control
.stats_info
->sw_stat
. \
6870 mem_alloc_fail_cnt
++;
6873 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6874 += (*skb
)->truesize
;
6875 /* storing the mapped addr in a temp variable
6876 * such it will be used for next rxd whose
6877 * Host Control is NULL
6879 rxdp1
->Buffer0_ptr
= *temp0
=
6880 pci_map_single( sp
->pdev
, (*skb
)->data
,
6881 size
- NET_IP_ALIGN
,
6882 PCI_DMA_FROMDEVICE
);
6883 if (pci_dma_mapping_error(sp
->pdev
, rxdp1
->Buffer0_ptr
))
6884 goto memalloc_failed
;
6885 rxdp
->Host_Control
= (unsigned long) (*skb
);
6887 } else if ((sp
->rxd_mode
== RXD_MODE_3B
) && (rxdp
->Host_Control
== 0)) {
6888 struct RxD3
*rxdp3
= (struct RxD3
*)rxdp
;
6889 /* Two buffer Mode */
6891 rxdp3
->Buffer2_ptr
= *temp2
;
6892 rxdp3
->Buffer0_ptr
= *temp0
;
6893 rxdp3
->Buffer1_ptr
= *temp1
;
6895 *skb
= dev_alloc_skb(size
);
6897 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6898 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6899 DBG_PRINT(INFO_DBG
, "2 buf mode SKBs\n");
6900 sp
->mac_control
.stats_info
->sw_stat
. \
6901 mem_alloc_fail_cnt
++;
6904 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6905 += (*skb
)->truesize
;
6906 rxdp3
->Buffer2_ptr
= *temp2
=
6907 pci_map_single(sp
->pdev
, (*skb
)->data
,
6909 PCI_DMA_FROMDEVICE
);
6910 if (pci_dma_mapping_error(sp
->pdev
, rxdp3
->Buffer2_ptr
))
6911 goto memalloc_failed
;
6912 rxdp3
->Buffer0_ptr
= *temp0
=
6913 pci_map_single( sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
6914 PCI_DMA_FROMDEVICE
);
6915 if (pci_dma_mapping_error(sp
->pdev
,
6916 rxdp3
->Buffer0_ptr
)) {
6917 pci_unmap_single (sp
->pdev
,
6918 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
6919 dev
->mtu
+ 4, PCI_DMA_FROMDEVICE
);
6920 goto memalloc_failed
;
6922 rxdp
->Host_Control
= (unsigned long) (*skb
);
6924 /* Buffer-1 will be dummy buffer not used */
6925 rxdp3
->Buffer1_ptr
= *temp1
=
6926 pci_map_single(sp
->pdev
, ba
->ba_1
, BUF1_LEN
,
6927 PCI_DMA_FROMDEVICE
);
6928 if (pci_dma_mapping_error(sp
->pdev
,
6929 rxdp3
->Buffer1_ptr
)) {
6930 pci_unmap_single (sp
->pdev
,
6931 (dma_addr_t
)rxdp3
->Buffer0_ptr
,
6932 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
6933 pci_unmap_single (sp
->pdev
,
6934 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
6935 dev
->mtu
+ 4, PCI_DMA_FROMDEVICE
);
6936 goto memalloc_failed
;
6942 stats
->pci_map_fail_cnt
++;
6943 stats
->mem_freed
+= (*skb
)->truesize
;
6944 dev_kfree_skb(*skb
);
6948 static void set_rxd_buffer_size(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6951 struct net_device
*dev
= sp
->dev
;
6952 if (sp
->rxd_mode
== RXD_MODE_1
) {
6953 rxdp
->Control_2
= SET_BUFFER0_SIZE_1( size
- NET_IP_ALIGN
);
6954 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
6955 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6956 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
6957 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3( dev
->mtu
+ 4);
6961 static int rxd_owner_bit_reset(struct s2io_nic
*sp
)
6963 int i
, j
, k
, blk_cnt
= 0, size
;
6964 struct mac_info
* mac_control
= &sp
->mac_control
;
6965 struct config_param
*config
= &sp
->config
;
6966 struct net_device
*dev
= sp
->dev
;
6967 struct RxD_t
*rxdp
= NULL
;
6968 struct sk_buff
*skb
= NULL
;
6969 struct buffAdd
*ba
= NULL
;
6970 u64 temp0_64
= 0, temp1_64
= 0, temp2_64
= 0;
6972 /* Calculate the size based on ring mode */
6973 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
6974 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
6975 if (sp
->rxd_mode
== RXD_MODE_1
)
6976 size
+= NET_IP_ALIGN
;
6977 else if (sp
->rxd_mode
== RXD_MODE_3B
)
6978 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6980 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6981 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
6982 (rxd_count
[sp
->rxd_mode
] +1);
6984 for (j
= 0; j
< blk_cnt
; j
++) {
6985 for (k
= 0; k
< rxd_count
[sp
->rxd_mode
]; k
++) {
6986 rxdp
= mac_control
->rings
[i
].
6987 rx_blocks
[j
].rxds
[k
].virt_addr
;
6988 if(sp
->rxd_mode
== RXD_MODE_3B
)
6989 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
6990 if (set_rxd_buffer_pointer(sp
, rxdp
, ba
,
6991 &skb
,(u64
*)&temp0_64
,
6998 set_rxd_buffer_size(sp
, rxdp
, size
);
7000 /* flip the Ownership bit to Hardware */
7001 rxdp
->Control_1
|= RXD_OWN_XENA
;
7009 static int s2io_add_isr(struct s2io_nic
* sp
)
7012 struct net_device
*dev
= sp
->dev
;
7015 if (sp
->config
.intr_type
== MSI_X
)
7016 ret
= s2io_enable_msi_x(sp
);
7018 DBG_PRINT(ERR_DBG
, "%s: Defaulting to INTA\n", dev
->name
);
7019 sp
->config
.intr_type
= INTA
;
7022 /* Store the values of the MSIX table in the struct s2io_nic structure */
7023 store_xmsi_data(sp
);
7025 /* After proper initialization of H/W, register ISR */
7026 if (sp
->config
.intr_type
== MSI_X
) {
7027 int i
, msix_rx_cnt
= 0;
7029 for (i
= 0; i
< sp
->num_entries
; i
++) {
7030 if (sp
->s2io_entries
[i
].in_use
== MSIX_FLG
) {
7031 if (sp
->s2io_entries
[i
].type
==
7033 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-RX",
7035 err
= request_irq(sp
->entries
[i
].vector
,
7036 s2io_msix_ring_handle
, 0,
7038 sp
->s2io_entries
[i
].arg
);
7039 } else if (sp
->s2io_entries
[i
].type
==
7041 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-TX",
7043 err
= request_irq(sp
->entries
[i
].vector
,
7044 s2io_msix_fifo_handle
, 0,
7046 sp
->s2io_entries
[i
].arg
);
7049 /* if either data or addr is zero print it. */
7050 if (!(sp
->msix_info
[i
].addr
&&
7051 sp
->msix_info
[i
].data
)) {
7053 "%s @Addr:0x%llx Data:0x%llx\n",
7055 (unsigned long long)
7056 sp
->msix_info
[i
].addr
,
7057 (unsigned long long)
7058 ntohl(sp
->msix_info
[i
].data
));
7062 remove_msix_isr(sp
);
7065 "%s:MSI-X-%d registration "
7066 "failed\n", dev
->name
, i
);
7069 "%s: Defaulting to INTA\n",
7071 sp
->config
.intr_type
= INTA
;
7074 sp
->s2io_entries
[i
].in_use
=
7075 MSIX_REGISTERED_SUCCESS
;
7079 printk(KERN_INFO
"MSI-X-RX %d entries enabled\n",
7081 DBG_PRINT(INFO_DBG
, "MSI-X-TX entries enabled"
7082 " through alarm vector\n");
7085 if (sp
->config
.intr_type
== INTA
) {
7086 err
= request_irq((int) sp
->pdev
->irq
, s2io_isr
, IRQF_SHARED
,
7089 DBG_PRINT(ERR_DBG
, "%s: ISR registration failed\n",
7096 static void s2io_rem_isr(struct s2io_nic
* sp
)
7098 if (sp
->config
.intr_type
== MSI_X
)
7099 remove_msix_isr(sp
);
7101 remove_inta_isr(sp
);
7104 static void do_s2io_card_down(struct s2io_nic
* sp
, int do_io
)
7107 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
7108 register u64 val64
= 0;
7109 struct config_param
*config
;
7110 config
= &sp
->config
;
7112 if (!is_s2io_card_up(sp
))
7115 del_timer_sync(&sp
->alarm_timer
);
7116 /* If s2io_set_link task is executing, wait till it completes. */
7117 while (test_and_set_bit(__S2IO_STATE_LINK_TASK
, &(sp
->state
))) {
7120 clear_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
7123 if (sp
->config
.napi
) {
7125 if (config
->intr_type
== MSI_X
) {
7126 for (; off
< sp
->config
.rx_ring_num
; off
++)
7127 napi_disable(&sp
->mac_control
.rings
[off
].napi
);
7130 napi_disable(&sp
->napi
);
7133 /* disable Tx and Rx traffic on the NIC */
7139 /* stop the tx queue, indicate link down */
7140 s2io_link(sp
, LINK_DOWN
);
7142 /* Check if the device is Quiescent and then Reset the NIC */
7144 /* As per the HW requirement we need to replenish the
7145 * receive buffer to avoid the ring bump. Since there is
7146 * no intention of processing the Rx frame at this pointwe are
7147 * just settting the ownership bit of rxd in Each Rx
7148 * ring to HW and set the appropriate buffer size
7149 * based on the ring mode
7151 rxd_owner_bit_reset(sp
);
7153 val64
= readq(&bar0
->adapter_status
);
7154 if (verify_xena_quiescence(sp
)) {
7155 if(verify_pcc_quiescent(sp
, sp
->device_enabled_once
))
7163 "s2io_close:Device not Quiescent ");
7164 DBG_PRINT(ERR_DBG
, "adaper status reads 0x%llx\n",
7165 (unsigned long long) val64
);
7172 /* Free all Tx buffers */
7173 free_tx_buffers(sp
);
7175 /* Free all Rx buffers */
7176 free_rx_buffers(sp
);
7178 clear_bit(__S2IO_STATE_LINK_TASK
, &(sp
->state
));
7181 static void s2io_card_down(struct s2io_nic
* sp
)
7183 do_s2io_card_down(sp
, 1);
7186 static int s2io_card_up(struct s2io_nic
* sp
)
7189 struct mac_info
*mac_control
;
7190 struct config_param
*config
;
7191 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
7194 /* Initialize the H/W I/O registers */
7197 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
7205 * Initializing the Rx buffers. For now we are considering only 1
7206 * Rx ring and initializing buffers into 30 Rx blocks
7208 mac_control
= &sp
->mac_control
;
7209 config
= &sp
->config
;
7211 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
7212 mac_control
->rings
[i
].mtu
= dev
->mtu
;
7213 ret
= fill_rx_buffers(sp
, &mac_control
->rings
[i
], 1);
7215 DBG_PRINT(ERR_DBG
, "%s: Out of memory in Open\n",
7218 free_rx_buffers(sp
);
7221 DBG_PRINT(INFO_DBG
, "Buf in ring:%d is %d:\n", i
,
7222 mac_control
->rings
[i
].rx_bufs_left
);
7225 /* Initialise napi */
7228 if (config
->intr_type
== MSI_X
) {
7229 for (i
= 0; i
< sp
->config
.rx_ring_num
; i
++)
7230 napi_enable(&sp
->mac_control
.rings
[i
].napi
);
7232 napi_enable(&sp
->napi
);
7236 /* Maintain the state prior to the open */
7237 if (sp
->promisc_flg
)
7238 sp
->promisc_flg
= 0;
7239 if (sp
->m_cast_flg
) {
7241 sp
->all_multi_pos
= 0;
7244 /* Setting its receive mode */
7245 s2io_set_multicast(dev
);
7248 /* Initialize max aggregatable pkts per session based on MTU */
7249 sp
->lro_max_aggr_per_sess
= ((1<<16) - 1) / dev
->mtu
;
7250 /* Check if we can use(if specified) user provided value */
7251 if (lro_max_pkts
< sp
->lro_max_aggr_per_sess
)
7252 sp
->lro_max_aggr_per_sess
= lro_max_pkts
;
7255 /* Enable Rx Traffic and interrupts on the NIC */
7256 if (start_nic(sp
)) {
7257 DBG_PRINT(ERR_DBG
, "%s: Starting NIC failed\n", dev
->name
);
7259 free_rx_buffers(sp
);
7263 /* Add interrupt service routine */
7264 if (s2io_add_isr(sp
) != 0) {
7265 if (sp
->config
.intr_type
== MSI_X
)
7268 free_rx_buffers(sp
);
7272 S2IO_TIMER_CONF(sp
->alarm_timer
, s2io_alarm_handle
, sp
, (HZ
/2));
7274 set_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
7276 /* Enable select interrupts */
7277 en_dis_err_alarms(sp
, ENA_ALL_INTRS
, ENABLE_INTRS
);
7278 if (sp
->config
.intr_type
!= INTA
) {
7279 interruptible
= TX_TRAFFIC_INTR
| TX_PIC_INTR
;
7280 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
7282 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
7283 interruptible
|= TX_PIC_INTR
;
7284 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
7291 * s2io_restart_nic - Resets the NIC.
7292 * @data : long pointer to the device private structure
7294 * This function is scheduled to be run by the s2io_tx_watchdog
7295 * function after 0.5 secs to reset the NIC. The idea is to reduce
7296 * the run time of the watch dog routine which is run holding a
7300 static void s2io_restart_nic(struct work_struct
*work
)
7302 struct s2io_nic
*sp
= container_of(work
, struct s2io_nic
, rst_timer_task
);
7303 struct net_device
*dev
= sp
->dev
;
7307 if (!netif_running(dev
))
7311 if (s2io_card_up(sp
)) {
7312 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
7315 s2io_wake_all_tx_queue(sp
);
7316 DBG_PRINT(ERR_DBG
, "%s: was reset by Tx watchdog timer\n",
7323 * s2io_tx_watchdog - Watchdog for transmit side.
7324 * @dev : Pointer to net device structure
7326 * This function is triggered if the Tx Queue is stopped
7327 * for a pre-defined amount of time when the Interface is still up.
7328 * If the Interface is jammed in such a situation, the hardware is
7329 * reset (by s2io_close) and restarted again (by s2io_open) to
7330 * overcome any problem that might have been caused in the hardware.
7335 static void s2io_tx_watchdog(struct net_device
*dev
)
7337 struct s2io_nic
*sp
= dev
->priv
;
7339 if (netif_carrier_ok(dev
)) {
7340 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
++;
7341 schedule_work(&sp
->rst_timer_task
);
7342 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
7347 * rx_osm_handler - To perform some OS related operations on SKB.
7348 * @sp: private member of the device structure,pointer to s2io_nic structure.
7349 * @skb : the socket buffer pointer.
7350 * @len : length of the packet
7351 * @cksum : FCS checksum of the frame.
7352 * @ring_no : the ring from which this RxD was extracted.
7354 * This function is called by the Rx interrupt serivce routine to perform
7355 * some OS related operations on the SKB before passing it to the upper
7356 * layers. It mainly checks if the checksum is OK, if so adds it to the
7357 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7358 * to the upper layer. If the checksum is wrong, it increments the Rx
7359 * packet error count, frees the SKB and returns error.
7361 * SUCCESS on success and -1 on failure.
7363 static int rx_osm_handler(struct ring_info
*ring_data
, struct RxD_t
* rxdp
)
7365 struct s2io_nic
*sp
= ring_data
->nic
;
7366 struct net_device
*dev
= (struct net_device
*) ring_data
->dev
;
7367 struct sk_buff
*skb
= (struct sk_buff
*)
7368 ((unsigned long) rxdp
->Host_Control
);
7369 int ring_no
= ring_data
->ring_no
;
7370 u16 l3_csum
, l4_csum
;
7371 unsigned long long err
= rxdp
->Control_1
& RXD_T_CODE
;
7378 /* Check for parity error */
7380 sp
->mac_control
.stats_info
->sw_stat
.parity_err_cnt
++;
7382 err_mask
= err
>> 48;
7385 sp
->mac_control
.stats_info
->sw_stat
.
7386 rx_parity_err_cnt
++;
7390 sp
->mac_control
.stats_info
->sw_stat
.
7395 sp
->mac_control
.stats_info
->sw_stat
.
7396 rx_parity_abort_cnt
++;
7400 sp
->mac_control
.stats_info
->sw_stat
.
7405 sp
->mac_control
.stats_info
->sw_stat
.
7410 sp
->mac_control
.stats_info
->sw_stat
.
7415 sp
->mac_control
.stats_info
->sw_stat
.
7416 rx_buf_size_err_cnt
++;
7420 sp
->mac_control
.stats_info
->sw_stat
.
7421 rx_rxd_corrupt_cnt
++;
7425 sp
->mac_control
.stats_info
->sw_stat
.
7430 * Drop the packet if bad transfer code. Exception being
7431 * 0x5, which could be due to unsupported IPv6 extension header.
7432 * In this case, we let stack handle the packet.
7433 * Note that in this case, since checksum will be incorrect,
7434 * stack will validate the same.
7436 if (err_mask
!= 0x5) {
7437 DBG_PRINT(ERR_DBG
, "%s: Rx error Value: 0x%x\n",
7438 dev
->name
, err_mask
);
7439 dev
->stats
.rx_crc_errors
++;
7440 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
7443 ring_data
->rx_bufs_left
-= 1;
7444 rxdp
->Host_Control
= 0;
7449 /* Updating statistics */
7450 ring_data
->rx_packets
++;
7451 rxdp
->Host_Control
= 0;
7452 if (sp
->rxd_mode
== RXD_MODE_1
) {
7453 int len
= RXD_GET_BUFFER0_SIZE_1(rxdp
->Control_2
);
7455 ring_data
->rx_bytes
+= len
;
7458 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
7459 int get_block
= ring_data
->rx_curr_get_info
.block_index
;
7460 int get_off
= ring_data
->rx_curr_get_info
.offset
;
7461 int buf0_len
= RXD_GET_BUFFER0_SIZE_3(rxdp
->Control_2
);
7462 int buf2_len
= RXD_GET_BUFFER2_SIZE_3(rxdp
->Control_2
);
7463 unsigned char *buff
= skb_push(skb
, buf0_len
);
7465 struct buffAdd
*ba
= &ring_data
->ba
[get_block
][get_off
];
7466 ring_data
->rx_bytes
+= buf0_len
+ buf2_len
;
7467 memcpy(buff
, ba
->ba_0
, buf0_len
);
7468 skb_put(skb
, buf2_len
);
7471 if ((rxdp
->Control_1
& TCP_OR_UDP_FRAME
) && ((!ring_data
->lro
) ||
7472 (ring_data
->lro
&& (!(rxdp
->Control_1
& RXD_FRAME_IP_FRAG
)))) &&
7474 l3_csum
= RXD_GET_L3_CKSUM(rxdp
->Control_1
);
7475 l4_csum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
7476 if ((l3_csum
== L3_CKSUM_OK
) && (l4_csum
== L4_CKSUM_OK
)) {
7478 * NIC verifies if the Checksum of the received
7479 * frame is Ok or not and accordingly returns
7480 * a flag in the RxD.
7482 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
7483 if (ring_data
->lro
) {
7488 ret
= s2io_club_tcp_session(ring_data
,
7489 skb
->data
, &tcp
, &tcp_len
, &lro
,
7492 case 3: /* Begin anew */
7495 case 1: /* Aggregate */
7497 lro_append_pkt(sp
, lro
,
7501 case 4: /* Flush session */
7503 lro_append_pkt(sp
, lro
,
7505 queue_rx_frame(lro
->parent
,
7507 clear_lro_session(lro
);
7508 sp
->mac_control
.stats_info
->
7509 sw_stat
.flush_max_pkts
++;
7512 case 2: /* Flush both */
7513 lro
->parent
->data_len
=
7515 sp
->mac_control
.stats_info
->
7516 sw_stat
.sending_both
++;
7517 queue_rx_frame(lro
->parent
,
7519 clear_lro_session(lro
);
7521 case 0: /* sessions exceeded */
7522 case -1: /* non-TCP or not
7526 * First pkt in session not
7527 * L3/L4 aggregatable
7532 "%s: Samadhana!!\n",
7539 * Packet with erroneous checksum, let the
7540 * upper layers deal with it.
7542 skb
->ip_summed
= CHECKSUM_NONE
;
7545 skb
->ip_summed
= CHECKSUM_NONE
;
7547 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
7549 queue_rx_frame(skb
, RXD_GET_VLAN_TAG(rxdp
->Control_2
));
7550 dev
->last_rx
= jiffies
;
7552 sp
->mac_control
.rings
[ring_no
].rx_bufs_left
-= 1;
7557 * s2io_link - stops/starts the Tx queue.
7558 * @sp : private member of the device structure, which is a pointer to the
7559 * s2io_nic structure.
7560 * @link : inidicates whether link is UP/DOWN.
7562 * This function stops/starts the Tx queue depending on whether the link
7563 * status of the NIC is is down or up. This is called by the Alarm
7564 * interrupt handler whenever a link change interrupt comes up.
7569 static void s2io_link(struct s2io_nic
* sp
, int link
)
7571 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
7573 if (link
!= sp
->last_link_state
) {
7575 if (link
== LINK_DOWN
) {
7576 DBG_PRINT(ERR_DBG
, "%s: Link down\n", dev
->name
);
7577 s2io_stop_all_tx_queue(sp
);
7578 netif_carrier_off(dev
);
7579 if(sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
)
7580 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
=
7581 jiffies
- sp
->start_time
;
7582 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
++;
7584 DBG_PRINT(ERR_DBG
, "%s: Link Up\n", dev
->name
);
7585 if (sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
)
7586 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
=
7587 jiffies
- sp
->start_time
;
7588 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
++;
7589 netif_carrier_on(dev
);
7590 s2io_wake_all_tx_queue(sp
);
7593 sp
->last_link_state
= link
;
7594 sp
->start_time
= jiffies
;
7598 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7599 * @sp : private member of the device structure, which is a pointer to the
7600 * s2io_nic structure.
7602 * This function initializes a few of the PCI and PCI-X configuration registers
7603 * with recommended values.
7608 static void s2io_init_pci(struct s2io_nic
* sp
)
7610 u16 pci_cmd
= 0, pcix_cmd
= 0;
7612 /* Enable Data Parity Error Recovery in PCI-X command register. */
7613 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7615 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7617 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7620 /* Set the PErr Response bit in PCI command register. */
7621 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7622 pci_write_config_word(sp
->pdev
, PCI_COMMAND
,
7623 (pci_cmd
| PCI_COMMAND_PARITY
));
7624 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7627 static int s2io_verify_parm(struct pci_dev
*pdev
, u8
*dev_intr_type
,
7630 if ((tx_fifo_num
> MAX_TX_FIFOS
) ||
7631 (tx_fifo_num
< 1)) {
7632 DBG_PRINT(ERR_DBG
, "s2io: Requested number of tx fifos "
7633 "(%d) not supported\n", tx_fifo_num
);
7635 if (tx_fifo_num
< 1)
7638 tx_fifo_num
= MAX_TX_FIFOS
;
7640 DBG_PRINT(ERR_DBG
, "s2io: Default to %d ", tx_fifo_num
);
7641 DBG_PRINT(ERR_DBG
, "tx fifos\n");
7645 *dev_multiq
= multiq
;
7647 if (tx_steering_type
&& (1 == tx_fifo_num
)) {
7648 if (tx_steering_type
!= TX_DEFAULT_STEERING
)
7650 "s2io: Tx steering is not supported with "
7651 "one fifo. Disabling Tx steering.\n");
7652 tx_steering_type
= NO_STEERING
;
7655 if ((tx_steering_type
< NO_STEERING
) ||
7656 (tx_steering_type
> TX_DEFAULT_STEERING
)) {
7657 DBG_PRINT(ERR_DBG
, "s2io: Requested transmit steering not "
7659 DBG_PRINT(ERR_DBG
, "s2io: Disabling transmit steering\n");
7660 tx_steering_type
= NO_STEERING
;
7663 if (rx_ring_num
> MAX_RX_RINGS
) {
7664 DBG_PRINT(ERR_DBG
, "s2io: Requested number of rx rings not "
7666 DBG_PRINT(ERR_DBG
, "s2io: Default to %d rx rings\n",
7668 rx_ring_num
= MAX_RX_RINGS
;
7671 if ((*dev_intr_type
!= INTA
) && (*dev_intr_type
!= MSI_X
)) {
7672 DBG_PRINT(ERR_DBG
, "s2io: Wrong intr_type requested. "
7673 "Defaulting to INTA\n");
7674 *dev_intr_type
= INTA
;
7677 if ((*dev_intr_type
== MSI_X
) &&
7678 ((pdev
->device
!= PCI_DEVICE_ID_HERC_WIN
) &&
7679 (pdev
->device
!= PCI_DEVICE_ID_HERC_UNI
))) {
7680 DBG_PRINT(ERR_DBG
, "s2io: Xframe I does not support MSI_X. "
7681 "Defaulting to INTA\n");
7682 *dev_intr_type
= INTA
;
7685 if ((rx_ring_mode
!= 1) && (rx_ring_mode
!= 2)) {
7686 DBG_PRINT(ERR_DBG
, "s2io: Requested ring mode not supported\n");
7687 DBG_PRINT(ERR_DBG
, "s2io: Defaulting to 1-buffer mode\n");
7694 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7695 * or Traffic class respectively.
7696 * @nic: device private variable
7697 * Description: The function configures the receive steering to
7698 * desired receive ring.
7699 * Return Value: SUCCESS on success and
7700 * '-1' on failure (endian settings incorrect).
7702 static int rts_ds_steer(struct s2io_nic
*nic
, u8 ds_codepoint
, u8 ring
)
7704 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
7705 register u64 val64
= 0;
7707 if (ds_codepoint
> 63)
7710 val64
= RTS_DS_MEM_DATA(ring
);
7711 writeq(val64
, &bar0
->rts_ds_mem_data
);
7713 val64
= RTS_DS_MEM_CTRL_WE
|
7714 RTS_DS_MEM_CTRL_STROBE_NEW_CMD
|
7715 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint
);
7717 writeq(val64
, &bar0
->rts_ds_mem_ctrl
);
7719 return wait_for_cmd_complete(&bar0
->rts_ds_mem_ctrl
,
7720 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED
,
7725 * s2io_init_nic - Initialization of the adapter .
7726 * @pdev : structure containing the PCI related information of the device.
7727 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7729 * The function initializes an adapter identified by the pci_dec structure.
7730 * All OS related initialization including memory and device structure and
7731 * initlaization of the device private variable is done. Also the swapper
7732 * control register is initialized to enable read and write into the I/O
7733 * registers of the device.
7735 * returns 0 on success and negative on failure.
7738 static int __devinit
7739 s2io_init_nic(struct pci_dev
*pdev
, const struct pci_device_id
*pre
)
7741 struct s2io_nic
*sp
;
7742 struct net_device
*dev
;
7744 int dma_flag
= FALSE
;
7745 u32 mac_up
, mac_down
;
7746 u64 val64
= 0, tmp64
= 0;
7747 struct XENA_dev_config __iomem
*bar0
= NULL
;
7749 struct mac_info
*mac_control
;
7750 struct config_param
*config
;
7752 u8 dev_intr_type
= intr_type
;
7754 DECLARE_MAC_BUF(mac
);
7756 ret
= s2io_verify_parm(pdev
, &dev_intr_type
, &dev_multiq
);
7760 if ((ret
= pci_enable_device(pdev
))) {
7762 "s2io_init_nic: pci_enable_device failed\n");
7766 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
7767 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 64bit DMA\n");
7769 if (pci_set_consistent_dma_mask
7770 (pdev
, DMA_64BIT_MASK
)) {
7772 "Unable to obtain 64bit DMA for \
7773 consistent allocations\n");
7774 pci_disable_device(pdev
);
7777 } else if (!pci_set_dma_mask(pdev
, DMA_32BIT_MASK
)) {
7778 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 32bit DMA\n");
7780 pci_disable_device(pdev
);
7783 if ((ret
= pci_request_regions(pdev
, s2io_driver_name
))) {
7784 DBG_PRINT(ERR_DBG
, "%s: Request Regions failed - %x \n", __FUNCTION__
, ret
);
7785 pci_disable_device(pdev
);
7789 dev
= alloc_etherdev_mq(sizeof(struct s2io_nic
), tx_fifo_num
);
7791 dev
= alloc_etherdev(sizeof(struct s2io_nic
));
7793 DBG_PRINT(ERR_DBG
, "Device allocation failed\n");
7794 pci_disable_device(pdev
);
7795 pci_release_regions(pdev
);
7799 pci_set_master(pdev
);
7800 pci_set_drvdata(pdev
, dev
);
7801 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7803 /* Private member variable initialized to s2io NIC structure */
7805 memset(sp
, 0, sizeof(struct s2io_nic
));
7808 sp
->high_dma_flag
= dma_flag
;
7809 sp
->device_enabled_once
= FALSE
;
7810 if (rx_ring_mode
== 1)
7811 sp
->rxd_mode
= RXD_MODE_1
;
7812 if (rx_ring_mode
== 2)
7813 sp
->rxd_mode
= RXD_MODE_3B
;
7815 sp
->config
.intr_type
= dev_intr_type
;
7817 if ((pdev
->device
== PCI_DEVICE_ID_HERC_WIN
) ||
7818 (pdev
->device
== PCI_DEVICE_ID_HERC_UNI
))
7819 sp
->device_type
= XFRAME_II_DEVICE
;
7821 sp
->device_type
= XFRAME_I_DEVICE
;
7823 sp
->lro
= lro_enable
;
7825 /* Initialize some PCI/PCI-X fields of the NIC. */
7829 * Setting the device configuration parameters.
7830 * Most of these parameters can be specified by the user during
7831 * module insertion as they are module loadable parameters. If
7832 * these parameters are not not specified during load time, they
7833 * are initialized with default values.
7835 mac_control
= &sp
->mac_control
;
7836 config
= &sp
->config
;
7838 config
->napi
= napi
;
7839 config
->tx_steering_type
= tx_steering_type
;
7841 /* Tx side parameters. */
7842 if (config
->tx_steering_type
== TX_PRIORITY_STEERING
)
7843 config
->tx_fifo_num
= MAX_TX_FIFOS
;
7845 config
->tx_fifo_num
= tx_fifo_num
;
7847 /* Initialize the fifos used for tx steering */
7848 if (config
->tx_fifo_num
< 5) {
7849 if (config
->tx_fifo_num
== 1)
7850 sp
->total_tcp_fifos
= 1;
7852 sp
->total_tcp_fifos
= config
->tx_fifo_num
- 1;
7853 sp
->udp_fifo_idx
= config
->tx_fifo_num
- 1;
7854 sp
->total_udp_fifos
= 1;
7855 sp
->other_fifo_idx
= sp
->total_tcp_fifos
- 1;
7857 sp
->total_tcp_fifos
= (tx_fifo_num
- FIFO_UDP_MAX_NUM
-
7858 FIFO_OTHER_MAX_NUM
);
7859 sp
->udp_fifo_idx
= sp
->total_tcp_fifos
;
7860 sp
->total_udp_fifos
= FIFO_UDP_MAX_NUM
;
7861 sp
->other_fifo_idx
= sp
->udp_fifo_idx
+ FIFO_UDP_MAX_NUM
;
7864 config
->multiq
= dev_multiq
;
7865 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
7866 config
->tx_cfg
[i
].fifo_len
= tx_fifo_len
[i
];
7867 config
->tx_cfg
[i
].fifo_priority
= i
;
7870 /* mapping the QoS priority to the configured fifos */
7871 for (i
= 0; i
< MAX_TX_FIFOS
; i
++)
7872 config
->fifo_mapping
[i
] = fifo_map
[config
->tx_fifo_num
- 1][i
];
7874 /* map the hashing selector table to the configured fifos */
7875 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
7876 sp
->fifo_selector
[i
] = fifo_selector
[i
];
7879 config
->tx_intr_type
= TXD_INT_TYPE_UTILZ
;
7880 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
7881 config
->tx_cfg
[i
].f_no_snoop
=
7882 (NO_SNOOP_TXD
| NO_SNOOP_TXD_BUFFER
);
7883 if (config
->tx_cfg
[i
].fifo_len
< 65) {
7884 config
->tx_intr_type
= TXD_INT_TYPE_PER_LIST
;
7888 /* + 2 because one Txd for skb->data and one Txd for UFO */
7889 config
->max_txds
= MAX_SKB_FRAGS
+ 2;
7891 /* Rx side parameters. */
7892 config
->rx_ring_num
= rx_ring_num
;
7893 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
7894 config
->rx_cfg
[i
].num_rxd
= rx_ring_sz
[i
] *
7895 (rxd_count
[sp
->rxd_mode
] + 1);
7896 config
->rx_cfg
[i
].ring_priority
= i
;
7897 mac_control
->rings
[i
].rx_bufs_left
= 0;
7898 mac_control
->rings
[i
].rxd_mode
= sp
->rxd_mode
;
7899 mac_control
->rings
[i
].rxd_count
= rxd_count
[sp
->rxd_mode
];
7900 mac_control
->rings
[i
].pdev
= sp
->pdev
;
7901 mac_control
->rings
[i
].dev
= sp
->dev
;
7904 for (i
= 0; i
< rx_ring_num
; i
++) {
7905 config
->rx_cfg
[i
].ring_org
= RING_ORG_BUFF1
;
7906 config
->rx_cfg
[i
].f_no_snoop
=
7907 (NO_SNOOP_RXD
| NO_SNOOP_RXD_BUFFER
);
7910 /* Setting Mac Control parameters */
7911 mac_control
->rmac_pause_time
= rmac_pause_time
;
7912 mac_control
->mc_pause_threshold_q0q3
= mc_pause_threshold_q0q3
;
7913 mac_control
->mc_pause_threshold_q4q7
= mc_pause_threshold_q4q7
;
7916 /* initialize the shared memory used by the NIC and the host */
7917 if (init_shared_mem(sp
)) {
7918 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n",
7921 goto mem_alloc_failed
;
7924 sp
->bar0
= ioremap(pci_resource_start(pdev
, 0),
7925 pci_resource_len(pdev
, 0));
7927 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem1\n",
7930 goto bar0_remap_failed
;
7933 sp
->bar1
= ioremap(pci_resource_start(pdev
, 2),
7934 pci_resource_len(pdev
, 2));
7936 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem2\n",
7939 goto bar1_remap_failed
;
7942 dev
->irq
= pdev
->irq
;
7943 dev
->base_addr
= (unsigned long) sp
->bar0
;
7945 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7946 for (j
= 0; j
< MAX_TX_FIFOS
; j
++) {
7947 mac_control
->tx_FIFO_start
[j
] = (struct TxFIFO_element __iomem
*)
7948 (sp
->bar1
+ (j
* 0x00020000));
7951 /* Driver entry points */
7952 dev
->open
= &s2io_open
;
7953 dev
->stop
= &s2io_close
;
7954 dev
->hard_start_xmit
= &s2io_xmit
;
7955 dev
->get_stats
= &s2io_get_stats
;
7956 dev
->set_multicast_list
= &s2io_set_multicast
;
7957 dev
->do_ioctl
= &s2io_ioctl
;
7958 dev
->set_mac_address
= &s2io_set_mac_addr
;
7959 dev
->change_mtu
= &s2io_change_mtu
;
7960 SET_ETHTOOL_OPS(dev
, &netdev_ethtool_ops
);
7961 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
7962 dev
->vlan_rx_register
= s2io_vlan_rx_register
;
7963 dev
->vlan_rx_kill_vid
= (void *)s2io_vlan_rx_kill_vid
;
7966 * will use eth_mac_addr() for dev->set_mac_address
7967 * mac address will be set every time dev->open() is called
7969 #ifdef CONFIG_NET_POLL_CONTROLLER
7970 dev
->poll_controller
= s2io_netpoll
;
7973 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
7974 if (sp
->high_dma_flag
== TRUE
)
7975 dev
->features
|= NETIF_F_HIGHDMA
;
7976 dev
->features
|= NETIF_F_TSO
;
7977 dev
->features
|= NETIF_F_TSO6
;
7978 if ((sp
->device_type
& XFRAME_II_DEVICE
) && (ufo
)) {
7979 dev
->features
|= NETIF_F_UFO
;
7980 dev
->features
|= NETIF_F_HW_CSUM
;
7982 dev
->tx_timeout
= &s2io_tx_watchdog
;
7983 dev
->watchdog_timeo
= WATCH_DOG_TIMEOUT
;
7984 INIT_WORK(&sp
->rst_timer_task
, s2io_restart_nic
);
7985 INIT_WORK(&sp
->set_link_task
, s2io_set_link
);
7987 pci_save_state(sp
->pdev
);
7989 /* Setting swapper control on the NIC, for proper reset operation */
7990 if (s2io_set_swapper(sp
)) {
7991 DBG_PRINT(ERR_DBG
, "%s:swapper settings are wrong\n",
7994 goto set_swap_failed
;
7997 /* Verify if the Herc works on the slot its placed into */
7998 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7999 mode
= s2io_verify_pci_mode(sp
);
8001 DBG_PRINT(ERR_DBG
, "%s: ", __FUNCTION__
);
8002 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
8004 goto set_swap_failed
;
8008 if (sp
->config
.intr_type
== MSI_X
) {
8009 sp
->num_entries
= config
->rx_ring_num
+ 1;
8010 ret
= s2io_enable_msi_x(sp
);
8013 ret
= s2io_test_msi(sp
);
8014 /* rollback MSI-X, will re-enable during add_isr() */
8015 remove_msix_isr(sp
);
8020 "%s: MSI-X requested but failed to enable\n",
8022 sp
->config
.intr_type
= INTA
;
8026 if (config
->intr_type
== MSI_X
) {
8027 for (i
= 0; i
< config
->rx_ring_num
; i
++)
8028 netif_napi_add(dev
, &mac_control
->rings
[i
].napi
,
8029 s2io_poll_msix
, 64);
8031 netif_napi_add(dev
, &sp
->napi
, s2io_poll_inta
, 64);
8034 /* Not needed for Herc */
8035 if (sp
->device_type
& XFRAME_I_DEVICE
) {
8037 * Fix for all "FFs" MAC address problems observed on
8040 fix_mac_address(sp
);
8045 * MAC address initialization.
8046 * For now only one mac address will be read and used.
8049 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
8050 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET
);
8051 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
8052 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
8053 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
, S2IO_BIT_RESET
);
8054 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
8055 mac_down
= (u32
) tmp64
;
8056 mac_up
= (u32
) (tmp64
>> 32);
8058 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_up
);
8059 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_up
>> 8);
8060 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_up
>> 16);
8061 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_up
>> 24);
8062 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_down
>> 16);
8063 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_down
>> 24);
8065 /* Set the factory defined MAC address initially */
8066 dev
->addr_len
= ETH_ALEN
;
8067 memcpy(dev
->dev_addr
, sp
->def_mac_addr
, ETH_ALEN
);
8068 memcpy(dev
->perm_addr
, dev
->dev_addr
, ETH_ALEN
);
8070 /* initialize number of multicast & unicast MAC entries variables */
8071 if (sp
->device_type
== XFRAME_I_DEVICE
) {
8072 config
->max_mc_addr
= S2IO_XENA_MAX_MC_ADDRESSES
;
8073 config
->max_mac_addr
= S2IO_XENA_MAX_MAC_ADDRESSES
;
8074 config
->mc_start_offset
= S2IO_XENA_MC_ADDR_START_OFFSET
;
8075 } else if (sp
->device_type
== XFRAME_II_DEVICE
) {
8076 config
->max_mc_addr
= S2IO_HERC_MAX_MC_ADDRESSES
;
8077 config
->max_mac_addr
= S2IO_HERC_MAX_MAC_ADDRESSES
;
8078 config
->mc_start_offset
= S2IO_HERC_MC_ADDR_START_OFFSET
;
8081 /* store mac addresses from CAM to s2io_nic structure */
8082 do_s2io_store_unicast_mc(sp
);
8084 /* Configure MSIX vector for number of rings configured plus one */
8085 if ((sp
->device_type
== XFRAME_II_DEVICE
) &&
8086 (config
->intr_type
== MSI_X
))
8087 sp
->num_entries
= config
->rx_ring_num
+ 1;
8089 /* Store the values of the MSIX table in the s2io_nic structure */
8090 store_xmsi_data(sp
);
8091 /* reset Nic and bring it to known state */
8095 * Initialize link state flags
8096 * and the card state parameter
8100 /* Initialize spinlocks */
8101 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
8102 spin_lock_init(&mac_control
->fifos
[i
].tx_lock
);
8105 * SXE-002: Configure link and activity LED to init state
8108 subid
= sp
->pdev
->subsystem_device
;
8109 if ((subid
& 0xFF) >= 0x07) {
8110 val64
= readq(&bar0
->gpio_control
);
8111 val64
|= 0x0000800000000000ULL
;
8112 writeq(val64
, &bar0
->gpio_control
);
8113 val64
= 0x0411040400000000ULL
;
8114 writeq(val64
, (void __iomem
*) bar0
+ 0x2700);
8115 val64
= readq(&bar0
->gpio_control
);
8118 sp
->rx_csum
= 1; /* Rx chksum verify enabled by default */
8120 if (register_netdev(dev
)) {
8121 DBG_PRINT(ERR_DBG
, "Device registration failed\n");
8123 goto register_failed
;
8126 DBG_PRINT(ERR_DBG
, "Copyright(c) 2002-2007 Neterion Inc.\n");
8127 DBG_PRINT(ERR_DBG
, "%s: Neterion %s (rev %d)\n",dev
->name
,
8128 sp
->product_name
, pdev
->revision
);
8129 DBG_PRINT(ERR_DBG
, "%s: Driver version %s\n", dev
->name
,
8130 s2io_driver_version
);
8131 DBG_PRINT(ERR_DBG
, "%s: MAC ADDR: %s\n",
8132 dev
->name
, print_mac(mac
, dev
->dev_addr
));
8133 DBG_PRINT(ERR_DBG
, "SERIAL NUMBER: %s\n", sp
->serial_num
);
8134 if (sp
->device_type
& XFRAME_II_DEVICE
) {
8135 mode
= s2io_print_pci_mode(sp
);
8137 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
8139 unregister_netdev(dev
);
8140 goto set_swap_failed
;
8143 switch(sp
->rxd_mode
) {
8145 DBG_PRINT(ERR_DBG
, "%s: 1-Buffer receive mode enabled\n",
8149 DBG_PRINT(ERR_DBG
, "%s: 2-Buffer receive mode enabled\n",
8154 switch (sp
->config
.napi
) {
8156 DBG_PRINT(ERR_DBG
, "%s: NAPI disabled\n", dev
->name
);
8159 DBG_PRINT(ERR_DBG
, "%s: NAPI enabled\n", dev
->name
);
8163 DBG_PRINT(ERR_DBG
, "%s: Using %d Tx fifo(s)\n", dev
->name
,
8164 sp
->config
.tx_fifo_num
);
8166 DBG_PRINT(ERR_DBG
, "%s: Using %d Rx ring(s)\n", dev
->name
,
8167 sp
->config
.rx_ring_num
);
8169 switch(sp
->config
.intr_type
) {
8171 DBG_PRINT(ERR_DBG
, "%s: Interrupt type INTA\n", dev
->name
);
8174 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI-X\n", dev
->name
);
8177 if (sp
->config
.multiq
) {
8178 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
8179 mac_control
->fifos
[i
].multiq
= config
->multiq
;
8180 DBG_PRINT(ERR_DBG
, "%s: Multiqueue support enabled\n",
8183 DBG_PRINT(ERR_DBG
, "%s: Multiqueue support disabled\n",
8186 switch (sp
->config
.tx_steering_type
) {
8188 DBG_PRINT(ERR_DBG
, "%s: No steering enabled for"
8189 " transmit\n", dev
->name
);
8191 case TX_PRIORITY_STEERING
:
8192 DBG_PRINT(ERR_DBG
, "%s: Priority steering enabled for"
8193 " transmit\n", dev
->name
);
8195 case TX_DEFAULT_STEERING
:
8196 DBG_PRINT(ERR_DBG
, "%s: Default steering enabled for"
8197 " transmit\n", dev
->name
);
8201 DBG_PRINT(ERR_DBG
, "%s: Large receive offload enabled\n",
8204 DBG_PRINT(ERR_DBG
, "%s: UDP Fragmentation Offload(UFO)"
8205 " enabled\n", dev
->name
);
8206 /* Initialize device name */
8207 sprintf(sp
->name
, "%s Neterion %s", dev
->name
, sp
->product_name
);
8210 * Make Link state as off at this point, when the Link change
8211 * interrupt comes the state will be automatically changed to
8214 netif_carrier_off(dev
);
8225 free_shared_mem(sp
);
8226 pci_disable_device(pdev
);
8227 pci_release_regions(pdev
);
8228 pci_set_drvdata(pdev
, NULL
);
8235 * s2io_rem_nic - Free the PCI device
8236 * @pdev: structure containing the PCI related information of the device.
8237 * Description: This function is called by the Pci subsystem to release a
8238 * PCI device and free up all resource held up by the device. This could
8239 * be in response to a Hot plug event or when the driver is to be removed
8243 static void __devexit
s2io_rem_nic(struct pci_dev
*pdev
)
8245 struct net_device
*dev
=
8246 (struct net_device
*) pci_get_drvdata(pdev
);
8247 struct s2io_nic
*sp
;
8250 DBG_PRINT(ERR_DBG
, "Driver Data is NULL!!\n");
8254 flush_scheduled_work();
8257 unregister_netdev(dev
);
8259 free_shared_mem(sp
);
8262 pci_release_regions(pdev
);
8263 pci_set_drvdata(pdev
, NULL
);
8265 pci_disable_device(pdev
);
8269 * s2io_starter - Entry point for the driver
8270 * Description: This function is the entry point for the driver. It verifies
8271 * the module loadable parameters and initializes PCI configuration space.
8274 static int __init
s2io_starter(void)
8276 return pci_register_driver(&s2io_driver
);
8280 * s2io_closer - Cleanup routine for the driver
8281 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8284 static __exit
void s2io_closer(void)
8286 pci_unregister_driver(&s2io_driver
);
8287 DBG_PRINT(INIT_DBG
, "cleanup done\n");
8290 module_init(s2io_starter
);
8291 module_exit(s2io_closer
);
8293 static int check_L2_lro_capable(u8
*buffer
, struct iphdr
**ip
,
8294 struct tcphdr
**tcp
, struct RxD_t
*rxdp
,
8295 struct s2io_nic
*sp
)
8298 u8 l2_type
= (u8
)((rxdp
->Control_1
>> 37) & 0x7), ip_len
;
8300 if (!(rxdp
->Control_1
& RXD_FRAME_PROTO_TCP
)) {
8301 DBG_PRINT(INIT_DBG
,"%s: Non-TCP frames not supported for LRO\n",
8306 /* Checking for DIX type or DIX type with VLAN */
8308 || (l2_type
== 4)) {
8309 ip_off
= HEADER_ETHERNET_II_802_3_SIZE
;
8311 * If vlan stripping is disabled and the frame is VLAN tagged,
8312 * shift the offset by the VLAN header size bytes.
8314 if ((!vlan_strip_flag
) &&
8315 (rxdp
->Control_1
& RXD_FRAME_VLAN_TAG
))
8316 ip_off
+= HEADER_VLAN_SIZE
;
8318 /* LLC, SNAP etc are considered non-mergeable */
8322 *ip
= (struct iphdr
*)((u8
*)buffer
+ ip_off
);
8323 ip_len
= (u8
)((*ip
)->ihl
);
8325 *tcp
= (struct tcphdr
*)((unsigned long)*ip
+ ip_len
);
8330 static int check_for_socket_match(struct lro
*lro
, struct iphdr
*ip
,
8333 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
8334 if ((lro
->iph
->saddr
!= ip
->saddr
) || (lro
->iph
->daddr
!= ip
->daddr
) ||
8335 (lro
->tcph
->source
!= tcp
->source
) || (lro
->tcph
->dest
!= tcp
->dest
))
8340 static inline int get_l4_pyld_length(struct iphdr
*ip
, struct tcphdr
*tcp
)
8342 return(ntohs(ip
->tot_len
) - (ip
->ihl
<< 2) - (tcp
->doff
<< 2));
8345 static void initiate_new_session(struct lro
*lro
, u8
*l2h
,
8346 struct iphdr
*ip
, struct tcphdr
*tcp
, u32 tcp_pyld_len
, u16 vlan_tag
)
8348 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
8352 lro
->tcp_next_seq
= tcp_pyld_len
+ ntohl(tcp
->seq
);
8353 lro
->tcp_ack
= tcp
->ack_seq
;
8355 lro
->total_len
= ntohs(ip
->tot_len
);
8357 lro
->vlan_tag
= vlan_tag
;
8359 * check if we saw TCP timestamp. Other consistency checks have
8360 * already been done.
8362 if (tcp
->doff
== 8) {
8364 ptr
= (__be32
*)(tcp
+1);
8366 lro
->cur_tsval
= ntohl(*(ptr
+1));
8367 lro
->cur_tsecr
= *(ptr
+2);
8372 static void update_L3L4_header(struct s2io_nic
*sp
, struct lro
*lro
)
8374 struct iphdr
*ip
= lro
->iph
;
8375 struct tcphdr
*tcp
= lro
->tcph
;
8377 struct stat_block
*statinfo
= sp
->mac_control
.stats_info
;
8378 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
8380 /* Update L3 header */
8381 ip
->tot_len
= htons(lro
->total_len
);
8383 nchk
= ip_fast_csum((u8
*)lro
->iph
, ip
->ihl
);
8386 /* Update L4 header */
8387 tcp
->ack_seq
= lro
->tcp_ack
;
8388 tcp
->window
= lro
->window
;
8390 /* Update tsecr field if this session has timestamps enabled */
8392 __be32
*ptr
= (__be32
*)(tcp
+ 1);
8393 *(ptr
+2) = lro
->cur_tsecr
;
8396 /* Update counters required for calculation of
8397 * average no. of packets aggregated.
8399 statinfo
->sw_stat
.sum_avg_pkts_aggregated
+= lro
->sg_num
;
8400 statinfo
->sw_stat
.num_aggregations
++;
8403 static void aggregate_new_rx(struct lro
*lro
, struct iphdr
*ip
,
8404 struct tcphdr
*tcp
, u32 l4_pyld
)
8406 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
8407 lro
->total_len
+= l4_pyld
;
8408 lro
->frags_len
+= l4_pyld
;
8409 lro
->tcp_next_seq
+= l4_pyld
;
8412 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8413 lro
->tcp_ack
= tcp
->ack_seq
;
8414 lro
->window
= tcp
->window
;
8418 /* Update tsecr and tsval from this packet */
8419 ptr
= (__be32
*)(tcp
+1);
8420 lro
->cur_tsval
= ntohl(*(ptr
+1));
8421 lro
->cur_tsecr
= *(ptr
+ 2);
8425 static int verify_l3_l4_lro_capable(struct lro
*l_lro
, struct iphdr
*ip
,
8426 struct tcphdr
*tcp
, u32 tcp_pyld_len
)
8430 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
8432 if (!tcp_pyld_len
) {
8433 /* Runt frame or a pure ack */
8437 if (ip
->ihl
!= 5) /* IP has options */
8440 /* If we see CE codepoint in IP header, packet is not mergeable */
8441 if (INET_ECN_is_ce(ipv4_get_dsfield(ip
)))
8444 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8445 if (tcp
->urg
|| tcp
->psh
|| tcp
->rst
|| tcp
->syn
|| tcp
->fin
||
8446 tcp
->ece
|| tcp
->cwr
|| !tcp
->ack
) {
8448 * Currently recognize only the ack control word and
8449 * any other control field being set would result in
8450 * flushing the LRO session
8456 * Allow only one TCP timestamp option. Don't aggregate if
8457 * any other options are detected.
8459 if (tcp
->doff
!= 5 && tcp
->doff
!= 8)
8462 if (tcp
->doff
== 8) {
8463 ptr
= (u8
*)(tcp
+ 1);
8464 while (*ptr
== TCPOPT_NOP
)
8466 if (*ptr
!= TCPOPT_TIMESTAMP
|| *(ptr
+1) != TCPOLEN_TIMESTAMP
)
8469 /* Ensure timestamp value increases monotonically */
8471 if (l_lro
->cur_tsval
> ntohl(*((__be32
*)(ptr
+2))))
8474 /* timestamp echo reply should be non-zero */
8475 if (*((__be32
*)(ptr
+6)) == 0)
8483 s2io_club_tcp_session(struct ring_info
*ring_data
, u8
*buffer
, u8
**tcp
,
8484 u32
*tcp_len
, struct lro
**lro
, struct RxD_t
*rxdp
,
8485 struct s2io_nic
*sp
)
8488 struct tcphdr
*tcph
;
8492 if (!(ret
= check_L2_lro_capable(buffer
, &ip
, (struct tcphdr
**)tcp
,
8494 DBG_PRINT(INFO_DBG
,"IP Saddr: %x Daddr: %x\n",
8495 ip
->saddr
, ip
->daddr
);
8499 vlan_tag
= RXD_GET_VLAN_TAG(rxdp
->Control_2
);
8500 tcph
= (struct tcphdr
*)*tcp
;
8501 *tcp_len
= get_l4_pyld_length(ip
, tcph
);
8502 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
8503 struct lro
*l_lro
= &ring_data
->lro0_n
[i
];
8504 if (l_lro
->in_use
) {
8505 if (check_for_socket_match(l_lro
, ip
, tcph
))
8507 /* Sock pair matched */
8510 if ((*lro
)->tcp_next_seq
!= ntohl(tcph
->seq
)) {
8511 DBG_PRINT(INFO_DBG
, "%s:Out of order. expected "
8512 "0x%x, actual 0x%x\n", __FUNCTION__
,
8513 (*lro
)->tcp_next_seq
,
8516 sp
->mac_control
.stats_info
->
8517 sw_stat
.outof_sequence_pkts
++;
8522 if (!verify_l3_l4_lro_capable(l_lro
, ip
, tcph
,*tcp_len
))
8523 ret
= 1; /* Aggregate */
8525 ret
= 2; /* Flush both */
8531 /* Before searching for available LRO objects,
8532 * check if the pkt is L3/L4 aggregatable. If not
8533 * don't create new LRO session. Just send this
8536 if (verify_l3_l4_lro_capable(NULL
, ip
, tcph
, *tcp_len
)) {
8540 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
8541 struct lro
*l_lro
= &ring_data
->lro0_n
[i
];
8542 if (!(l_lro
->in_use
)) {
8544 ret
= 3; /* Begin anew */
8550 if (ret
== 0) { /* sessions exceeded */
8551 DBG_PRINT(INFO_DBG
,"%s:All LRO sessions already in use\n",
8559 initiate_new_session(*lro
, buffer
, ip
, tcph
, *tcp_len
,
8563 update_L3L4_header(sp
, *lro
);
8566 aggregate_new_rx(*lro
, ip
, tcph
, *tcp_len
);
8567 if ((*lro
)->sg_num
== sp
->lro_max_aggr_per_sess
) {
8568 update_L3L4_header(sp
, *lro
);
8569 ret
= 4; /* Flush the LRO */
8573 DBG_PRINT(ERR_DBG
,"%s:Dont know, can't say!!\n",
8581 static void clear_lro_session(struct lro
*lro
)
8583 static u16 lro_struct_size
= sizeof(struct lro
);
8585 memset(lro
, 0, lro_struct_size
);
8588 static void queue_rx_frame(struct sk_buff
*skb
, u16 vlan_tag
)
8590 struct net_device
*dev
= skb
->dev
;
8591 struct s2io_nic
*sp
= dev
->priv
;
8593 skb
->protocol
= eth_type_trans(skb
, dev
);
8594 if (sp
->vlgrp
&& vlan_tag
8595 && (vlan_strip_flag
)) {
8596 /* Queueing the vlan frame to the upper layer */
8597 if (sp
->config
.napi
)
8598 vlan_hwaccel_receive_skb(skb
, sp
->vlgrp
, vlan_tag
);
8600 vlan_hwaccel_rx(skb
, sp
->vlgrp
, vlan_tag
);
8602 if (sp
->config
.napi
)
8603 netif_receive_skb(skb
);
8609 static void lro_append_pkt(struct s2io_nic
*sp
, struct lro
*lro
,
8610 struct sk_buff
*skb
,
8613 struct sk_buff
*first
= lro
->parent
;
8615 first
->len
+= tcp_len
;
8616 first
->data_len
= lro
->frags_len
;
8617 skb_pull(skb
, (skb
->len
- tcp_len
));
8618 if (skb_shinfo(first
)->frag_list
)
8619 lro
->last_frag
->next
= skb
;
8621 skb_shinfo(first
)->frag_list
= skb
;
8622 first
->truesize
+= skb
->truesize
;
8623 lro
->last_frag
= skb
;
8624 sp
->mac_control
.stats_info
->sw_stat
.clubbed_frms_cnt
++;
8629 * s2io_io_error_detected - called when PCI error is detected
8630 * @pdev: Pointer to PCI device
8631 * @state: The current pci connection state
8633 * This function is called after a PCI bus error affecting
8634 * this device has been detected.
8636 static pci_ers_result_t
s2io_io_error_detected(struct pci_dev
*pdev
,
8637 pci_channel_state_t state
)
8639 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8640 struct s2io_nic
*sp
= netdev
->priv
;
8642 netif_device_detach(netdev
);
8644 if (netif_running(netdev
)) {
8645 /* Bring down the card, while avoiding PCI I/O */
8646 do_s2io_card_down(sp
, 0);
8648 pci_disable_device(pdev
);
8650 return PCI_ERS_RESULT_NEED_RESET
;
8654 * s2io_io_slot_reset - called after the pci bus has been reset.
8655 * @pdev: Pointer to PCI device
8657 * Restart the card from scratch, as if from a cold-boot.
8658 * At this point, the card has exprienced a hard reset,
8659 * followed by fixups by BIOS, and has its config space
8660 * set up identically to what it was at cold boot.
8662 static pci_ers_result_t
s2io_io_slot_reset(struct pci_dev
*pdev
)
8664 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8665 struct s2io_nic
*sp
= netdev
->priv
;
8667 if (pci_enable_device(pdev
)) {
8668 printk(KERN_ERR
"s2io: "
8669 "Cannot re-enable PCI device after reset.\n");
8670 return PCI_ERS_RESULT_DISCONNECT
;
8673 pci_set_master(pdev
);
8676 return PCI_ERS_RESULT_RECOVERED
;
8680 * s2io_io_resume - called when traffic can start flowing again.
8681 * @pdev: Pointer to PCI device
8683 * This callback is called when the error recovery driver tells
8684 * us that its OK to resume normal operation.
8686 static void s2io_io_resume(struct pci_dev
*pdev
)
8688 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8689 struct s2io_nic
*sp
= netdev
->priv
;
8691 if (netif_running(netdev
)) {
8692 if (s2io_card_up(sp
)) {
8693 printk(KERN_ERR
"s2io: "
8694 "Can't bring device back up after reset.\n");
8698 if (s2io_set_mac_addr(netdev
, netdev
->dev_addr
) == FAILURE
) {
8700 printk(KERN_ERR
"s2io: "
8701 "Can't resetore mac addr after reset.\n");
8706 netif_device_attach(netdev
);
8707 netif_tx_wake_all_queues(netdev
);