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Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[mirror_ubuntu-artful-kernel.git] / drivers / net / s2io.c
1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 *
30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 ************************************************************************/
46
47 #include <linux/module.h>
48 #include <linux/types.h>
49 #include <linux/errno.h>
50 #include <linux/ioport.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/kernel.h>
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/skbuff.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/stddef.h>
60 #include <linux/ioctl.h>
61 #include <linux/timex.h>
62 #include <linux/sched.h>
63 #include <linux/ethtool.h>
64 #include <linux/workqueue.h>
65 #include <linux/if_vlan.h>
66 #include <linux/ip.h>
67 #include <linux/tcp.h>
68 #include <net/tcp.h>
69
70 #include <asm/system.h>
71 #include <asm/uaccess.h>
72 #include <asm/io.h>
73 #include <asm/div64.h>
74 #include <asm/irq.h>
75
76 /* local include */
77 #include "s2io.h"
78 #include "s2io-regs.h"
79
80 #define DRV_VERSION "2.0.15.2"
81
82 /* S2io Driver name & version. */
83 static char s2io_driver_name[] = "Neterion";
84 static char s2io_driver_version[] = DRV_VERSION;
85
86 static int rxd_size[4] = {32,48,48,64};
87 static int rxd_count[4] = {127,85,85,63};
88
89 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
90 {
91 int ret;
92
93 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
94 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
95
96 return ret;
97 }
98
99 /*
100 * Cards with following subsystem_id have a link state indication
101 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
102 * macro below identifies these cards given the subsystem_id.
103 */
104 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
105 (dev_type == XFRAME_I_DEVICE) ? \
106 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
107 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
108
109 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
110 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
111 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
112 #define PANIC 1
113 #define LOW 2
114 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
115 {
116 mac_info_t *mac_control;
117
118 mac_control = &sp->mac_control;
119 if (rxb_size <= rxd_count[sp->rxd_mode])
120 return PANIC;
121 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
122 return LOW;
123 return 0;
124 }
125
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
133 };
134
135 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
136 {"tmac_frms"},
137 {"tmac_data_octets"},
138 {"tmac_drop_frms"},
139 {"tmac_mcst_frms"},
140 {"tmac_bcst_frms"},
141 {"tmac_pause_ctrl_frms"},
142 {"tmac_ttl_octets"},
143 {"tmac_ucst_frms"},
144 {"tmac_nucst_frms"},
145 {"tmac_any_err_frms"},
146 {"tmac_ttl_less_fb_octets"},
147 {"tmac_vld_ip_octets"},
148 {"tmac_vld_ip"},
149 {"tmac_drop_ip"},
150 {"tmac_icmp"},
151 {"tmac_rst_tcp"},
152 {"tmac_tcp"},
153 {"tmac_udp"},
154 {"rmac_vld_frms"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
157 {"rmac_drop_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
161 {"rmac_out_rng_len_err_frms"},
162 {"rmac_long_frms"},
163 {"rmac_pause_ctrl_frms"},
164 {"rmac_unsup_ctrl_frms"},
165 {"rmac_ttl_octets"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
168 {"rmac_discarded_frms"},
169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
171 {"rmac_ttl_frms"},
172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
174 {"rmac_frag_frms"},
175 {"rmac_jabber_frms"},
176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
182 {"rmac_ip"},
183 {"rmac_ip_octets"},
184 {"rmac_hdr_err_ip"},
185 {"rmac_drop_ip"},
186 {"rmac_icmp"},
187 {"rmac_tcp"},
188 {"rmac_udp"},
189 {"rmac_err_drp_udp"},
190 {"rmac_xgmii_err_sym"},
191 {"rmac_frms_q0"},
192 {"rmac_frms_q1"},
193 {"rmac_frms_q2"},
194 {"rmac_frms_q3"},
195 {"rmac_frms_q4"},
196 {"rmac_frms_q5"},
197 {"rmac_frms_q6"},
198 {"rmac_frms_q7"},
199 {"rmac_full_q0"},
200 {"rmac_full_q1"},
201 {"rmac_full_q2"},
202 {"rmac_full_q3"},
203 {"rmac_full_q4"},
204 {"rmac_full_q5"},
205 {"rmac_full_q6"},
206 {"rmac_full_q7"},
207 {"rmac_pause_cnt"},
208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
210 {"rmac_accepted_ip"},
211 {"rmac_err_tcp"},
212 {"rd_req_cnt"},
213 {"new_rd_req_cnt"},
214 {"new_rd_req_rtry_cnt"},
215 {"rd_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
217 {"wr_req_cnt"},
218 {"new_wr_req_cnt"},
219 {"new_wr_req_rtry_cnt"},
220 {"wr_rtry_cnt"},
221 {"wr_disc_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
223 {"txp_wr_cnt"},
224 {"txd_rd_cnt"},
225 {"txd_wr_cnt"},
226 {"rxd_rd_cnt"},
227 {"rxd_wr_cnt"},
228 {"txf_rd_cnt"},
229 {"rxf_wr_cnt"},
230 {"rmac_ttl_1519_4095_frms"},
231 {"rmac_ttl_4096_8191_frms"},
232 {"rmac_ttl_8192_max_frms"},
233 {"rmac_ttl_gt_max_frms"},
234 {"rmac_osized_alt_frms"},
235 {"rmac_jabber_alt_frms"},
236 {"rmac_gt_max_alt_frms"},
237 {"rmac_vlan_frms"},
238 {"rmac_len_discard"},
239 {"rmac_fcs_discard"},
240 {"rmac_pf_discard"},
241 {"rmac_da_discard"},
242 {"rmac_red_discard"},
243 {"rmac_rts_discard"},
244 {"rmac_ingm_full_discard"},
245 {"link_fault_cnt"},
246 {"\n DRIVER STATISTICS"},
247 {"single_bit_ecc_errs"},
248 {"double_bit_ecc_errs"},
249 {"parity_err_cnt"},
250 {"serious_err_cnt"},
251 {"soft_reset_cnt"},
252 {"fifo_full_cnt"},
253 {"ring_full_cnt"},
254 ("alarm_transceiver_temp_high"),
255 ("alarm_transceiver_temp_low"),
256 ("alarm_laser_bias_current_high"),
257 ("alarm_laser_bias_current_low"),
258 ("alarm_laser_output_power_high"),
259 ("alarm_laser_output_power_low"),
260 ("warn_transceiver_temp_high"),
261 ("warn_transceiver_temp_low"),
262 ("warn_laser_bias_current_high"),
263 ("warn_laser_bias_current_low"),
264 ("warn_laser_output_power_high"),
265 ("warn_laser_output_power_low"),
266 ("lro_aggregated_pkts"),
267 ("lro_flush_both_count"),
268 ("lro_out_of_sequence_pkts"),
269 ("lro_flush_due_to_max_pkts"),
270 ("lro_avg_aggr_pkts"),
271 };
272
273 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
274 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
275
276 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
277 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
278
279 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
280 init_timer(&timer); \
281 timer.function = handle; \
282 timer.data = (unsigned long) arg; \
283 mod_timer(&timer, (jiffies + exp)) \
284
285 /* Add the vlan */
286 static void s2io_vlan_rx_register(struct net_device *dev,
287 struct vlan_group *grp)
288 {
289 nic_t *nic = dev->priv;
290 unsigned long flags;
291
292 spin_lock_irqsave(&nic->tx_lock, flags);
293 nic->vlgrp = grp;
294 spin_unlock_irqrestore(&nic->tx_lock, flags);
295 }
296
297 /* Unregister the vlan */
298 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
299 {
300 nic_t *nic = dev->priv;
301 unsigned long flags;
302
303 spin_lock_irqsave(&nic->tx_lock, flags);
304 if (nic->vlgrp)
305 nic->vlgrp->vlan_devices[vid] = NULL;
306 spin_unlock_irqrestore(&nic->tx_lock, flags);
307 }
308
309 /*
310 * Constants to be programmed into the Xena's registers, to configure
311 * the XAUI.
312 */
313
314 #define END_SIGN 0x0
315 static const u64 herc_act_dtx_cfg[] = {
316 /* Set address */
317 0x8000051536750000ULL, 0x80000515367500E0ULL,
318 /* Write data */
319 0x8000051536750004ULL, 0x80000515367500E4ULL,
320 /* Set address */
321 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
322 /* Write data */
323 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
324 /* Set address */
325 0x801205150D440000ULL, 0x801205150D4400E0ULL,
326 /* Write data */
327 0x801205150D440004ULL, 0x801205150D4400E4ULL,
328 /* Set address */
329 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
330 /* Write data */
331 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
332 /* Done */
333 END_SIGN
334 };
335
336 static const u64 xena_dtx_cfg[] = {
337 /* Set address */
338 0x8000051500000000ULL, 0x80000515000000E0ULL,
339 /* Write data */
340 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
341 /* Set address */
342 0x8001051500000000ULL, 0x80010515000000E0ULL,
343 /* Write data */
344 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
345 /* Set address */
346 0x8002051500000000ULL, 0x80020515000000E0ULL,
347 /* Write data */
348 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
349 END_SIGN
350 };
351
352 /*
353 * Constants for Fixing the MacAddress problem seen mostly on
354 * Alpha machines.
355 */
356 static const u64 fix_mac[] = {
357 0x0060000000000000ULL, 0x0060600000000000ULL,
358 0x0040600000000000ULL, 0x0000600000000000ULL,
359 0x0020600000000000ULL, 0x0060600000000000ULL,
360 0x0020600000000000ULL, 0x0060600000000000ULL,
361 0x0020600000000000ULL, 0x0060600000000000ULL,
362 0x0020600000000000ULL, 0x0060600000000000ULL,
363 0x0020600000000000ULL, 0x0060600000000000ULL,
364 0x0020600000000000ULL, 0x0060600000000000ULL,
365 0x0020600000000000ULL, 0x0060600000000000ULL,
366 0x0020600000000000ULL, 0x0060600000000000ULL,
367 0x0020600000000000ULL, 0x0060600000000000ULL,
368 0x0020600000000000ULL, 0x0060600000000000ULL,
369 0x0020600000000000ULL, 0x0000600000000000ULL,
370 0x0040600000000000ULL, 0x0060600000000000ULL,
371 END_SIGN
372 };
373
374 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
375 MODULE_LICENSE("GPL");
376 MODULE_VERSION(DRV_VERSION);
377
378
379 /* Module Loadable parameters. */
380 S2IO_PARM_INT(tx_fifo_num, 1);
381 S2IO_PARM_INT(rx_ring_num, 1);
382
383
384 S2IO_PARM_INT(rx_ring_mode, 1);
385 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
386 S2IO_PARM_INT(rmac_pause_time, 0x100);
387 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
388 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
389 S2IO_PARM_INT(shared_splits, 0);
390 S2IO_PARM_INT(tmac_util_period, 5);
391 S2IO_PARM_INT(rmac_util_period, 5);
392 S2IO_PARM_INT(bimodal, 0);
393 S2IO_PARM_INT(l3l4hdr_size, 128);
394 /* Frequency of Rx desc syncs expressed as power of 2 */
395 S2IO_PARM_INT(rxsync_frequency, 3);
396 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
397 S2IO_PARM_INT(intr_type, 0);
398 /* Large receive offload feature */
399 S2IO_PARM_INT(lro, 0);
400 /* Max pkts to be aggregated by LRO at one time. If not specified,
401 * aggregation happens until we hit max IP pkt size(64K)
402 */
403 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
404 #ifndef CONFIG_S2IO_NAPI
405 S2IO_PARM_INT(indicate_max_pkts, 0);
406 #endif
407
408 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
409 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
410 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
411 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
412 static unsigned int rts_frm_len[MAX_RX_RINGS] =
413 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
414
415 module_param_array(tx_fifo_len, uint, NULL, 0);
416 module_param_array(rx_ring_sz, uint, NULL, 0);
417 module_param_array(rts_frm_len, uint, NULL, 0);
418
419 /*
420 * S2IO device table.
421 * This table lists all the devices that this driver supports.
422 */
423 static struct pci_device_id s2io_tbl[] __devinitdata = {
424 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
425 PCI_ANY_ID, PCI_ANY_ID},
426 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
427 PCI_ANY_ID, PCI_ANY_ID},
428 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
429 PCI_ANY_ID, PCI_ANY_ID},
430 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
431 PCI_ANY_ID, PCI_ANY_ID},
432 {0,}
433 };
434
435 MODULE_DEVICE_TABLE(pci, s2io_tbl);
436
437 static struct pci_driver s2io_driver = {
438 .name = "S2IO",
439 .id_table = s2io_tbl,
440 .probe = s2io_init_nic,
441 .remove = __devexit_p(s2io_rem_nic),
442 };
443
444 /* A simplifier macro used both by init and free shared_mem Fns(). */
445 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
446
447 /**
448 * init_shared_mem - Allocation and Initialization of Memory
449 * @nic: Device private variable.
450 * Description: The function allocates all the memory areas shared
451 * between the NIC and the driver. This includes Tx descriptors,
452 * Rx descriptors and the statistics block.
453 */
454
455 static int init_shared_mem(struct s2io_nic *nic)
456 {
457 u32 size;
458 void *tmp_v_addr, *tmp_v_addr_next;
459 dma_addr_t tmp_p_addr, tmp_p_addr_next;
460 RxD_block_t *pre_rxd_blk = NULL;
461 int i, j, blk_cnt, rx_sz, tx_sz;
462 int lst_size, lst_per_page;
463 struct net_device *dev = nic->dev;
464 unsigned long tmp;
465 buffAdd_t *ba;
466
467 mac_info_t *mac_control;
468 struct config_param *config;
469
470 mac_control = &nic->mac_control;
471 config = &nic->config;
472
473
474 /* Allocation and initialization of TXDLs in FIOFs */
475 size = 0;
476 for (i = 0; i < config->tx_fifo_num; i++) {
477 size += config->tx_cfg[i].fifo_len;
478 }
479 if (size > MAX_AVAILABLE_TXDS) {
480 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
481 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
482 return -EINVAL;
483 }
484
485 lst_size = (sizeof(TxD_t) * config->max_txds);
486 tx_sz = lst_size * size;
487 lst_per_page = PAGE_SIZE / lst_size;
488
489 for (i = 0; i < config->tx_fifo_num; i++) {
490 int fifo_len = config->tx_cfg[i].fifo_len;
491 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
492 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
493 GFP_KERNEL);
494 if (!mac_control->fifos[i].list_info) {
495 DBG_PRINT(ERR_DBG,
496 "Malloc failed for list_info\n");
497 return -ENOMEM;
498 }
499 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
500 }
501 for (i = 0; i < config->tx_fifo_num; i++) {
502 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
503 lst_per_page);
504 mac_control->fifos[i].tx_curr_put_info.offset = 0;
505 mac_control->fifos[i].tx_curr_put_info.fifo_len =
506 config->tx_cfg[i].fifo_len - 1;
507 mac_control->fifos[i].tx_curr_get_info.offset = 0;
508 mac_control->fifos[i].tx_curr_get_info.fifo_len =
509 config->tx_cfg[i].fifo_len - 1;
510 mac_control->fifos[i].fifo_no = i;
511 mac_control->fifos[i].nic = nic;
512 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
513
514 for (j = 0; j < page_num; j++) {
515 int k = 0;
516 dma_addr_t tmp_p;
517 void *tmp_v;
518 tmp_v = pci_alloc_consistent(nic->pdev,
519 PAGE_SIZE, &tmp_p);
520 if (!tmp_v) {
521 DBG_PRINT(ERR_DBG,
522 "pci_alloc_consistent ");
523 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
524 return -ENOMEM;
525 }
526 /* If we got a zero DMA address(can happen on
527 * certain platforms like PPC), reallocate.
528 * Store virtual address of page we don't want,
529 * to be freed later.
530 */
531 if (!tmp_p) {
532 mac_control->zerodma_virt_addr = tmp_v;
533 DBG_PRINT(INIT_DBG,
534 "%s: Zero DMA address for TxDL. ", dev->name);
535 DBG_PRINT(INIT_DBG,
536 "Virtual address %p\n", tmp_v);
537 tmp_v = pci_alloc_consistent(nic->pdev,
538 PAGE_SIZE, &tmp_p);
539 if (!tmp_v) {
540 DBG_PRINT(ERR_DBG,
541 "pci_alloc_consistent ");
542 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
543 return -ENOMEM;
544 }
545 }
546 while (k < lst_per_page) {
547 int l = (j * lst_per_page) + k;
548 if (l == config->tx_cfg[i].fifo_len)
549 break;
550 mac_control->fifos[i].list_info[l].list_virt_addr =
551 tmp_v + (k * lst_size);
552 mac_control->fifos[i].list_info[l].list_phy_addr =
553 tmp_p + (k * lst_size);
554 k++;
555 }
556 }
557 }
558
559 nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
560 if (!nic->ufo_in_band_v)
561 return -ENOMEM;
562 memset(nic->ufo_in_band_v, 0, size);
563
564 /* Allocation and initialization of RXDs in Rings */
565 size = 0;
566 for (i = 0; i < config->rx_ring_num; i++) {
567 if (config->rx_cfg[i].num_rxd %
568 (rxd_count[nic->rxd_mode] + 1)) {
569 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
570 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
571 i);
572 DBG_PRINT(ERR_DBG, "RxDs per Block");
573 return FAILURE;
574 }
575 size += config->rx_cfg[i].num_rxd;
576 mac_control->rings[i].block_count =
577 config->rx_cfg[i].num_rxd /
578 (rxd_count[nic->rxd_mode] + 1 );
579 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
580 mac_control->rings[i].block_count;
581 }
582 if (nic->rxd_mode == RXD_MODE_1)
583 size = (size * (sizeof(RxD1_t)));
584 else
585 size = (size * (sizeof(RxD3_t)));
586 rx_sz = size;
587
588 for (i = 0; i < config->rx_ring_num; i++) {
589 mac_control->rings[i].rx_curr_get_info.block_index = 0;
590 mac_control->rings[i].rx_curr_get_info.offset = 0;
591 mac_control->rings[i].rx_curr_get_info.ring_len =
592 config->rx_cfg[i].num_rxd - 1;
593 mac_control->rings[i].rx_curr_put_info.block_index = 0;
594 mac_control->rings[i].rx_curr_put_info.offset = 0;
595 mac_control->rings[i].rx_curr_put_info.ring_len =
596 config->rx_cfg[i].num_rxd - 1;
597 mac_control->rings[i].nic = nic;
598 mac_control->rings[i].ring_no = i;
599
600 blk_cnt = config->rx_cfg[i].num_rxd /
601 (rxd_count[nic->rxd_mode] + 1);
602 /* Allocating all the Rx blocks */
603 for (j = 0; j < blk_cnt; j++) {
604 rx_block_info_t *rx_blocks;
605 int l;
606
607 rx_blocks = &mac_control->rings[i].rx_blocks[j];
608 size = SIZE_OF_BLOCK; //size is always page size
609 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
610 &tmp_p_addr);
611 if (tmp_v_addr == NULL) {
612 /*
613 * In case of failure, free_shared_mem()
614 * is called, which should free any
615 * memory that was alloced till the
616 * failure happened.
617 */
618 rx_blocks->block_virt_addr = tmp_v_addr;
619 return -ENOMEM;
620 }
621 memset(tmp_v_addr, 0, size);
622 rx_blocks->block_virt_addr = tmp_v_addr;
623 rx_blocks->block_dma_addr = tmp_p_addr;
624 rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
625 rxd_count[nic->rxd_mode],
626 GFP_KERNEL);
627 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
628 rx_blocks->rxds[l].virt_addr =
629 rx_blocks->block_virt_addr +
630 (rxd_size[nic->rxd_mode] * l);
631 rx_blocks->rxds[l].dma_addr =
632 rx_blocks->block_dma_addr +
633 (rxd_size[nic->rxd_mode] * l);
634 }
635 }
636 /* Interlinking all Rx Blocks */
637 for (j = 0; j < blk_cnt; j++) {
638 tmp_v_addr =
639 mac_control->rings[i].rx_blocks[j].block_virt_addr;
640 tmp_v_addr_next =
641 mac_control->rings[i].rx_blocks[(j + 1) %
642 blk_cnt].block_virt_addr;
643 tmp_p_addr =
644 mac_control->rings[i].rx_blocks[j].block_dma_addr;
645 tmp_p_addr_next =
646 mac_control->rings[i].rx_blocks[(j + 1) %
647 blk_cnt].block_dma_addr;
648
649 pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
650 pre_rxd_blk->reserved_2_pNext_RxD_block =
651 (unsigned long) tmp_v_addr_next;
652 pre_rxd_blk->pNext_RxD_Blk_physical =
653 (u64) tmp_p_addr_next;
654 }
655 }
656 if (nic->rxd_mode >= RXD_MODE_3A) {
657 /*
658 * Allocation of Storages for buffer addresses in 2BUFF mode
659 * and the buffers as well.
660 */
661 for (i = 0; i < config->rx_ring_num; i++) {
662 blk_cnt = config->rx_cfg[i].num_rxd /
663 (rxd_count[nic->rxd_mode]+ 1);
664 mac_control->rings[i].ba =
665 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
666 GFP_KERNEL);
667 if (!mac_control->rings[i].ba)
668 return -ENOMEM;
669 for (j = 0; j < blk_cnt; j++) {
670 int k = 0;
671 mac_control->rings[i].ba[j] =
672 kmalloc((sizeof(buffAdd_t) *
673 (rxd_count[nic->rxd_mode] + 1)),
674 GFP_KERNEL);
675 if (!mac_control->rings[i].ba[j])
676 return -ENOMEM;
677 while (k != rxd_count[nic->rxd_mode]) {
678 ba = &mac_control->rings[i].ba[j][k];
679
680 ba->ba_0_org = (void *) kmalloc
681 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
682 if (!ba->ba_0_org)
683 return -ENOMEM;
684 tmp = (unsigned long)ba->ba_0_org;
685 tmp += ALIGN_SIZE;
686 tmp &= ~((unsigned long) ALIGN_SIZE);
687 ba->ba_0 = (void *) tmp;
688
689 ba->ba_1_org = (void *) kmalloc
690 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
691 if (!ba->ba_1_org)
692 return -ENOMEM;
693 tmp = (unsigned long) ba->ba_1_org;
694 tmp += ALIGN_SIZE;
695 tmp &= ~((unsigned long) ALIGN_SIZE);
696 ba->ba_1 = (void *) tmp;
697 k++;
698 }
699 }
700 }
701 }
702
703 /* Allocation and initialization of Statistics block */
704 size = sizeof(StatInfo_t);
705 mac_control->stats_mem = pci_alloc_consistent
706 (nic->pdev, size, &mac_control->stats_mem_phy);
707
708 if (!mac_control->stats_mem) {
709 /*
710 * In case of failure, free_shared_mem() is called, which
711 * should free any memory that was alloced till the
712 * failure happened.
713 */
714 return -ENOMEM;
715 }
716 mac_control->stats_mem_sz = size;
717
718 tmp_v_addr = mac_control->stats_mem;
719 mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
720 memset(tmp_v_addr, 0, size);
721 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
722 (unsigned long long) tmp_p_addr);
723
724 return SUCCESS;
725 }
726
727 /**
728 * free_shared_mem - Free the allocated Memory
729 * @nic: Device private variable.
730 * Description: This function is to free all memory locations allocated by
731 * the init_shared_mem() function and return it to the kernel.
732 */
733
734 static void free_shared_mem(struct s2io_nic *nic)
735 {
736 int i, j, blk_cnt, size;
737 void *tmp_v_addr;
738 dma_addr_t tmp_p_addr;
739 mac_info_t *mac_control;
740 struct config_param *config;
741 int lst_size, lst_per_page;
742 struct net_device *dev = nic->dev;
743
744 if (!nic)
745 return;
746
747 mac_control = &nic->mac_control;
748 config = &nic->config;
749
750 lst_size = (sizeof(TxD_t) * config->max_txds);
751 lst_per_page = PAGE_SIZE / lst_size;
752
753 for (i = 0; i < config->tx_fifo_num; i++) {
754 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
755 lst_per_page);
756 for (j = 0; j < page_num; j++) {
757 int mem_blks = (j * lst_per_page);
758 if (!mac_control->fifos[i].list_info)
759 return;
760 if (!mac_control->fifos[i].list_info[mem_blks].
761 list_virt_addr)
762 break;
763 pci_free_consistent(nic->pdev, PAGE_SIZE,
764 mac_control->fifos[i].
765 list_info[mem_blks].
766 list_virt_addr,
767 mac_control->fifos[i].
768 list_info[mem_blks].
769 list_phy_addr);
770 }
771 /* If we got a zero DMA address during allocation,
772 * free the page now
773 */
774 if (mac_control->zerodma_virt_addr) {
775 pci_free_consistent(nic->pdev, PAGE_SIZE,
776 mac_control->zerodma_virt_addr,
777 (dma_addr_t)0);
778 DBG_PRINT(INIT_DBG,
779 "%s: Freeing TxDL with zero DMA addr. ",
780 dev->name);
781 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
782 mac_control->zerodma_virt_addr);
783 }
784 kfree(mac_control->fifos[i].list_info);
785 }
786
787 size = SIZE_OF_BLOCK;
788 for (i = 0; i < config->rx_ring_num; i++) {
789 blk_cnt = mac_control->rings[i].block_count;
790 for (j = 0; j < blk_cnt; j++) {
791 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
792 block_virt_addr;
793 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
794 block_dma_addr;
795 if (tmp_v_addr == NULL)
796 break;
797 pci_free_consistent(nic->pdev, size,
798 tmp_v_addr, tmp_p_addr);
799 kfree(mac_control->rings[i].rx_blocks[j].rxds);
800 }
801 }
802
803 if (nic->rxd_mode >= RXD_MODE_3A) {
804 /* Freeing buffer storage addresses in 2BUFF mode. */
805 for (i = 0; i < config->rx_ring_num; i++) {
806 blk_cnt = config->rx_cfg[i].num_rxd /
807 (rxd_count[nic->rxd_mode] + 1);
808 for (j = 0; j < blk_cnt; j++) {
809 int k = 0;
810 if (!mac_control->rings[i].ba[j])
811 continue;
812 while (k != rxd_count[nic->rxd_mode]) {
813 buffAdd_t *ba =
814 &mac_control->rings[i].ba[j][k];
815 kfree(ba->ba_0_org);
816 kfree(ba->ba_1_org);
817 k++;
818 }
819 kfree(mac_control->rings[i].ba[j]);
820 }
821 kfree(mac_control->rings[i].ba);
822 }
823 }
824
825 if (mac_control->stats_mem) {
826 pci_free_consistent(nic->pdev,
827 mac_control->stats_mem_sz,
828 mac_control->stats_mem,
829 mac_control->stats_mem_phy);
830 }
831 if (nic->ufo_in_band_v)
832 kfree(nic->ufo_in_band_v);
833 }
834
835 /**
836 * s2io_verify_pci_mode -
837 */
838
839 static int s2io_verify_pci_mode(nic_t *nic)
840 {
841 XENA_dev_config_t __iomem *bar0 = nic->bar0;
842 register u64 val64 = 0;
843 int mode;
844
845 val64 = readq(&bar0->pci_mode);
846 mode = (u8)GET_PCI_MODE(val64);
847
848 if ( val64 & PCI_MODE_UNKNOWN_MODE)
849 return -1; /* Unknown PCI mode */
850 return mode;
851 }
852
853 #define NEC_VENID 0x1033
854 #define NEC_DEVID 0x0125
855 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
856 {
857 struct pci_dev *tdev = NULL;
858 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
859 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
860 if (tdev->bus == s2io_pdev->bus->parent)
861 pci_dev_put(tdev);
862 return 1;
863 }
864 }
865 return 0;
866 }
867
868 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
869 /**
870 * s2io_print_pci_mode -
871 */
872 static int s2io_print_pci_mode(nic_t *nic)
873 {
874 XENA_dev_config_t __iomem *bar0 = nic->bar0;
875 register u64 val64 = 0;
876 int mode;
877 struct config_param *config = &nic->config;
878
879 val64 = readq(&bar0->pci_mode);
880 mode = (u8)GET_PCI_MODE(val64);
881
882 if ( val64 & PCI_MODE_UNKNOWN_MODE)
883 return -1; /* Unknown PCI mode */
884
885 config->bus_speed = bus_speed[mode];
886
887 if (s2io_on_nec_bridge(nic->pdev)) {
888 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
889 nic->dev->name);
890 return mode;
891 }
892
893 if (val64 & PCI_MODE_32_BITS) {
894 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
895 } else {
896 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
897 }
898
899 switch(mode) {
900 case PCI_MODE_PCI_33:
901 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
902 break;
903 case PCI_MODE_PCI_66:
904 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
905 break;
906 case PCI_MODE_PCIX_M1_66:
907 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
908 break;
909 case PCI_MODE_PCIX_M1_100:
910 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
911 break;
912 case PCI_MODE_PCIX_M1_133:
913 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
914 break;
915 case PCI_MODE_PCIX_M2_66:
916 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
917 break;
918 case PCI_MODE_PCIX_M2_100:
919 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
920 break;
921 case PCI_MODE_PCIX_M2_133:
922 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
923 break;
924 default:
925 return -1; /* Unsupported bus speed */
926 }
927
928 return mode;
929 }
930
931 /**
932 * init_nic - Initialization of hardware
933 * @nic: device peivate variable
934 * Description: The function sequentially configures every block
935 * of the H/W from their reset values.
936 * Return Value: SUCCESS on success and
937 * '-1' on failure (endian settings incorrect).
938 */
939
940 static int init_nic(struct s2io_nic *nic)
941 {
942 XENA_dev_config_t __iomem *bar0 = nic->bar0;
943 struct net_device *dev = nic->dev;
944 register u64 val64 = 0;
945 void __iomem *add;
946 u32 time;
947 int i, j;
948 mac_info_t *mac_control;
949 struct config_param *config;
950 int dtx_cnt = 0;
951 unsigned long long mem_share;
952 int mem_size;
953
954 mac_control = &nic->mac_control;
955 config = &nic->config;
956
957 /* to set the swapper controle on the card */
958 if(s2io_set_swapper(nic)) {
959 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
960 return -1;
961 }
962
963 /*
964 * Herc requires EOI to be removed from reset before XGXS, so..
965 */
966 if (nic->device_type & XFRAME_II_DEVICE) {
967 val64 = 0xA500000000ULL;
968 writeq(val64, &bar0->sw_reset);
969 msleep(500);
970 val64 = readq(&bar0->sw_reset);
971 }
972
973 /* Remove XGXS from reset state */
974 val64 = 0;
975 writeq(val64, &bar0->sw_reset);
976 msleep(500);
977 val64 = readq(&bar0->sw_reset);
978
979 /* Enable Receiving broadcasts */
980 add = &bar0->mac_cfg;
981 val64 = readq(&bar0->mac_cfg);
982 val64 |= MAC_RMAC_BCAST_ENABLE;
983 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
984 writel((u32) val64, add);
985 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
986 writel((u32) (val64 >> 32), (add + 4));
987
988 /* Read registers in all blocks */
989 val64 = readq(&bar0->mac_int_mask);
990 val64 = readq(&bar0->mc_int_mask);
991 val64 = readq(&bar0->xgxs_int_mask);
992
993 /* Set MTU */
994 val64 = dev->mtu;
995 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
996
997 if (nic->device_type & XFRAME_II_DEVICE) {
998 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
999 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1000 &bar0->dtx_control, UF);
1001 if (dtx_cnt & 0x1)
1002 msleep(1); /* Necessary!! */
1003 dtx_cnt++;
1004 }
1005 } else {
1006 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1007 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1008 &bar0->dtx_control, UF);
1009 val64 = readq(&bar0->dtx_control);
1010 dtx_cnt++;
1011 }
1012 }
1013
1014 /* Tx DMA Initialization */
1015 val64 = 0;
1016 writeq(val64, &bar0->tx_fifo_partition_0);
1017 writeq(val64, &bar0->tx_fifo_partition_1);
1018 writeq(val64, &bar0->tx_fifo_partition_2);
1019 writeq(val64, &bar0->tx_fifo_partition_3);
1020
1021
1022 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1023 val64 |=
1024 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1025 13) | vBIT(config->tx_cfg[i].fifo_priority,
1026 ((i * 32) + 5), 3);
1027
1028 if (i == (config->tx_fifo_num - 1)) {
1029 if (i % 2 == 0)
1030 i++;
1031 }
1032
1033 switch (i) {
1034 case 1:
1035 writeq(val64, &bar0->tx_fifo_partition_0);
1036 val64 = 0;
1037 break;
1038 case 3:
1039 writeq(val64, &bar0->tx_fifo_partition_1);
1040 val64 = 0;
1041 break;
1042 case 5:
1043 writeq(val64, &bar0->tx_fifo_partition_2);
1044 val64 = 0;
1045 break;
1046 case 7:
1047 writeq(val64, &bar0->tx_fifo_partition_3);
1048 break;
1049 }
1050 }
1051
1052 /*
1053 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1054 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1055 */
1056 if ((nic->device_type == XFRAME_I_DEVICE) &&
1057 (get_xena_rev_id(nic->pdev) < 4))
1058 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1059
1060 val64 = readq(&bar0->tx_fifo_partition_0);
1061 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1062 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1063
1064 /*
1065 * Initialization of Tx_PA_CONFIG register to ignore packet
1066 * integrity checking.
1067 */
1068 val64 = readq(&bar0->tx_pa_cfg);
1069 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1070 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1071 writeq(val64, &bar0->tx_pa_cfg);
1072
1073 /* Rx DMA intialization. */
1074 val64 = 0;
1075 for (i = 0; i < config->rx_ring_num; i++) {
1076 val64 |=
1077 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1078 3);
1079 }
1080 writeq(val64, &bar0->rx_queue_priority);
1081
1082 /*
1083 * Allocating equal share of memory to all the
1084 * configured Rings.
1085 */
1086 val64 = 0;
1087 if (nic->device_type & XFRAME_II_DEVICE)
1088 mem_size = 32;
1089 else
1090 mem_size = 64;
1091
1092 for (i = 0; i < config->rx_ring_num; i++) {
1093 switch (i) {
1094 case 0:
1095 mem_share = (mem_size / config->rx_ring_num +
1096 mem_size % config->rx_ring_num);
1097 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1098 continue;
1099 case 1:
1100 mem_share = (mem_size / config->rx_ring_num);
1101 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1102 continue;
1103 case 2:
1104 mem_share = (mem_size / config->rx_ring_num);
1105 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1106 continue;
1107 case 3:
1108 mem_share = (mem_size / config->rx_ring_num);
1109 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1110 continue;
1111 case 4:
1112 mem_share = (mem_size / config->rx_ring_num);
1113 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1114 continue;
1115 case 5:
1116 mem_share = (mem_size / config->rx_ring_num);
1117 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1118 continue;
1119 case 6:
1120 mem_share = (mem_size / config->rx_ring_num);
1121 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1122 continue;
1123 case 7:
1124 mem_share = (mem_size / config->rx_ring_num);
1125 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1126 continue;
1127 }
1128 }
1129 writeq(val64, &bar0->rx_queue_cfg);
1130
1131 /*
1132 * Filling Tx round robin registers
1133 * as per the number of FIFOs
1134 */
1135 switch (config->tx_fifo_num) {
1136 case 1:
1137 val64 = 0x0000000000000000ULL;
1138 writeq(val64, &bar0->tx_w_round_robin_0);
1139 writeq(val64, &bar0->tx_w_round_robin_1);
1140 writeq(val64, &bar0->tx_w_round_robin_2);
1141 writeq(val64, &bar0->tx_w_round_robin_3);
1142 writeq(val64, &bar0->tx_w_round_robin_4);
1143 break;
1144 case 2:
1145 val64 = 0x0000010000010000ULL;
1146 writeq(val64, &bar0->tx_w_round_robin_0);
1147 val64 = 0x0100000100000100ULL;
1148 writeq(val64, &bar0->tx_w_round_robin_1);
1149 val64 = 0x0001000001000001ULL;
1150 writeq(val64, &bar0->tx_w_round_robin_2);
1151 val64 = 0x0000010000010000ULL;
1152 writeq(val64, &bar0->tx_w_round_robin_3);
1153 val64 = 0x0100000000000000ULL;
1154 writeq(val64, &bar0->tx_w_round_robin_4);
1155 break;
1156 case 3:
1157 val64 = 0x0001000102000001ULL;
1158 writeq(val64, &bar0->tx_w_round_robin_0);
1159 val64 = 0x0001020000010001ULL;
1160 writeq(val64, &bar0->tx_w_round_robin_1);
1161 val64 = 0x0200000100010200ULL;
1162 writeq(val64, &bar0->tx_w_round_robin_2);
1163 val64 = 0x0001000102000001ULL;
1164 writeq(val64, &bar0->tx_w_round_robin_3);
1165 val64 = 0x0001020000000000ULL;
1166 writeq(val64, &bar0->tx_w_round_robin_4);
1167 break;
1168 case 4:
1169 val64 = 0x0001020300010200ULL;
1170 writeq(val64, &bar0->tx_w_round_robin_0);
1171 val64 = 0x0100000102030001ULL;
1172 writeq(val64, &bar0->tx_w_round_robin_1);
1173 val64 = 0x0200010000010203ULL;
1174 writeq(val64, &bar0->tx_w_round_robin_2);
1175 val64 = 0x0001020001000001ULL;
1176 writeq(val64, &bar0->tx_w_round_robin_3);
1177 val64 = 0x0203000100000000ULL;
1178 writeq(val64, &bar0->tx_w_round_robin_4);
1179 break;
1180 case 5:
1181 val64 = 0x0001000203000102ULL;
1182 writeq(val64, &bar0->tx_w_round_robin_0);
1183 val64 = 0x0001020001030004ULL;
1184 writeq(val64, &bar0->tx_w_round_robin_1);
1185 val64 = 0x0001000203000102ULL;
1186 writeq(val64, &bar0->tx_w_round_robin_2);
1187 val64 = 0x0001020001030004ULL;
1188 writeq(val64, &bar0->tx_w_round_robin_3);
1189 val64 = 0x0001000000000000ULL;
1190 writeq(val64, &bar0->tx_w_round_robin_4);
1191 break;
1192 case 6:
1193 val64 = 0x0001020304000102ULL;
1194 writeq(val64, &bar0->tx_w_round_robin_0);
1195 val64 = 0x0304050001020001ULL;
1196 writeq(val64, &bar0->tx_w_round_robin_1);
1197 val64 = 0x0203000100000102ULL;
1198 writeq(val64, &bar0->tx_w_round_robin_2);
1199 val64 = 0x0304000102030405ULL;
1200 writeq(val64, &bar0->tx_w_round_robin_3);
1201 val64 = 0x0001000200000000ULL;
1202 writeq(val64, &bar0->tx_w_round_robin_4);
1203 break;
1204 case 7:
1205 val64 = 0x0001020001020300ULL;
1206 writeq(val64, &bar0->tx_w_round_robin_0);
1207 val64 = 0x0102030400010203ULL;
1208 writeq(val64, &bar0->tx_w_round_robin_1);
1209 val64 = 0x0405060001020001ULL;
1210 writeq(val64, &bar0->tx_w_round_robin_2);
1211 val64 = 0x0304050000010200ULL;
1212 writeq(val64, &bar0->tx_w_round_robin_3);
1213 val64 = 0x0102030000000000ULL;
1214 writeq(val64, &bar0->tx_w_round_robin_4);
1215 break;
1216 case 8:
1217 val64 = 0x0001020300040105ULL;
1218 writeq(val64, &bar0->tx_w_round_robin_0);
1219 val64 = 0x0200030106000204ULL;
1220 writeq(val64, &bar0->tx_w_round_robin_1);
1221 val64 = 0x0103000502010007ULL;
1222 writeq(val64, &bar0->tx_w_round_robin_2);
1223 val64 = 0x0304010002060500ULL;
1224 writeq(val64, &bar0->tx_w_round_robin_3);
1225 val64 = 0x0103020400000000ULL;
1226 writeq(val64, &bar0->tx_w_round_robin_4);
1227 break;
1228 }
1229
1230 /* Enable all configured Tx FIFO partitions */
1231 val64 = readq(&bar0->tx_fifo_partition_0);
1232 val64 |= (TX_FIFO_PARTITION_EN);
1233 writeq(val64, &bar0->tx_fifo_partition_0);
1234
1235 /* Filling the Rx round robin registers as per the
1236 * number of Rings and steering based on QoS.
1237 */
1238 switch (config->rx_ring_num) {
1239 case 1:
1240 val64 = 0x8080808080808080ULL;
1241 writeq(val64, &bar0->rts_qos_steering);
1242 break;
1243 case 2:
1244 val64 = 0x0000010000010000ULL;
1245 writeq(val64, &bar0->rx_w_round_robin_0);
1246 val64 = 0x0100000100000100ULL;
1247 writeq(val64, &bar0->rx_w_round_robin_1);
1248 val64 = 0x0001000001000001ULL;
1249 writeq(val64, &bar0->rx_w_round_robin_2);
1250 val64 = 0x0000010000010000ULL;
1251 writeq(val64, &bar0->rx_w_round_robin_3);
1252 val64 = 0x0100000000000000ULL;
1253 writeq(val64, &bar0->rx_w_round_robin_4);
1254
1255 val64 = 0x8080808040404040ULL;
1256 writeq(val64, &bar0->rts_qos_steering);
1257 break;
1258 case 3:
1259 val64 = 0x0001000102000001ULL;
1260 writeq(val64, &bar0->rx_w_round_robin_0);
1261 val64 = 0x0001020000010001ULL;
1262 writeq(val64, &bar0->rx_w_round_robin_1);
1263 val64 = 0x0200000100010200ULL;
1264 writeq(val64, &bar0->rx_w_round_robin_2);
1265 val64 = 0x0001000102000001ULL;
1266 writeq(val64, &bar0->rx_w_round_robin_3);
1267 val64 = 0x0001020000000000ULL;
1268 writeq(val64, &bar0->rx_w_round_robin_4);
1269
1270 val64 = 0x8080804040402020ULL;
1271 writeq(val64, &bar0->rts_qos_steering);
1272 break;
1273 case 4:
1274 val64 = 0x0001020300010200ULL;
1275 writeq(val64, &bar0->rx_w_round_robin_0);
1276 val64 = 0x0100000102030001ULL;
1277 writeq(val64, &bar0->rx_w_round_robin_1);
1278 val64 = 0x0200010000010203ULL;
1279 writeq(val64, &bar0->rx_w_round_robin_2);
1280 val64 = 0x0001020001000001ULL;
1281 writeq(val64, &bar0->rx_w_round_robin_3);
1282 val64 = 0x0203000100000000ULL;
1283 writeq(val64, &bar0->rx_w_round_robin_4);
1284
1285 val64 = 0x8080404020201010ULL;
1286 writeq(val64, &bar0->rts_qos_steering);
1287 break;
1288 case 5:
1289 val64 = 0x0001000203000102ULL;
1290 writeq(val64, &bar0->rx_w_round_robin_0);
1291 val64 = 0x0001020001030004ULL;
1292 writeq(val64, &bar0->rx_w_round_robin_1);
1293 val64 = 0x0001000203000102ULL;
1294 writeq(val64, &bar0->rx_w_round_robin_2);
1295 val64 = 0x0001020001030004ULL;
1296 writeq(val64, &bar0->rx_w_round_robin_3);
1297 val64 = 0x0001000000000000ULL;
1298 writeq(val64, &bar0->rx_w_round_robin_4);
1299
1300 val64 = 0x8080404020201008ULL;
1301 writeq(val64, &bar0->rts_qos_steering);
1302 break;
1303 case 6:
1304 val64 = 0x0001020304000102ULL;
1305 writeq(val64, &bar0->rx_w_round_robin_0);
1306 val64 = 0x0304050001020001ULL;
1307 writeq(val64, &bar0->rx_w_round_robin_1);
1308 val64 = 0x0203000100000102ULL;
1309 writeq(val64, &bar0->rx_w_round_robin_2);
1310 val64 = 0x0304000102030405ULL;
1311 writeq(val64, &bar0->rx_w_round_robin_3);
1312 val64 = 0x0001000200000000ULL;
1313 writeq(val64, &bar0->rx_w_round_robin_4);
1314
1315 val64 = 0x8080404020100804ULL;
1316 writeq(val64, &bar0->rts_qos_steering);
1317 break;
1318 case 7:
1319 val64 = 0x0001020001020300ULL;
1320 writeq(val64, &bar0->rx_w_round_robin_0);
1321 val64 = 0x0102030400010203ULL;
1322 writeq(val64, &bar0->rx_w_round_robin_1);
1323 val64 = 0x0405060001020001ULL;
1324 writeq(val64, &bar0->rx_w_round_robin_2);
1325 val64 = 0x0304050000010200ULL;
1326 writeq(val64, &bar0->rx_w_round_robin_3);
1327 val64 = 0x0102030000000000ULL;
1328 writeq(val64, &bar0->rx_w_round_robin_4);
1329
1330 val64 = 0x8080402010080402ULL;
1331 writeq(val64, &bar0->rts_qos_steering);
1332 break;
1333 case 8:
1334 val64 = 0x0001020300040105ULL;
1335 writeq(val64, &bar0->rx_w_round_robin_0);
1336 val64 = 0x0200030106000204ULL;
1337 writeq(val64, &bar0->rx_w_round_robin_1);
1338 val64 = 0x0103000502010007ULL;
1339 writeq(val64, &bar0->rx_w_round_robin_2);
1340 val64 = 0x0304010002060500ULL;
1341 writeq(val64, &bar0->rx_w_round_robin_3);
1342 val64 = 0x0103020400000000ULL;
1343 writeq(val64, &bar0->rx_w_round_robin_4);
1344
1345 val64 = 0x8040201008040201ULL;
1346 writeq(val64, &bar0->rts_qos_steering);
1347 break;
1348 }
1349
1350 /* UDP Fix */
1351 val64 = 0;
1352 for (i = 0; i < 8; i++)
1353 writeq(val64, &bar0->rts_frm_len_n[i]);
1354
1355 /* Set the default rts frame length for the rings configured */
1356 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1357 for (i = 0 ; i < config->rx_ring_num ; i++)
1358 writeq(val64, &bar0->rts_frm_len_n[i]);
1359
1360 /* Set the frame length for the configured rings
1361 * desired by the user
1362 */
1363 for (i = 0; i < config->rx_ring_num; i++) {
1364 /* If rts_frm_len[i] == 0 then it is assumed that user not
1365 * specified frame length steering.
1366 * If the user provides the frame length then program
1367 * the rts_frm_len register for those values or else
1368 * leave it as it is.
1369 */
1370 if (rts_frm_len[i] != 0) {
1371 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1372 &bar0->rts_frm_len_n[i]);
1373 }
1374 }
1375
1376 /* Program statistics memory */
1377 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1378
1379 if (nic->device_type == XFRAME_II_DEVICE) {
1380 val64 = STAT_BC(0x320);
1381 writeq(val64, &bar0->stat_byte_cnt);
1382 }
1383
1384 /*
1385 * Initializing the sampling rate for the device to calculate the
1386 * bandwidth utilization.
1387 */
1388 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1389 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1390 writeq(val64, &bar0->mac_link_util);
1391
1392
1393 /*
1394 * Initializing the Transmit and Receive Traffic Interrupt
1395 * Scheme.
1396 */
1397 /*
1398 * TTI Initialization. Default Tx timer gets us about
1399 * 250 interrupts per sec. Continuous interrupts are enabled
1400 * by default.
1401 */
1402 if (nic->device_type == XFRAME_II_DEVICE) {
1403 int count = (nic->config.bus_speed * 125)/2;
1404 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1405 } else {
1406
1407 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1408 }
1409 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1410 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1411 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1412 if (use_continuous_tx_intrs)
1413 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1414 writeq(val64, &bar0->tti_data1_mem);
1415
1416 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1417 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1418 TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1419 writeq(val64, &bar0->tti_data2_mem);
1420
1421 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1422 writeq(val64, &bar0->tti_command_mem);
1423
1424 /*
1425 * Once the operation completes, the Strobe bit of the command
1426 * register will be reset. We poll for this particular condition
1427 * We wait for a maximum of 500ms for the operation to complete,
1428 * if it's not complete by then we return error.
1429 */
1430 time = 0;
1431 while (TRUE) {
1432 val64 = readq(&bar0->tti_command_mem);
1433 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1434 break;
1435 }
1436 if (time > 10) {
1437 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1438 dev->name);
1439 return -1;
1440 }
1441 msleep(50);
1442 time++;
1443 }
1444
1445 if (nic->config.bimodal) {
1446 int k = 0;
1447 for (k = 0; k < config->rx_ring_num; k++) {
1448 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1449 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1450 writeq(val64, &bar0->tti_command_mem);
1451
1452 /*
1453 * Once the operation completes, the Strobe bit of the command
1454 * register will be reset. We poll for this particular condition
1455 * We wait for a maximum of 500ms for the operation to complete,
1456 * if it's not complete by then we return error.
1457 */
1458 time = 0;
1459 while (TRUE) {
1460 val64 = readq(&bar0->tti_command_mem);
1461 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1462 break;
1463 }
1464 if (time > 10) {
1465 DBG_PRINT(ERR_DBG,
1466 "%s: TTI init Failed\n",
1467 dev->name);
1468 return -1;
1469 }
1470 time++;
1471 msleep(50);
1472 }
1473 }
1474 } else {
1475
1476 /* RTI Initialization */
1477 if (nic->device_type == XFRAME_II_DEVICE) {
1478 /*
1479 * Programmed to generate Apprx 500 Intrs per
1480 * second
1481 */
1482 int count = (nic->config.bus_speed * 125)/4;
1483 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1484 } else {
1485 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1486 }
1487 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1488 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1489 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1490
1491 writeq(val64, &bar0->rti_data1_mem);
1492
1493 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1494 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1495 if (nic->intr_type == MSI_X)
1496 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1497 RTI_DATA2_MEM_RX_UFC_D(0x40));
1498 else
1499 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1500 RTI_DATA2_MEM_RX_UFC_D(0x80));
1501 writeq(val64, &bar0->rti_data2_mem);
1502
1503 for (i = 0; i < config->rx_ring_num; i++) {
1504 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1505 | RTI_CMD_MEM_OFFSET(i);
1506 writeq(val64, &bar0->rti_command_mem);
1507
1508 /*
1509 * Once the operation completes, the Strobe bit of the
1510 * command register will be reset. We poll for this
1511 * particular condition. We wait for a maximum of 500ms
1512 * for the operation to complete, if it's not complete
1513 * by then we return error.
1514 */
1515 time = 0;
1516 while (TRUE) {
1517 val64 = readq(&bar0->rti_command_mem);
1518 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1519 break;
1520 }
1521 if (time > 10) {
1522 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1523 dev->name);
1524 return -1;
1525 }
1526 time++;
1527 msleep(50);
1528 }
1529 }
1530 }
1531
1532 /*
1533 * Initializing proper values as Pause threshold into all
1534 * the 8 Queues on Rx side.
1535 */
1536 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1537 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1538
1539 /* Disable RMAC PAD STRIPPING */
1540 add = &bar0->mac_cfg;
1541 val64 = readq(&bar0->mac_cfg);
1542 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1543 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1544 writel((u32) (val64), add);
1545 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1546 writel((u32) (val64 >> 32), (add + 4));
1547 val64 = readq(&bar0->mac_cfg);
1548
1549 /* Enable FCS stripping by adapter */
1550 add = &bar0->mac_cfg;
1551 val64 = readq(&bar0->mac_cfg);
1552 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1553 if (nic->device_type == XFRAME_II_DEVICE)
1554 writeq(val64, &bar0->mac_cfg);
1555 else {
1556 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1557 writel((u32) (val64), add);
1558 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1559 writel((u32) (val64 >> 32), (add + 4));
1560 }
1561
1562 /*
1563 * Set the time value to be inserted in the pause frame
1564 * generated by xena.
1565 */
1566 val64 = readq(&bar0->rmac_pause_cfg);
1567 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1568 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1569 writeq(val64, &bar0->rmac_pause_cfg);
1570
1571 /*
1572 * Set the Threshold Limit for Generating the pause frame
1573 * If the amount of data in any Queue exceeds ratio of
1574 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1575 * pause frame is generated
1576 */
1577 val64 = 0;
1578 for (i = 0; i < 4; i++) {
1579 val64 |=
1580 (((u64) 0xFF00 | nic->mac_control.
1581 mc_pause_threshold_q0q3)
1582 << (i * 2 * 8));
1583 }
1584 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1585
1586 val64 = 0;
1587 for (i = 0; i < 4; i++) {
1588 val64 |=
1589 (((u64) 0xFF00 | nic->mac_control.
1590 mc_pause_threshold_q4q7)
1591 << (i * 2 * 8));
1592 }
1593 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1594
1595 /*
1596 * TxDMA will stop Read request if the number of read split has
1597 * exceeded the limit pointed by shared_splits
1598 */
1599 val64 = readq(&bar0->pic_control);
1600 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1601 writeq(val64, &bar0->pic_control);
1602
1603 if (nic->config.bus_speed == 266) {
1604 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1605 writeq(0x0, &bar0->read_retry_delay);
1606 writeq(0x0, &bar0->write_retry_delay);
1607 }
1608
1609 /*
1610 * Programming the Herc to split every write transaction
1611 * that does not start on an ADB to reduce disconnects.
1612 */
1613 if (nic->device_type == XFRAME_II_DEVICE) {
1614 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1615 writeq(val64, &bar0->misc_control);
1616 val64 = readq(&bar0->pic_control2);
1617 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1618 writeq(val64, &bar0->pic_control2);
1619 }
1620 if (strstr(nic->product_name, "CX4")) {
1621 val64 = TMAC_AVG_IPG(0x17);
1622 writeq(val64, &bar0->tmac_avg_ipg);
1623 }
1624
1625 return SUCCESS;
1626 }
1627 #define LINK_UP_DOWN_INTERRUPT 1
1628 #define MAC_RMAC_ERR_TIMER 2
1629
1630 static int s2io_link_fault_indication(nic_t *nic)
1631 {
1632 if (nic->intr_type != INTA)
1633 return MAC_RMAC_ERR_TIMER;
1634 if (nic->device_type == XFRAME_II_DEVICE)
1635 return LINK_UP_DOWN_INTERRUPT;
1636 else
1637 return MAC_RMAC_ERR_TIMER;
1638 }
1639
1640 /**
1641 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1642 * @nic: device private variable,
1643 * @mask: A mask indicating which Intr block must be modified and,
1644 * @flag: A flag indicating whether to enable or disable the Intrs.
1645 * Description: This function will either disable or enable the interrupts
1646 * depending on the flag argument. The mask argument can be used to
1647 * enable/disable any Intr block.
1648 * Return Value: NONE.
1649 */
1650
1651 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1652 {
1653 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1654 register u64 val64 = 0, temp64 = 0;
1655
1656 /* Top level interrupt classification */
1657 /* PIC Interrupts */
1658 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1659 /* Enable PIC Intrs in the general intr mask register */
1660 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1661 if (flag == ENABLE_INTRS) {
1662 temp64 = readq(&bar0->general_int_mask);
1663 temp64 &= ~((u64) val64);
1664 writeq(temp64, &bar0->general_int_mask);
1665 /*
1666 * If Hercules adapter enable GPIO otherwise
1667 * disable all PCIX, Flash, MDIO, IIC and GPIO
1668 * interrupts for now.
1669 * TODO
1670 */
1671 if (s2io_link_fault_indication(nic) ==
1672 LINK_UP_DOWN_INTERRUPT ) {
1673 temp64 = readq(&bar0->pic_int_mask);
1674 temp64 &= ~((u64) PIC_INT_GPIO);
1675 writeq(temp64, &bar0->pic_int_mask);
1676 temp64 = readq(&bar0->gpio_int_mask);
1677 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1678 writeq(temp64, &bar0->gpio_int_mask);
1679 } else {
1680 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1681 }
1682 /*
1683 * No MSI Support is available presently, so TTI and
1684 * RTI interrupts are also disabled.
1685 */
1686 } else if (flag == DISABLE_INTRS) {
1687 /*
1688 * Disable PIC Intrs in the general
1689 * intr mask register
1690 */
1691 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1692 temp64 = readq(&bar0->general_int_mask);
1693 val64 |= temp64;
1694 writeq(val64, &bar0->general_int_mask);
1695 }
1696 }
1697
1698 /* DMA Interrupts */
1699 /* Enabling/Disabling Tx DMA interrupts */
1700 if (mask & TX_DMA_INTR) {
1701 /* Enable TxDMA Intrs in the general intr mask register */
1702 val64 = TXDMA_INT_M;
1703 if (flag == ENABLE_INTRS) {
1704 temp64 = readq(&bar0->general_int_mask);
1705 temp64 &= ~((u64) val64);
1706 writeq(temp64, &bar0->general_int_mask);
1707 /*
1708 * Keep all interrupts other than PFC interrupt
1709 * and PCC interrupt disabled in DMA level.
1710 */
1711 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1712 TXDMA_PCC_INT_M);
1713 writeq(val64, &bar0->txdma_int_mask);
1714 /*
1715 * Enable only the MISC error 1 interrupt in PFC block
1716 */
1717 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1718 writeq(val64, &bar0->pfc_err_mask);
1719 /*
1720 * Enable only the FB_ECC error interrupt in PCC block
1721 */
1722 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1723 writeq(val64, &bar0->pcc_err_mask);
1724 } else if (flag == DISABLE_INTRS) {
1725 /*
1726 * Disable TxDMA Intrs in the general intr mask
1727 * register
1728 */
1729 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1730 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1731 temp64 = readq(&bar0->general_int_mask);
1732 val64 |= temp64;
1733 writeq(val64, &bar0->general_int_mask);
1734 }
1735 }
1736
1737 /* Enabling/Disabling Rx DMA interrupts */
1738 if (mask & RX_DMA_INTR) {
1739 /* Enable RxDMA Intrs in the general intr mask register */
1740 val64 = RXDMA_INT_M;
1741 if (flag == ENABLE_INTRS) {
1742 temp64 = readq(&bar0->general_int_mask);
1743 temp64 &= ~((u64) val64);
1744 writeq(temp64, &bar0->general_int_mask);
1745 /*
1746 * All RxDMA block interrupts are disabled for now
1747 * TODO
1748 */
1749 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1750 } else if (flag == DISABLE_INTRS) {
1751 /*
1752 * Disable RxDMA Intrs in the general intr mask
1753 * register
1754 */
1755 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1756 temp64 = readq(&bar0->general_int_mask);
1757 val64 |= temp64;
1758 writeq(val64, &bar0->general_int_mask);
1759 }
1760 }
1761
1762 /* MAC Interrupts */
1763 /* Enabling/Disabling MAC interrupts */
1764 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1765 val64 = TXMAC_INT_M | RXMAC_INT_M;
1766 if (flag == ENABLE_INTRS) {
1767 temp64 = readq(&bar0->general_int_mask);
1768 temp64 &= ~((u64) val64);
1769 writeq(temp64, &bar0->general_int_mask);
1770 /*
1771 * All MAC block error interrupts are disabled for now
1772 * TODO
1773 */
1774 } else if (flag == DISABLE_INTRS) {
1775 /*
1776 * Disable MAC Intrs in the general intr mask register
1777 */
1778 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1779 writeq(DISABLE_ALL_INTRS,
1780 &bar0->mac_rmac_err_mask);
1781
1782 temp64 = readq(&bar0->general_int_mask);
1783 val64 |= temp64;
1784 writeq(val64, &bar0->general_int_mask);
1785 }
1786 }
1787
1788 /* XGXS Interrupts */
1789 if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1790 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1791 if (flag == ENABLE_INTRS) {
1792 temp64 = readq(&bar0->general_int_mask);
1793 temp64 &= ~((u64) val64);
1794 writeq(temp64, &bar0->general_int_mask);
1795 /*
1796 * All XGXS block error interrupts are disabled for now
1797 * TODO
1798 */
1799 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1800 } else if (flag == DISABLE_INTRS) {
1801 /*
1802 * Disable MC Intrs in the general intr mask register
1803 */
1804 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1805 temp64 = readq(&bar0->general_int_mask);
1806 val64 |= temp64;
1807 writeq(val64, &bar0->general_int_mask);
1808 }
1809 }
1810
1811 /* Memory Controller(MC) interrupts */
1812 if (mask & MC_INTR) {
1813 val64 = MC_INT_M;
1814 if (flag == ENABLE_INTRS) {
1815 temp64 = readq(&bar0->general_int_mask);
1816 temp64 &= ~((u64) val64);
1817 writeq(temp64, &bar0->general_int_mask);
1818 /*
1819 * Enable all MC Intrs.
1820 */
1821 writeq(0x0, &bar0->mc_int_mask);
1822 writeq(0x0, &bar0->mc_err_mask);
1823 } else if (flag == DISABLE_INTRS) {
1824 /*
1825 * Disable MC Intrs in the general intr mask register
1826 */
1827 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1828 temp64 = readq(&bar0->general_int_mask);
1829 val64 |= temp64;
1830 writeq(val64, &bar0->general_int_mask);
1831 }
1832 }
1833
1834
1835 /* Tx traffic interrupts */
1836 if (mask & TX_TRAFFIC_INTR) {
1837 val64 = TXTRAFFIC_INT_M;
1838 if (flag == ENABLE_INTRS) {
1839 temp64 = readq(&bar0->general_int_mask);
1840 temp64 &= ~((u64) val64);
1841 writeq(temp64, &bar0->general_int_mask);
1842 /*
1843 * Enable all the Tx side interrupts
1844 * writing 0 Enables all 64 TX interrupt levels
1845 */
1846 writeq(0x0, &bar0->tx_traffic_mask);
1847 } else if (flag == DISABLE_INTRS) {
1848 /*
1849 * Disable Tx Traffic Intrs in the general intr mask
1850 * register.
1851 */
1852 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1853 temp64 = readq(&bar0->general_int_mask);
1854 val64 |= temp64;
1855 writeq(val64, &bar0->general_int_mask);
1856 }
1857 }
1858
1859 /* Rx traffic interrupts */
1860 if (mask & RX_TRAFFIC_INTR) {
1861 val64 = RXTRAFFIC_INT_M;
1862 if (flag == ENABLE_INTRS) {
1863 temp64 = readq(&bar0->general_int_mask);
1864 temp64 &= ~((u64) val64);
1865 writeq(temp64, &bar0->general_int_mask);
1866 /* writing 0 Enables all 8 RX interrupt levels */
1867 writeq(0x0, &bar0->rx_traffic_mask);
1868 } else if (flag == DISABLE_INTRS) {
1869 /*
1870 * Disable Rx Traffic Intrs in the general intr mask
1871 * register.
1872 */
1873 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1874 temp64 = readq(&bar0->general_int_mask);
1875 val64 |= temp64;
1876 writeq(val64, &bar0->general_int_mask);
1877 }
1878 }
1879 }
1880
1881 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1882 {
1883 int ret = 0;
1884
1885 if (flag == FALSE) {
1886 if ((!herc && (rev_id >= 4)) || herc) {
1887 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1888 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1889 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1890 ret = 1;
1891 }
1892 }else {
1893 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1894 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1895 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1896 ret = 1;
1897 }
1898 }
1899 } else {
1900 if ((!herc && (rev_id >= 4)) || herc) {
1901 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1902 ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1903 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1904 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1905 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1906 ret = 1;
1907 }
1908 } else {
1909 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1910 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1911 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1912 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1913 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1914 ret = 1;
1915 }
1916 }
1917 }
1918
1919 return ret;
1920 }
1921 /**
1922 * verify_xena_quiescence - Checks whether the H/W is ready
1923 * @val64 : Value read from adapter status register.
1924 * @flag : indicates if the adapter enable bit was ever written once
1925 * before.
1926 * Description: Returns whether the H/W is ready to go or not. Depending
1927 * on whether adapter enable bit was written or not the comparison
1928 * differs and the calling function passes the input argument flag to
1929 * indicate this.
1930 * Return: 1 If xena is quiescence
1931 * 0 If Xena is not quiescence
1932 */
1933
1934 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1935 {
1936 int ret = 0, herc;
1937 u64 tmp64 = ~((u64) val64);
1938 int rev_id = get_xena_rev_id(sp->pdev);
1939
1940 herc = (sp->device_type == XFRAME_II_DEVICE);
1941 if (!
1942 (tmp64 &
1943 (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1944 ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1945 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1946 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1947 ADAPTER_STATUS_P_PLL_LOCK))) {
1948 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1949 }
1950
1951 return ret;
1952 }
1953
1954 /**
1955 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1956 * @sp: Pointer to device specifc structure
1957 * Description :
1958 * New procedure to clear mac address reading problems on Alpha platforms
1959 *
1960 */
1961
1962 static void fix_mac_address(nic_t * sp)
1963 {
1964 XENA_dev_config_t __iomem *bar0 = sp->bar0;
1965 u64 val64;
1966 int i = 0;
1967
1968 while (fix_mac[i] != END_SIGN) {
1969 writeq(fix_mac[i++], &bar0->gpio_control);
1970 udelay(10);
1971 val64 = readq(&bar0->gpio_control);
1972 }
1973 }
1974
1975 /**
1976 * start_nic - Turns the device on
1977 * @nic : device private variable.
1978 * Description:
1979 * This function actually turns the device on. Before this function is
1980 * called,all Registers are configured from their reset states
1981 * and shared memory is allocated but the NIC is still quiescent. On
1982 * calling this function, the device interrupts are cleared and the NIC is
1983 * literally switched on by writing into the adapter control register.
1984 * Return Value:
1985 * SUCCESS on success and -1 on failure.
1986 */
1987
1988 static int start_nic(struct s2io_nic *nic)
1989 {
1990 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1991 struct net_device *dev = nic->dev;
1992 register u64 val64 = 0;
1993 u16 subid, i;
1994 mac_info_t *mac_control;
1995 struct config_param *config;
1996
1997 mac_control = &nic->mac_control;
1998 config = &nic->config;
1999
2000 /* PRC Initialization and configuration */
2001 for (i = 0; i < config->rx_ring_num; i++) {
2002 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2003 &bar0->prc_rxd0_n[i]);
2004
2005 val64 = readq(&bar0->prc_ctrl_n[i]);
2006 if (nic->config.bimodal)
2007 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2008 if (nic->rxd_mode == RXD_MODE_1)
2009 val64 |= PRC_CTRL_RC_ENABLED;
2010 else
2011 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2012 if (nic->device_type == XFRAME_II_DEVICE)
2013 val64 |= PRC_CTRL_GROUP_READS;
2014 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2015 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2016 writeq(val64, &bar0->prc_ctrl_n[i]);
2017 }
2018
2019 if (nic->rxd_mode == RXD_MODE_3B) {
2020 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2021 val64 = readq(&bar0->rx_pa_cfg);
2022 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2023 writeq(val64, &bar0->rx_pa_cfg);
2024 }
2025
2026 /*
2027 * Enabling MC-RLDRAM. After enabling the device, we timeout
2028 * for around 100ms, which is approximately the time required
2029 * for the device to be ready for operation.
2030 */
2031 val64 = readq(&bar0->mc_rldram_mrs);
2032 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2033 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2034 val64 = readq(&bar0->mc_rldram_mrs);
2035
2036 msleep(100); /* Delay by around 100 ms. */
2037
2038 /* Enabling ECC Protection. */
2039 val64 = readq(&bar0->adapter_control);
2040 val64 &= ~ADAPTER_ECC_EN;
2041 writeq(val64, &bar0->adapter_control);
2042
2043 /*
2044 * Clearing any possible Link state change interrupts that
2045 * could have popped up just before Enabling the card.
2046 */
2047 val64 = readq(&bar0->mac_rmac_err_reg);
2048 if (val64)
2049 writeq(val64, &bar0->mac_rmac_err_reg);
2050
2051 /*
2052 * Verify if the device is ready to be enabled, if so enable
2053 * it.
2054 */
2055 val64 = readq(&bar0->adapter_status);
2056 if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
2057 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2058 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2059 (unsigned long long) val64);
2060 return FAILURE;
2061 }
2062
2063 /*
2064 * With some switches, link might be already up at this point.
2065 * Because of this weird behavior, when we enable laser,
2066 * we may not get link. We need to handle this. We cannot
2067 * figure out which switch is misbehaving. So we are forced to
2068 * make a global change.
2069 */
2070
2071 /* Enabling Laser. */
2072 val64 = readq(&bar0->adapter_control);
2073 val64 |= ADAPTER_EOI_TX_ON;
2074 writeq(val64, &bar0->adapter_control);
2075
2076 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2077 /*
2078 * Dont see link state interrupts initally on some switches,
2079 * so directly scheduling the link state task here.
2080 */
2081 schedule_work(&nic->set_link_task);
2082 }
2083 /* SXE-002: Initialize link and activity LED */
2084 subid = nic->pdev->subsystem_device;
2085 if (((subid & 0xFF) >= 0x07) &&
2086 (nic->device_type == XFRAME_I_DEVICE)) {
2087 val64 = readq(&bar0->gpio_control);
2088 val64 |= 0x0000800000000000ULL;
2089 writeq(val64, &bar0->gpio_control);
2090 val64 = 0x0411040400000000ULL;
2091 writeq(val64, (void __iomem *)bar0 + 0x2700);
2092 }
2093
2094 return SUCCESS;
2095 }
2096 /**
2097 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2098 */
2099 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2100 {
2101 nic_t *nic = fifo_data->nic;
2102 struct sk_buff *skb;
2103 TxD_t *txds;
2104 u16 j, frg_cnt;
2105
2106 txds = txdlp;
2107 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2108 pci_unmap_single(nic->pdev, (dma_addr_t)
2109 txds->Buffer_Pointer, sizeof(u64),
2110 PCI_DMA_TODEVICE);
2111 txds++;
2112 }
2113
2114 skb = (struct sk_buff *) ((unsigned long)
2115 txds->Host_Control);
2116 if (!skb) {
2117 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2118 return NULL;
2119 }
2120 pci_unmap_single(nic->pdev, (dma_addr_t)
2121 txds->Buffer_Pointer,
2122 skb->len - skb->data_len,
2123 PCI_DMA_TODEVICE);
2124 frg_cnt = skb_shinfo(skb)->nr_frags;
2125 if (frg_cnt) {
2126 txds++;
2127 for (j = 0; j < frg_cnt; j++, txds++) {
2128 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2129 if (!txds->Buffer_Pointer)
2130 break;
2131 pci_unmap_page(nic->pdev, (dma_addr_t)
2132 txds->Buffer_Pointer,
2133 frag->size, PCI_DMA_TODEVICE);
2134 }
2135 }
2136 memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
2137 return(skb);
2138 }
2139
2140 /**
2141 * free_tx_buffers - Free all queued Tx buffers
2142 * @nic : device private variable.
2143 * Description:
2144 * Free all queued Tx buffers.
2145 * Return Value: void
2146 */
2147
2148 static void free_tx_buffers(struct s2io_nic *nic)
2149 {
2150 struct net_device *dev = nic->dev;
2151 struct sk_buff *skb;
2152 TxD_t *txdp;
2153 int i, j;
2154 mac_info_t *mac_control;
2155 struct config_param *config;
2156 int cnt = 0;
2157
2158 mac_control = &nic->mac_control;
2159 config = &nic->config;
2160
2161 for (i = 0; i < config->tx_fifo_num; i++) {
2162 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2163 txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2164 list_virt_addr;
2165 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2166 if (skb) {
2167 dev_kfree_skb(skb);
2168 cnt++;
2169 }
2170 }
2171 DBG_PRINT(INTR_DBG,
2172 "%s:forcibly freeing %d skbs on FIFO%d\n",
2173 dev->name, cnt, i);
2174 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2175 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2176 }
2177 }
2178
2179 /**
2180 * stop_nic - To stop the nic
2181 * @nic ; device private variable.
2182 * Description:
2183 * This function does exactly the opposite of what the start_nic()
2184 * function does. This function is called to stop the device.
2185 * Return Value:
2186 * void.
2187 */
2188
2189 static void stop_nic(struct s2io_nic *nic)
2190 {
2191 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2192 register u64 val64 = 0;
2193 u16 interruptible;
2194 mac_info_t *mac_control;
2195 struct config_param *config;
2196
2197 mac_control = &nic->mac_control;
2198 config = &nic->config;
2199
2200 /* Disable all interrupts */
2201 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2202 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2203 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2204 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2205
2206 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2207 val64 = readq(&bar0->adapter_control);
2208 val64 &= ~(ADAPTER_CNTL_EN);
2209 writeq(val64, &bar0->adapter_control);
2210 }
2211
2212 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2213 {
2214 struct net_device *dev = nic->dev;
2215 struct sk_buff *frag_list;
2216 void *tmp;
2217
2218 /* Buffer-1 receives L3/L4 headers */
2219 ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2220 (nic->pdev, skb->data, l3l4hdr_size + 4,
2221 PCI_DMA_FROMDEVICE);
2222
2223 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2224 skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2225 if (skb_shinfo(skb)->frag_list == NULL) {
2226 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2227 return -ENOMEM ;
2228 }
2229 frag_list = skb_shinfo(skb)->frag_list;
2230 frag_list->next = NULL;
2231 tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2232 frag_list->data = tmp;
2233 frag_list->tail = tmp;
2234
2235 /* Buffer-2 receives L4 data payload */
2236 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2237 frag_list->data, dev->mtu,
2238 PCI_DMA_FROMDEVICE);
2239 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2240 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2241
2242 return SUCCESS;
2243 }
2244
2245 /**
2246 * fill_rx_buffers - Allocates the Rx side skbs
2247 * @nic: device private variable
2248 * @ring_no: ring number
2249 * Description:
2250 * The function allocates Rx side skbs and puts the physical
2251 * address of these buffers into the RxD buffer pointers, so that the NIC
2252 * can DMA the received frame into these locations.
2253 * The NIC supports 3 receive modes, viz
2254 * 1. single buffer,
2255 * 2. three buffer and
2256 * 3. Five buffer modes.
2257 * Each mode defines how many fragments the received frame will be split
2258 * up into by the NIC. The frame is split into L3 header, L4 Header,
2259 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2260 * is split into 3 fragments. As of now only single buffer mode is
2261 * supported.
2262 * Return Value:
2263 * SUCCESS on success or an appropriate -ve value on failure.
2264 */
2265
2266 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2267 {
2268 struct net_device *dev = nic->dev;
2269 struct sk_buff *skb;
2270 RxD_t *rxdp;
2271 int off, off1, size, block_no, block_no1;
2272 u32 alloc_tab = 0;
2273 u32 alloc_cnt;
2274 mac_info_t *mac_control;
2275 struct config_param *config;
2276 u64 tmp;
2277 buffAdd_t *ba;
2278 #ifndef CONFIG_S2IO_NAPI
2279 unsigned long flags;
2280 #endif
2281 RxD_t *first_rxdp = NULL;
2282
2283 mac_control = &nic->mac_control;
2284 config = &nic->config;
2285 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2286 atomic_read(&nic->rx_bufs_left[ring_no]);
2287
2288 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2289 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2290 while (alloc_tab < alloc_cnt) {
2291 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2292 block_index;
2293 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2294
2295 rxdp = mac_control->rings[ring_no].
2296 rx_blocks[block_no].rxds[off].virt_addr;
2297
2298 if ((block_no == block_no1) && (off == off1) &&
2299 (rxdp->Host_Control)) {
2300 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2301 dev->name);
2302 DBG_PRINT(INTR_DBG, " info equated\n");
2303 goto end;
2304 }
2305 if (off && (off == rxd_count[nic->rxd_mode])) {
2306 mac_control->rings[ring_no].rx_curr_put_info.
2307 block_index++;
2308 if (mac_control->rings[ring_no].rx_curr_put_info.
2309 block_index == mac_control->rings[ring_no].
2310 block_count)
2311 mac_control->rings[ring_no].rx_curr_put_info.
2312 block_index = 0;
2313 block_no = mac_control->rings[ring_no].
2314 rx_curr_put_info.block_index;
2315 if (off == rxd_count[nic->rxd_mode])
2316 off = 0;
2317 mac_control->rings[ring_no].rx_curr_put_info.
2318 offset = off;
2319 rxdp = mac_control->rings[ring_no].
2320 rx_blocks[block_no].block_virt_addr;
2321 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2322 dev->name, rxdp);
2323 }
2324 #ifndef CONFIG_S2IO_NAPI
2325 spin_lock_irqsave(&nic->put_lock, flags);
2326 mac_control->rings[ring_no].put_pos =
2327 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2328 spin_unlock_irqrestore(&nic->put_lock, flags);
2329 #endif
2330 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2331 ((nic->rxd_mode >= RXD_MODE_3A) &&
2332 (rxdp->Control_2 & BIT(0)))) {
2333 mac_control->rings[ring_no].rx_curr_put_info.
2334 offset = off;
2335 goto end;
2336 }
2337 /* calculate size of skb based on ring mode */
2338 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2339 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2340 if (nic->rxd_mode == RXD_MODE_1)
2341 size += NET_IP_ALIGN;
2342 else if (nic->rxd_mode == RXD_MODE_3B)
2343 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2344 else
2345 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2346
2347 /* allocate skb */
2348 skb = dev_alloc_skb(size);
2349 if(!skb) {
2350 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2351 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2352 if (first_rxdp) {
2353 wmb();
2354 first_rxdp->Control_1 |= RXD_OWN_XENA;
2355 }
2356 return -ENOMEM ;
2357 }
2358 if (nic->rxd_mode == RXD_MODE_1) {
2359 /* 1 buffer mode - normal operation mode */
2360 memset(rxdp, 0, sizeof(RxD1_t));
2361 skb_reserve(skb, NET_IP_ALIGN);
2362 ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2363 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2364 PCI_DMA_FROMDEVICE);
2365 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2366
2367 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2368 /*
2369 * 2 or 3 buffer mode -
2370 * Both 2 buffer mode and 3 buffer mode provides 128
2371 * byte aligned receive buffers.
2372 *
2373 * 3 buffer mode provides header separation where in
2374 * skb->data will have L3/L4 headers where as
2375 * skb_shinfo(skb)->frag_list will have the L4 data
2376 * payload
2377 */
2378
2379 memset(rxdp, 0, sizeof(RxD3_t));
2380 ba = &mac_control->rings[ring_no].ba[block_no][off];
2381 skb_reserve(skb, BUF0_LEN);
2382 tmp = (u64)(unsigned long) skb->data;
2383 tmp += ALIGN_SIZE;
2384 tmp &= ~ALIGN_SIZE;
2385 skb->data = (void *) (unsigned long)tmp;
2386 skb->tail = (void *) (unsigned long)tmp;
2387
2388 if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2389 ((RxD3_t*)rxdp)->Buffer0_ptr =
2390 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2391 PCI_DMA_FROMDEVICE);
2392 else
2393 pci_dma_sync_single_for_device(nic->pdev,
2394 (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2395 BUF0_LEN, PCI_DMA_FROMDEVICE);
2396 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2397 if (nic->rxd_mode == RXD_MODE_3B) {
2398 /* Two buffer mode */
2399
2400 /*
2401 * Buffer2 will have L3/L4 header plus
2402 * L4 payload
2403 */
2404 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2405 (nic->pdev, skb->data, dev->mtu + 4,
2406 PCI_DMA_FROMDEVICE);
2407
2408 /* Buffer-1 will be dummy buffer. Not used */
2409 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2410 ((RxD3_t*)rxdp)->Buffer1_ptr =
2411 pci_map_single(nic->pdev,
2412 ba->ba_1, BUF1_LEN,
2413 PCI_DMA_FROMDEVICE);
2414 }
2415 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2416 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2417 (dev->mtu + 4);
2418 } else {
2419 /* 3 buffer mode */
2420 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2421 dev_kfree_skb_irq(skb);
2422 if (first_rxdp) {
2423 wmb();
2424 first_rxdp->Control_1 |=
2425 RXD_OWN_XENA;
2426 }
2427 return -ENOMEM ;
2428 }
2429 }
2430 rxdp->Control_2 |= BIT(0);
2431 }
2432 rxdp->Host_Control = (unsigned long) (skb);
2433 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2434 rxdp->Control_1 |= RXD_OWN_XENA;
2435 off++;
2436 if (off == (rxd_count[nic->rxd_mode] + 1))
2437 off = 0;
2438 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2439
2440 rxdp->Control_2 |= SET_RXD_MARKER;
2441 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2442 if (first_rxdp) {
2443 wmb();
2444 first_rxdp->Control_1 |= RXD_OWN_XENA;
2445 }
2446 first_rxdp = rxdp;
2447 }
2448 atomic_inc(&nic->rx_bufs_left[ring_no]);
2449 alloc_tab++;
2450 }
2451
2452 end:
2453 /* Transfer ownership of first descriptor to adapter just before
2454 * exiting. Before that, use memory barrier so that ownership
2455 * and other fields are seen by adapter correctly.
2456 */
2457 if (first_rxdp) {
2458 wmb();
2459 first_rxdp->Control_1 |= RXD_OWN_XENA;
2460 }
2461
2462 return SUCCESS;
2463 }
2464
2465 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2466 {
2467 struct net_device *dev = sp->dev;
2468 int j;
2469 struct sk_buff *skb;
2470 RxD_t *rxdp;
2471 mac_info_t *mac_control;
2472 buffAdd_t *ba;
2473
2474 mac_control = &sp->mac_control;
2475 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2476 rxdp = mac_control->rings[ring_no].
2477 rx_blocks[blk].rxds[j].virt_addr;
2478 skb = (struct sk_buff *)
2479 ((unsigned long) rxdp->Host_Control);
2480 if (!skb) {
2481 continue;
2482 }
2483 if (sp->rxd_mode == RXD_MODE_1) {
2484 pci_unmap_single(sp->pdev, (dma_addr_t)
2485 ((RxD1_t*)rxdp)->Buffer0_ptr,
2486 dev->mtu +
2487 HEADER_ETHERNET_II_802_3_SIZE
2488 + HEADER_802_2_SIZE +
2489 HEADER_SNAP_SIZE,
2490 PCI_DMA_FROMDEVICE);
2491 memset(rxdp, 0, sizeof(RxD1_t));
2492 } else if(sp->rxd_mode == RXD_MODE_3B) {
2493 ba = &mac_control->rings[ring_no].
2494 ba[blk][j];
2495 pci_unmap_single(sp->pdev, (dma_addr_t)
2496 ((RxD3_t*)rxdp)->Buffer0_ptr,
2497 BUF0_LEN,
2498 PCI_DMA_FROMDEVICE);
2499 pci_unmap_single(sp->pdev, (dma_addr_t)
2500 ((RxD3_t*)rxdp)->Buffer1_ptr,
2501 BUF1_LEN,
2502 PCI_DMA_FROMDEVICE);
2503 pci_unmap_single(sp->pdev, (dma_addr_t)
2504 ((RxD3_t*)rxdp)->Buffer2_ptr,
2505 dev->mtu + 4,
2506 PCI_DMA_FROMDEVICE);
2507 memset(rxdp, 0, sizeof(RxD3_t));
2508 } else {
2509 pci_unmap_single(sp->pdev, (dma_addr_t)
2510 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2511 PCI_DMA_FROMDEVICE);
2512 pci_unmap_single(sp->pdev, (dma_addr_t)
2513 ((RxD3_t*)rxdp)->Buffer1_ptr,
2514 l3l4hdr_size + 4,
2515 PCI_DMA_FROMDEVICE);
2516 pci_unmap_single(sp->pdev, (dma_addr_t)
2517 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2518 PCI_DMA_FROMDEVICE);
2519 memset(rxdp, 0, sizeof(RxD3_t));
2520 }
2521 dev_kfree_skb(skb);
2522 atomic_dec(&sp->rx_bufs_left[ring_no]);
2523 }
2524 }
2525
2526 /**
2527 * free_rx_buffers - Frees all Rx buffers
2528 * @sp: device private variable.
2529 * Description:
2530 * This function will free all Rx buffers allocated by host.
2531 * Return Value:
2532 * NONE.
2533 */
2534
2535 static void free_rx_buffers(struct s2io_nic *sp)
2536 {
2537 struct net_device *dev = sp->dev;
2538 int i, blk = 0, buf_cnt = 0;
2539 mac_info_t *mac_control;
2540 struct config_param *config;
2541
2542 mac_control = &sp->mac_control;
2543 config = &sp->config;
2544
2545 for (i = 0; i < config->rx_ring_num; i++) {
2546 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2547 free_rxd_blk(sp,i,blk);
2548
2549 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2550 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2551 mac_control->rings[i].rx_curr_put_info.offset = 0;
2552 mac_control->rings[i].rx_curr_get_info.offset = 0;
2553 atomic_set(&sp->rx_bufs_left[i], 0);
2554 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2555 dev->name, buf_cnt, i);
2556 }
2557 }
2558
2559 /**
2560 * s2io_poll - Rx interrupt handler for NAPI support
2561 * @dev : pointer to the device structure.
2562 * @budget : The number of packets that were budgeted to be processed
2563 * during one pass through the 'Poll" function.
2564 * Description:
2565 * Comes into picture only if NAPI support has been incorporated. It does
2566 * the same thing that rx_intr_handler does, but not in a interrupt context
2567 * also It will process only a given number of packets.
2568 * Return value:
2569 * 0 on success and 1 if there are No Rx packets to be processed.
2570 */
2571
2572 #if defined(CONFIG_S2IO_NAPI)
2573 static int s2io_poll(struct net_device *dev, int *budget)
2574 {
2575 nic_t *nic = dev->priv;
2576 int pkt_cnt = 0, org_pkts_to_process;
2577 mac_info_t *mac_control;
2578 struct config_param *config;
2579 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2580 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2581 int i;
2582
2583 atomic_inc(&nic->isr_cnt);
2584 mac_control = &nic->mac_control;
2585 config = &nic->config;
2586
2587 nic->pkts_to_process = *budget;
2588 if (nic->pkts_to_process > dev->quota)
2589 nic->pkts_to_process = dev->quota;
2590 org_pkts_to_process = nic->pkts_to_process;
2591
2592 writeq(val64, &bar0->rx_traffic_int);
2593 val64 = readl(&bar0->rx_traffic_int);
2594
2595 for (i = 0; i < config->rx_ring_num; i++) {
2596 rx_intr_handler(&mac_control->rings[i]);
2597 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2598 if (!nic->pkts_to_process) {
2599 /* Quota for the current iteration has been met */
2600 goto no_rx;
2601 }
2602 }
2603 if (!pkt_cnt)
2604 pkt_cnt = 1;
2605
2606 dev->quota -= pkt_cnt;
2607 *budget -= pkt_cnt;
2608 netif_rx_complete(dev);
2609
2610 for (i = 0; i < config->rx_ring_num; i++) {
2611 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2612 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2613 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2614 break;
2615 }
2616 }
2617 /* Re enable the Rx interrupts. */
2618 writeq(0x0, &bar0->rx_traffic_mask);
2619 val64 = readl(&bar0->rx_traffic_mask);
2620 atomic_dec(&nic->isr_cnt);
2621 return 0;
2622
2623 no_rx:
2624 dev->quota -= pkt_cnt;
2625 *budget -= pkt_cnt;
2626
2627 for (i = 0; i < config->rx_ring_num; i++) {
2628 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2629 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2630 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2631 break;
2632 }
2633 }
2634 atomic_dec(&nic->isr_cnt);
2635 return 1;
2636 }
2637 #endif
2638
2639 #ifdef CONFIG_NET_POLL_CONTROLLER
2640 /**
2641 * s2io_netpoll - netpoll event handler entry point
2642 * @dev : pointer to the device structure.
2643 * Description:
2644 * This function will be called by upper layer to check for events on the
2645 * interface in situations where interrupts are disabled. It is used for
2646 * specific in-kernel networking tasks, such as remote consoles and kernel
2647 * debugging over the network (example netdump in RedHat).
2648 */
2649 static void s2io_netpoll(struct net_device *dev)
2650 {
2651 nic_t *nic = dev->priv;
2652 mac_info_t *mac_control;
2653 struct config_param *config;
2654 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2655 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2656 int i;
2657
2658 disable_irq(dev->irq);
2659
2660 atomic_inc(&nic->isr_cnt);
2661 mac_control = &nic->mac_control;
2662 config = &nic->config;
2663
2664 writeq(val64, &bar0->rx_traffic_int);
2665 writeq(val64, &bar0->tx_traffic_int);
2666
2667 /* we need to free up the transmitted skbufs or else netpoll will
2668 * run out of skbs and will fail and eventually netpoll application such
2669 * as netdump will fail.
2670 */
2671 for (i = 0; i < config->tx_fifo_num; i++)
2672 tx_intr_handler(&mac_control->fifos[i]);
2673
2674 /* check for received packet and indicate up to network */
2675 for (i = 0; i < config->rx_ring_num; i++)
2676 rx_intr_handler(&mac_control->rings[i]);
2677
2678 for (i = 0; i < config->rx_ring_num; i++) {
2679 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2680 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2681 DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2682 break;
2683 }
2684 }
2685 atomic_dec(&nic->isr_cnt);
2686 enable_irq(dev->irq);
2687 return;
2688 }
2689 #endif
2690
2691 /**
2692 * rx_intr_handler - Rx interrupt handler
2693 * @nic: device private variable.
2694 * Description:
2695 * If the interrupt is because of a received frame or if the
2696 * receive ring contains fresh as yet un-processed frames,this function is
2697 * called. It picks out the RxD at which place the last Rx processing had
2698 * stopped and sends the skb to the OSM's Rx handler and then increments
2699 * the offset.
2700 * Return Value:
2701 * NONE.
2702 */
2703 static void rx_intr_handler(ring_info_t *ring_data)
2704 {
2705 nic_t *nic = ring_data->nic;
2706 struct net_device *dev = (struct net_device *) nic->dev;
2707 int get_block, put_block, put_offset;
2708 rx_curr_get_info_t get_info, put_info;
2709 RxD_t *rxdp;
2710 struct sk_buff *skb;
2711 #ifndef CONFIG_S2IO_NAPI
2712 int pkt_cnt = 0;
2713 #endif
2714 int i;
2715
2716 spin_lock(&nic->rx_lock);
2717 if (atomic_read(&nic->card_state) == CARD_DOWN) {
2718 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2719 __FUNCTION__, dev->name);
2720 spin_unlock(&nic->rx_lock);
2721 return;
2722 }
2723
2724 get_info = ring_data->rx_curr_get_info;
2725 get_block = get_info.block_index;
2726 put_info = ring_data->rx_curr_put_info;
2727 put_block = put_info.block_index;
2728 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2729 #ifndef CONFIG_S2IO_NAPI
2730 spin_lock(&nic->put_lock);
2731 put_offset = ring_data->put_pos;
2732 spin_unlock(&nic->put_lock);
2733 #else
2734 put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2735 put_info.offset;
2736 #endif
2737 while (RXD_IS_UP2DT(rxdp)) {
2738 /* If your are next to put index then it's FIFO full condition */
2739 if ((get_block == put_block) &&
2740 (get_info.offset + 1) == put_info.offset) {
2741 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2742 break;
2743 }
2744 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2745 if (skb == NULL) {
2746 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2747 dev->name);
2748 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2749 spin_unlock(&nic->rx_lock);
2750 return;
2751 }
2752 if (nic->rxd_mode == RXD_MODE_1) {
2753 pci_unmap_single(nic->pdev, (dma_addr_t)
2754 ((RxD1_t*)rxdp)->Buffer0_ptr,
2755 dev->mtu +
2756 HEADER_ETHERNET_II_802_3_SIZE +
2757 HEADER_802_2_SIZE +
2758 HEADER_SNAP_SIZE,
2759 PCI_DMA_FROMDEVICE);
2760 } else if (nic->rxd_mode == RXD_MODE_3B) {
2761 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2762 ((RxD3_t*)rxdp)->Buffer0_ptr,
2763 BUF0_LEN, PCI_DMA_FROMDEVICE);
2764 pci_unmap_single(nic->pdev, (dma_addr_t)
2765 ((RxD3_t*)rxdp)->Buffer2_ptr,
2766 dev->mtu + 4,
2767 PCI_DMA_FROMDEVICE);
2768 } else {
2769 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2770 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2771 PCI_DMA_FROMDEVICE);
2772 pci_unmap_single(nic->pdev, (dma_addr_t)
2773 ((RxD3_t*)rxdp)->Buffer1_ptr,
2774 l3l4hdr_size + 4,
2775 PCI_DMA_FROMDEVICE);
2776 pci_unmap_single(nic->pdev, (dma_addr_t)
2777 ((RxD3_t*)rxdp)->Buffer2_ptr,
2778 dev->mtu, PCI_DMA_FROMDEVICE);
2779 }
2780 prefetch(skb->data);
2781 rx_osm_handler(ring_data, rxdp);
2782 get_info.offset++;
2783 ring_data->rx_curr_get_info.offset = get_info.offset;
2784 rxdp = ring_data->rx_blocks[get_block].
2785 rxds[get_info.offset].virt_addr;
2786 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2787 get_info.offset = 0;
2788 ring_data->rx_curr_get_info.offset = get_info.offset;
2789 get_block++;
2790 if (get_block == ring_data->block_count)
2791 get_block = 0;
2792 ring_data->rx_curr_get_info.block_index = get_block;
2793 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2794 }
2795
2796 #ifdef CONFIG_S2IO_NAPI
2797 nic->pkts_to_process -= 1;
2798 if (!nic->pkts_to_process)
2799 break;
2800 #else
2801 pkt_cnt++;
2802 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2803 break;
2804 #endif
2805 }
2806 if (nic->lro) {
2807 /* Clear all LRO sessions before exiting */
2808 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2809 lro_t *lro = &nic->lro0_n[i];
2810 if (lro->in_use) {
2811 update_L3L4_header(nic, lro);
2812 queue_rx_frame(lro->parent);
2813 clear_lro_session(lro);
2814 }
2815 }
2816 }
2817
2818 spin_unlock(&nic->rx_lock);
2819 }
2820
2821 /**
2822 * tx_intr_handler - Transmit interrupt handler
2823 * @nic : device private variable
2824 * Description:
2825 * If an interrupt was raised to indicate DMA complete of the
2826 * Tx packet, this function is called. It identifies the last TxD
2827 * whose buffer was freed and frees all skbs whose data have already
2828 * DMA'ed into the NICs internal memory.
2829 * Return Value:
2830 * NONE
2831 */
2832
2833 static void tx_intr_handler(fifo_info_t *fifo_data)
2834 {
2835 nic_t *nic = fifo_data->nic;
2836 struct net_device *dev = (struct net_device *) nic->dev;
2837 tx_curr_get_info_t get_info, put_info;
2838 struct sk_buff *skb;
2839 TxD_t *txdlp;
2840
2841 get_info = fifo_data->tx_curr_get_info;
2842 put_info = fifo_data->tx_curr_put_info;
2843 txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2844 list_virt_addr;
2845 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2846 (get_info.offset != put_info.offset) &&
2847 (txdlp->Host_Control)) {
2848 /* Check for TxD errors */
2849 if (txdlp->Control_1 & TXD_T_CODE) {
2850 unsigned long long err;
2851 err = txdlp->Control_1 & TXD_T_CODE;
2852 if (err & 0x1) {
2853 nic->mac_control.stats_info->sw_stat.
2854 parity_err_cnt++;
2855 }
2856 if ((err >> 48) == 0xA) {
2857 DBG_PRINT(TX_DBG, "TxD returned due \
2858 to loss of link\n");
2859 }
2860 else {
2861 DBG_PRINT(ERR_DBG, "***TxD error \
2862 %llx\n", err);
2863 }
2864 }
2865
2866 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2867 if (skb == NULL) {
2868 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2869 __FUNCTION__);
2870 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2871 return;
2872 }
2873
2874 /* Updating the statistics block */
2875 nic->stats.tx_bytes += skb->len;
2876 dev_kfree_skb_irq(skb);
2877
2878 get_info.offset++;
2879 if (get_info.offset == get_info.fifo_len + 1)
2880 get_info.offset = 0;
2881 txdlp = (TxD_t *) fifo_data->list_info
2882 [get_info.offset].list_virt_addr;
2883 fifo_data->tx_curr_get_info.offset =
2884 get_info.offset;
2885 }
2886
2887 spin_lock(&nic->tx_lock);
2888 if (netif_queue_stopped(dev))
2889 netif_wake_queue(dev);
2890 spin_unlock(&nic->tx_lock);
2891 }
2892
2893 /**
2894 * s2io_mdio_write - Function to write in to MDIO registers
2895 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2896 * @addr : address value
2897 * @value : data value
2898 * @dev : pointer to net_device structure
2899 * Description:
2900 * This function is used to write values to the MDIO registers
2901 * NONE
2902 */
2903 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2904 {
2905 u64 val64 = 0x0;
2906 nic_t *sp = dev->priv;
2907 XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
2908
2909 //address transaction
2910 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2911 | MDIO_MMD_DEV_ADDR(mmd_type)
2912 | MDIO_MMS_PRT_ADDR(0x0);
2913 writeq(val64, &bar0->mdio_control);
2914 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2915 writeq(val64, &bar0->mdio_control);
2916 udelay(100);
2917
2918 //Data transaction
2919 val64 = 0x0;
2920 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2921 | MDIO_MMD_DEV_ADDR(mmd_type)
2922 | MDIO_MMS_PRT_ADDR(0x0)
2923 | MDIO_MDIO_DATA(value)
2924 | MDIO_OP(MDIO_OP_WRITE_TRANS);
2925 writeq(val64, &bar0->mdio_control);
2926 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2927 writeq(val64, &bar0->mdio_control);
2928 udelay(100);
2929
2930 val64 = 0x0;
2931 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2932 | MDIO_MMD_DEV_ADDR(mmd_type)
2933 | MDIO_MMS_PRT_ADDR(0x0)
2934 | MDIO_OP(MDIO_OP_READ_TRANS);
2935 writeq(val64, &bar0->mdio_control);
2936 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2937 writeq(val64, &bar0->mdio_control);
2938 udelay(100);
2939
2940 }
2941
2942 /**
2943 * s2io_mdio_read - Function to write in to MDIO registers
2944 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2945 * @addr : address value
2946 * @dev : pointer to net_device structure
2947 * Description:
2948 * This function is used to read values to the MDIO registers
2949 * NONE
2950 */
2951 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2952 {
2953 u64 val64 = 0x0;
2954 u64 rval64 = 0x0;
2955 nic_t *sp = dev->priv;
2956 XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
2957
2958 /* address transaction */
2959 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2960 | MDIO_MMD_DEV_ADDR(mmd_type)
2961 | MDIO_MMS_PRT_ADDR(0x0);
2962 writeq(val64, &bar0->mdio_control);
2963 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2964 writeq(val64, &bar0->mdio_control);
2965 udelay(100);
2966
2967 /* Data transaction */
2968 val64 = 0x0;
2969 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2970 | MDIO_MMD_DEV_ADDR(mmd_type)
2971 | MDIO_MMS_PRT_ADDR(0x0)
2972 | MDIO_OP(MDIO_OP_READ_TRANS);
2973 writeq(val64, &bar0->mdio_control);
2974 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2975 writeq(val64, &bar0->mdio_control);
2976 udelay(100);
2977
2978 /* Read the value from regs */
2979 rval64 = readq(&bar0->mdio_control);
2980 rval64 = rval64 & 0xFFFF0000;
2981 rval64 = rval64 >> 16;
2982 return rval64;
2983 }
2984 /**
2985 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
2986 * @counter : couter value to be updated
2987 * @flag : flag to indicate the status
2988 * @type : counter type
2989 * Description:
2990 * This function is to check the status of the xpak counters value
2991 * NONE
2992 */
2993
2994 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2995 {
2996 u64 mask = 0x3;
2997 u64 val64;
2998 int i;
2999 for(i = 0; i <index; i++)
3000 mask = mask << 0x2;
3001
3002 if(flag > 0)
3003 {
3004 *counter = *counter + 1;
3005 val64 = *regs_stat & mask;
3006 val64 = val64 >> (index * 0x2);
3007 val64 = val64 + 1;
3008 if(val64 == 3)
3009 {
3010 switch(type)
3011 {
3012 case 1:
3013 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3014 "service. Excessive temperatures may "
3015 "result in premature transceiver "
3016 "failure \n");
3017 break;
3018 case 2:
3019 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3020 "service Excessive bias currents may "
3021 "indicate imminent laser diode "
3022 "failure \n");
3023 break;
3024 case 3:
3025 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3026 "service Excessive laser output "
3027 "power may saturate far-end "
3028 "receiver\n");
3029 break;
3030 default:
3031 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3032 "type \n");
3033 }
3034 val64 = 0x0;
3035 }
3036 val64 = val64 << (index * 0x2);
3037 *regs_stat = (*regs_stat & (~mask)) | (val64);
3038
3039 } else {
3040 *regs_stat = *regs_stat & (~mask);
3041 }
3042 }
3043
3044 /**
3045 * s2io_updt_xpak_counter - Function to update the xpak counters
3046 * @dev : pointer to net_device struct
3047 * Description:
3048 * This function is to upate the status of the xpak counters value
3049 * NONE
3050 */
3051 static void s2io_updt_xpak_counter(struct net_device *dev)
3052 {
3053 u16 flag = 0x0;
3054 u16 type = 0x0;
3055 u16 val16 = 0x0;
3056 u64 val64 = 0x0;
3057 u64 addr = 0x0;
3058
3059 nic_t *sp = dev->priv;
3060 StatInfo_t *stat_info = sp->mac_control.stats_info;
3061
3062 /* Check the communication with the MDIO slave */
3063 addr = 0x0000;
3064 val64 = 0x0;
3065 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3066 if((val64 == 0xFFFF) || (val64 == 0x0000))
3067 {
3068 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3069 "Returned %llx\n", (unsigned long long)val64);
3070 return;
3071 }
3072
3073 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3074 if(val64 != 0x2040)
3075 {
3076 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3077 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3078 (unsigned long long)val64);
3079 return;
3080 }
3081
3082 /* Loading the DOM register to MDIO register */
3083 addr = 0xA100;
3084 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3085 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3086
3087 /* Reading the Alarm flags */
3088 addr = 0xA070;
3089 val64 = 0x0;
3090 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3091
3092 flag = CHECKBIT(val64, 0x7);
3093 type = 1;
3094 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3095 &stat_info->xpak_stat.xpak_regs_stat,
3096 0x0, flag, type);
3097
3098 if(CHECKBIT(val64, 0x6))
3099 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3100
3101 flag = CHECKBIT(val64, 0x3);
3102 type = 2;
3103 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3104 &stat_info->xpak_stat.xpak_regs_stat,
3105 0x2, flag, type);
3106
3107 if(CHECKBIT(val64, 0x2))
3108 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3109
3110 flag = CHECKBIT(val64, 0x1);
3111 type = 3;
3112 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3113 &stat_info->xpak_stat.xpak_regs_stat,
3114 0x4, flag, type);
3115
3116 if(CHECKBIT(val64, 0x0))
3117 stat_info->xpak_stat.alarm_laser_output_power_low++;
3118
3119 /* Reading the Warning flags */
3120 addr = 0xA074;
3121 val64 = 0x0;
3122 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3123
3124 if(CHECKBIT(val64, 0x7))
3125 stat_info->xpak_stat.warn_transceiver_temp_high++;
3126
3127 if(CHECKBIT(val64, 0x6))
3128 stat_info->xpak_stat.warn_transceiver_temp_low++;
3129
3130 if(CHECKBIT(val64, 0x3))
3131 stat_info->xpak_stat.warn_laser_bias_current_high++;
3132
3133 if(CHECKBIT(val64, 0x2))
3134 stat_info->xpak_stat.warn_laser_bias_current_low++;
3135
3136 if(CHECKBIT(val64, 0x1))
3137 stat_info->xpak_stat.warn_laser_output_power_high++;
3138
3139 if(CHECKBIT(val64, 0x0))
3140 stat_info->xpak_stat.warn_laser_output_power_low++;
3141 }
3142
3143 /**
3144 * alarm_intr_handler - Alarm Interrrupt handler
3145 * @nic: device private variable
3146 * Description: If the interrupt was neither because of Rx packet or Tx
3147 * complete, this function is called. If the interrupt was to indicate
3148 * a loss of link, the OSM link status handler is invoked for any other
3149 * alarm interrupt the block that raised the interrupt is displayed
3150 * and a H/W reset is issued.
3151 * Return Value:
3152 * NONE
3153 */
3154
3155 static void alarm_intr_handler(struct s2io_nic *nic)
3156 {
3157 struct net_device *dev = (struct net_device *) nic->dev;
3158 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3159 register u64 val64 = 0, err_reg = 0;
3160 u64 cnt;
3161 int i;
3162 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3163 /* Handling the XPAK counters update */
3164 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3165 /* waiting for an hour */
3166 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3167 } else {
3168 s2io_updt_xpak_counter(dev);
3169 /* reset the count to zero */
3170 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3171 }
3172
3173 /* Handling link status change error Intr */
3174 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3175 err_reg = readq(&bar0->mac_rmac_err_reg);
3176 writeq(err_reg, &bar0->mac_rmac_err_reg);
3177 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3178 schedule_work(&nic->set_link_task);
3179 }
3180 }
3181
3182 /* Handling Ecc errors */
3183 val64 = readq(&bar0->mc_err_reg);
3184 writeq(val64, &bar0->mc_err_reg);
3185 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3186 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3187 nic->mac_control.stats_info->sw_stat.
3188 double_ecc_errs++;
3189 DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3190 dev->name);
3191 DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3192 if (nic->device_type != XFRAME_II_DEVICE) {
3193 /* Reset XframeI only if critical error */
3194 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3195 MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3196 netif_stop_queue(dev);
3197 schedule_work(&nic->rst_timer_task);
3198 nic->mac_control.stats_info->sw_stat.
3199 soft_reset_cnt++;
3200 }
3201 }
3202 } else {
3203 nic->mac_control.stats_info->sw_stat.
3204 single_ecc_errs++;
3205 }
3206 }
3207
3208 /* In case of a serious error, the device will be Reset. */
3209 val64 = readq(&bar0->serr_source);
3210 if (val64 & SERR_SOURCE_ANY) {
3211 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3212 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3213 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3214 (unsigned long long)val64);
3215 netif_stop_queue(dev);
3216 schedule_work(&nic->rst_timer_task);
3217 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3218 }
3219
3220 /*
3221 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3222 * Error occurs, the adapter will be recycled by disabling the
3223 * adapter enable bit and enabling it again after the device
3224 * becomes Quiescent.
3225 */
3226 val64 = readq(&bar0->pcc_err_reg);
3227 writeq(val64, &bar0->pcc_err_reg);
3228 if (val64 & PCC_FB_ECC_DB_ERR) {
3229 u64 ac = readq(&bar0->adapter_control);
3230 ac &= ~(ADAPTER_CNTL_EN);
3231 writeq(ac, &bar0->adapter_control);
3232 ac = readq(&bar0->adapter_control);
3233 schedule_work(&nic->set_link_task);
3234 }
3235 /* Check for data parity error */
3236 val64 = readq(&bar0->pic_int_status);
3237 if (val64 & PIC_INT_GPIO) {
3238 val64 = readq(&bar0->gpio_int_reg);
3239 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3240 nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3241 schedule_work(&nic->rst_timer_task);
3242 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3243 }
3244 }
3245
3246 /* Check for ring full counter */
3247 if (nic->device_type & XFRAME_II_DEVICE) {
3248 val64 = readq(&bar0->ring_bump_counter1);
3249 for (i=0; i<4; i++) {
3250 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3251 cnt >>= 64 - ((i+1)*16);
3252 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3253 += cnt;
3254 }
3255
3256 val64 = readq(&bar0->ring_bump_counter2);
3257 for (i=0; i<4; i++) {
3258 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3259 cnt >>= 64 - ((i+1)*16);
3260 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3261 += cnt;
3262 }
3263 }
3264
3265 /* Other type of interrupts are not being handled now, TODO */
3266 }
3267
3268 /**
3269 * wait_for_cmd_complete - waits for a command to complete.
3270 * @sp : private member of the device structure, which is a pointer to the
3271 * s2io_nic structure.
3272 * Description: Function that waits for a command to Write into RMAC
3273 * ADDR DATA registers to be completed and returns either success or
3274 * error depending on whether the command was complete or not.
3275 * Return value:
3276 * SUCCESS on success and FAILURE on failure.
3277 */
3278
3279 static int wait_for_cmd_complete(void *addr, u64 busy_bit)
3280 {
3281 int ret = FAILURE, cnt = 0;
3282 u64 val64;
3283
3284 while (TRUE) {
3285 val64 = readq(addr);
3286 if (!(val64 & busy_bit)) {
3287 ret = SUCCESS;
3288 break;
3289 }
3290
3291 if(in_interrupt())
3292 mdelay(50);
3293 else
3294 msleep(50);
3295
3296 if (cnt++ > 10)
3297 break;
3298 }
3299 return ret;
3300 }
3301
3302 /**
3303 * s2io_reset - Resets the card.
3304 * @sp : private member of the device structure.
3305 * Description: Function to Reset the card. This function then also
3306 * restores the previously saved PCI configuration space registers as
3307 * the card reset also resets the configuration space.
3308 * Return value:
3309 * void.
3310 */
3311
3312 static void s2io_reset(nic_t * sp)
3313 {
3314 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3315 u64 val64;
3316 u16 subid, pci_cmd;
3317
3318 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3319 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3320
3321 val64 = SW_RESET_ALL;
3322 writeq(val64, &bar0->sw_reset);
3323
3324 /*
3325 * At this stage, if the PCI write is indeed completed, the
3326 * card is reset and so is the PCI Config space of the device.
3327 * So a read cannot be issued at this stage on any of the
3328 * registers to ensure the write into "sw_reset" register
3329 * has gone through.
3330 * Question: Is there any system call that will explicitly force
3331 * all the write commands still pending on the bus to be pushed
3332 * through?
3333 * As of now I'am just giving a 250ms delay and hoping that the
3334 * PCI write to sw_reset register is done by this time.
3335 */
3336 msleep(250);
3337 if (strstr(sp->product_name, "CX4")) {
3338 msleep(750);
3339 }
3340
3341 /* Restore the PCI state saved during initialization. */
3342 pci_restore_state(sp->pdev);
3343 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3344 pci_cmd);
3345 s2io_init_pci(sp);
3346
3347 msleep(250);
3348
3349 /* Set swapper to enable I/O register access */
3350 s2io_set_swapper(sp);
3351
3352 /* Restore the MSIX table entries from local variables */
3353 restore_xmsi_data(sp);
3354
3355 /* Clear certain PCI/PCI-X fields after reset */
3356 if (sp->device_type == XFRAME_II_DEVICE) {
3357 /* Clear "detected parity error" bit */
3358 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3359
3360 /* Clearing PCIX Ecc status register */
3361 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3362
3363 /* Clearing PCI_STATUS error reflected here */
3364 writeq(BIT(62), &bar0->txpic_int_reg);
3365 }
3366
3367 /* Reset device statistics maintained by OS */
3368 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3369
3370 /* SXE-002: Configure link and activity LED to turn it off */
3371 subid = sp->pdev->subsystem_device;
3372 if (((subid & 0xFF) >= 0x07) &&
3373 (sp->device_type == XFRAME_I_DEVICE)) {
3374 val64 = readq(&bar0->gpio_control);
3375 val64 |= 0x0000800000000000ULL;
3376 writeq(val64, &bar0->gpio_control);
3377 val64 = 0x0411040400000000ULL;
3378 writeq(val64, (void __iomem *)bar0 + 0x2700);
3379 }
3380
3381 /*
3382 * Clear spurious ECC interrupts that would have occured on
3383 * XFRAME II cards after reset.
3384 */
3385 if (sp->device_type == XFRAME_II_DEVICE) {
3386 val64 = readq(&bar0->pcc_err_reg);
3387 writeq(val64, &bar0->pcc_err_reg);
3388 }
3389
3390 sp->device_enabled_once = FALSE;
3391 }
3392
3393 /**
3394 * s2io_set_swapper - to set the swapper controle on the card
3395 * @sp : private member of the device structure,
3396 * pointer to the s2io_nic structure.
3397 * Description: Function to set the swapper control on the card
3398 * correctly depending on the 'endianness' of the system.
3399 * Return value:
3400 * SUCCESS on success and FAILURE on failure.
3401 */
3402
3403 static int s2io_set_swapper(nic_t * sp)
3404 {
3405 struct net_device *dev = sp->dev;
3406 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3407 u64 val64, valt, valr;
3408
3409 /*
3410 * Set proper endian settings and verify the same by reading
3411 * the PIF Feed-back register.
3412 */
3413
3414 val64 = readq(&bar0->pif_rd_swapper_fb);
3415 if (val64 != 0x0123456789ABCDEFULL) {
3416 int i = 0;
3417 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3418 0x8100008181000081ULL, /* FE=1, SE=0 */
3419 0x4200004242000042ULL, /* FE=0, SE=1 */
3420 0}; /* FE=0, SE=0 */
3421
3422 while(i<4) {
3423 writeq(value[i], &bar0->swapper_ctrl);
3424 val64 = readq(&bar0->pif_rd_swapper_fb);
3425 if (val64 == 0x0123456789ABCDEFULL)
3426 break;
3427 i++;
3428 }
3429 if (i == 4) {
3430 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3431 dev->name);
3432 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3433 (unsigned long long) val64);
3434 return FAILURE;
3435 }
3436 valr = value[i];
3437 } else {
3438 valr = readq(&bar0->swapper_ctrl);
3439 }
3440
3441 valt = 0x0123456789ABCDEFULL;
3442 writeq(valt, &bar0->xmsi_address);
3443 val64 = readq(&bar0->xmsi_address);
3444
3445 if(val64 != valt) {
3446 int i = 0;
3447 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3448 0x0081810000818100ULL, /* FE=1, SE=0 */
3449 0x0042420000424200ULL, /* FE=0, SE=1 */
3450 0}; /* FE=0, SE=0 */
3451
3452 while(i<4) {
3453 writeq((value[i] | valr), &bar0->swapper_ctrl);
3454 writeq(valt, &bar0->xmsi_address);
3455 val64 = readq(&bar0->xmsi_address);
3456 if(val64 == valt)
3457 break;
3458 i++;
3459 }
3460 if(i == 4) {
3461 unsigned long long x = val64;
3462 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3463 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3464 return FAILURE;
3465 }
3466 }
3467 val64 = readq(&bar0->swapper_ctrl);
3468 val64 &= 0xFFFF000000000000ULL;
3469
3470 #ifdef __BIG_ENDIAN
3471 /*
3472 * The device by default set to a big endian format, so a
3473 * big endian driver need not set anything.
3474 */
3475 val64 |= (SWAPPER_CTRL_TXP_FE |
3476 SWAPPER_CTRL_TXP_SE |
3477 SWAPPER_CTRL_TXD_R_FE |
3478 SWAPPER_CTRL_TXD_W_FE |
3479 SWAPPER_CTRL_TXF_R_FE |
3480 SWAPPER_CTRL_RXD_R_FE |
3481 SWAPPER_CTRL_RXD_W_FE |
3482 SWAPPER_CTRL_RXF_W_FE |
3483 SWAPPER_CTRL_XMSI_FE |
3484 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3485 if (sp->intr_type == INTA)
3486 val64 |= SWAPPER_CTRL_XMSI_SE;
3487 writeq(val64, &bar0->swapper_ctrl);
3488 #else
3489 /*
3490 * Initially we enable all bits to make it accessible by the
3491 * driver, then we selectively enable only those bits that
3492 * we want to set.
3493 */
3494 val64 |= (SWAPPER_CTRL_TXP_FE |
3495 SWAPPER_CTRL_TXP_SE |
3496 SWAPPER_CTRL_TXD_R_FE |
3497 SWAPPER_CTRL_TXD_R_SE |
3498 SWAPPER_CTRL_TXD_W_FE |
3499 SWAPPER_CTRL_TXD_W_SE |
3500 SWAPPER_CTRL_TXF_R_FE |
3501 SWAPPER_CTRL_RXD_R_FE |
3502 SWAPPER_CTRL_RXD_R_SE |
3503 SWAPPER_CTRL_RXD_W_FE |
3504 SWAPPER_CTRL_RXD_W_SE |
3505 SWAPPER_CTRL_RXF_W_FE |
3506 SWAPPER_CTRL_XMSI_FE |
3507 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3508 if (sp->intr_type == INTA)
3509 val64 |= SWAPPER_CTRL_XMSI_SE;
3510 writeq(val64, &bar0->swapper_ctrl);
3511 #endif
3512 val64 = readq(&bar0->swapper_ctrl);
3513
3514 /*
3515 * Verifying if endian settings are accurate by reading a
3516 * feedback register.
3517 */
3518 val64 = readq(&bar0->pif_rd_swapper_fb);
3519 if (val64 != 0x0123456789ABCDEFULL) {
3520 /* Endian settings are incorrect, calls for another dekko. */
3521 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3522 dev->name);
3523 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3524 (unsigned long long) val64);
3525 return FAILURE;
3526 }
3527
3528 return SUCCESS;
3529 }
3530
3531 static int wait_for_msix_trans(nic_t *nic, int i)
3532 {
3533 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3534 u64 val64;
3535 int ret = 0, cnt = 0;
3536
3537 do {
3538 val64 = readq(&bar0->xmsi_access);
3539 if (!(val64 & BIT(15)))
3540 break;
3541 mdelay(1);
3542 cnt++;
3543 } while(cnt < 5);
3544 if (cnt == 5) {
3545 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3546 ret = 1;
3547 }
3548
3549 return ret;
3550 }
3551
3552 static void restore_xmsi_data(nic_t *nic)
3553 {
3554 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3555 u64 val64;
3556 int i;
3557
3558 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3559 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3560 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3561 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3562 writeq(val64, &bar0->xmsi_access);
3563 if (wait_for_msix_trans(nic, i)) {
3564 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3565 continue;
3566 }
3567 }
3568 }
3569
3570 static void store_xmsi_data(nic_t *nic)
3571 {
3572 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3573 u64 val64, addr, data;
3574 int i;
3575
3576 /* Store and display */
3577 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3578 val64 = (BIT(15) | vBIT(i, 26, 6));
3579 writeq(val64, &bar0->xmsi_access);
3580 if (wait_for_msix_trans(nic, i)) {
3581 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3582 continue;
3583 }
3584 addr = readq(&bar0->xmsi_address);
3585 data = readq(&bar0->xmsi_data);
3586 if (addr && data) {
3587 nic->msix_info[i].addr = addr;
3588 nic->msix_info[i].data = data;
3589 }
3590 }
3591 }
3592
3593 int s2io_enable_msi(nic_t *nic)
3594 {
3595 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3596 u16 msi_ctrl, msg_val;
3597 struct config_param *config = &nic->config;
3598 struct net_device *dev = nic->dev;
3599 u64 val64, tx_mat, rx_mat;
3600 int i, err;
3601
3602 val64 = readq(&bar0->pic_control);
3603 val64 &= ~BIT(1);
3604 writeq(val64, &bar0->pic_control);
3605
3606 err = pci_enable_msi(nic->pdev);
3607 if (err) {
3608 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3609 nic->dev->name);
3610 return err;
3611 }
3612
3613 /*
3614 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3615 * for interrupt handling.
3616 */
3617 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3618 msg_val ^= 0x1;
3619 pci_write_config_word(nic->pdev, 0x4c, msg_val);
3620 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3621
3622 pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3623 msi_ctrl |= 0x10;
3624 pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3625
3626 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3627 tx_mat = readq(&bar0->tx_mat0_n[0]);
3628 for (i=0; i<config->tx_fifo_num; i++) {
3629 tx_mat |= TX_MAT_SET(i, 1);
3630 }
3631 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3632
3633 rx_mat = readq(&bar0->rx_mat);
3634 for (i=0; i<config->rx_ring_num; i++) {
3635 rx_mat |= RX_MAT_SET(i, 1);
3636 }
3637 writeq(rx_mat, &bar0->rx_mat);
3638
3639 dev->irq = nic->pdev->irq;
3640 return 0;
3641 }
3642
3643 static int s2io_enable_msi_x(nic_t *nic)
3644 {
3645 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3646 u64 tx_mat, rx_mat;
3647 u16 msi_control; /* Temp variable */
3648 int ret, i, j, msix_indx = 1;
3649
3650 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3651 GFP_KERNEL);
3652 if (nic->entries == NULL) {
3653 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3654 return -ENOMEM;
3655 }
3656 memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3657
3658 nic->s2io_entries =
3659 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3660 GFP_KERNEL);
3661 if (nic->s2io_entries == NULL) {
3662 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3663 kfree(nic->entries);
3664 return -ENOMEM;
3665 }
3666 memset(nic->s2io_entries, 0,
3667 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3668
3669 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3670 nic->entries[i].entry = i;
3671 nic->s2io_entries[i].entry = i;
3672 nic->s2io_entries[i].arg = NULL;
3673 nic->s2io_entries[i].in_use = 0;
3674 }
3675
3676 tx_mat = readq(&bar0->tx_mat0_n[0]);
3677 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3678 tx_mat |= TX_MAT_SET(i, msix_indx);
3679 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3680 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3681 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3682 }
3683 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3684
3685 if (!nic->config.bimodal) {
3686 rx_mat = readq(&bar0->rx_mat);
3687 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3688 rx_mat |= RX_MAT_SET(j, msix_indx);
3689 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3690 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3691 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3692 }
3693 writeq(rx_mat, &bar0->rx_mat);
3694 } else {
3695 tx_mat = readq(&bar0->tx_mat0_n[7]);
3696 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3697 tx_mat |= TX_MAT_SET(i, msix_indx);
3698 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3699 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3700 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3701 }
3702 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3703 }
3704
3705 nic->avail_msix_vectors = 0;
3706 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3707 /* We fail init if error or we get less vectors than min required */
3708 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3709 nic->avail_msix_vectors = ret;
3710 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3711 }
3712 if (ret) {
3713 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3714 kfree(nic->entries);
3715 kfree(nic->s2io_entries);
3716 nic->entries = NULL;
3717 nic->s2io_entries = NULL;
3718 nic->avail_msix_vectors = 0;
3719 return -ENOMEM;
3720 }
3721 if (!nic->avail_msix_vectors)
3722 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3723
3724 /*
3725 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3726 * in the herc NIC. (Temp change, needs to be removed later)
3727 */
3728 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3729 msi_control |= 0x1; /* Enable MSI */
3730 pci_write_config_word(nic->pdev, 0x42, msi_control);
3731
3732 return 0;
3733 }
3734
3735 /* ********************************************************* *
3736 * Functions defined below concern the OS part of the driver *
3737 * ********************************************************* */
3738
3739 /**
3740 * s2io_open - open entry point of the driver
3741 * @dev : pointer to the device structure.
3742 * Description:
3743 * This function is the open entry point of the driver. It mainly calls a
3744 * function to allocate Rx buffers and inserts them into the buffer
3745 * descriptors and then enables the Rx part of the NIC.
3746 * Return value:
3747 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3748 * file on failure.
3749 */
3750
3751 static int s2io_open(struct net_device *dev)
3752 {
3753 nic_t *sp = dev->priv;
3754 int err = 0;
3755
3756 /*
3757 * Make sure you have link off by default every time
3758 * Nic is initialized
3759 */
3760 netif_carrier_off(dev);
3761 sp->last_link_state = 0;
3762
3763 /* Initialize H/W and enable interrupts */
3764 err = s2io_card_up(sp);
3765 if (err) {
3766 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3767 dev->name);
3768 goto hw_init_failed;
3769 }
3770
3771 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3772 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3773 s2io_card_down(sp);
3774 err = -ENODEV;
3775 goto hw_init_failed;
3776 }
3777
3778 netif_start_queue(dev);
3779 return 0;
3780
3781 hw_init_failed:
3782 if (sp->intr_type == MSI_X) {
3783 if (sp->entries)
3784 kfree(sp->entries);
3785 if (sp->s2io_entries)
3786 kfree(sp->s2io_entries);
3787 }
3788 return err;
3789 }
3790
3791 /**
3792 * s2io_close -close entry point of the driver
3793 * @dev : device pointer.
3794 * Description:
3795 * This is the stop entry point of the driver. It needs to undo exactly
3796 * whatever was done by the open entry point,thus it's usually referred to
3797 * as the close function.Among other things this function mainly stops the
3798 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3799 * Return value:
3800 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3801 * file on failure.
3802 */
3803
3804 static int s2io_close(struct net_device *dev)
3805 {
3806 nic_t *sp = dev->priv;
3807
3808 flush_scheduled_work();
3809 netif_stop_queue(dev);
3810 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3811 s2io_card_down(sp);
3812
3813 sp->device_close_flag = TRUE; /* Device is shut down. */
3814 return 0;
3815 }
3816
3817 /**
3818 * s2io_xmit - Tx entry point of te driver
3819 * @skb : the socket buffer containing the Tx data.
3820 * @dev : device pointer.
3821 * Description :
3822 * This function is the Tx entry point of the driver. S2IO NIC supports
3823 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3824 * NOTE: when device cant queue the pkt,just the trans_start variable will
3825 * not be upadted.
3826 * Return value:
3827 * 0 on success & 1 on failure.
3828 */
3829
3830 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3831 {
3832 nic_t *sp = dev->priv;
3833 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3834 register u64 val64;
3835 TxD_t *txdp;
3836 TxFIFO_element_t __iomem *tx_fifo;
3837 unsigned long flags;
3838 u16 vlan_tag = 0;
3839 int vlan_priority = 0;
3840 mac_info_t *mac_control;
3841 struct config_param *config;
3842 int offload_type;
3843
3844 mac_control = &sp->mac_control;
3845 config = &sp->config;
3846
3847 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3848 spin_lock_irqsave(&sp->tx_lock, flags);
3849 if (atomic_read(&sp->card_state) == CARD_DOWN) {
3850 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3851 dev->name);
3852 spin_unlock_irqrestore(&sp->tx_lock, flags);
3853 dev_kfree_skb(skb);
3854 return 0;
3855 }
3856
3857 queue = 0;
3858
3859 /* Get Fifo number to Transmit based on vlan priority */
3860 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3861 vlan_tag = vlan_tx_tag_get(skb);
3862 vlan_priority = vlan_tag >> 13;
3863 queue = config->fifo_mapping[vlan_priority];
3864 }
3865
3866 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3867 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3868 txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3869 list_virt_addr;
3870
3871 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3872 /* Avoid "put" pointer going beyond "get" pointer */
3873 if (txdp->Host_Control ||
3874 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3875 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3876 netif_stop_queue(dev);
3877 dev_kfree_skb(skb);
3878 spin_unlock_irqrestore(&sp->tx_lock, flags);
3879 return 0;
3880 }
3881
3882 /* A buffer with no data will be dropped */
3883 if (!skb->len) {
3884 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3885 dev_kfree_skb(skb);
3886 spin_unlock_irqrestore(&sp->tx_lock, flags);
3887 return 0;
3888 }
3889
3890 offload_type = s2io_offload_type(skb);
3891 #ifdef NETIF_F_TSO
3892 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3893 txdp->Control_1 |= TXD_TCP_LSO_EN;
3894 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
3895 }
3896 #endif
3897 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3898 txdp->Control_2 |=
3899 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3900 TXD_TX_CKO_UDP_EN);
3901 }
3902 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3903 txdp->Control_1 |= TXD_LIST_OWN_XENA;
3904 txdp->Control_2 |= config->tx_intr_type;
3905
3906 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3907 txdp->Control_2 |= TXD_VLAN_ENABLE;
3908 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3909 }
3910
3911 frg_len = skb->len - skb->data_len;
3912 if (offload_type == SKB_GSO_UDP) {
3913 int ufo_size;
3914
3915 ufo_size = s2io_udp_mss(skb);
3916 ufo_size &= ~7;
3917 txdp->Control_1 |= TXD_UFO_EN;
3918 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3919 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3920 #ifdef __BIG_ENDIAN
3921 sp->ufo_in_band_v[put_off] =
3922 (u64)skb_shinfo(skb)->ip6_frag_id;
3923 #else
3924 sp->ufo_in_band_v[put_off] =
3925 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3926 #endif
3927 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3928 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3929 sp->ufo_in_band_v,
3930 sizeof(u64), PCI_DMA_TODEVICE);
3931 txdp++;
3932 }
3933
3934 txdp->Buffer_Pointer = pci_map_single
3935 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3936 txdp->Host_Control = (unsigned long) skb;
3937 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3938 if (offload_type == SKB_GSO_UDP)
3939 txdp->Control_1 |= TXD_UFO_EN;
3940
3941 frg_cnt = skb_shinfo(skb)->nr_frags;
3942 /* For fragmented SKB. */
3943 for (i = 0; i < frg_cnt; i++) {
3944 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3945 /* A '0' length fragment will be ignored */
3946 if (!frag->size)
3947 continue;
3948 txdp++;
3949 txdp->Buffer_Pointer = (u64) pci_map_page
3950 (sp->pdev, frag->page, frag->page_offset,
3951 frag->size, PCI_DMA_TODEVICE);
3952 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
3953 if (offload_type == SKB_GSO_UDP)
3954 txdp->Control_1 |= TXD_UFO_EN;
3955 }
3956 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3957
3958 if (offload_type == SKB_GSO_UDP)
3959 frg_cnt++; /* as Txd0 was used for inband header */
3960
3961 tx_fifo = mac_control->tx_FIFO_start[queue];
3962 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3963 writeq(val64, &tx_fifo->TxDL_Pointer);
3964
3965 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3966 TX_FIFO_LAST_LIST);
3967 if (offload_type)
3968 val64 |= TX_FIFO_SPECIAL_FUNC;
3969
3970 writeq(val64, &tx_fifo->List_Control);
3971
3972 mmiowb();
3973
3974 put_off++;
3975 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3976 put_off = 0;
3977 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3978
3979 /* Avoid "put" pointer going beyond "get" pointer */
3980 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3981 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
3982 DBG_PRINT(TX_DBG,
3983 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3984 put_off, get_off);
3985 netif_stop_queue(dev);
3986 }
3987
3988 dev->trans_start = jiffies;
3989 spin_unlock_irqrestore(&sp->tx_lock, flags);
3990
3991 return 0;
3992 }
3993
3994 static void
3995 s2io_alarm_handle(unsigned long data)
3996 {
3997 nic_t *sp = (nic_t *)data;
3998
3999 alarm_intr_handler(sp);
4000 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4001 }
4002
4003 static int s2io_chk_rx_buffers(nic_t *sp, int rng_n)
4004 {
4005 int rxb_size, level;
4006
4007 if (!sp->lro) {
4008 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4009 level = rx_buffer_level(sp, rxb_size, rng_n);
4010
4011 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4012 int ret;
4013 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4014 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4015 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4016 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4017 __FUNCTION__);
4018 clear_bit(0, (&sp->tasklet_status));
4019 return -1;
4020 }
4021 clear_bit(0, (&sp->tasklet_status));
4022 } else if (level == LOW)
4023 tasklet_schedule(&sp->task);
4024
4025 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4026 DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
4027 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4028 }
4029 return 0;
4030 }
4031
4032 static irqreturn_t
4033 s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
4034 {
4035 struct net_device *dev = (struct net_device *) dev_id;
4036 nic_t *sp = dev->priv;
4037 int i;
4038 mac_info_t *mac_control;
4039 struct config_param *config;
4040
4041 atomic_inc(&sp->isr_cnt);
4042 mac_control = &sp->mac_control;
4043 config = &sp->config;
4044 DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4045
4046 /* If Intr is because of Rx Traffic */
4047 for (i = 0; i < config->rx_ring_num; i++)
4048 rx_intr_handler(&mac_control->rings[i]);
4049
4050 /* If Intr is because of Tx Traffic */
4051 for (i = 0; i < config->tx_fifo_num; i++)
4052 tx_intr_handler(&mac_control->fifos[i]);
4053
4054 /*
4055 * If the Rx buffer count is below the panic threshold then
4056 * reallocate the buffers from the interrupt handler itself,
4057 * else schedule a tasklet to reallocate the buffers.
4058 */
4059 for (i = 0; i < config->rx_ring_num; i++)
4060 s2io_chk_rx_buffers(sp, i);
4061
4062 atomic_dec(&sp->isr_cnt);
4063 return IRQ_HANDLED;
4064 }
4065
4066 static irqreturn_t
4067 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
4068 {
4069 ring_info_t *ring = (ring_info_t *)dev_id;
4070 nic_t *sp = ring->nic;
4071
4072 atomic_inc(&sp->isr_cnt);
4073
4074 rx_intr_handler(ring);
4075 s2io_chk_rx_buffers(sp, ring->ring_no);
4076
4077 atomic_dec(&sp->isr_cnt);
4078 return IRQ_HANDLED;
4079 }
4080
4081 static irqreturn_t
4082 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
4083 {
4084 fifo_info_t *fifo = (fifo_info_t *)dev_id;
4085 nic_t *sp = fifo->nic;
4086
4087 atomic_inc(&sp->isr_cnt);
4088 tx_intr_handler(fifo);
4089 atomic_dec(&sp->isr_cnt);
4090 return IRQ_HANDLED;
4091 }
4092 static void s2io_txpic_intr_handle(nic_t *sp)
4093 {
4094 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4095 u64 val64;
4096
4097 val64 = readq(&bar0->pic_int_status);
4098 if (val64 & PIC_INT_GPIO) {
4099 val64 = readq(&bar0->gpio_int_reg);
4100 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4101 (val64 & GPIO_INT_REG_LINK_UP)) {
4102 /*
4103 * This is unstable state so clear both up/down
4104 * interrupt and adapter to re-evaluate the link state.
4105 */
4106 val64 |= GPIO_INT_REG_LINK_DOWN;
4107 val64 |= GPIO_INT_REG_LINK_UP;
4108 writeq(val64, &bar0->gpio_int_reg);
4109 val64 = readq(&bar0->gpio_int_mask);
4110 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4111 GPIO_INT_MASK_LINK_DOWN);
4112 writeq(val64, &bar0->gpio_int_mask);
4113 }
4114 else if (val64 & GPIO_INT_REG_LINK_UP) {
4115 val64 = readq(&bar0->adapter_status);
4116 if (verify_xena_quiescence(sp, val64,
4117 sp->device_enabled_once)) {
4118 /* Enable Adapter */
4119 val64 = readq(&bar0->adapter_control);
4120 val64 |= ADAPTER_CNTL_EN;
4121 writeq(val64, &bar0->adapter_control);
4122 val64 |= ADAPTER_LED_ON;
4123 writeq(val64, &bar0->adapter_control);
4124 if (!sp->device_enabled_once)
4125 sp->device_enabled_once = 1;
4126
4127 s2io_link(sp, LINK_UP);
4128 /*
4129 * unmask link down interrupt and mask link-up
4130 * intr
4131 */
4132 val64 = readq(&bar0->gpio_int_mask);
4133 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4134 val64 |= GPIO_INT_MASK_LINK_UP;
4135 writeq(val64, &bar0->gpio_int_mask);
4136
4137 }
4138 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4139 val64 = readq(&bar0->adapter_status);
4140 if (verify_xena_quiescence(sp, val64,
4141 sp->device_enabled_once)) {
4142 s2io_link(sp, LINK_DOWN);
4143 /* Link is down so unmaks link up interrupt */
4144 val64 = readq(&bar0->gpio_int_mask);
4145 val64 &= ~GPIO_INT_MASK_LINK_UP;
4146 val64 |= GPIO_INT_MASK_LINK_DOWN;
4147 writeq(val64, &bar0->gpio_int_mask);
4148 }
4149 }
4150 }
4151 val64 = readq(&bar0->gpio_int_mask);
4152 }
4153
4154 /**
4155 * s2io_isr - ISR handler of the device .
4156 * @irq: the irq of the device.
4157 * @dev_id: a void pointer to the dev structure of the NIC.
4158 * @pt_regs: pointer to the registers pushed on the stack.
4159 * Description: This function is the ISR handler of the device. It
4160 * identifies the reason for the interrupt and calls the relevant
4161 * service routines. As a contongency measure, this ISR allocates the
4162 * recv buffers, if their numbers are below the panic value which is
4163 * presently set to 25% of the original number of rcv buffers allocated.
4164 * Return value:
4165 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4166 * IRQ_NONE: will be returned if interrupt is not from our device
4167 */
4168 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
4169 {
4170 struct net_device *dev = (struct net_device *) dev_id;
4171 nic_t *sp = dev->priv;
4172 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4173 int i;
4174 u64 reason = 0, val64, org_mask;
4175 mac_info_t *mac_control;
4176 struct config_param *config;
4177
4178 atomic_inc(&sp->isr_cnt);
4179 mac_control = &sp->mac_control;
4180 config = &sp->config;
4181
4182 /*
4183 * Identify the cause for interrupt and call the appropriate
4184 * interrupt handler. Causes for the interrupt could be;
4185 * 1. Rx of packet.
4186 * 2. Tx complete.
4187 * 3. Link down.
4188 * 4. Error in any functional blocks of the NIC.
4189 */
4190 reason = readq(&bar0->general_int_status);
4191
4192 if (!reason) {
4193 /* The interrupt was not raised by Xena. */
4194 atomic_dec(&sp->isr_cnt);
4195 return IRQ_NONE;
4196 }
4197
4198 val64 = 0xFFFFFFFFFFFFFFFFULL;
4199 /* Store current mask before masking all interrupts */
4200 org_mask = readq(&bar0->general_int_mask);
4201 writeq(val64, &bar0->general_int_mask);
4202
4203 #ifdef CONFIG_S2IO_NAPI
4204 if (reason & GEN_INTR_RXTRAFFIC) {
4205 if (netif_rx_schedule_prep(dev)) {
4206 writeq(val64, &bar0->rx_traffic_mask);
4207 __netif_rx_schedule(dev);
4208 }
4209 }
4210 #else
4211 /*
4212 * Rx handler is called by default, without checking for the
4213 * cause of interrupt.
4214 * rx_traffic_int reg is an R1 register, writing all 1's
4215 * will ensure that the actual interrupt causing bit get's
4216 * cleared and hence a read can be avoided.
4217 */
4218 writeq(val64, &bar0->rx_traffic_int);
4219 for (i = 0; i < config->rx_ring_num; i++) {
4220 rx_intr_handler(&mac_control->rings[i]);
4221 }
4222 #endif
4223
4224 /*
4225 * tx_traffic_int reg is an R1 register, writing all 1's
4226 * will ensure that the actual interrupt causing bit get's
4227 * cleared and hence a read can be avoided.
4228 */
4229 writeq(val64, &bar0->tx_traffic_int);
4230
4231 for (i = 0; i < config->tx_fifo_num; i++)
4232 tx_intr_handler(&mac_control->fifos[i]);
4233
4234 if (reason & GEN_INTR_TXPIC)
4235 s2io_txpic_intr_handle(sp);
4236 /*
4237 * If the Rx buffer count is below the panic threshold then
4238 * reallocate the buffers from the interrupt handler itself,
4239 * else schedule a tasklet to reallocate the buffers.
4240 */
4241 #ifndef CONFIG_S2IO_NAPI
4242 for (i = 0; i < config->rx_ring_num; i++)
4243 s2io_chk_rx_buffers(sp, i);
4244 #endif
4245 writeq(org_mask, &bar0->general_int_mask);
4246 atomic_dec(&sp->isr_cnt);
4247 return IRQ_HANDLED;
4248 }
4249
4250 /**
4251 * s2io_updt_stats -
4252 */
4253 static void s2io_updt_stats(nic_t *sp)
4254 {
4255 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4256 u64 val64;
4257 int cnt = 0;
4258
4259 if (atomic_read(&sp->card_state) == CARD_UP) {
4260 /* Apprx 30us on a 133 MHz bus */
4261 val64 = SET_UPDT_CLICKS(10) |
4262 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4263 writeq(val64, &bar0->stat_cfg);
4264 do {
4265 udelay(100);
4266 val64 = readq(&bar0->stat_cfg);
4267 if (!(val64 & BIT(0)))
4268 break;
4269 cnt++;
4270 if (cnt == 5)
4271 break; /* Updt failed */
4272 } while(1);
4273 } else {
4274 memset(sp->mac_control.stats_info, 0, sizeof(StatInfo_t));
4275 }
4276 }
4277
4278 /**
4279 * s2io_get_stats - Updates the device statistics structure.
4280 * @dev : pointer to the device structure.
4281 * Description:
4282 * This function updates the device statistics structure in the s2io_nic
4283 * structure and returns a pointer to the same.
4284 * Return value:
4285 * pointer to the updated net_device_stats structure.
4286 */
4287
4288 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4289 {
4290 nic_t *sp = dev->priv;
4291 mac_info_t *mac_control;
4292 struct config_param *config;
4293
4294
4295 mac_control = &sp->mac_control;
4296 config = &sp->config;
4297
4298 /* Configure Stats for immediate updt */
4299 s2io_updt_stats(sp);
4300
4301 sp->stats.tx_packets =
4302 le32_to_cpu(mac_control->stats_info->tmac_frms);
4303 sp->stats.tx_errors =
4304 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4305 sp->stats.rx_errors =
4306 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
4307 sp->stats.multicast =
4308 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4309 sp->stats.rx_length_errors =
4310 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
4311
4312 return (&sp->stats);
4313 }
4314
4315 /**
4316 * s2io_set_multicast - entry point for multicast address enable/disable.
4317 * @dev : pointer to the device structure
4318 * Description:
4319 * This function is a driver entry point which gets called by the kernel
4320 * whenever multicast addresses must be enabled/disabled. This also gets
4321 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4322 * determine, if multicast address must be enabled or if promiscuous mode
4323 * is to be disabled etc.
4324 * Return value:
4325 * void.
4326 */
4327
4328 static void s2io_set_multicast(struct net_device *dev)
4329 {
4330 int i, j, prev_cnt;
4331 struct dev_mc_list *mclist;
4332 nic_t *sp = dev->priv;
4333 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4334 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4335 0xfeffffffffffULL;
4336 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4337 void __iomem *add;
4338
4339 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4340 /* Enable all Multicast addresses */
4341 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4342 &bar0->rmac_addr_data0_mem);
4343 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4344 &bar0->rmac_addr_data1_mem);
4345 val64 = RMAC_ADDR_CMD_MEM_WE |
4346 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4347 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4348 writeq(val64, &bar0->rmac_addr_cmd_mem);
4349 /* Wait till command completes */
4350 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4351 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4352
4353 sp->m_cast_flg = 1;
4354 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4355 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4356 /* Disable all Multicast addresses */
4357 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4358 &bar0->rmac_addr_data0_mem);
4359 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4360 &bar0->rmac_addr_data1_mem);
4361 val64 = RMAC_ADDR_CMD_MEM_WE |
4362 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4363 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4364 writeq(val64, &bar0->rmac_addr_cmd_mem);
4365 /* Wait till command completes */
4366 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4367 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4368
4369 sp->m_cast_flg = 0;
4370 sp->all_multi_pos = 0;
4371 }
4372
4373 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4374 /* Put the NIC into promiscuous mode */
4375 add = &bar0->mac_cfg;
4376 val64 = readq(&bar0->mac_cfg);
4377 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4378
4379 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4380 writel((u32) val64, add);
4381 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4382 writel((u32) (val64 >> 32), (add + 4));
4383
4384 val64 = readq(&bar0->mac_cfg);
4385 sp->promisc_flg = 1;
4386 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4387 dev->name);
4388 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4389 /* Remove the NIC from promiscuous mode */
4390 add = &bar0->mac_cfg;
4391 val64 = readq(&bar0->mac_cfg);
4392 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4393
4394 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4395 writel((u32) val64, add);
4396 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4397 writel((u32) (val64 >> 32), (add + 4));
4398
4399 val64 = readq(&bar0->mac_cfg);
4400 sp->promisc_flg = 0;
4401 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4402 dev->name);
4403 }
4404
4405 /* Update individual M_CAST address list */
4406 if ((!sp->m_cast_flg) && dev->mc_count) {
4407 if (dev->mc_count >
4408 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4409 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4410 dev->name);
4411 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4412 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4413 return;
4414 }
4415
4416 prev_cnt = sp->mc_addr_count;
4417 sp->mc_addr_count = dev->mc_count;
4418
4419 /* Clear out the previous list of Mc in the H/W. */
4420 for (i = 0; i < prev_cnt; i++) {
4421 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4422 &bar0->rmac_addr_data0_mem);
4423 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4424 &bar0->rmac_addr_data1_mem);
4425 val64 = RMAC_ADDR_CMD_MEM_WE |
4426 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4427 RMAC_ADDR_CMD_MEM_OFFSET
4428 (MAC_MC_ADDR_START_OFFSET + i);
4429 writeq(val64, &bar0->rmac_addr_cmd_mem);
4430
4431 /* Wait for command completes */
4432 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4433 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4434 DBG_PRINT(ERR_DBG, "%s: Adding ",
4435 dev->name);
4436 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4437 return;
4438 }
4439 }
4440
4441 /* Create the new Rx filter list and update the same in H/W. */
4442 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4443 i++, mclist = mclist->next) {
4444 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4445 ETH_ALEN);
4446 mac_addr = 0;
4447 for (j = 0; j < ETH_ALEN; j++) {
4448 mac_addr |= mclist->dmi_addr[j];
4449 mac_addr <<= 8;
4450 }
4451 mac_addr >>= 8;
4452 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4453 &bar0->rmac_addr_data0_mem);
4454 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4455 &bar0->rmac_addr_data1_mem);
4456 val64 = RMAC_ADDR_CMD_MEM_WE |
4457 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4458 RMAC_ADDR_CMD_MEM_OFFSET
4459 (i + MAC_MC_ADDR_START_OFFSET);
4460 writeq(val64, &bar0->rmac_addr_cmd_mem);
4461
4462 /* Wait for command completes */
4463 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4464 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4465 DBG_PRINT(ERR_DBG, "%s: Adding ",
4466 dev->name);
4467 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4468 return;
4469 }
4470 }
4471 }
4472 }
4473
4474 /**
4475 * s2io_set_mac_addr - Programs the Xframe mac address
4476 * @dev : pointer to the device structure.
4477 * @addr: a uchar pointer to the new mac address which is to be set.
4478 * Description : This procedure will program the Xframe to receive
4479 * frames with new Mac Address
4480 * Return value: SUCCESS on success and an appropriate (-)ve integer
4481 * as defined in errno.h file on failure.
4482 */
4483
4484 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4485 {
4486 nic_t *sp = dev->priv;
4487 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4488 register u64 val64, mac_addr = 0;
4489 int i;
4490
4491 /*
4492 * Set the new MAC address as the new unicast filter and reflect this
4493 * change on the device address registered with the OS. It will be
4494 * at offset 0.
4495 */
4496 for (i = 0; i < ETH_ALEN; i++) {
4497 mac_addr <<= 8;
4498 mac_addr |= addr[i];
4499 }
4500
4501 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4502 &bar0->rmac_addr_data0_mem);
4503
4504 val64 =
4505 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4506 RMAC_ADDR_CMD_MEM_OFFSET(0);
4507 writeq(val64, &bar0->rmac_addr_cmd_mem);
4508 /* Wait till command completes */
4509 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4510 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4511 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4512 return FAILURE;
4513 }
4514
4515 return SUCCESS;
4516 }
4517
4518 /**
4519 * s2io_ethtool_sset - Sets different link parameters.
4520 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4521 * @info: pointer to the structure with parameters given by ethtool to set
4522 * link information.
4523 * Description:
4524 * The function sets different link parameters provided by the user onto
4525 * the NIC.
4526 * Return value:
4527 * 0 on success.
4528 */
4529
4530 static int s2io_ethtool_sset(struct net_device *dev,
4531 struct ethtool_cmd *info)
4532 {
4533 nic_t *sp = dev->priv;
4534 if ((info->autoneg == AUTONEG_ENABLE) ||
4535 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4536 return -EINVAL;
4537 else {
4538 s2io_close(sp->dev);
4539 s2io_open(sp->dev);
4540 }
4541
4542 return 0;
4543 }
4544
4545 /**
4546 * s2io_ethtol_gset - Return link specific information.
4547 * @sp : private member of the device structure, pointer to the
4548 * s2io_nic structure.
4549 * @info : pointer to the structure with parameters given by ethtool
4550 * to return link information.
4551 * Description:
4552 * Returns link specific information like speed, duplex etc.. to ethtool.
4553 * Return value :
4554 * return 0 on success.
4555 */
4556
4557 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4558 {
4559 nic_t *sp = dev->priv;
4560 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4561 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4562 info->port = PORT_FIBRE;
4563 /* info->transceiver?? TODO */
4564
4565 if (netif_carrier_ok(sp->dev)) {
4566 info->speed = 10000;
4567 info->duplex = DUPLEX_FULL;
4568 } else {
4569 info->speed = -1;
4570 info->duplex = -1;
4571 }
4572
4573 info->autoneg = AUTONEG_DISABLE;
4574 return 0;
4575 }
4576
4577 /**
4578 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4579 * @sp : private member of the device structure, which is a pointer to the
4580 * s2io_nic structure.
4581 * @info : pointer to the structure with parameters given by ethtool to
4582 * return driver information.
4583 * Description:
4584 * Returns driver specefic information like name, version etc.. to ethtool.
4585 * Return value:
4586 * void
4587 */
4588
4589 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4590 struct ethtool_drvinfo *info)
4591 {
4592 nic_t *sp = dev->priv;
4593
4594 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4595 strncpy(info->version, s2io_driver_version, sizeof(info->version));
4596 strncpy(info->fw_version, "", sizeof(info->fw_version));
4597 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4598 info->regdump_len = XENA_REG_SPACE;
4599 info->eedump_len = XENA_EEPROM_SPACE;
4600 info->testinfo_len = S2IO_TEST_LEN;
4601 info->n_stats = S2IO_STAT_LEN;
4602 }
4603
4604 /**
4605 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4606 * @sp: private member of the device structure, which is a pointer to the
4607 * s2io_nic structure.
4608 * @regs : pointer to the structure with parameters given by ethtool for
4609 * dumping the registers.
4610 * @reg_space: The input argumnet into which all the registers are dumped.
4611 * Description:
4612 * Dumps the entire register space of xFrame NIC into the user given
4613 * buffer area.
4614 * Return value :
4615 * void .
4616 */
4617
4618 static void s2io_ethtool_gregs(struct net_device *dev,
4619 struct ethtool_regs *regs, void *space)
4620 {
4621 int i;
4622 u64 reg;
4623 u8 *reg_space = (u8 *) space;
4624 nic_t *sp = dev->priv;
4625
4626 regs->len = XENA_REG_SPACE;
4627 regs->version = sp->pdev->subsystem_device;
4628
4629 for (i = 0; i < regs->len; i += 8) {
4630 reg = readq(sp->bar0 + i);
4631 memcpy((reg_space + i), &reg, 8);
4632 }
4633 }
4634
4635 /**
4636 * s2io_phy_id - timer function that alternates adapter LED.
4637 * @data : address of the private member of the device structure, which
4638 * is a pointer to the s2io_nic structure, provided as an u32.
4639 * Description: This is actually the timer function that alternates the
4640 * adapter LED bit of the adapter control bit to set/reset every time on
4641 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4642 * once every second.
4643 */
4644 static void s2io_phy_id(unsigned long data)
4645 {
4646 nic_t *sp = (nic_t *) data;
4647 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4648 u64 val64 = 0;
4649 u16 subid;
4650
4651 subid = sp->pdev->subsystem_device;
4652 if ((sp->device_type == XFRAME_II_DEVICE) ||
4653 ((subid & 0xFF) >= 0x07)) {
4654 val64 = readq(&bar0->gpio_control);
4655 val64 ^= GPIO_CTRL_GPIO_0;
4656 writeq(val64, &bar0->gpio_control);
4657 } else {
4658 val64 = readq(&bar0->adapter_control);
4659 val64 ^= ADAPTER_LED_ON;
4660 writeq(val64, &bar0->adapter_control);
4661 }
4662
4663 mod_timer(&sp->id_timer, jiffies + HZ / 2);
4664 }
4665
4666 /**
4667 * s2io_ethtool_idnic - To physically identify the nic on the system.
4668 * @sp : private member of the device structure, which is a pointer to the
4669 * s2io_nic structure.
4670 * @id : pointer to the structure with identification parameters given by
4671 * ethtool.
4672 * Description: Used to physically identify the NIC on the system.
4673 * The Link LED will blink for a time specified by the user for
4674 * identification.
4675 * NOTE: The Link has to be Up to be able to blink the LED. Hence
4676 * identification is possible only if it's link is up.
4677 * Return value:
4678 * int , returns 0 on success
4679 */
4680
4681 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4682 {
4683 u64 val64 = 0, last_gpio_ctrl_val;
4684 nic_t *sp = dev->priv;
4685 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4686 u16 subid;
4687
4688 subid = sp->pdev->subsystem_device;
4689 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4690 if ((sp->device_type == XFRAME_I_DEVICE) &&
4691 ((subid & 0xFF) < 0x07)) {
4692 val64 = readq(&bar0->adapter_control);
4693 if (!(val64 & ADAPTER_CNTL_EN)) {
4694 printk(KERN_ERR
4695 "Adapter Link down, cannot blink LED\n");
4696 return -EFAULT;
4697 }
4698 }
4699 if (sp->id_timer.function == NULL) {
4700 init_timer(&sp->id_timer);
4701 sp->id_timer.function = s2io_phy_id;
4702 sp->id_timer.data = (unsigned long) sp;
4703 }
4704 mod_timer(&sp->id_timer, jiffies);
4705 if (data)
4706 msleep_interruptible(data * HZ);
4707 else
4708 msleep_interruptible(MAX_FLICKER_TIME);
4709 del_timer_sync(&sp->id_timer);
4710
4711 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4712 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4713 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4714 }
4715
4716 return 0;
4717 }
4718
4719 /**
4720 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4721 * @sp : private member of the device structure, which is a pointer to the
4722 * s2io_nic structure.
4723 * @ep : pointer to the structure with pause parameters given by ethtool.
4724 * Description:
4725 * Returns the Pause frame generation and reception capability of the NIC.
4726 * Return value:
4727 * void
4728 */
4729 static void s2io_ethtool_getpause_data(struct net_device *dev,
4730 struct ethtool_pauseparam *ep)
4731 {
4732 u64 val64;
4733 nic_t *sp = dev->priv;
4734 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4735
4736 val64 = readq(&bar0->rmac_pause_cfg);
4737 if (val64 & RMAC_PAUSE_GEN_ENABLE)
4738 ep->tx_pause = TRUE;
4739 if (val64 & RMAC_PAUSE_RX_ENABLE)
4740 ep->rx_pause = TRUE;
4741 ep->autoneg = FALSE;
4742 }
4743
4744 /**
4745 * s2io_ethtool_setpause_data - set/reset pause frame generation.
4746 * @sp : private member of the device structure, which is a pointer to the
4747 * s2io_nic structure.
4748 * @ep : pointer to the structure with pause parameters given by ethtool.
4749 * Description:
4750 * It can be used to set or reset Pause frame generation or reception
4751 * support of the NIC.
4752 * Return value:
4753 * int, returns 0 on Success
4754 */
4755
4756 static int s2io_ethtool_setpause_data(struct net_device *dev,
4757 struct ethtool_pauseparam *ep)
4758 {
4759 u64 val64;
4760 nic_t *sp = dev->priv;
4761 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4762
4763 val64 = readq(&bar0->rmac_pause_cfg);
4764 if (ep->tx_pause)
4765 val64 |= RMAC_PAUSE_GEN_ENABLE;
4766 else
4767 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4768 if (ep->rx_pause)
4769 val64 |= RMAC_PAUSE_RX_ENABLE;
4770 else
4771 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4772 writeq(val64, &bar0->rmac_pause_cfg);
4773 return 0;
4774 }
4775
4776 /**
4777 * read_eeprom - reads 4 bytes of data from user given offset.
4778 * @sp : private member of the device structure, which is a pointer to the
4779 * s2io_nic structure.
4780 * @off : offset at which the data must be written
4781 * @data : Its an output parameter where the data read at the given
4782 * offset is stored.
4783 * Description:
4784 * Will read 4 bytes of data from the user given offset and return the
4785 * read data.
4786 * NOTE: Will allow to read only part of the EEPROM visible through the
4787 * I2C bus.
4788 * Return value:
4789 * -1 on failure and 0 on success.
4790 */
4791
4792 #define S2IO_DEV_ID 5
4793 static int read_eeprom(nic_t * sp, int off, u64 * data)
4794 {
4795 int ret = -1;
4796 u32 exit_cnt = 0;
4797 u64 val64;
4798 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4799
4800 if (sp->device_type == XFRAME_I_DEVICE) {
4801 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4802 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4803 I2C_CONTROL_CNTL_START;
4804 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4805
4806 while (exit_cnt < 5) {
4807 val64 = readq(&bar0->i2c_control);
4808 if (I2C_CONTROL_CNTL_END(val64)) {
4809 *data = I2C_CONTROL_GET_DATA(val64);
4810 ret = 0;
4811 break;
4812 }
4813 msleep(50);
4814 exit_cnt++;
4815 }
4816 }
4817
4818 if (sp->device_type == XFRAME_II_DEVICE) {
4819 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4820 SPI_CONTROL_BYTECNT(0x3) |
4821 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4822 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4823 val64 |= SPI_CONTROL_REQ;
4824 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4825 while (exit_cnt < 5) {
4826 val64 = readq(&bar0->spi_control);
4827 if (val64 & SPI_CONTROL_NACK) {
4828 ret = 1;
4829 break;
4830 } else if (val64 & SPI_CONTROL_DONE) {
4831 *data = readq(&bar0->spi_data);
4832 *data &= 0xffffff;
4833 ret = 0;
4834 break;
4835 }
4836 msleep(50);
4837 exit_cnt++;
4838 }
4839 }
4840 return ret;
4841 }
4842
4843 /**
4844 * write_eeprom - actually writes the relevant part of the data value.
4845 * @sp : private member of the device structure, which is a pointer to the
4846 * s2io_nic structure.
4847 * @off : offset at which the data must be written
4848 * @data : The data that is to be written
4849 * @cnt : Number of bytes of the data that are actually to be written into
4850 * the Eeprom. (max of 3)
4851 * Description:
4852 * Actually writes the relevant part of the data value into the Eeprom
4853 * through the I2C bus.
4854 * Return value:
4855 * 0 on success, -1 on failure.
4856 */
4857
4858 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4859 {
4860 int exit_cnt = 0, ret = -1;
4861 u64 val64;
4862 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4863
4864 if (sp->device_type == XFRAME_I_DEVICE) {
4865 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4866 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4867 I2C_CONTROL_CNTL_START;
4868 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4869
4870 while (exit_cnt < 5) {
4871 val64 = readq(&bar0->i2c_control);
4872 if (I2C_CONTROL_CNTL_END(val64)) {
4873 if (!(val64 & I2C_CONTROL_NACK))
4874 ret = 0;
4875 break;
4876 }
4877 msleep(50);
4878 exit_cnt++;
4879 }
4880 }
4881
4882 if (sp->device_type == XFRAME_II_DEVICE) {
4883 int write_cnt = (cnt == 8) ? 0 : cnt;
4884 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4885
4886 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4887 SPI_CONTROL_BYTECNT(write_cnt) |
4888 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4889 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4890 val64 |= SPI_CONTROL_REQ;
4891 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4892 while (exit_cnt < 5) {
4893 val64 = readq(&bar0->spi_control);
4894 if (val64 & SPI_CONTROL_NACK) {
4895 ret = 1;
4896 break;
4897 } else if (val64 & SPI_CONTROL_DONE) {
4898 ret = 0;
4899 break;
4900 }
4901 msleep(50);
4902 exit_cnt++;
4903 }
4904 }
4905 return ret;
4906 }
4907 static void s2io_vpd_read(nic_t *nic)
4908 {
4909 u8 *vpd_data;
4910 u8 data;
4911 int i=0, cnt, fail = 0;
4912 int vpd_addr = 0x80;
4913
4914 if (nic->device_type == XFRAME_II_DEVICE) {
4915 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4916 vpd_addr = 0x80;
4917 }
4918 else {
4919 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4920 vpd_addr = 0x50;
4921 }
4922
4923 vpd_data = kmalloc(256, GFP_KERNEL);
4924 if (!vpd_data)
4925 return;
4926
4927 for (i = 0; i < 256; i +=4 ) {
4928 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4929 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
4930 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4931 for (cnt = 0; cnt <5; cnt++) {
4932 msleep(2);
4933 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4934 if (data == 0x80)
4935 break;
4936 }
4937 if (cnt >= 5) {
4938 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
4939 fail = 1;
4940 break;
4941 }
4942 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
4943 (u32 *)&vpd_data[i]);
4944 }
4945 if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) {
4946 memset(nic->product_name, 0, vpd_data[1]);
4947 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4948 }
4949 kfree(vpd_data);
4950 }
4951
4952 /**
4953 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
4954 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4955 * @eeprom : pointer to the user level structure provided by ethtool,
4956 * containing all relevant information.
4957 * @data_buf : user defined value to be written into Eeprom.
4958 * Description: Reads the values stored in the Eeprom at given offset
4959 * for a given length. Stores these values int the input argument data
4960 * buffer 'data_buf' and returns these to the caller (ethtool.)
4961 * Return value:
4962 * int 0 on success
4963 */
4964
4965 static int s2io_ethtool_geeprom(struct net_device *dev,
4966 struct ethtool_eeprom *eeprom, u8 * data_buf)
4967 {
4968 u32 i, valid;
4969 u64 data;
4970 nic_t *sp = dev->priv;
4971
4972 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4973
4974 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4975 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4976
4977 for (i = 0; i < eeprom->len; i += 4) {
4978 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4979 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4980 return -EFAULT;
4981 }
4982 valid = INV(data);
4983 memcpy((data_buf + i), &valid, 4);
4984 }
4985 return 0;
4986 }
4987
4988 /**
4989 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4990 * @sp : private member of the device structure, which is a pointer to the
4991 * s2io_nic structure.
4992 * @eeprom : pointer to the user level structure provided by ethtool,
4993 * containing all relevant information.
4994 * @data_buf ; user defined value to be written into Eeprom.
4995 * Description:
4996 * Tries to write the user provided value in the Eeprom, at the offset
4997 * given by the user.
4998 * Return value:
4999 * 0 on success, -EFAULT on failure.
5000 */
5001
5002 static int s2io_ethtool_seeprom(struct net_device *dev,
5003 struct ethtool_eeprom *eeprom,
5004 u8 * data_buf)
5005 {
5006 int len = eeprom->len, cnt = 0;
5007 u64 valid = 0, data;
5008 nic_t *sp = dev->priv;
5009
5010 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5011 DBG_PRINT(ERR_DBG,
5012 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5013 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5014 eeprom->magic);
5015 return -EFAULT;
5016 }
5017
5018 while (len) {
5019 data = (u32) data_buf[cnt] & 0x000000FF;
5020 if (data) {
5021 valid = (u32) (data << 24);
5022 } else
5023 valid = data;
5024
5025 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5026 DBG_PRINT(ERR_DBG,
5027 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5028 DBG_PRINT(ERR_DBG,
5029 "write into the specified offset\n");
5030 return -EFAULT;
5031 }
5032 cnt++;
5033 len--;
5034 }
5035
5036 return 0;
5037 }
5038
5039 /**
5040 * s2io_register_test - reads and writes into all clock domains.
5041 * @sp : private member of the device structure, which is a pointer to the
5042 * s2io_nic structure.
5043 * @data : variable that returns the result of each of the test conducted b
5044 * by the driver.
5045 * Description:
5046 * Read and write into all clock domains. The NIC has 3 clock domains,
5047 * see that registers in all the three regions are accessible.
5048 * Return value:
5049 * 0 on success.
5050 */
5051
5052 static int s2io_register_test(nic_t * sp, uint64_t * data)
5053 {
5054 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5055 u64 val64 = 0, exp_val;
5056 int fail = 0;
5057
5058 val64 = readq(&bar0->pif_rd_swapper_fb);
5059 if (val64 != 0x123456789abcdefULL) {
5060 fail = 1;
5061 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5062 }
5063
5064 val64 = readq(&bar0->rmac_pause_cfg);
5065 if (val64 != 0xc000ffff00000000ULL) {
5066 fail = 1;
5067 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5068 }
5069
5070 val64 = readq(&bar0->rx_queue_cfg);
5071 if (sp->device_type == XFRAME_II_DEVICE)
5072 exp_val = 0x0404040404040404ULL;
5073 else
5074 exp_val = 0x0808080808080808ULL;
5075 if (val64 != exp_val) {
5076 fail = 1;
5077 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5078 }
5079
5080 val64 = readq(&bar0->xgxs_efifo_cfg);
5081 if (val64 != 0x000000001923141EULL) {
5082 fail = 1;
5083 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5084 }
5085
5086 val64 = 0x5A5A5A5A5A5A5A5AULL;
5087 writeq(val64, &bar0->xmsi_data);
5088 val64 = readq(&bar0->xmsi_data);
5089 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5090 fail = 1;
5091 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5092 }
5093
5094 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5095 writeq(val64, &bar0->xmsi_data);
5096 val64 = readq(&bar0->xmsi_data);
5097 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5098 fail = 1;
5099 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5100 }
5101
5102 *data = fail;
5103 return fail;
5104 }
5105
5106 /**
5107 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5108 * @sp : private member of the device structure, which is a pointer to the
5109 * s2io_nic structure.
5110 * @data:variable that returns the result of each of the test conducted by
5111 * the driver.
5112 * Description:
5113 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5114 * register.
5115 * Return value:
5116 * 0 on success.
5117 */
5118
5119 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
5120 {
5121 int fail = 0;
5122 u64 ret_data, org_4F0, org_7F0;
5123 u8 saved_4F0 = 0, saved_7F0 = 0;
5124 struct net_device *dev = sp->dev;
5125
5126 /* Test Write Error at offset 0 */
5127 /* Note that SPI interface allows write access to all areas
5128 * of EEPROM. Hence doing all negative testing only for Xframe I.
5129 */
5130 if (sp->device_type == XFRAME_I_DEVICE)
5131 if (!write_eeprom(sp, 0, 0, 3))
5132 fail = 1;
5133
5134 /* Save current values at offsets 0x4F0 and 0x7F0 */
5135 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5136 saved_4F0 = 1;
5137 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5138 saved_7F0 = 1;
5139
5140 /* Test Write at offset 4f0 */
5141 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5142 fail = 1;
5143 if (read_eeprom(sp, 0x4F0, &ret_data))
5144 fail = 1;
5145
5146 if (ret_data != 0x012345) {
5147 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5148 "Data written %llx Data read %llx\n",
5149 dev->name, (unsigned long long)0x12345,
5150 (unsigned long long)ret_data);
5151 fail = 1;
5152 }
5153
5154 /* Reset the EEPROM data go FFFF */
5155 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5156
5157 /* Test Write Request Error at offset 0x7c */
5158 if (sp->device_type == XFRAME_I_DEVICE)
5159 if (!write_eeprom(sp, 0x07C, 0, 3))
5160 fail = 1;
5161
5162 /* Test Write Request at offset 0x7f0 */
5163 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5164 fail = 1;
5165 if (read_eeprom(sp, 0x7F0, &ret_data))
5166 fail = 1;
5167
5168 if (ret_data != 0x012345) {
5169 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5170 "Data written %llx Data read %llx\n",
5171 dev->name, (unsigned long long)0x12345,
5172 (unsigned long long)ret_data);
5173 fail = 1;
5174 }
5175
5176 /* Reset the EEPROM data go FFFF */
5177 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5178
5179 if (sp->device_type == XFRAME_I_DEVICE) {
5180 /* Test Write Error at offset 0x80 */
5181 if (!write_eeprom(sp, 0x080, 0, 3))
5182 fail = 1;
5183
5184 /* Test Write Error at offset 0xfc */
5185 if (!write_eeprom(sp, 0x0FC, 0, 3))
5186 fail = 1;
5187
5188 /* Test Write Error at offset 0x100 */
5189 if (!write_eeprom(sp, 0x100, 0, 3))
5190 fail = 1;
5191
5192 /* Test Write Error at offset 4ec */
5193 if (!write_eeprom(sp, 0x4EC, 0, 3))
5194 fail = 1;
5195 }
5196
5197 /* Restore values at offsets 0x4F0 and 0x7F0 */
5198 if (saved_4F0)
5199 write_eeprom(sp, 0x4F0, org_4F0, 3);
5200 if (saved_7F0)
5201 write_eeprom(sp, 0x7F0, org_7F0, 3);
5202
5203 *data = fail;
5204 return fail;
5205 }
5206
5207 /**
5208 * s2io_bist_test - invokes the MemBist test of the card .
5209 * @sp : private member of the device structure, which is a pointer to the
5210 * s2io_nic structure.
5211 * @data:variable that returns the result of each of the test conducted by
5212 * the driver.
5213 * Description:
5214 * This invokes the MemBist test of the card. We give around
5215 * 2 secs time for the Test to complete. If it's still not complete
5216 * within this peiod, we consider that the test failed.
5217 * Return value:
5218 * 0 on success and -1 on failure.
5219 */
5220
5221 static int s2io_bist_test(nic_t * sp, uint64_t * data)
5222 {
5223 u8 bist = 0;
5224 int cnt = 0, ret = -1;
5225
5226 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5227 bist |= PCI_BIST_START;
5228 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5229
5230 while (cnt < 20) {
5231 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5232 if (!(bist & PCI_BIST_START)) {
5233 *data = (bist & PCI_BIST_CODE_MASK);
5234 ret = 0;
5235 break;
5236 }
5237 msleep(100);
5238 cnt++;
5239 }
5240
5241 return ret;
5242 }
5243
5244 /**
5245 * s2io-link_test - verifies the link state of the nic
5246 * @sp ; private member of the device structure, which is a pointer to the
5247 * s2io_nic structure.
5248 * @data: variable that returns the result of each of the test conducted by
5249 * the driver.
5250 * Description:
5251 * The function verifies the link state of the NIC and updates the input
5252 * argument 'data' appropriately.
5253 * Return value:
5254 * 0 on success.
5255 */
5256
5257 static int s2io_link_test(nic_t * sp, uint64_t * data)
5258 {
5259 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5260 u64 val64;
5261
5262 val64 = readq(&bar0->adapter_status);
5263 if(!(LINK_IS_UP(val64)))
5264 *data = 1;
5265 else
5266 *data = 0;
5267
5268 return *data;
5269 }
5270
5271 /**
5272 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5273 * @sp - private member of the device structure, which is a pointer to the
5274 * s2io_nic structure.
5275 * @data - variable that returns the result of each of the test
5276 * conducted by the driver.
5277 * Description:
5278 * This is one of the offline test that tests the read and write
5279 * access to the RldRam chip on the NIC.
5280 * Return value:
5281 * 0 on success.
5282 */
5283
5284 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
5285 {
5286 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5287 u64 val64;
5288 int cnt, iteration = 0, test_fail = 0;
5289
5290 val64 = readq(&bar0->adapter_control);
5291 val64 &= ~ADAPTER_ECC_EN;
5292 writeq(val64, &bar0->adapter_control);
5293
5294 val64 = readq(&bar0->mc_rldram_test_ctrl);
5295 val64 |= MC_RLDRAM_TEST_MODE;
5296 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5297
5298 val64 = readq(&bar0->mc_rldram_mrs);
5299 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5300 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5301
5302 val64 |= MC_RLDRAM_MRS_ENABLE;
5303 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5304
5305 while (iteration < 2) {
5306 val64 = 0x55555555aaaa0000ULL;
5307 if (iteration == 1) {
5308 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5309 }
5310 writeq(val64, &bar0->mc_rldram_test_d0);
5311
5312 val64 = 0xaaaa5a5555550000ULL;
5313 if (iteration == 1) {
5314 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5315 }
5316 writeq(val64, &bar0->mc_rldram_test_d1);
5317
5318 val64 = 0x55aaaaaaaa5a0000ULL;
5319 if (iteration == 1) {
5320 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5321 }
5322 writeq(val64, &bar0->mc_rldram_test_d2);
5323
5324 val64 = (u64) (0x0000003ffffe0100ULL);
5325 writeq(val64, &bar0->mc_rldram_test_add);
5326
5327 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5328 MC_RLDRAM_TEST_GO;
5329 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5330
5331 for (cnt = 0; cnt < 5; cnt++) {
5332 val64 = readq(&bar0->mc_rldram_test_ctrl);
5333 if (val64 & MC_RLDRAM_TEST_DONE)
5334 break;
5335 msleep(200);
5336 }
5337
5338 if (cnt == 5)
5339 break;
5340
5341 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5342 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5343
5344 for (cnt = 0; cnt < 5; cnt++) {
5345 val64 = readq(&bar0->mc_rldram_test_ctrl);
5346 if (val64 & MC_RLDRAM_TEST_DONE)
5347 break;
5348 msleep(500);
5349 }
5350
5351 if (cnt == 5)
5352 break;
5353
5354 val64 = readq(&bar0->mc_rldram_test_ctrl);
5355 if (!(val64 & MC_RLDRAM_TEST_PASS))
5356 test_fail = 1;
5357
5358 iteration++;
5359 }
5360
5361 *data = test_fail;
5362
5363 /* Bring the adapter out of test mode */
5364 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5365
5366 return test_fail;
5367 }
5368
5369 /**
5370 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5371 * @sp : private member of the device structure, which is a pointer to the
5372 * s2io_nic structure.
5373 * @ethtest : pointer to a ethtool command specific structure that will be
5374 * returned to the user.
5375 * @data : variable that returns the result of each of the test
5376 * conducted by the driver.
5377 * Description:
5378 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5379 * the health of the card.
5380 * Return value:
5381 * void
5382 */
5383
5384 static void s2io_ethtool_test(struct net_device *dev,
5385 struct ethtool_test *ethtest,
5386 uint64_t * data)
5387 {
5388 nic_t *sp = dev->priv;
5389 int orig_state = netif_running(sp->dev);
5390
5391 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5392 /* Offline Tests. */
5393 if (orig_state)
5394 s2io_close(sp->dev);
5395
5396 if (s2io_register_test(sp, &data[0]))
5397 ethtest->flags |= ETH_TEST_FL_FAILED;
5398
5399 s2io_reset(sp);
5400
5401 if (s2io_rldram_test(sp, &data[3]))
5402 ethtest->flags |= ETH_TEST_FL_FAILED;
5403
5404 s2io_reset(sp);
5405
5406 if (s2io_eeprom_test(sp, &data[1]))
5407 ethtest->flags |= ETH_TEST_FL_FAILED;
5408
5409 if (s2io_bist_test(sp, &data[4]))
5410 ethtest->flags |= ETH_TEST_FL_FAILED;
5411
5412 if (orig_state)
5413 s2io_open(sp->dev);
5414
5415 data[2] = 0;
5416 } else {
5417 /* Online Tests. */
5418 if (!orig_state) {
5419 DBG_PRINT(ERR_DBG,
5420 "%s: is not up, cannot run test\n",
5421 dev->name);
5422 data[0] = -1;
5423 data[1] = -1;
5424 data[2] = -1;
5425 data[3] = -1;
5426 data[4] = -1;
5427 }
5428
5429 if (s2io_link_test(sp, &data[2]))
5430 ethtest->flags |= ETH_TEST_FL_FAILED;
5431
5432 data[0] = 0;
5433 data[1] = 0;
5434 data[3] = 0;
5435 data[4] = 0;
5436 }
5437 }
5438
5439 static void s2io_get_ethtool_stats(struct net_device *dev,
5440 struct ethtool_stats *estats,
5441 u64 * tmp_stats)
5442 {
5443 int i = 0;
5444 nic_t *sp = dev->priv;
5445 StatInfo_t *stat_info = sp->mac_control.stats_info;
5446
5447 s2io_updt_stats(sp);
5448 tmp_stats[i++] =
5449 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5450 le32_to_cpu(stat_info->tmac_frms);
5451 tmp_stats[i++] =
5452 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5453 le32_to_cpu(stat_info->tmac_data_octets);
5454 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5455 tmp_stats[i++] =
5456 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5457 le32_to_cpu(stat_info->tmac_mcst_frms);
5458 tmp_stats[i++] =
5459 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5460 le32_to_cpu(stat_info->tmac_bcst_frms);
5461 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5462 tmp_stats[i++] =
5463 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5464 le32_to_cpu(stat_info->tmac_ttl_octets);
5465 tmp_stats[i++] =
5466 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5467 le32_to_cpu(stat_info->tmac_ucst_frms);
5468 tmp_stats[i++] =
5469 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5470 le32_to_cpu(stat_info->tmac_nucst_frms);
5471 tmp_stats[i++] =
5472 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5473 le32_to_cpu(stat_info->tmac_any_err_frms);
5474 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5475 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5476 tmp_stats[i++] =
5477 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5478 le32_to_cpu(stat_info->tmac_vld_ip);
5479 tmp_stats[i++] =
5480 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5481 le32_to_cpu(stat_info->tmac_drop_ip);
5482 tmp_stats[i++] =
5483 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5484 le32_to_cpu(stat_info->tmac_icmp);
5485 tmp_stats[i++] =
5486 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5487 le32_to_cpu(stat_info->tmac_rst_tcp);
5488 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5489 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5490 le32_to_cpu(stat_info->tmac_udp);
5491 tmp_stats[i++] =
5492 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5493 le32_to_cpu(stat_info->rmac_vld_frms);
5494 tmp_stats[i++] =
5495 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5496 le32_to_cpu(stat_info->rmac_data_octets);
5497 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5498 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5499 tmp_stats[i++] =
5500 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5501 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5502 tmp_stats[i++] =
5503 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5504 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5505 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5506 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
5507 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5508 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5509 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5510 tmp_stats[i++] =
5511 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5512 le32_to_cpu(stat_info->rmac_ttl_octets);
5513 tmp_stats[i++] =
5514 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5515 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5516 tmp_stats[i++] =
5517 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5518 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
5519 tmp_stats[i++] =
5520 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5521 le32_to_cpu(stat_info->rmac_discarded_frms);
5522 tmp_stats[i++] =
5523 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5524 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5525 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5526 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
5527 tmp_stats[i++] =
5528 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5529 le32_to_cpu(stat_info->rmac_usized_frms);
5530 tmp_stats[i++] =
5531 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5532 le32_to_cpu(stat_info->rmac_osized_frms);
5533 tmp_stats[i++] =
5534 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5535 le32_to_cpu(stat_info->rmac_frag_frms);
5536 tmp_stats[i++] =
5537 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5538 le32_to_cpu(stat_info->rmac_jabber_frms);
5539 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5540 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5541 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5542 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5543 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5544 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5545 tmp_stats[i++] =
5546 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5547 le32_to_cpu(stat_info->rmac_ip);
5548 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5549 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5550 tmp_stats[i++] =
5551 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5552 le32_to_cpu(stat_info->rmac_drop_ip);
5553 tmp_stats[i++] =
5554 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5555 le32_to_cpu(stat_info->rmac_icmp);
5556 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5557 tmp_stats[i++] =
5558 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5559 le32_to_cpu(stat_info->rmac_udp);
5560 tmp_stats[i++] =
5561 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5562 le32_to_cpu(stat_info->rmac_err_drp_udp);
5563 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5564 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5565 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5566 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5567 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5568 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5569 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5570 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5571 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5572 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5573 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5574 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5575 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5576 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5577 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5578 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5579 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
5580 tmp_stats[i++] =
5581 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5582 le32_to_cpu(stat_info->rmac_pause_cnt);
5583 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5584 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
5585 tmp_stats[i++] =
5586 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5587 le32_to_cpu(stat_info->rmac_accepted_ip);
5588 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5589 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5590 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5591 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5592 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5593 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5594 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5595 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5596 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5597 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5598 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5599 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5600 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5601 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5602 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5603 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5604 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5605 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5606 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5607 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5608 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5609 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5610 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5611 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5612 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5613 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5614 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5615 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5616 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5617 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5618 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5619 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5620 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5621 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5622 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5623 tmp_stats[i++] = 0;
5624 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5625 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5626 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5627 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5628 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5629 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5630 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5631 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5632 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5633 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5634 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5635 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5636 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5637 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5638 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5639 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5640 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5641 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5642 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
5643 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5644 tmp_stats[i++] = stat_info->sw_stat.sending_both;
5645 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5646 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
5647 if (stat_info->sw_stat.num_aggregations) {
5648 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5649 int count = 0;
5650 /*
5651 * Since 64-bit divide does not work on all platforms,
5652 * do repeated subtraction.
5653 */
5654 while (tmp >= stat_info->sw_stat.num_aggregations) {
5655 tmp -= stat_info->sw_stat.num_aggregations;
5656 count++;
5657 }
5658 tmp_stats[i++] = count;
5659 }
5660 else
5661 tmp_stats[i++] = 0;
5662 }
5663
5664 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5665 {
5666 return (XENA_REG_SPACE);
5667 }
5668
5669
5670 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5671 {
5672 nic_t *sp = dev->priv;
5673
5674 return (sp->rx_csum);
5675 }
5676
5677 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5678 {
5679 nic_t *sp = dev->priv;
5680
5681 if (data)
5682 sp->rx_csum = 1;
5683 else
5684 sp->rx_csum = 0;
5685
5686 return 0;
5687 }
5688
5689 static int s2io_get_eeprom_len(struct net_device *dev)
5690 {
5691 return (XENA_EEPROM_SPACE);
5692 }
5693
5694 static int s2io_ethtool_self_test_count(struct net_device *dev)
5695 {
5696 return (S2IO_TEST_LEN);
5697 }
5698
5699 static void s2io_ethtool_get_strings(struct net_device *dev,
5700 u32 stringset, u8 * data)
5701 {
5702 switch (stringset) {
5703 case ETH_SS_TEST:
5704 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5705 break;
5706 case ETH_SS_STATS:
5707 memcpy(data, &ethtool_stats_keys,
5708 sizeof(ethtool_stats_keys));
5709 }
5710 }
5711 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5712 {
5713 return (S2IO_STAT_LEN);
5714 }
5715
5716 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5717 {
5718 if (data)
5719 dev->features |= NETIF_F_IP_CSUM;
5720 else
5721 dev->features &= ~NETIF_F_IP_CSUM;
5722
5723 return 0;
5724 }
5725
5726 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5727 {
5728 return (dev->features & NETIF_F_TSO) != 0;
5729 }
5730 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5731 {
5732 if (data)
5733 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5734 else
5735 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5736
5737 return 0;
5738 }
5739
5740 static const struct ethtool_ops netdev_ethtool_ops = {
5741 .get_settings = s2io_ethtool_gset,
5742 .set_settings = s2io_ethtool_sset,
5743 .get_drvinfo = s2io_ethtool_gdrvinfo,
5744 .get_regs_len = s2io_ethtool_get_regs_len,
5745 .get_regs = s2io_ethtool_gregs,
5746 .get_link = ethtool_op_get_link,
5747 .get_eeprom_len = s2io_get_eeprom_len,
5748 .get_eeprom = s2io_ethtool_geeprom,
5749 .set_eeprom = s2io_ethtool_seeprom,
5750 .get_pauseparam = s2io_ethtool_getpause_data,
5751 .set_pauseparam = s2io_ethtool_setpause_data,
5752 .get_rx_csum = s2io_ethtool_get_rx_csum,
5753 .set_rx_csum = s2io_ethtool_set_rx_csum,
5754 .get_tx_csum = ethtool_op_get_tx_csum,
5755 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5756 .get_sg = ethtool_op_get_sg,
5757 .set_sg = ethtool_op_set_sg,
5758 #ifdef NETIF_F_TSO
5759 .get_tso = s2io_ethtool_op_get_tso,
5760 .set_tso = s2io_ethtool_op_set_tso,
5761 #endif
5762 .get_ufo = ethtool_op_get_ufo,
5763 .set_ufo = ethtool_op_set_ufo,
5764 .self_test_count = s2io_ethtool_self_test_count,
5765 .self_test = s2io_ethtool_test,
5766 .get_strings = s2io_ethtool_get_strings,
5767 .phys_id = s2io_ethtool_idnic,
5768 .get_stats_count = s2io_ethtool_get_stats_count,
5769 .get_ethtool_stats = s2io_get_ethtool_stats
5770 };
5771
5772 /**
5773 * s2io_ioctl - Entry point for the Ioctl
5774 * @dev : Device pointer.
5775 * @ifr : An IOCTL specefic structure, that can contain a pointer to
5776 * a proprietary structure used to pass information to the driver.
5777 * @cmd : This is used to distinguish between the different commands that
5778 * can be passed to the IOCTL functions.
5779 * Description:
5780 * Currently there are no special functionality supported in IOCTL, hence
5781 * function always return EOPNOTSUPPORTED
5782 */
5783
5784 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5785 {
5786 return -EOPNOTSUPP;
5787 }
5788
5789 /**
5790 * s2io_change_mtu - entry point to change MTU size for the device.
5791 * @dev : device pointer.
5792 * @new_mtu : the new MTU size for the device.
5793 * Description: A driver entry point to change MTU size for the device.
5794 * Before changing the MTU the device must be stopped.
5795 * Return value:
5796 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5797 * file on failure.
5798 */
5799
5800 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5801 {
5802 nic_t *sp = dev->priv;
5803
5804 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5805 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5806 dev->name);
5807 return -EPERM;
5808 }
5809
5810 dev->mtu = new_mtu;
5811 if (netif_running(dev)) {
5812 s2io_card_down(sp);
5813 netif_stop_queue(dev);
5814 if (s2io_card_up(sp)) {
5815 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5816 __FUNCTION__);
5817 }
5818 if (netif_queue_stopped(dev))
5819 netif_wake_queue(dev);
5820 } else { /* Device is down */
5821 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5822 u64 val64 = new_mtu;
5823
5824 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5825 }
5826
5827 return 0;
5828 }
5829
5830 /**
5831 * s2io_tasklet - Bottom half of the ISR.
5832 * @dev_adr : address of the device structure in dma_addr_t format.
5833 * Description:
5834 * This is the tasklet or the bottom half of the ISR. This is
5835 * an extension of the ISR which is scheduled by the scheduler to be run
5836 * when the load on the CPU is low. All low priority tasks of the ISR can
5837 * be pushed into the tasklet. For now the tasklet is used only to
5838 * replenish the Rx buffers in the Rx buffer descriptors.
5839 * Return value:
5840 * void.
5841 */
5842
5843 static void s2io_tasklet(unsigned long dev_addr)
5844 {
5845 struct net_device *dev = (struct net_device *) dev_addr;
5846 nic_t *sp = dev->priv;
5847 int i, ret;
5848 mac_info_t *mac_control;
5849 struct config_param *config;
5850
5851 mac_control = &sp->mac_control;
5852 config = &sp->config;
5853
5854 if (!TASKLET_IN_USE) {
5855 for (i = 0; i < config->rx_ring_num; i++) {
5856 ret = fill_rx_buffers(sp, i);
5857 if (ret == -ENOMEM) {
5858 DBG_PRINT(ERR_DBG, "%s: Out of ",
5859 dev->name);
5860 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5861 break;
5862 } else if (ret == -EFILL) {
5863 DBG_PRINT(ERR_DBG,
5864 "%s: Rx Ring %d is full\n",
5865 dev->name, i);
5866 break;
5867 }
5868 }
5869 clear_bit(0, (&sp->tasklet_status));
5870 }
5871 }
5872
5873 /**
5874 * s2io_set_link - Set the LInk status
5875 * @data: long pointer to device private structue
5876 * Description: Sets the link status for the adapter
5877 */
5878
5879 static void s2io_set_link(unsigned long data)
5880 {
5881 nic_t *nic = (nic_t *) data;
5882 struct net_device *dev = nic->dev;
5883 XENA_dev_config_t __iomem *bar0 = nic->bar0;
5884 register u64 val64;
5885 u16 subid;
5886
5887 if (test_and_set_bit(0, &(nic->link_state))) {
5888 /* The card is being reset, no point doing anything */
5889 return;
5890 }
5891
5892 subid = nic->pdev->subsystem_device;
5893 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5894 /*
5895 * Allow a small delay for the NICs self initiated
5896 * cleanup to complete.
5897 */
5898 msleep(100);
5899 }
5900
5901 val64 = readq(&bar0->adapter_status);
5902 if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
5903 if (LINK_IS_UP(val64)) {
5904 val64 = readq(&bar0->adapter_control);
5905 val64 |= ADAPTER_CNTL_EN;
5906 writeq(val64, &bar0->adapter_control);
5907 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5908 subid)) {
5909 val64 = readq(&bar0->gpio_control);
5910 val64 |= GPIO_CTRL_GPIO_0;
5911 writeq(val64, &bar0->gpio_control);
5912 val64 = readq(&bar0->gpio_control);
5913 } else {
5914 val64 |= ADAPTER_LED_ON;
5915 writeq(val64, &bar0->adapter_control);
5916 }
5917 if (s2io_link_fault_indication(nic) ==
5918 MAC_RMAC_ERR_TIMER) {
5919 val64 = readq(&bar0->adapter_status);
5920 if (!LINK_IS_UP(val64)) {
5921 DBG_PRINT(ERR_DBG, "%s:", dev->name);
5922 DBG_PRINT(ERR_DBG, " Link down");
5923 DBG_PRINT(ERR_DBG, "after ");
5924 DBG_PRINT(ERR_DBG, "enabling ");
5925 DBG_PRINT(ERR_DBG, "device \n");
5926 }
5927 }
5928 if (nic->device_enabled_once == FALSE) {
5929 nic->device_enabled_once = TRUE;
5930 }
5931 s2io_link(nic, LINK_UP);
5932 } else {
5933 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5934 subid)) {
5935 val64 = readq(&bar0->gpio_control);
5936 val64 &= ~GPIO_CTRL_GPIO_0;
5937 writeq(val64, &bar0->gpio_control);
5938 val64 = readq(&bar0->gpio_control);
5939 }
5940 s2io_link(nic, LINK_DOWN);
5941 }
5942 } else { /* NIC is not Quiescent. */
5943 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5944 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5945 netif_stop_queue(dev);
5946 }
5947 clear_bit(0, &(nic->link_state));
5948 }
5949
5950 static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
5951 struct sk_buff **skb, u64 *temp0, u64 *temp1,
5952 u64 *temp2, int size)
5953 {
5954 struct net_device *dev = sp->dev;
5955 struct sk_buff *frag_list;
5956
5957 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
5958 /* allocate skb */
5959 if (*skb) {
5960 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
5961 /*
5962 * As Rx frame are not going to be processed,
5963 * using same mapped address for the Rxd
5964 * buffer pointer
5965 */
5966 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0;
5967 } else {
5968 *skb = dev_alloc_skb(size);
5969 if (!(*skb)) {
5970 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
5971 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
5972 return -ENOMEM ;
5973 }
5974 /* storing the mapped addr in a temp variable
5975 * such it will be used for next rxd whose
5976 * Host Control is NULL
5977 */
5978 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0 =
5979 pci_map_single( sp->pdev, (*skb)->data,
5980 size - NET_IP_ALIGN,
5981 PCI_DMA_FROMDEVICE);
5982 rxdp->Host_Control = (unsigned long) (*skb);
5983 }
5984 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
5985 /* Two buffer Mode */
5986 if (*skb) {
5987 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
5988 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
5989 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
5990 } else {
5991 *skb = dev_alloc_skb(size);
5992 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
5993 pci_map_single(sp->pdev, (*skb)->data,
5994 dev->mtu + 4,
5995 PCI_DMA_FROMDEVICE);
5996 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
5997 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
5998 PCI_DMA_FROMDEVICE);
5999 rxdp->Host_Control = (unsigned long) (*skb);
6000
6001 /* Buffer-1 will be dummy buffer not used */
6002 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6003 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6004 PCI_DMA_FROMDEVICE);
6005 }
6006 } else if ((rxdp->Host_Control == 0)) {
6007 /* Three buffer mode */
6008 if (*skb) {
6009 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
6010 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
6011 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
6012 } else {
6013 *skb = dev_alloc_skb(size);
6014
6015 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
6016 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6017 PCI_DMA_FROMDEVICE);
6018 /* Buffer-1 receives L3/L4 headers */
6019 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6020 pci_map_single( sp->pdev, (*skb)->data,
6021 l3l4hdr_size + 4,
6022 PCI_DMA_FROMDEVICE);
6023 /*
6024 * skb_shinfo(skb)->frag_list will have L4
6025 * data payload
6026 */
6027 skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6028 ALIGN_SIZE);
6029 if (skb_shinfo(*skb)->frag_list == NULL) {
6030 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6031 failed\n ", dev->name);
6032 return -ENOMEM ;
6033 }
6034 frag_list = skb_shinfo(*skb)->frag_list;
6035 frag_list->next = NULL;
6036 /*
6037 * Buffer-2 receives L4 data payload
6038 */
6039 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
6040 pci_map_single( sp->pdev, frag_list->data,
6041 dev->mtu, PCI_DMA_FROMDEVICE);
6042 }
6043 }
6044 return 0;
6045 }
6046 static void set_rxd_buffer_size(nic_t *sp, RxD_t *rxdp, int size)
6047 {
6048 struct net_device *dev = sp->dev;
6049 if (sp->rxd_mode == RXD_MODE_1) {
6050 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6051 } else if (sp->rxd_mode == RXD_MODE_3B) {
6052 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6053 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6054 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6055 } else {
6056 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6057 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6058 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6059 }
6060 }
6061
6062 static int rxd_owner_bit_reset(nic_t *sp)
6063 {
6064 int i, j, k, blk_cnt = 0, size;
6065 mac_info_t * mac_control = &sp->mac_control;
6066 struct config_param *config = &sp->config;
6067 struct net_device *dev = sp->dev;
6068 RxD_t *rxdp = NULL;
6069 struct sk_buff *skb = NULL;
6070 buffAdd_t *ba = NULL;
6071 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6072
6073 /* Calculate the size based on ring mode */
6074 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6075 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6076 if (sp->rxd_mode == RXD_MODE_1)
6077 size += NET_IP_ALIGN;
6078 else if (sp->rxd_mode == RXD_MODE_3B)
6079 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6080 else
6081 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6082
6083 for (i = 0; i < config->rx_ring_num; i++) {
6084 blk_cnt = config->rx_cfg[i].num_rxd /
6085 (rxd_count[sp->rxd_mode] +1);
6086
6087 for (j = 0; j < blk_cnt; j++) {
6088 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6089 rxdp = mac_control->rings[i].
6090 rx_blocks[j].rxds[k].virt_addr;
6091 if(sp->rxd_mode >= RXD_MODE_3A)
6092 ba = &mac_control->rings[i].ba[j][k];
6093 set_rxd_buffer_pointer(sp, rxdp, ba,
6094 &skb,(u64 *)&temp0_64,
6095 (u64 *)&temp1_64,
6096 (u64 *)&temp2_64, size);
6097
6098 set_rxd_buffer_size(sp, rxdp, size);
6099 wmb();
6100 /* flip the Ownership bit to Hardware */
6101 rxdp->Control_1 |= RXD_OWN_XENA;
6102 }
6103 }
6104 }
6105 return 0;
6106
6107 }
6108
6109 static int s2io_add_isr(nic_t * sp)
6110 {
6111 int ret = 0;
6112 struct net_device *dev = sp->dev;
6113 int err = 0;
6114
6115 if (sp->intr_type == MSI)
6116 ret = s2io_enable_msi(sp);
6117 else if (sp->intr_type == MSI_X)
6118 ret = s2io_enable_msi_x(sp);
6119 if (ret) {
6120 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6121 sp->intr_type = INTA;
6122 }
6123
6124 /* Store the values of the MSIX table in the nic_t structure */
6125 store_xmsi_data(sp);
6126
6127 /* After proper initialization of H/W, register ISR */
6128 if (sp->intr_type == MSI) {
6129 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6130 IRQF_SHARED, sp->name, dev);
6131 if (err) {
6132 pci_disable_msi(sp->pdev);
6133 DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6134 dev->name);
6135 return -1;
6136 }
6137 }
6138 if (sp->intr_type == MSI_X) {
6139 int i;
6140
6141 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6142 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6143 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6144 dev->name, i);
6145 err = request_irq(sp->entries[i].vector,
6146 s2io_msix_fifo_handle, 0, sp->desc[i],
6147 sp->s2io_entries[i].arg);
6148 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6149 (unsigned long long)sp->msix_info[i].addr);
6150 } else {
6151 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6152 dev->name, i);
6153 err = request_irq(sp->entries[i].vector,
6154 s2io_msix_ring_handle, 0, sp->desc[i],
6155 sp->s2io_entries[i].arg);
6156 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6157 (unsigned long long)sp->msix_info[i].addr);
6158 }
6159 if (err) {
6160 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6161 "failed\n", dev->name, i);
6162 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6163 return -1;
6164 }
6165 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6166 }
6167 }
6168 if (sp->intr_type == INTA) {
6169 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6170 sp->name, dev);
6171 if (err) {
6172 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6173 dev->name);
6174 return -1;
6175 }
6176 }
6177 return 0;
6178 }
6179 static void s2io_rem_isr(nic_t * sp)
6180 {
6181 int cnt = 0;
6182 struct net_device *dev = sp->dev;
6183
6184 if (sp->intr_type == MSI_X) {
6185 int i;
6186 u16 msi_control;
6187
6188 for (i=1; (sp->s2io_entries[i].in_use ==
6189 MSIX_REGISTERED_SUCCESS); i++) {
6190 int vector = sp->entries[i].vector;
6191 void *arg = sp->s2io_entries[i].arg;
6192
6193 free_irq(vector, arg);
6194 }
6195 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6196 msi_control &= 0xFFFE; /* Disable MSI */
6197 pci_write_config_word(sp->pdev, 0x42, msi_control);
6198
6199 pci_disable_msix(sp->pdev);
6200 } else {
6201 free_irq(sp->pdev->irq, dev);
6202 if (sp->intr_type == MSI) {
6203 u16 val;
6204
6205 pci_disable_msi(sp->pdev);
6206 pci_read_config_word(sp->pdev, 0x4c, &val);
6207 val ^= 0x1;
6208 pci_write_config_word(sp->pdev, 0x4c, val);
6209 }
6210 }
6211 /* Waiting till all Interrupt handlers are complete */
6212 cnt = 0;
6213 do {
6214 msleep(10);
6215 if (!atomic_read(&sp->isr_cnt))
6216 break;
6217 cnt++;
6218 } while(cnt < 5);
6219 }
6220
6221 static void s2io_card_down(nic_t * sp)
6222 {
6223 int cnt = 0;
6224 XENA_dev_config_t __iomem *bar0 = sp->bar0;
6225 unsigned long flags;
6226 register u64 val64 = 0;
6227
6228 del_timer_sync(&sp->alarm_timer);
6229 /* If s2io_set_link task is executing, wait till it completes. */
6230 while (test_and_set_bit(0, &(sp->link_state))) {
6231 msleep(50);
6232 }
6233 atomic_set(&sp->card_state, CARD_DOWN);
6234
6235 /* disable Tx and Rx traffic on the NIC */
6236 stop_nic(sp);
6237
6238 s2io_rem_isr(sp);
6239
6240 /* Kill tasklet. */
6241 tasklet_kill(&sp->task);
6242
6243 /* Check if the device is Quiescent and then Reset the NIC */
6244 do {
6245 /* As per the HW requirement we need to replenish the
6246 * receive buffer to avoid the ring bump. Since there is
6247 * no intention of processing the Rx frame at this pointwe are
6248 * just settting the ownership bit of rxd in Each Rx
6249 * ring to HW and set the appropriate buffer size
6250 * based on the ring mode
6251 */
6252 rxd_owner_bit_reset(sp);
6253
6254 val64 = readq(&bar0->adapter_status);
6255 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
6256 break;
6257 }
6258
6259 msleep(50);
6260 cnt++;
6261 if (cnt == 10) {
6262 DBG_PRINT(ERR_DBG,
6263 "s2io_close:Device not Quiescent ");
6264 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6265 (unsigned long long) val64);
6266 break;
6267 }
6268 } while (1);
6269 s2io_reset(sp);
6270
6271 spin_lock_irqsave(&sp->tx_lock, flags);
6272 /* Free all Tx buffers */
6273 free_tx_buffers(sp);
6274 spin_unlock_irqrestore(&sp->tx_lock, flags);
6275
6276 /* Free all Rx buffers */
6277 spin_lock_irqsave(&sp->rx_lock, flags);
6278 free_rx_buffers(sp);
6279 spin_unlock_irqrestore(&sp->rx_lock, flags);
6280
6281 clear_bit(0, &(sp->link_state));
6282 }
6283
6284 static int s2io_card_up(nic_t * sp)
6285 {
6286 int i, ret = 0;
6287 mac_info_t *mac_control;
6288 struct config_param *config;
6289 struct net_device *dev = (struct net_device *) sp->dev;
6290 u16 interruptible;
6291
6292 /* Initialize the H/W I/O registers */
6293 if (init_nic(sp) != 0) {
6294 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6295 dev->name);
6296 s2io_reset(sp);
6297 return -ENODEV;
6298 }
6299
6300 /*
6301 * Initializing the Rx buffers. For now we are considering only 1
6302 * Rx ring and initializing buffers into 30 Rx blocks
6303 */
6304 mac_control = &sp->mac_control;
6305 config = &sp->config;
6306
6307 for (i = 0; i < config->rx_ring_num; i++) {
6308 if ((ret = fill_rx_buffers(sp, i))) {
6309 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6310 dev->name);
6311 s2io_reset(sp);
6312 free_rx_buffers(sp);
6313 return -ENOMEM;
6314 }
6315 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6316 atomic_read(&sp->rx_bufs_left[i]));
6317 }
6318
6319 /* Setting its receive mode */
6320 s2io_set_multicast(dev);
6321
6322 if (sp->lro) {
6323 /* Initialize max aggregatable pkts per session based on MTU */
6324 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6325 /* Check if we can use(if specified) user provided value */
6326 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6327 sp->lro_max_aggr_per_sess = lro_max_pkts;
6328 }
6329
6330 /* Enable Rx Traffic and interrupts on the NIC */
6331 if (start_nic(sp)) {
6332 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6333 s2io_reset(sp);
6334 free_rx_buffers(sp);
6335 return -ENODEV;
6336 }
6337
6338 /* Add interrupt service routine */
6339 if (s2io_add_isr(sp) != 0) {
6340 if (sp->intr_type == MSI_X)
6341 s2io_rem_isr(sp);
6342 s2io_reset(sp);
6343 free_rx_buffers(sp);
6344 return -ENODEV;
6345 }
6346
6347 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6348
6349 /* Enable tasklet for the device */
6350 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6351
6352 /* Enable select interrupts */
6353 if (sp->intr_type != INTA)
6354 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6355 else {
6356 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6357 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6358 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6359 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6360 }
6361
6362
6363 atomic_set(&sp->card_state, CARD_UP);
6364 return 0;
6365 }
6366
6367 /**
6368 * s2io_restart_nic - Resets the NIC.
6369 * @data : long pointer to the device private structure
6370 * Description:
6371 * This function is scheduled to be run by the s2io_tx_watchdog
6372 * function after 0.5 secs to reset the NIC. The idea is to reduce
6373 * the run time of the watch dog routine which is run holding a
6374 * spin lock.
6375 */
6376
6377 static void s2io_restart_nic(unsigned long data)
6378 {
6379 struct net_device *dev = (struct net_device *) data;
6380 nic_t *sp = dev->priv;
6381
6382 s2io_card_down(sp);
6383 if (s2io_card_up(sp)) {
6384 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6385 dev->name);
6386 }
6387 netif_wake_queue(dev);
6388 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6389 dev->name);
6390
6391 }
6392
6393 /**
6394 * s2io_tx_watchdog - Watchdog for transmit side.
6395 * @dev : Pointer to net device structure
6396 * Description:
6397 * This function is triggered if the Tx Queue is stopped
6398 * for a pre-defined amount of time when the Interface is still up.
6399 * If the Interface is jammed in such a situation, the hardware is
6400 * reset (by s2io_close) and restarted again (by s2io_open) to
6401 * overcome any problem that might have been caused in the hardware.
6402 * Return value:
6403 * void
6404 */
6405
6406 static void s2io_tx_watchdog(struct net_device *dev)
6407 {
6408 nic_t *sp = dev->priv;
6409
6410 if (netif_carrier_ok(dev)) {
6411 schedule_work(&sp->rst_timer_task);
6412 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
6413 }
6414 }
6415
6416 /**
6417 * rx_osm_handler - To perform some OS related operations on SKB.
6418 * @sp: private member of the device structure,pointer to s2io_nic structure.
6419 * @skb : the socket buffer pointer.
6420 * @len : length of the packet
6421 * @cksum : FCS checksum of the frame.
6422 * @ring_no : the ring from which this RxD was extracted.
6423 * Description:
6424 * This function is called by the Rx interrupt serivce routine to perform
6425 * some OS related operations on the SKB before passing it to the upper
6426 * layers. It mainly checks if the checksum is OK, if so adds it to the
6427 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6428 * to the upper layer. If the checksum is wrong, it increments the Rx
6429 * packet error count, frees the SKB and returns error.
6430 * Return value:
6431 * SUCCESS on success and -1 on failure.
6432 */
6433 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
6434 {
6435 nic_t *sp = ring_data->nic;
6436 struct net_device *dev = (struct net_device *) sp->dev;
6437 struct sk_buff *skb = (struct sk_buff *)
6438 ((unsigned long) rxdp->Host_Control);
6439 int ring_no = ring_data->ring_no;
6440 u16 l3_csum, l4_csum;
6441 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
6442 lro_t *lro;
6443
6444 skb->dev = dev;
6445
6446 if (err) {
6447 /* Check for parity error */
6448 if (err & 0x1) {
6449 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6450 }
6451
6452 /*
6453 * Drop the packet if bad transfer code. Exception being
6454 * 0x5, which could be due to unsupported IPv6 extension header.
6455 * In this case, we let stack handle the packet.
6456 * Note that in this case, since checksum will be incorrect,
6457 * stack will validate the same.
6458 */
6459 if (err && ((err >> 48) != 0x5)) {
6460 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6461 dev->name, err);
6462 sp->stats.rx_crc_errors++;
6463 dev_kfree_skb(skb);
6464 atomic_dec(&sp->rx_bufs_left[ring_no]);
6465 rxdp->Host_Control = 0;
6466 return 0;
6467 }
6468 }
6469
6470 /* Updating statistics */
6471 rxdp->Host_Control = 0;
6472 sp->rx_pkt_count++;
6473 sp->stats.rx_packets++;
6474 if (sp->rxd_mode == RXD_MODE_1) {
6475 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
6476
6477 sp->stats.rx_bytes += len;
6478 skb_put(skb, len);
6479
6480 } else if (sp->rxd_mode >= RXD_MODE_3A) {
6481 int get_block = ring_data->rx_curr_get_info.block_index;
6482 int get_off = ring_data->rx_curr_get_info.offset;
6483 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6484 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6485 unsigned char *buff = skb_push(skb, buf0_len);
6486
6487 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
6488 sp->stats.rx_bytes += buf0_len + buf2_len;
6489 memcpy(buff, ba->ba_0, buf0_len);
6490
6491 if (sp->rxd_mode == RXD_MODE_3A) {
6492 int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6493
6494 skb_put(skb, buf1_len);
6495 skb->len += buf2_len;
6496 skb->data_len += buf2_len;
6497 skb->truesize += buf2_len;
6498 skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6499 sp->stats.rx_bytes += buf1_len;
6500
6501 } else
6502 skb_put(skb, buf2_len);
6503 }
6504
6505 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6506 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
6507 (sp->rx_csum)) {
6508 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
6509 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6510 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
6511 /*
6512 * NIC verifies if the Checksum of the received
6513 * frame is Ok or not and accordingly returns
6514 * a flag in the RxD.
6515 */
6516 skb->ip_summed = CHECKSUM_UNNECESSARY;
6517 if (sp->lro) {
6518 u32 tcp_len;
6519 u8 *tcp;
6520 int ret = 0;
6521
6522 ret = s2io_club_tcp_session(skb->data, &tcp,
6523 &tcp_len, &lro, rxdp, sp);
6524 switch (ret) {
6525 case 3: /* Begin anew */
6526 lro->parent = skb;
6527 goto aggregate;
6528 case 1: /* Aggregate */
6529 {
6530 lro_append_pkt(sp, lro,
6531 skb, tcp_len);
6532 goto aggregate;
6533 }
6534 case 4: /* Flush session */
6535 {
6536 lro_append_pkt(sp, lro,
6537 skb, tcp_len);
6538 queue_rx_frame(lro->parent);
6539 clear_lro_session(lro);
6540 sp->mac_control.stats_info->
6541 sw_stat.flush_max_pkts++;
6542 goto aggregate;
6543 }
6544 case 2: /* Flush both */
6545 lro->parent->data_len =
6546 lro->frags_len;
6547 sp->mac_control.stats_info->
6548 sw_stat.sending_both++;
6549 queue_rx_frame(lro->parent);
6550 clear_lro_session(lro);
6551 goto send_up;
6552 case 0: /* sessions exceeded */
6553 case -1: /* non-TCP or not
6554 * L2 aggregatable
6555 */
6556 case 5: /*
6557 * First pkt in session not
6558 * L3/L4 aggregatable
6559 */
6560 break;
6561 default:
6562 DBG_PRINT(ERR_DBG,
6563 "%s: Samadhana!!\n",
6564 __FUNCTION__);
6565 BUG();
6566 }
6567 }
6568 } else {
6569 /*
6570 * Packet with erroneous checksum, let the
6571 * upper layers deal with it.
6572 */
6573 skb->ip_summed = CHECKSUM_NONE;
6574 }
6575 } else {
6576 skb->ip_summed = CHECKSUM_NONE;
6577 }
6578
6579 if (!sp->lro) {
6580 skb->protocol = eth_type_trans(skb, dev);
6581 #ifdef CONFIG_S2IO_NAPI
6582 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6583 /* Queueing the vlan frame to the upper layer */
6584 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6585 RXD_GET_VLAN_TAG(rxdp->Control_2));
6586 } else {
6587 netif_receive_skb(skb);
6588 }
6589 #else
6590 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6591 /* Queueing the vlan frame to the upper layer */
6592 vlan_hwaccel_rx(skb, sp->vlgrp,
6593 RXD_GET_VLAN_TAG(rxdp->Control_2));
6594 } else {
6595 netif_rx(skb);
6596 }
6597 #endif
6598 } else {
6599 send_up:
6600 queue_rx_frame(skb);
6601 }
6602 dev->last_rx = jiffies;
6603 aggregate:
6604 atomic_dec(&sp->rx_bufs_left[ring_no]);
6605 return SUCCESS;
6606 }
6607
6608 /**
6609 * s2io_link - stops/starts the Tx queue.
6610 * @sp : private member of the device structure, which is a pointer to the
6611 * s2io_nic structure.
6612 * @link : inidicates whether link is UP/DOWN.
6613 * Description:
6614 * This function stops/starts the Tx queue depending on whether the link
6615 * status of the NIC is is down or up. This is called by the Alarm
6616 * interrupt handler whenever a link change interrupt comes up.
6617 * Return value:
6618 * void.
6619 */
6620
6621 static void s2io_link(nic_t * sp, int link)
6622 {
6623 struct net_device *dev = (struct net_device *) sp->dev;
6624
6625 if (link != sp->last_link_state) {
6626 if (link == LINK_DOWN) {
6627 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6628 netif_carrier_off(dev);
6629 } else {
6630 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
6631 netif_carrier_on(dev);
6632 }
6633 }
6634 sp->last_link_state = link;
6635 }
6636
6637 /**
6638 * get_xena_rev_id - to identify revision ID of xena.
6639 * @pdev : PCI Dev structure
6640 * Description:
6641 * Function to identify the Revision ID of xena.
6642 * Return value:
6643 * returns the revision ID of the device.
6644 */
6645
6646 static int get_xena_rev_id(struct pci_dev *pdev)
6647 {
6648 u8 id = 0;
6649 int ret;
6650 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
6651 return id;
6652 }
6653
6654 /**
6655 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6656 * @sp : private member of the device structure, which is a pointer to the
6657 * s2io_nic structure.
6658 * Description:
6659 * This function initializes a few of the PCI and PCI-X configuration registers
6660 * with recommended values.
6661 * Return value:
6662 * void
6663 */
6664
6665 static void s2io_init_pci(nic_t * sp)
6666 {
6667 u16 pci_cmd = 0, pcix_cmd = 0;
6668
6669 /* Enable Data Parity Error Recovery in PCI-X command register. */
6670 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6671 &(pcix_cmd));
6672 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6673 (pcix_cmd | 1));
6674 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6675 &(pcix_cmd));
6676
6677 /* Set the PErr Response bit in PCI command register. */
6678 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6679 pci_write_config_word(sp->pdev, PCI_COMMAND,
6680 (pci_cmd | PCI_COMMAND_PARITY));
6681 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6682 }
6683
6684 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6685 {
6686 if ( tx_fifo_num > 8) {
6687 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6688 "supported\n");
6689 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6690 tx_fifo_num = 8;
6691 }
6692 if ( rx_ring_num > 8) {
6693 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6694 "supported\n");
6695 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6696 rx_ring_num = 8;
6697 }
6698 #ifdef CONFIG_S2IO_NAPI
6699 if (*dev_intr_type != INTA) {
6700 DBG_PRINT(ERR_DBG, "s2io: NAPI cannot be enabled when "
6701 "MSI/MSI-X is enabled. Defaulting to INTA\n");
6702 *dev_intr_type = INTA;
6703 }
6704 #endif
6705 #ifndef CONFIG_PCI_MSI
6706 if (*dev_intr_type != INTA) {
6707 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6708 "MSI/MSI-X. Defaulting to INTA\n");
6709 *dev_intr_type = INTA;
6710 }
6711 #else
6712 if (*dev_intr_type > MSI_X) {
6713 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6714 "Defaulting to INTA\n");
6715 *dev_intr_type = INTA;
6716 }
6717 #endif
6718 if ((*dev_intr_type == MSI_X) &&
6719 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6720 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6721 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
6722 "Defaulting to INTA\n");
6723 *dev_intr_type = INTA;
6724 }
6725 if (rx_ring_mode > 3) {
6726 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6727 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
6728 rx_ring_mode = 3;
6729 }
6730 return SUCCESS;
6731 }
6732
6733 /**
6734 * s2io_init_nic - Initialization of the adapter .
6735 * @pdev : structure containing the PCI related information of the device.
6736 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6737 * Description:
6738 * The function initializes an adapter identified by the pci_dec structure.
6739 * All OS related initialization including memory and device structure and
6740 * initlaization of the device private variable is done. Also the swapper
6741 * control register is initialized to enable read and write into the I/O
6742 * registers of the device.
6743 * Return value:
6744 * returns 0 on success and negative on failure.
6745 */
6746
6747 static int __devinit
6748 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6749 {
6750 nic_t *sp;
6751 struct net_device *dev;
6752 int i, j, ret;
6753 int dma_flag = FALSE;
6754 u32 mac_up, mac_down;
6755 u64 val64 = 0, tmp64 = 0;
6756 XENA_dev_config_t __iomem *bar0 = NULL;
6757 u16 subid;
6758 mac_info_t *mac_control;
6759 struct config_param *config;
6760 int mode;
6761 u8 dev_intr_type = intr_type;
6762
6763 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6764 return ret;
6765
6766 if ((ret = pci_enable_device(pdev))) {
6767 DBG_PRINT(ERR_DBG,
6768 "s2io_init_nic: pci_enable_device failed\n");
6769 return ret;
6770 }
6771
6772 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
6773 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6774 dma_flag = TRUE;
6775 if (pci_set_consistent_dma_mask
6776 (pdev, DMA_64BIT_MASK)) {
6777 DBG_PRINT(ERR_DBG,
6778 "Unable to obtain 64bit DMA for \
6779 consistent allocations\n");
6780 pci_disable_device(pdev);
6781 return -ENOMEM;
6782 }
6783 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
6784 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6785 } else {
6786 pci_disable_device(pdev);
6787 return -ENOMEM;
6788 }
6789 if (dev_intr_type != MSI_X) {
6790 if (pci_request_regions(pdev, s2io_driver_name)) {
6791 DBG_PRINT(ERR_DBG, "Request Regions failed\n");
6792 pci_disable_device(pdev);
6793 return -ENODEV;
6794 }
6795 }
6796 else {
6797 if (!(request_mem_region(pci_resource_start(pdev, 0),
6798 pci_resource_len(pdev, 0), s2io_driver_name))) {
6799 DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6800 pci_disable_device(pdev);
6801 return -ENODEV;
6802 }
6803 if (!(request_mem_region(pci_resource_start(pdev, 2),
6804 pci_resource_len(pdev, 2), s2io_driver_name))) {
6805 DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6806 release_mem_region(pci_resource_start(pdev, 0),
6807 pci_resource_len(pdev, 0));
6808 pci_disable_device(pdev);
6809 return -ENODEV;
6810 }
6811 }
6812
6813 dev = alloc_etherdev(sizeof(nic_t));
6814 if (dev == NULL) {
6815 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6816 pci_disable_device(pdev);
6817 pci_release_regions(pdev);
6818 return -ENODEV;
6819 }
6820
6821 pci_set_master(pdev);
6822 pci_set_drvdata(pdev, dev);
6823 SET_MODULE_OWNER(dev);
6824 SET_NETDEV_DEV(dev, &pdev->dev);
6825
6826 /* Private member variable initialized to s2io NIC structure */
6827 sp = dev->priv;
6828 memset(sp, 0, sizeof(nic_t));
6829 sp->dev = dev;
6830 sp->pdev = pdev;
6831 sp->high_dma_flag = dma_flag;
6832 sp->device_enabled_once = FALSE;
6833 if (rx_ring_mode == 1)
6834 sp->rxd_mode = RXD_MODE_1;
6835 if (rx_ring_mode == 2)
6836 sp->rxd_mode = RXD_MODE_3B;
6837 if (rx_ring_mode == 3)
6838 sp->rxd_mode = RXD_MODE_3A;
6839
6840 sp->intr_type = dev_intr_type;
6841
6842 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6843 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6844 sp->device_type = XFRAME_II_DEVICE;
6845 else
6846 sp->device_type = XFRAME_I_DEVICE;
6847
6848 sp->lro = lro;
6849
6850 /* Initialize some PCI/PCI-X fields of the NIC. */
6851 s2io_init_pci(sp);
6852
6853 /*
6854 * Setting the device configuration parameters.
6855 * Most of these parameters can be specified by the user during
6856 * module insertion as they are module loadable parameters. If
6857 * these parameters are not not specified during load time, they
6858 * are initialized with default values.
6859 */
6860 mac_control = &sp->mac_control;
6861 config = &sp->config;
6862
6863 /* Tx side parameters. */
6864 config->tx_fifo_num = tx_fifo_num;
6865 for (i = 0; i < MAX_TX_FIFOS; i++) {
6866 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
6867 config->tx_cfg[i].fifo_priority = i;
6868 }
6869
6870 /* mapping the QoS priority to the configured fifos */
6871 for (i = 0; i < MAX_TX_FIFOS; i++)
6872 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
6873
6874 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
6875 for (i = 0; i < config->tx_fifo_num; i++) {
6876 config->tx_cfg[i].f_no_snoop =
6877 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
6878 if (config->tx_cfg[i].fifo_len < 65) {
6879 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
6880 break;
6881 }
6882 }
6883 /* + 2 because one Txd for skb->data and one Txd for UFO */
6884 config->max_txds = MAX_SKB_FRAGS + 2;
6885
6886 /* Rx side parameters. */
6887 config->rx_ring_num = rx_ring_num;
6888 for (i = 0; i < MAX_RX_RINGS; i++) {
6889 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
6890 (rxd_count[sp->rxd_mode] + 1);
6891 config->rx_cfg[i].ring_priority = i;
6892 }
6893
6894 for (i = 0; i < rx_ring_num; i++) {
6895 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
6896 config->rx_cfg[i].f_no_snoop =
6897 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
6898 }
6899
6900 /* Setting Mac Control parameters */
6901 mac_control->rmac_pause_time = rmac_pause_time;
6902 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6903 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6904
6905
6906 /* Initialize Ring buffer parameters. */
6907 for (i = 0; i < config->rx_ring_num; i++)
6908 atomic_set(&sp->rx_bufs_left[i], 0);
6909
6910 /* Initialize the number of ISRs currently running */
6911 atomic_set(&sp->isr_cnt, 0);
6912
6913 /* initialize the shared memory used by the NIC and the host */
6914 if (init_shared_mem(sp)) {
6915 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
6916 dev->name);
6917 ret = -ENOMEM;
6918 goto mem_alloc_failed;
6919 }
6920
6921 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6922 pci_resource_len(pdev, 0));
6923 if (!sp->bar0) {
6924 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
6925 dev->name);
6926 ret = -ENOMEM;
6927 goto bar0_remap_failed;
6928 }
6929
6930 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6931 pci_resource_len(pdev, 2));
6932 if (!sp->bar1) {
6933 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
6934 dev->name);
6935 ret = -ENOMEM;
6936 goto bar1_remap_failed;
6937 }
6938
6939 dev->irq = pdev->irq;
6940 dev->base_addr = (unsigned long) sp->bar0;
6941
6942 /* Initializing the BAR1 address as the start of the FIFO pointer. */
6943 for (j = 0; j < MAX_TX_FIFOS; j++) {
6944 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6945 (sp->bar1 + (j * 0x00020000));
6946 }
6947
6948 /* Driver entry points */
6949 dev->open = &s2io_open;
6950 dev->stop = &s2io_close;
6951 dev->hard_start_xmit = &s2io_xmit;
6952 dev->get_stats = &s2io_get_stats;
6953 dev->set_multicast_list = &s2io_set_multicast;
6954 dev->do_ioctl = &s2io_ioctl;
6955 dev->change_mtu = &s2io_change_mtu;
6956 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
6957 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6958 dev->vlan_rx_register = s2io_vlan_rx_register;
6959 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
6960
6961 /*
6962 * will use eth_mac_addr() for dev->set_mac_address
6963 * mac address will be set every time dev->open() is called
6964 */
6965 #if defined(CONFIG_S2IO_NAPI)
6966 dev->poll = s2io_poll;
6967 dev->weight = 32;
6968 #endif
6969
6970 #ifdef CONFIG_NET_POLL_CONTROLLER
6971 dev->poll_controller = s2io_netpoll;
6972 #endif
6973
6974 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6975 if (sp->high_dma_flag == TRUE)
6976 dev->features |= NETIF_F_HIGHDMA;
6977 #ifdef NETIF_F_TSO
6978 dev->features |= NETIF_F_TSO;
6979 #endif
6980 #ifdef NETIF_F_TSO6
6981 dev->features |= NETIF_F_TSO6;
6982 #endif
6983 if (sp->device_type & XFRAME_II_DEVICE) {
6984 dev->features |= NETIF_F_UFO;
6985 dev->features |= NETIF_F_HW_CSUM;
6986 }
6987
6988 dev->tx_timeout = &s2io_tx_watchdog;
6989 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
6990 INIT_WORK(&sp->rst_timer_task,
6991 (void (*)(void *)) s2io_restart_nic, dev);
6992 INIT_WORK(&sp->set_link_task,
6993 (void (*)(void *)) s2io_set_link, sp);
6994
6995 pci_save_state(sp->pdev);
6996
6997 /* Setting swapper control on the NIC, for proper reset operation */
6998 if (s2io_set_swapper(sp)) {
6999 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7000 dev->name);
7001 ret = -EAGAIN;
7002 goto set_swap_failed;
7003 }
7004
7005 /* Verify if the Herc works on the slot its placed into */
7006 if (sp->device_type & XFRAME_II_DEVICE) {
7007 mode = s2io_verify_pci_mode(sp);
7008 if (mode < 0) {
7009 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7010 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7011 ret = -EBADSLT;
7012 goto set_swap_failed;
7013 }
7014 }
7015
7016 /* Not needed for Herc */
7017 if (sp->device_type & XFRAME_I_DEVICE) {
7018 /*
7019 * Fix for all "FFs" MAC address problems observed on
7020 * Alpha platforms
7021 */
7022 fix_mac_address(sp);
7023 s2io_reset(sp);
7024 }
7025
7026 /*
7027 * MAC address initialization.
7028 * For now only one mac address will be read and used.
7029 */
7030 bar0 = sp->bar0;
7031 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7032 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7033 writeq(val64, &bar0->rmac_addr_cmd_mem);
7034 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7035 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
7036 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7037 mac_down = (u32) tmp64;
7038 mac_up = (u32) (tmp64 >> 32);
7039
7040 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
7041
7042 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7043 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7044 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7045 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7046 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7047 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7048
7049 /* Set the factory defined MAC address initially */
7050 dev->addr_len = ETH_ALEN;
7051 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7052
7053 /* reset Nic and bring it to known state */
7054 s2io_reset(sp);
7055
7056 /*
7057 * Initialize the tasklet status and link state flags
7058 * and the card state parameter
7059 */
7060 atomic_set(&(sp->card_state), 0);
7061 sp->tasklet_status = 0;
7062 sp->link_state = 0;
7063
7064 /* Initialize spinlocks */
7065 spin_lock_init(&sp->tx_lock);
7066 #ifndef CONFIG_S2IO_NAPI
7067 spin_lock_init(&sp->put_lock);
7068 #endif
7069 spin_lock_init(&sp->rx_lock);
7070
7071 /*
7072 * SXE-002: Configure link and activity LED to init state
7073 * on driver load.
7074 */
7075 subid = sp->pdev->subsystem_device;
7076 if ((subid & 0xFF) >= 0x07) {
7077 val64 = readq(&bar0->gpio_control);
7078 val64 |= 0x0000800000000000ULL;
7079 writeq(val64, &bar0->gpio_control);
7080 val64 = 0x0411040400000000ULL;
7081 writeq(val64, (void __iomem *) bar0 + 0x2700);
7082 val64 = readq(&bar0->gpio_control);
7083 }
7084
7085 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7086
7087 if (register_netdev(dev)) {
7088 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7089 ret = -ENODEV;
7090 goto register_failed;
7091 }
7092 s2io_vpd_read(sp);
7093 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
7094 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7095 sp->product_name, get_xena_rev_id(sp->pdev));
7096 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7097 s2io_driver_version);
7098 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7099 "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
7100 sp->def_mac_addr[0].mac_addr[0],
7101 sp->def_mac_addr[0].mac_addr[1],
7102 sp->def_mac_addr[0].mac_addr[2],
7103 sp->def_mac_addr[0].mac_addr[3],
7104 sp->def_mac_addr[0].mac_addr[4],
7105 sp->def_mac_addr[0].mac_addr[5]);
7106 if (sp->device_type & XFRAME_II_DEVICE) {
7107 mode = s2io_print_pci_mode(sp);
7108 if (mode < 0) {
7109 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7110 ret = -EBADSLT;
7111 unregister_netdev(dev);
7112 goto set_swap_failed;
7113 }
7114 }
7115 switch(sp->rxd_mode) {
7116 case RXD_MODE_1:
7117 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7118 dev->name);
7119 break;
7120 case RXD_MODE_3B:
7121 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7122 dev->name);
7123 break;
7124 case RXD_MODE_3A:
7125 DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7126 dev->name);
7127 break;
7128 }
7129 #ifdef CONFIG_S2IO_NAPI
7130 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7131 #endif
7132 switch(sp->intr_type) {
7133 case INTA:
7134 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7135 break;
7136 case MSI:
7137 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7138 break;
7139 case MSI_X:
7140 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7141 break;
7142 }
7143 if (sp->lro)
7144 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7145 dev->name);
7146
7147 /* Initialize device name */
7148 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7149
7150 /* Initialize bimodal Interrupts */
7151 sp->config.bimodal = bimodal;
7152 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7153 sp->config.bimodal = 0;
7154 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7155 dev->name);
7156 }
7157
7158 /*
7159 * Make Link state as off at this point, when the Link change
7160 * interrupt comes the state will be automatically changed to
7161 * the right state.
7162 */
7163 netif_carrier_off(dev);
7164
7165 return 0;
7166
7167 register_failed:
7168 set_swap_failed:
7169 iounmap(sp->bar1);
7170 bar1_remap_failed:
7171 iounmap(sp->bar0);
7172 bar0_remap_failed:
7173 mem_alloc_failed:
7174 free_shared_mem(sp);
7175 pci_disable_device(pdev);
7176 if (dev_intr_type != MSI_X)
7177 pci_release_regions(pdev);
7178 else {
7179 release_mem_region(pci_resource_start(pdev, 0),
7180 pci_resource_len(pdev, 0));
7181 release_mem_region(pci_resource_start(pdev, 2),
7182 pci_resource_len(pdev, 2));
7183 }
7184 pci_set_drvdata(pdev, NULL);
7185 free_netdev(dev);
7186
7187 return ret;
7188 }
7189
7190 /**
7191 * s2io_rem_nic - Free the PCI device
7192 * @pdev: structure containing the PCI related information of the device.
7193 * Description: This function is called by the Pci subsystem to release a
7194 * PCI device and free up all resource held up by the device. This could
7195 * be in response to a Hot plug event or when the driver is to be removed
7196 * from memory.
7197 */
7198
7199 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7200 {
7201 struct net_device *dev =
7202 (struct net_device *) pci_get_drvdata(pdev);
7203 nic_t *sp;
7204
7205 if (dev == NULL) {
7206 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7207 return;
7208 }
7209
7210 sp = dev->priv;
7211 unregister_netdev(dev);
7212
7213 free_shared_mem(sp);
7214 iounmap(sp->bar0);
7215 iounmap(sp->bar1);
7216 pci_disable_device(pdev);
7217 if (sp->intr_type != MSI_X)
7218 pci_release_regions(pdev);
7219 else {
7220 release_mem_region(pci_resource_start(pdev, 0),
7221 pci_resource_len(pdev, 0));
7222 release_mem_region(pci_resource_start(pdev, 2),
7223 pci_resource_len(pdev, 2));
7224 }
7225 pci_set_drvdata(pdev, NULL);
7226 free_netdev(dev);
7227 }
7228
7229 /**
7230 * s2io_starter - Entry point for the driver
7231 * Description: This function is the entry point for the driver. It verifies
7232 * the module loadable parameters and initializes PCI configuration space.
7233 */
7234
7235 int __init s2io_starter(void)
7236 {
7237 return pci_register_driver(&s2io_driver);
7238 }
7239
7240 /**
7241 * s2io_closer - Cleanup routine for the driver
7242 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7243 */
7244
7245 static void s2io_closer(void)
7246 {
7247 pci_unregister_driver(&s2io_driver);
7248 DBG_PRINT(INIT_DBG, "cleanup done\n");
7249 }
7250
7251 module_init(s2io_starter);
7252 module_exit(s2io_closer);
7253
7254 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7255 struct tcphdr **tcp, RxD_t *rxdp)
7256 {
7257 int ip_off;
7258 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7259
7260 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7261 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7262 __FUNCTION__);
7263 return -1;
7264 }
7265
7266 /* TODO:
7267 * By default the VLAN field in the MAC is stripped by the card, if this
7268 * feature is turned off in rx_pa_cfg register, then the ip_off field
7269 * has to be shifted by a further 2 bytes
7270 */
7271 switch (l2_type) {
7272 case 0: /* DIX type */
7273 case 4: /* DIX type with VLAN */
7274 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7275 break;
7276 /* LLC, SNAP etc are considered non-mergeable */
7277 default:
7278 return -1;
7279 }
7280
7281 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7282 ip_len = (u8)((*ip)->ihl);
7283 ip_len <<= 2;
7284 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7285
7286 return 0;
7287 }
7288
7289 static int check_for_socket_match(lro_t *lro, struct iphdr *ip,
7290 struct tcphdr *tcp)
7291 {
7292 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7293 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7294 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7295 return -1;
7296 return 0;
7297 }
7298
7299 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7300 {
7301 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7302 }
7303
7304 static void initiate_new_session(lro_t *lro, u8 *l2h,
7305 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7306 {
7307 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7308 lro->l2h = l2h;
7309 lro->iph = ip;
7310 lro->tcph = tcp;
7311 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7312 lro->tcp_ack = ntohl(tcp->ack_seq);
7313 lro->sg_num = 1;
7314 lro->total_len = ntohs(ip->tot_len);
7315 lro->frags_len = 0;
7316 /*
7317 * check if we saw TCP timestamp. Other consistency checks have
7318 * already been done.
7319 */
7320 if (tcp->doff == 8) {
7321 u32 *ptr;
7322 ptr = (u32 *)(tcp+1);
7323 lro->saw_ts = 1;
7324 lro->cur_tsval = *(ptr+1);
7325 lro->cur_tsecr = *(ptr+2);
7326 }
7327 lro->in_use = 1;
7328 }
7329
7330 static void update_L3L4_header(nic_t *sp, lro_t *lro)
7331 {
7332 struct iphdr *ip = lro->iph;
7333 struct tcphdr *tcp = lro->tcph;
7334 u16 nchk;
7335 StatInfo_t *statinfo = sp->mac_control.stats_info;
7336 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7337
7338 /* Update L3 header */
7339 ip->tot_len = htons(lro->total_len);
7340 ip->check = 0;
7341 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7342 ip->check = nchk;
7343
7344 /* Update L4 header */
7345 tcp->ack_seq = lro->tcp_ack;
7346 tcp->window = lro->window;
7347
7348 /* Update tsecr field if this session has timestamps enabled */
7349 if (lro->saw_ts) {
7350 u32 *ptr = (u32 *)(tcp + 1);
7351 *(ptr+2) = lro->cur_tsecr;
7352 }
7353
7354 /* Update counters required for calculation of
7355 * average no. of packets aggregated.
7356 */
7357 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7358 statinfo->sw_stat.num_aggregations++;
7359 }
7360
7361 static void aggregate_new_rx(lro_t *lro, struct iphdr *ip,
7362 struct tcphdr *tcp, u32 l4_pyld)
7363 {
7364 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7365 lro->total_len += l4_pyld;
7366 lro->frags_len += l4_pyld;
7367 lro->tcp_next_seq += l4_pyld;
7368 lro->sg_num++;
7369
7370 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7371 lro->tcp_ack = tcp->ack_seq;
7372 lro->window = tcp->window;
7373
7374 if (lro->saw_ts) {
7375 u32 *ptr;
7376 /* Update tsecr and tsval from this packet */
7377 ptr = (u32 *) (tcp + 1);
7378 lro->cur_tsval = *(ptr + 1);
7379 lro->cur_tsecr = *(ptr + 2);
7380 }
7381 }
7382
7383 static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
7384 struct tcphdr *tcp, u32 tcp_pyld_len)
7385 {
7386 u8 *ptr;
7387
7388 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7389
7390 if (!tcp_pyld_len) {
7391 /* Runt frame or a pure ack */
7392 return -1;
7393 }
7394
7395 if (ip->ihl != 5) /* IP has options */
7396 return -1;
7397
7398 /* If we see CE codepoint in IP header, packet is not mergeable */
7399 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7400 return -1;
7401
7402 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7403 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
7404 tcp->ece || tcp->cwr || !tcp->ack) {
7405 /*
7406 * Currently recognize only the ack control word and
7407 * any other control field being set would result in
7408 * flushing the LRO session
7409 */
7410 return -1;
7411 }
7412
7413 /*
7414 * Allow only one TCP timestamp option. Don't aggregate if
7415 * any other options are detected.
7416 */
7417 if (tcp->doff != 5 && tcp->doff != 8)
7418 return -1;
7419
7420 if (tcp->doff == 8) {
7421 ptr = (u8 *)(tcp + 1);
7422 while (*ptr == TCPOPT_NOP)
7423 ptr++;
7424 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7425 return -1;
7426
7427 /* Ensure timestamp value increases monotonically */
7428 if (l_lro)
7429 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7430 return -1;
7431
7432 /* timestamp echo reply should be non-zero */
7433 if (*((u32 *)(ptr+6)) == 0)
7434 return -1;
7435 }
7436
7437 return 0;
7438 }
7439
7440 static int
7441 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
7442 RxD_t *rxdp, nic_t *sp)
7443 {
7444 struct iphdr *ip;
7445 struct tcphdr *tcph;
7446 int ret = 0, i;
7447
7448 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7449 rxdp))) {
7450 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7451 ip->saddr, ip->daddr);
7452 } else {
7453 return ret;
7454 }
7455
7456 tcph = (struct tcphdr *)*tcp;
7457 *tcp_len = get_l4_pyld_length(ip, tcph);
7458 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7459 lro_t *l_lro = &sp->lro0_n[i];
7460 if (l_lro->in_use) {
7461 if (check_for_socket_match(l_lro, ip, tcph))
7462 continue;
7463 /* Sock pair matched */
7464 *lro = l_lro;
7465
7466 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7467 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7468 "0x%x, actual 0x%x\n", __FUNCTION__,
7469 (*lro)->tcp_next_seq,
7470 ntohl(tcph->seq));
7471
7472 sp->mac_control.stats_info->
7473 sw_stat.outof_sequence_pkts++;
7474 ret = 2;
7475 break;
7476 }
7477
7478 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7479 ret = 1; /* Aggregate */
7480 else
7481 ret = 2; /* Flush both */
7482 break;
7483 }
7484 }
7485
7486 if (ret == 0) {
7487 /* Before searching for available LRO objects,
7488 * check if the pkt is L3/L4 aggregatable. If not
7489 * don't create new LRO session. Just send this
7490 * packet up.
7491 */
7492 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7493 return 5;
7494 }
7495
7496 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7497 lro_t *l_lro = &sp->lro0_n[i];
7498 if (!(l_lro->in_use)) {
7499 *lro = l_lro;
7500 ret = 3; /* Begin anew */
7501 break;
7502 }
7503 }
7504 }
7505
7506 if (ret == 0) { /* sessions exceeded */
7507 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7508 __FUNCTION__);
7509 *lro = NULL;
7510 return ret;
7511 }
7512
7513 switch (ret) {
7514 case 3:
7515 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7516 break;
7517 case 2:
7518 update_L3L4_header(sp, *lro);
7519 break;
7520 case 1:
7521 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7522 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7523 update_L3L4_header(sp, *lro);
7524 ret = 4; /* Flush the LRO */
7525 }
7526 break;
7527 default:
7528 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7529 __FUNCTION__);
7530 break;
7531 }
7532
7533 return ret;
7534 }
7535
7536 static void clear_lro_session(lro_t *lro)
7537 {
7538 static u16 lro_struct_size = sizeof(lro_t);
7539
7540 memset(lro, 0, lro_struct_size);
7541 }
7542
7543 static void queue_rx_frame(struct sk_buff *skb)
7544 {
7545 struct net_device *dev = skb->dev;
7546
7547 skb->protocol = eth_type_trans(skb, dev);
7548 #ifdef CONFIG_S2IO_NAPI
7549 netif_receive_skb(skb);
7550 #else
7551 netif_rx(skb);
7552 #endif
7553 }
7554
7555 static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
7556 u32 tcp_len)
7557 {
7558 struct sk_buff *first = lro->parent;
7559
7560 first->len += tcp_len;
7561 first->data_len = lro->frags_len;
7562 skb_pull(skb, (skb->len - tcp_len));
7563 if (skb_shinfo(first)->frag_list)
7564 lro->last_frag->next = skb;
7565 else
7566 skb_shinfo(first)->frag_list = skb;
7567 lro->last_frag = skb;
7568 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7569 return;
7570 }
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