1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 * rx_ring_num : This can be used to program the number of receive rings used
31 * rx_ring_sz: This defines the number of descriptors each ring can have. This
32 * is also an array of size 8.
33 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
34 * values are 1, 2 and 3.
35 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
36 * tx_fifo_len: This too is an array of 8. Each element defines the number of
37 * Tx descriptors that can be associated with each corresponding FIFO.
38 ************************************************************************/
40 #include <linux/config.h>
41 #include <linux/module.h>
42 #include <linux/types.h>
43 #include <linux/errno.h>
44 #include <linux/ioport.h>
45 #include <linux/pci.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/kernel.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/init.h>
52 #include <linux/delay.h>
53 #include <linux/stddef.h>
54 #include <linux/ioctl.h>
55 #include <linux/timex.h>
56 #include <linux/sched.h>
57 #include <linux/ethtool.h>
58 #include <linux/workqueue.h>
59 #include <linux/if_vlan.h>
61 #include <asm/system.h>
62 #include <asm/uaccess.h>
67 #include "s2io-regs.h"
69 #define DRV_VERSION "Version 2.0.9.3"
71 /* S2io Driver name & version. */
72 static char s2io_driver_name
[] = "Neterion";
73 static char s2io_driver_version
[] = DRV_VERSION
;
75 int rxd_size
[4] = {32,48,48,64};
76 int rxd_count
[4] = {127,85,85,63};
78 static inline int RXD_IS_UP2DT(RxD_t
*rxdp
)
82 ret
= ((!(rxdp
->Control_1
& RXD_OWN_XENA
)) &&
83 (GET_RXD_MARKER(rxdp
->Control_2
) != THE_RXD_MARK
));
89 * Cards with following subsystem_id have a link state indication
90 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
91 * macro below identifies these cards given the subsystem_id.
93 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
94 (dev_type == XFRAME_I_DEVICE) ? \
95 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
96 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
98 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
99 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
100 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
103 static inline int rx_buffer_level(nic_t
* sp
, int rxb_size
, int ring
)
106 mac_info_t
*mac_control
;
108 mac_control
= &sp
->mac_control
;
109 if ((mac_control
->rings
[ring
].pkt_cnt
- rxb_size
) > 16) {
111 if (rxb_size
<= rxd_count
[sp
->rxd_mode
]) {
119 /* Ethtool related variables and Macros. */
120 static char s2io_gstrings
[][ETH_GSTRING_LEN
] = {
121 "Register test\t(offline)",
122 "Eeprom test\t(offline)",
123 "Link test\t(online)",
124 "RLDRAM test\t(offline)",
125 "BIST Test\t(offline)"
128 static char ethtool_stats_keys
[][ETH_GSTRING_LEN
] = {
130 {"tmac_data_octets"},
134 {"tmac_pause_ctrl_frms"},
135 {"tmac_any_err_frms"},
136 {"tmac_vld_ip_octets"},
144 {"rmac_data_octets"},
145 {"rmac_fcs_err_frms"},
147 {"rmac_vld_mcst_frms"},
148 {"rmac_vld_bcst_frms"},
149 {"rmac_in_rng_len_err_frms"},
151 {"rmac_pause_ctrl_frms"},
152 {"rmac_discarded_frms"},
153 {"rmac_usized_frms"},
154 {"rmac_osized_frms"},
156 {"rmac_jabber_frms"},
164 {"rmac_err_drp_udp"},
166 {"rmac_accepted_ip"},
168 {"\n DRIVER STATISTICS"},
169 {"single_bit_ecc_errs"},
170 {"double_bit_ecc_errs"},
173 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
174 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
176 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
177 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
179 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
180 init_timer(&timer); \
181 timer.function = handle; \
182 timer.data = (unsigned long) arg; \
183 mod_timer(&timer, (jiffies + exp)) \
186 static void s2io_vlan_rx_register(struct net_device
*dev
,
187 struct vlan_group
*grp
)
189 nic_t
*nic
= dev
->priv
;
192 spin_lock_irqsave(&nic
->tx_lock
, flags
);
194 spin_unlock_irqrestore(&nic
->tx_lock
, flags
);
197 /* Unregister the vlan */
198 static void s2io_vlan_rx_kill_vid(struct net_device
*dev
, unsigned long vid
)
200 nic_t
*nic
= dev
->priv
;
203 spin_lock_irqsave(&nic
->tx_lock
, flags
);
205 nic
->vlgrp
->vlan_devices
[vid
] = NULL
;
206 spin_unlock_irqrestore(&nic
->tx_lock
, flags
);
210 * Constants to be programmed into the Xena's registers, to configure
214 #define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL
217 static u64 herc_act_dtx_cfg
[] = {
219 0x8000051536750000ULL
, 0x80000515367500E0ULL
,
221 0x8000051536750004ULL
, 0x80000515367500E4ULL
,
223 0x80010515003F0000ULL
, 0x80010515003F00E0ULL
,
225 0x80010515003F0004ULL
, 0x80010515003F00E4ULL
,
227 0x801205150D440000ULL
, 0x801205150D4400E0ULL
,
229 0x801205150D440004ULL
, 0x801205150D4400E4ULL
,
231 0x80020515F2100000ULL
, 0x80020515F21000E0ULL
,
233 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
238 static u64 xena_mdio_cfg
[] = {
240 0xC001010000000000ULL
, 0xC0010100000000E0ULL
,
241 0xC0010100008000E4ULL
,
242 /* Remove Reset from PMA PLL */
243 0xC001010000000000ULL
, 0xC0010100000000E0ULL
,
244 0xC0010100000000E4ULL
,
248 static u64 xena_dtx_cfg
[] = {
249 0x8000051500000000ULL
, 0x80000515000000E0ULL
,
250 0x80000515D93500E4ULL
, 0x8001051500000000ULL
,
251 0x80010515000000E0ULL
, 0x80010515001E00E4ULL
,
252 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
253 0x80020515F21000E4ULL
,
254 /* Set PADLOOPBACKN */
255 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
256 0x80020515B20000E4ULL
, 0x8003051500000000ULL
,
257 0x80030515000000E0ULL
, 0x80030515B20000E4ULL
,
258 0x8004051500000000ULL
, 0x80040515000000E0ULL
,
259 0x80040515B20000E4ULL
, 0x8005051500000000ULL
,
260 0x80050515000000E0ULL
, 0x80050515B20000E4ULL
,
262 /* Remove PADLOOPBACKN */
263 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
264 0x80020515F20000E4ULL
, 0x8003051500000000ULL
,
265 0x80030515000000E0ULL
, 0x80030515F20000E4ULL
,
266 0x8004051500000000ULL
, 0x80040515000000E0ULL
,
267 0x80040515F20000E4ULL
, 0x8005051500000000ULL
,
268 0x80050515000000E0ULL
, 0x80050515F20000E4ULL
,
273 * Constants for Fixing the MacAddress problem seen mostly on
276 static u64 fix_mac
[] = {
277 0x0060000000000000ULL
, 0x0060600000000000ULL
,
278 0x0040600000000000ULL
, 0x0000600000000000ULL
,
279 0x0020600000000000ULL
, 0x0060600000000000ULL
,
280 0x0020600000000000ULL
, 0x0060600000000000ULL
,
281 0x0020600000000000ULL
, 0x0060600000000000ULL
,
282 0x0020600000000000ULL
, 0x0060600000000000ULL
,
283 0x0020600000000000ULL
, 0x0060600000000000ULL
,
284 0x0020600000000000ULL
, 0x0060600000000000ULL
,
285 0x0020600000000000ULL
, 0x0060600000000000ULL
,
286 0x0020600000000000ULL
, 0x0060600000000000ULL
,
287 0x0020600000000000ULL
, 0x0060600000000000ULL
,
288 0x0020600000000000ULL
, 0x0060600000000000ULL
,
289 0x0020600000000000ULL
, 0x0000600000000000ULL
,
290 0x0040600000000000ULL
, 0x0060600000000000ULL
,
294 /* Module Loadable parameters. */
295 static unsigned int tx_fifo_num
= 1;
296 static unsigned int tx_fifo_len
[MAX_TX_FIFOS
] =
297 {[0 ...(MAX_TX_FIFOS
- 1)] = 0 };
298 static unsigned int rx_ring_num
= 1;
299 static unsigned int rx_ring_sz
[MAX_RX_RINGS
] =
300 {[0 ...(MAX_RX_RINGS
- 1)] = 0 };
301 static unsigned int rts_frm_len
[MAX_RX_RINGS
] =
302 {[0 ...(MAX_RX_RINGS
- 1)] = 0 };
303 static unsigned int rx_ring_mode
= 1;
304 static unsigned int use_continuous_tx_intrs
= 1;
305 static unsigned int rmac_pause_time
= 65535;
306 static unsigned int mc_pause_threshold_q0q3
= 187;
307 static unsigned int mc_pause_threshold_q4q7
= 187;
308 static unsigned int shared_splits
;
309 static unsigned int tmac_util_period
= 5;
310 static unsigned int rmac_util_period
= 5;
311 static unsigned int bimodal
= 0;
312 static unsigned int l3l4hdr_size
= 128;
313 #ifndef CONFIG_S2IO_NAPI
314 static unsigned int indicate_max_pkts
;
316 /* Frequency of Rx desc syncs expressed as power of 2 */
317 static unsigned int rxsync_frequency
= 3;
318 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
319 static unsigned int intr_type
= 0;
323 * This table lists all the devices that this driver supports.
325 static struct pci_device_id s2io_tbl
[] __devinitdata
= {
326 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_WIN
,
327 PCI_ANY_ID
, PCI_ANY_ID
},
328 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_UNI
,
329 PCI_ANY_ID
, PCI_ANY_ID
},
330 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_WIN
,
331 PCI_ANY_ID
, PCI_ANY_ID
},
332 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_UNI
,
333 PCI_ANY_ID
, PCI_ANY_ID
},
337 MODULE_DEVICE_TABLE(pci
, s2io_tbl
);
339 static struct pci_driver s2io_driver
= {
341 .id_table
= s2io_tbl
,
342 .probe
= s2io_init_nic
,
343 .remove
= __devexit_p(s2io_rem_nic
),
346 /* A simplifier macro used both by init and free shared_mem Fns(). */
347 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
350 * init_shared_mem - Allocation and Initialization of Memory
351 * @nic: Device private variable.
352 * Description: The function allocates all the memory areas shared
353 * between the NIC and the driver. This includes Tx descriptors,
354 * Rx descriptors and the statistics block.
357 static int init_shared_mem(struct s2io_nic
*nic
)
360 void *tmp_v_addr
, *tmp_v_addr_next
;
361 dma_addr_t tmp_p_addr
, tmp_p_addr_next
;
362 RxD_block_t
*pre_rxd_blk
= NULL
;
363 int i
, j
, blk_cnt
, rx_sz
, tx_sz
;
364 int lst_size
, lst_per_page
;
365 struct net_device
*dev
= nic
->dev
;
369 mac_info_t
*mac_control
;
370 struct config_param
*config
;
372 mac_control
= &nic
->mac_control
;
373 config
= &nic
->config
;
376 /* Allocation and initialization of TXDLs in FIOFs */
378 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
379 size
+= config
->tx_cfg
[i
].fifo_len
;
381 if (size
> MAX_AVAILABLE_TXDS
) {
382 DBG_PRINT(ERR_DBG
, "%s: Requested TxDs too high, ",
384 DBG_PRINT(ERR_DBG
, "Requested: %d, max supported: 8192\n", size
);
388 lst_size
= (sizeof(TxD_t
) * config
->max_txds
);
389 tx_sz
= lst_size
* size
;
390 lst_per_page
= PAGE_SIZE
/ lst_size
;
392 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
393 int fifo_len
= config
->tx_cfg
[i
].fifo_len
;
394 int list_holder_size
= fifo_len
* sizeof(list_info_hold_t
);
395 mac_control
->fifos
[i
].list_info
= kmalloc(list_holder_size
,
397 if (!mac_control
->fifos
[i
].list_info
) {
399 "Malloc failed for list_info\n");
402 memset(mac_control
->fifos
[i
].list_info
, 0, list_holder_size
);
404 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
405 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
407 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
408 mac_control
->fifos
[i
].tx_curr_put_info
.fifo_len
=
409 config
->tx_cfg
[i
].fifo_len
- 1;
410 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
411 mac_control
->fifos
[i
].tx_curr_get_info
.fifo_len
=
412 config
->tx_cfg
[i
].fifo_len
- 1;
413 mac_control
->fifos
[i
].fifo_no
= i
;
414 mac_control
->fifos
[i
].nic
= nic
;
415 mac_control
->fifos
[i
].max_txds
= MAX_SKB_FRAGS
+ 1;
417 for (j
= 0; j
< page_num
; j
++) {
421 tmp_v
= pci_alloc_consistent(nic
->pdev
,
425 "pci_alloc_consistent ");
426 DBG_PRINT(ERR_DBG
, "failed for TxDL\n");
429 /* If we got a zero DMA address(can happen on
430 * certain platforms like PPC), reallocate.
431 * Store virtual address of page we don't want,
435 mac_control
->zerodma_virt_addr
= tmp_v
;
437 "%s: Zero DMA address for TxDL. ", dev
->name
);
439 "Virtual address %p\n", tmp_v
);
440 tmp_v
= pci_alloc_consistent(nic
->pdev
,
444 "pci_alloc_consistent ");
445 DBG_PRINT(ERR_DBG
, "failed for TxDL\n");
449 while (k
< lst_per_page
) {
450 int l
= (j
* lst_per_page
) + k
;
451 if (l
== config
->tx_cfg
[i
].fifo_len
)
453 mac_control
->fifos
[i
].list_info
[l
].list_virt_addr
=
454 tmp_v
+ (k
* lst_size
);
455 mac_control
->fifos
[i
].list_info
[l
].list_phy_addr
=
456 tmp_p
+ (k
* lst_size
);
462 /* Allocation and initialization of RXDs in Rings */
464 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
465 if (config
->rx_cfg
[i
].num_rxd
%
466 (rxd_count
[nic
->rxd_mode
] + 1)) {
467 DBG_PRINT(ERR_DBG
, "%s: RxD count of ", dev
->name
);
468 DBG_PRINT(ERR_DBG
, "Ring%d is not a multiple of ",
470 DBG_PRINT(ERR_DBG
, "RxDs per Block");
473 size
+= config
->rx_cfg
[i
].num_rxd
;
474 mac_control
->rings
[i
].block_count
=
475 config
->rx_cfg
[i
].num_rxd
/
476 (rxd_count
[nic
->rxd_mode
] + 1 );
477 mac_control
->rings
[i
].pkt_cnt
= config
->rx_cfg
[i
].num_rxd
-
478 mac_control
->rings
[i
].block_count
;
480 if (nic
->rxd_mode
== RXD_MODE_1
)
481 size
= (size
* (sizeof(RxD1_t
)));
483 size
= (size
* (sizeof(RxD3_t
)));
486 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
487 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
488 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
489 mac_control
->rings
[i
].rx_curr_get_info
.ring_len
=
490 config
->rx_cfg
[i
].num_rxd
- 1;
491 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
492 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
493 mac_control
->rings
[i
].rx_curr_put_info
.ring_len
=
494 config
->rx_cfg
[i
].num_rxd
- 1;
495 mac_control
->rings
[i
].nic
= nic
;
496 mac_control
->rings
[i
].ring_no
= i
;
498 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
499 (rxd_count
[nic
->rxd_mode
] + 1);
500 /* Allocating all the Rx blocks */
501 for (j
= 0; j
< blk_cnt
; j
++) {
502 rx_block_info_t
*rx_blocks
;
505 rx_blocks
= &mac_control
->rings
[i
].rx_blocks
[j
];
506 size
= SIZE_OF_BLOCK
; //size is always page size
507 tmp_v_addr
= pci_alloc_consistent(nic
->pdev
, size
,
509 if (tmp_v_addr
== NULL
) {
511 * In case of failure, free_shared_mem()
512 * is called, which should free any
513 * memory that was alloced till the
516 rx_blocks
->block_virt_addr
= tmp_v_addr
;
519 memset(tmp_v_addr
, 0, size
);
520 rx_blocks
->block_virt_addr
= tmp_v_addr
;
521 rx_blocks
->block_dma_addr
= tmp_p_addr
;
522 rx_blocks
->rxds
= kmalloc(sizeof(rxd_info_t
)*
523 rxd_count
[nic
->rxd_mode
],
525 for (l
=0; l
<rxd_count
[nic
->rxd_mode
];l
++) {
526 rx_blocks
->rxds
[l
].virt_addr
=
527 rx_blocks
->block_virt_addr
+
528 (rxd_size
[nic
->rxd_mode
] * l
);
529 rx_blocks
->rxds
[l
].dma_addr
=
530 rx_blocks
->block_dma_addr
+
531 (rxd_size
[nic
->rxd_mode
] * l
);
534 mac_control
->rings
[i
].rx_blocks
[j
].block_virt_addr
=
536 mac_control
->rings
[i
].rx_blocks
[j
].block_dma_addr
=
539 /* Interlinking all Rx Blocks */
540 for (j
= 0; j
< blk_cnt
; j
++) {
542 mac_control
->rings
[i
].rx_blocks
[j
].block_virt_addr
;
544 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
545 blk_cnt
].block_virt_addr
;
547 mac_control
->rings
[i
].rx_blocks
[j
].block_dma_addr
;
549 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
550 blk_cnt
].block_dma_addr
;
552 pre_rxd_blk
= (RxD_block_t
*) tmp_v_addr
;
553 pre_rxd_blk
->reserved_2_pNext_RxD_block
=
554 (unsigned long) tmp_v_addr_next
;
555 pre_rxd_blk
->pNext_RxD_Blk_physical
=
556 (u64
) tmp_p_addr_next
;
559 if (nic
->rxd_mode
>= RXD_MODE_3A
) {
561 * Allocation of Storages for buffer addresses in 2BUFF mode
562 * and the buffers as well.
564 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
565 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
566 (rxd_count
[nic
->rxd_mode
]+ 1);
567 mac_control
->rings
[i
].ba
=
568 kmalloc((sizeof(buffAdd_t
*) * blk_cnt
),
570 if (!mac_control
->rings
[i
].ba
)
572 for (j
= 0; j
< blk_cnt
; j
++) {
574 mac_control
->rings
[i
].ba
[j
] =
575 kmalloc((sizeof(buffAdd_t
) *
576 (rxd_count
[nic
->rxd_mode
] + 1)),
578 if (!mac_control
->rings
[i
].ba
[j
])
580 while (k
!= rxd_count
[nic
->rxd_mode
]) {
581 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
583 ba
->ba_0_org
= (void *) kmalloc
584 (BUF0_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
587 tmp
= (unsigned long)ba
->ba_0_org
;
589 tmp
&= ~((unsigned long) ALIGN_SIZE
);
590 ba
->ba_0
= (void *) tmp
;
592 ba
->ba_1_org
= (void *) kmalloc
593 (BUF1_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
596 tmp
= (unsigned long) ba
->ba_1_org
;
598 tmp
&= ~((unsigned long) ALIGN_SIZE
);
599 ba
->ba_1
= (void *) tmp
;
606 /* Allocation and initialization of Statistics block */
607 size
= sizeof(StatInfo_t
);
608 mac_control
->stats_mem
= pci_alloc_consistent
609 (nic
->pdev
, size
, &mac_control
->stats_mem_phy
);
611 if (!mac_control
->stats_mem
) {
613 * In case of failure, free_shared_mem() is called, which
614 * should free any memory that was alloced till the
619 mac_control
->stats_mem_sz
= size
;
621 tmp_v_addr
= mac_control
->stats_mem
;
622 mac_control
->stats_info
= (StatInfo_t
*) tmp_v_addr
;
623 memset(tmp_v_addr
, 0, size
);
624 DBG_PRINT(INIT_DBG
, "%s:Ring Mem PHY: 0x%llx\n", dev
->name
,
625 (unsigned long long) tmp_p_addr
);
631 * free_shared_mem - Free the allocated Memory
632 * @nic: Device private variable.
633 * Description: This function is to free all memory locations allocated by
634 * the init_shared_mem() function and return it to the kernel.
637 static void free_shared_mem(struct s2io_nic
*nic
)
639 int i
, j
, blk_cnt
, size
;
641 dma_addr_t tmp_p_addr
;
642 mac_info_t
*mac_control
;
643 struct config_param
*config
;
644 int lst_size
, lst_per_page
;
645 struct net_device
*dev
= nic
->dev
;
650 mac_control
= &nic
->mac_control
;
651 config
= &nic
->config
;
653 lst_size
= (sizeof(TxD_t
) * config
->max_txds
);
654 lst_per_page
= PAGE_SIZE
/ lst_size
;
656 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
657 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
659 for (j
= 0; j
< page_num
; j
++) {
660 int mem_blks
= (j
* lst_per_page
);
661 if (!mac_control
->fifos
[i
].list_info
)
663 if (!mac_control
->fifos
[i
].list_info
[mem_blks
].
666 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
667 mac_control
->fifos
[i
].
670 mac_control
->fifos
[i
].
674 /* If we got a zero DMA address during allocation,
677 if (mac_control
->zerodma_virt_addr
) {
678 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
679 mac_control
->zerodma_virt_addr
,
682 "%s: Freeing TxDL with zero DMA addr. ",
684 DBG_PRINT(INIT_DBG
, "Virtual address %p\n",
685 mac_control
->zerodma_virt_addr
);
687 kfree(mac_control
->fifos
[i
].list_info
);
690 size
= SIZE_OF_BLOCK
;
691 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
692 blk_cnt
= mac_control
->rings
[i
].block_count
;
693 for (j
= 0; j
< blk_cnt
; j
++) {
694 tmp_v_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
696 tmp_p_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
698 if (tmp_v_addr
== NULL
)
700 pci_free_consistent(nic
->pdev
, size
,
701 tmp_v_addr
, tmp_p_addr
);
702 kfree(mac_control
->rings
[i
].rx_blocks
[j
].rxds
);
706 if (nic
->rxd_mode
>= RXD_MODE_3A
) {
707 /* Freeing buffer storage addresses in 2BUFF mode. */
708 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
709 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
710 (rxd_count
[nic
->rxd_mode
] + 1);
711 for (j
= 0; j
< blk_cnt
; j
++) {
713 if (!mac_control
->rings
[i
].ba
[j
])
715 while (k
!= rxd_count
[nic
->rxd_mode
]) {
717 &mac_control
->rings
[i
].ba
[j
][k
];
722 kfree(mac_control
->rings
[i
].ba
[j
]);
724 kfree(mac_control
->rings
[i
].ba
);
728 if (mac_control
->stats_mem
) {
729 pci_free_consistent(nic
->pdev
,
730 mac_control
->stats_mem_sz
,
731 mac_control
->stats_mem
,
732 mac_control
->stats_mem_phy
);
737 * s2io_verify_pci_mode -
740 static int s2io_verify_pci_mode(nic_t
*nic
)
742 XENA_dev_config_t __iomem
*bar0
= nic
->bar0
;
743 register u64 val64
= 0;
746 val64
= readq(&bar0
->pci_mode
);
747 mode
= (u8
)GET_PCI_MODE(val64
);
749 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
750 return -1; /* Unknown PCI mode */
756 * s2io_print_pci_mode -
758 static int s2io_print_pci_mode(nic_t
*nic
)
760 XENA_dev_config_t __iomem
*bar0
= nic
->bar0
;
761 register u64 val64
= 0;
763 struct config_param
*config
= &nic
->config
;
765 val64
= readq(&bar0
->pci_mode
);
766 mode
= (u8
)GET_PCI_MODE(val64
);
768 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
769 return -1; /* Unknown PCI mode */
771 if (val64
& PCI_MODE_32_BITS
) {
772 DBG_PRINT(ERR_DBG
, "%s: Device is on 32 bit ", nic
->dev
->name
);
774 DBG_PRINT(ERR_DBG
, "%s: Device is on 64 bit ", nic
->dev
->name
);
778 case PCI_MODE_PCI_33
:
779 DBG_PRINT(ERR_DBG
, "33MHz PCI bus\n");
780 config
->bus_speed
= 33;
782 case PCI_MODE_PCI_66
:
783 DBG_PRINT(ERR_DBG
, "66MHz PCI bus\n");
784 config
->bus_speed
= 133;
786 case PCI_MODE_PCIX_M1_66
:
787 DBG_PRINT(ERR_DBG
, "66MHz PCIX(M1) bus\n");
788 config
->bus_speed
= 133; /* Herc doubles the clock rate */
790 case PCI_MODE_PCIX_M1_100
:
791 DBG_PRINT(ERR_DBG
, "100MHz PCIX(M1) bus\n");
792 config
->bus_speed
= 200;
794 case PCI_MODE_PCIX_M1_133
:
795 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M1) bus\n");
796 config
->bus_speed
= 266;
798 case PCI_MODE_PCIX_M2_66
:
799 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M2) bus\n");
800 config
->bus_speed
= 133;
802 case PCI_MODE_PCIX_M2_100
:
803 DBG_PRINT(ERR_DBG
, "200MHz PCIX(M2) bus\n");
804 config
->bus_speed
= 200;
806 case PCI_MODE_PCIX_M2_133
:
807 DBG_PRINT(ERR_DBG
, "266MHz PCIX(M2) bus\n");
808 config
->bus_speed
= 266;
811 return -1; /* Unsupported bus speed */
818 * init_nic - Initialization of hardware
819 * @nic: device peivate variable
820 * Description: The function sequentially configures every block
821 * of the H/W from their reset values.
822 * Return Value: SUCCESS on success and
823 * '-1' on failure (endian settings incorrect).
826 static int init_nic(struct s2io_nic
*nic
)
828 XENA_dev_config_t __iomem
*bar0
= nic
->bar0
;
829 struct net_device
*dev
= nic
->dev
;
830 register u64 val64
= 0;
834 mac_info_t
*mac_control
;
835 struct config_param
*config
;
836 int mdio_cnt
= 0, dtx_cnt
= 0;
837 unsigned long long mem_share
;
840 mac_control
= &nic
->mac_control
;
841 config
= &nic
->config
;
843 /* to set the swapper controle on the card */
844 if(s2io_set_swapper(nic
)) {
845 DBG_PRINT(ERR_DBG
,"ERROR: Setting Swapper failed\n");
850 * Herc requires EOI to be removed from reset before XGXS, so..
852 if (nic
->device_type
& XFRAME_II_DEVICE
) {
853 val64
= 0xA500000000ULL
;
854 writeq(val64
, &bar0
->sw_reset
);
856 val64
= readq(&bar0
->sw_reset
);
859 /* Remove XGXS from reset state */
861 writeq(val64
, &bar0
->sw_reset
);
863 val64
= readq(&bar0
->sw_reset
);
865 /* Enable Receiving broadcasts */
866 add
= &bar0
->mac_cfg
;
867 val64
= readq(&bar0
->mac_cfg
);
868 val64
|= MAC_RMAC_BCAST_ENABLE
;
869 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
870 writel((u32
) val64
, add
);
871 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
872 writel((u32
) (val64
>> 32), (add
+ 4));
874 /* Read registers in all blocks */
875 val64
= readq(&bar0
->mac_int_mask
);
876 val64
= readq(&bar0
->mc_int_mask
);
877 val64
= readq(&bar0
->xgxs_int_mask
);
881 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
884 * Configuring the XAUI Interface of Xena.
885 * ***************************************
886 * To Configure the Xena's XAUI, one has to write a series
887 * of 64 bit values into two registers in a particular
888 * sequence. Hence a macro 'SWITCH_SIGN' has been defined
889 * which will be defined in the array of configuration values
890 * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
891 * to switch writing from one regsiter to another. We continue
892 * writing these values until we encounter the 'END_SIGN' macro.
893 * For example, After making a series of 21 writes into
894 * dtx_control register the 'SWITCH_SIGN' appears and hence we
895 * start writing into mdio_control until we encounter END_SIGN.
897 if (nic
->device_type
& XFRAME_II_DEVICE
) {
898 while (herc_act_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
899 SPECIAL_REG_WRITE(herc_act_dtx_cfg
[dtx_cnt
],
900 &bar0
->dtx_control
, UF
);
902 msleep(1); /* Necessary!! */
908 while (xena_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
909 if (xena_dtx_cfg
[dtx_cnt
] == SWITCH_SIGN
) {
913 SPECIAL_REG_WRITE(xena_dtx_cfg
[dtx_cnt
],
914 &bar0
->dtx_control
, UF
);
915 val64
= readq(&bar0
->dtx_control
);
919 while (xena_mdio_cfg
[mdio_cnt
] != END_SIGN
) {
920 if (xena_mdio_cfg
[mdio_cnt
] == SWITCH_SIGN
) {
924 SPECIAL_REG_WRITE(xena_mdio_cfg
[mdio_cnt
],
925 &bar0
->mdio_control
, UF
);
926 val64
= readq(&bar0
->mdio_control
);
929 if ((xena_dtx_cfg
[dtx_cnt
] == END_SIGN
) &&
930 (xena_mdio_cfg
[mdio_cnt
] == END_SIGN
)) {
938 /* Tx DMA Initialization */
940 writeq(val64
, &bar0
->tx_fifo_partition_0
);
941 writeq(val64
, &bar0
->tx_fifo_partition_1
);
942 writeq(val64
, &bar0
->tx_fifo_partition_2
);
943 writeq(val64
, &bar0
->tx_fifo_partition_3
);
946 for (i
= 0, j
= 0; i
< config
->tx_fifo_num
; i
++) {
948 vBIT(config
->tx_cfg
[i
].fifo_len
- 1, ((i
* 32) + 19),
949 13) | vBIT(config
->tx_cfg
[i
].fifo_priority
,
952 if (i
== (config
->tx_fifo_num
- 1)) {
959 writeq(val64
, &bar0
->tx_fifo_partition_0
);
963 writeq(val64
, &bar0
->tx_fifo_partition_1
);
967 writeq(val64
, &bar0
->tx_fifo_partition_2
);
971 writeq(val64
, &bar0
->tx_fifo_partition_3
);
976 /* Enable Tx FIFO partition 0. */
977 val64
= readq(&bar0
->tx_fifo_partition_0
);
978 val64
|= BIT(0); /* To enable the FIFO partition. */
979 writeq(val64
, &bar0
->tx_fifo_partition_0
);
982 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
983 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
985 if ((nic
->device_type
== XFRAME_I_DEVICE
) &&
986 (get_xena_rev_id(nic
->pdev
) < 4))
987 writeq(PCC_ENABLE_FOUR
, &bar0
->pcc_enable
);
989 val64
= readq(&bar0
->tx_fifo_partition_0
);
990 DBG_PRINT(INIT_DBG
, "Fifo partition at: 0x%p is: 0x%llx\n",
991 &bar0
->tx_fifo_partition_0
, (unsigned long long) val64
);
994 * Initialization of Tx_PA_CONFIG register to ignore packet
995 * integrity checking.
997 val64
= readq(&bar0
->tx_pa_cfg
);
998 val64
|= TX_PA_CFG_IGNORE_FRM_ERR
| TX_PA_CFG_IGNORE_SNAP_OUI
|
999 TX_PA_CFG_IGNORE_LLC_CTRL
| TX_PA_CFG_IGNORE_L2_ERR
;
1000 writeq(val64
, &bar0
->tx_pa_cfg
);
1002 /* Rx DMA intialization. */
1004 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1006 vBIT(config
->rx_cfg
[i
].ring_priority
, (5 + (i
* 8)),
1009 writeq(val64
, &bar0
->rx_queue_priority
);
1012 * Allocating equal share of memory to all the
1016 if (nic
->device_type
& XFRAME_II_DEVICE
)
1021 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1024 mem_share
= (mem_size
/ config
->rx_ring_num
+
1025 mem_size
% config
->rx_ring_num
);
1026 val64
|= RX_QUEUE_CFG_Q0_SZ(mem_share
);
1029 mem_share
= (mem_size
/ config
->rx_ring_num
);
1030 val64
|= RX_QUEUE_CFG_Q1_SZ(mem_share
);
1033 mem_share
= (mem_size
/ config
->rx_ring_num
);
1034 val64
|= RX_QUEUE_CFG_Q2_SZ(mem_share
);
1037 mem_share
= (mem_size
/ config
->rx_ring_num
);
1038 val64
|= RX_QUEUE_CFG_Q3_SZ(mem_share
);
1041 mem_share
= (mem_size
/ config
->rx_ring_num
);
1042 val64
|= RX_QUEUE_CFG_Q4_SZ(mem_share
);
1045 mem_share
= (mem_size
/ config
->rx_ring_num
);
1046 val64
|= RX_QUEUE_CFG_Q5_SZ(mem_share
);
1049 mem_share
= (mem_size
/ config
->rx_ring_num
);
1050 val64
|= RX_QUEUE_CFG_Q6_SZ(mem_share
);
1053 mem_share
= (mem_size
/ config
->rx_ring_num
);
1054 val64
|= RX_QUEUE_CFG_Q7_SZ(mem_share
);
1058 writeq(val64
, &bar0
->rx_queue_cfg
);
1061 * Filling Tx round robin registers
1062 * as per the number of FIFOs
1064 switch (config
->tx_fifo_num
) {
1066 val64
= 0x0000000000000000ULL
;
1067 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1068 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1069 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1070 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1071 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1074 val64
= 0x0000010000010000ULL
;
1075 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1076 val64
= 0x0100000100000100ULL
;
1077 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1078 val64
= 0x0001000001000001ULL
;
1079 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1080 val64
= 0x0000010000010000ULL
;
1081 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1082 val64
= 0x0100000000000000ULL
;
1083 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1086 val64
= 0x0001000102000001ULL
;
1087 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1088 val64
= 0x0001020000010001ULL
;
1089 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1090 val64
= 0x0200000100010200ULL
;
1091 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1092 val64
= 0x0001000102000001ULL
;
1093 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1094 val64
= 0x0001020000000000ULL
;
1095 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1098 val64
= 0x0001020300010200ULL
;
1099 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1100 val64
= 0x0100000102030001ULL
;
1101 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1102 val64
= 0x0200010000010203ULL
;
1103 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1104 val64
= 0x0001020001000001ULL
;
1105 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1106 val64
= 0x0203000100000000ULL
;
1107 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1110 val64
= 0x0001000203000102ULL
;
1111 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1112 val64
= 0x0001020001030004ULL
;
1113 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1114 val64
= 0x0001000203000102ULL
;
1115 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1116 val64
= 0x0001020001030004ULL
;
1117 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1118 val64
= 0x0001000000000000ULL
;
1119 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1122 val64
= 0x0001020304000102ULL
;
1123 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1124 val64
= 0x0304050001020001ULL
;
1125 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1126 val64
= 0x0203000100000102ULL
;
1127 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1128 val64
= 0x0304000102030405ULL
;
1129 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1130 val64
= 0x0001000200000000ULL
;
1131 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1134 val64
= 0x0001020001020300ULL
;
1135 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1136 val64
= 0x0102030400010203ULL
;
1137 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1138 val64
= 0x0405060001020001ULL
;
1139 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1140 val64
= 0x0304050000010200ULL
;
1141 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1142 val64
= 0x0102030000000000ULL
;
1143 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1146 val64
= 0x0001020300040105ULL
;
1147 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1148 val64
= 0x0200030106000204ULL
;
1149 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1150 val64
= 0x0103000502010007ULL
;
1151 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1152 val64
= 0x0304010002060500ULL
;
1153 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1154 val64
= 0x0103020400000000ULL
;
1155 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1159 /* Filling the Rx round robin registers as per the
1160 * number of Rings and steering based on QoS.
1162 switch (config
->rx_ring_num
) {
1164 val64
= 0x8080808080808080ULL
;
1165 writeq(val64
, &bar0
->rts_qos_steering
);
1168 val64
= 0x0000010000010000ULL
;
1169 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1170 val64
= 0x0100000100000100ULL
;
1171 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1172 val64
= 0x0001000001000001ULL
;
1173 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1174 val64
= 0x0000010000010000ULL
;
1175 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1176 val64
= 0x0100000000000000ULL
;
1177 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1179 val64
= 0x8080808040404040ULL
;
1180 writeq(val64
, &bar0
->rts_qos_steering
);
1183 val64
= 0x0001000102000001ULL
;
1184 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1185 val64
= 0x0001020000010001ULL
;
1186 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1187 val64
= 0x0200000100010200ULL
;
1188 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1189 val64
= 0x0001000102000001ULL
;
1190 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1191 val64
= 0x0001020000000000ULL
;
1192 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1194 val64
= 0x8080804040402020ULL
;
1195 writeq(val64
, &bar0
->rts_qos_steering
);
1198 val64
= 0x0001020300010200ULL
;
1199 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1200 val64
= 0x0100000102030001ULL
;
1201 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1202 val64
= 0x0200010000010203ULL
;
1203 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1204 val64
= 0x0001020001000001ULL
;
1205 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1206 val64
= 0x0203000100000000ULL
;
1207 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1209 val64
= 0x8080404020201010ULL
;
1210 writeq(val64
, &bar0
->rts_qos_steering
);
1213 val64
= 0x0001000203000102ULL
;
1214 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1215 val64
= 0x0001020001030004ULL
;
1216 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1217 val64
= 0x0001000203000102ULL
;
1218 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1219 val64
= 0x0001020001030004ULL
;
1220 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1221 val64
= 0x0001000000000000ULL
;
1222 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1224 val64
= 0x8080404020201008ULL
;
1225 writeq(val64
, &bar0
->rts_qos_steering
);
1228 val64
= 0x0001020304000102ULL
;
1229 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1230 val64
= 0x0304050001020001ULL
;
1231 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1232 val64
= 0x0203000100000102ULL
;
1233 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1234 val64
= 0x0304000102030405ULL
;
1235 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1236 val64
= 0x0001000200000000ULL
;
1237 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1239 val64
= 0x8080404020100804ULL
;
1240 writeq(val64
, &bar0
->rts_qos_steering
);
1243 val64
= 0x0001020001020300ULL
;
1244 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1245 val64
= 0x0102030400010203ULL
;
1246 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1247 val64
= 0x0405060001020001ULL
;
1248 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1249 val64
= 0x0304050000010200ULL
;
1250 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1251 val64
= 0x0102030000000000ULL
;
1252 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1254 val64
= 0x8080402010080402ULL
;
1255 writeq(val64
, &bar0
->rts_qos_steering
);
1258 val64
= 0x0001020300040105ULL
;
1259 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1260 val64
= 0x0200030106000204ULL
;
1261 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1262 val64
= 0x0103000502010007ULL
;
1263 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1264 val64
= 0x0304010002060500ULL
;
1265 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1266 val64
= 0x0103020400000000ULL
;
1267 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1269 val64
= 0x8040201008040201ULL
;
1270 writeq(val64
, &bar0
->rts_qos_steering
);
1276 for (i
= 0; i
< 8; i
++)
1277 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1279 /* Set the default rts frame length for the rings configured */
1280 val64
= MAC_RTS_FRM_LEN_SET(dev
->mtu
+22);
1281 for (i
= 0 ; i
< config
->rx_ring_num
; i
++)
1282 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1284 /* Set the frame length for the configured rings
1285 * desired by the user
1287 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1288 /* If rts_frm_len[i] == 0 then it is assumed that user not
1289 * specified frame length steering.
1290 * If the user provides the frame length then program
1291 * the rts_frm_len register for those values or else
1292 * leave it as it is.
1294 if (rts_frm_len
[i
] != 0) {
1295 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len
[i
]),
1296 &bar0
->rts_frm_len_n
[i
]);
1300 /* Program statistics memory */
1301 writeq(mac_control
->stats_mem_phy
, &bar0
->stat_addr
);
1303 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1304 val64
= STAT_BC(0x320);
1305 writeq(val64
, &bar0
->stat_byte_cnt
);
1309 * Initializing the sampling rate for the device to calculate the
1310 * bandwidth utilization.
1312 val64
= MAC_TX_LINK_UTIL_VAL(tmac_util_period
) |
1313 MAC_RX_LINK_UTIL_VAL(rmac_util_period
);
1314 writeq(val64
, &bar0
->mac_link_util
);
1318 * Initializing the Transmit and Receive Traffic Interrupt
1322 * TTI Initialization. Default Tx timer gets us about
1323 * 250 interrupts per sec. Continuous interrupts are enabled
1326 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1327 int count
= (nic
->config
.bus_speed
* 125)/2;
1328 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(count
);
1331 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1333 val64
|= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1334 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1335 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN
;
1336 if (use_continuous_tx_intrs
)
1337 val64
|= TTI_DATA1_MEM_TX_TIMER_CI_EN
;
1338 writeq(val64
, &bar0
->tti_data1_mem
);
1340 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1341 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1342 TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1343 writeq(val64
, &bar0
->tti_data2_mem
);
1345 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
1346 writeq(val64
, &bar0
->tti_command_mem
);
1349 * Once the operation completes, the Strobe bit of the command
1350 * register will be reset. We poll for this particular condition
1351 * We wait for a maximum of 500ms for the operation to complete,
1352 * if it's not complete by then we return error.
1356 val64
= readq(&bar0
->tti_command_mem
);
1357 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
1361 DBG_PRINT(ERR_DBG
, "%s: TTI init Failed\n",
1369 if (nic
->config
.bimodal
) {
1371 for (k
= 0; k
< config
->rx_ring_num
; k
++) {
1372 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
1373 val64
|= TTI_CMD_MEM_OFFSET(0x38+k
);
1374 writeq(val64
, &bar0
->tti_command_mem
);
1377 * Once the operation completes, the Strobe bit of the command
1378 * register will be reset. We poll for this particular condition
1379 * We wait for a maximum of 500ms for the operation to complete,
1380 * if it's not complete by then we return error.
1384 val64
= readq(&bar0
->tti_command_mem
);
1385 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
1390 "%s: TTI init Failed\n",
1400 /* RTI Initialization */
1401 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1403 * Programmed to generate Apprx 500 Intrs per
1406 int count
= (nic
->config
.bus_speed
* 125)/4;
1407 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(count
);
1409 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1411 val64
|= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1412 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1413 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN
;
1415 writeq(val64
, &bar0
->rti_data1_mem
);
1417 val64
= RTI_DATA2_MEM_RX_UFC_A(0x1) |
1418 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1419 if (nic
->intr_type
== MSI_X
)
1420 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1421 RTI_DATA2_MEM_RX_UFC_D(0x40));
1423 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1424 RTI_DATA2_MEM_RX_UFC_D(0x80));
1425 writeq(val64
, &bar0
->rti_data2_mem
);
1427 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1428 val64
= RTI_CMD_MEM_WE
| RTI_CMD_MEM_STROBE_NEW_CMD
1429 | RTI_CMD_MEM_OFFSET(i
);
1430 writeq(val64
, &bar0
->rti_command_mem
);
1433 * Once the operation completes, the Strobe bit of the
1434 * command register will be reset. We poll for this
1435 * particular condition. We wait for a maximum of 500ms
1436 * for the operation to complete, if it's not complete
1437 * by then we return error.
1441 val64
= readq(&bar0
->rti_command_mem
);
1442 if (!(val64
& RTI_CMD_MEM_STROBE_NEW_CMD
)) {
1446 DBG_PRINT(ERR_DBG
, "%s: RTI init Failed\n",
1457 * Initializing proper values as Pause threshold into all
1458 * the 8 Queues on Rx side.
1460 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q0q3
);
1461 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q4q7
);
1463 /* Disable RMAC PAD STRIPPING */
1464 add
= &bar0
->mac_cfg
;
1465 val64
= readq(&bar0
->mac_cfg
);
1466 val64
&= ~(MAC_CFG_RMAC_STRIP_PAD
);
1467 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1468 writel((u32
) (val64
), add
);
1469 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1470 writel((u32
) (val64
>> 32), (add
+ 4));
1471 val64
= readq(&bar0
->mac_cfg
);
1474 * Set the time value to be inserted in the pause frame
1475 * generated by xena.
1477 val64
= readq(&bar0
->rmac_pause_cfg
);
1478 val64
&= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1479 val64
|= RMAC_PAUSE_HG_PTIME(nic
->mac_control
.rmac_pause_time
);
1480 writeq(val64
, &bar0
->rmac_pause_cfg
);
1483 * Set the Threshold Limit for Generating the pause frame
1484 * If the amount of data in any Queue exceeds ratio of
1485 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1486 * pause frame is generated
1489 for (i
= 0; i
< 4; i
++) {
1491 (((u64
) 0xFF00 | nic
->mac_control
.
1492 mc_pause_threshold_q0q3
)
1495 writeq(val64
, &bar0
->mc_pause_thresh_q0q3
);
1498 for (i
= 0; i
< 4; i
++) {
1500 (((u64
) 0xFF00 | nic
->mac_control
.
1501 mc_pause_threshold_q4q7
)
1504 writeq(val64
, &bar0
->mc_pause_thresh_q4q7
);
1507 * TxDMA will stop Read request if the number of read split has
1508 * exceeded the limit pointed by shared_splits
1510 val64
= readq(&bar0
->pic_control
);
1511 val64
|= PIC_CNTL_SHARED_SPLITS(shared_splits
);
1512 writeq(val64
, &bar0
->pic_control
);
1515 * Programming the Herc to split every write transaction
1516 * that does not start on an ADB to reduce disconnects.
1518 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1519 val64
= WREQ_SPLIT_MASK_SET_MASK(255);
1520 writeq(val64
, &bar0
->wreq_split_mask
);
1523 /* Setting Link stability period to 64 ms */
1524 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1525 val64
= MISC_LINK_STABILITY_PRD(3);
1526 writeq(val64
, &bar0
->misc_control
);
1531 #define LINK_UP_DOWN_INTERRUPT 1
1532 #define MAC_RMAC_ERR_TIMER 2
1534 static int s2io_link_fault_indication(nic_t
*nic
)
1536 if (nic
->intr_type
!= INTA
)
1537 return MAC_RMAC_ERR_TIMER
;
1538 if (nic
->device_type
== XFRAME_II_DEVICE
)
1539 return LINK_UP_DOWN_INTERRUPT
;
1541 return MAC_RMAC_ERR_TIMER
;
1545 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1546 * @nic: device private variable,
1547 * @mask: A mask indicating which Intr block must be modified and,
1548 * @flag: A flag indicating whether to enable or disable the Intrs.
1549 * Description: This function will either disable or enable the interrupts
1550 * depending on the flag argument. The mask argument can be used to
1551 * enable/disable any Intr block.
1552 * Return Value: NONE.
1555 static void en_dis_able_nic_intrs(struct s2io_nic
*nic
, u16 mask
, int flag
)
1557 XENA_dev_config_t __iomem
*bar0
= nic
->bar0
;
1558 register u64 val64
= 0, temp64
= 0;
1560 /* Top level interrupt classification */
1561 /* PIC Interrupts */
1562 if ((mask
& (TX_PIC_INTR
| RX_PIC_INTR
))) {
1563 /* Enable PIC Intrs in the general intr mask register */
1564 val64
= TXPIC_INT_M
| PIC_RX_INT_M
;
1565 if (flag
== ENABLE_INTRS
) {
1566 temp64
= readq(&bar0
->general_int_mask
);
1567 temp64
&= ~((u64
) val64
);
1568 writeq(temp64
, &bar0
->general_int_mask
);
1570 * If Hercules adapter enable GPIO otherwise
1571 * disabled all PCIX, Flash, MDIO, IIC and GPIO
1572 * interrupts for now.
1575 if (s2io_link_fault_indication(nic
) ==
1576 LINK_UP_DOWN_INTERRUPT
) {
1577 temp64
= readq(&bar0
->pic_int_mask
);
1578 temp64
&= ~((u64
) PIC_INT_GPIO
);
1579 writeq(temp64
, &bar0
->pic_int_mask
);
1580 temp64
= readq(&bar0
->gpio_int_mask
);
1581 temp64
&= ~((u64
) GPIO_INT_MASK_LINK_UP
);
1582 writeq(temp64
, &bar0
->gpio_int_mask
);
1584 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1587 * No MSI Support is available presently, so TTI and
1588 * RTI interrupts are also disabled.
1590 } else if (flag
== DISABLE_INTRS
) {
1592 * Disable PIC Intrs in the general
1593 * intr mask register
1595 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1596 temp64
= readq(&bar0
->general_int_mask
);
1598 writeq(val64
, &bar0
->general_int_mask
);
1602 /* DMA Interrupts */
1603 /* Enabling/Disabling Tx DMA interrupts */
1604 if (mask
& TX_DMA_INTR
) {
1605 /* Enable TxDMA Intrs in the general intr mask register */
1606 val64
= TXDMA_INT_M
;
1607 if (flag
== ENABLE_INTRS
) {
1608 temp64
= readq(&bar0
->general_int_mask
);
1609 temp64
&= ~((u64
) val64
);
1610 writeq(temp64
, &bar0
->general_int_mask
);
1612 * Keep all interrupts other than PFC interrupt
1613 * and PCC interrupt disabled in DMA level.
1615 val64
= DISABLE_ALL_INTRS
& ~(TXDMA_PFC_INT_M
|
1617 writeq(val64
, &bar0
->txdma_int_mask
);
1619 * Enable only the MISC error 1 interrupt in PFC block
1621 val64
= DISABLE_ALL_INTRS
& (~PFC_MISC_ERR_1
);
1622 writeq(val64
, &bar0
->pfc_err_mask
);
1624 * Enable only the FB_ECC error interrupt in PCC block
1626 val64
= DISABLE_ALL_INTRS
& (~PCC_FB_ECC_ERR
);
1627 writeq(val64
, &bar0
->pcc_err_mask
);
1628 } else if (flag
== DISABLE_INTRS
) {
1630 * Disable TxDMA Intrs in the general intr mask
1633 writeq(DISABLE_ALL_INTRS
, &bar0
->txdma_int_mask
);
1634 writeq(DISABLE_ALL_INTRS
, &bar0
->pfc_err_mask
);
1635 temp64
= readq(&bar0
->general_int_mask
);
1637 writeq(val64
, &bar0
->general_int_mask
);
1641 /* Enabling/Disabling Rx DMA interrupts */
1642 if (mask
& RX_DMA_INTR
) {
1643 /* Enable RxDMA Intrs in the general intr mask register */
1644 val64
= RXDMA_INT_M
;
1645 if (flag
== ENABLE_INTRS
) {
1646 temp64
= readq(&bar0
->general_int_mask
);
1647 temp64
&= ~((u64
) val64
);
1648 writeq(temp64
, &bar0
->general_int_mask
);
1650 * All RxDMA block interrupts are disabled for now
1653 writeq(DISABLE_ALL_INTRS
, &bar0
->rxdma_int_mask
);
1654 } else if (flag
== DISABLE_INTRS
) {
1656 * Disable RxDMA Intrs in the general intr mask
1659 writeq(DISABLE_ALL_INTRS
, &bar0
->rxdma_int_mask
);
1660 temp64
= readq(&bar0
->general_int_mask
);
1662 writeq(val64
, &bar0
->general_int_mask
);
1666 /* MAC Interrupts */
1667 /* Enabling/Disabling MAC interrupts */
1668 if (mask
& (TX_MAC_INTR
| RX_MAC_INTR
)) {
1669 val64
= TXMAC_INT_M
| RXMAC_INT_M
;
1670 if (flag
== ENABLE_INTRS
) {
1671 temp64
= readq(&bar0
->general_int_mask
);
1672 temp64
&= ~((u64
) val64
);
1673 writeq(temp64
, &bar0
->general_int_mask
);
1675 * All MAC block error interrupts are disabled for now
1678 } else if (flag
== DISABLE_INTRS
) {
1680 * Disable MAC Intrs in the general intr mask register
1682 writeq(DISABLE_ALL_INTRS
, &bar0
->mac_int_mask
);
1683 writeq(DISABLE_ALL_INTRS
,
1684 &bar0
->mac_rmac_err_mask
);
1686 temp64
= readq(&bar0
->general_int_mask
);
1688 writeq(val64
, &bar0
->general_int_mask
);
1692 /* XGXS Interrupts */
1693 if (mask
& (TX_XGXS_INTR
| RX_XGXS_INTR
)) {
1694 val64
= TXXGXS_INT_M
| RXXGXS_INT_M
;
1695 if (flag
== ENABLE_INTRS
) {
1696 temp64
= readq(&bar0
->general_int_mask
);
1697 temp64
&= ~((u64
) val64
);
1698 writeq(temp64
, &bar0
->general_int_mask
);
1700 * All XGXS block error interrupts are disabled for now
1703 writeq(DISABLE_ALL_INTRS
, &bar0
->xgxs_int_mask
);
1704 } else if (flag
== DISABLE_INTRS
) {
1706 * Disable MC Intrs in the general intr mask register
1708 writeq(DISABLE_ALL_INTRS
, &bar0
->xgxs_int_mask
);
1709 temp64
= readq(&bar0
->general_int_mask
);
1711 writeq(val64
, &bar0
->general_int_mask
);
1715 /* Memory Controller(MC) interrupts */
1716 if (mask
& MC_INTR
) {
1718 if (flag
== ENABLE_INTRS
) {
1719 temp64
= readq(&bar0
->general_int_mask
);
1720 temp64
&= ~((u64
) val64
);
1721 writeq(temp64
, &bar0
->general_int_mask
);
1723 * Enable all MC Intrs.
1725 writeq(0x0, &bar0
->mc_int_mask
);
1726 writeq(0x0, &bar0
->mc_err_mask
);
1727 } else if (flag
== DISABLE_INTRS
) {
1729 * Disable MC Intrs in the general intr mask register
1731 writeq(DISABLE_ALL_INTRS
, &bar0
->mc_int_mask
);
1732 temp64
= readq(&bar0
->general_int_mask
);
1734 writeq(val64
, &bar0
->general_int_mask
);
1739 /* Tx traffic interrupts */
1740 if (mask
& TX_TRAFFIC_INTR
) {
1741 val64
= TXTRAFFIC_INT_M
;
1742 if (flag
== ENABLE_INTRS
) {
1743 temp64
= readq(&bar0
->general_int_mask
);
1744 temp64
&= ~((u64
) val64
);
1745 writeq(temp64
, &bar0
->general_int_mask
);
1747 * Enable all the Tx side interrupts
1748 * writing 0 Enables all 64 TX interrupt levels
1750 writeq(0x0, &bar0
->tx_traffic_mask
);
1751 } else if (flag
== DISABLE_INTRS
) {
1753 * Disable Tx Traffic Intrs in the general intr mask
1756 writeq(DISABLE_ALL_INTRS
, &bar0
->tx_traffic_mask
);
1757 temp64
= readq(&bar0
->general_int_mask
);
1759 writeq(val64
, &bar0
->general_int_mask
);
1763 /* Rx traffic interrupts */
1764 if (mask
& RX_TRAFFIC_INTR
) {
1765 val64
= RXTRAFFIC_INT_M
;
1766 if (flag
== ENABLE_INTRS
) {
1767 temp64
= readq(&bar0
->general_int_mask
);
1768 temp64
&= ~((u64
) val64
);
1769 writeq(temp64
, &bar0
->general_int_mask
);
1770 /* writing 0 Enables all 8 RX interrupt levels */
1771 writeq(0x0, &bar0
->rx_traffic_mask
);
1772 } else if (flag
== DISABLE_INTRS
) {
1774 * Disable Rx Traffic Intrs in the general intr mask
1777 writeq(DISABLE_ALL_INTRS
, &bar0
->rx_traffic_mask
);
1778 temp64
= readq(&bar0
->general_int_mask
);
1780 writeq(val64
, &bar0
->general_int_mask
);
1785 static int check_prc_pcc_state(u64 val64
, int flag
, int rev_id
, int herc
)
1789 if (flag
== FALSE
) {
1790 if ((!herc
&& (rev_id
>= 4)) || herc
) {
1791 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) &&
1792 ((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
1793 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
1797 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) &&
1798 ((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
1799 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
1804 if ((!herc
&& (rev_id
>= 4)) || herc
) {
1805 if (((val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) ==
1806 ADAPTER_STATUS_RMAC_PCC_IDLE
) &&
1807 (!(val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ||
1808 ((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
1809 ADAPTER_STATUS_RC_PRC_QUIESCENT
))) {
1813 if (((val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) ==
1814 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) &&
1815 (!(val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ||
1816 ((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
1817 ADAPTER_STATUS_RC_PRC_QUIESCENT
))) {
1826 * verify_xena_quiescence - Checks whether the H/W is ready
1827 * @val64 : Value read from adapter status register.
1828 * @flag : indicates if the adapter enable bit was ever written once
1830 * Description: Returns whether the H/W is ready to go or not. Depending
1831 * on whether adapter enable bit was written or not the comparison
1832 * differs and the calling function passes the input argument flag to
1834 * Return: 1 If xena is quiescence
1835 * 0 If Xena is not quiescence
1838 static int verify_xena_quiescence(nic_t
*sp
, u64 val64
, int flag
)
1841 u64 tmp64
= ~((u64
) val64
);
1842 int rev_id
= get_xena_rev_id(sp
->pdev
);
1844 herc
= (sp
->device_type
== XFRAME_II_DEVICE
);
1847 (ADAPTER_STATUS_TDMA_READY
| ADAPTER_STATUS_RDMA_READY
|
1848 ADAPTER_STATUS_PFC_READY
| ADAPTER_STATUS_TMAC_BUF_EMPTY
|
1849 ADAPTER_STATUS_PIC_QUIESCENT
| ADAPTER_STATUS_MC_DRAM_READY
|
1850 ADAPTER_STATUS_MC_QUEUES_READY
| ADAPTER_STATUS_M_PLL_LOCK
|
1851 ADAPTER_STATUS_P_PLL_LOCK
))) {
1852 ret
= check_prc_pcc_state(val64
, flag
, rev_id
, herc
);
1859 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1860 * @sp: Pointer to device specifc structure
1862 * New procedure to clear mac address reading problems on Alpha platforms
1866 static void fix_mac_address(nic_t
* sp
)
1868 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
1872 while (fix_mac
[i
] != END_SIGN
) {
1873 writeq(fix_mac
[i
++], &bar0
->gpio_control
);
1875 val64
= readq(&bar0
->gpio_control
);
1880 * start_nic - Turns the device on
1881 * @nic : device private variable.
1883 * This function actually turns the device on. Before this function is
1884 * called,all Registers are configured from their reset states
1885 * and shared memory is allocated but the NIC is still quiescent. On
1886 * calling this function, the device interrupts are cleared and the NIC is
1887 * literally switched on by writing into the adapter control register.
1889 * SUCCESS on success and -1 on failure.
1892 static int start_nic(struct s2io_nic
*nic
)
1894 XENA_dev_config_t __iomem
*bar0
= nic
->bar0
;
1895 struct net_device
*dev
= nic
->dev
;
1896 register u64 val64
= 0;
1899 mac_info_t
*mac_control
;
1900 struct config_param
*config
;
1902 mac_control
= &nic
->mac_control
;
1903 config
= &nic
->config
;
1905 /* PRC Initialization and configuration */
1906 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1907 writeq((u64
) mac_control
->rings
[i
].rx_blocks
[0].block_dma_addr
,
1908 &bar0
->prc_rxd0_n
[i
]);
1910 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
1911 if (nic
->config
.bimodal
)
1912 val64
|= PRC_CTRL_BIMODAL_INTERRUPT
;
1913 if (nic
->rxd_mode
== RXD_MODE_1
)
1914 val64
|= PRC_CTRL_RC_ENABLED
;
1916 val64
|= PRC_CTRL_RC_ENABLED
| PRC_CTRL_RING_MODE_3
;
1917 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
1920 if (nic
->rxd_mode
== RXD_MODE_3B
) {
1921 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1922 val64
= readq(&bar0
->rx_pa_cfg
);
1923 val64
|= RX_PA_CFG_IGNORE_L2_ERR
;
1924 writeq(val64
, &bar0
->rx_pa_cfg
);
1928 * Enabling MC-RLDRAM. After enabling the device, we timeout
1929 * for around 100ms, which is approximately the time required
1930 * for the device to be ready for operation.
1932 val64
= readq(&bar0
->mc_rldram_mrs
);
1933 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
| MC_RLDRAM_MRS_ENABLE
;
1934 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
1935 val64
= readq(&bar0
->mc_rldram_mrs
);
1937 msleep(100); /* Delay by around 100 ms. */
1939 /* Enabling ECC Protection. */
1940 val64
= readq(&bar0
->adapter_control
);
1941 val64
&= ~ADAPTER_ECC_EN
;
1942 writeq(val64
, &bar0
->adapter_control
);
1945 * Clearing any possible Link state change interrupts that
1946 * could have popped up just before Enabling the card.
1948 val64
= readq(&bar0
->mac_rmac_err_reg
);
1950 writeq(val64
, &bar0
->mac_rmac_err_reg
);
1953 * Verify if the device is ready to be enabled, if so enable
1956 val64
= readq(&bar0
->adapter_status
);
1957 if (!verify_xena_quiescence(nic
, val64
, nic
->device_enabled_once
)) {
1958 DBG_PRINT(ERR_DBG
, "%s: device is not ready, ", dev
->name
);
1959 DBG_PRINT(ERR_DBG
, "Adapter status reads: 0x%llx\n",
1960 (unsigned long long) val64
);
1964 /* Enable select interrupts */
1965 if (nic
->intr_type
!= INTA
)
1966 en_dis_able_nic_intrs(nic
, ENA_ALL_INTRS
, DISABLE_INTRS
);
1968 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
1969 interruptible
|= TX_PIC_INTR
| RX_PIC_INTR
;
1970 interruptible
|= TX_MAC_INTR
| RX_MAC_INTR
;
1971 en_dis_able_nic_intrs(nic
, interruptible
, ENABLE_INTRS
);
1975 * With some switches, link might be already up at this point.
1976 * Because of this weird behavior, when we enable laser,
1977 * we may not get link. We need to handle this. We cannot
1978 * figure out which switch is misbehaving. So we are forced to
1979 * make a global change.
1982 /* Enabling Laser. */
1983 val64
= readq(&bar0
->adapter_control
);
1984 val64
|= ADAPTER_EOI_TX_ON
;
1985 writeq(val64
, &bar0
->adapter_control
);
1987 /* SXE-002: Initialize link and activity LED */
1988 subid
= nic
->pdev
->subsystem_device
;
1989 if (((subid
& 0xFF) >= 0x07) &&
1990 (nic
->device_type
== XFRAME_I_DEVICE
)) {
1991 val64
= readq(&bar0
->gpio_control
);
1992 val64
|= 0x0000800000000000ULL
;
1993 writeq(val64
, &bar0
->gpio_control
);
1994 val64
= 0x0411040400000000ULL
;
1995 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
1999 * Don't see link state interrupts on certain switches, so
2000 * directly scheduling a link state task from here.
2002 schedule_work(&nic
->set_link_task
);
2008 * free_tx_buffers - Free all queued Tx buffers
2009 * @nic : device private variable.
2011 * Free all queued Tx buffers.
2012 * Return Value: void
2015 static void free_tx_buffers(struct s2io_nic
*nic
)
2017 struct net_device
*dev
= nic
->dev
;
2018 struct sk_buff
*skb
;
2021 mac_info_t
*mac_control
;
2022 struct config_param
*config
;
2023 int cnt
= 0, frg_cnt
;
2025 mac_control
= &nic
->mac_control
;
2026 config
= &nic
->config
;
2028 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
2029 for (j
= 0; j
< config
->tx_cfg
[i
].fifo_len
- 1; j
++) {
2030 txdp
= (TxD_t
*) mac_control
->fifos
[i
].list_info
[j
].
2033 (struct sk_buff
*) ((unsigned long) txdp
->
2036 memset(txdp
, 0, sizeof(TxD_t
) *
2040 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2041 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2042 txdp
->Buffer_Pointer
,
2043 skb
->len
- skb
->data_len
,
2049 for (j
= 0; j
< frg_cnt
; j
++, txdp
++) {
2051 &skb_shinfo(skb
)->frags
[j
];
2052 pci_unmap_page(nic
->pdev
,
2062 memset(txdp
, 0, sizeof(TxD_t
) * config
->max_txds
);
2066 "%s:forcibly freeing %d skbs on FIFO%d\n",
2068 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
2069 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
2074 * stop_nic - To stop the nic
2075 * @nic ; device private variable.
2077 * This function does exactly the opposite of what the start_nic()
2078 * function does. This function is called to stop the device.
2083 static void stop_nic(struct s2io_nic
*nic
)
2085 XENA_dev_config_t __iomem
*bar0
= nic
->bar0
;
2086 register u64 val64
= 0;
2087 u16 interruptible
, i
;
2088 mac_info_t
*mac_control
;
2089 struct config_param
*config
;
2091 mac_control
= &nic
->mac_control
;
2092 config
= &nic
->config
;
2094 /* Disable all interrupts */
2095 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
2096 interruptible
|= TX_PIC_INTR
| RX_PIC_INTR
;
2097 interruptible
|= TX_MAC_INTR
| RX_MAC_INTR
;
2098 en_dis_able_nic_intrs(nic
, interruptible
, DISABLE_INTRS
);
2101 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2102 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
2103 val64
&= ~((u64
) PRC_CTRL_RC_ENABLED
);
2104 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
2108 int fill_rxd_3buf(nic_t
*nic
, RxD_t
*rxdp
, struct sk_buff
*skb
)
2110 struct net_device
*dev
= nic
->dev
;
2111 struct sk_buff
*frag_list
;
2114 /* Buffer-1 receives L3/L4 headers */
2115 ((RxD3_t
*)rxdp
)->Buffer1_ptr
= pci_map_single
2116 (nic
->pdev
, skb
->data
, l3l4hdr_size
+ 4,
2117 PCI_DMA_FROMDEVICE
);
2119 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2120 skb_shinfo(skb
)->frag_list
= dev_alloc_skb(dev
->mtu
+ ALIGN_SIZE
);
2121 if (skb_shinfo(skb
)->frag_list
== NULL
) {
2122 DBG_PRINT(ERR_DBG
, "%s: dev_alloc_skb failed\n ", dev
->name
);
2125 frag_list
= skb_shinfo(skb
)->frag_list
;
2126 frag_list
->next
= NULL
;
2127 tmp
= (void *)ALIGN((long)frag_list
->data
, ALIGN_SIZE
+ 1);
2128 frag_list
->data
= tmp
;
2129 frag_list
->tail
= tmp
;
2131 /* Buffer-2 receives L4 data payload */
2132 ((RxD3_t
*)rxdp
)->Buffer2_ptr
= pci_map_single(nic
->pdev
,
2133 frag_list
->data
, dev
->mtu
,
2134 PCI_DMA_FROMDEVICE
);
2135 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(l3l4hdr_size
+ 4);
2136 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3(dev
->mtu
);
2142 * fill_rx_buffers - Allocates the Rx side skbs
2143 * @nic: device private variable
2144 * @ring_no: ring number
2146 * The function allocates Rx side skbs and puts the physical
2147 * address of these buffers into the RxD buffer pointers, so that the NIC
2148 * can DMA the received frame into these locations.
2149 * The NIC supports 3 receive modes, viz
2151 * 2. three buffer and
2152 * 3. Five buffer modes.
2153 * Each mode defines how many fragments the received frame will be split
2154 * up into by the NIC. The frame is split into L3 header, L4 Header,
2155 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2156 * is split into 3 fragments. As of now only single buffer mode is
2159 * SUCCESS on success or an appropriate -ve value on failure.
2162 static int fill_rx_buffers(struct s2io_nic
*nic
, int ring_no
)
2164 struct net_device
*dev
= nic
->dev
;
2165 struct sk_buff
*skb
;
2167 int off
, off1
, size
, block_no
, block_no1
;
2170 mac_info_t
*mac_control
;
2171 struct config_param
*config
;
2174 #ifndef CONFIG_S2IO_NAPI
2175 unsigned long flags
;
2177 RxD_t
*first_rxdp
= NULL
;
2179 mac_control
= &nic
->mac_control
;
2180 config
= &nic
->config
;
2181 alloc_cnt
= mac_control
->rings
[ring_no
].pkt_cnt
-
2182 atomic_read(&nic
->rx_bufs_left
[ring_no
]);
2184 while (alloc_tab
< alloc_cnt
) {
2185 block_no
= mac_control
->rings
[ring_no
].rx_curr_put_info
.
2187 block_no1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.
2189 off
= mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
;
2190 off1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.offset
;
2192 rxdp
= mac_control
->rings
[ring_no
].
2193 rx_blocks
[block_no
].rxds
[off
].virt_addr
;
2195 if ((block_no
== block_no1
) && (off
== off1
) &&
2196 (rxdp
->Host_Control
)) {
2197 DBG_PRINT(INTR_DBG
, "%s: Get and Put",
2199 DBG_PRINT(INTR_DBG
, " info equated\n");
2202 if (off
&& (off
== rxd_count
[nic
->rxd_mode
])) {
2203 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2205 if (mac_control
->rings
[ring_no
].rx_curr_put_info
.
2206 block_index
== mac_control
->rings
[ring_no
].
2208 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2210 block_no
= mac_control
->rings
[ring_no
].
2211 rx_curr_put_info
.block_index
;
2212 if (off
== rxd_count
[nic
->rxd_mode
])
2214 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2216 rxdp
= mac_control
->rings
[ring_no
].
2217 rx_blocks
[block_no
].block_virt_addr
;
2218 DBG_PRINT(INTR_DBG
, "%s: Next block at: %p\n",
2221 #ifndef CONFIG_S2IO_NAPI
2222 spin_lock_irqsave(&nic
->put_lock
, flags
);
2223 mac_control
->rings
[ring_no
].put_pos
=
2224 (block_no
* (rxd_count
[nic
->rxd_mode
] + 1)) + off
;
2225 spin_unlock_irqrestore(&nic
->put_lock
, flags
);
2227 if ((rxdp
->Control_1
& RXD_OWN_XENA
) &&
2228 ((nic
->rxd_mode
>= RXD_MODE_3A
) &&
2229 (rxdp
->Control_2
& BIT(0)))) {
2230 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2234 /* calculate size of skb based on ring mode */
2235 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
2236 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
2237 if (nic
->rxd_mode
== RXD_MODE_1
)
2238 size
+= NET_IP_ALIGN
;
2239 else if (nic
->rxd_mode
== RXD_MODE_3B
)
2240 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2242 size
= l3l4hdr_size
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2245 skb
= dev_alloc_skb(size
);
2247 DBG_PRINT(ERR_DBG
, "%s: Out of ", dev
->name
);
2248 DBG_PRINT(ERR_DBG
, "memory to allocate SKBs\n");
2251 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2255 if (nic
->rxd_mode
== RXD_MODE_1
) {
2256 /* 1 buffer mode - normal operation mode */
2257 memset(rxdp
, 0, sizeof(RxD1_t
));
2258 skb_reserve(skb
, NET_IP_ALIGN
);
2259 ((RxD1_t
*)rxdp
)->Buffer0_ptr
= pci_map_single
2260 (nic
->pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
2261 rxdp
->Control_2
&= (~MASK_BUFFER0_SIZE_1
);
2262 rxdp
->Control_2
|= SET_BUFFER0_SIZE_1(size
);
2264 } else if (nic
->rxd_mode
>= RXD_MODE_3A
) {
2266 * 2 or 3 buffer mode -
2267 * Both 2 buffer mode and 3 buffer mode provides 128
2268 * byte aligned receive buffers.
2270 * 3 buffer mode provides header separation where in
2271 * skb->data will have L3/L4 headers where as
2272 * skb_shinfo(skb)->frag_list will have the L4 data
2276 memset(rxdp
, 0, sizeof(RxD3_t
));
2277 ba
= &mac_control
->rings
[ring_no
].ba
[block_no
][off
];
2278 skb_reserve(skb
, BUF0_LEN
);
2279 tmp
= (u64
)(unsigned long) skb
->data
;
2282 skb
->data
= (void *) (unsigned long)tmp
;
2283 skb
->tail
= (void *) (unsigned long)tmp
;
2285 ((RxD3_t
*)rxdp
)->Buffer0_ptr
=
2286 pci_map_single(nic
->pdev
, ba
->ba_0
, BUF0_LEN
,
2287 PCI_DMA_FROMDEVICE
);
2288 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
2289 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2290 /* Two buffer mode */
2293 * Buffer2 will have L3/L4 header plus
2296 ((RxD3_t
*)rxdp
)->Buffer2_ptr
= pci_map_single
2297 (nic
->pdev
, skb
->data
, dev
->mtu
+ 4,
2298 PCI_DMA_FROMDEVICE
);
2300 /* Buffer-1 will be dummy buffer not used */
2301 ((RxD3_t
*)rxdp
)->Buffer1_ptr
=
2302 pci_map_single(nic
->pdev
, ba
->ba_1
, BUF1_LEN
,
2303 PCI_DMA_FROMDEVICE
);
2304 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
2305 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3
2309 if (fill_rxd_3buf(nic
, rxdp
, skb
) == -ENOMEM
) {
2310 dev_kfree_skb_irq(skb
);
2313 first_rxdp
->Control_1
|=
2319 rxdp
->Control_2
|= BIT(0);
2321 rxdp
->Host_Control
= (unsigned long) (skb
);
2322 if (alloc_tab
& ((1 << rxsync_frequency
) - 1))
2323 rxdp
->Control_1
|= RXD_OWN_XENA
;
2325 if (off
== (rxd_count
[nic
->rxd_mode
] + 1))
2327 mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
= off
;
2329 rxdp
->Control_2
|= SET_RXD_MARKER
;
2330 if (!(alloc_tab
& ((1 << rxsync_frequency
) - 1))) {
2333 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2337 atomic_inc(&nic
->rx_bufs_left
[ring_no
]);
2342 /* Transfer ownership of first descriptor to adapter just before
2343 * exiting. Before that, use memory barrier so that ownership
2344 * and other fields are seen by adapter correctly.
2348 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2354 static void free_rxd_blk(struct s2io_nic
*sp
, int ring_no
, int blk
)
2356 struct net_device
*dev
= sp
->dev
;
2358 struct sk_buff
*skb
;
2360 mac_info_t
*mac_control
;
2363 mac_control
= &sp
->mac_control
;
2364 for (j
= 0 ; j
< rxd_count
[sp
->rxd_mode
]; j
++) {
2365 rxdp
= mac_control
->rings
[ring_no
].
2366 rx_blocks
[blk
].rxds
[j
].virt_addr
;
2367 skb
= (struct sk_buff
*)
2368 ((unsigned long) rxdp
->Host_Control
);
2372 if (sp
->rxd_mode
== RXD_MODE_1
) {
2373 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2374 ((RxD1_t
*)rxdp
)->Buffer0_ptr
,
2376 HEADER_ETHERNET_II_802_3_SIZE
2377 + HEADER_802_2_SIZE
+
2379 PCI_DMA_FROMDEVICE
);
2380 memset(rxdp
, 0, sizeof(RxD1_t
));
2381 } else if(sp
->rxd_mode
== RXD_MODE_3B
) {
2382 ba
= &mac_control
->rings
[ring_no
].
2384 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2385 ((RxD3_t
*)rxdp
)->Buffer0_ptr
,
2387 PCI_DMA_FROMDEVICE
);
2388 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2389 ((RxD3_t
*)rxdp
)->Buffer1_ptr
,
2391 PCI_DMA_FROMDEVICE
);
2392 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2393 ((RxD3_t
*)rxdp
)->Buffer2_ptr
,
2395 PCI_DMA_FROMDEVICE
);
2396 memset(rxdp
, 0, sizeof(RxD3_t
));
2398 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2399 ((RxD3_t
*)rxdp
)->Buffer0_ptr
, BUF0_LEN
,
2400 PCI_DMA_FROMDEVICE
);
2401 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2402 ((RxD3_t
*)rxdp
)->Buffer1_ptr
,
2404 PCI_DMA_FROMDEVICE
);
2405 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2406 ((RxD3_t
*)rxdp
)->Buffer2_ptr
, dev
->mtu
,
2407 PCI_DMA_FROMDEVICE
);
2408 memset(rxdp
, 0, sizeof(RxD3_t
));
2411 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
2416 * free_rx_buffers - Frees all Rx buffers
2417 * @sp: device private variable.
2419 * This function will free all Rx buffers allocated by host.
2424 static void free_rx_buffers(struct s2io_nic
*sp
)
2426 struct net_device
*dev
= sp
->dev
;
2427 int i
, blk
= 0, buf_cnt
= 0;
2428 mac_info_t
*mac_control
;
2429 struct config_param
*config
;
2431 mac_control
= &sp
->mac_control
;
2432 config
= &sp
->config
;
2434 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2435 for (blk
= 0; blk
< rx_ring_sz
[i
]; blk
++)
2436 free_rxd_blk(sp
,i
,blk
);
2438 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
2439 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
2440 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
2441 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
2442 atomic_set(&sp
->rx_bufs_left
[i
], 0);
2443 DBG_PRINT(INIT_DBG
, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2444 dev
->name
, buf_cnt
, i
);
2449 * s2io_poll - Rx interrupt handler for NAPI support
2450 * @dev : pointer to the device structure.
2451 * @budget : The number of packets that were budgeted to be processed
2452 * during one pass through the 'Poll" function.
2454 * Comes into picture only if NAPI support has been incorporated. It does
2455 * the same thing that rx_intr_handler does, but not in a interrupt context
2456 * also It will process only a given number of packets.
2458 * 0 on success and 1 if there are No Rx packets to be processed.
2461 #if defined(CONFIG_S2IO_NAPI)
2462 static int s2io_poll(struct net_device
*dev
, int *budget
)
2464 nic_t
*nic
= dev
->priv
;
2465 int pkt_cnt
= 0, org_pkts_to_process
;
2466 mac_info_t
*mac_control
;
2467 struct config_param
*config
;
2468 XENA_dev_config_t __iomem
*bar0
= nic
->bar0
;
2472 atomic_inc(&nic
->isr_cnt
);
2473 mac_control
= &nic
->mac_control
;
2474 config
= &nic
->config
;
2476 nic
->pkts_to_process
= *budget
;
2477 if (nic
->pkts_to_process
> dev
->quota
)
2478 nic
->pkts_to_process
= dev
->quota
;
2479 org_pkts_to_process
= nic
->pkts_to_process
;
2481 val64
= readq(&bar0
->rx_traffic_int
);
2482 writeq(val64
, &bar0
->rx_traffic_int
);
2484 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2485 rx_intr_handler(&mac_control
->rings
[i
]);
2486 pkt_cnt
= org_pkts_to_process
- nic
->pkts_to_process
;
2487 if (!nic
->pkts_to_process
) {
2488 /* Quota for the current iteration has been met */
2495 dev
->quota
-= pkt_cnt
;
2497 netif_rx_complete(dev
);
2499 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2500 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2501 DBG_PRINT(ERR_DBG
, "%s:Out of memory", dev
->name
);
2502 DBG_PRINT(ERR_DBG
, " in Rx Poll!!\n");
2506 /* Re enable the Rx interrupts. */
2507 en_dis_able_nic_intrs(nic
, RX_TRAFFIC_INTR
, ENABLE_INTRS
);
2508 atomic_dec(&nic
->isr_cnt
);
2512 dev
->quota
-= pkt_cnt
;
2515 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2516 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2517 DBG_PRINT(ERR_DBG
, "%s:Out of memory", dev
->name
);
2518 DBG_PRINT(ERR_DBG
, " in Rx Poll!!\n");
2522 atomic_dec(&nic
->isr_cnt
);
2528 * rx_intr_handler - Rx interrupt handler
2529 * @nic: device private variable.
2531 * If the interrupt is because of a received frame or if the
2532 * receive ring contains fresh as yet un-processed frames,this function is
2533 * called. It picks out the RxD at which place the last Rx processing had
2534 * stopped and sends the skb to the OSM's Rx handler and then increments
2539 static void rx_intr_handler(ring_info_t
*ring_data
)
2541 nic_t
*nic
= ring_data
->nic
;
2542 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2543 int get_block
, put_block
, put_offset
;
2544 rx_curr_get_info_t get_info
, put_info
;
2546 struct sk_buff
*skb
;
2547 #ifndef CONFIG_S2IO_NAPI
2550 spin_lock(&nic
->rx_lock
);
2551 if (atomic_read(&nic
->card_state
) == CARD_DOWN
) {
2552 DBG_PRINT(INTR_DBG
, "%s: %s going down for reset\n",
2553 __FUNCTION__
, dev
->name
);
2554 spin_unlock(&nic
->rx_lock
);
2558 get_info
= ring_data
->rx_curr_get_info
;
2559 get_block
= get_info
.block_index
;
2560 put_info
= ring_data
->rx_curr_put_info
;
2561 put_block
= put_info
.block_index
;
2562 rxdp
= ring_data
->rx_blocks
[get_block
].rxds
[get_info
.offset
].virt_addr
;
2563 #ifndef CONFIG_S2IO_NAPI
2564 spin_lock(&nic
->put_lock
);
2565 put_offset
= ring_data
->put_pos
;
2566 spin_unlock(&nic
->put_lock
);
2568 put_offset
= (put_block
* (rxd_count
[nic
->rxd_mode
] + 1)) +
2571 while (RXD_IS_UP2DT(rxdp
)) {
2572 /* If your are next to put index then it's FIFO full condition */
2573 if ((get_block
== put_block
) &&
2574 (get_info
.offset
+ 1) == put_info
.offset
) {
2575 DBG_PRINT(ERR_DBG
, "%s: Ring Full\n",dev
->name
);
2578 skb
= (struct sk_buff
*) ((unsigned long)rxdp
->Host_Control
);
2580 DBG_PRINT(ERR_DBG
, "%s: The skb is ",
2582 DBG_PRINT(ERR_DBG
, "Null in Rx Intr\n");
2583 spin_unlock(&nic
->rx_lock
);
2586 if (nic
->rxd_mode
== RXD_MODE_1
) {
2587 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2588 ((RxD1_t
*)rxdp
)->Buffer0_ptr
,
2590 HEADER_ETHERNET_II_802_3_SIZE
+
2593 PCI_DMA_FROMDEVICE
);
2594 } else if (nic
->rxd_mode
== RXD_MODE_3B
) {
2595 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2596 ((RxD3_t
*)rxdp
)->Buffer0_ptr
,
2597 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2598 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2599 ((RxD3_t
*)rxdp
)->Buffer1_ptr
,
2600 BUF1_LEN
, PCI_DMA_FROMDEVICE
);
2601 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2602 ((RxD3_t
*)rxdp
)->Buffer2_ptr
,
2604 PCI_DMA_FROMDEVICE
);
2606 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2607 ((RxD3_t
*)rxdp
)->Buffer0_ptr
, BUF0_LEN
,
2608 PCI_DMA_FROMDEVICE
);
2609 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2610 ((RxD3_t
*)rxdp
)->Buffer1_ptr
,
2612 PCI_DMA_FROMDEVICE
);
2613 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2614 ((RxD3_t
*)rxdp
)->Buffer2_ptr
,
2615 dev
->mtu
, PCI_DMA_FROMDEVICE
);
2617 rx_osm_handler(ring_data
, rxdp
);
2619 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2620 rxdp
= ring_data
->rx_blocks
[get_block
].
2621 rxds
[get_info
.offset
].virt_addr
;
2622 if (get_info
.offset
== rxd_count
[nic
->rxd_mode
]) {
2623 get_info
.offset
= 0;
2624 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2626 if (get_block
== ring_data
->block_count
)
2628 ring_data
->rx_curr_get_info
.block_index
= get_block
;
2629 rxdp
= ring_data
->rx_blocks
[get_block
].block_virt_addr
;
2632 #ifdef CONFIG_S2IO_NAPI
2633 nic
->pkts_to_process
-= 1;
2634 if (!nic
->pkts_to_process
)
2638 if ((indicate_max_pkts
) && (pkt_cnt
> indicate_max_pkts
))
2642 spin_unlock(&nic
->rx_lock
);
2646 * tx_intr_handler - Transmit interrupt handler
2647 * @nic : device private variable
2649 * If an interrupt was raised to indicate DMA complete of the
2650 * Tx packet, this function is called. It identifies the last TxD
2651 * whose buffer was freed and frees all skbs whose data have already
2652 * DMA'ed into the NICs internal memory.
2657 static void tx_intr_handler(fifo_info_t
*fifo_data
)
2659 nic_t
*nic
= fifo_data
->nic
;
2660 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2661 tx_curr_get_info_t get_info
, put_info
;
2662 struct sk_buff
*skb
;
2666 get_info
= fifo_data
->tx_curr_get_info
;
2667 put_info
= fifo_data
->tx_curr_put_info
;
2668 txdlp
= (TxD_t
*) fifo_data
->list_info
[get_info
.offset
].
2670 while ((!(txdlp
->Control_1
& TXD_LIST_OWN_XENA
)) &&
2671 (get_info
.offset
!= put_info
.offset
) &&
2672 (txdlp
->Host_Control
)) {
2673 /* Check for TxD errors */
2674 if (txdlp
->Control_1
& TXD_T_CODE
) {
2675 unsigned long long err
;
2676 err
= txdlp
->Control_1
& TXD_T_CODE
;
2677 if ((err
>> 48) == 0xA) {
2678 DBG_PRINT(TX_DBG
, "TxD returned due \
2679 to loss of link\n");
2682 DBG_PRINT(ERR_DBG
, "***TxD error \
2687 skb
= (struct sk_buff
*) ((unsigned long)
2688 txdlp
->Host_Control
);
2690 DBG_PRINT(ERR_DBG
, "%s: Null skb ",
2692 DBG_PRINT(ERR_DBG
, "in Tx Free Intr\n");
2696 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2697 nic
->tx_pkt_count
++;
2699 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2700 txdlp
->Buffer_Pointer
,
2701 skb
->len
- skb
->data_len
,
2707 for (j
= 0; j
< frg_cnt
; j
++, txdlp
++) {
2709 &skb_shinfo(skb
)->frags
[j
];
2710 if (!txdlp
->Buffer_Pointer
)
2712 pci_unmap_page(nic
->pdev
,
2722 (sizeof(TxD_t
) * fifo_data
->max_txds
));
2724 /* Updating the statistics block */
2725 nic
->stats
.tx_bytes
+= skb
->len
;
2726 dev_kfree_skb_irq(skb
);
2729 get_info
.offset
%= get_info
.fifo_len
+ 1;
2730 txdlp
= (TxD_t
*) fifo_data
->list_info
2731 [get_info
.offset
].list_virt_addr
;
2732 fifo_data
->tx_curr_get_info
.offset
=
2736 spin_lock(&nic
->tx_lock
);
2737 if (netif_queue_stopped(dev
))
2738 netif_wake_queue(dev
);
2739 spin_unlock(&nic
->tx_lock
);
2743 * alarm_intr_handler - Alarm Interrrupt handler
2744 * @nic: device private variable
2745 * Description: If the interrupt was neither because of Rx packet or Tx
2746 * complete, this function is called. If the interrupt was to indicate
2747 * a loss of link, the OSM link status handler is invoked for any other
2748 * alarm interrupt the block that raised the interrupt is displayed
2749 * and a H/W reset is issued.
2754 static void alarm_intr_handler(struct s2io_nic
*nic
)
2756 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2757 XENA_dev_config_t __iomem
*bar0
= nic
->bar0
;
2758 register u64 val64
= 0, err_reg
= 0;
2760 /* Handling link status change error Intr */
2761 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
2762 err_reg
= readq(&bar0
->mac_rmac_err_reg
);
2763 writeq(err_reg
, &bar0
->mac_rmac_err_reg
);
2764 if (err_reg
& RMAC_LINK_STATE_CHANGE_INT
) {
2765 schedule_work(&nic
->set_link_task
);
2769 /* Handling Ecc errors */
2770 val64
= readq(&bar0
->mc_err_reg
);
2771 writeq(val64
, &bar0
->mc_err_reg
);
2772 if (val64
& (MC_ERR_REG_ECC_ALL_SNG
| MC_ERR_REG_ECC_ALL_DBL
)) {
2773 if (val64
& MC_ERR_REG_ECC_ALL_DBL
) {
2774 nic
->mac_control
.stats_info
->sw_stat
.
2776 DBG_PRINT(INIT_DBG
, "%s: Device indicates ",
2778 DBG_PRINT(INIT_DBG
, "double ECC error!!\n");
2779 if (nic
->device_type
!= XFRAME_II_DEVICE
) {
2780 /* Reset XframeI only if critical error */
2781 if (val64
& (MC_ERR_REG_MIRI_ECC_DB_ERR_0
|
2782 MC_ERR_REG_MIRI_ECC_DB_ERR_1
)) {
2783 netif_stop_queue(dev
);
2784 schedule_work(&nic
->rst_timer_task
);
2788 nic
->mac_control
.stats_info
->sw_stat
.
2793 /* In case of a serious error, the device will be Reset. */
2794 val64
= readq(&bar0
->serr_source
);
2795 if (val64
& SERR_SOURCE_ANY
) {
2796 DBG_PRINT(ERR_DBG
, "%s: Device indicates ", dev
->name
);
2797 DBG_PRINT(ERR_DBG
, "serious error %llx!!\n",
2798 (unsigned long long)val64
);
2799 netif_stop_queue(dev
);
2800 schedule_work(&nic
->rst_timer_task
);
2804 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2805 * Error occurs, the adapter will be recycled by disabling the
2806 * adapter enable bit and enabling it again after the device
2807 * becomes Quiescent.
2809 val64
= readq(&bar0
->pcc_err_reg
);
2810 writeq(val64
, &bar0
->pcc_err_reg
);
2811 if (val64
& PCC_FB_ECC_DB_ERR
) {
2812 u64 ac
= readq(&bar0
->adapter_control
);
2813 ac
&= ~(ADAPTER_CNTL_EN
);
2814 writeq(ac
, &bar0
->adapter_control
);
2815 ac
= readq(&bar0
->adapter_control
);
2816 schedule_work(&nic
->set_link_task
);
2819 /* Other type of interrupts are not being handled now, TODO */
2823 * wait_for_cmd_complete - waits for a command to complete.
2824 * @sp : private member of the device structure, which is a pointer to the
2825 * s2io_nic structure.
2826 * Description: Function that waits for a command to Write into RMAC
2827 * ADDR DATA registers to be completed and returns either success or
2828 * error depending on whether the command was complete or not.
2830 * SUCCESS on success and FAILURE on failure.
2833 static int wait_for_cmd_complete(nic_t
* sp
)
2835 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
2836 int ret
= FAILURE
, cnt
= 0;
2840 val64
= readq(&bar0
->rmac_addr_cmd_mem
);
2841 if (!(val64
& RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
)) {
2854 * s2io_reset - Resets the card.
2855 * @sp : private member of the device structure.
2856 * Description: Function to Reset the card. This function then also
2857 * restores the previously saved PCI configuration space registers as
2858 * the card reset also resets the configuration space.
2863 void s2io_reset(nic_t
* sp
)
2865 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
2869 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
2870 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, &(pci_cmd
));
2872 val64
= SW_RESET_ALL
;
2873 writeq(val64
, &bar0
->sw_reset
);
2876 * At this stage, if the PCI write is indeed completed, the
2877 * card is reset and so is the PCI Config space of the device.
2878 * So a read cannot be issued at this stage on any of the
2879 * registers to ensure the write into "sw_reset" register
2881 * Question: Is there any system call that will explicitly force
2882 * all the write commands still pending on the bus to be pushed
2884 * As of now I'am just giving a 250ms delay and hoping that the
2885 * PCI write to sw_reset register is done by this time.
2889 /* Restore the PCI state saved during initialization. */
2890 pci_restore_state(sp
->pdev
);
2891 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
2897 /* Set swapper to enable I/O register access */
2898 s2io_set_swapper(sp
);
2900 /* Restore the MSIX table entries from local variables */
2901 restore_xmsi_data(sp
);
2903 /* Clear certain PCI/PCI-X fields after reset */
2904 if (sp
->device_type
== XFRAME_II_DEVICE
) {
2905 /* Clear parity err detect bit */
2906 pci_write_config_word(sp
->pdev
, PCI_STATUS
, 0x8000);
2908 /* Clearing PCIX Ecc status register */
2909 pci_write_config_dword(sp
->pdev
, 0x68, 0x7C);
2911 /* Clearing PCI_STATUS error reflected here */
2912 writeq(BIT(62), &bar0
->txpic_int_reg
);
2915 /* Reset device statistics maintained by OS */
2916 memset(&sp
->stats
, 0, sizeof (struct net_device_stats
));
2918 /* SXE-002: Configure link and activity LED to turn it off */
2919 subid
= sp
->pdev
->subsystem_device
;
2920 if (((subid
& 0xFF) >= 0x07) &&
2921 (sp
->device_type
== XFRAME_I_DEVICE
)) {
2922 val64
= readq(&bar0
->gpio_control
);
2923 val64
|= 0x0000800000000000ULL
;
2924 writeq(val64
, &bar0
->gpio_control
);
2925 val64
= 0x0411040400000000ULL
;
2926 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
2930 * Clear spurious ECC interrupts that would have occured on
2931 * XFRAME II cards after reset.
2933 if (sp
->device_type
== XFRAME_II_DEVICE
) {
2934 val64
= readq(&bar0
->pcc_err_reg
);
2935 writeq(val64
, &bar0
->pcc_err_reg
);
2938 sp
->device_enabled_once
= FALSE
;
2942 * s2io_set_swapper - to set the swapper controle on the card
2943 * @sp : private member of the device structure,
2944 * pointer to the s2io_nic structure.
2945 * Description: Function to set the swapper control on the card
2946 * correctly depending on the 'endianness' of the system.
2948 * SUCCESS on success and FAILURE on failure.
2951 int s2io_set_swapper(nic_t
* sp
)
2953 struct net_device
*dev
= sp
->dev
;
2954 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
2955 u64 val64
, valt
, valr
;
2958 * Set proper endian settings and verify the same by reading
2959 * the PIF Feed-back register.
2962 val64
= readq(&bar0
->pif_rd_swapper_fb
);
2963 if (val64
!= 0x0123456789ABCDEFULL
) {
2965 u64 value
[] = { 0xC30000C3C30000C3ULL
, /* FE=1, SE=1 */
2966 0x8100008181000081ULL
, /* FE=1, SE=0 */
2967 0x4200004242000042ULL
, /* FE=0, SE=1 */
2968 0}; /* FE=0, SE=0 */
2971 writeq(value
[i
], &bar0
->swapper_ctrl
);
2972 val64
= readq(&bar0
->pif_rd_swapper_fb
);
2973 if (val64
== 0x0123456789ABCDEFULL
)
2978 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
2980 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
2981 (unsigned long long) val64
);
2986 valr
= readq(&bar0
->swapper_ctrl
);
2989 valt
= 0x0123456789ABCDEFULL
;
2990 writeq(valt
, &bar0
->xmsi_address
);
2991 val64
= readq(&bar0
->xmsi_address
);
2995 u64 value
[] = { 0x00C3C30000C3C300ULL
, /* FE=1, SE=1 */
2996 0x0081810000818100ULL
, /* FE=1, SE=0 */
2997 0x0042420000424200ULL
, /* FE=0, SE=1 */
2998 0}; /* FE=0, SE=0 */
3001 writeq((value
[i
] | valr
), &bar0
->swapper_ctrl
);
3002 writeq(valt
, &bar0
->xmsi_address
);
3003 val64
= readq(&bar0
->xmsi_address
);
3009 unsigned long long x
= val64
;
3010 DBG_PRINT(ERR_DBG
, "Write failed, Xmsi_addr ");
3011 DBG_PRINT(ERR_DBG
, "reads:0x%llx\n", x
);
3015 val64
= readq(&bar0
->swapper_ctrl
);
3016 val64
&= 0xFFFF000000000000ULL
;
3020 * The device by default set to a big endian format, so a
3021 * big endian driver need not set anything.
3023 val64
|= (SWAPPER_CTRL_TXP_FE
|
3024 SWAPPER_CTRL_TXP_SE
|
3025 SWAPPER_CTRL_TXD_R_FE
|
3026 SWAPPER_CTRL_TXD_W_FE
|
3027 SWAPPER_CTRL_TXF_R_FE
|
3028 SWAPPER_CTRL_RXD_R_FE
|
3029 SWAPPER_CTRL_RXD_W_FE
|
3030 SWAPPER_CTRL_RXF_W_FE
|
3031 SWAPPER_CTRL_XMSI_FE
|
3032 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3033 if (sp
->intr_type
== INTA
)
3034 val64
|= SWAPPER_CTRL_XMSI_SE
;
3035 writeq(val64
, &bar0
->swapper_ctrl
);
3038 * Initially we enable all bits to make it accessible by the
3039 * driver, then we selectively enable only those bits that
3042 val64
|= (SWAPPER_CTRL_TXP_FE
|
3043 SWAPPER_CTRL_TXP_SE
|
3044 SWAPPER_CTRL_TXD_R_FE
|
3045 SWAPPER_CTRL_TXD_R_SE
|
3046 SWAPPER_CTRL_TXD_W_FE
|
3047 SWAPPER_CTRL_TXD_W_SE
|
3048 SWAPPER_CTRL_TXF_R_FE
|
3049 SWAPPER_CTRL_RXD_R_FE
|
3050 SWAPPER_CTRL_RXD_R_SE
|
3051 SWAPPER_CTRL_RXD_W_FE
|
3052 SWAPPER_CTRL_RXD_W_SE
|
3053 SWAPPER_CTRL_RXF_W_FE
|
3054 SWAPPER_CTRL_XMSI_FE
|
3055 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3056 if (sp
->intr_type
== INTA
)
3057 val64
|= SWAPPER_CTRL_XMSI_SE
;
3058 writeq(val64
, &bar0
->swapper_ctrl
);
3060 val64
= readq(&bar0
->swapper_ctrl
);
3063 * Verifying if endian settings are accurate by reading a
3064 * feedback register.
3066 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3067 if (val64
!= 0x0123456789ABCDEFULL
) {
3068 /* Endian settings are incorrect, calls for another dekko. */
3069 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3071 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3072 (unsigned long long) val64
);
3079 static int wait_for_msix_trans(nic_t
*nic
, int i
)
3081 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
3083 int ret
= 0, cnt
= 0;
3086 val64
= readq(&bar0
->xmsi_access
);
3087 if (!(val64
& BIT(15)))
3093 DBG_PRINT(ERR_DBG
, "XMSI # %d Access failed\n", i
);
3100 void restore_xmsi_data(nic_t
*nic
)
3102 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
3106 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3107 writeq(nic
->msix_info
[i
].addr
, &bar0
->xmsi_address
);
3108 writeq(nic
->msix_info
[i
].data
, &bar0
->xmsi_data
);
3109 val64
= (BIT(7) | BIT(15) | vBIT(i
, 26, 6));
3110 writeq(val64
, &bar0
->xmsi_access
);
3111 if (wait_for_msix_trans(nic
, i
)) {
3112 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3118 static void store_xmsi_data(nic_t
*nic
)
3120 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
3121 u64 val64
, addr
, data
;
3124 /* Store and display */
3125 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3126 val64
= (BIT(15) | vBIT(i
, 26, 6));
3127 writeq(val64
, &bar0
->xmsi_access
);
3128 if (wait_for_msix_trans(nic
, i
)) {
3129 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3132 addr
= readq(&bar0
->xmsi_address
);
3133 data
= readq(&bar0
->xmsi_data
);
3135 nic
->msix_info
[i
].addr
= addr
;
3136 nic
->msix_info
[i
].data
= data
;
3141 int s2io_enable_msi(nic_t
*nic
)
3143 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
3144 u16 msi_ctrl
, msg_val
;
3145 struct config_param
*config
= &nic
->config
;
3146 struct net_device
*dev
= nic
->dev
;
3147 u64 val64
, tx_mat
, rx_mat
;
3150 val64
= readq(&bar0
->pic_control
);
3152 writeq(val64
, &bar0
->pic_control
);
3154 err
= pci_enable_msi(nic
->pdev
);
3156 DBG_PRINT(ERR_DBG
, "%s: enabling MSI failed\n",
3162 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3163 * for interrupt handling.
3165 pci_read_config_word(nic
->pdev
, 0x4c, &msg_val
);
3167 pci_write_config_word(nic
->pdev
, 0x4c, msg_val
);
3168 pci_read_config_word(nic
->pdev
, 0x4c, &msg_val
);
3170 pci_read_config_word(nic
->pdev
, 0x42, &msi_ctrl
);
3172 pci_write_config_word(nic
->pdev
, 0x42, msi_ctrl
);
3174 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3175 tx_mat
= readq(&bar0
->tx_mat0_n
[0]);
3176 for (i
=0; i
<config
->tx_fifo_num
; i
++) {
3177 tx_mat
|= TX_MAT_SET(i
, 1);
3179 writeq(tx_mat
, &bar0
->tx_mat0_n
[0]);
3181 rx_mat
= readq(&bar0
->rx_mat
);
3182 for (i
=0; i
<config
->rx_ring_num
; i
++) {
3183 rx_mat
|= RX_MAT_SET(i
, 1);
3185 writeq(rx_mat
, &bar0
->rx_mat
);
3187 dev
->irq
= nic
->pdev
->irq
;
3191 int s2io_enable_msi_x(nic_t
*nic
)
3193 XENA_dev_config_t
*bar0
= (XENA_dev_config_t
*) nic
->bar0
;
3195 u16 msi_control
; /* Temp variable */
3196 int ret
, i
, j
, msix_indx
= 1;
3198 nic
->entries
= kmalloc(MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
),
3200 if (nic
->entries
== NULL
) {
3201 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n", __FUNCTION__
);
3204 memset(nic
->entries
, 0, MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3207 kmalloc(MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
),
3209 if (nic
->s2io_entries
== NULL
) {
3210 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n", __FUNCTION__
);
3211 kfree(nic
->entries
);
3214 memset(nic
->s2io_entries
, 0,
3215 MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3217 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3218 nic
->entries
[i
].entry
= i
;
3219 nic
->s2io_entries
[i
].entry
= i
;
3220 nic
->s2io_entries
[i
].arg
= NULL
;
3221 nic
->s2io_entries
[i
].in_use
= 0;
3224 tx_mat
= readq(&bar0
->tx_mat0_n
[0]);
3225 for (i
=0; i
<nic
->config
.tx_fifo_num
; i
++, msix_indx
++) {
3226 tx_mat
|= TX_MAT_SET(i
, msix_indx
);
3227 nic
->s2io_entries
[msix_indx
].arg
= &nic
->mac_control
.fifos
[i
];
3228 nic
->s2io_entries
[msix_indx
].type
= MSIX_FIFO_TYPE
;
3229 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3231 writeq(tx_mat
, &bar0
->tx_mat0_n
[0]);
3233 if (!nic
->config
.bimodal
) {
3234 rx_mat
= readq(&bar0
->rx_mat
);
3235 for (j
=0; j
<nic
->config
.rx_ring_num
; j
++, msix_indx
++) {
3236 rx_mat
|= RX_MAT_SET(j
, msix_indx
);
3237 nic
->s2io_entries
[msix_indx
].arg
= &nic
->mac_control
.rings
[j
];
3238 nic
->s2io_entries
[msix_indx
].type
= MSIX_RING_TYPE
;
3239 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3241 writeq(rx_mat
, &bar0
->rx_mat
);
3243 tx_mat
= readq(&bar0
->tx_mat0_n
[7]);
3244 for (j
=0; j
<nic
->config
.rx_ring_num
; j
++, msix_indx
++) {
3245 tx_mat
|= TX_MAT_SET(i
, msix_indx
);
3246 nic
->s2io_entries
[msix_indx
].arg
= &nic
->mac_control
.rings
[j
];
3247 nic
->s2io_entries
[msix_indx
].type
= MSIX_RING_TYPE
;
3248 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3250 writeq(tx_mat
, &bar0
->tx_mat0_n
[7]);
3253 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, MAX_REQUESTED_MSI_X
);
3255 DBG_PRINT(ERR_DBG
, "%s: Enabling MSIX failed\n", nic
->dev
->name
);
3256 kfree(nic
->entries
);
3257 kfree(nic
->s2io_entries
);
3258 nic
->entries
= NULL
;
3259 nic
->s2io_entries
= NULL
;
3264 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3265 * in the herc NIC. (Temp change, needs to be removed later)
3267 pci_read_config_word(nic
->pdev
, 0x42, &msi_control
);
3268 msi_control
|= 0x1; /* Enable MSI */
3269 pci_write_config_word(nic
->pdev
, 0x42, msi_control
);
3274 /* ********************************************************* *
3275 * Functions defined below concern the OS part of the driver *
3276 * ********************************************************* */
3279 * s2io_open - open entry point of the driver
3280 * @dev : pointer to the device structure.
3282 * This function is the open entry point of the driver. It mainly calls a
3283 * function to allocate Rx buffers and inserts them into the buffer
3284 * descriptors and then enables the Rx part of the NIC.
3286 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3290 static int s2io_open(struct net_device
*dev
)
3292 nic_t
*sp
= dev
->priv
;
3295 u16 msi_control
; /* Temp variable */
3298 * Make sure you have link off by default every time
3299 * Nic is initialized
3301 netif_carrier_off(dev
);
3302 sp
->last_link_state
= 0;
3304 /* Initialize H/W and enable interrupts */
3305 if (s2io_card_up(sp
)) {
3306 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
3309 goto hw_init_failed
;
3312 /* Store the values of the MSIX table in the nic_t structure */
3313 store_xmsi_data(sp
);
3315 /* After proper initialization of H/W, register ISR */
3316 if (sp
->intr_type
== MSI
) {
3317 err
= request_irq((int) sp
->pdev
->irq
, s2io_msi_handle
,
3318 SA_SHIRQ
, sp
->name
, dev
);
3320 DBG_PRINT(ERR_DBG
, "%s: MSI registration \
3321 failed\n", dev
->name
);
3322 goto isr_registration_failed
;
3325 if (sp
->intr_type
== MSI_X
) {
3326 for (i
=1; (sp
->s2io_entries
[i
].in_use
== MSIX_FLG
); i
++) {
3327 if (sp
->s2io_entries
[i
].type
== MSIX_FIFO_TYPE
) {
3328 sprintf(sp
->desc1
, "%s:MSI-X-%d-TX",
3330 err
= request_irq(sp
->entries
[i
].vector
,
3331 s2io_msix_fifo_handle
, 0, sp
->desc1
,
3332 sp
->s2io_entries
[i
].arg
);
3333 DBG_PRINT(ERR_DBG
, "%s @ 0x%llx\n", sp
->desc1
,
3334 sp
->msix_info
[i
].addr
);
3336 sprintf(sp
->desc2
, "%s:MSI-X-%d-RX",
3338 err
= request_irq(sp
->entries
[i
].vector
,
3339 s2io_msix_ring_handle
, 0, sp
->desc2
,
3340 sp
->s2io_entries
[i
].arg
);
3341 DBG_PRINT(ERR_DBG
, "%s @ 0x%llx\n", sp
->desc2
,
3342 sp
->msix_info
[i
].addr
);
3345 DBG_PRINT(ERR_DBG
, "%s: MSI-X-%d registration \
3346 failed\n", dev
->name
, i
);
3347 DBG_PRINT(ERR_DBG
, "Returned: %d\n", err
);
3348 goto isr_registration_failed
;
3350 sp
->s2io_entries
[i
].in_use
= MSIX_REGISTERED_SUCCESS
;
3353 if (sp
->intr_type
== INTA
) {
3354 err
= request_irq((int) sp
->pdev
->irq
, s2io_isr
, SA_SHIRQ
,
3357 DBG_PRINT(ERR_DBG
, "%s: ISR registration failed\n",
3359 goto isr_registration_failed
;
3363 if (s2io_set_mac_addr(dev
, dev
->dev_addr
) == FAILURE
) {
3364 DBG_PRINT(ERR_DBG
, "Set Mac Address Failed\n");
3366 goto setting_mac_address_failed
;
3369 netif_start_queue(dev
);
3372 setting_mac_address_failed
:
3373 if (sp
->intr_type
!= MSI_X
)
3374 free_irq(sp
->pdev
->irq
, dev
);
3375 isr_registration_failed
:
3376 del_timer_sync(&sp
->alarm_timer
);
3377 if (sp
->intr_type
== MSI_X
) {
3378 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3379 for (i
=1; (sp
->s2io_entries
[i
].in_use
==
3380 MSIX_REGISTERED_SUCCESS
); i
++) {
3381 int vector
= sp
->entries
[i
].vector
;
3382 void *arg
= sp
->s2io_entries
[i
].arg
;
3384 free_irq(vector
, arg
);
3386 pci_disable_msix(sp
->pdev
);
3389 pci_read_config_word(sp
->pdev
, 0x42, &msi_control
);
3390 msi_control
&= 0xFFFE; /* Disable MSI */
3391 pci_write_config_word(sp
->pdev
, 0x42, msi_control
);
3394 else if (sp
->intr_type
== MSI
)
3395 pci_disable_msi(sp
->pdev
);
3398 if (sp
->intr_type
== MSI_X
) {
3401 if (sp
->s2io_entries
)
3402 kfree(sp
->s2io_entries
);
3408 * s2io_close -close entry point of the driver
3409 * @dev : device pointer.
3411 * This is the stop entry point of the driver. It needs to undo exactly
3412 * whatever was done by the open entry point,thus it's usually referred to
3413 * as the close function.Among other things this function mainly stops the
3414 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3416 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3420 static int s2io_close(struct net_device
*dev
)
3422 nic_t
*sp
= dev
->priv
;
3426 flush_scheduled_work();
3427 netif_stop_queue(dev
);
3428 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3431 if (sp
->intr_type
== MSI_X
) {
3432 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3433 for (i
=1; (sp
->s2io_entries
[i
].in_use
==
3434 MSIX_REGISTERED_SUCCESS
); i
++) {
3435 int vector
= sp
->entries
[i
].vector
;
3436 void *arg
= sp
->s2io_entries
[i
].arg
;
3438 free_irq(vector
, arg
);
3440 pci_read_config_word(sp
->pdev
, 0x42, &msi_control
);
3441 msi_control
&= 0xFFFE; /* Disable MSI */
3442 pci_write_config_word(sp
->pdev
, 0x42, msi_control
);
3444 pci_disable_msix(sp
->pdev
);
3448 free_irq(sp
->pdev
->irq
, dev
);
3449 if (sp
->intr_type
== MSI
)
3450 pci_disable_msi(sp
->pdev
);
3452 sp
->device_close_flag
= TRUE
; /* Device is shut down. */
3457 * s2io_xmit - Tx entry point of te driver
3458 * @skb : the socket buffer containing the Tx data.
3459 * @dev : device pointer.
3461 * This function is the Tx entry point of the driver. S2IO NIC supports
3462 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3463 * NOTE: when device cant queue the pkt,just the trans_start variable will
3466 * 0 on success & 1 on failure.
3469 static int s2io_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3471 nic_t
*sp
= dev
->priv
;
3472 u16 frg_cnt
, frg_len
, i
, queue
, queue_len
, put_off
, get_off
;
3475 TxFIFO_element_t __iomem
*tx_fifo
;
3476 unsigned long flags
;
3481 int vlan_priority
= 0;
3482 mac_info_t
*mac_control
;
3483 struct config_param
*config
;
3485 mac_control
= &sp
->mac_control
;
3486 config
= &sp
->config
;
3488 DBG_PRINT(TX_DBG
, "%s: In Neterion Tx routine\n", dev
->name
);
3489 spin_lock_irqsave(&sp
->tx_lock
, flags
);
3490 if (atomic_read(&sp
->card_state
) == CARD_DOWN
) {
3491 DBG_PRINT(TX_DBG
, "%s: Card going down for reset\n",
3493 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3500 /* Get Fifo number to Transmit based on vlan priority */
3501 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
3502 vlan_tag
= vlan_tx_tag_get(skb
);
3503 vlan_priority
= vlan_tag
>> 13;
3504 queue
= config
->fifo_mapping
[vlan_priority
];
3507 put_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_put_info
.offset
;
3508 get_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_get_info
.offset
;
3509 txdp
= (TxD_t
*) mac_control
->fifos
[queue
].list_info
[put_off
].
3512 queue_len
= mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1;
3513 /* Avoid "put" pointer going beyond "get" pointer */
3514 if (txdp
->Host_Control
|| (((put_off
+ 1) % queue_len
) == get_off
)) {
3515 DBG_PRINT(TX_DBG
, "Error in xmit, No free TXDs.\n");
3516 netif_stop_queue(dev
);
3518 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3522 /* A buffer with no data will be dropped */
3524 DBG_PRINT(TX_DBG
, "%s:Buffer has no data..\n", dev
->name
);
3526 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3531 mss
= skb_shinfo(skb
)->tso_size
;
3533 txdp
->Control_1
|= TXD_TCP_LSO_EN
;
3534 txdp
->Control_1
|= TXD_TCP_LSO_MSS(mss
);
3538 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
3539 frg_len
= skb
->len
- skb
->data_len
;
3541 txdp
->Buffer_Pointer
= pci_map_single
3542 (sp
->pdev
, skb
->data
, frg_len
, PCI_DMA_TODEVICE
);
3543 txdp
->Host_Control
= (unsigned long) skb
;
3544 if (skb
->ip_summed
== CHECKSUM_HW
) {
3546 (TXD_TX_CKO_IPV4_EN
| TXD_TX_CKO_TCP_EN
|
3550 txdp
->Control_2
|= config
->tx_intr_type
;
3552 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
3553 txdp
->Control_2
|= TXD_VLAN_ENABLE
;
3554 txdp
->Control_2
|= TXD_VLAN_TAG(vlan_tag
);
3557 txdp
->Control_1
|= (TXD_BUFFER0_SIZE(frg_len
) |
3558 TXD_GATHER_CODE_FIRST
);
3559 txdp
->Control_1
|= TXD_LIST_OWN_XENA
;
3561 /* For fragmented SKB. */
3562 for (i
= 0; i
< frg_cnt
; i
++) {
3563 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
3564 /* A '0' length fragment will be ignored */
3568 txdp
->Buffer_Pointer
= (u64
) pci_map_page
3569 (sp
->pdev
, frag
->page
, frag
->page_offset
,
3570 frag
->size
, PCI_DMA_TODEVICE
);
3571 txdp
->Control_1
|= TXD_BUFFER0_SIZE(frag
->size
);
3573 txdp
->Control_1
|= TXD_GATHER_CODE_LAST
;
3575 tx_fifo
= mac_control
->tx_FIFO_start
[queue
];
3576 val64
= mac_control
->fifos
[queue
].list_info
[put_off
].list_phy_addr
;
3577 writeq(val64
, &tx_fifo
->TxDL_Pointer
);
3579 val64
= (TX_FIFO_LAST_TXD_NUM(frg_cnt
) | TX_FIFO_FIRST_LIST
|
3584 val64
|= TX_FIFO_SPECIAL_FUNC
;
3586 writeq(val64
, &tx_fifo
->List_Control
);
3591 put_off
%= mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1;
3592 mac_control
->fifos
[queue
].tx_curr_put_info
.offset
= put_off
;
3594 /* Avoid "put" pointer going beyond "get" pointer */
3595 if (((put_off
+ 1) % queue_len
) == get_off
) {
3597 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3599 netif_stop_queue(dev
);
3602 dev
->trans_start
= jiffies
;
3603 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3609 s2io_alarm_handle(unsigned long data
)
3611 nic_t
*sp
= (nic_t
*)data
;
3613 alarm_intr_handler(sp
);
3614 mod_timer(&sp
->alarm_timer
, jiffies
+ HZ
/ 2);
3618 s2io_msi_handle(int irq
, void *dev_id
, struct pt_regs
*regs
)
3620 struct net_device
*dev
= (struct net_device
*) dev_id
;
3621 nic_t
*sp
= dev
->priv
;
3624 mac_info_t
*mac_control
;
3625 struct config_param
*config
;
3627 atomic_inc(&sp
->isr_cnt
);
3628 mac_control
= &sp
->mac_control
;
3629 config
= &sp
->config
;
3630 DBG_PRINT(INTR_DBG
, "%s: MSI handler\n", __FUNCTION__
);
3632 /* If Intr is because of Rx Traffic */
3633 for (i
= 0; i
< config
->rx_ring_num
; i
++)
3634 rx_intr_handler(&mac_control
->rings
[i
]);
3636 /* If Intr is because of Tx Traffic */
3637 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
3638 tx_intr_handler(&mac_control
->fifos
[i
]);
3641 * If the Rx buffer count is below the panic threshold then
3642 * reallocate the buffers from the interrupt handler itself,
3643 * else schedule a tasklet to reallocate the buffers.
3645 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
3646 int rxb_size
= atomic_read(&sp
->rx_bufs_left
[i
]);
3647 int level
= rx_buffer_level(sp
, rxb_size
, i
);
3649 if ((level
== PANIC
) && (!TASKLET_IN_USE
)) {
3650 DBG_PRINT(INTR_DBG
, "%s: Rx BD hit ", dev
->name
);
3651 DBG_PRINT(INTR_DBG
, "PANIC levels\n");
3652 if ((ret
= fill_rx_buffers(sp
, i
)) == -ENOMEM
) {
3653 DBG_PRINT(ERR_DBG
, "%s:Out of memory",
3655 DBG_PRINT(ERR_DBG
, " in ISR!!\n");
3656 clear_bit(0, (&sp
->tasklet_status
));
3657 atomic_dec(&sp
->isr_cnt
);
3660 clear_bit(0, (&sp
->tasklet_status
));
3661 } else if (level
== LOW
) {
3662 tasklet_schedule(&sp
->task
);
3666 atomic_dec(&sp
->isr_cnt
);
3671 s2io_msix_ring_handle(int irq
, void *dev_id
, struct pt_regs
*regs
)
3673 ring_info_t
*ring
= (ring_info_t
*)dev_id
;
3674 nic_t
*sp
= ring
->nic
;
3675 int rxb_size
, level
, rng_n
;
3677 atomic_inc(&sp
->isr_cnt
);
3678 rx_intr_handler(ring
);
3680 rng_n
= ring
->ring_no
;
3681 rxb_size
= atomic_read(&sp
->rx_bufs_left
[rng_n
]);
3682 level
= rx_buffer_level(sp
, rxb_size
, rng_n
);
3684 if ((level
== PANIC
) && (!TASKLET_IN_USE
)) {
3686 DBG_PRINT(INTR_DBG
, "%s: Rx BD hit ", __FUNCTION__
);
3687 DBG_PRINT(INTR_DBG
, "PANIC levels\n");
3688 if ((ret
= fill_rx_buffers(sp
, rng_n
)) == -ENOMEM
) {
3689 DBG_PRINT(ERR_DBG
, "Out of memory in %s",
3691 clear_bit(0, (&sp
->tasklet_status
));
3694 clear_bit(0, (&sp
->tasklet_status
));
3695 } else if (level
== LOW
) {
3696 tasklet_schedule(&sp
->task
);
3698 atomic_dec(&sp
->isr_cnt
);
3704 s2io_msix_fifo_handle(int irq
, void *dev_id
, struct pt_regs
*regs
)
3706 fifo_info_t
*fifo
= (fifo_info_t
*)dev_id
;
3707 nic_t
*sp
= fifo
->nic
;
3709 atomic_inc(&sp
->isr_cnt
);
3710 tx_intr_handler(fifo
);
3711 atomic_dec(&sp
->isr_cnt
);
3715 static void s2io_txpic_intr_handle(nic_t
*sp
)
3717 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
3720 val64
= readq(&bar0
->pic_int_status
);
3721 if (val64
& PIC_INT_GPIO
) {
3722 val64
= readq(&bar0
->gpio_int_reg
);
3723 if ((val64
& GPIO_INT_REG_LINK_DOWN
) &&
3724 (val64
& GPIO_INT_REG_LINK_UP
)) {
3725 val64
|= GPIO_INT_REG_LINK_DOWN
;
3726 val64
|= GPIO_INT_REG_LINK_UP
;
3727 writeq(val64
, &bar0
->gpio_int_reg
);
3731 if (((sp
->last_link_state
== LINK_UP
) &&
3732 (val64
& GPIO_INT_REG_LINK_DOWN
)) ||
3733 ((sp
->last_link_state
== LINK_DOWN
) &&
3734 (val64
& GPIO_INT_REG_LINK_UP
))) {
3735 val64
= readq(&bar0
->gpio_int_mask
);
3736 val64
|= GPIO_INT_MASK_LINK_DOWN
;
3737 val64
|= GPIO_INT_MASK_LINK_UP
;
3738 writeq(val64
, &bar0
->gpio_int_mask
);
3739 s2io_set_link((unsigned long)sp
);
3742 if (sp
->last_link_state
== LINK_UP
) {
3743 /*enable down interrupt */
3744 val64
= readq(&bar0
->gpio_int_mask
);
3745 /* unmasks link down intr */
3746 val64
&= ~GPIO_INT_MASK_LINK_DOWN
;
3747 /* masks link up intr */
3748 val64
|= GPIO_INT_MASK_LINK_UP
;
3749 writeq(val64
, &bar0
->gpio_int_mask
);
3751 /*enable UP Interrupt */
3752 val64
= readq(&bar0
->gpio_int_mask
);
3753 /* unmasks link up interrupt */
3754 val64
&= ~GPIO_INT_MASK_LINK_UP
;
3755 /* masks link down interrupt */
3756 val64
|= GPIO_INT_MASK_LINK_DOWN
;
3757 writeq(val64
, &bar0
->gpio_int_mask
);
3763 * s2io_isr - ISR handler of the device .
3764 * @irq: the irq of the device.
3765 * @dev_id: a void pointer to the dev structure of the NIC.
3766 * @pt_regs: pointer to the registers pushed on the stack.
3767 * Description: This function is the ISR handler of the device. It
3768 * identifies the reason for the interrupt and calls the relevant
3769 * service routines. As a contongency measure, this ISR allocates the
3770 * recv buffers, if their numbers are below the panic value which is
3771 * presently set to 25% of the original number of rcv buffers allocated.
3773 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
3774 * IRQ_NONE: will be returned if interrupt is not from our device
3776 static irqreturn_t
s2io_isr(int irq
, void *dev_id
, struct pt_regs
*regs
)
3778 struct net_device
*dev
= (struct net_device
*) dev_id
;
3779 nic_t
*sp
= dev
->priv
;
3780 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
3782 u64 reason
= 0, val64
;
3783 mac_info_t
*mac_control
;
3784 struct config_param
*config
;
3786 atomic_inc(&sp
->isr_cnt
);
3787 mac_control
= &sp
->mac_control
;
3788 config
= &sp
->config
;
3791 * Identify the cause for interrupt and call the appropriate
3792 * interrupt handler. Causes for the interrupt could be;
3796 * 4. Error in any functional blocks of the NIC.
3798 reason
= readq(&bar0
->general_int_status
);
3801 /* The interrupt was not raised by Xena. */
3802 atomic_dec(&sp
->isr_cnt
);
3806 #ifdef CONFIG_S2IO_NAPI
3807 if (reason
& GEN_INTR_RXTRAFFIC
) {
3808 if (netif_rx_schedule_prep(dev
)) {
3809 en_dis_able_nic_intrs(sp
, RX_TRAFFIC_INTR
,
3811 __netif_rx_schedule(dev
);
3815 /* If Intr is because of Rx Traffic */
3816 if (reason
& GEN_INTR_RXTRAFFIC
) {
3818 * rx_traffic_int reg is an R1 register, writing all 1's
3819 * will ensure that the actual interrupt causing bit get's
3820 * cleared and hence a read can be avoided.
3822 val64
= 0xFFFFFFFFFFFFFFFFULL
;
3823 writeq(val64
, &bar0
->rx_traffic_int
);
3824 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
3825 rx_intr_handler(&mac_control
->rings
[i
]);
3830 /* If Intr is because of Tx Traffic */
3831 if (reason
& GEN_INTR_TXTRAFFIC
) {
3833 * tx_traffic_int reg is an R1 register, writing all 1's
3834 * will ensure that the actual interrupt causing bit get's
3835 * cleared and hence a read can be avoided.
3837 val64
= 0xFFFFFFFFFFFFFFFFULL
;
3838 writeq(val64
, &bar0
->tx_traffic_int
);
3840 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
3841 tx_intr_handler(&mac_control
->fifos
[i
]);
3844 if (reason
& GEN_INTR_TXPIC
)
3845 s2io_txpic_intr_handle(sp
);
3847 * If the Rx buffer count is below the panic threshold then
3848 * reallocate the buffers from the interrupt handler itself,
3849 * else schedule a tasklet to reallocate the buffers.
3851 #ifndef CONFIG_S2IO_NAPI
3852 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
3854 int rxb_size
= atomic_read(&sp
->rx_bufs_left
[i
]);
3855 int level
= rx_buffer_level(sp
, rxb_size
, i
);
3857 if ((level
== PANIC
) && (!TASKLET_IN_USE
)) {
3858 DBG_PRINT(INTR_DBG
, "%s: Rx BD hit ", dev
->name
);
3859 DBG_PRINT(INTR_DBG
, "PANIC levels\n");
3860 if ((ret
= fill_rx_buffers(sp
, i
)) == -ENOMEM
) {
3861 DBG_PRINT(ERR_DBG
, "%s:Out of memory",
3863 DBG_PRINT(ERR_DBG
, " in ISR!!\n");
3864 clear_bit(0, (&sp
->tasklet_status
));
3865 atomic_dec(&sp
->isr_cnt
);
3868 clear_bit(0, (&sp
->tasklet_status
));
3869 } else if (level
== LOW
) {
3870 tasklet_schedule(&sp
->task
);
3875 atomic_dec(&sp
->isr_cnt
);
3882 static void s2io_updt_stats(nic_t
*sp
)
3884 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
3888 if (atomic_read(&sp
->card_state
) == CARD_UP
) {
3889 /* Apprx 30us on a 133 MHz bus */
3890 val64
= SET_UPDT_CLICKS(10) |
3891 STAT_CFG_ONE_SHOT_EN
| STAT_CFG_STAT_EN
;
3892 writeq(val64
, &bar0
->stat_cfg
);
3895 val64
= readq(&bar0
->stat_cfg
);
3896 if (!(val64
& BIT(0)))
3900 break; /* Updt failed */
3906 * s2io_get_stats - Updates the device statistics structure.
3907 * @dev : pointer to the device structure.
3909 * This function updates the device statistics structure in the s2io_nic
3910 * structure and returns a pointer to the same.
3912 * pointer to the updated net_device_stats structure.
3915 static struct net_device_stats
*s2io_get_stats(struct net_device
*dev
)
3917 nic_t
*sp
= dev
->priv
;
3918 mac_info_t
*mac_control
;
3919 struct config_param
*config
;
3922 mac_control
= &sp
->mac_control
;
3923 config
= &sp
->config
;
3925 /* Configure Stats for immediate updt */
3926 s2io_updt_stats(sp
);
3928 sp
->stats
.tx_packets
=
3929 le32_to_cpu(mac_control
->stats_info
->tmac_frms
);
3930 sp
->stats
.tx_errors
=
3931 le32_to_cpu(mac_control
->stats_info
->tmac_any_err_frms
);
3932 sp
->stats
.rx_errors
=
3933 le32_to_cpu(mac_control
->stats_info
->rmac_drop_frms
);
3934 sp
->stats
.multicast
=
3935 le32_to_cpu(mac_control
->stats_info
->rmac_vld_mcst_frms
);
3936 sp
->stats
.rx_length_errors
=
3937 le32_to_cpu(mac_control
->stats_info
->rmac_long_frms
);
3939 return (&sp
->stats
);
3943 * s2io_set_multicast - entry point for multicast address enable/disable.
3944 * @dev : pointer to the device structure
3946 * This function is a driver entry point which gets called by the kernel
3947 * whenever multicast addresses must be enabled/disabled. This also gets
3948 * called to set/reset promiscuous mode. Depending on the deivce flag, we
3949 * determine, if multicast address must be enabled or if promiscuous mode
3950 * is to be disabled etc.
3955 static void s2io_set_multicast(struct net_device
*dev
)
3958 struct dev_mc_list
*mclist
;
3959 nic_t
*sp
= dev
->priv
;
3960 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
3961 u64 val64
= 0, multi_mac
= 0x010203040506ULL
, mask
=
3963 u64 dis_addr
= 0xffffffffffffULL
, mac_addr
= 0;
3966 if ((dev
->flags
& IFF_ALLMULTI
) && (!sp
->m_cast_flg
)) {
3967 /* Enable all Multicast addresses */
3968 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac
),
3969 &bar0
->rmac_addr_data0_mem
);
3970 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask
),
3971 &bar0
->rmac_addr_data1_mem
);
3972 val64
= RMAC_ADDR_CMD_MEM_WE
|
3973 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
3974 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET
);
3975 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
3976 /* Wait till command completes */
3977 wait_for_cmd_complete(sp
);
3980 sp
->all_multi_pos
= MAC_MC_ALL_MC_ADDR_OFFSET
;
3981 } else if ((dev
->flags
& IFF_ALLMULTI
) && (sp
->m_cast_flg
)) {
3982 /* Disable all Multicast addresses */
3983 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
3984 &bar0
->rmac_addr_data0_mem
);
3985 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
3986 &bar0
->rmac_addr_data1_mem
);
3987 val64
= RMAC_ADDR_CMD_MEM_WE
|
3988 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
3989 RMAC_ADDR_CMD_MEM_OFFSET(sp
->all_multi_pos
);
3990 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
3991 /* Wait till command completes */
3992 wait_for_cmd_complete(sp
);
3995 sp
->all_multi_pos
= 0;
3998 if ((dev
->flags
& IFF_PROMISC
) && (!sp
->promisc_flg
)) {
3999 /* Put the NIC into promiscuous mode */
4000 add
= &bar0
->mac_cfg
;
4001 val64
= readq(&bar0
->mac_cfg
);
4002 val64
|= MAC_CFG_RMAC_PROM_ENABLE
;
4004 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4005 writel((u32
) val64
, add
);
4006 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4007 writel((u32
) (val64
>> 32), (add
+ 4));
4009 val64
= readq(&bar0
->mac_cfg
);
4010 sp
->promisc_flg
= 1;
4011 DBG_PRINT(INFO_DBG
, "%s: entered promiscuous mode\n",
4013 } else if (!(dev
->flags
& IFF_PROMISC
) && (sp
->promisc_flg
)) {
4014 /* Remove the NIC from promiscuous mode */
4015 add
= &bar0
->mac_cfg
;
4016 val64
= readq(&bar0
->mac_cfg
);
4017 val64
&= ~MAC_CFG_RMAC_PROM_ENABLE
;
4019 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4020 writel((u32
) val64
, add
);
4021 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4022 writel((u32
) (val64
>> 32), (add
+ 4));
4024 val64
= readq(&bar0
->mac_cfg
);
4025 sp
->promisc_flg
= 0;
4026 DBG_PRINT(INFO_DBG
, "%s: left promiscuous mode\n",
4030 /* Update individual M_CAST address list */
4031 if ((!sp
->m_cast_flg
) && dev
->mc_count
) {
4033 (MAX_ADDRS_SUPPORTED
- MAC_MC_ADDR_START_OFFSET
- 1)) {
4034 DBG_PRINT(ERR_DBG
, "%s: No more Rx filters ",
4036 DBG_PRINT(ERR_DBG
, "can be added, please enable ");
4037 DBG_PRINT(ERR_DBG
, "ALL_MULTI instead\n");
4041 prev_cnt
= sp
->mc_addr_count
;
4042 sp
->mc_addr_count
= dev
->mc_count
;
4044 /* Clear out the previous list of Mc in the H/W. */
4045 for (i
= 0; i
< prev_cnt
; i
++) {
4046 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4047 &bar0
->rmac_addr_data0_mem
);
4048 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4049 &bar0
->rmac_addr_data1_mem
);
4050 val64
= RMAC_ADDR_CMD_MEM_WE
|
4051 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4052 RMAC_ADDR_CMD_MEM_OFFSET
4053 (MAC_MC_ADDR_START_OFFSET
+ i
);
4054 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4056 /* Wait for command completes */
4057 if (wait_for_cmd_complete(sp
)) {
4058 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4060 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4065 /* Create the new Rx filter list and update the same in H/W. */
4066 for (i
= 0, mclist
= dev
->mc_list
; i
< dev
->mc_count
;
4067 i
++, mclist
= mclist
->next
) {
4068 memcpy(sp
->usr_addrs
[i
].addr
, mclist
->dmi_addr
,
4070 for (j
= 0; j
< ETH_ALEN
; j
++) {
4071 mac_addr
|= mclist
->dmi_addr
[j
];
4075 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
4076 &bar0
->rmac_addr_data0_mem
);
4077 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4078 &bar0
->rmac_addr_data1_mem
);
4079 val64
= RMAC_ADDR_CMD_MEM_WE
|
4080 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4081 RMAC_ADDR_CMD_MEM_OFFSET
4082 (i
+ MAC_MC_ADDR_START_OFFSET
);
4083 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4085 /* Wait for command completes */
4086 if (wait_for_cmd_complete(sp
)) {
4087 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4089 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4097 * s2io_set_mac_addr - Programs the Xframe mac address
4098 * @dev : pointer to the device structure.
4099 * @addr: a uchar pointer to the new mac address which is to be set.
4100 * Description : This procedure will program the Xframe to receive
4101 * frames with new Mac Address
4102 * Return value: SUCCESS on success and an appropriate (-)ve integer
4103 * as defined in errno.h file on failure.
4106 int s2io_set_mac_addr(struct net_device
*dev
, u8
* addr
)
4108 nic_t
*sp
= dev
->priv
;
4109 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4110 register u64 val64
, mac_addr
= 0;
4114 * Set the new MAC address as the new unicast filter and reflect this
4115 * change on the device address registered with the OS. It will be
4118 for (i
= 0; i
< ETH_ALEN
; i
++) {
4120 mac_addr
|= addr
[i
];
4123 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
4124 &bar0
->rmac_addr_data0_mem
);
4127 RMAC_ADDR_CMD_MEM_WE
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4128 RMAC_ADDR_CMD_MEM_OFFSET(0);
4129 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4130 /* Wait till command completes */
4131 if (wait_for_cmd_complete(sp
)) {
4132 DBG_PRINT(ERR_DBG
, "%s: set_mac_addr failed\n", dev
->name
);
4140 * s2io_ethtool_sset - Sets different link parameters.
4141 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4142 * @info: pointer to the structure with parameters given by ethtool to set
4145 * The function sets different link parameters provided by the user onto
4151 static int s2io_ethtool_sset(struct net_device
*dev
,
4152 struct ethtool_cmd
*info
)
4154 nic_t
*sp
= dev
->priv
;
4155 if ((info
->autoneg
== AUTONEG_ENABLE
) ||
4156 (info
->speed
!= SPEED_10000
) || (info
->duplex
!= DUPLEX_FULL
))
4159 s2io_close(sp
->dev
);
4167 * s2io_ethtol_gset - Return link specific information.
4168 * @sp : private member of the device structure, pointer to the
4169 * s2io_nic structure.
4170 * @info : pointer to the structure with parameters given by ethtool
4171 * to return link information.
4173 * Returns link specific information like speed, duplex etc.. to ethtool.
4175 * return 0 on success.
4178 static int s2io_ethtool_gset(struct net_device
*dev
, struct ethtool_cmd
*info
)
4180 nic_t
*sp
= dev
->priv
;
4181 info
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4182 info
->advertising
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4183 info
->port
= PORT_FIBRE
;
4184 /* info->transceiver?? TODO */
4186 if (netif_carrier_ok(sp
->dev
)) {
4187 info
->speed
= 10000;
4188 info
->duplex
= DUPLEX_FULL
;
4194 info
->autoneg
= AUTONEG_DISABLE
;
4199 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4200 * @sp : private member of the device structure, which is a pointer to the
4201 * s2io_nic structure.
4202 * @info : pointer to the structure with parameters given by ethtool to
4203 * return driver information.
4205 * Returns driver specefic information like name, version etc.. to ethtool.
4210 static void s2io_ethtool_gdrvinfo(struct net_device
*dev
,
4211 struct ethtool_drvinfo
*info
)
4213 nic_t
*sp
= dev
->priv
;
4215 strncpy(info
->driver
, s2io_driver_name
, sizeof(info
->driver
));
4216 strncpy(info
->version
, s2io_driver_version
, sizeof(info
->version
));
4217 strncpy(info
->fw_version
, "", sizeof(info
->fw_version
));
4218 strncpy(info
->bus_info
, pci_name(sp
->pdev
), sizeof(info
->bus_info
));
4219 info
->regdump_len
= XENA_REG_SPACE
;
4220 info
->eedump_len
= XENA_EEPROM_SPACE
;
4221 info
->testinfo_len
= S2IO_TEST_LEN
;
4222 info
->n_stats
= S2IO_STAT_LEN
;
4226 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4227 * @sp: private member of the device structure, which is a pointer to the
4228 * s2io_nic structure.
4229 * @regs : pointer to the structure with parameters given by ethtool for
4230 * dumping the registers.
4231 * @reg_space: The input argumnet into which all the registers are dumped.
4233 * Dumps the entire register space of xFrame NIC into the user given
4239 static void s2io_ethtool_gregs(struct net_device
*dev
,
4240 struct ethtool_regs
*regs
, void *space
)
4244 u8
*reg_space
= (u8
*) space
;
4245 nic_t
*sp
= dev
->priv
;
4247 regs
->len
= XENA_REG_SPACE
;
4248 regs
->version
= sp
->pdev
->subsystem_device
;
4250 for (i
= 0; i
< regs
->len
; i
+= 8) {
4251 reg
= readq(sp
->bar0
+ i
);
4252 memcpy((reg_space
+ i
), ®
, 8);
4257 * s2io_phy_id - timer function that alternates adapter LED.
4258 * @data : address of the private member of the device structure, which
4259 * is a pointer to the s2io_nic structure, provided as an u32.
4260 * Description: This is actually the timer function that alternates the
4261 * adapter LED bit of the adapter control bit to set/reset every time on
4262 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4263 * once every second.
4265 static void s2io_phy_id(unsigned long data
)
4267 nic_t
*sp
= (nic_t
*) data
;
4268 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4272 subid
= sp
->pdev
->subsystem_device
;
4273 if ((sp
->device_type
== XFRAME_II_DEVICE
) ||
4274 ((subid
& 0xFF) >= 0x07)) {
4275 val64
= readq(&bar0
->gpio_control
);
4276 val64
^= GPIO_CTRL_GPIO_0
;
4277 writeq(val64
, &bar0
->gpio_control
);
4279 val64
= readq(&bar0
->adapter_control
);
4280 val64
^= ADAPTER_LED_ON
;
4281 writeq(val64
, &bar0
->adapter_control
);
4284 mod_timer(&sp
->id_timer
, jiffies
+ HZ
/ 2);
4288 * s2io_ethtool_idnic - To physically identify the nic on the system.
4289 * @sp : private member of the device structure, which is a pointer to the
4290 * s2io_nic structure.
4291 * @id : pointer to the structure with identification parameters given by
4293 * Description: Used to physically identify the NIC on the system.
4294 * The Link LED will blink for a time specified by the user for
4296 * NOTE: The Link has to be Up to be able to blink the LED. Hence
4297 * identification is possible only if it's link is up.
4299 * int , returns 0 on success
4302 static int s2io_ethtool_idnic(struct net_device
*dev
, u32 data
)
4304 u64 val64
= 0, last_gpio_ctrl_val
;
4305 nic_t
*sp
= dev
->priv
;
4306 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4309 subid
= sp
->pdev
->subsystem_device
;
4310 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
4311 if ((sp
->device_type
== XFRAME_I_DEVICE
) &&
4312 ((subid
& 0xFF) < 0x07)) {
4313 val64
= readq(&bar0
->adapter_control
);
4314 if (!(val64
& ADAPTER_CNTL_EN
)) {
4316 "Adapter Link down, cannot blink LED\n");
4320 if (sp
->id_timer
.function
== NULL
) {
4321 init_timer(&sp
->id_timer
);
4322 sp
->id_timer
.function
= s2io_phy_id
;
4323 sp
->id_timer
.data
= (unsigned long) sp
;
4325 mod_timer(&sp
->id_timer
, jiffies
);
4327 msleep_interruptible(data
* HZ
);
4329 msleep_interruptible(MAX_FLICKER_TIME
);
4330 del_timer_sync(&sp
->id_timer
);
4332 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp
->device_type
, subid
)) {
4333 writeq(last_gpio_ctrl_val
, &bar0
->gpio_control
);
4334 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
4341 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4342 * @sp : private member of the device structure, which is a pointer to the
4343 * s2io_nic structure.
4344 * @ep : pointer to the structure with pause parameters given by ethtool.
4346 * Returns the Pause frame generation and reception capability of the NIC.
4350 static void s2io_ethtool_getpause_data(struct net_device
*dev
,
4351 struct ethtool_pauseparam
*ep
)
4354 nic_t
*sp
= dev
->priv
;
4355 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4357 val64
= readq(&bar0
->rmac_pause_cfg
);
4358 if (val64
& RMAC_PAUSE_GEN_ENABLE
)
4359 ep
->tx_pause
= TRUE
;
4360 if (val64
& RMAC_PAUSE_RX_ENABLE
)
4361 ep
->rx_pause
= TRUE
;
4362 ep
->autoneg
= FALSE
;
4366 * s2io_ethtool_setpause_data - set/reset pause frame generation.
4367 * @sp : private member of the device structure, which is a pointer to the
4368 * s2io_nic structure.
4369 * @ep : pointer to the structure with pause parameters given by ethtool.
4371 * It can be used to set or reset Pause frame generation or reception
4372 * support of the NIC.
4374 * int, returns 0 on Success
4377 static int s2io_ethtool_setpause_data(struct net_device
*dev
,
4378 struct ethtool_pauseparam
*ep
)
4381 nic_t
*sp
= dev
->priv
;
4382 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4384 val64
= readq(&bar0
->rmac_pause_cfg
);
4386 val64
|= RMAC_PAUSE_GEN_ENABLE
;
4388 val64
&= ~RMAC_PAUSE_GEN_ENABLE
;
4390 val64
|= RMAC_PAUSE_RX_ENABLE
;
4392 val64
&= ~RMAC_PAUSE_RX_ENABLE
;
4393 writeq(val64
, &bar0
->rmac_pause_cfg
);
4398 * read_eeprom - reads 4 bytes of data from user given offset.
4399 * @sp : private member of the device structure, which is a pointer to the
4400 * s2io_nic structure.
4401 * @off : offset at which the data must be written
4402 * @data : Its an output parameter where the data read at the given
4405 * Will read 4 bytes of data from the user given offset and return the
4407 * NOTE: Will allow to read only part of the EEPROM visible through the
4410 * -1 on failure and 0 on success.
4413 #define S2IO_DEV_ID 5
4414 static int read_eeprom(nic_t
* sp
, int off
, u64
* data
)
4419 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4421 if (sp
->device_type
== XFRAME_I_DEVICE
) {
4422 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
4423 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ
|
4424 I2C_CONTROL_CNTL_START
;
4425 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
4427 while (exit_cnt
< 5) {
4428 val64
= readq(&bar0
->i2c_control
);
4429 if (I2C_CONTROL_CNTL_END(val64
)) {
4430 *data
= I2C_CONTROL_GET_DATA(val64
);
4439 if (sp
->device_type
== XFRAME_II_DEVICE
) {
4440 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
4441 SPI_CONTROL_BYTECNT(0x3) |
4442 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off
);
4443 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
4444 val64
|= SPI_CONTROL_REQ
;
4445 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
4446 while (exit_cnt
< 5) {
4447 val64
= readq(&bar0
->spi_control
);
4448 if (val64
& SPI_CONTROL_NACK
) {
4451 } else if (val64
& SPI_CONTROL_DONE
) {
4452 *data
= readq(&bar0
->spi_data
);
4465 * write_eeprom - actually writes the relevant part of the data value.
4466 * @sp : private member of the device structure, which is a pointer to the
4467 * s2io_nic structure.
4468 * @off : offset at which the data must be written
4469 * @data : The data that is to be written
4470 * @cnt : Number of bytes of the data that are actually to be written into
4471 * the Eeprom. (max of 3)
4473 * Actually writes the relevant part of the data value into the Eeprom
4474 * through the I2C bus.
4476 * 0 on success, -1 on failure.
4479 static int write_eeprom(nic_t
* sp
, int off
, u64 data
, int cnt
)
4481 int exit_cnt
= 0, ret
= -1;
4483 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4485 if (sp
->device_type
== XFRAME_I_DEVICE
) {
4486 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
4487 I2C_CONTROL_BYTE_CNT(cnt
) | I2C_CONTROL_SET_DATA((u32
)data
) |
4488 I2C_CONTROL_CNTL_START
;
4489 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
4491 while (exit_cnt
< 5) {
4492 val64
= readq(&bar0
->i2c_control
);
4493 if (I2C_CONTROL_CNTL_END(val64
)) {
4494 if (!(val64
& I2C_CONTROL_NACK
))
4503 if (sp
->device_type
== XFRAME_II_DEVICE
) {
4504 int write_cnt
= (cnt
== 8) ? 0 : cnt
;
4505 writeq(SPI_DATA_WRITE(data
,(cnt
<<3)), &bar0
->spi_data
);
4507 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
4508 SPI_CONTROL_BYTECNT(write_cnt
) |
4509 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off
);
4510 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
4511 val64
|= SPI_CONTROL_REQ
;
4512 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
4513 while (exit_cnt
< 5) {
4514 val64
= readq(&bar0
->spi_control
);
4515 if (val64
& SPI_CONTROL_NACK
) {
4518 } else if (val64
& SPI_CONTROL_DONE
) {
4530 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
4531 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4532 * @eeprom : pointer to the user level structure provided by ethtool,
4533 * containing all relevant information.
4534 * @data_buf : user defined value to be written into Eeprom.
4535 * Description: Reads the values stored in the Eeprom at given offset
4536 * for a given length. Stores these values int the input argument data
4537 * buffer 'data_buf' and returns these to the caller (ethtool.)
4542 static int s2io_ethtool_geeprom(struct net_device
*dev
,
4543 struct ethtool_eeprom
*eeprom
, u8
* data_buf
)
4547 nic_t
*sp
= dev
->priv
;
4549 eeprom
->magic
= sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16);
4551 if ((eeprom
->offset
+ eeprom
->len
) > (XENA_EEPROM_SPACE
))
4552 eeprom
->len
= XENA_EEPROM_SPACE
- eeprom
->offset
;
4554 for (i
= 0; i
< eeprom
->len
; i
+= 4) {
4555 if (read_eeprom(sp
, (eeprom
->offset
+ i
), &data
)) {
4556 DBG_PRINT(ERR_DBG
, "Read of EEPROM failed\n");
4560 memcpy((data_buf
+ i
), &valid
, 4);
4566 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4567 * @sp : private member of the device structure, which is a pointer to the
4568 * s2io_nic structure.
4569 * @eeprom : pointer to the user level structure provided by ethtool,
4570 * containing all relevant information.
4571 * @data_buf ; user defined value to be written into Eeprom.
4573 * Tries to write the user provided value in the Eeprom, at the offset
4574 * given by the user.
4576 * 0 on success, -EFAULT on failure.
4579 static int s2io_ethtool_seeprom(struct net_device
*dev
,
4580 struct ethtool_eeprom
*eeprom
,
4583 int len
= eeprom
->len
, cnt
= 0;
4584 u64 valid
= 0, data
;
4585 nic_t
*sp
= dev
->priv
;
4587 if (eeprom
->magic
!= (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16))) {
4589 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
4590 DBG_PRINT(ERR_DBG
, "is wrong, Its not 0x%x\n",
4596 data
= (u32
) data_buf
[cnt
] & 0x000000FF;
4598 valid
= (u32
) (data
<< 24);
4602 if (write_eeprom(sp
, (eeprom
->offset
+ cnt
), valid
, 0)) {
4604 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
4606 "write into the specified offset\n");
4617 * s2io_register_test - reads and writes into all clock domains.
4618 * @sp : private member of the device structure, which is a pointer to the
4619 * s2io_nic structure.
4620 * @data : variable that returns the result of each of the test conducted b
4623 * Read and write into all clock domains. The NIC has 3 clock domains,
4624 * see that registers in all the three regions are accessible.
4629 static int s2io_register_test(nic_t
* sp
, uint64_t * data
)
4631 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4632 u64 val64
= 0, exp_val
;
4635 val64
= readq(&bar0
->pif_rd_swapper_fb
);
4636 if (val64
!= 0x123456789abcdefULL
) {
4638 DBG_PRINT(INFO_DBG
, "Read Test level 1 fails\n");
4641 val64
= readq(&bar0
->rmac_pause_cfg
);
4642 if (val64
!= 0xc000ffff00000000ULL
) {
4644 DBG_PRINT(INFO_DBG
, "Read Test level 2 fails\n");
4647 val64
= readq(&bar0
->rx_queue_cfg
);
4648 if (sp
->device_type
== XFRAME_II_DEVICE
)
4649 exp_val
= 0x0404040404040404ULL
;
4651 exp_val
= 0x0808080808080808ULL
;
4652 if (val64
!= exp_val
) {
4654 DBG_PRINT(INFO_DBG
, "Read Test level 3 fails\n");
4657 val64
= readq(&bar0
->xgxs_efifo_cfg
);
4658 if (val64
!= 0x000000001923141EULL
) {
4660 DBG_PRINT(INFO_DBG
, "Read Test level 4 fails\n");
4663 val64
= 0x5A5A5A5A5A5A5A5AULL
;
4664 writeq(val64
, &bar0
->xmsi_data
);
4665 val64
= readq(&bar0
->xmsi_data
);
4666 if (val64
!= 0x5A5A5A5A5A5A5A5AULL
) {
4668 DBG_PRINT(ERR_DBG
, "Write Test level 1 fails\n");
4671 val64
= 0xA5A5A5A5A5A5A5A5ULL
;
4672 writeq(val64
, &bar0
->xmsi_data
);
4673 val64
= readq(&bar0
->xmsi_data
);
4674 if (val64
!= 0xA5A5A5A5A5A5A5A5ULL
) {
4676 DBG_PRINT(ERR_DBG
, "Write Test level 2 fails\n");
4684 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
4685 * @sp : private member of the device structure, which is a pointer to the
4686 * s2io_nic structure.
4687 * @data:variable that returns the result of each of the test conducted by
4690 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
4696 static int s2io_eeprom_test(nic_t
* sp
, uint64_t * data
)
4699 u64 ret_data
, org_4F0
, org_7F0
;
4700 u8 saved_4F0
= 0, saved_7F0
= 0;
4701 struct net_device
*dev
= sp
->dev
;
4703 /* Test Write Error at offset 0 */
4704 /* Note that SPI interface allows write access to all areas
4705 * of EEPROM. Hence doing all negative testing only for Xframe I.
4707 if (sp
->device_type
== XFRAME_I_DEVICE
)
4708 if (!write_eeprom(sp
, 0, 0, 3))
4711 /* Save current values at offsets 0x4F0 and 0x7F0 */
4712 if (!read_eeprom(sp
, 0x4F0, &org_4F0
))
4714 if (!read_eeprom(sp
, 0x7F0, &org_7F0
))
4717 /* Test Write at offset 4f0 */
4718 if (write_eeprom(sp
, 0x4F0, 0x012345, 3))
4720 if (read_eeprom(sp
, 0x4F0, &ret_data
))
4723 if (ret_data
!= 0x012345) {
4724 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x4F0. Data written %llx Data read %llx\n", dev
->name
, (u64
)0x12345, ret_data
);
4728 /* Reset the EEPROM data go FFFF */
4729 write_eeprom(sp
, 0x4F0, 0xFFFFFF, 3);
4731 /* Test Write Request Error at offset 0x7c */
4732 if (sp
->device_type
== XFRAME_I_DEVICE
)
4733 if (!write_eeprom(sp
, 0x07C, 0, 3))
4736 /* Test Write Request at offset 0x7f0 */
4737 if (write_eeprom(sp
, 0x7F0, 0x012345, 3))
4739 if (read_eeprom(sp
, 0x7F0, &ret_data
))
4742 if (ret_data
!= 0x012345) {
4743 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x7F0. Data written %llx Data read %llx\n", dev
->name
, (u64
)0x12345, ret_data
);
4747 /* Reset the EEPROM data go FFFF */
4748 write_eeprom(sp
, 0x7F0, 0xFFFFFF, 3);
4750 if (sp
->device_type
== XFRAME_I_DEVICE
) {
4751 /* Test Write Error at offset 0x80 */
4752 if (!write_eeprom(sp
, 0x080, 0, 3))
4755 /* Test Write Error at offset 0xfc */
4756 if (!write_eeprom(sp
, 0x0FC, 0, 3))
4759 /* Test Write Error at offset 0x100 */
4760 if (!write_eeprom(sp
, 0x100, 0, 3))
4763 /* Test Write Error at offset 4ec */
4764 if (!write_eeprom(sp
, 0x4EC, 0, 3))
4768 /* Restore values at offsets 0x4F0 and 0x7F0 */
4770 write_eeprom(sp
, 0x4F0, org_4F0
, 3);
4772 write_eeprom(sp
, 0x7F0, org_7F0
, 3);
4779 * s2io_bist_test - invokes the MemBist test of the card .
4780 * @sp : private member of the device structure, which is a pointer to the
4781 * s2io_nic structure.
4782 * @data:variable that returns the result of each of the test conducted by
4785 * This invokes the MemBist test of the card. We give around
4786 * 2 secs time for the Test to complete. If it's still not complete
4787 * within this peiod, we consider that the test failed.
4789 * 0 on success and -1 on failure.
4792 static int s2io_bist_test(nic_t
* sp
, uint64_t * data
)
4795 int cnt
= 0, ret
= -1;
4797 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
4798 bist
|= PCI_BIST_START
;
4799 pci_write_config_word(sp
->pdev
, PCI_BIST
, bist
);
4802 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
4803 if (!(bist
& PCI_BIST_START
)) {
4804 *data
= (bist
& PCI_BIST_CODE_MASK
);
4816 * s2io-link_test - verifies the link state of the nic
4817 * @sp ; private member of the device structure, which is a pointer to the
4818 * s2io_nic structure.
4819 * @data: variable that returns the result of each of the test conducted by
4822 * The function verifies the link state of the NIC and updates the input
4823 * argument 'data' appropriately.
4828 static int s2io_link_test(nic_t
* sp
, uint64_t * data
)
4830 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4833 val64
= readq(&bar0
->adapter_status
);
4834 if (val64
& ADAPTER_STATUS_RMAC_LOCAL_FAULT
)
4841 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
4842 * @sp - private member of the device structure, which is a pointer to the
4843 * s2io_nic structure.
4844 * @data - variable that returns the result of each of the test
4845 * conducted by the driver.
4847 * This is one of the offline test that tests the read and write
4848 * access to the RldRam chip on the NIC.
4853 static int s2io_rldram_test(nic_t
* sp
, uint64_t * data
)
4855 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
4857 int cnt
, iteration
= 0, test_fail
= 0;
4859 val64
= readq(&bar0
->adapter_control
);
4860 val64
&= ~ADAPTER_ECC_EN
;
4861 writeq(val64
, &bar0
->adapter_control
);
4863 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
4864 val64
|= MC_RLDRAM_TEST_MODE
;
4865 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
4867 val64
= readq(&bar0
->mc_rldram_mrs
);
4868 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
;
4869 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
4871 val64
|= MC_RLDRAM_MRS_ENABLE
;
4872 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
4874 while (iteration
< 2) {
4875 val64
= 0x55555555aaaa0000ULL
;
4876 if (iteration
== 1) {
4877 val64
^= 0xFFFFFFFFFFFF0000ULL
;
4879 writeq(val64
, &bar0
->mc_rldram_test_d0
);
4881 val64
= 0xaaaa5a5555550000ULL
;
4882 if (iteration
== 1) {
4883 val64
^= 0xFFFFFFFFFFFF0000ULL
;
4885 writeq(val64
, &bar0
->mc_rldram_test_d1
);
4887 val64
= 0x55aaaaaaaa5a0000ULL
;
4888 if (iteration
== 1) {
4889 val64
^= 0xFFFFFFFFFFFF0000ULL
;
4891 writeq(val64
, &bar0
->mc_rldram_test_d2
);
4893 val64
= (u64
) (0x0000003ffffe0100ULL
);
4894 writeq(val64
, &bar0
->mc_rldram_test_add
);
4896 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_WRITE
|
4898 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
4900 for (cnt
= 0; cnt
< 5; cnt
++) {
4901 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
4902 if (val64
& MC_RLDRAM_TEST_DONE
)
4910 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_GO
;
4911 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
4913 for (cnt
= 0; cnt
< 5; cnt
++) {
4914 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
4915 if (val64
& MC_RLDRAM_TEST_DONE
)
4923 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
4924 if (!(val64
& MC_RLDRAM_TEST_PASS
))
4932 /* Bring the adapter out of test mode */
4933 SPECIAL_REG_WRITE(0, &bar0
->mc_rldram_test_ctrl
, LF
);
4939 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
4940 * @sp : private member of the device structure, which is a pointer to the
4941 * s2io_nic structure.
4942 * @ethtest : pointer to a ethtool command specific structure that will be
4943 * returned to the user.
4944 * @data : variable that returns the result of each of the test
4945 * conducted by the driver.
4947 * This function conducts 6 tests ( 4 offline and 2 online) to determine
4948 * the health of the card.
4953 static void s2io_ethtool_test(struct net_device
*dev
,
4954 struct ethtool_test
*ethtest
,
4957 nic_t
*sp
= dev
->priv
;
4958 int orig_state
= netif_running(sp
->dev
);
4960 if (ethtest
->flags
== ETH_TEST_FL_OFFLINE
) {
4961 /* Offline Tests. */
4963 s2io_close(sp
->dev
);
4965 if (s2io_register_test(sp
, &data
[0]))
4966 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
4970 if (s2io_rldram_test(sp
, &data
[3]))
4971 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
4975 if (s2io_eeprom_test(sp
, &data
[1]))
4976 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
4978 if (s2io_bist_test(sp
, &data
[4]))
4979 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
4989 "%s: is not up, cannot run test\n",
4998 if (s2io_link_test(sp
, &data
[2]))
4999 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5008 static void s2io_get_ethtool_stats(struct net_device
*dev
,
5009 struct ethtool_stats
*estats
,
5013 nic_t
*sp
= dev
->priv
;
5014 StatInfo_t
*stat_info
= sp
->mac_control
.stats_info
;
5016 s2io_updt_stats(sp
);
5018 (u64
)le32_to_cpu(stat_info
->tmac_frms_oflow
) << 32 |
5019 le32_to_cpu(stat_info
->tmac_frms
);
5021 (u64
)le32_to_cpu(stat_info
->tmac_data_octets_oflow
) << 32 |
5022 le32_to_cpu(stat_info
->tmac_data_octets
);
5023 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_drop_frms
);
5025 (u64
)le32_to_cpu(stat_info
->tmac_mcst_frms_oflow
) << 32 |
5026 le32_to_cpu(stat_info
->tmac_mcst_frms
);
5028 (u64
)le32_to_cpu(stat_info
->tmac_bcst_frms_oflow
) << 32 |
5029 le32_to_cpu(stat_info
->tmac_bcst_frms
);
5030 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_pause_ctrl_frms
);
5032 (u64
)le32_to_cpu(stat_info
->tmac_any_err_frms_oflow
) << 32 |
5033 le32_to_cpu(stat_info
->tmac_any_err_frms
);
5034 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_vld_ip_octets
);
5036 (u64
)le32_to_cpu(stat_info
->tmac_vld_ip_oflow
) << 32 |
5037 le32_to_cpu(stat_info
->tmac_vld_ip
);
5039 (u64
)le32_to_cpu(stat_info
->tmac_drop_ip_oflow
) << 32 |
5040 le32_to_cpu(stat_info
->tmac_drop_ip
);
5042 (u64
)le32_to_cpu(stat_info
->tmac_icmp_oflow
) << 32 |
5043 le32_to_cpu(stat_info
->tmac_icmp
);
5045 (u64
)le32_to_cpu(stat_info
->tmac_rst_tcp_oflow
) << 32 |
5046 le32_to_cpu(stat_info
->tmac_rst_tcp
);
5047 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_tcp
);
5048 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->tmac_udp_oflow
) << 32 |
5049 le32_to_cpu(stat_info
->tmac_udp
);
5051 (u64
)le32_to_cpu(stat_info
->rmac_vld_frms_oflow
) << 32 |
5052 le32_to_cpu(stat_info
->rmac_vld_frms
);
5054 (u64
)le32_to_cpu(stat_info
->rmac_data_octets_oflow
) << 32 |
5055 le32_to_cpu(stat_info
->rmac_data_octets
);
5056 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_fcs_err_frms
);
5057 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_drop_frms
);
5059 (u64
)le32_to_cpu(stat_info
->rmac_vld_mcst_frms_oflow
) << 32 |
5060 le32_to_cpu(stat_info
->rmac_vld_mcst_frms
);
5062 (u64
)le32_to_cpu(stat_info
->rmac_vld_bcst_frms_oflow
) << 32 |
5063 le32_to_cpu(stat_info
->rmac_vld_bcst_frms
);
5064 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_in_rng_len_err_frms
);
5065 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_long_frms
);
5066 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_pause_ctrl_frms
);
5068 (u64
)le32_to_cpu(stat_info
->rmac_discarded_frms_oflow
) << 32 |
5069 le32_to_cpu(stat_info
->rmac_discarded_frms
);
5071 (u64
)le32_to_cpu(stat_info
->rmac_usized_frms_oflow
) << 32 |
5072 le32_to_cpu(stat_info
->rmac_usized_frms
);
5074 (u64
)le32_to_cpu(stat_info
->rmac_osized_frms_oflow
) << 32 |
5075 le32_to_cpu(stat_info
->rmac_osized_frms
);
5077 (u64
)le32_to_cpu(stat_info
->rmac_frag_frms_oflow
) << 32 |
5078 le32_to_cpu(stat_info
->rmac_frag_frms
);
5080 (u64
)le32_to_cpu(stat_info
->rmac_jabber_frms_oflow
) << 32 |
5081 le32_to_cpu(stat_info
->rmac_jabber_frms
);
5082 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->rmac_ip_oflow
) << 32 |
5083 le32_to_cpu(stat_info
->rmac_ip
);
5084 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ip_octets
);
5085 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_hdr_err_ip
);
5086 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->rmac_drop_ip_oflow
) << 32 |
5087 le32_to_cpu(stat_info
->rmac_drop_ip
);
5088 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->rmac_icmp_oflow
) << 32 |
5089 le32_to_cpu(stat_info
->rmac_icmp
);
5090 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_tcp
);
5091 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->rmac_udp_oflow
) << 32 |
5092 le32_to_cpu(stat_info
->rmac_udp
);
5094 (u64
)le32_to_cpu(stat_info
->rmac_err_drp_udp_oflow
) << 32 |
5095 le32_to_cpu(stat_info
->rmac_err_drp_udp
);
5097 (u64
)le32_to_cpu(stat_info
->rmac_pause_cnt_oflow
) << 32 |
5098 le32_to_cpu(stat_info
->rmac_pause_cnt
);
5100 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ip_oflow
) << 32 |
5101 le32_to_cpu(stat_info
->rmac_accepted_ip
);
5102 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_err_tcp
);
5104 tmp_stats
[i
++] = stat_info
->sw_stat
.single_ecc_errs
;
5105 tmp_stats
[i
++] = stat_info
->sw_stat
.double_ecc_errs
;
5108 static int s2io_ethtool_get_regs_len(struct net_device
*dev
)
5110 return (XENA_REG_SPACE
);
5114 static u32
s2io_ethtool_get_rx_csum(struct net_device
* dev
)
5116 nic_t
*sp
= dev
->priv
;
5118 return (sp
->rx_csum
);
5121 static int s2io_ethtool_set_rx_csum(struct net_device
*dev
, u32 data
)
5123 nic_t
*sp
= dev
->priv
;
5133 static int s2io_get_eeprom_len(struct net_device
*dev
)
5135 return (XENA_EEPROM_SPACE
);
5138 static int s2io_ethtool_self_test_count(struct net_device
*dev
)
5140 return (S2IO_TEST_LEN
);
5143 static void s2io_ethtool_get_strings(struct net_device
*dev
,
5144 u32 stringset
, u8
* data
)
5146 switch (stringset
) {
5148 memcpy(data
, s2io_gstrings
, S2IO_STRINGS_LEN
);
5151 memcpy(data
, ðtool_stats_keys
,
5152 sizeof(ethtool_stats_keys
));
5155 static int s2io_ethtool_get_stats_count(struct net_device
*dev
)
5157 return (S2IO_STAT_LEN
);
5160 static int s2io_ethtool_op_set_tx_csum(struct net_device
*dev
, u32 data
)
5163 dev
->features
|= NETIF_F_IP_CSUM
;
5165 dev
->features
&= ~NETIF_F_IP_CSUM
;
5171 static struct ethtool_ops netdev_ethtool_ops
= {
5172 .get_settings
= s2io_ethtool_gset
,
5173 .set_settings
= s2io_ethtool_sset
,
5174 .get_drvinfo
= s2io_ethtool_gdrvinfo
,
5175 .get_regs_len
= s2io_ethtool_get_regs_len
,
5176 .get_regs
= s2io_ethtool_gregs
,
5177 .get_link
= ethtool_op_get_link
,
5178 .get_eeprom_len
= s2io_get_eeprom_len
,
5179 .get_eeprom
= s2io_ethtool_geeprom
,
5180 .set_eeprom
= s2io_ethtool_seeprom
,
5181 .get_pauseparam
= s2io_ethtool_getpause_data
,
5182 .set_pauseparam
= s2io_ethtool_setpause_data
,
5183 .get_rx_csum
= s2io_ethtool_get_rx_csum
,
5184 .set_rx_csum
= s2io_ethtool_set_rx_csum
,
5185 .get_tx_csum
= ethtool_op_get_tx_csum
,
5186 .set_tx_csum
= s2io_ethtool_op_set_tx_csum
,
5187 .get_sg
= ethtool_op_get_sg
,
5188 .set_sg
= ethtool_op_set_sg
,
5190 .get_tso
= ethtool_op_get_tso
,
5191 .set_tso
= ethtool_op_set_tso
,
5193 .self_test_count
= s2io_ethtool_self_test_count
,
5194 .self_test
= s2io_ethtool_test
,
5195 .get_strings
= s2io_ethtool_get_strings
,
5196 .phys_id
= s2io_ethtool_idnic
,
5197 .get_stats_count
= s2io_ethtool_get_stats_count
,
5198 .get_ethtool_stats
= s2io_get_ethtool_stats
5202 * s2io_ioctl - Entry point for the Ioctl
5203 * @dev : Device pointer.
5204 * @ifr : An IOCTL specefic structure, that can contain a pointer to
5205 * a proprietary structure used to pass information to the driver.
5206 * @cmd : This is used to distinguish between the different commands that
5207 * can be passed to the IOCTL functions.
5209 * Currently there are no special functionality supported in IOCTL, hence
5210 * function always return EOPNOTSUPPORTED
5213 static int s2io_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
5219 * s2io_change_mtu - entry point to change MTU size for the device.
5220 * @dev : device pointer.
5221 * @new_mtu : the new MTU size for the device.
5222 * Description: A driver entry point to change MTU size for the device.
5223 * Before changing the MTU the device must be stopped.
5225 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5229 static int s2io_change_mtu(struct net_device
*dev
, int new_mtu
)
5231 nic_t
*sp
= dev
->priv
;
5233 if ((new_mtu
< MIN_MTU
) || (new_mtu
> S2IO_JUMBO_SIZE
)) {
5234 DBG_PRINT(ERR_DBG
, "%s: MTU size is invalid.\n",
5240 if (netif_running(dev
)) {
5242 netif_stop_queue(dev
);
5243 if (s2io_card_up(sp
)) {
5244 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
5247 if (netif_queue_stopped(dev
))
5248 netif_wake_queue(dev
);
5249 } else { /* Device is down */
5250 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
5251 u64 val64
= new_mtu
;
5253 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
5260 * s2io_tasklet - Bottom half of the ISR.
5261 * @dev_adr : address of the device structure in dma_addr_t format.
5263 * This is the tasklet or the bottom half of the ISR. This is
5264 * an extension of the ISR which is scheduled by the scheduler to be run
5265 * when the load on the CPU is low. All low priority tasks of the ISR can
5266 * be pushed into the tasklet. For now the tasklet is used only to
5267 * replenish the Rx buffers in the Rx buffer descriptors.
5272 static void s2io_tasklet(unsigned long dev_addr
)
5274 struct net_device
*dev
= (struct net_device
*) dev_addr
;
5275 nic_t
*sp
= dev
->priv
;
5277 mac_info_t
*mac_control
;
5278 struct config_param
*config
;
5280 mac_control
= &sp
->mac_control
;
5281 config
= &sp
->config
;
5283 if (!TASKLET_IN_USE
) {
5284 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
5285 ret
= fill_rx_buffers(sp
, i
);
5286 if (ret
== -ENOMEM
) {
5287 DBG_PRINT(ERR_DBG
, "%s: Out of ",
5289 DBG_PRINT(ERR_DBG
, "memory in tasklet\n");
5291 } else if (ret
== -EFILL
) {
5293 "%s: Rx Ring %d is full\n",
5298 clear_bit(0, (&sp
->tasklet_status
));
5303 * s2io_set_link - Set the LInk status
5304 * @data: long pointer to device private structue
5305 * Description: Sets the link status for the adapter
5308 static void s2io_set_link(unsigned long data
)
5310 nic_t
*nic
= (nic_t
*) data
;
5311 struct net_device
*dev
= nic
->dev
;
5312 XENA_dev_config_t __iomem
*bar0
= nic
->bar0
;
5316 if (test_and_set_bit(0, &(nic
->link_state
))) {
5317 /* The card is being reset, no point doing anything */
5321 subid
= nic
->pdev
->subsystem_device
;
5322 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
5324 * Allow a small delay for the NICs self initiated
5325 * cleanup to complete.
5330 val64
= readq(&bar0
->adapter_status
);
5331 if (verify_xena_quiescence(nic
, val64
, nic
->device_enabled_once
)) {
5332 if (LINK_IS_UP(val64
)) {
5333 val64
= readq(&bar0
->adapter_control
);
5334 val64
|= ADAPTER_CNTL_EN
;
5335 writeq(val64
, &bar0
->adapter_control
);
5336 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic
->device_type
,
5338 val64
= readq(&bar0
->gpio_control
);
5339 val64
|= GPIO_CTRL_GPIO_0
;
5340 writeq(val64
, &bar0
->gpio_control
);
5341 val64
= readq(&bar0
->gpio_control
);
5343 val64
|= ADAPTER_LED_ON
;
5344 writeq(val64
, &bar0
->adapter_control
);
5346 if (s2io_link_fault_indication(nic
) ==
5347 MAC_RMAC_ERR_TIMER
) {
5348 val64
= readq(&bar0
->adapter_status
);
5349 if (!LINK_IS_UP(val64
)) {
5350 DBG_PRINT(ERR_DBG
, "%s:", dev
->name
);
5351 DBG_PRINT(ERR_DBG
, " Link down");
5352 DBG_PRINT(ERR_DBG
, "after ");
5353 DBG_PRINT(ERR_DBG
, "enabling ");
5354 DBG_PRINT(ERR_DBG
, "device \n");
5357 if (nic
->device_enabled_once
== FALSE
) {
5358 nic
->device_enabled_once
= TRUE
;
5360 s2io_link(nic
, LINK_UP
);
5362 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic
->device_type
,
5364 val64
= readq(&bar0
->gpio_control
);
5365 val64
&= ~GPIO_CTRL_GPIO_0
;
5366 writeq(val64
, &bar0
->gpio_control
);
5367 val64
= readq(&bar0
->gpio_control
);
5369 s2io_link(nic
, LINK_DOWN
);
5371 } else { /* NIC is not Quiescent. */
5372 DBG_PRINT(ERR_DBG
, "%s: Error: ", dev
->name
);
5373 DBG_PRINT(ERR_DBG
, "device is not Quiescent\n");
5374 netif_stop_queue(dev
);
5376 clear_bit(0, &(nic
->link_state
));
5379 static void s2io_card_down(nic_t
* sp
)
5382 XENA_dev_config_t __iomem
*bar0
= sp
->bar0
;
5383 unsigned long flags
;
5384 register u64 val64
= 0;
5386 del_timer_sync(&sp
->alarm_timer
);
5387 /* If s2io_set_link task is executing, wait till it completes. */
5388 while (test_and_set_bit(0, &(sp
->link_state
))) {
5391 atomic_set(&sp
->card_state
, CARD_DOWN
);
5393 /* disable Tx and Rx traffic on the NIC */
5397 tasklet_kill(&sp
->task
);
5399 /* Check if the device is Quiescent and then Reset the NIC */
5401 val64
= readq(&bar0
->adapter_status
);
5402 if (verify_xena_quiescence(sp
, val64
, sp
->device_enabled_once
)) {
5410 "s2io_close:Device not Quiescent ");
5411 DBG_PRINT(ERR_DBG
, "adaper status reads 0x%llx\n",
5412 (unsigned long long) val64
);
5418 /* Waiting till all Interrupt handlers are complete */
5422 if (!atomic_read(&sp
->isr_cnt
))
5427 spin_lock_irqsave(&sp
->tx_lock
, flags
);
5428 /* Free all Tx buffers */
5429 free_tx_buffers(sp
);
5430 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
5432 /* Free all Rx buffers */
5433 spin_lock_irqsave(&sp
->rx_lock
, flags
);
5434 free_rx_buffers(sp
);
5435 spin_unlock_irqrestore(&sp
->rx_lock
, flags
);
5437 clear_bit(0, &(sp
->link_state
));
5440 static int s2io_card_up(nic_t
* sp
)
5443 mac_info_t
*mac_control
;
5444 struct config_param
*config
;
5445 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
5447 /* Initialize the H/W I/O registers */
5448 if (init_nic(sp
) != 0) {
5449 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
5454 if (sp
->intr_type
== MSI
)
5455 ret
= s2io_enable_msi(sp
);
5456 else if (sp
->intr_type
== MSI_X
)
5457 ret
= s2io_enable_msi_x(sp
);
5459 DBG_PRINT(ERR_DBG
, "%s: Defaulting to INTA\n", dev
->name
);
5460 sp
->intr_type
= INTA
;
5464 * Initializing the Rx buffers. For now we are considering only 1
5465 * Rx ring and initializing buffers into 30 Rx blocks
5467 mac_control
= &sp
->mac_control
;
5468 config
= &sp
->config
;
5470 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
5471 if ((ret
= fill_rx_buffers(sp
, i
))) {
5472 DBG_PRINT(ERR_DBG
, "%s: Out of memory in Open\n",
5475 free_rx_buffers(sp
);
5478 DBG_PRINT(INFO_DBG
, "Buf in ring:%d is %d:\n", i
,
5479 atomic_read(&sp
->rx_bufs_left
[i
]));
5482 /* Setting its receive mode */
5483 s2io_set_multicast(dev
);
5485 /* Enable tasklet for the device */
5486 tasklet_init(&sp
->task
, s2io_tasklet
, (unsigned long) dev
);
5488 /* Enable Rx Traffic and interrupts on the NIC */
5489 if (start_nic(sp
)) {
5490 DBG_PRINT(ERR_DBG
, "%s: Starting NIC failed\n", dev
->name
);
5491 tasklet_kill(&sp
->task
);
5493 free_irq(dev
->irq
, dev
);
5494 free_rx_buffers(sp
);
5498 S2IO_TIMER_CONF(sp
->alarm_timer
, s2io_alarm_handle
, sp
, (HZ
/2));
5500 atomic_set(&sp
->card_state
, CARD_UP
);
5505 * s2io_restart_nic - Resets the NIC.
5506 * @data : long pointer to the device private structure
5508 * This function is scheduled to be run by the s2io_tx_watchdog
5509 * function after 0.5 secs to reset the NIC. The idea is to reduce
5510 * the run time of the watch dog routine which is run holding a
5514 static void s2io_restart_nic(unsigned long data
)
5516 struct net_device
*dev
= (struct net_device
*) data
;
5517 nic_t
*sp
= dev
->priv
;
5520 if (s2io_card_up(sp
)) {
5521 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
5524 netif_wake_queue(dev
);
5525 DBG_PRINT(ERR_DBG
, "%s: was reset by Tx watchdog timer\n",
5531 * s2io_tx_watchdog - Watchdog for transmit side.
5532 * @dev : Pointer to net device structure
5534 * This function is triggered if the Tx Queue is stopped
5535 * for a pre-defined amount of time when the Interface is still up.
5536 * If the Interface is jammed in such a situation, the hardware is
5537 * reset (by s2io_close) and restarted again (by s2io_open) to
5538 * overcome any problem that might have been caused in the hardware.
5543 static void s2io_tx_watchdog(struct net_device
*dev
)
5545 nic_t
*sp
= dev
->priv
;
5547 if (netif_carrier_ok(dev
)) {
5548 schedule_work(&sp
->rst_timer_task
);
5553 * rx_osm_handler - To perform some OS related operations on SKB.
5554 * @sp: private member of the device structure,pointer to s2io_nic structure.
5555 * @skb : the socket buffer pointer.
5556 * @len : length of the packet
5557 * @cksum : FCS checksum of the frame.
5558 * @ring_no : the ring from which this RxD was extracted.
5560 * This function is called by the Tx interrupt serivce routine to perform
5561 * some OS related operations on the SKB before passing it to the upper
5562 * layers. It mainly checks if the checksum is OK, if so adds it to the
5563 * SKBs cksum variable, increments the Rx packet count and passes the SKB
5564 * to the upper layer. If the checksum is wrong, it increments the Rx
5565 * packet error count, frees the SKB and returns error.
5567 * SUCCESS on success and -1 on failure.
5569 static int rx_osm_handler(ring_info_t
*ring_data
, RxD_t
* rxdp
)
5571 nic_t
*sp
= ring_data
->nic
;
5572 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
5573 struct sk_buff
*skb
= (struct sk_buff
*)
5574 ((unsigned long) rxdp
->Host_Control
);
5575 int ring_no
= ring_data
->ring_no
;
5576 u16 l3_csum
, l4_csum
;
5579 if (rxdp
->Control_1
& RXD_T_CODE
) {
5580 unsigned long long err
= rxdp
->Control_1
& RXD_T_CODE
;
5581 DBG_PRINT(ERR_DBG
, "%s: Rx error Value: 0x%llx\n",
5584 sp
->stats
.rx_crc_errors
++;
5585 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
5586 rxdp
->Host_Control
= 0;
5590 /* Updating statistics */
5591 rxdp
->Host_Control
= 0;
5593 sp
->stats
.rx_packets
++;
5594 if (sp
->rxd_mode
== RXD_MODE_1
) {
5595 int len
= RXD_GET_BUFFER0_SIZE_1(rxdp
->Control_2
);
5597 sp
->stats
.rx_bytes
+= len
;
5600 } else if (sp
->rxd_mode
>= RXD_MODE_3A
) {
5601 int get_block
= ring_data
->rx_curr_get_info
.block_index
;
5602 int get_off
= ring_data
->rx_curr_get_info
.offset
;
5603 int buf0_len
= RXD_GET_BUFFER0_SIZE_3(rxdp
->Control_2
);
5604 int buf2_len
= RXD_GET_BUFFER2_SIZE_3(rxdp
->Control_2
);
5605 unsigned char *buff
= skb_push(skb
, buf0_len
);
5607 buffAdd_t
*ba
= &ring_data
->ba
[get_block
][get_off
];
5608 sp
->stats
.rx_bytes
+= buf0_len
+ buf2_len
;
5609 memcpy(buff
, ba
->ba_0
, buf0_len
);
5611 if (sp
->rxd_mode
== RXD_MODE_3A
) {
5612 int buf1_len
= RXD_GET_BUFFER1_SIZE_3(rxdp
->Control_2
);
5614 skb_put(skb
, buf1_len
);
5615 skb
->len
+= buf2_len
;
5616 skb
->data_len
+= buf2_len
;
5617 skb
->truesize
+= buf2_len
;
5618 skb_put(skb_shinfo(skb
)->frag_list
, buf2_len
);
5619 sp
->stats
.rx_bytes
+= buf1_len
;
5622 skb_put(skb
, buf2_len
);
5625 if ((rxdp
->Control_1
& TCP_OR_UDP_FRAME
) &&
5627 l3_csum
= RXD_GET_L3_CKSUM(rxdp
->Control_1
);
5628 l4_csum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
5629 if ((l3_csum
== L3_CKSUM_OK
) && (l4_csum
== L4_CKSUM_OK
)) {
5631 * NIC verifies if the Checksum of the received
5632 * frame is Ok or not and accordingly returns
5633 * a flag in the RxD.
5635 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5638 * Packet with erroneous checksum, let the
5639 * upper layers deal with it.
5641 skb
->ip_summed
= CHECKSUM_NONE
;
5644 skb
->ip_summed
= CHECKSUM_NONE
;
5647 skb
->protocol
= eth_type_trans(skb
, dev
);
5648 #ifdef CONFIG_S2IO_NAPI
5649 if (sp
->vlgrp
&& RXD_GET_VLAN_TAG(rxdp
->Control_2
)) {
5650 /* Queueing the vlan frame to the upper layer */
5651 vlan_hwaccel_receive_skb(skb
, sp
->vlgrp
,
5652 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
5654 netif_receive_skb(skb
);
5657 if (sp
->vlgrp
&& RXD_GET_VLAN_TAG(rxdp
->Control_2
)) {
5658 /* Queueing the vlan frame to the upper layer */
5659 vlan_hwaccel_rx(skb
, sp
->vlgrp
,
5660 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
5665 dev
->last_rx
= jiffies
;
5666 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
5671 * s2io_link - stops/starts the Tx queue.
5672 * @sp : private member of the device structure, which is a pointer to the
5673 * s2io_nic structure.
5674 * @link : inidicates whether link is UP/DOWN.
5676 * This function stops/starts the Tx queue depending on whether the link
5677 * status of the NIC is is down or up. This is called by the Alarm
5678 * interrupt handler whenever a link change interrupt comes up.
5683 void s2io_link(nic_t
* sp
, int link
)
5685 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
5687 if (link
!= sp
->last_link_state
) {
5688 if (link
== LINK_DOWN
) {
5689 DBG_PRINT(ERR_DBG
, "%s: Link down\n", dev
->name
);
5690 netif_carrier_off(dev
);
5692 DBG_PRINT(ERR_DBG
, "%s: Link Up\n", dev
->name
);
5693 netif_carrier_on(dev
);
5696 sp
->last_link_state
= link
;
5700 * get_xena_rev_id - to identify revision ID of xena.
5701 * @pdev : PCI Dev structure
5703 * Function to identify the Revision ID of xena.
5705 * returns the revision ID of the device.
5708 int get_xena_rev_id(struct pci_dev
*pdev
)
5712 ret
= pci_read_config_byte(pdev
, PCI_REVISION_ID
, (u8
*) & id
);
5717 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
5718 * @sp : private member of the device structure, which is a pointer to the
5719 * s2io_nic structure.
5721 * This function initializes a few of the PCI and PCI-X configuration registers
5722 * with recommended values.
5727 static void s2io_init_pci(nic_t
* sp
)
5729 u16 pci_cmd
= 0, pcix_cmd
= 0;
5731 /* Enable Data Parity Error Recovery in PCI-X command register. */
5732 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
5734 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
5736 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
5739 /* Set the PErr Response bit in PCI command register. */
5740 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
5741 pci_write_config_word(sp
->pdev
, PCI_COMMAND
,
5742 (pci_cmd
| PCI_COMMAND_PARITY
));
5743 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
5745 /* Forcibly disabling relaxed ordering capability of the card. */
5747 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
5749 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
5753 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
5754 MODULE_LICENSE("GPL");
5755 MODULE_VERSION(DRV_VERSION
);
5757 module_param(tx_fifo_num
, int, 0);
5758 module_param(rx_ring_num
, int, 0);
5759 module_param(rx_ring_mode
, int, 0);
5760 module_param_array(tx_fifo_len
, uint
, NULL
, 0);
5761 module_param_array(rx_ring_sz
, uint
, NULL
, 0);
5762 module_param_array(rts_frm_len
, uint
, NULL
, 0);
5763 module_param(use_continuous_tx_intrs
, int, 1);
5764 module_param(rmac_pause_time
, int, 0);
5765 module_param(mc_pause_threshold_q0q3
, int, 0);
5766 module_param(mc_pause_threshold_q4q7
, int, 0);
5767 module_param(shared_splits
, int, 0);
5768 module_param(tmac_util_period
, int, 0);
5769 module_param(rmac_util_period
, int, 0);
5770 module_param(bimodal
, bool, 0);
5771 module_param(l3l4hdr_size
, int , 0);
5772 #ifndef CONFIG_S2IO_NAPI
5773 module_param(indicate_max_pkts
, int, 0);
5775 module_param(rxsync_frequency
, int, 0);
5776 module_param(intr_type
, int, 0);
5779 * s2io_init_nic - Initialization of the adapter .
5780 * @pdev : structure containing the PCI related information of the device.
5781 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
5783 * The function initializes an adapter identified by the pci_dec structure.
5784 * All OS related initialization including memory and device structure and
5785 * initlaization of the device private variable is done. Also the swapper
5786 * control register is initialized to enable read and write into the I/O
5787 * registers of the device.
5789 * returns 0 on success and negative on failure.
5792 static int __devinit
5793 s2io_init_nic(struct pci_dev
*pdev
, const struct pci_device_id
*pre
)
5796 struct net_device
*dev
;
5798 int dma_flag
= FALSE
;
5799 u32 mac_up
, mac_down
;
5800 u64 val64
= 0, tmp64
= 0;
5801 XENA_dev_config_t __iomem
*bar0
= NULL
;
5803 mac_info_t
*mac_control
;
5804 struct config_param
*config
;
5806 u8 dev_intr_type
= intr_type
;
5808 #ifdef CONFIG_S2IO_NAPI
5809 if (dev_intr_type
!= INTA
) {
5810 DBG_PRINT(ERR_DBG
, "NAPI cannot be enabled when MSI/MSI-X \
5811 is enabled. Defaulting to INTA\n");
5812 dev_intr_type
= INTA
;
5815 DBG_PRINT(ERR_DBG
, "NAPI support has been enabled\n");
5818 if ((ret
= pci_enable_device(pdev
))) {
5820 "s2io_init_nic: pci_enable_device failed\n");
5824 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
5825 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 64bit DMA\n");
5827 if (pci_set_consistent_dma_mask
5828 (pdev
, DMA_64BIT_MASK
)) {
5830 "Unable to obtain 64bit DMA for \
5831 consistent allocations\n");
5832 pci_disable_device(pdev
);
5835 } else if (!pci_set_dma_mask(pdev
, DMA_32BIT_MASK
)) {
5836 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 32bit DMA\n");
5838 pci_disable_device(pdev
);
5842 if ((dev_intr_type
== MSI_X
) &&
5843 ((pdev
->device
!= PCI_DEVICE_ID_HERC_WIN
) &&
5844 (pdev
->device
!= PCI_DEVICE_ID_HERC_UNI
))) {
5845 DBG_PRINT(ERR_DBG
, "Xframe I does not support MSI_X. \
5846 Defaulting to INTA\n");
5847 dev_intr_type
= INTA
;
5849 if (dev_intr_type
!= MSI_X
) {
5850 if (pci_request_regions(pdev
, s2io_driver_name
)) {
5851 DBG_PRINT(ERR_DBG
, "Request Regions failed\n"),
5852 pci_disable_device(pdev
);
5857 if (!(request_mem_region(pci_resource_start(pdev
, 0),
5858 pci_resource_len(pdev
, 0), s2io_driver_name
))) {
5859 DBG_PRINT(ERR_DBG
, "bar0 Request Regions failed\n");
5860 pci_disable_device(pdev
);
5863 if (!(request_mem_region(pci_resource_start(pdev
, 2),
5864 pci_resource_len(pdev
, 2), s2io_driver_name
))) {
5865 DBG_PRINT(ERR_DBG
, "bar1 Request Regions failed\n");
5866 release_mem_region(pci_resource_start(pdev
, 0),
5867 pci_resource_len(pdev
, 0));
5868 pci_disable_device(pdev
);
5873 dev
= alloc_etherdev(sizeof(nic_t
));
5875 DBG_PRINT(ERR_DBG
, "Device allocation failed\n");
5876 pci_disable_device(pdev
);
5877 pci_release_regions(pdev
);
5881 pci_set_master(pdev
);
5882 pci_set_drvdata(pdev
, dev
);
5883 SET_MODULE_OWNER(dev
);
5884 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5886 /* Private member variable initialized to s2io NIC structure */
5888 memset(sp
, 0, sizeof(nic_t
));
5891 sp
->high_dma_flag
= dma_flag
;
5892 sp
->device_enabled_once
= FALSE
;
5893 if (rx_ring_mode
== 1)
5894 sp
->rxd_mode
= RXD_MODE_1
;
5895 if (rx_ring_mode
== 2)
5896 sp
->rxd_mode
= RXD_MODE_3B
;
5897 if (rx_ring_mode
== 3)
5898 sp
->rxd_mode
= RXD_MODE_3A
;
5900 sp
->intr_type
= dev_intr_type
;
5902 if ((pdev
->device
== PCI_DEVICE_ID_HERC_WIN
) ||
5903 (pdev
->device
== PCI_DEVICE_ID_HERC_UNI
))
5904 sp
->device_type
= XFRAME_II_DEVICE
;
5906 sp
->device_type
= XFRAME_I_DEVICE
;
5909 /* Initialize some PCI/PCI-X fields of the NIC. */
5913 * Setting the device configuration parameters.
5914 * Most of these parameters can be specified by the user during
5915 * module insertion as they are module loadable parameters. If
5916 * these parameters are not not specified during load time, they
5917 * are initialized with default values.
5919 mac_control
= &sp
->mac_control
;
5920 config
= &sp
->config
;
5922 /* Tx side parameters. */
5923 if (tx_fifo_len
[0] == 0)
5924 tx_fifo_len
[0] = DEFAULT_FIFO_LEN
; /* Default value. */
5925 config
->tx_fifo_num
= tx_fifo_num
;
5926 for (i
= 0; i
< MAX_TX_FIFOS
; i
++) {
5927 config
->tx_cfg
[i
].fifo_len
= tx_fifo_len
[i
];
5928 config
->tx_cfg
[i
].fifo_priority
= i
;
5931 /* mapping the QoS priority to the configured fifos */
5932 for (i
= 0; i
< MAX_TX_FIFOS
; i
++)
5933 config
->fifo_mapping
[i
] = fifo_map
[config
->tx_fifo_num
][i
];
5935 config
->tx_intr_type
= TXD_INT_TYPE_UTILZ
;
5936 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
5937 config
->tx_cfg
[i
].f_no_snoop
=
5938 (NO_SNOOP_TXD
| NO_SNOOP_TXD_BUFFER
);
5939 if (config
->tx_cfg
[i
].fifo_len
< 65) {
5940 config
->tx_intr_type
= TXD_INT_TYPE_PER_LIST
;
5944 config
->max_txds
= MAX_SKB_FRAGS
+ 1;
5946 /* Rx side parameters. */
5947 if (rx_ring_sz
[0] == 0)
5948 rx_ring_sz
[0] = SMALL_BLK_CNT
; /* Default value. */
5949 config
->rx_ring_num
= rx_ring_num
;
5950 for (i
= 0; i
< MAX_RX_RINGS
; i
++) {
5951 config
->rx_cfg
[i
].num_rxd
= rx_ring_sz
[i
] *
5952 (rxd_count
[sp
->rxd_mode
] + 1);
5953 config
->rx_cfg
[i
].ring_priority
= i
;
5956 for (i
= 0; i
< rx_ring_num
; i
++) {
5957 config
->rx_cfg
[i
].ring_org
= RING_ORG_BUFF1
;
5958 config
->rx_cfg
[i
].f_no_snoop
=
5959 (NO_SNOOP_RXD
| NO_SNOOP_RXD_BUFFER
);
5962 /* Setting Mac Control parameters */
5963 mac_control
->rmac_pause_time
= rmac_pause_time
;
5964 mac_control
->mc_pause_threshold_q0q3
= mc_pause_threshold_q0q3
;
5965 mac_control
->mc_pause_threshold_q4q7
= mc_pause_threshold_q4q7
;
5968 /* Initialize Ring buffer parameters. */
5969 for (i
= 0; i
< config
->rx_ring_num
; i
++)
5970 atomic_set(&sp
->rx_bufs_left
[i
], 0);
5972 /* Initialize the number of ISRs currently running */
5973 atomic_set(&sp
->isr_cnt
, 0);
5975 /* initialize the shared memory used by the NIC and the host */
5976 if (init_shared_mem(sp
)) {
5977 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n",
5980 goto mem_alloc_failed
;
5983 sp
->bar0
= ioremap(pci_resource_start(pdev
, 0),
5984 pci_resource_len(pdev
, 0));
5986 DBG_PRINT(ERR_DBG
, "%s: S2IO: cannot remap io mem1\n",
5989 goto bar0_remap_failed
;
5992 sp
->bar1
= ioremap(pci_resource_start(pdev
, 2),
5993 pci_resource_len(pdev
, 2));
5995 DBG_PRINT(ERR_DBG
, "%s: S2IO: cannot remap io mem2\n",
5998 goto bar1_remap_failed
;
6001 dev
->irq
= pdev
->irq
;
6002 dev
->base_addr
= (unsigned long) sp
->bar0
;
6004 /* Initializing the BAR1 address as the start of the FIFO pointer. */
6005 for (j
= 0; j
< MAX_TX_FIFOS
; j
++) {
6006 mac_control
->tx_FIFO_start
[j
] = (TxFIFO_element_t __iomem
*)
6007 (sp
->bar1
+ (j
* 0x00020000));
6010 /* Driver entry points */
6011 dev
->open
= &s2io_open
;
6012 dev
->stop
= &s2io_close
;
6013 dev
->hard_start_xmit
= &s2io_xmit
;
6014 dev
->get_stats
= &s2io_get_stats
;
6015 dev
->set_multicast_list
= &s2io_set_multicast
;
6016 dev
->do_ioctl
= &s2io_ioctl
;
6017 dev
->change_mtu
= &s2io_change_mtu
;
6018 SET_ETHTOOL_OPS(dev
, &netdev_ethtool_ops
);
6019 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
6020 dev
->vlan_rx_register
= s2io_vlan_rx_register
;
6021 dev
->vlan_rx_kill_vid
= (void *)s2io_vlan_rx_kill_vid
;
6024 * will use eth_mac_addr() for dev->set_mac_address
6025 * mac address will be set every time dev->open() is called
6027 #if defined(CONFIG_S2IO_NAPI)
6028 dev
->poll
= s2io_poll
;
6032 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
6033 if (sp
->high_dma_flag
== TRUE
)
6034 dev
->features
|= NETIF_F_HIGHDMA
;
6036 dev
->features
|= NETIF_F_TSO
;
6039 dev
->tx_timeout
= &s2io_tx_watchdog
;
6040 dev
->watchdog_timeo
= WATCH_DOG_TIMEOUT
;
6041 INIT_WORK(&sp
->rst_timer_task
,
6042 (void (*)(void *)) s2io_restart_nic
, dev
);
6043 INIT_WORK(&sp
->set_link_task
,
6044 (void (*)(void *)) s2io_set_link
, sp
);
6046 pci_save_state(sp
->pdev
);
6048 /* Setting swapper control on the NIC, for proper reset operation */
6049 if (s2io_set_swapper(sp
)) {
6050 DBG_PRINT(ERR_DBG
, "%s:swapper settings are wrong\n",
6053 goto set_swap_failed
;
6056 /* Verify if the Herc works on the slot its placed into */
6057 if (sp
->device_type
& XFRAME_II_DEVICE
) {
6058 mode
= s2io_verify_pci_mode(sp
);
6060 DBG_PRINT(ERR_DBG
, "%s: ", __FUNCTION__
);
6061 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
6063 goto set_swap_failed
;
6067 /* Not needed for Herc */
6068 if (sp
->device_type
& XFRAME_I_DEVICE
) {
6070 * Fix for all "FFs" MAC address problems observed on
6073 fix_mac_address(sp
);
6078 * MAC address initialization.
6079 * For now only one mac address will be read and used.
6082 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
6083 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET
);
6084 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
6085 wait_for_cmd_complete(sp
);
6087 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
6088 mac_down
= (u32
) tmp64
;
6089 mac_up
= (u32
) (tmp64
>> 32);
6091 memset(sp
->def_mac_addr
[0].mac_addr
, 0, sizeof(ETH_ALEN
));
6093 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_up
);
6094 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_up
>> 8);
6095 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_up
>> 16);
6096 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_up
>> 24);
6097 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_down
>> 16);
6098 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_down
>> 24);
6100 /* Set the factory defined MAC address initially */
6101 dev
->addr_len
= ETH_ALEN
;
6102 memcpy(dev
->dev_addr
, sp
->def_mac_addr
, ETH_ALEN
);
6105 * Initialize the tasklet status and link state flags
6106 * and the card state parameter
6108 atomic_set(&(sp
->card_state
), 0);
6109 sp
->tasklet_status
= 0;
6112 /* Initialize spinlocks */
6113 spin_lock_init(&sp
->tx_lock
);
6114 #ifndef CONFIG_S2IO_NAPI
6115 spin_lock_init(&sp
->put_lock
);
6117 spin_lock_init(&sp
->rx_lock
);
6120 * SXE-002: Configure link and activity LED to init state
6123 subid
= sp
->pdev
->subsystem_device
;
6124 if ((subid
& 0xFF) >= 0x07) {
6125 val64
= readq(&bar0
->gpio_control
);
6126 val64
|= 0x0000800000000000ULL
;
6127 writeq(val64
, &bar0
->gpio_control
);
6128 val64
= 0x0411040400000000ULL
;
6129 writeq(val64
, (void __iomem
*) bar0
+ 0x2700);
6130 val64
= readq(&bar0
->gpio_control
);
6133 sp
->rx_csum
= 1; /* Rx chksum verify enabled by default */
6135 if (register_netdev(dev
)) {
6136 DBG_PRINT(ERR_DBG
, "Device registration failed\n");
6138 goto register_failed
;
6141 if (sp
->device_type
& XFRAME_II_DEVICE
) {
6142 DBG_PRINT(ERR_DBG
, "%s: Neterion Xframe II 10GbE adapter ",
6144 DBG_PRINT(ERR_DBG
, "(rev %d), Version %s",
6145 get_xena_rev_id(sp
->pdev
),
6146 s2io_driver_version
);
6147 switch(sp
->intr_type
) {
6149 DBG_PRINT(ERR_DBG
, ", Intr type INTA");
6152 DBG_PRINT(ERR_DBG
, ", Intr type MSI");
6155 DBG_PRINT(ERR_DBG
, ", Intr type MSI-X");
6159 DBG_PRINT(ERR_DBG
, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6160 DBG_PRINT(ERR_DBG
, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6161 sp
->def_mac_addr
[0].mac_addr
[0],
6162 sp
->def_mac_addr
[0].mac_addr
[1],
6163 sp
->def_mac_addr
[0].mac_addr
[2],
6164 sp
->def_mac_addr
[0].mac_addr
[3],
6165 sp
->def_mac_addr
[0].mac_addr
[4],
6166 sp
->def_mac_addr
[0].mac_addr
[5]);
6167 mode
= s2io_print_pci_mode(sp
);
6169 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode ");
6171 goto set_swap_failed
;
6174 DBG_PRINT(ERR_DBG
, "%s: Neterion Xframe I 10GbE adapter ",
6176 DBG_PRINT(ERR_DBG
, "(rev %d), Version %s",
6177 get_xena_rev_id(sp
->pdev
),
6178 s2io_driver_version
);
6179 switch(sp
->intr_type
) {
6181 DBG_PRINT(ERR_DBG
, ", Intr type INTA");
6184 DBG_PRINT(ERR_DBG
, ", Intr type MSI");
6187 DBG_PRINT(ERR_DBG
, ", Intr type MSI-X");
6190 DBG_PRINT(ERR_DBG
, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6191 DBG_PRINT(ERR_DBG
, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6192 sp
->def_mac_addr
[0].mac_addr
[0],
6193 sp
->def_mac_addr
[0].mac_addr
[1],
6194 sp
->def_mac_addr
[0].mac_addr
[2],
6195 sp
->def_mac_addr
[0].mac_addr
[3],
6196 sp
->def_mac_addr
[0].mac_addr
[4],
6197 sp
->def_mac_addr
[0].mac_addr
[5]);
6199 if (sp
->rxd_mode
== RXD_MODE_3B
)
6200 DBG_PRINT(ERR_DBG
, "%s: 2-Buffer mode support has been "
6201 "enabled\n",dev
->name
);
6202 if (sp
->rxd_mode
== RXD_MODE_3A
)
6203 DBG_PRINT(ERR_DBG
, "%s: 3-Buffer mode support has been "
6204 "enabled\n",dev
->name
);
6206 /* Initialize device name */
6207 strcpy(sp
->name
, dev
->name
);
6208 if (sp
->device_type
& XFRAME_II_DEVICE
)
6209 strcat(sp
->name
, ": Neterion Xframe II 10GbE adapter");
6211 strcat(sp
->name
, ": Neterion Xframe I 10GbE adapter");
6213 /* Initialize bimodal Interrupts */
6214 sp
->config
.bimodal
= bimodal
;
6215 if (!(sp
->device_type
& XFRAME_II_DEVICE
) && bimodal
) {
6216 sp
->config
.bimodal
= 0;
6217 DBG_PRINT(ERR_DBG
,"%s:Bimodal intr not supported by Xframe I\n",
6222 * Make Link state as off at this point, when the Link change
6223 * interrupt comes the state will be automatically changed to
6226 netif_carrier_off(dev
);
6237 free_shared_mem(sp
);
6238 pci_disable_device(pdev
);
6239 if (dev_intr_type
!= MSI_X
)
6240 pci_release_regions(pdev
);
6242 release_mem_region(pci_resource_start(pdev
, 0),
6243 pci_resource_len(pdev
, 0));
6244 release_mem_region(pci_resource_start(pdev
, 2),
6245 pci_resource_len(pdev
, 2));
6247 pci_set_drvdata(pdev
, NULL
);
6254 * s2io_rem_nic - Free the PCI device
6255 * @pdev: structure containing the PCI related information of the device.
6256 * Description: This function is called by the Pci subsystem to release a
6257 * PCI device and free up all resource held up by the device. This could
6258 * be in response to a Hot plug event or when the driver is to be removed
6262 static void __devexit
s2io_rem_nic(struct pci_dev
*pdev
)
6264 struct net_device
*dev
=
6265 (struct net_device
*) pci_get_drvdata(pdev
);
6269 DBG_PRINT(ERR_DBG
, "Driver Data is NULL!!\n");
6274 unregister_netdev(dev
);
6276 free_shared_mem(sp
);
6279 pci_disable_device(pdev
);
6280 if (sp
->intr_type
!= MSI_X
)
6281 pci_release_regions(pdev
);
6283 release_mem_region(pci_resource_start(pdev
, 0),
6284 pci_resource_len(pdev
, 0));
6285 release_mem_region(pci_resource_start(pdev
, 2),
6286 pci_resource_len(pdev
, 2));
6288 pci_set_drvdata(pdev
, NULL
);
6293 * s2io_starter - Entry point for the driver
6294 * Description: This function is the entry point for the driver. It verifies
6295 * the module loadable parameters and initializes PCI configuration space.
6298 int __init
s2io_starter(void)
6300 return pci_module_init(&s2io_driver
);
6304 * s2io_closer - Cleanup routine for the driver
6305 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
6308 void s2io_closer(void)
6310 pci_unregister_driver(&s2io_driver
);
6311 DBG_PRINT(INIT_DBG
, "cleanup done\n");
6314 module_init(s2io_starter
);
6315 module_exit(s2io_closer
);