drivers/net/s2io.h

   1 /************************************************************************
   2  * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  ************************************************************************/
  13 #ifndef _S2IO_H
  14 #define _S2IO_H
  15
  16 #define TBD 0
  17 #define BIT(loc)                (0x8000000000000000ULL >> (loc))
  18 #define vBIT(val, loc, sz)      (((u64)val) << (64-loc-sz))
  19 #define INV(d)  ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
  20
  21 #ifndef BOOL
  22 #define BOOL    int
  23 #endif
  24
  25 #ifndef TRUE
  26 #define TRUE    1
  27 #define FALSE   0
  28 #endif
  29
  30 #undef SUCCESS
  31 #define SUCCESS 0
  32 #define FAILURE -1
  33 #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
  34 #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
  35
  36 #define CHECKBIT(value, nbit) (value & (1 << nbit))
  37
  38 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
  39 #define MAX_FLICKER_TIME        60000 /* 60 Secs */
  40
  41 /* Maximum outstanding splits to be configured into xena. */
  42 enum {
  43         XENA_ONE_SPLIT_TRANSACTION = 0,
  44         XENA_TWO_SPLIT_TRANSACTION = 1,
  45         XENA_THREE_SPLIT_TRANSACTION = 2,
  46         XENA_FOUR_SPLIT_TRANSACTION = 3,
  47         XENA_EIGHT_SPLIT_TRANSACTION = 4,
  48         XENA_TWELVE_SPLIT_TRANSACTION = 5,
  49         XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  50         XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  51 };
  52 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  53
  54 /*  OS concerned variables and constants */
  55 #define WATCH_DOG_TIMEOUT               15*HZ
  56 #define EFILL                           0x1234
  57 #define ALIGN_SIZE                      127
  58 #define PCIX_COMMAND_REGISTER           0x62
  59
  60 /*
  61  * Debug related variables.
  62  */
  63 /* different debug levels. */
  64 #define ERR_DBG         0
  65 #define INIT_DBG        1
  66 #define INFO_DBG        2
  67 #define TX_DBG          3
  68 #define INTR_DBG        4
  69
  70 /* Global variable that defines the present debug level of the driver. */
  71 static int debug_level = ERR_DBG;
  72
  73 /* DEBUG message print. */
  74 #define DBG_PRINT(dbg_level, args...)  if(!(debug_level<dbg_level)) printk(args)
  75
  76 /* Protocol assist features of the NIC */
  77 #define L3_CKSUM_OK 0xFFFF
  78 #define L4_CKSUM_OK 0xFFFF
  79 #define S2IO_JUMBO_SIZE 9600
  80
  81 /* Driver statistics maintained by driver */
  82 struct swStat {
  83         unsigned long long single_ecc_errs;
  84         unsigned long long double_ecc_errs;
  85         unsigned long long parity_err_cnt;
  86         unsigned long long serious_err_cnt;
  87         unsigned long long soft_reset_cnt;
  88         unsigned long long fifo_full_cnt;
  89         unsigned long long ring_full_cnt;
  90         /* LRO statistics */
  91         unsigned long long clubbed_frms_cnt;
  92         unsigned long long sending_both;
  93         unsigned long long outof_sequence_pkts;
  94         unsigned long long flush_max_pkts;
  95         unsigned long long sum_avg_pkts_aggregated;
  96         unsigned long long num_aggregations;
  97 };
  98
  99 /* Xpak releated alarm and warnings */
 100 struct xpakStat {
 101         u64 alarm_transceiver_temp_high;
 102         u64 alarm_transceiver_temp_low;
 103         u64 alarm_laser_bias_current_high;
 104         u64 alarm_laser_bias_current_low;
 105         u64 alarm_laser_output_power_high;
 106         u64 alarm_laser_output_power_low;
 107         u64 warn_transceiver_temp_high;
 108         u64 warn_transceiver_temp_low;
 109         u64 warn_laser_bias_current_high;
 110         u64 warn_laser_bias_current_low;
 111         u64 warn_laser_output_power_high;
 112         u64 warn_laser_output_power_low;
 113         u64 xpak_regs_stat;
 114         u32 xpak_timer_count;
 115 };
 116
 117
 118 /* The statistics block of Xena */
 119 struct stat_block {
 120 /* Tx MAC statistics counters. */
 121         __le32 tmac_data_octets;
 122         __le32 tmac_frms;
 123         __le64 tmac_drop_frms;
 124         __le32 tmac_bcst_frms;
 125         __le32 tmac_mcst_frms;
 126         __le64 tmac_pause_ctrl_frms;
 127         __le32 tmac_ucst_frms;
 128         __le32 tmac_ttl_octets;
 129         __le32 tmac_any_err_frms;
 130         __le32 tmac_nucst_frms;
 131         __le64 tmac_ttl_less_fb_octets;
 132         __le64 tmac_vld_ip_octets;
 133         __le32 tmac_drop_ip;
 134         __le32 tmac_vld_ip;
 135         __le32 tmac_rst_tcp;
 136         __le32 tmac_icmp;
 137         __le64 tmac_tcp;
 138         __le32 reserved_0;
 139         __le32 tmac_udp;
 140
 141 /* Rx MAC Statistics counters. */
 142         __le32 rmac_data_octets;
 143         __le32 rmac_vld_frms;
 144         __le64 rmac_fcs_err_frms;
 145         __le64 rmac_drop_frms;
 146         __le32 rmac_vld_bcst_frms;
 147         __le32 rmac_vld_mcst_frms;
 148         __le32 rmac_out_rng_len_err_frms;
 149         __le32 rmac_in_rng_len_err_frms;
 150         __le64 rmac_long_frms;
 151         __le64 rmac_pause_ctrl_frms;
 152         __le64 rmac_unsup_ctrl_frms;
 153         __le32 rmac_accepted_ucst_frms;
 154         __le32 rmac_ttl_octets;
 155         __le32 rmac_discarded_frms;
 156         __le32 rmac_accepted_nucst_frms;
 157         __le32 reserved_1;
 158         __le32 rmac_drop_events;
 159         __le64 rmac_ttl_less_fb_octets;
 160         __le64 rmac_ttl_frms;
 161         __le64 reserved_2;
 162         __le32 rmac_usized_frms;
 163         __le32 reserved_3;
 164         __le32 rmac_frag_frms;
 165         __le32 rmac_osized_frms;
 166         __le32 reserved_4;
 167         __le32 rmac_jabber_frms;
 168         __le64 rmac_ttl_64_frms;
 169         __le64 rmac_ttl_65_127_frms;
 170         __le64 reserved_5;
 171         __le64 rmac_ttl_128_255_frms;
 172         __le64 rmac_ttl_256_511_frms;
 173         __le64 reserved_6;
 174         __le64 rmac_ttl_512_1023_frms;
 175         __le64 rmac_ttl_1024_1518_frms;
 176         __le32 rmac_ip;
 177         __le32 reserved_7;
 178         __le64 rmac_ip_octets;
 179         __le32 rmac_drop_ip;
 180         __le32 rmac_hdr_err_ip;
 181         __le32 reserved_8;
 182         __le32 rmac_icmp;
 183         __le64 rmac_tcp;
 184         __le32 rmac_err_drp_udp;
 185         __le32 rmac_udp;
 186         __le64 rmac_xgmii_err_sym;
 187         __le64 rmac_frms_q0;
 188         __le64 rmac_frms_q1;
 189         __le64 rmac_frms_q2;
 190         __le64 rmac_frms_q3;
 191         __le64 rmac_frms_q4;
 192         __le64 rmac_frms_q5;
 193         __le64 rmac_frms_q6;
 194         __le64 rmac_frms_q7;
 195         __le16 rmac_full_q3;
 196         __le16 rmac_full_q2;
 197         __le16 rmac_full_q1;
 198         __le16 rmac_full_q0;
 199         __le16 rmac_full_q7;
 200         __le16 rmac_full_q6;
 201         __le16 rmac_full_q5;
 202         __le16 rmac_full_q4;
 203         __le32 reserved_9;
 204         __le32 rmac_pause_cnt;
 205         __le64 rmac_xgmii_data_err_cnt;
 206         __le64 rmac_xgmii_ctrl_err_cnt;
 207         __le32 rmac_err_tcp;
 208         __le32 rmac_accepted_ip;
 209
 210 /* PCI/PCI-X Read transaction statistics. */
 211         __le32 new_rd_req_cnt;
 212         __le32 rd_req_cnt;
 213         __le32 rd_rtry_cnt;
 214         __le32 new_rd_req_rtry_cnt;
 215
 216 /* PCI/PCI-X Write/Read transaction statistics. */
 217         __le32 wr_req_cnt;
 218         __le32 wr_rtry_rd_ack_cnt;
 219         __le32 new_wr_req_rtry_cnt;
 220         __le32 new_wr_req_cnt;
 221         __le32 wr_disc_cnt;
 222         __le32 wr_rtry_cnt;
 223
 224 /*      PCI/PCI-X Write / DMA Transaction statistics. */
 225         __le32 txp_wr_cnt;
 226         __le32 rd_rtry_wr_ack_cnt;
 227         __le32 txd_wr_cnt;
 228         __le32 txd_rd_cnt;
 229         __le32 rxd_wr_cnt;
 230         __le32 rxd_rd_cnt;
 231         __le32 rxf_wr_cnt;
 232         __le32 txf_rd_cnt;
 233
 234 /* Tx MAC statistics overflow counters. */
 235         __le32 tmac_data_octets_oflow;
 236         __le32 tmac_frms_oflow;
 237         __le32 tmac_bcst_frms_oflow;
 238         __le32 tmac_mcst_frms_oflow;
 239         __le32 tmac_ucst_frms_oflow;
 240         __le32 tmac_ttl_octets_oflow;
 241         __le32 tmac_any_err_frms_oflow;
 242         __le32 tmac_nucst_frms_oflow;
 243         __le64 tmac_vlan_frms;
 244         __le32 tmac_drop_ip_oflow;
 245         __le32 tmac_vld_ip_oflow;
 246         __le32 tmac_rst_tcp_oflow;
 247         __le32 tmac_icmp_oflow;
 248         __le32 tpa_unknown_protocol;
 249         __le32 tmac_udp_oflow;
 250         __le32 reserved_10;
 251         __le32 tpa_parse_failure;
 252
 253 /* Rx MAC Statistics overflow counters. */
 254         __le32 rmac_data_octets_oflow;
 255         __le32 rmac_vld_frms_oflow;
 256         __le32 rmac_vld_bcst_frms_oflow;
 257         __le32 rmac_vld_mcst_frms_oflow;
 258         __le32 rmac_accepted_ucst_frms_oflow;
 259         __le32 rmac_ttl_octets_oflow;
 260         __le32 rmac_discarded_frms_oflow;
 261         __le32 rmac_accepted_nucst_frms_oflow;
 262         __le32 rmac_usized_frms_oflow;
 263         __le32 rmac_drop_events_oflow;
 264         __le32 rmac_frag_frms_oflow;
 265         __le32 rmac_osized_frms_oflow;
 266         __le32 rmac_ip_oflow;
 267         __le32 rmac_jabber_frms_oflow;
 268         __le32 rmac_icmp_oflow;
 269         __le32 rmac_drop_ip_oflow;
 270         __le32 rmac_err_drp_udp_oflow;
 271         __le32 rmac_udp_oflow;
 272         __le32 reserved_11;
 273         __le32 rmac_pause_cnt_oflow;
 274         __le64 rmac_ttl_1519_4095_frms;
 275         __le64 rmac_ttl_4096_8191_frms;
 276         __le64 rmac_ttl_8192_max_frms;
 277         __le64 rmac_ttl_gt_max_frms;
 278         __le64 rmac_osized_alt_frms;
 279         __le64 rmac_jabber_alt_frms;
 280         __le64 rmac_gt_max_alt_frms;
 281         __le64 rmac_vlan_frms;
 282         __le32 rmac_len_discard;
 283         __le32 rmac_fcs_discard;
 284         __le32 rmac_pf_discard;
 285         __le32 rmac_da_discard;
 286         __le32 rmac_red_discard;
 287         __le32 rmac_rts_discard;
 288         __le32 reserved_12;
 289         __le32 rmac_ingm_full_discard;
 290         __le32 reserved_13;
 291         __le32 rmac_accepted_ip_oflow;
 292         __le32 reserved_14;
 293         __le32 link_fault_cnt;
 294         u8  buffer[20];
 295         struct swStat sw_stat;
 296         struct xpakStat xpak_stat;
 297 };
 298
 299 /*
 300  * Structures representing different init time configuration
 301  * parameters of the NIC.
 302  */
 303
 304 #define MAX_TX_FIFOS 8
 305 #define MAX_RX_RINGS 8
 306
 307 /* FIFO mappings for all possible number of fifos configured */
 308 static int fifo_map[][MAX_TX_FIFOS] = {
 309         {0, 0, 0, 0, 0, 0, 0, 0},
 310         {0, 0, 0, 0, 1, 1, 1, 1},
 311         {0, 0, 0, 1, 1, 1, 2, 2},
 312         {0, 0, 1, 1, 2, 2, 3, 3},
 313         {0, 0, 1, 1, 2, 2, 3, 4},
 314         {0, 0, 1, 1, 2, 3, 4, 5},
 315         {0, 0, 1, 2, 3, 4, 5, 6},
 316         {0, 1, 2, 3, 4, 5, 6, 7},
 317 };
 318
 319 /* Maintains Per FIFO related information. */
 320 struct tx_fifo_config {
 321 #define MAX_AVAILABLE_TXDS      8192
 322         u32 fifo_len;           /* specifies len of FIFO upto 8192, ie no of TxDLs */
 323 /* Priority definition */
 324 #define TX_FIFO_PRI_0               0   /*Highest */
 325 #define TX_FIFO_PRI_1               1
 326 #define TX_FIFO_PRI_2               2
 327 #define TX_FIFO_PRI_3               3
 328 #define TX_FIFO_PRI_4               4
 329 #define TX_FIFO_PRI_5               5
 330 #define TX_FIFO_PRI_6               6
 331 #define TX_FIFO_PRI_7               7   /*lowest */
 332         u8 fifo_priority;       /* specifies pointer level for FIFO */
 333         /* user should not set twos fifos with same pri */
 334         u8 f_no_snoop;
 335 #define NO_SNOOP_TXD                0x01
 336 #define NO_SNOOP_TXD_BUFFER          0x02
 337 };
 338
 339
 340 /* Maintains per Ring related information */
 341 struct rx_ring_config {
 342         u32 num_rxd;            /*No of RxDs per Rx Ring */
 343 #define RX_RING_PRI_0               0   /* highest */
 344 #define RX_RING_PRI_1               1
 345 #define RX_RING_PRI_2               2
 346 #define RX_RING_PRI_3               3
 347 #define RX_RING_PRI_4               4
 348 #define RX_RING_PRI_5               5
 349 #define RX_RING_PRI_6               6
 350 #define RX_RING_PRI_7               7   /* lowest */
 351
 352         u8 ring_priority;       /*Specifies service priority of ring */
 353         /* OSM should not set any two rings with same priority */
 354         u8 ring_org;            /*Organization of ring */
 355 #define RING_ORG_BUFF1          0x01
 356 #define RX_RING_ORG_BUFF3       0x03
 357 #define RX_RING_ORG_BUFF5       0x05
 358
 359         u8 f_no_snoop;
 360 #define NO_SNOOP_RXD                0x01
 361 #define NO_SNOOP_RXD_BUFFER         0x02
 362 };
 363
 364 /* This structure provides contains values of the tunable parameters
 365  * of the H/W
 366  */
 367 struct config_param {
 368 /* Tx Side */
 369         u32 tx_fifo_num;        /*Number of Tx FIFOs */
 370
 371         u8 fifo_mapping[MAX_TX_FIFOS];
 372         struct tx_fifo_config tx_cfg[MAX_TX_FIFOS];     /*Per-Tx FIFO config */
 373         u32 max_txds;           /*Max no. of Tx buffer descriptor per TxDL */
 374         u64 tx_intr_type;
 375         /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
 376
 377 /* Rx Side */
 378         u32 rx_ring_num;        /*Number of receive rings */
 379 #define MAX_RX_BLOCKS_PER_RING  150
 380
 381         struct rx_ring_config rx_cfg[MAX_RX_RINGS];     /*Per-Rx Ring config */
 382         u8 bimodal;             /*Flag for setting bimodal interrupts*/
 383
 384 #define HEADER_ETHERNET_II_802_3_SIZE 14
 385 #define HEADER_802_2_SIZE              3
 386 #define HEADER_SNAP_SIZE               5
 387 #define HEADER_VLAN_SIZE               4
 388
 389 #define MIN_MTU                       46
 390 #define MAX_PYLD                    1500
 391 #define MAX_MTU                     (MAX_PYLD+18)
 392 #define MAX_MTU_VLAN                (MAX_PYLD+22)
 393 #define MAX_PYLD_JUMBO              9600
 394 #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
 395 #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
 396         u16 bus_speed;
 397 };
 398
 399 /* Structure representing MAC Addrs */
 400 struct mac_addr {
 401         u8 mac_addr[ETH_ALEN];
 402 };
 403
 404 /* Structure that represent every FIFO element in the BAR1
 405  * Address location.
 406  */
 407 struct TxFIFO_element {
 408         u64 TxDL_Pointer;
 409
 410         u64 List_Control;
 411 #define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
 412 #define TX_FIFO_FIRST_LIST             BIT(14)
 413 #define TX_FIFO_LAST_LIST              BIT(15)
 414 #define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
 415 #define TX_FIFO_SPECIAL_FUNC           BIT(23)
 416 #define TX_FIFO_DS_NO_SNOOP            BIT(31)
 417 #define TX_FIFO_BUFF_NO_SNOOP          BIT(30)
 418 };
 419
 420 /* Tx descriptor structure */
 421 struct TxD {
 422         u64 Control_1;
 423 /* bit mask */
 424 #define TXD_LIST_OWN_XENA       BIT(7)
 425 #define TXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 426 #define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))
 427 #define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)
 428 #define TXD_GATHER_CODE         (BIT(22) | BIT(23))
 429 #define TXD_GATHER_CODE_FIRST   BIT(22)
 430 #define TXD_GATHER_CODE_LAST    BIT(23)
 431 #define TXD_TCP_LSO_EN          BIT(30)
 432 #define TXD_UDP_COF_EN          BIT(31)
 433 #define TXD_UFO_EN              BIT(31) | BIT(30)
 434 #define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
 435 #define TXD_UFO_MSS(val)        vBIT(val,34,14)
 436 #define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
 437
 438         u64 Control_2;
 439 #define TXD_TX_CKO_CONTROL      (BIT(5)|BIT(6)|BIT(7))
 440 #define TXD_TX_CKO_IPV4_EN      BIT(5)
 441 #define TXD_TX_CKO_TCP_EN       BIT(6)
 442 #define TXD_TX_CKO_UDP_EN       BIT(7)
 443 #define TXD_VLAN_ENABLE         BIT(15)
 444 #define TXD_VLAN_TAG(val)       vBIT(val,16,16)
 445 #define TXD_INT_NUMBER(val)     vBIT(val,34,6)
 446 #define TXD_INT_TYPE_PER_LIST   BIT(47)
 447 #define TXD_INT_TYPE_UTILZ      BIT(46)
 448 #define TXD_SET_MARKER         vBIT(0x6,0,4)
 449
 450         u64 Buffer_Pointer;
 451         u64 Host_Control;       /* reserved for host */
 452 };
 453
 454 /* Structure to hold the phy and virt addr of every TxDL. */
 455 struct list_info_hold {
 456         dma_addr_t list_phy_addr;
 457         void *list_virt_addr;
 458 };
 459
 460 /* Rx descriptor structure for 1 buffer mode */
 461 struct RxD_t {
 462         u64 Host_Control;       /* reserved for host */
 463         u64 Control_1;
 464 #define RXD_OWN_XENA            BIT(7)
 465 #define RXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 466 #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
 467 #define RXD_FRAME_PROTO_IPV4    BIT(27)
 468 #define RXD_FRAME_PROTO_IPV6    BIT(28)
 469 #define RXD_FRAME_IP_FRAG       BIT(29)
 470 #define RXD_FRAME_PROTO_TCP     BIT(30)
 471 #define RXD_FRAME_PROTO_UDP     BIT(31)
 472 #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
 473 #define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)
 474 #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
 475
 476         u64 Control_2;
 477 #define THE_RXD_MARK            0x3
 478 #define SET_RXD_MARKER          vBIT(THE_RXD_MARK, 0, 2)
 479 #define GET_RXD_MARKER(ctrl)    ((ctrl & SET_RXD_MARKER) >> 62)
 480
 481 #define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)
 482 #define SET_VLAN_TAG(val)       vBIT(val,48,16)
 483 #define SET_NUM_TAG(val)       vBIT(val,16,32)
 484
 485
 486 };
 487 /* Rx descriptor structure for 1 buffer mode */
 488 struct RxD1 {
 489         struct RxD_t h;
 490
 491 #define MASK_BUFFER0_SIZE_1       vBIT(0x3FFF,2,14)
 492 #define SET_BUFFER0_SIZE_1(val)   vBIT(val,2,14)
 493 #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
 494         (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
 495         u64 Buffer0_ptr;
 496 };
 497 /* Rx descriptor structure for 3 or 2 buffer mode */
 498
 499 struct RxD3 {
 500         struct RxD_t h;
 501
 502 #define MASK_BUFFER0_SIZE_3       vBIT(0xFF,2,14)
 503 #define MASK_BUFFER1_SIZE_3       vBIT(0xFFFF,16,16)
 504 #define MASK_BUFFER2_SIZE_3       vBIT(0xFFFF,32,16)
 505 #define SET_BUFFER0_SIZE_3(val)   vBIT(val,8,8)
 506 #define SET_BUFFER1_SIZE_3(val)   vBIT(val,16,16)
 507 #define SET_BUFFER2_SIZE_3(val)   vBIT(val,32,16)
 508 #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
 509         (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
 510 #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
 511         (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
 512 #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
 513         (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
 514 #define BUF0_LEN        40
 515 #define BUF1_LEN        1
 516
 517         u64 Buffer0_ptr;
 518         u64 Buffer1_ptr;
 519         u64 Buffer2_ptr;
 520 };
 521
 522
 523 /* Structure that represents the Rx descriptor block which contains
 524  * 128 Rx descriptors.
 525  */
 526 struct RxD_block {
 527 #define MAX_RXDS_PER_BLOCK_1            127
 528         struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
 529
 530         u64 reserved_0;
 531 #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
 532         u64 reserved_1;         /* 0xFEFFFFFFFFFFFFFF to mark last
 533                                  * Rxd in this blk */
 534         u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
 535         u64 pNext_RxD_Blk_physical;     /* Buff0_ptr.In a 32 bit arch
 536                                          * the upper 32 bits should
 537                                          * be 0 */
 538 };
 539
 540 #define SIZE_OF_BLOCK   4096
 541
 542 #define RXD_MODE_1      0 /* One Buffer mode */
 543 #define RXD_MODE_3A     1 /* Three Buffer mode */
 544 #define RXD_MODE_3B     2 /* Two Buffer mode */
 545
 546 /* Structure to hold virtual addresses of Buf0 and Buf1 in
 547  * 2buf mode. */
 548 struct buffAdd {
 549         void *ba_0_org;
 550         void *ba_1_org;
 551         void *ba_0;
 552         void *ba_1;
 553 };
 554
 555 /* Structure which stores all the MAC control parameters */
 556
 557 /* This structure stores the offset of the RxD in the ring
 558  * from which the Rx Interrupt processor can start picking
 559  * up the RxDs for processing.
 560  */
 561 struct rx_curr_get_info {
 562         u32 block_index;
 563         u32 offset;
 564         u32 ring_len;
 565 };
 566
 567 struct rx_curr_put_info {
 568         u32 block_index;
 569         u32 offset;
 570         u32 ring_len;
 571 };
 572
 573 /* This structure stores the offset of the TxDl in the FIFO
 574  * from which the Tx Interrupt processor can start picking
 575  * up the TxDLs for send complete interrupt processing.
 576  */
 577 struct tx_curr_get_info {
 578         u32 offset;
 579         u32 fifo_len;
 580 };
 581
 582 struct tx_curr_put_info {
 583         u32 offset;
 584         u32 fifo_len;
 585 };
 586
 587 struct rxd_info {
 588         void *virt_addr;
 589         dma_addr_t dma_addr;
 590 };
 591
 592 /* Structure that holds the Phy and virt addresses of the Blocks */
 593 struct rx_block_info {
 594         void *block_virt_addr;
 595         dma_addr_t block_dma_addr;
 596         struct rxd_info *rxds;
 597 };
 598
 599 /* Ring specific structure */
 600 struct ring_info {
 601         /* The ring number */
 602         int ring_no;
 603
 604         /*
 605          *  Place holders for the virtual and physical addresses of
 606          *  all the Rx Blocks
 607          */
 608         struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
 609         int block_count;
 610         int pkt_cnt;
 611
 612         /*
 613          * Put pointer info which indictes which RxD has to be replenished
 614          * with a new buffer.
 615          */
 616         struct rx_curr_put_info rx_curr_put_info;
 617
 618         /*
 619          * Get pointer info which indictes which is the last RxD that was
 620          * processed by the driver.
 621          */
 622         struct rx_curr_get_info rx_curr_get_info;
 623
 624         /* Index to the absolute position of the put pointer of Rx ring */
 625         int put_pos;
 626
 627         /* Buffer Address store. */
 628         struct buffAdd **ba;
 629         struct s2io_nic *nic;
 630 };
 631
 632 /* Fifo specific structure */
 633 struct fifo_info {
 634         /* FIFO number */
 635         int fifo_no;
 636
 637         /* Maximum TxDs per TxDL */
 638         int max_txds;
 639
 640         /* Place holder of all the TX List's Phy and Virt addresses. */
 641         struct list_info_hold *list_info;
 642
 643         /*
 644          * Current offset within the tx FIFO where driver would write
 645          * new Tx frame
 646          */
 647         struct tx_curr_put_info tx_curr_put_info;
 648
 649         /*
 650          * Current offset within tx FIFO from where the driver would start freeing
 651          * the buffers
 652          */
 653         struct tx_curr_get_info tx_curr_get_info;
 654
 655         struct s2io_nic *nic;
 656 };
 657
 658 /* Information related to the Tx and Rx FIFOs and Rings of Xena
 659  * is maintained in this structure.
 660  */
 661 struct mac_info {
 662 /* tx side stuff */
 663         /* logical pointer of start of each Tx FIFO */
 664         struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
 665
 666         /* Fifo specific structure */
 667         struct fifo_info fifos[MAX_TX_FIFOS];
 668
 669         /* Save virtual address of TxD page with zero DMA addr(if any) */
 670         void *zerodma_virt_addr;
 671
 672 /* rx side stuff */
 673         /* Ring specific structure */
 674         struct ring_info rings[MAX_RX_RINGS];
 675
 676         u16 rmac_pause_time;
 677         u16 mc_pause_threshold_q0q3;
 678         u16 mc_pause_threshold_q4q7;
 679
 680         void *stats_mem;        /* orignal pointer to allocated mem */
 681         dma_addr_t stats_mem_phy;       /* Physical address of the stat block */
 682         u32 stats_mem_sz;
 683         struct stat_block *stats_info;  /* Logical address of the stat block */
 684 };
 685
 686 /* structure representing the user defined MAC addresses */
 687 struct usr_addr {
 688         char addr[ETH_ALEN];
 689         int usage_cnt;
 690 };
 691
 692 /* Default Tunable parameters of the NIC. */
 693 #define DEFAULT_FIFO_0_LEN 4096
 694 #define DEFAULT_FIFO_1_7_LEN 512
 695 #define SMALL_BLK_CNT   30
 696 #define LARGE_BLK_CNT   100
 697
 698 /*
 699  * Structure to keep track of the MSI-X vectors and the corresponding
 700  * argument registered against each vector
 701  */
 702 #define MAX_REQUESTED_MSI_X     17
 703 struct s2io_msix_entry
 704 {
 705         u16 vector;
 706         u16 entry;
 707         void *arg;
 708
 709         u8 type;
 710 #define MSIX_FIFO_TYPE  1
 711 #define MSIX_RING_TYPE  2
 712
 713         u8 in_use;
 714 #define MSIX_REGISTERED_SUCCESS 0xAA
 715 };
 716
 717 struct msix_info_st {
 718         u64 addr;
 719         u64 data;
 720 };
 721
 722 /* Data structure to represent a LRO session */
 723 struct lro {
 724         struct sk_buff  *parent;
 725         struct sk_buff  *last_frag;
 726         u8              *l2h;
 727         struct iphdr    *iph;
 728         struct tcphdr   *tcph;
 729         u32             tcp_next_seq;
 730         u32             tcp_ack;
 731         int             total_len;
 732         int             frags_len;
 733         int             sg_num;
 734         int             in_use;
 735         u16             window;
 736         u32             cur_tsval;
 737         u32             cur_tsecr;
 738         u8              saw_ts;
 739 };
 740
 741 /* Structure representing one instance of the NIC */
 742 struct s2io_nic {
 743         int rxd_mode;
 744         /*
 745          * Count of packets to be processed in a given iteration, it will be indicated
 746          * by the quota field of the device structure when NAPI is enabled.
 747          */
 748         int pkts_to_process;
 749         struct net_device *dev;
 750         struct mac_info mac_control;
 751         struct config_param config;
 752         struct pci_dev *pdev;
 753         void __iomem *bar0;
 754         void __iomem *bar1;
 755 #define MAX_MAC_SUPPORTED   16
 756 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
 757
 758         struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];
 759         struct mac_addr pre_mac_addr[MAX_MAC_SUPPORTED];
 760
 761         struct net_device_stats stats;
 762         int high_dma_flag;
 763         int device_close_flag;
 764         int device_enabled_once;
 765
 766         char name[60];
 767         struct tasklet_struct task;
 768         volatile unsigned long tasklet_status;
 769
 770         /* Timer that handles I/O errors/exceptions */
 771         struct timer_list alarm_timer;
 772
 773         /* Space to back up the PCI config space */
 774         u32 config_space[256 / sizeof(u32)];
 775
 776         atomic_t rx_bufs_left[MAX_RX_RINGS];
 777
 778         spinlock_t tx_lock;
 779         spinlock_t put_lock;
 780
 781 #define PROMISC     1
 782 #define ALL_MULTI   2
 783
 784 #define MAX_ADDRS_SUPPORTED 64
 785         u16 usr_addr_count;
 786         u16 mc_addr_count;
 787         struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];
 788
 789         u16 m_cast_flg;
 790         u16 all_multi_pos;
 791         u16 promisc_flg;
 792
 793         u16 tx_pkt_count;
 794         u16 rx_pkt_count;
 795         u16 tx_err_count;
 796         u16 rx_err_count;
 797
 798         /*  Id timer, used to blink NIC to physically identify NIC. */
 799         struct timer_list id_timer;
 800
 801         /*  Restart timer, used to restart NIC if the device is stuck and
 802          *  a schedule task that will set the correct Link state once the
 803          *  NIC's PHY has stabilized after a state change.
 804          */
 805         struct work_struct rst_timer_task;
 806         struct work_struct set_link_task;
 807
 808         /* Flag that can be used to turn on or turn off the Rx checksum
 809          * offload feature.
 810          */
 811         int rx_csum;
 812
 813         /*  after blink, the adapter must be restored with original
 814          *  values.
 815          */
 816         u64 adapt_ctrl_org;
 817
 818         /* Last known link state. */
 819         u16 last_link_state;
 820 #define LINK_DOWN       1
 821 #define LINK_UP         2
 822
 823         int task_flag;
 824 #define CARD_DOWN 1
 825 #define CARD_UP 2
 826         atomic_t card_state;
 827         volatile unsigned long link_state;
 828         struct vlan_group *vlgrp;
 829 #define MSIX_FLG                0xA5
 830         struct msix_entry *entries;
 831         struct s2io_msix_entry *s2io_entries;
 832         char desc[MAX_REQUESTED_MSI_X][25];
 833
 834         int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
 835
 836         struct msix_info_st msix_info[0x3f];
 837
 838 #define XFRAME_I_DEVICE         1
 839 #define XFRAME_II_DEVICE        2
 840         u8 device_type;
 841
 842 #define MAX_LRO_SESSIONS        32
 843         struct lro lro0_n[MAX_LRO_SESSIONS];
 844         unsigned long   clubbed_frms_cnt;
 845         unsigned long   sending_both;
 846         u8              lro;
 847         u16             lro_max_aggr_per_sess;
 848
 849 #define INTA    0
 850 #define MSI     1
 851 #define MSI_X   2
 852         u8 intr_type;
 853
 854         spinlock_t      rx_lock;
 855         atomic_t        isr_cnt;
 856         u64 *ufo_in_band_v;
 857 #define VPD_STRING_LEN 80
 858         u8  product_name[VPD_STRING_LEN];
 859         u8  serial_num[VPD_STRING_LEN];
 860 };
 861
 862 #define RESET_ERROR 1;
 863 #define CMD_ERROR   2;
 864
 865 /*  OS related system calls */
 866 #ifndef readq
 867 static inline u64 readq(void __iomem *addr)
 868 {
 869         u64 ret = 0;
 870         ret = readl(addr + 4);
 871         ret <<= 32;
 872         ret |= readl(addr);
 873
 874         return ret;
 875 }
 876 #endif
 877
 878 #ifndef writeq
 879 static inline void writeq(u64 val, void __iomem *addr)
 880 {
 881         writel((u32) (val), addr);
 882         writel((u32) (val >> 32), (addr + 4));
 883 }
 884 #endif
 885
 886 /*
 887  * Some registers have to be written in a particular order to
 888  * expect correct hardware operation. The macro SPECIAL_REG_WRITE
 889  * is used to perform such ordered writes. Defines UF (Upper First)
 890  * and LF (Lower First) will be used to specify the required write order.
 891  */
 892 #define UF      1
 893 #define LF      2
 894 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
 895 {
 896         u32 ret;
 897
 898         if (order == LF) {
 899                 writel((u32) (val), addr);
 900                 ret = readl(addr);
 901                 writel((u32) (val >> 32), (addr + 4));
 902                 ret = readl(addr + 4);
 903         } else {
 904                 writel((u32) (val >> 32), (addr + 4));
 905                 ret = readl(addr + 4);
 906                 writel((u32) (val), addr);
 907                 ret = readl(addr);
 908         }
 909 }
 910
 911 /*  Interrupt related values of Xena */
 912
 913 #define ENABLE_INTRS    1
 914 #define DISABLE_INTRS   2
 915
 916 /*  Highest level interrupt blocks */
 917 #define TX_PIC_INTR     (0x0001<<0)
 918 #define TX_DMA_INTR     (0x0001<<1)
 919 #define TX_MAC_INTR     (0x0001<<2)
 920 #define TX_XGXS_INTR    (0x0001<<3)
 921 #define TX_TRAFFIC_INTR (0x0001<<4)
 922 #define RX_PIC_INTR     (0x0001<<5)
 923 #define RX_DMA_INTR     (0x0001<<6)
 924 #define RX_MAC_INTR     (0x0001<<7)
 925 #define RX_XGXS_INTR    (0x0001<<8)
 926 #define RX_TRAFFIC_INTR (0x0001<<9)
 927 #define MC_INTR         (0x0001<<10)
 928 #define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
 929                             TX_DMA_INTR     | \
 930                             TX_MAC_INTR     | \
 931                             TX_XGXS_INTR    | \
 932                             TX_TRAFFIC_INTR | \
 933                             RX_PIC_INTR     | \
 934                             RX_DMA_INTR     | \
 935                             RX_MAC_INTR     | \
 936                             RX_XGXS_INTR    | \
 937                             RX_TRAFFIC_INTR | \
 938                             MC_INTR )
 939
 940 /*  Interrupt masks for the general interrupt mask register */
 941 #define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL
 942
 943 #define TXPIC_INT_M         BIT(0)
 944 #define TXDMA_INT_M         BIT(1)
 945 #define TXMAC_INT_M         BIT(2)
 946 #define TXXGXS_INT_M        BIT(3)
 947 #define TXTRAFFIC_INT_M     BIT(8)
 948 #define PIC_RX_INT_M        BIT(32)
 949 #define RXDMA_INT_M         BIT(33)
 950 #define RXMAC_INT_M         BIT(34)
 951 #define MC_INT_M            BIT(35)
 952 #define RXXGXS_INT_M        BIT(36)
 953 #define RXTRAFFIC_INT_M     BIT(40)
 954
 955 /*  PIC level Interrupts TODO*/
 956
 957 /*  DMA level Inressupts */
 958 #define TXDMA_PFC_INT_M     BIT(0)
 959 #define TXDMA_PCC_INT_M     BIT(2)
 960
 961 /*  PFC block interrupts */
 962 #define PFC_MISC_ERR_1      BIT(0)      /* Interrupt to indicate FIFO full */
 963
 964 /* PCC block interrupts. */
 965 #define PCC_FB_ECC_ERR     vBIT(0xff, 16, 8)    /* Interrupt to indicate
 966                                                    PCC_FB_ECC Error. */
 967
 968 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
 969 /*
 970  * Prototype declaration.
 971  */
 972 static int __devinit s2io_init_nic(struct pci_dev *pdev,
 973                                    const struct pci_device_id *pre);
 974 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
 975 static int init_shared_mem(struct s2io_nic *sp);
 976 static void free_shared_mem(struct s2io_nic *sp);
 977 static int init_nic(struct s2io_nic *nic);
 978 static void rx_intr_handler(struct ring_info *ring_data);
 979 static void tx_intr_handler(struct fifo_info *fifo_data);
 980 static void alarm_intr_handler(struct s2io_nic *sp);
 981
 982 static int s2io_starter(void);
 983 static void s2io_closer(void);
 984 static void s2io_tx_watchdog(struct net_device *dev);
 985 static void s2io_tasklet(unsigned long dev_addr);
 986 static void s2io_set_multicast(struct net_device *dev);
 987 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
 988 static void s2io_link(struct s2io_nic * sp, int link);
 989 static void s2io_reset(struct s2io_nic * sp);
 990 static int s2io_poll(struct net_device *dev, int *budget);
 991 static void s2io_init_pci(struct s2io_nic * sp);
 992 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
 993 static void s2io_alarm_handle(unsigned long data);
 994 static int s2io_enable_msi(struct s2io_nic *nic);
 995 static irqreturn_t s2io_msi_handle(int irq, void *dev_id);
 996 static irqreturn_t
 997 s2io_msix_ring_handle(int irq, void *dev_id);
 998 static irqreturn_t
 999 s2io_msix_fifo_handle(int irq, void *dev_id);
1000 static irqreturn_t s2io_isr(int irq, void *dev_id);
1001 static int verify_xena_quiescence(struct s2io_nic *sp);
1002 static const struct ethtool_ops netdev_ethtool_ops;
1003 static void s2io_set_link(struct work_struct *work);
1004 static int s2io_set_swapper(struct s2io_nic * sp);
1005 static void s2io_card_down(struct s2io_nic *nic);
1006 static int s2io_card_up(struct s2io_nic *nic);
1007 static int get_xena_rev_id(struct pci_dev *pdev);
1008 static int wait_for_cmd_complete(void *addr, u64 busy_bit);
1009 static int s2io_add_isr(struct s2io_nic * sp);
1010 static void s2io_rem_isr(struct s2io_nic * sp);
1011
1012 static void restore_xmsi_data(struct s2io_nic *nic);
1013
1014 static int
1015 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1016                       struct RxD_t *rxdp, struct s2io_nic *sp);
1017 static void clear_lro_session(struct lro *lro);
1018 static void queue_rx_frame(struct sk_buff *skb);
1019 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1020 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1021                            struct sk_buff *skb, u32 tcp_len);
1022
1023 #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1024 #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1025 #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1026
1027 #define S2IO_PARM_INT(X, def_val) \
1028         static unsigned int X = def_val;\
1029                 module_param(X , uint, 0);
1030
1031 #endif                          /* _S2IO_H */