drivers/net/s2io.h

   1 /************************************************************************
   2  * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2007 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  ************************************************************************/
  13 #ifndef _S2IO_H
  14 #define _S2IO_H
  15
  16 #define TBD 0
  17 #define BIT(loc)                (0x8000000000000000ULL >> (loc))
  18 #define vBIT(val, loc, sz)      (((u64)val) << (64-loc-sz))
  19 #define INV(d)  ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
  20
  21 #ifndef BOOL
  22 #define BOOL    int
  23 #endif
  24
  25 #ifndef TRUE
  26 #define TRUE    1
  27 #define FALSE   0
  28 #endif
  29
  30 #undef SUCCESS
  31 #define SUCCESS 0
  32 #define FAILURE -1
  33 #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
  34 #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
  35 #define S2IO_BIT_RESET 1
  36 #define S2IO_BIT_SET 2
  37 #define CHECKBIT(value, nbit) (value & (1 << nbit))
  38
  39 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
  40 #define MAX_FLICKER_TIME        60000 /* 60 Secs */
  41
  42 /* Maximum outstanding splits to be configured into xena. */
  43 enum {
  44         XENA_ONE_SPLIT_TRANSACTION = 0,
  45         XENA_TWO_SPLIT_TRANSACTION = 1,
  46         XENA_THREE_SPLIT_TRANSACTION = 2,
  47         XENA_FOUR_SPLIT_TRANSACTION = 3,
  48         XENA_EIGHT_SPLIT_TRANSACTION = 4,
  49         XENA_TWELVE_SPLIT_TRANSACTION = 5,
  50         XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  51         XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  52 };
  53 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  54
  55 /*  OS concerned variables and constants */
  56 #define WATCH_DOG_TIMEOUT               15*HZ
  57 #define EFILL                           0x1234
  58 #define ALIGN_SIZE                      127
  59 #define PCIX_COMMAND_REGISTER           0x62
  60
  61 /*
  62  * Debug related variables.
  63  */
  64 /* different debug levels. */
  65 #define ERR_DBG         0
  66 #define INIT_DBG        1
  67 #define INFO_DBG        2
  68 #define TX_DBG          3
  69 #define INTR_DBG        4
  70
  71 /* Global variable that defines the present debug level of the driver. */
  72 static int debug_level = ERR_DBG;
  73
  74 /* DEBUG message print. */
  75 #define DBG_PRINT(dbg_level, args...)  if(!(debug_level<dbg_level)) printk(args)
  76
  77 #ifndef DMA_ERROR_CODE
  78 #define DMA_ERROR_CODE          (~(dma_addr_t)0x0)
  79 #endif
  80
  81 /* Protocol assist features of the NIC */
  82 #define L3_CKSUM_OK 0xFFFF
  83 #define L4_CKSUM_OK 0xFFFF
  84 #define S2IO_JUMBO_SIZE 9600
  85
  86 /* Driver statistics maintained by driver */
  87 struct swStat {
  88         unsigned long long single_ecc_errs;
  89         unsigned long long double_ecc_errs;
  90         unsigned long long parity_err_cnt;
  91         unsigned long long serious_err_cnt;
  92         unsigned long long soft_reset_cnt;
  93         unsigned long long fifo_full_cnt;
  94         unsigned long long ring_full_cnt;
  95         /* LRO statistics */
  96         unsigned long long clubbed_frms_cnt;
  97         unsigned long long sending_both;
  98         unsigned long long outof_sequence_pkts;
  99         unsigned long long flush_max_pkts;
 100         unsigned long long sum_avg_pkts_aggregated;
 101         unsigned long long num_aggregations;
 102         /* Other statistics */
 103         unsigned long long mem_alloc_fail_cnt;
 104         unsigned long long pci_map_fail_cnt;
 105         unsigned long long watchdog_timer_cnt;
 106         unsigned long long mem_allocated;
 107         unsigned long long mem_freed;
 108         unsigned long long link_up_cnt;
 109         unsigned long long link_down_cnt;
 110         unsigned long long link_up_time;
 111         unsigned long long link_down_time;
 112
 113         /* Transfer Code statistics */
 114         unsigned long long tx_buf_abort_cnt;
 115         unsigned long long tx_desc_abort_cnt;
 116         unsigned long long tx_parity_err_cnt;
 117         unsigned long long tx_link_loss_cnt;
 118         unsigned long long tx_list_proc_err_cnt;
 119
 120         unsigned long long rx_parity_err_cnt;
 121         unsigned long long rx_abort_cnt;
 122         unsigned long long rx_parity_abort_cnt;
 123         unsigned long long rx_rda_fail_cnt;
 124         unsigned long long rx_unkn_prot_cnt;
 125         unsigned long long rx_fcs_err_cnt;
 126         unsigned long long rx_buf_size_err_cnt;
 127         unsigned long long rx_rxd_corrupt_cnt;
 128         unsigned long long rx_unkn_err_cnt;
 129 };
 130
 131 /* Xpak releated alarm and warnings */
 132 struct xpakStat {
 133         u64 alarm_transceiver_temp_high;
 134         u64 alarm_transceiver_temp_low;
 135         u64 alarm_laser_bias_current_high;
 136         u64 alarm_laser_bias_current_low;
 137         u64 alarm_laser_output_power_high;
 138         u64 alarm_laser_output_power_low;
 139         u64 warn_transceiver_temp_high;
 140         u64 warn_transceiver_temp_low;
 141         u64 warn_laser_bias_current_high;
 142         u64 warn_laser_bias_current_low;
 143         u64 warn_laser_output_power_high;
 144         u64 warn_laser_output_power_low;
 145         u64 xpak_regs_stat;
 146         u32 xpak_timer_count;
 147 };
 148
 149
 150 /* The statistics block of Xena */
 151 struct stat_block {
 152 /* Tx MAC statistics counters. */
 153         __le32 tmac_data_octets;
 154         __le32 tmac_frms;
 155         __le64 tmac_drop_frms;
 156         __le32 tmac_bcst_frms;
 157         __le32 tmac_mcst_frms;
 158         __le64 tmac_pause_ctrl_frms;
 159         __le32 tmac_ucst_frms;
 160         __le32 tmac_ttl_octets;
 161         __le32 tmac_any_err_frms;
 162         __le32 tmac_nucst_frms;
 163         __le64 tmac_ttl_less_fb_octets;
 164         __le64 tmac_vld_ip_octets;
 165         __le32 tmac_drop_ip;
 166         __le32 tmac_vld_ip;
 167         __le32 tmac_rst_tcp;
 168         __le32 tmac_icmp;
 169         __le64 tmac_tcp;
 170         __le32 reserved_0;
 171         __le32 tmac_udp;
 172
 173 /* Rx MAC Statistics counters. */
 174         __le32 rmac_data_octets;
 175         __le32 rmac_vld_frms;
 176         __le64 rmac_fcs_err_frms;
 177         __le64 rmac_drop_frms;
 178         __le32 rmac_vld_bcst_frms;
 179         __le32 rmac_vld_mcst_frms;
 180         __le32 rmac_out_rng_len_err_frms;
 181         __le32 rmac_in_rng_len_err_frms;
 182         __le64 rmac_long_frms;
 183         __le64 rmac_pause_ctrl_frms;
 184         __le64 rmac_unsup_ctrl_frms;
 185         __le32 rmac_accepted_ucst_frms;
 186         __le32 rmac_ttl_octets;
 187         __le32 rmac_discarded_frms;
 188         __le32 rmac_accepted_nucst_frms;
 189         __le32 reserved_1;
 190         __le32 rmac_drop_events;
 191         __le64 rmac_ttl_less_fb_octets;
 192         __le64 rmac_ttl_frms;
 193         __le64 reserved_2;
 194         __le32 rmac_usized_frms;
 195         __le32 reserved_3;
 196         __le32 rmac_frag_frms;
 197         __le32 rmac_osized_frms;
 198         __le32 reserved_4;
 199         __le32 rmac_jabber_frms;
 200         __le64 rmac_ttl_64_frms;
 201         __le64 rmac_ttl_65_127_frms;
 202         __le64 reserved_5;
 203         __le64 rmac_ttl_128_255_frms;
 204         __le64 rmac_ttl_256_511_frms;
 205         __le64 reserved_6;
 206         __le64 rmac_ttl_512_1023_frms;
 207         __le64 rmac_ttl_1024_1518_frms;
 208         __le32 rmac_ip;
 209         __le32 reserved_7;
 210         __le64 rmac_ip_octets;
 211         __le32 rmac_drop_ip;
 212         __le32 rmac_hdr_err_ip;
 213         __le32 reserved_8;
 214         __le32 rmac_icmp;
 215         __le64 rmac_tcp;
 216         __le32 rmac_err_drp_udp;
 217         __le32 rmac_udp;
 218         __le64 rmac_xgmii_err_sym;
 219         __le64 rmac_frms_q0;
 220         __le64 rmac_frms_q1;
 221         __le64 rmac_frms_q2;
 222         __le64 rmac_frms_q3;
 223         __le64 rmac_frms_q4;
 224         __le64 rmac_frms_q5;
 225         __le64 rmac_frms_q6;
 226         __le64 rmac_frms_q7;
 227         __le16 rmac_full_q3;
 228         __le16 rmac_full_q2;
 229         __le16 rmac_full_q1;
 230         __le16 rmac_full_q0;
 231         __le16 rmac_full_q7;
 232         __le16 rmac_full_q6;
 233         __le16 rmac_full_q5;
 234         __le16 rmac_full_q4;
 235         __le32 reserved_9;
 236         __le32 rmac_pause_cnt;
 237         __le64 rmac_xgmii_data_err_cnt;
 238         __le64 rmac_xgmii_ctrl_err_cnt;
 239         __le32 rmac_err_tcp;
 240         __le32 rmac_accepted_ip;
 241
 242 /* PCI/PCI-X Read transaction statistics. */
 243         __le32 new_rd_req_cnt;
 244         __le32 rd_req_cnt;
 245         __le32 rd_rtry_cnt;
 246         __le32 new_rd_req_rtry_cnt;
 247
 248 /* PCI/PCI-X Write/Read transaction statistics. */
 249         __le32 wr_req_cnt;
 250         __le32 wr_rtry_rd_ack_cnt;
 251         __le32 new_wr_req_rtry_cnt;
 252         __le32 new_wr_req_cnt;
 253         __le32 wr_disc_cnt;
 254         __le32 wr_rtry_cnt;
 255
 256 /*      PCI/PCI-X Write / DMA Transaction statistics. */
 257         __le32 txp_wr_cnt;
 258         __le32 rd_rtry_wr_ack_cnt;
 259         __le32 txd_wr_cnt;
 260         __le32 txd_rd_cnt;
 261         __le32 rxd_wr_cnt;
 262         __le32 rxd_rd_cnt;
 263         __le32 rxf_wr_cnt;
 264         __le32 txf_rd_cnt;
 265
 266 /* Tx MAC statistics overflow counters. */
 267         __le32 tmac_data_octets_oflow;
 268         __le32 tmac_frms_oflow;
 269         __le32 tmac_bcst_frms_oflow;
 270         __le32 tmac_mcst_frms_oflow;
 271         __le32 tmac_ucst_frms_oflow;
 272         __le32 tmac_ttl_octets_oflow;
 273         __le32 tmac_any_err_frms_oflow;
 274         __le32 tmac_nucst_frms_oflow;
 275         __le64 tmac_vlan_frms;
 276         __le32 tmac_drop_ip_oflow;
 277         __le32 tmac_vld_ip_oflow;
 278         __le32 tmac_rst_tcp_oflow;
 279         __le32 tmac_icmp_oflow;
 280         __le32 tpa_unknown_protocol;
 281         __le32 tmac_udp_oflow;
 282         __le32 reserved_10;
 283         __le32 tpa_parse_failure;
 284
 285 /* Rx MAC Statistics overflow counters. */
 286         __le32 rmac_data_octets_oflow;
 287         __le32 rmac_vld_frms_oflow;
 288         __le32 rmac_vld_bcst_frms_oflow;
 289         __le32 rmac_vld_mcst_frms_oflow;
 290         __le32 rmac_accepted_ucst_frms_oflow;
 291         __le32 rmac_ttl_octets_oflow;
 292         __le32 rmac_discarded_frms_oflow;
 293         __le32 rmac_accepted_nucst_frms_oflow;
 294         __le32 rmac_usized_frms_oflow;
 295         __le32 rmac_drop_events_oflow;
 296         __le32 rmac_frag_frms_oflow;
 297         __le32 rmac_osized_frms_oflow;
 298         __le32 rmac_ip_oflow;
 299         __le32 rmac_jabber_frms_oflow;
 300         __le32 rmac_icmp_oflow;
 301         __le32 rmac_drop_ip_oflow;
 302         __le32 rmac_err_drp_udp_oflow;
 303         __le32 rmac_udp_oflow;
 304         __le32 reserved_11;
 305         __le32 rmac_pause_cnt_oflow;
 306         __le64 rmac_ttl_1519_4095_frms;
 307         __le64 rmac_ttl_4096_8191_frms;
 308         __le64 rmac_ttl_8192_max_frms;
 309         __le64 rmac_ttl_gt_max_frms;
 310         __le64 rmac_osized_alt_frms;
 311         __le64 rmac_jabber_alt_frms;
 312         __le64 rmac_gt_max_alt_frms;
 313         __le64 rmac_vlan_frms;
 314         __le32 rmac_len_discard;
 315         __le32 rmac_fcs_discard;
 316         __le32 rmac_pf_discard;
 317         __le32 rmac_da_discard;
 318         __le32 rmac_red_discard;
 319         __le32 rmac_rts_discard;
 320         __le32 reserved_12;
 321         __le32 rmac_ingm_full_discard;
 322         __le32 reserved_13;
 323         __le32 rmac_accepted_ip_oflow;
 324         __le32 reserved_14;
 325         __le32 link_fault_cnt;
 326         u8  buffer[20];
 327         struct swStat sw_stat;
 328         struct xpakStat xpak_stat;
 329 };
 330
 331 /* Default value for 'vlan_strip_tag' configuration parameter */
 332 #define NO_STRIP_IN_PROMISC 2
 333
 334 /*
 335  * Structures representing different init time configuration
 336  * parameters of the NIC.
 337  */
 338
 339 #define MAX_TX_FIFOS 8
 340 #define MAX_RX_RINGS 8
 341
 342 #define MAX_RX_DESC_1  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
 343 #define MAX_RX_DESC_2  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
 344 #define MAX_RX_DESC_3  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
 345 #define MAX_TX_DESC    (MAX_AVAILABLE_TXDS)
 346
 347 /* FIFO mappings for all possible number of fifos configured */
 348 static int fifo_map[][MAX_TX_FIFOS] = {
 349         {0, 0, 0, 0, 0, 0, 0, 0},
 350         {0, 0, 0, 0, 1, 1, 1, 1},
 351         {0, 0, 0, 1, 1, 1, 2, 2},
 352         {0, 0, 1, 1, 2, 2, 3, 3},
 353         {0, 0, 1, 1, 2, 2, 3, 4},
 354         {0, 0, 1, 1, 2, 3, 4, 5},
 355         {0, 0, 1, 2, 3, 4, 5, 6},
 356         {0, 1, 2, 3, 4, 5, 6, 7},
 357 };
 358
 359 /* Maintains Per FIFO related information. */
 360 struct tx_fifo_config {
 361 #define MAX_AVAILABLE_TXDS      8192
 362         u32 fifo_len;           /* specifies len of FIFO upto 8192, ie no of TxDLs */
 363 /* Priority definition */
 364 #define TX_FIFO_PRI_0               0   /*Highest */
 365 #define TX_FIFO_PRI_1               1
 366 #define TX_FIFO_PRI_2               2
 367 #define TX_FIFO_PRI_3               3
 368 #define TX_FIFO_PRI_4               4
 369 #define TX_FIFO_PRI_5               5
 370 #define TX_FIFO_PRI_6               6
 371 #define TX_FIFO_PRI_7               7   /*lowest */
 372         u8 fifo_priority;       /* specifies pointer level for FIFO */
 373         /* user should not set twos fifos with same pri */
 374         u8 f_no_snoop;
 375 #define NO_SNOOP_TXD                0x01
 376 #define NO_SNOOP_TXD_BUFFER          0x02
 377 };
 378
 379
 380 /* Maintains per Ring related information */
 381 struct rx_ring_config {
 382         u32 num_rxd;            /*No of RxDs per Rx Ring */
 383 #define RX_RING_PRI_0               0   /* highest */
 384 #define RX_RING_PRI_1               1
 385 #define RX_RING_PRI_2               2
 386 #define RX_RING_PRI_3               3
 387 #define RX_RING_PRI_4               4
 388 #define RX_RING_PRI_5               5
 389 #define RX_RING_PRI_6               6
 390 #define RX_RING_PRI_7               7   /* lowest */
 391
 392         u8 ring_priority;       /*Specifies service priority of ring */
 393         /* OSM should not set any two rings with same priority */
 394         u8 ring_org;            /*Organization of ring */
 395 #define RING_ORG_BUFF1          0x01
 396 #define RX_RING_ORG_BUFF3       0x03
 397 #define RX_RING_ORG_BUFF5       0x05
 398
 399         u8 f_no_snoop;
 400 #define NO_SNOOP_RXD                0x01
 401 #define NO_SNOOP_RXD_BUFFER         0x02
 402 };
 403
 404 /* This structure provides contains values of the tunable parameters
 405  * of the H/W
 406  */
 407 struct config_param {
 408 /* Tx Side */
 409         u32 tx_fifo_num;        /*Number of Tx FIFOs */
 410
 411         u8 fifo_mapping[MAX_TX_FIFOS];
 412         struct tx_fifo_config tx_cfg[MAX_TX_FIFOS];     /*Per-Tx FIFO config */
 413         u32 max_txds;           /*Max no. of Tx buffer descriptor per TxDL */
 414         u64 tx_intr_type;
 415 #define INTA    0
 416 #define MSI_X   2
 417         u8 intr_type;
 418
 419         /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
 420
 421 /* Rx Side */
 422         u32 rx_ring_num;        /*Number of receive rings */
 423 #define MAX_RX_BLOCKS_PER_RING  150
 424
 425         struct rx_ring_config rx_cfg[MAX_RX_RINGS];     /*Per-Rx Ring config */
 426         u8 bimodal;             /*Flag for setting bimodal interrupts*/
 427
 428 #define HEADER_ETHERNET_II_802_3_SIZE 14
 429 #define HEADER_802_2_SIZE              3
 430 #define HEADER_SNAP_SIZE               5
 431 #define HEADER_VLAN_SIZE               4
 432
 433 #define MIN_MTU                       46
 434 #define MAX_PYLD                    1500
 435 #define MAX_MTU                     (MAX_PYLD+18)
 436 #define MAX_MTU_VLAN                (MAX_PYLD+22)
 437 #define MAX_PYLD_JUMBO              9600
 438 #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
 439 #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
 440         u16 bus_speed;
 441 };
 442
 443 /* Structure representing MAC Addrs */
 444 struct mac_addr {
 445         u8 mac_addr[ETH_ALEN];
 446 };
 447
 448 /* Structure that represent every FIFO element in the BAR1
 449  * Address location.
 450  */
 451 struct TxFIFO_element {
 452         u64 TxDL_Pointer;
 453
 454         u64 List_Control;
 455 #define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
 456 #define TX_FIFO_FIRST_LIST             BIT(14)
 457 #define TX_FIFO_LAST_LIST              BIT(15)
 458 #define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
 459 #define TX_FIFO_SPECIAL_FUNC           BIT(23)
 460 #define TX_FIFO_DS_NO_SNOOP            BIT(31)
 461 #define TX_FIFO_BUFF_NO_SNOOP          BIT(30)
 462 };
 463
 464 /* Tx descriptor structure */
 465 struct TxD {
 466         u64 Control_1;
 467 /* bit mask */
 468 #define TXD_LIST_OWN_XENA       BIT(7)
 469 #define TXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 470 #define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))
 471 #define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)
 472 #define TXD_GATHER_CODE         (BIT(22) | BIT(23))
 473 #define TXD_GATHER_CODE_FIRST   BIT(22)
 474 #define TXD_GATHER_CODE_LAST    BIT(23)
 475 #define TXD_TCP_LSO_EN          BIT(30)
 476 #define TXD_UDP_COF_EN          BIT(31)
 477 #define TXD_UFO_EN              BIT(31) | BIT(30)
 478 #define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
 479 #define TXD_UFO_MSS(val)        vBIT(val,34,14)
 480 #define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
 481
 482         u64 Control_2;
 483 #define TXD_TX_CKO_CONTROL      (BIT(5)|BIT(6)|BIT(7))
 484 #define TXD_TX_CKO_IPV4_EN      BIT(5)
 485 #define TXD_TX_CKO_TCP_EN       BIT(6)
 486 #define TXD_TX_CKO_UDP_EN       BIT(7)
 487 #define TXD_VLAN_ENABLE         BIT(15)
 488 #define TXD_VLAN_TAG(val)       vBIT(val,16,16)
 489 #define TXD_INT_NUMBER(val)     vBIT(val,34,6)
 490 #define TXD_INT_TYPE_PER_LIST   BIT(47)
 491 #define TXD_INT_TYPE_UTILZ      BIT(46)
 492 #define TXD_SET_MARKER         vBIT(0x6,0,4)
 493
 494         u64 Buffer_Pointer;
 495         u64 Host_Control;       /* reserved for host */
 496 };
 497
 498 /* Structure to hold the phy and virt addr of every TxDL. */
 499 struct list_info_hold {
 500         dma_addr_t list_phy_addr;
 501         void *list_virt_addr;
 502 };
 503
 504 /* Rx descriptor structure for 1 buffer mode */
 505 struct RxD_t {
 506         u64 Host_Control;       /* reserved for host */
 507         u64 Control_1;
 508 #define RXD_OWN_XENA            BIT(7)
 509 #define RXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))
 510 #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
 511 #define RXD_FRAME_PROTO_IPV4    BIT(27)
 512 #define RXD_FRAME_PROTO_IPV6    BIT(28)
 513 #define RXD_FRAME_IP_FRAG       BIT(29)
 514 #define RXD_FRAME_PROTO_TCP     BIT(30)
 515 #define RXD_FRAME_PROTO_UDP     BIT(31)
 516 #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
 517 #define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)
 518 #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
 519
 520         u64 Control_2;
 521 #define THE_RXD_MARK            0x3
 522 #define SET_RXD_MARKER          vBIT(THE_RXD_MARK, 0, 2)
 523 #define GET_RXD_MARKER(ctrl)    ((ctrl & SET_RXD_MARKER) >> 62)
 524
 525 #define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)
 526 #define SET_VLAN_TAG(val)       vBIT(val,48,16)
 527 #define SET_NUM_TAG(val)       vBIT(val,16,32)
 528
 529
 530 };
 531 /* Rx descriptor structure for 1 buffer mode */
 532 struct RxD1 {
 533         struct RxD_t h;
 534
 535 #define MASK_BUFFER0_SIZE_1       vBIT(0x3FFF,2,14)
 536 #define SET_BUFFER0_SIZE_1(val)   vBIT(val,2,14)
 537 #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
 538         (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
 539         u64 Buffer0_ptr;
 540 };
 541 /* Rx descriptor structure for 3 or 2 buffer mode */
 542
 543 struct RxD3 {
 544         struct RxD_t h;
 545
 546 #define MASK_BUFFER0_SIZE_3       vBIT(0xFF,2,14)
 547 #define MASK_BUFFER1_SIZE_3       vBIT(0xFFFF,16,16)
 548 #define MASK_BUFFER2_SIZE_3       vBIT(0xFFFF,32,16)
 549 #define SET_BUFFER0_SIZE_3(val)   vBIT(val,8,8)
 550 #define SET_BUFFER1_SIZE_3(val)   vBIT(val,16,16)
 551 #define SET_BUFFER2_SIZE_3(val)   vBIT(val,32,16)
 552 #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
 553         (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
 554 #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
 555         (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
 556 #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
 557         (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
 558 #define BUF0_LEN        40
 559 #define BUF1_LEN        1
 560
 561         u64 Buffer0_ptr;
 562         u64 Buffer1_ptr;
 563         u64 Buffer2_ptr;
 564 };
 565
 566
 567 /* Structure that represents the Rx descriptor block which contains
 568  * 128 Rx descriptors.
 569  */
 570 struct RxD_block {
 571 #define MAX_RXDS_PER_BLOCK_1            127
 572         struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
 573
 574         u64 reserved_0;
 575 #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
 576         u64 reserved_1;         /* 0xFEFFFFFFFFFFFFFF to mark last
 577                                  * Rxd in this blk */
 578         u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
 579         u64 pNext_RxD_Blk_physical;     /* Buff0_ptr.In a 32 bit arch
 580                                          * the upper 32 bits should
 581                                          * be 0 */
 582 };
 583
 584 #define SIZE_OF_BLOCK   4096
 585
 586 #define RXD_MODE_1      0 /* One Buffer mode */
 587 #define RXD_MODE_3B     1 /* Two Buffer mode */
 588
 589 /* Structure to hold virtual addresses of Buf0 and Buf1 in
 590  * 2buf mode. */
 591 struct buffAdd {
 592         void *ba_0_org;
 593         void *ba_1_org;
 594         void *ba_0;
 595         void *ba_1;
 596 };
 597
 598 /* Structure which stores all the MAC control parameters */
 599
 600 /* This structure stores the offset of the RxD in the ring
 601  * from which the Rx Interrupt processor can start picking
 602  * up the RxDs for processing.
 603  */
 604 struct rx_curr_get_info {
 605         u32 block_index;
 606         u32 offset;
 607         u32 ring_len;
 608 };
 609
 610 struct rx_curr_put_info {
 611         u32 block_index;
 612         u32 offset;
 613         u32 ring_len;
 614 };
 615
 616 /* This structure stores the offset of the TxDl in the FIFO
 617  * from which the Tx Interrupt processor can start picking
 618  * up the TxDLs for send complete interrupt processing.
 619  */
 620 struct tx_curr_get_info {
 621         u32 offset;
 622         u32 fifo_len;
 623 };
 624
 625 struct tx_curr_put_info {
 626         u32 offset;
 627         u32 fifo_len;
 628 };
 629
 630 struct rxd_info {
 631         void *virt_addr;
 632         dma_addr_t dma_addr;
 633 };
 634
 635 /* Structure that holds the Phy and virt addresses of the Blocks */
 636 struct rx_block_info {
 637         void *block_virt_addr;
 638         dma_addr_t block_dma_addr;
 639         struct rxd_info *rxds;
 640 };
 641
 642 /* Ring specific structure */
 643 struct ring_info {
 644         /* The ring number */
 645         int ring_no;
 646
 647         /*
 648          *  Place holders for the virtual and physical addresses of
 649          *  all the Rx Blocks
 650          */
 651         struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
 652         int block_count;
 653         int pkt_cnt;
 654
 655         /*
 656          * Put pointer info which indictes which RxD has to be replenished
 657          * with a new buffer.
 658          */
 659         struct rx_curr_put_info rx_curr_put_info;
 660
 661         /*
 662          * Get pointer info which indictes which is the last RxD that was
 663          * processed by the driver.
 664          */
 665         struct rx_curr_get_info rx_curr_get_info;
 666
 667         /* Index to the absolute position of the put pointer of Rx ring */
 668         int put_pos;
 669
 670         /* Buffer Address store. */
 671         struct buffAdd **ba;
 672         struct s2io_nic *nic;
 673 };
 674
 675 /* Fifo specific structure */
 676 struct fifo_info {
 677         /* FIFO number */
 678         int fifo_no;
 679
 680         /* Maximum TxDs per TxDL */
 681         int max_txds;
 682
 683         /* Place holder of all the TX List's Phy and Virt addresses. */
 684         struct list_info_hold *list_info;
 685
 686         /*
 687          * Current offset within the tx FIFO where driver would write
 688          * new Tx frame
 689          */
 690         struct tx_curr_put_info tx_curr_put_info;
 691
 692         /*
 693          * Current offset within tx FIFO from where the driver would start freeing
 694          * the buffers
 695          */
 696         struct tx_curr_get_info tx_curr_get_info;
 697
 698         struct s2io_nic *nic;
 699 };
 700
 701 /* Information related to the Tx and Rx FIFOs and Rings of Xena
 702  * is maintained in this structure.
 703  */
 704 struct mac_info {
 705 /* tx side stuff */
 706         /* logical pointer of start of each Tx FIFO */
 707         struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
 708
 709         /* Fifo specific structure */
 710         struct fifo_info fifos[MAX_TX_FIFOS];
 711
 712         /* Save virtual address of TxD page with zero DMA addr(if any) */
 713         void *zerodma_virt_addr;
 714
 715 /* rx side stuff */
 716         /* Ring specific structure */
 717         struct ring_info rings[MAX_RX_RINGS];
 718
 719         u16 rmac_pause_time;
 720         u16 mc_pause_threshold_q0q3;
 721         u16 mc_pause_threshold_q4q7;
 722
 723         void *stats_mem;        /* orignal pointer to allocated mem */
 724         dma_addr_t stats_mem_phy;       /* Physical address of the stat block */
 725         u32 stats_mem_sz;
 726         struct stat_block *stats_info;  /* Logical address of the stat block */
 727 };
 728
 729 /* structure representing the user defined MAC addresses */
 730 struct usr_addr {
 731         char addr[ETH_ALEN];
 732         int usage_cnt;
 733 };
 734
 735 /* Default Tunable parameters of the NIC. */
 736 #define DEFAULT_FIFO_0_LEN 4096
 737 #define DEFAULT_FIFO_1_7_LEN 512
 738 #define SMALL_BLK_CNT   30
 739 #define LARGE_BLK_CNT   100
 740
 741 /*
 742  * Structure to keep track of the MSI-X vectors and the corresponding
 743  * argument registered against each vector
 744  */
 745 #define MAX_REQUESTED_MSI_X     17
 746 struct s2io_msix_entry
 747 {
 748         u16 vector;
 749         u16 entry;
 750         void *arg;
 751
 752         u8 type;
 753 #define MSIX_FIFO_TYPE  1
 754 #define MSIX_RING_TYPE  2
 755
 756         u8 in_use;
 757 #define MSIX_REGISTERED_SUCCESS 0xAA
 758 };
 759
 760 struct msix_info_st {
 761         u64 addr;
 762         u64 data;
 763 };
 764
 765 /* Data structure to represent a LRO session */
 766 struct lro {
 767         struct sk_buff  *parent;
 768         struct sk_buff  *last_frag;
 769         u8              *l2h;
 770         struct iphdr    *iph;
 771         struct tcphdr   *tcph;
 772         u32             tcp_next_seq;
 773         __be32          tcp_ack;
 774         int             total_len;
 775         int             frags_len;
 776         int             sg_num;
 777         int             in_use;
 778         __be16          window;
 779         u32             cur_tsval;
 780         u32             cur_tsecr;
 781         u8              saw_ts;
 782 };
 783
 784 /* Structure representing one instance of the NIC */
 785 struct s2io_nic {
 786         int rxd_mode;
 787         /*
 788          * Count of packets to be processed in a given iteration, it will be indicated
 789          * by the quota field of the device structure when NAPI is enabled.
 790          */
 791         int pkts_to_process;
 792         struct net_device *dev;
 793         struct napi_struct napi;
 794         struct mac_info mac_control;
 795         struct config_param config;
 796         struct pci_dev *pdev;
 797         void __iomem *bar0;
 798         void __iomem *bar1;
 799 #define MAX_MAC_SUPPORTED   16
 800 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
 801
 802         struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];
 803
 804         struct net_device_stats stats;
 805         int high_dma_flag;
 806         int device_enabled_once;
 807
 808         char name[60];
 809         struct tasklet_struct task;
 810         volatile unsigned long tasklet_status;
 811
 812         /* Timer that handles I/O errors/exceptions */
 813         struct timer_list alarm_timer;
 814
 815         /* Space to back up the PCI config space */
 816         u32 config_space[256 / sizeof(u32)];
 817
 818         atomic_t rx_bufs_left[MAX_RX_RINGS];
 819
 820         spinlock_t tx_lock;
 821         spinlock_t put_lock;
 822
 823 #define PROMISC     1
 824 #define ALL_MULTI   2
 825
 826 #define MAX_ADDRS_SUPPORTED 64
 827         u16 usr_addr_count;
 828         u16 mc_addr_count;
 829         struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];
 830
 831         u16 m_cast_flg;
 832         u16 all_multi_pos;
 833         u16 promisc_flg;
 834
 835         /*  Id timer, used to blink NIC to physically identify NIC. */
 836         struct timer_list id_timer;
 837
 838         /*  Restart timer, used to restart NIC if the device is stuck and
 839          *  a schedule task that will set the correct Link state once the
 840          *  NIC's PHY has stabilized after a state change.
 841          */
 842         struct work_struct rst_timer_task;
 843         struct work_struct set_link_task;
 844
 845         /* Flag that can be used to turn on or turn off the Rx checksum
 846          * offload feature.
 847          */
 848         int rx_csum;
 849
 850         /*  after blink, the adapter must be restored with original
 851          *  values.
 852          */
 853         u64 adapt_ctrl_org;
 854
 855         /* Last known link state. */
 856         u16 last_link_state;
 857 #define LINK_DOWN       1
 858 #define LINK_UP         2
 859
 860         int task_flag;
 861         unsigned long long start_time;
 862 #define CARD_DOWN 1
 863 #define CARD_UP 2
 864         atomic_t card_state;
 865         volatile unsigned long link_state;
 866         struct vlan_group *vlgrp;
 867 #define MSIX_FLG                0xA5
 868         struct msix_entry *entries;
 869         int msi_detected;
 870         wait_queue_head_t msi_wait;
 871         struct s2io_msix_entry *s2io_entries;
 872         char desc[MAX_REQUESTED_MSI_X][25];
 873
 874         int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
 875
 876         struct msix_info_st msix_info[0x3f];
 877
 878 #define XFRAME_I_DEVICE         1
 879 #define XFRAME_II_DEVICE        2
 880         u8 device_type;
 881
 882 #define MAX_LRO_SESSIONS        32
 883         struct lro lro0_n[MAX_LRO_SESSIONS];
 884         unsigned long   clubbed_frms_cnt;
 885         unsigned long   sending_both;
 886         u8              lro;
 887         u16             lro_max_aggr_per_sess;
 888
 889 #define INTA    0
 890 #define MSI_X   2
 891         u8 intr_type;
 892
 893         spinlock_t      rx_lock;
 894         atomic_t        isr_cnt;
 895         u64 *ufo_in_band_v;
 896 #define VPD_STRING_LEN 80
 897         u8  product_name[VPD_STRING_LEN];
 898         u8  serial_num[VPD_STRING_LEN];
 899 };
 900
 901 #define RESET_ERROR 1;
 902 #define CMD_ERROR   2;
 903
 904 /*  OS related system calls */
 905 #ifndef readq
 906 static inline u64 readq(void __iomem *addr)
 907 {
 908         u64 ret = 0;
 909         ret = readl(addr + 4);
 910         ret <<= 32;
 911         ret |= readl(addr);
 912
 913         return ret;
 914 }
 915 #endif
 916
 917 #ifndef writeq
 918 static inline void writeq(u64 val, void __iomem *addr)
 919 {
 920         writel((u32) (val), addr);
 921         writel((u32) (val >> 32), (addr + 4));
 922 }
 923 #endif
 924
 925 /*
 926  * Some registers have to be written in a particular order to
 927  * expect correct hardware operation. The macro SPECIAL_REG_WRITE
 928  * is used to perform such ordered writes. Defines UF (Upper First)
 929  * and LF (Lower First) will be used to specify the required write order.
 930  */
 931 #define UF      1
 932 #define LF      2
 933 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
 934 {
 935         u32 ret;
 936
 937         if (order == LF) {
 938                 writel((u32) (val), addr);
 939                 ret = readl(addr);
 940                 writel((u32) (val >> 32), (addr + 4));
 941                 ret = readl(addr + 4);
 942         } else {
 943                 writel((u32) (val >> 32), (addr + 4));
 944                 ret = readl(addr + 4);
 945                 writel((u32) (val), addr);
 946                 ret = readl(addr);
 947         }
 948 }
 949
 950 /*  Interrupt related values of Xena */
 951
 952 #define ENABLE_INTRS    1
 953 #define DISABLE_INTRS   2
 954
 955 /*  Highest level interrupt blocks */
 956 #define TX_PIC_INTR     (0x0001<<0)
 957 #define TX_DMA_INTR     (0x0001<<1)
 958 #define TX_MAC_INTR     (0x0001<<2)
 959 #define TX_XGXS_INTR    (0x0001<<3)
 960 #define TX_TRAFFIC_INTR (0x0001<<4)
 961 #define RX_PIC_INTR     (0x0001<<5)
 962 #define RX_DMA_INTR     (0x0001<<6)
 963 #define RX_MAC_INTR     (0x0001<<7)
 964 #define RX_XGXS_INTR    (0x0001<<8)
 965 #define RX_TRAFFIC_INTR (0x0001<<9)
 966 #define MC_INTR         (0x0001<<10)
 967 #define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
 968                             TX_DMA_INTR     | \
 969                             TX_MAC_INTR     | \
 970                             TX_XGXS_INTR    | \
 971                             TX_TRAFFIC_INTR | \
 972                             RX_PIC_INTR     | \
 973                             RX_DMA_INTR     | \
 974                             RX_MAC_INTR     | \
 975                             RX_XGXS_INTR    | \
 976                             RX_TRAFFIC_INTR | \
 977                             MC_INTR )
 978
 979 /*  Interrupt masks for the general interrupt mask register */
 980 #define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL
 981
 982 #define TXPIC_INT_M         BIT(0)
 983 #define TXDMA_INT_M         BIT(1)
 984 #define TXMAC_INT_M         BIT(2)
 985 #define TXXGXS_INT_M        BIT(3)
 986 #define TXTRAFFIC_INT_M     BIT(8)
 987 #define PIC_RX_INT_M        BIT(32)
 988 #define RXDMA_INT_M         BIT(33)
 989 #define RXMAC_INT_M         BIT(34)
 990 #define MC_INT_M            BIT(35)
 991 #define RXXGXS_INT_M        BIT(36)
 992 #define RXTRAFFIC_INT_M     BIT(40)
 993
 994 /*  PIC level Interrupts TODO*/
 995
 996 /*  DMA level Inressupts */
 997 #define TXDMA_PFC_INT_M     BIT(0)
 998 #define TXDMA_PCC_INT_M     BIT(2)
 999
1000 /*  PFC block interrupts */
1001 #define PFC_MISC_ERR_1      BIT(0)      /* Interrupt to indicate FIFO full */
1002
1003 /* PCC block interrupts. */
1004 #define PCC_FB_ECC_ERR     vBIT(0xff, 16, 8)    /* Interrupt to indicate
1005                                                    PCC_FB_ECC Error. */
1006
1007 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1008 /*
1009  * Prototype declaration.
1010  */
1011 static int __devinit s2io_init_nic(struct pci_dev *pdev,
1012                                    const struct pci_device_id *pre);
1013 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1014 static int init_shared_mem(struct s2io_nic *sp);
1015 static void free_shared_mem(struct s2io_nic *sp);
1016 static int init_nic(struct s2io_nic *nic);
1017 static void rx_intr_handler(struct ring_info *ring_data);
1018 static void tx_intr_handler(struct fifo_info *fifo_data);
1019 static void alarm_intr_handler(struct s2io_nic *sp);
1020
1021 static int s2io_starter(void);
1022 static void s2io_closer(void);
1023 static void s2io_tx_watchdog(struct net_device *dev);
1024 static void s2io_tasklet(unsigned long dev_addr);
1025 static void s2io_set_multicast(struct net_device *dev);
1026 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1027 static void s2io_link(struct s2io_nic * sp, int link);
1028 static void s2io_reset(struct s2io_nic * sp);
1029 static int s2io_poll(struct napi_struct *napi, int budget);
1030 static void s2io_init_pci(struct s2io_nic * sp);
1031 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
1032 static void s2io_alarm_handle(unsigned long data);
1033 static irqreturn_t
1034 s2io_msix_ring_handle(int irq, void *dev_id);
1035 static irqreturn_t
1036 s2io_msix_fifo_handle(int irq, void *dev_id);
1037 static irqreturn_t s2io_isr(int irq, void *dev_id);
1038 static int verify_xena_quiescence(struct s2io_nic *sp);
1039 static const struct ethtool_ops netdev_ethtool_ops;
1040 static void s2io_set_link(struct work_struct *work);
1041 static int s2io_set_swapper(struct s2io_nic * sp);
1042 static void s2io_card_down(struct s2io_nic *nic);
1043 static int s2io_card_up(struct s2io_nic *nic);
1044 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1045                                         int bit_state);
1046 static int s2io_add_isr(struct s2io_nic * sp);
1047 static void s2io_rem_isr(struct s2io_nic * sp);
1048
1049 static void restore_xmsi_data(struct s2io_nic *nic);
1050
1051 static int
1052 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1053                       struct RxD_t *rxdp, struct s2io_nic *sp);
1054 static void clear_lro_session(struct lro *lro);
1055 static void queue_rx_frame(struct sk_buff *skb);
1056 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1057 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1058                            struct sk_buff *skb, u32 tcp_len);
1059 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1060
1061 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1062                                               pci_channel_state_t state);
1063 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1064 static void s2io_io_resume(struct pci_dev *pdev);
1065
1066 #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1067 #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1068 #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1069
1070 #define S2IO_PARM_INT(X, def_val) \
1071         static unsigned int X = def_val;\
1072                 module_param(X , uint, 0);
1073
1074 #endif                          /* _S2IO_H */