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1 /* Silan SC92031 PCI Fast Ethernet Adapter driver
2 *
3 * Based on vendor drivers:
4 * Silan Fast Ethernet Netcard Driver:
5 * MODULE_AUTHOR ("gaoyonghong");
6 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
7 * MODULE_LICENSE("GPL");
8 * 8139D Fast Ethernet driver:
9 * (C) 2002 by gaoyonghong
10 * MODULE_AUTHOR ("gaoyonghong");
11 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
12 * MODULE_LICENSE("GPL");
13 * Both are almost identical and seem to be based on pci-skeleton.c
14 *
15 * Rewritten for 2.6 by Cesar Eduardo Barros
16 */
17
18 /* Note about set_mac_address: I don't know how to change the hardware
19 * matching, so you need to enable IFF_PROMISC when using it.
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/pci.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/crc32.h>
31
32 #include <asm/irq.h>
33
34 #define PCI_VENDOR_ID_SILAN 0x1904
35 #define PCI_DEVICE_ID_SILAN_SC92031 0x2031
36 #define PCI_DEVICE_ID_SILAN_8139D 0x8139
37
38 #define SC92031_NAME "sc92031"
39 #define SC92031_DESCRIPTION "Silan SC92031 PCI Fast Ethernet Adapter driver"
40 #define SC92031_VERSION "2.0c"
41
42 /* BAR 0 is MMIO, BAR 1 is PIO */
43 #ifndef SC92031_USE_BAR
44 #define SC92031_USE_BAR 0
45 #endif
46
47 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
48 static int multicast_filter_limit = 64;
49 module_param(multicast_filter_limit, int, 0);
50 MODULE_PARM_DESC(multicast_filter_limit,
51 "Maximum number of filtered multicast addresses");
52
53 static int media;
54 module_param(media, int, 0);
55 MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
56 " 0x01 = 10M half, 0x02 = 10M full,"
57 " 0x04 = 100M half, 0x08 = 100M full)");
58
59 /* Size of the in-memory receive ring. */
60 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
61 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
62
63 /* Number of Tx descriptor registers. */
64 #define NUM_TX_DESC 4
65
66 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
67 #define MAX_ETH_FRAME_SIZE 1536
68
69 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
70 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
71 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
72
73 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
74 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
75
76 /* Time in jiffies before concluding the transmitter is hung. */
77 #define TX_TIMEOUT (4*HZ)
78
79 #define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
80
81 /* media options */
82 #define AUTOSELECT 0x00
83 #define M10_HALF 0x01
84 #define M10_FULL 0x02
85 #define M100_HALF 0x04
86 #define M100_FULL 0x08
87
88 /* Symbolic offsets to registers. */
89 enum silan_registers {
90 Config0 = 0x00, // Config0
91 Config1 = 0x04, // Config1
92 RxBufWPtr = 0x08, // Rx buffer writer poiter
93 IntrStatus = 0x0C, // Interrupt status
94 IntrMask = 0x10, // Interrupt mask
95 RxbufAddr = 0x14, // Rx buffer start address
96 RxBufRPtr = 0x18, // Rx buffer read pointer
97 Txstatusall = 0x1C, // Transmit status of all descriptors
98 TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
99 TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
100 RxConfig = 0x40, // Rx configuration
101 MAC0 = 0x44, // Ethernet hardware address.
102 MAR0 = 0x4C, // Multicast filter.
103 RxStatus0 = 0x54, // Rx status
104 TxConfig = 0x5C, // Tx configuration
105 PhyCtrl = 0x60, // physical control
106 FlowCtrlConfig = 0x64, // flow control
107 Miicmd0 = 0x68, // Mii command0 register
108 Miicmd1 = 0x6C, // Mii command1 register
109 Miistatus = 0x70, // Mii status register
110 Timercnt = 0x74, // Timer counter register
111 TimerIntr = 0x78, // Timer interrupt register
112 PMConfig = 0x7C, // Power Manager configuration
113 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
114 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
115 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
116 TestD0 = 0xD0,
117 TestD4 = 0xD4,
118 TestD8 = 0xD8,
119 };
120
121 #define MII_BMCR 0 // Basic mode control register
122 #define MII_BMSR 1 // Basic mode status register
123 #define MII_JAB 16
124 #define MII_OutputStatus 24
125
126 #define BMCR_FULLDPLX 0x0100 // Full duplex
127 #define BMCR_ANRESTART 0x0200 // Auto negotiation restart
128 #define BMCR_ANENABLE 0x1000 // Enable auto negotiation
129 #define BMCR_SPEED100 0x2000 // Select 100Mbps
130 #define BMSR_LSTATUS 0x0004 // Link status
131 #define PHY_16_JAB_ENB 0x1000
132 #define PHY_16_PORT_ENB 0x1
133
134 enum IntrStatusBits {
135 LinkFail = 0x80000000,
136 LinkOK = 0x40000000,
137 TimeOut = 0x20000000,
138 RxOverflow = 0x0040,
139 RxOK = 0x0020,
140 TxOK = 0x0001,
141 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
142 };
143
144 enum TxStatusBits {
145 TxCarrierLost = 0x20000000,
146 TxAborted = 0x10000000,
147 TxOutOfWindow = 0x08000000,
148 TxNccShift = 22,
149 EarlyTxThresShift = 16,
150 TxStatOK = 0x8000,
151 TxUnderrun = 0x4000,
152 TxOwn = 0x2000,
153 };
154
155 enum RxStatusBits {
156 RxStatesOK = 0x80000,
157 RxBadAlign = 0x40000,
158 RxHugeFrame = 0x20000,
159 RxSmallFrame = 0x10000,
160 RxCRCOK = 0x8000,
161 RxCrlFrame = 0x4000,
162 Rx_Broadcast = 0x2000,
163 Rx_Multicast = 0x1000,
164 RxAddrMatch = 0x0800,
165 MiiErr = 0x0400,
166 };
167
168 enum RxConfigBits {
169 RxFullDx = 0x80000000,
170 RxEnb = 0x40000000,
171 RxSmall = 0x20000000,
172 RxHuge = 0x10000000,
173 RxErr = 0x08000000,
174 RxAllphys = 0x04000000,
175 RxMulticast = 0x02000000,
176 RxBroadcast = 0x01000000,
177 RxLoopBack = (1 << 23) | (1 << 22),
178 LowThresholdShift = 12,
179 HighThresholdShift = 2,
180 };
181
182 enum TxConfigBits {
183 TxFullDx = 0x80000000,
184 TxEnb = 0x40000000,
185 TxEnbPad = 0x20000000,
186 TxEnbHuge = 0x10000000,
187 TxEnbFCS = 0x08000000,
188 TxNoBackOff = 0x04000000,
189 TxEnbPrem = 0x02000000,
190 TxCareLostCrs = 0x1000000,
191 TxExdCollNum = 0xf00000,
192 TxDataRate = 0x80000,
193 };
194
195 enum PhyCtrlconfigbits {
196 PhyCtrlAne = 0x80000000,
197 PhyCtrlSpd100 = 0x40000000,
198 PhyCtrlSpd10 = 0x20000000,
199 PhyCtrlPhyBaseAddr = 0x1f000000,
200 PhyCtrlDux = 0x800000,
201 PhyCtrlReset = 0x400000,
202 };
203
204 enum FlowCtrlConfigBits {
205 FlowCtrlFullDX = 0x80000000,
206 FlowCtrlEnb = 0x40000000,
207 };
208
209 enum Config0Bits {
210 Cfg0_Reset = 0x80000000,
211 Cfg0_Anaoff = 0x40000000,
212 Cfg0_LDPS = 0x20000000,
213 };
214
215 enum Config1Bits {
216 Cfg1_EarlyRx = 1 << 31,
217 Cfg1_EarlyTx = 1 << 30,
218
219 //rx buffer size
220 Cfg1_Rcv8K = 0x0,
221 Cfg1_Rcv16K = 0x1,
222 Cfg1_Rcv32K = 0x3,
223 Cfg1_Rcv64K = 0x7,
224 Cfg1_Rcv128K = 0xf,
225 };
226
227 enum MiiCmd0Bits {
228 Mii_Divider = 0x20000000,
229 Mii_WRITE = 0x400000,
230 Mii_READ = 0x200000,
231 Mii_SCAN = 0x100000,
232 Mii_Tamod = 0x80000,
233 Mii_Drvmod = 0x40000,
234 Mii_mdc = 0x20000,
235 Mii_mdoen = 0x10000,
236 Mii_mdo = 0x8000,
237 Mii_mdi = 0x4000,
238 };
239
240 enum MiiStatusBits {
241 Mii_StatusBusy = 0x80000000,
242 };
243
244 enum PMConfigBits {
245 PM_Enable = 1 << 31,
246 PM_LongWF = 1 << 30,
247 PM_Magic = 1 << 29,
248 PM_LANWake = 1 << 28,
249 PM_LWPTN = (1 << 27 | 1<< 26),
250 PM_LinkUp = 1 << 25,
251 PM_WakeUp = 1 << 24,
252 };
253
254 /* Locking rules:
255 * priv->lock protects most of the fields of priv and most of the
256 * hardware registers. It does not have to protect against softirqs
257 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
258 * it also does not need to be used in ->open and ->stop while the
259 * device interrupts are off.
260 * Not having to protect against softirqs is very useful due to heavy
261 * use of mdelay() at _sc92031_reset.
262 * Functions prefixed with _sc92031_ must be called with the lock held;
263 * functions prefixed with sc92031_ must be called without the lock held.
264 * Use mmiowb() before unlocking if the hardware was written to.
265 */
266
267 /* Locking rules for the interrupt:
268 * - the interrupt and the tasklet never run at the same time
269 * - neither run between sc92031_disable_interrupts and
270 * sc92031_enable_interrupt
271 */
272
273 struct sc92031_priv {
274 spinlock_t lock;
275 /* iomap.h cookie */
276 void __iomem *port_base;
277 /* pci device structure */
278 struct pci_dev *pdev;
279 /* tasklet */
280 struct tasklet_struct tasklet;
281
282 /* CPU address of rx ring */
283 void *rx_ring;
284 /* PCI address of rx ring */
285 dma_addr_t rx_ring_dma_addr;
286 /* PCI address of rx ring read pointer */
287 dma_addr_t rx_ring_tail;
288
289 /* tx ring write index */
290 unsigned tx_head;
291 /* tx ring read index */
292 unsigned tx_tail;
293 /* CPU address of tx bounce buffer */
294 void *tx_bufs;
295 /* PCI address of tx bounce buffer */
296 dma_addr_t tx_bufs_dma_addr;
297
298 /* copies of some hardware registers */
299 u32 intr_status;
300 atomic_t intr_mask;
301 u32 rx_config;
302 u32 tx_config;
303 u32 pm_config;
304
305 /* copy of some flags from dev->flags */
306 unsigned int mc_flags;
307
308 /* for ETHTOOL_GSTATS */
309 u64 tx_timeouts;
310 u64 rx_loss;
311
312 /* for dev->get_stats */
313 long rx_value;
314 struct net_device_stats stats;
315 };
316
317 /* I don't know which registers can be safely read; however, I can guess
318 * MAC0 is one of them. */
319 static inline void _sc92031_dummy_read(void __iomem *port_base)
320 {
321 ioread32(port_base + MAC0);
322 }
323
324 static u32 _sc92031_mii_wait(void __iomem *port_base)
325 {
326 u32 mii_status;
327
328 do {
329 udelay(10);
330 mii_status = ioread32(port_base + Miistatus);
331 } while (mii_status & Mii_StatusBusy);
332
333 return mii_status;
334 }
335
336 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
337 {
338 iowrite32(Mii_Divider, port_base + Miicmd0);
339
340 _sc92031_mii_wait(port_base);
341
342 iowrite32(cmd1, port_base + Miicmd1);
343 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
344
345 return _sc92031_mii_wait(port_base);
346 }
347
348 static void _sc92031_mii_scan(void __iomem *port_base)
349 {
350 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
351 }
352
353 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
354 {
355 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
356 }
357
358 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
359 {
360 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
361 }
362
363 static void sc92031_disable_interrupts(struct net_device *dev)
364 {
365 struct sc92031_priv *priv = netdev_priv(dev);
366 void __iomem *port_base = priv->port_base;
367
368 /* tell the tasklet/interrupt not to enable interrupts */
369 atomic_set(&priv->intr_mask, 0);
370 wmb();
371
372 /* stop interrupts */
373 iowrite32(0, port_base + IntrMask);
374 _sc92031_dummy_read(port_base);
375 mmiowb();
376
377 /* wait for any concurrent interrupt/tasklet to finish */
378 synchronize_irq(dev->irq);
379 tasklet_disable(&priv->tasklet);
380 }
381
382 static void sc92031_enable_interrupts(struct net_device *dev)
383 {
384 struct sc92031_priv *priv = netdev_priv(dev);
385 void __iomem *port_base = priv->port_base;
386
387 tasklet_enable(&priv->tasklet);
388
389 atomic_set(&priv->intr_mask, IntrBits);
390 wmb();
391
392 iowrite32(IntrBits, port_base + IntrMask);
393 mmiowb();
394 }
395
396 static void _sc92031_disable_tx_rx(struct net_device *dev)
397 {
398 struct sc92031_priv *priv = netdev_priv(dev);
399 void __iomem *port_base = priv->port_base;
400
401 priv->rx_config &= ~RxEnb;
402 priv->tx_config &= ~TxEnb;
403 iowrite32(priv->rx_config, port_base + RxConfig);
404 iowrite32(priv->tx_config, port_base + TxConfig);
405 }
406
407 static void _sc92031_enable_tx_rx(struct net_device *dev)
408 {
409 struct sc92031_priv *priv = netdev_priv(dev);
410 void __iomem *port_base = priv->port_base;
411
412 priv->rx_config |= RxEnb;
413 priv->tx_config |= TxEnb;
414 iowrite32(priv->rx_config, port_base + RxConfig);
415 iowrite32(priv->tx_config, port_base + TxConfig);
416 }
417
418 static void _sc92031_tx_clear(struct net_device *dev)
419 {
420 struct sc92031_priv *priv = netdev_priv(dev);
421
422 while (priv->tx_head - priv->tx_tail > 0) {
423 priv->tx_tail++;
424 priv->stats.tx_dropped++;
425 }
426 priv->tx_head = priv->tx_tail = 0;
427 }
428
429 static void _sc92031_set_mar(struct net_device *dev)
430 {
431 struct sc92031_priv *priv = netdev_priv(dev);
432 void __iomem *port_base = priv->port_base;
433 u32 mar0 = 0, mar1 = 0;
434
435 if ((dev->flags & IFF_PROMISC)
436 || dev->mc_count > multicast_filter_limit
437 || (dev->flags & IFF_ALLMULTI))
438 mar0 = mar1 = 0xffffffff;
439 else if (dev->flags & IFF_MULTICAST) {
440 struct dev_mc_list *mc_list;
441
442 for (mc_list = dev->mc_list; mc_list; mc_list = mc_list->next) {
443 u32 crc;
444 unsigned bit = 0;
445
446 crc = ~ether_crc(ETH_ALEN, mc_list->dmi_addr);
447 crc >>= 24;
448
449 if (crc & 0x01) bit |= 0x02;
450 if (crc & 0x02) bit |= 0x01;
451 if (crc & 0x10) bit |= 0x20;
452 if (crc & 0x20) bit |= 0x10;
453 if (crc & 0x40) bit |= 0x08;
454 if (crc & 0x80) bit |= 0x04;
455
456 if (bit > 31)
457 mar0 |= 0x1 << (bit - 32);
458 else
459 mar1 |= 0x1 << bit;
460 }
461 }
462
463 iowrite32(mar0, port_base + MAR0);
464 iowrite32(mar1, port_base + MAR0 + 4);
465 }
466
467 static void _sc92031_set_rx_config(struct net_device *dev)
468 {
469 struct sc92031_priv *priv = netdev_priv(dev);
470 void __iomem *port_base = priv->port_base;
471 unsigned int old_mc_flags;
472 u32 rx_config_bits = 0;
473
474 old_mc_flags = priv->mc_flags;
475
476 if (dev->flags & IFF_PROMISC)
477 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
478 | RxMulticast | RxAllphys;
479
480 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
481 rx_config_bits |= RxMulticast;
482
483 if (dev->flags & IFF_BROADCAST)
484 rx_config_bits |= RxBroadcast;
485
486 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
487 | RxMulticast | RxAllphys);
488 priv->rx_config |= rx_config_bits;
489
490 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
491 | IFF_MULTICAST | IFF_BROADCAST);
492
493 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
494 iowrite32(priv->rx_config, port_base + RxConfig);
495 }
496
497 static bool _sc92031_check_media(struct net_device *dev)
498 {
499 struct sc92031_priv *priv = netdev_priv(dev);
500 void __iomem *port_base = priv->port_base;
501 u16 bmsr;
502
503 bmsr = _sc92031_mii_read(port_base, MII_BMSR);
504 rmb();
505 if (bmsr & BMSR_LSTATUS) {
506 bool speed_100, duplex_full;
507 u32 flow_ctrl_config = 0;
508 u16 output_status = _sc92031_mii_read(port_base,
509 MII_OutputStatus);
510 _sc92031_mii_scan(port_base);
511
512 speed_100 = output_status & 0x2;
513 duplex_full = output_status & 0x4;
514
515 /* Initial Tx/Rx configuration */
516 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
517 priv->tx_config = 0x48800000;
518
519 /* NOTE: vendor driver had dead code here to enable tx padding */
520
521 if (!speed_100)
522 priv->tx_config |= 0x80000;
523
524 // configure rx mode
525 _sc92031_set_rx_config(dev);
526
527 if (duplex_full) {
528 priv->rx_config |= RxFullDx;
529 priv->tx_config |= TxFullDx;
530 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
531 } else {
532 priv->rx_config &= ~RxFullDx;
533 priv->tx_config &= ~TxFullDx;
534 }
535
536 _sc92031_set_mar(dev);
537 _sc92031_set_rx_config(dev);
538 _sc92031_enable_tx_rx(dev);
539 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
540
541 netif_carrier_on(dev);
542
543 if (printk_ratelimit())
544 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
545 dev->name,
546 speed_100 ? "100" : "10",
547 duplex_full ? "full" : "half");
548 return true;
549 } else {
550 _sc92031_mii_scan(port_base);
551
552 netif_carrier_off(dev);
553
554 _sc92031_disable_tx_rx(dev);
555
556 if (printk_ratelimit())
557 printk(KERN_INFO "%s: link down\n", dev->name);
558 return false;
559 }
560 }
561
562 static void _sc92031_phy_reset(struct net_device *dev)
563 {
564 struct sc92031_priv *priv = netdev_priv(dev);
565 void __iomem *port_base = priv->port_base;
566 u32 phy_ctrl;
567
568 phy_ctrl = ioread32(port_base + PhyCtrl);
569 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
570 phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
571
572 switch (media) {
573 default:
574 case AUTOSELECT:
575 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
576 break;
577 case M10_HALF:
578 phy_ctrl |= PhyCtrlSpd10;
579 break;
580 case M10_FULL:
581 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
582 break;
583 case M100_HALF:
584 phy_ctrl |= PhyCtrlSpd100;
585 break;
586 case M100_FULL:
587 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
588 break;
589 }
590
591 iowrite32(phy_ctrl, port_base + PhyCtrl);
592 mdelay(10);
593
594 phy_ctrl &= ~PhyCtrlReset;
595 iowrite32(phy_ctrl, port_base + PhyCtrl);
596 mdelay(1);
597
598 _sc92031_mii_write(port_base, MII_JAB,
599 PHY_16_JAB_ENB | PHY_16_PORT_ENB);
600 _sc92031_mii_scan(port_base);
601
602 netif_carrier_off(dev);
603 netif_stop_queue(dev);
604 }
605
606 static void _sc92031_reset(struct net_device *dev)
607 {
608 struct sc92031_priv *priv = netdev_priv(dev);
609 void __iomem *port_base = priv->port_base;
610
611 /* disable PM */
612 iowrite32(0, port_base + PMConfig);
613
614 /* soft reset the chip */
615 iowrite32(Cfg0_Reset, port_base + Config0);
616 mdelay(200);
617
618 iowrite32(0, port_base + Config0);
619 mdelay(10);
620
621 /* disable interrupts */
622 iowrite32(0, port_base + IntrMask);
623
624 /* clear multicast address */
625 iowrite32(0, port_base + MAR0);
626 iowrite32(0, port_base + MAR0 + 4);
627
628 /* init rx ring */
629 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
630 priv->rx_ring_tail = priv->rx_ring_dma_addr;
631
632 /* init tx ring */
633 _sc92031_tx_clear(dev);
634
635 /* clear old register values */
636 priv->intr_status = 0;
637 atomic_set(&priv->intr_mask, 0);
638 priv->rx_config = 0;
639 priv->tx_config = 0;
640 priv->mc_flags = 0;
641
642 /* configure rx buffer size */
643 /* NOTE: vendor driver had dead code here to enable early tx/rx */
644 iowrite32(Cfg1_Rcv64K, port_base + Config1);
645
646 _sc92031_phy_reset(dev);
647 _sc92031_check_media(dev);
648
649 /* calculate rx fifo overflow */
650 priv->rx_value = 0;
651
652 /* enable PM */
653 iowrite32(priv->pm_config, port_base + PMConfig);
654
655 /* clear intr register */
656 ioread32(port_base + IntrStatus);
657 }
658
659 static void _sc92031_tx_tasklet(struct net_device *dev)
660 {
661 struct sc92031_priv *priv = netdev_priv(dev);
662 void __iomem *port_base = priv->port_base;
663
664 unsigned old_tx_tail;
665 unsigned entry;
666 u32 tx_status;
667
668 old_tx_tail = priv->tx_tail;
669 while (priv->tx_head - priv->tx_tail > 0) {
670 entry = priv->tx_tail % NUM_TX_DESC;
671 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
672
673 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
674 break;
675
676 priv->tx_tail++;
677
678 if (tx_status & TxStatOK) {
679 priv->stats.tx_bytes += tx_status & 0x1fff;
680 priv->stats.tx_packets++;
681 /* Note: TxCarrierLost is always asserted at 100mbps. */
682 priv->stats.collisions += (tx_status >> 22) & 0xf;
683 }
684
685 if (tx_status & (TxOutOfWindow | TxAborted)) {
686 priv->stats.tx_errors++;
687
688 if (tx_status & TxAborted)
689 priv->stats.tx_aborted_errors++;
690
691 if (tx_status & TxCarrierLost)
692 priv->stats.tx_carrier_errors++;
693
694 if (tx_status & TxOutOfWindow)
695 priv->stats.tx_window_errors++;
696 }
697
698 if (tx_status & TxUnderrun)
699 priv->stats.tx_fifo_errors++;
700 }
701
702 if (priv->tx_tail != old_tx_tail)
703 if (netif_queue_stopped(dev))
704 netif_wake_queue(dev);
705 }
706
707 static void _sc92031_rx_tasklet_error(u32 rx_status,
708 struct sc92031_priv *priv, unsigned rx_size)
709 {
710 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
711 priv->stats.rx_errors++;
712 priv->stats.rx_length_errors++;
713 }
714
715 if (!(rx_status & RxStatesOK)) {
716 priv->stats.rx_errors++;
717
718 if (rx_status & (RxHugeFrame | RxSmallFrame))
719 priv->stats.rx_length_errors++;
720
721 if (rx_status & RxBadAlign)
722 priv->stats.rx_frame_errors++;
723
724 if (!(rx_status & RxCRCOK))
725 priv->stats.rx_crc_errors++;
726 } else
727 priv->rx_loss++;
728 }
729
730 static void _sc92031_rx_tasklet(struct net_device *dev)
731 {
732 struct sc92031_priv *priv = netdev_priv(dev);
733 void __iomem *port_base = priv->port_base;
734
735 dma_addr_t rx_ring_head;
736 unsigned rx_len;
737 unsigned rx_ring_offset;
738 void *rx_ring = priv->rx_ring;
739
740 rx_ring_head = ioread32(port_base + RxBufWPtr);
741 rmb();
742
743 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
744 * we need to change it to 32 bits physical address
745 */
746 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
747 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
748 if (rx_ring_head < priv->rx_ring_dma_addr)
749 rx_ring_head += RX_BUF_LEN;
750
751 if (rx_ring_head >= priv->rx_ring_tail)
752 rx_len = rx_ring_head - priv->rx_ring_tail;
753 else
754 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
755
756 if (!rx_len)
757 return;
758
759 if (unlikely(rx_len > RX_BUF_LEN)) {
760 if (printk_ratelimit())
761 printk(KERN_ERR "%s: rx packets length > rx buffer\n",
762 dev->name);
763 return;
764 }
765
766 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
767
768 while (rx_len) {
769 u32 rx_status;
770 unsigned rx_size, rx_size_align, pkt_size;
771 struct sk_buff *skb;
772
773 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
774 rmb();
775
776 rx_size = rx_status >> 20;
777 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
778 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
779
780 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
781
782 if (unlikely(rx_status == 0
783 || rx_size > (MAX_ETH_FRAME_SIZE + 4)
784 || rx_size < 16
785 || !(rx_status & RxStatesOK))) {
786 _sc92031_rx_tasklet_error(rx_status, priv, rx_size);
787 break;
788 }
789
790 if (unlikely(rx_size_align + 4 > rx_len)) {
791 if (printk_ratelimit())
792 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
793 break;
794 }
795
796 rx_len -= rx_size_align + 4;
797
798 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
799 if (unlikely(!skb)) {
800 if (printk_ratelimit())
801 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
802 dev->name, pkt_size);
803 goto next;
804 }
805
806 skb_reserve(skb, NET_IP_ALIGN);
807
808 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
809 memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset),
810 rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset);
811 memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)),
812 rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset));
813 } else {
814 memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size);
815 }
816
817 skb->dev = dev;
818 skb->protocol = eth_type_trans(skb, dev);
819 dev->last_rx = jiffies;
820 netif_rx(skb);
821
822 priv->stats.rx_bytes += pkt_size;
823 priv->stats.rx_packets++;
824
825 if (rx_status & Rx_Multicast)
826 priv->stats.multicast++;
827
828 next:
829 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
830 }
831 mb();
832
833 priv->rx_ring_tail = rx_ring_head;
834 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
835 }
836
837 static void _sc92031_link_tasklet(struct net_device *dev)
838 {
839 struct sc92031_priv *priv = netdev_priv(dev);
840
841 if (_sc92031_check_media(dev))
842 netif_wake_queue(dev);
843 else {
844 netif_stop_queue(dev);
845 priv->stats.tx_carrier_errors++;
846 }
847 }
848
849 static void sc92031_tasklet(unsigned long data)
850 {
851 struct net_device *dev = (struct net_device *)data;
852 struct sc92031_priv *priv = netdev_priv(dev);
853 void __iomem *port_base = priv->port_base;
854 u32 intr_status, intr_mask;
855
856 intr_status = priv->intr_status;
857
858 spin_lock(&priv->lock);
859
860 if (unlikely(!netif_running(dev)))
861 goto out;
862
863 if (intr_status & TxOK)
864 _sc92031_tx_tasklet(dev);
865
866 if (intr_status & RxOK)
867 _sc92031_rx_tasklet(dev);
868
869 if (intr_status & RxOverflow)
870 priv->stats.rx_errors++;
871
872 if (intr_status & TimeOut) {
873 priv->stats.rx_errors++;
874 priv->stats.rx_length_errors++;
875 }
876
877 if (intr_status & (LinkFail | LinkOK))
878 _sc92031_link_tasklet(dev);
879
880 out:
881 intr_mask = atomic_read(&priv->intr_mask);
882 rmb();
883
884 iowrite32(intr_mask, port_base + IntrMask);
885 mmiowb();
886
887 spin_unlock(&priv->lock);
888 }
889
890 static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
891 {
892 struct net_device *dev = dev_id;
893 struct sc92031_priv *priv = netdev_priv(dev);
894 void __iomem *port_base = priv->port_base;
895 u32 intr_status, intr_mask;
896
897 /* mask interrupts before clearing IntrStatus */
898 iowrite32(0, port_base + IntrMask);
899 _sc92031_dummy_read(port_base);
900
901 intr_status = ioread32(port_base + IntrStatus);
902 if (unlikely(intr_status == 0xffffffff))
903 return IRQ_NONE; // hardware has gone missing
904
905 intr_status &= IntrBits;
906 if (!intr_status)
907 goto out_none;
908
909 priv->intr_status = intr_status;
910 tasklet_schedule(&priv->tasklet);
911
912 return IRQ_HANDLED;
913
914 out_none:
915 intr_mask = atomic_read(&priv->intr_mask);
916 rmb();
917
918 iowrite32(intr_mask, port_base + IntrMask);
919 mmiowb();
920
921 return IRQ_NONE;
922 }
923
924 static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
925 {
926 struct sc92031_priv *priv = netdev_priv(dev);
927 void __iomem *port_base = priv->port_base;
928
929 // FIXME I do not understand what is this trying to do.
930 if (netif_running(dev)) {
931 int temp;
932
933 spin_lock_bh(&priv->lock);
934
935 /* Update the error count. */
936 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
937
938 if (temp == 0xffff) {
939 priv->rx_value += temp;
940 priv->stats.rx_fifo_errors = priv->rx_value;
941 } else {
942 priv->stats.rx_fifo_errors = temp + priv->rx_value;
943 }
944
945 spin_unlock_bh(&priv->lock);
946 }
947
948 return &priv->stats;
949 }
950
951 static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev)
952 {
953 int err = 0;
954 struct sc92031_priv *priv = netdev_priv(dev);
955 void __iomem *port_base = priv->port_base;
956
957 unsigned len;
958 unsigned entry;
959 u32 tx_status;
960
961 if (unlikely(skb->len > TX_BUF_SIZE)) {
962 err = -EMSGSIZE;
963 priv->stats.tx_dropped++;
964 goto out;
965 }
966
967 spin_lock(&priv->lock);
968
969 if (unlikely(!netif_carrier_ok(dev))) {
970 err = -ENOLINK;
971 priv->stats.tx_dropped++;
972 goto out_unlock;
973 }
974
975 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
976
977 entry = priv->tx_head++ % NUM_TX_DESC;
978
979 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
980
981 len = skb->len;
982 if (unlikely(len < ETH_ZLEN)) {
983 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
984 0, ETH_ZLEN - len);
985 len = ETH_ZLEN;
986 }
987
988 wmb();
989
990 if (len < 100)
991 tx_status = len;
992 else if (len < 300)
993 tx_status = 0x30000 | len;
994 else
995 tx_status = 0x50000 | len;
996
997 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
998 port_base + TxAddr0 + entry * 4);
999 iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
1000 mmiowb();
1001
1002 dev->trans_start = jiffies;
1003
1004 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
1005 netif_stop_queue(dev);
1006
1007 out_unlock:
1008 spin_unlock(&priv->lock);
1009
1010 out:
1011 dev_kfree_skb(skb);
1012
1013 return err;
1014 }
1015
1016 static int sc92031_open(struct net_device *dev)
1017 {
1018 int err;
1019 struct sc92031_priv *priv = netdev_priv(dev);
1020 struct pci_dev *pdev = priv->pdev;
1021
1022 priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
1023 &priv->rx_ring_dma_addr);
1024 if (unlikely(!priv->rx_ring)) {
1025 err = -ENOMEM;
1026 goto out_alloc_rx_ring;
1027 }
1028
1029 priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1030 &priv->tx_bufs_dma_addr);
1031 if (unlikely(!priv->tx_bufs)) {
1032 err = -ENOMEM;
1033 goto out_alloc_tx_bufs;
1034 }
1035 priv->tx_head = priv->tx_tail = 0;
1036
1037 err = request_irq(pdev->irq, sc92031_interrupt,
1038 IRQF_SHARED, dev->name, dev);
1039 if (unlikely(err < 0))
1040 goto out_request_irq;
1041
1042 priv->pm_config = 0;
1043
1044 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1045 spin_lock_bh(&priv->lock);
1046
1047 _sc92031_reset(dev);
1048 mmiowb();
1049
1050 spin_unlock_bh(&priv->lock);
1051 sc92031_enable_interrupts(dev);
1052
1053 if (netif_carrier_ok(dev))
1054 netif_start_queue(dev);
1055 else
1056 netif_tx_disable(dev);
1057
1058 return 0;
1059
1060 out_request_irq:
1061 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1062 priv->tx_bufs_dma_addr);
1063 out_alloc_tx_bufs:
1064 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1065 priv->rx_ring_dma_addr);
1066 out_alloc_rx_ring:
1067 return err;
1068 }
1069
1070 static int sc92031_stop(struct net_device *dev)
1071 {
1072 struct sc92031_priv *priv = netdev_priv(dev);
1073 struct pci_dev *pdev = priv->pdev;
1074
1075 netif_tx_disable(dev);
1076
1077 /* Disable interrupts, stop Tx and Rx. */
1078 sc92031_disable_interrupts(dev);
1079
1080 spin_lock_bh(&priv->lock);
1081
1082 _sc92031_disable_tx_rx(dev);
1083 _sc92031_tx_clear(dev);
1084 mmiowb();
1085
1086 spin_unlock_bh(&priv->lock);
1087
1088 free_irq(pdev->irq, dev);
1089 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1090 priv->tx_bufs_dma_addr);
1091 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1092 priv->rx_ring_dma_addr);
1093
1094 return 0;
1095 }
1096
1097 static void sc92031_set_multicast_list(struct net_device *dev)
1098 {
1099 struct sc92031_priv *priv = netdev_priv(dev);
1100
1101 spin_lock_bh(&priv->lock);
1102
1103 _sc92031_set_mar(dev);
1104 _sc92031_set_rx_config(dev);
1105 mmiowb();
1106
1107 spin_unlock_bh(&priv->lock);
1108 }
1109
1110 static void sc92031_tx_timeout(struct net_device *dev)
1111 {
1112 struct sc92031_priv *priv = netdev_priv(dev);
1113
1114 /* Disable interrupts by clearing the interrupt mask.*/
1115 sc92031_disable_interrupts(dev);
1116
1117 spin_lock(&priv->lock);
1118
1119 priv->tx_timeouts++;
1120
1121 _sc92031_reset(dev);
1122 mmiowb();
1123
1124 spin_unlock(&priv->lock);
1125
1126 /* enable interrupts */
1127 sc92031_enable_interrupts(dev);
1128
1129 if (netif_carrier_ok(dev))
1130 netif_wake_queue(dev);
1131 }
1132
1133 #ifdef CONFIG_NET_POLL_CONTROLLER
1134 static void sc92031_poll_controller(struct net_device *dev)
1135 {
1136 disable_irq(dev->irq);
1137 if (sc92031_interrupt(dev->irq, dev) != IRQ_NONE)
1138 sc92031_tasklet((unsigned long)dev);
1139 enable_irq(dev->irq);
1140 }
1141 #endif
1142
1143 static int sc92031_ethtool_get_settings(struct net_device *dev,
1144 struct ethtool_cmd *cmd)
1145 {
1146 struct sc92031_priv *priv = netdev_priv(dev);
1147 void __iomem *port_base = priv->port_base;
1148 u8 phy_address;
1149 u32 phy_ctrl;
1150 u16 output_status;
1151
1152 spin_lock_bh(&priv->lock);
1153
1154 phy_address = ioread32(port_base + Miicmd1) >> 27;
1155 phy_ctrl = ioread32(port_base + PhyCtrl);
1156
1157 output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1158 _sc92031_mii_scan(port_base);
1159 mmiowb();
1160
1161 spin_unlock_bh(&priv->lock);
1162
1163 cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1164 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1165 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1166
1167 cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
1168
1169 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1170 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1171 cmd->advertising |= ADVERTISED_Autoneg;
1172
1173 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1174 cmd->advertising |= ADVERTISED_10baseT_Half;
1175
1176 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1177 == (PhyCtrlSpd10 | PhyCtrlDux))
1178 cmd->advertising |= ADVERTISED_10baseT_Full;
1179
1180 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1181 cmd->advertising |= ADVERTISED_100baseT_Half;
1182
1183 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1184 == (PhyCtrlSpd100 | PhyCtrlDux))
1185 cmd->advertising |= ADVERTISED_100baseT_Full;
1186
1187 if (phy_ctrl & PhyCtrlAne)
1188 cmd->advertising |= ADVERTISED_Autoneg;
1189
1190 cmd->speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1191 cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1192 cmd->port = PORT_MII;
1193 cmd->phy_address = phy_address;
1194 cmd->transceiver = XCVR_INTERNAL;
1195 cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1196
1197 return 0;
1198 }
1199
1200 static int sc92031_ethtool_set_settings(struct net_device *dev,
1201 struct ethtool_cmd *cmd)
1202 {
1203 struct sc92031_priv *priv = netdev_priv(dev);
1204 void __iomem *port_base = priv->port_base;
1205 u32 phy_ctrl;
1206 u32 old_phy_ctrl;
1207
1208 if (!(cmd->speed == SPEED_10 || cmd->speed == SPEED_100))
1209 return -EINVAL;
1210 if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL))
1211 return -EINVAL;
1212 if (!(cmd->port == PORT_MII))
1213 return -EINVAL;
1214 if (!(cmd->phy_address == 0x1f))
1215 return -EINVAL;
1216 if (!(cmd->transceiver == XCVR_INTERNAL))
1217 return -EINVAL;
1218 if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE))
1219 return -EINVAL;
1220
1221 if (cmd->autoneg == AUTONEG_ENABLE) {
1222 if (!(cmd->advertising & (ADVERTISED_Autoneg
1223 | ADVERTISED_100baseT_Full
1224 | ADVERTISED_100baseT_Half
1225 | ADVERTISED_10baseT_Full
1226 | ADVERTISED_10baseT_Half)))
1227 return -EINVAL;
1228
1229 phy_ctrl = PhyCtrlAne;
1230
1231 // FIXME: I'm not sure what the original code was trying to do
1232 if (cmd->advertising & ADVERTISED_Autoneg)
1233 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1234 if (cmd->advertising & ADVERTISED_100baseT_Full)
1235 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1236 if (cmd->advertising & ADVERTISED_100baseT_Half)
1237 phy_ctrl |= PhyCtrlSpd100;
1238 if (cmd->advertising & ADVERTISED_10baseT_Full)
1239 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1240 if (cmd->advertising & ADVERTISED_10baseT_Half)
1241 phy_ctrl |= PhyCtrlSpd10;
1242 } else {
1243 // FIXME: Whole branch guessed
1244 phy_ctrl = 0;
1245
1246 if (cmd->speed == SPEED_10)
1247 phy_ctrl |= PhyCtrlSpd10;
1248 else /* cmd->speed == SPEED_100 */
1249 phy_ctrl |= PhyCtrlSpd100;
1250
1251 if (cmd->duplex == DUPLEX_FULL)
1252 phy_ctrl |= PhyCtrlDux;
1253 }
1254
1255 spin_lock_bh(&priv->lock);
1256
1257 old_phy_ctrl = ioread32(port_base + PhyCtrl);
1258 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1259 | PhyCtrlSpd100 | PhyCtrlSpd10);
1260 if (phy_ctrl != old_phy_ctrl)
1261 iowrite32(phy_ctrl, port_base + PhyCtrl);
1262
1263 spin_unlock_bh(&priv->lock);
1264
1265 return 0;
1266 }
1267
1268 static void sc92031_ethtool_get_drvinfo(struct net_device *dev,
1269 struct ethtool_drvinfo *drvinfo)
1270 {
1271 struct sc92031_priv *priv = netdev_priv(dev);
1272 struct pci_dev *pdev = priv->pdev;
1273
1274 strcpy(drvinfo->driver, SC92031_NAME);
1275 strcpy(drvinfo->version, SC92031_VERSION);
1276 strcpy(drvinfo->bus_info, pci_name(pdev));
1277 }
1278
1279 static void sc92031_ethtool_get_wol(struct net_device *dev,
1280 struct ethtool_wolinfo *wolinfo)
1281 {
1282 struct sc92031_priv *priv = netdev_priv(dev);
1283 void __iomem *port_base = priv->port_base;
1284 u32 pm_config;
1285
1286 spin_lock_bh(&priv->lock);
1287 pm_config = ioread32(port_base + PMConfig);
1288 spin_unlock_bh(&priv->lock);
1289
1290 // FIXME: Guessed
1291 wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1292 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1293 wolinfo->wolopts = 0;
1294
1295 if (pm_config & PM_LinkUp)
1296 wolinfo->wolopts |= WAKE_PHY;
1297
1298 if (pm_config & PM_Magic)
1299 wolinfo->wolopts |= WAKE_MAGIC;
1300
1301 if (pm_config & PM_WakeUp)
1302 // FIXME: Guessed
1303 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1304 }
1305
1306 static int sc92031_ethtool_set_wol(struct net_device *dev,
1307 struct ethtool_wolinfo *wolinfo)
1308 {
1309 struct sc92031_priv *priv = netdev_priv(dev);
1310 void __iomem *port_base = priv->port_base;
1311 u32 pm_config;
1312
1313 spin_lock_bh(&priv->lock);
1314
1315 pm_config = ioread32(port_base + PMConfig)
1316 & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1317
1318 if (wolinfo->wolopts & WAKE_PHY)
1319 pm_config |= PM_LinkUp;
1320
1321 if (wolinfo->wolopts & WAKE_MAGIC)
1322 pm_config |= PM_Magic;
1323
1324 // FIXME: Guessed
1325 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1326 pm_config |= PM_WakeUp;
1327
1328 priv->pm_config = pm_config;
1329 iowrite32(pm_config, port_base + PMConfig);
1330 mmiowb();
1331
1332 spin_unlock_bh(&priv->lock);
1333
1334 return 0;
1335 }
1336
1337 static int sc92031_ethtool_nway_reset(struct net_device *dev)
1338 {
1339 int err = 0;
1340 struct sc92031_priv *priv = netdev_priv(dev);
1341 void __iomem *port_base = priv->port_base;
1342 u16 bmcr;
1343
1344 spin_lock_bh(&priv->lock);
1345
1346 bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1347 if (!(bmcr & BMCR_ANENABLE)) {
1348 err = -EINVAL;
1349 goto out;
1350 }
1351
1352 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1353
1354 out:
1355 _sc92031_mii_scan(port_base);
1356 mmiowb();
1357
1358 spin_unlock_bh(&priv->lock);
1359
1360 return err;
1361 }
1362
1363 static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1364 "tx_timeout",
1365 "rx_loss",
1366 };
1367
1368 static void sc92031_ethtool_get_strings(struct net_device *dev,
1369 u32 stringset, u8 *data)
1370 {
1371 if (stringset == ETH_SS_STATS)
1372 memcpy(data, sc92031_ethtool_stats_strings,
1373 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1374 }
1375
1376 static int sc92031_ethtool_get_stats_count(struct net_device *dev)
1377 {
1378 return SILAN_STATS_NUM;
1379 }
1380
1381 static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1382 struct ethtool_stats *stats, u64 *data)
1383 {
1384 struct sc92031_priv *priv = netdev_priv(dev);
1385
1386 spin_lock_bh(&priv->lock);
1387 data[0] = priv->tx_timeouts;
1388 data[1] = priv->rx_loss;
1389 spin_unlock_bh(&priv->lock);
1390 }
1391
1392 static struct ethtool_ops sc92031_ethtool_ops = {
1393 .get_settings = sc92031_ethtool_get_settings,
1394 .set_settings = sc92031_ethtool_set_settings,
1395 .get_drvinfo = sc92031_ethtool_get_drvinfo,
1396 .get_wol = sc92031_ethtool_get_wol,
1397 .set_wol = sc92031_ethtool_set_wol,
1398 .nway_reset = sc92031_ethtool_nway_reset,
1399 .get_link = ethtool_op_get_link,
1400 .get_tx_csum = ethtool_op_get_tx_csum,
1401 .get_sg = ethtool_op_get_sg,
1402 .get_tso = ethtool_op_get_tso,
1403 .get_strings = sc92031_ethtool_get_strings,
1404 .get_stats_count = sc92031_ethtool_get_stats_count,
1405 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
1406 .get_perm_addr = ethtool_op_get_perm_addr,
1407 .get_ufo = ethtool_op_get_ufo,
1408 };
1409
1410 static int __devinit sc92031_probe(struct pci_dev *pdev,
1411 const struct pci_device_id *id)
1412 {
1413 int err;
1414 void __iomem* port_base;
1415 struct net_device *dev;
1416 struct sc92031_priv *priv;
1417 u32 mac0, mac1;
1418
1419 err = pci_enable_device(pdev);
1420 if (unlikely(err < 0))
1421 goto out_enable_device;
1422
1423 pci_set_master(pdev);
1424
1425 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1426 if (unlikely(err < 0))
1427 goto out_set_dma_mask;
1428
1429 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1430 if (unlikely(err < 0))
1431 goto out_set_dma_mask;
1432
1433 err = pci_request_regions(pdev, SC92031_NAME);
1434 if (unlikely(err < 0))
1435 goto out_request_regions;
1436
1437 port_base = pci_iomap(pdev, SC92031_USE_BAR, 0);
1438 if (unlikely(!port_base)) {
1439 err = -EIO;
1440 goto out_iomap;
1441 }
1442
1443 dev = alloc_etherdev(sizeof(struct sc92031_priv));
1444 if (unlikely(!dev)) {
1445 err = -ENOMEM;
1446 goto out_alloc_etherdev;
1447 }
1448
1449 pci_set_drvdata(pdev, dev);
1450
1451 #if SC92031_USE_BAR == 0
1452 dev->mem_start = pci_resource_start(pdev, SC92031_USE_BAR);
1453 dev->mem_end = pci_resource_end(pdev, SC92031_USE_BAR);
1454 #elif SC92031_USE_BAR == 1
1455 dev->base_addr = pci_resource_start(pdev, SC92031_USE_BAR);
1456 #endif
1457 dev->irq = pdev->irq;
1458
1459 /* faked with skb_copy_and_csum_dev */
1460 dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1461
1462 dev->get_stats = sc92031_get_stats;
1463 dev->ethtool_ops = &sc92031_ethtool_ops;
1464 dev->hard_start_xmit = sc92031_start_xmit;
1465 dev->watchdog_timeo = TX_TIMEOUT;
1466 dev->open = sc92031_open;
1467 dev->stop = sc92031_stop;
1468 dev->set_multicast_list = sc92031_set_multicast_list;
1469 dev->tx_timeout = sc92031_tx_timeout;
1470 #ifdef CONFIG_NET_POLL_CONTROLLER
1471 dev->poll_controller = sc92031_poll_controller;
1472 #endif
1473
1474 priv = netdev_priv(dev);
1475 spin_lock_init(&priv->lock);
1476 priv->port_base = port_base;
1477 priv->pdev = pdev;
1478 tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1479 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1480 * sc92031_open will work correctly */
1481 tasklet_disable_nosync(&priv->tasklet);
1482
1483 /* PCI PM Wakeup */
1484 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1485
1486 mac0 = ioread32(port_base + MAC0);
1487 mac1 = ioread32(port_base + MAC0 + 4);
1488 dev->dev_addr[0] = dev->perm_addr[0] = mac0 >> 24;
1489 dev->dev_addr[1] = dev->perm_addr[1] = mac0 >> 16;
1490 dev->dev_addr[2] = dev->perm_addr[2] = mac0 >> 8;
1491 dev->dev_addr[3] = dev->perm_addr[3] = mac0;
1492 dev->dev_addr[4] = dev->perm_addr[4] = mac1 >> 8;
1493 dev->dev_addr[5] = dev->perm_addr[5] = mac1;
1494
1495 err = register_netdev(dev);
1496 if (err < 0)
1497 goto out_register_netdev;
1498
1499 return 0;
1500
1501 out_register_netdev:
1502 free_netdev(dev);
1503 out_alloc_etherdev:
1504 pci_iounmap(pdev, port_base);
1505 out_iomap:
1506 pci_release_regions(pdev);
1507 out_request_regions:
1508 out_set_dma_mask:
1509 pci_disable_device(pdev);
1510 out_enable_device:
1511 return err;
1512 }
1513
1514 static void __devexit sc92031_remove(struct pci_dev *pdev)
1515 {
1516 struct net_device *dev = pci_get_drvdata(pdev);
1517 struct sc92031_priv *priv = netdev_priv(dev);
1518 void __iomem* port_base = priv->port_base;
1519
1520 unregister_netdev(dev);
1521 free_netdev(dev);
1522 pci_iounmap(pdev, port_base);
1523 pci_release_regions(pdev);
1524 pci_disable_device(pdev);
1525 }
1526
1527 static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1528 {
1529 struct net_device *dev = pci_get_drvdata(pdev);
1530 struct sc92031_priv *priv = netdev_priv(dev);
1531
1532 pci_save_state(pdev);
1533
1534 if (!netif_running(dev))
1535 goto out;
1536
1537 netif_device_detach(dev);
1538
1539 /* Disable interrupts, stop Tx and Rx. */
1540 sc92031_disable_interrupts(dev);
1541
1542 spin_lock_bh(&priv->lock);
1543
1544 _sc92031_disable_tx_rx(dev);
1545 _sc92031_tx_clear(dev);
1546 mmiowb();
1547
1548 spin_unlock_bh(&priv->lock);
1549
1550 out:
1551 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1552
1553 return 0;
1554 }
1555
1556 static int sc92031_resume(struct pci_dev *pdev)
1557 {
1558 struct net_device *dev = pci_get_drvdata(pdev);
1559 struct sc92031_priv *priv = netdev_priv(dev);
1560
1561 pci_restore_state(pdev);
1562 pci_set_power_state(pdev, PCI_D0);
1563
1564 if (!netif_running(dev))
1565 goto out;
1566
1567 /* Interrupts already disabled by sc92031_suspend */
1568 spin_lock_bh(&priv->lock);
1569
1570 _sc92031_reset(dev);
1571 mmiowb();
1572
1573 spin_unlock_bh(&priv->lock);
1574 sc92031_enable_interrupts(dev);
1575
1576 netif_device_attach(dev);
1577
1578 if (netif_carrier_ok(dev))
1579 netif_wake_queue(dev);
1580 else
1581 netif_tx_disable(dev);
1582
1583 out:
1584 return 0;
1585 }
1586
1587 static struct pci_device_id sc92031_pci_device_id_table[] __devinitdata = {
1588 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_SC92031) },
1589 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_8139D) },
1590 { 0, }
1591 };
1592 MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1593
1594 static struct pci_driver sc92031_pci_driver = {
1595 .name = SC92031_NAME,
1596 .id_table = sc92031_pci_device_id_table,
1597 .probe = sc92031_probe,
1598 .remove = __devexit_p(sc92031_remove),
1599 .suspend = sc92031_suspend,
1600 .resume = sc92031_resume,
1601 };
1602
1603 static int __init sc92031_init(void)
1604 {
1605 printk(KERN_INFO SC92031_DESCRIPTION " " SC92031_VERSION "\n");
1606 return pci_register_driver(&sc92031_pci_driver);
1607 }
1608
1609 static void __exit sc92031_exit(void)
1610 {
1611 pci_unregister_driver(&sc92031_pci_driver);
1612 }
1613
1614 module_init(sc92031_init);
1615 module_exit(sc92031_exit);
1616
1617 MODULE_LICENSE("GPL");
1618 MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1619 MODULE_DESCRIPTION(SC92031_DESCRIPTION);
1620 MODULE_VERSION(SC92031_VERSION);
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