1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include "net_driver.h"
23 #include "falcon_hwdefs.h"
24 #include "falcon_io.h"
28 #include "workarounds.h"
30 /* Falcon hardware control.
31 * Falcon is the internal codename for the SFC4000 controller that is
32 * present in SFE400X evaluation boards
36 * struct falcon_nic_data - Falcon NIC state
37 * @next_buffer_table: First available buffer table id
38 * @pci_dev2: The secondary PCI device if present
40 struct falcon_nic_data
{
41 unsigned next_buffer_table
;
42 struct pci_dev
*pci_dev2
;
45 /**************************************************************************
49 **************************************************************************
52 static int disable_dma_stats
;
54 /* This is set to 16 for a good reason. In summary, if larger than
55 * 16, the descriptor cache holds more than a default socket
56 * buffer's worth of packets (for UDP we can only have at most one
57 * socket buffer's worth outstanding). This combined with the fact
58 * that we only get 1 TX event per descriptor cache means the NIC
61 #define TX_DC_ENTRIES 16
62 #define TX_DC_ENTRIES_ORDER 0
63 #define TX_DC_BASE 0x130000
65 #define RX_DC_ENTRIES 64
66 #define RX_DC_ENTRIES_ORDER 2
67 #define RX_DC_BASE 0x100000
69 /* RX FIFO XOFF watermark
71 * When the amount of the RX FIFO increases used increases past this
72 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
73 * This also has an effect on RX/TX arbitration
75 static int rx_xoff_thresh_bytes
= -1;
76 module_param(rx_xoff_thresh_bytes
, int, 0644);
77 MODULE_PARM_DESC(rx_xoff_thresh_bytes
, "RX fifo XOFF threshold");
79 /* RX FIFO XON watermark
81 * When the amount of the RX FIFO used decreases below this
82 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
83 * This also has an effect on RX/TX arbitration
85 static int rx_xon_thresh_bytes
= -1;
86 module_param(rx_xon_thresh_bytes
, int, 0644);
87 MODULE_PARM_DESC(rx_xon_thresh_bytes
, "RX fifo XON threshold");
89 /* TX descriptor ring size - min 512 max 4k */
90 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
91 #define FALCON_TXD_RING_SIZE 1024
92 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
94 /* RX descriptor ring size - min 512 max 4k */
95 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
96 #define FALCON_RXD_RING_SIZE 1024
97 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
99 /* Event queue size - max 32k */
100 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
101 #define FALCON_EVQ_SIZE 4096
102 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
104 /* Max number of internal errors. After this resets will not be performed */
105 #define FALCON_MAX_INT_ERRORS 4
107 /* Maximum period that we wait for flush events. If the flush event
108 * doesn't arrive in this period of time then we check if the queue
109 * was disabled anyway. */
110 #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
112 /**************************************************************************
116 **************************************************************************
119 /* DMA address mask (up to 46-bit, avoiding compiler warnings)
121 * Note that it is possible to have a platform with 64-bit longs and
122 * 32-bit DMA addresses, or vice versa. EFX_DMA_MASK takes care of the
125 #if BITS_PER_LONG == 64
126 #define FALCON_DMA_MASK EFX_DMA_MASK(0x00003fffffffffffUL)
128 #define FALCON_DMA_MASK EFX_DMA_MASK(0x00003fffffffffffULL)
131 /* TX DMA length mask (13-bit) */
132 #define FALCON_TX_DMA_MASK (4096 - 1)
134 /* Size and alignment of special buffers (4KB) */
135 #define FALCON_BUF_SIZE 4096
137 /* Dummy SRAM size code */
138 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
140 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
141 #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
142 #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
143 #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
144 #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
145 #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
147 #define FALCON_IS_DUAL_FUNC(efx) \
148 (falcon_rev(efx) < FALCON_REV_B0)
150 /**************************************************************************
152 * Falcon hardware access
154 **************************************************************************/
156 /* Read the current event from the event queue */
157 static inline efx_qword_t
*falcon_event(struct efx_channel
*channel
,
160 return (((efx_qword_t
*) (channel
->eventq
.addr
)) + index
);
163 /* See if an event is present
165 * We check both the high and low dword of the event for all ones. We
166 * wrote all ones when we cleared the event, and no valid event can
167 * have all ones in either its high or low dwords. This approach is
168 * robust against reordering.
170 * Note that using a single 64-bit comparison is incorrect; even
171 * though the CPU read will be atomic, the DMA write may not be.
173 static inline int falcon_event_present(efx_qword_t
*event
)
175 return (!(EFX_DWORD_IS_ALL_ONES(event
->dword
[0]) |
176 EFX_DWORD_IS_ALL_ONES(event
->dword
[1])));
179 /**************************************************************************
181 * I2C bus - this is a bit-bashing interface using GPIO pins
182 * Note that it uses the output enables to tristate the outputs
183 * SDA is the data pin and SCL is the clock
185 **************************************************************************
187 static void falcon_setsdascl(struct efx_i2c_interface
*i2c
)
191 falcon_read(i2c
->efx
, ®
, GPIO_CTL_REG_KER
);
192 EFX_SET_OWORD_FIELD(reg
, GPIO0_OEN
, (i2c
->scl
? 0 : 1));
193 EFX_SET_OWORD_FIELD(reg
, GPIO3_OEN
, (i2c
->sda
? 0 : 1));
194 falcon_write(i2c
->efx
, ®
, GPIO_CTL_REG_KER
);
197 static int falcon_getsda(struct efx_i2c_interface
*i2c
)
201 falcon_read(i2c
->efx
, ®
, GPIO_CTL_REG_KER
);
202 return EFX_OWORD_FIELD(reg
, GPIO3_IN
);
205 static int falcon_getscl(struct efx_i2c_interface
*i2c
)
209 falcon_read(i2c
->efx
, ®
, GPIO_CTL_REG_KER
);
210 return EFX_DWORD_FIELD(reg
, GPIO0_IN
);
213 static struct efx_i2c_bit_operations falcon_i2c_bit_operations
= {
214 .setsda
= falcon_setsdascl
,
215 .setscl
= falcon_setsdascl
,
216 .getsda
= falcon_getsda
,
217 .getscl
= falcon_getscl
,
222 /**************************************************************************
224 * Falcon special buffer handling
225 * Special buffers are used for event queues and the TX and RX
228 *************************************************************************/
231 * Initialise a Falcon special buffer
233 * This will define a buffer (previously allocated via
234 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
235 * it to be used for event queues, descriptor rings etc.
238 falcon_init_special_buffer(struct efx_nic
*efx
,
239 struct efx_special_buffer
*buffer
)
241 efx_qword_t buf_desc
;
246 EFX_BUG_ON_PARANOID(!buffer
->addr
);
248 /* Write buffer descriptors to NIC */
249 for (i
= 0; i
< buffer
->entries
; i
++) {
250 index
= buffer
->index
+ i
;
251 dma_addr
= buffer
->dma_addr
+ (i
* 4096);
252 EFX_LOG(efx
, "mapping special buffer %d at %llx\n",
253 index
, (unsigned long long)dma_addr
);
254 EFX_POPULATE_QWORD_4(buf_desc
,
255 IP_DAT_BUF_SIZE
, IP_DAT_BUF_SIZE_4K
,
257 BUF_ADR_FBUF
, (dma_addr
>> 12),
258 BUF_OWNER_ID_FBUF
, 0);
259 falcon_write_sram(efx
, &buf_desc
, index
);
265 /* Unmaps a buffer from Falcon and clears the buffer table entries */
267 falcon_fini_special_buffer(struct efx_nic
*efx
,
268 struct efx_special_buffer
*buffer
)
270 efx_oword_t buf_tbl_upd
;
271 unsigned int start
= buffer
->index
;
272 unsigned int end
= (buffer
->index
+ buffer
->entries
- 1);
274 if (!buffer
->entries
)
277 EFX_LOG(efx
, "unmapping special buffers %d-%d\n",
278 buffer
->index
, buffer
->index
+ buffer
->entries
- 1);
280 EFX_POPULATE_OWORD_4(buf_tbl_upd
,
284 BUF_CLR_START_ID
, start
);
285 falcon_write(efx
, &buf_tbl_upd
, BUF_TBL_UPD_REG_KER
);
289 * Allocate a new Falcon special buffer
291 * This allocates memory for a new buffer, clears it and allocates a
292 * new buffer ID range. It does not write into Falcon's buffer table.
294 * This call will allocate 4KB buffers, since Falcon can't use 8KB
295 * buffers for event queues and descriptor rings.
297 static int falcon_alloc_special_buffer(struct efx_nic
*efx
,
298 struct efx_special_buffer
*buffer
,
301 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
303 len
= ALIGN(len
, FALCON_BUF_SIZE
);
305 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
310 buffer
->entries
= len
/ FALCON_BUF_SIZE
;
311 BUG_ON(buffer
->dma_addr
& (FALCON_BUF_SIZE
- 1));
313 /* All zeros is a potentially valid event so memset to 0xff */
314 memset(buffer
->addr
, 0xff, len
);
316 /* Select new buffer ID */
317 buffer
->index
= nic_data
->next_buffer_table
;
318 nic_data
->next_buffer_table
+= buffer
->entries
;
320 EFX_LOG(efx
, "allocating special buffers %d-%d at %llx+%x "
321 "(virt %p phys %lx)\n", buffer
->index
,
322 buffer
->index
+ buffer
->entries
- 1,
323 (unsigned long long)buffer
->dma_addr
, len
,
324 buffer
->addr
, virt_to_phys(buffer
->addr
));
329 static void falcon_free_special_buffer(struct efx_nic
*efx
,
330 struct efx_special_buffer
*buffer
)
335 EFX_LOG(efx
, "deallocating special buffers %d-%d at %llx+%x "
336 "(virt %p phys %lx)\n", buffer
->index
,
337 buffer
->index
+ buffer
->entries
- 1,
338 (unsigned long long)buffer
->dma_addr
, buffer
->len
,
339 buffer
->addr
, virt_to_phys(buffer
->addr
));
341 pci_free_consistent(efx
->pci_dev
, buffer
->len
, buffer
->addr
,
347 /**************************************************************************
349 * Falcon generic buffer handling
350 * These buffers are used for interrupt status and MAC stats
352 **************************************************************************/
354 static int falcon_alloc_buffer(struct efx_nic
*efx
,
355 struct efx_buffer
*buffer
, unsigned int len
)
357 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
362 memset(buffer
->addr
, 0, len
);
366 static void falcon_free_buffer(struct efx_nic
*efx
, struct efx_buffer
*buffer
)
369 pci_free_consistent(efx
->pci_dev
, buffer
->len
,
370 buffer
->addr
, buffer
->dma_addr
);
375 /**************************************************************************
379 **************************************************************************/
381 /* Returns a pointer to the specified transmit descriptor in the TX
382 * descriptor queue belonging to the specified channel.
384 static inline efx_qword_t
*falcon_tx_desc(struct efx_tx_queue
*tx_queue
,
387 return (((efx_qword_t
*) (tx_queue
->txd
.addr
)) + index
);
390 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
391 static inline void falcon_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
396 write_ptr
= tx_queue
->write_count
& FALCON_TXD_RING_MASK
;
397 EFX_POPULATE_DWORD_1(reg
, TX_DESC_WPTR_DWORD
, write_ptr
);
398 falcon_writel_page(tx_queue
->efx
, ®
,
399 TX_DESC_UPD_REG_KER_DWORD
, tx_queue
->queue
);
403 /* For each entry inserted into the software descriptor ring, create a
404 * descriptor in the hardware TX descriptor ring (in host memory), and
407 void falcon_push_buffers(struct efx_tx_queue
*tx_queue
)
410 struct efx_tx_buffer
*buffer
;
414 BUG_ON(tx_queue
->write_count
== tx_queue
->insert_count
);
417 write_ptr
= tx_queue
->write_count
& FALCON_TXD_RING_MASK
;
418 buffer
= &tx_queue
->buffer
[write_ptr
];
419 txd
= falcon_tx_desc(tx_queue
, write_ptr
);
420 ++tx_queue
->write_count
;
422 /* Create TX descriptor ring entry */
423 EFX_POPULATE_QWORD_5(*txd
,
425 TX_KER_CONT
, buffer
->continuation
,
426 TX_KER_BYTE_CNT
, buffer
->len
,
427 TX_KER_BUF_REGION
, 0,
428 TX_KER_BUF_ADR
, buffer
->dma_addr
);
429 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
431 wmb(); /* Ensure descriptors are written before they are fetched */
432 falcon_notify_tx_desc(tx_queue
);
435 /* Allocate hardware resources for a TX queue */
436 int falcon_probe_tx(struct efx_tx_queue
*tx_queue
)
438 struct efx_nic
*efx
= tx_queue
->efx
;
439 return falcon_alloc_special_buffer(efx
, &tx_queue
->txd
,
440 FALCON_TXD_RING_SIZE
*
441 sizeof(efx_qword_t
));
444 int falcon_init_tx(struct efx_tx_queue
*tx_queue
)
446 efx_oword_t tx_desc_ptr
;
447 struct efx_nic
*efx
= tx_queue
->efx
;
450 /* Pin TX descriptor ring */
451 rc
= falcon_init_special_buffer(efx
, &tx_queue
->txd
);
455 /* Push TX descriptor ring to card */
456 EFX_POPULATE_OWORD_10(tx_desc_ptr
,
460 TX_DESCQ_BUF_BASE_ID
, tx_queue
->txd
.index
,
461 TX_DESCQ_EVQ_ID
, tx_queue
->channel
->evqnum
,
462 TX_DESCQ_OWNER_ID
, 0,
463 TX_DESCQ_LABEL
, tx_queue
->queue
,
464 TX_DESCQ_SIZE
, FALCON_TXD_RING_ORDER
,
466 TX_NON_IP_DROP_DIS_B0
, 1);
468 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
469 int csum
= !(efx
->net_dev
->features
& NETIF_F_IP_CSUM
);
470 EFX_SET_OWORD_FIELD(tx_desc_ptr
, TX_IP_CHKSM_DIS_B0
, csum
);
471 EFX_SET_OWORD_FIELD(tx_desc_ptr
, TX_TCP_CHKSM_DIS_B0
, csum
);
474 falcon_write_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
477 if (falcon_rev(efx
) < FALCON_REV_B0
) {
480 BUG_ON(tx_queue
->queue
>= 128); /* HW limit */
482 falcon_read(efx
, ®
, TX_CHKSM_CFG_REG_KER_A1
);
483 if (efx
->net_dev
->features
& NETIF_F_IP_CSUM
)
484 clear_bit_le(tx_queue
->queue
, (void *)®
);
486 set_bit_le(tx_queue
->queue
, (void *)®
);
487 falcon_write(efx
, ®
, TX_CHKSM_CFG_REG_KER_A1
);
493 static int falcon_flush_tx_queue(struct efx_tx_queue
*tx_queue
)
495 struct efx_nic
*efx
= tx_queue
->efx
;
496 struct efx_channel
*channel
= &efx
->channel
[0];
497 efx_oword_t tx_flush_descq
;
498 unsigned int read_ptr
, i
;
500 /* Post a flush command */
501 EFX_POPULATE_OWORD_2(tx_flush_descq
,
502 TX_FLUSH_DESCQ_CMD
, 1,
503 TX_FLUSH_DESCQ
, tx_queue
->queue
);
504 falcon_write(efx
, &tx_flush_descq
, TX_FLUSH_DESCQ_REG_KER
);
505 msleep(FALCON_FLUSH_TIMEOUT
);
507 if (EFX_WORKAROUND_7803(efx
))
510 /* Look for a flush completed event */
511 read_ptr
= channel
->eventq_read_ptr
;
512 for (i
= 0; i
< FALCON_EVQ_SIZE
; ++i
) {
513 efx_qword_t
*event
= falcon_event(channel
, read_ptr
);
514 int ev_code
, ev_sub_code
, ev_queue
;
515 if (!falcon_event_present(event
))
518 ev_code
= EFX_QWORD_FIELD(*event
, EV_CODE
);
519 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
520 ev_queue
= EFX_QWORD_FIELD(*event
, DRIVER_EV_TX_DESCQ_ID
);
521 if ((ev_sub_code
== TX_DESCQ_FLS_DONE_EV_DECODE
) &&
522 (ev_queue
== tx_queue
->queue
)) {
523 EFX_LOG(efx
, "tx queue %d flush command succesful\n",
528 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
531 if (EFX_WORKAROUND_11557(efx
)) {
535 falcon_read_table(efx
, ®
, efx
->type
->txd_ptr_tbl_base
,
537 enabled
= EFX_OWORD_FIELD(reg
, TX_DESCQ_EN
);
539 EFX_LOG(efx
, "tx queue %d disabled without a "
540 "flush event seen\n", tx_queue
->queue
);
545 EFX_ERR(efx
, "tx queue %d flush command timed out\n", tx_queue
->queue
);
549 void falcon_fini_tx(struct efx_tx_queue
*tx_queue
)
551 struct efx_nic
*efx
= tx_queue
->efx
;
552 efx_oword_t tx_desc_ptr
;
554 /* Stop the hardware using the queue */
555 if (falcon_flush_tx_queue(tx_queue
))
556 EFX_ERR(efx
, "failed to flush tx queue %d\n", tx_queue
->queue
);
558 /* Remove TX descriptor ring from card */
559 EFX_ZERO_OWORD(tx_desc_ptr
);
560 falcon_write_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
563 /* Unpin TX descriptor ring */
564 falcon_fini_special_buffer(efx
, &tx_queue
->txd
);
567 /* Free buffers backing TX queue */
568 void falcon_remove_tx(struct efx_tx_queue
*tx_queue
)
570 falcon_free_special_buffer(tx_queue
->efx
, &tx_queue
->txd
);
573 /**************************************************************************
577 **************************************************************************/
579 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
580 static inline efx_qword_t
*falcon_rx_desc(struct efx_rx_queue
*rx_queue
,
583 return (((efx_qword_t
*) (rx_queue
->rxd
.addr
)) + index
);
586 /* This creates an entry in the RX descriptor queue */
587 static inline void falcon_build_rx_desc(struct efx_rx_queue
*rx_queue
,
590 struct efx_rx_buffer
*rx_buf
;
593 rxd
= falcon_rx_desc(rx_queue
, index
);
594 rx_buf
= efx_rx_buffer(rx_queue
, index
);
595 EFX_POPULATE_QWORD_3(*rxd
,
598 rx_queue
->efx
->type
->rx_buffer_padding
,
599 RX_KER_BUF_REGION
, 0,
600 RX_KER_BUF_ADR
, rx_buf
->dma_addr
);
603 /* This writes to the RX_DESC_WPTR register for the specified receive
606 void falcon_notify_rx_desc(struct efx_rx_queue
*rx_queue
)
611 while (rx_queue
->notified_count
!= rx_queue
->added_count
) {
612 falcon_build_rx_desc(rx_queue
,
613 rx_queue
->notified_count
&
614 FALCON_RXD_RING_MASK
);
615 ++rx_queue
->notified_count
;
619 write_ptr
= rx_queue
->added_count
& FALCON_RXD_RING_MASK
;
620 EFX_POPULATE_DWORD_1(reg
, RX_DESC_WPTR_DWORD
, write_ptr
);
621 falcon_writel_page(rx_queue
->efx
, ®
,
622 RX_DESC_UPD_REG_KER_DWORD
, rx_queue
->queue
);
625 int falcon_probe_rx(struct efx_rx_queue
*rx_queue
)
627 struct efx_nic
*efx
= rx_queue
->efx
;
628 return falcon_alloc_special_buffer(efx
, &rx_queue
->rxd
,
629 FALCON_RXD_RING_SIZE
*
630 sizeof(efx_qword_t
));
633 int falcon_init_rx(struct efx_rx_queue
*rx_queue
)
635 efx_oword_t rx_desc_ptr
;
636 struct efx_nic
*efx
= rx_queue
->efx
;
638 int is_b0
= falcon_rev(efx
) >= FALCON_REV_B0
;
639 int iscsi_digest_en
= is_b0
;
641 EFX_LOG(efx
, "RX queue %d ring in special buffers %d-%d\n",
642 rx_queue
->queue
, rx_queue
->rxd
.index
,
643 rx_queue
->rxd
.index
+ rx_queue
->rxd
.entries
- 1);
645 /* Pin RX descriptor ring */
646 rc
= falcon_init_special_buffer(efx
, &rx_queue
->rxd
);
650 /* Push RX descriptor ring to card */
651 EFX_POPULATE_OWORD_10(rx_desc_ptr
,
652 RX_ISCSI_DDIG_EN
, iscsi_digest_en
,
653 RX_ISCSI_HDIG_EN
, iscsi_digest_en
,
654 RX_DESCQ_BUF_BASE_ID
, rx_queue
->rxd
.index
,
655 RX_DESCQ_EVQ_ID
, rx_queue
->channel
->evqnum
,
656 RX_DESCQ_OWNER_ID
, 0,
657 RX_DESCQ_LABEL
, rx_queue
->queue
,
658 RX_DESCQ_SIZE
, FALCON_RXD_RING_ORDER
,
659 RX_DESCQ_TYPE
, 0 /* kernel queue */ ,
660 /* For >=B0 this is scatter so disable */
661 RX_DESCQ_JUMBO
, !is_b0
,
663 falcon_write_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
668 static int falcon_flush_rx_queue(struct efx_rx_queue
*rx_queue
)
670 struct efx_nic
*efx
= rx_queue
->efx
;
671 struct efx_channel
*channel
= &efx
->channel
[0];
672 unsigned int read_ptr
, i
;
673 efx_oword_t rx_flush_descq
;
675 /* Post a flush command */
676 EFX_POPULATE_OWORD_2(rx_flush_descq
,
677 RX_FLUSH_DESCQ_CMD
, 1,
678 RX_FLUSH_DESCQ
, rx_queue
->queue
);
679 falcon_write(efx
, &rx_flush_descq
, RX_FLUSH_DESCQ_REG_KER
);
680 msleep(FALCON_FLUSH_TIMEOUT
);
682 if (EFX_WORKAROUND_7803(efx
))
685 /* Look for a flush completed event */
686 read_ptr
= channel
->eventq_read_ptr
;
687 for (i
= 0; i
< FALCON_EVQ_SIZE
; ++i
) {
688 efx_qword_t
*event
= falcon_event(channel
, read_ptr
);
689 int ev_code
, ev_sub_code
, ev_queue
, ev_failed
;
690 if (!falcon_event_present(event
))
693 ev_code
= EFX_QWORD_FIELD(*event
, EV_CODE
);
694 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
695 ev_queue
= EFX_QWORD_FIELD(*event
, DRIVER_EV_RX_DESCQ_ID
);
696 ev_failed
= EFX_QWORD_FIELD(*event
, DRIVER_EV_RX_FLUSH_FAIL
);
698 if ((ev_sub_code
== RX_DESCQ_FLS_DONE_EV_DECODE
) &&
699 (ev_queue
== rx_queue
->queue
)) {
701 EFX_INFO(efx
, "rx queue %d flush command "
702 "failed\n", rx_queue
->queue
);
705 EFX_LOG(efx
, "rx queue %d flush command "
706 "succesful\n", rx_queue
->queue
);
711 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
714 if (EFX_WORKAROUND_11557(efx
)) {
718 falcon_read_table(efx
, ®
, efx
->type
->rxd_ptr_tbl_base
,
720 enabled
= EFX_OWORD_FIELD(reg
, RX_DESCQ_EN
);
722 EFX_LOG(efx
, "rx queue %d disabled without a "
723 "flush event seen\n", rx_queue
->queue
);
728 EFX_ERR(efx
, "rx queue %d flush command timed out\n", rx_queue
->queue
);
732 void falcon_fini_rx(struct efx_rx_queue
*rx_queue
)
734 efx_oword_t rx_desc_ptr
;
735 struct efx_nic
*efx
= rx_queue
->efx
;
738 /* Try and flush the rx queue. This may need to be repeated */
739 for (i
= 0; i
< 5; i
++) {
740 rc
= falcon_flush_rx_queue(rx_queue
);
746 EFX_ERR(efx
, "failed to flush rx queue %d\n", rx_queue
->queue
);
748 /* Remove RX descriptor ring from card */
749 EFX_ZERO_OWORD(rx_desc_ptr
);
750 falcon_write_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
753 /* Unpin RX descriptor ring */
754 falcon_fini_special_buffer(efx
, &rx_queue
->rxd
);
757 /* Free buffers backing RX queue */
758 void falcon_remove_rx(struct efx_rx_queue
*rx_queue
)
760 falcon_free_special_buffer(rx_queue
->efx
, &rx_queue
->rxd
);
763 /**************************************************************************
765 * Falcon event queue processing
766 * Event queues are processed by per-channel tasklets.
768 **************************************************************************/
770 /* Update a channel's event queue's read pointer (RPTR) register
772 * This writes the EVQ_RPTR_REG register for the specified channel's
775 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
776 * whereas channel->eventq_read_ptr contains the index of the "next to
779 void falcon_eventq_read_ack(struct efx_channel
*channel
)
782 struct efx_nic
*efx
= channel
->efx
;
784 EFX_POPULATE_DWORD_1(reg
, EVQ_RPTR_DWORD
, channel
->eventq_read_ptr
);
785 falcon_writel_table(efx
, ®
, efx
->type
->evq_rptr_tbl_base
,
789 /* Use HW to insert a SW defined event */
790 void falcon_generate_event(struct efx_channel
*channel
, efx_qword_t
*event
)
792 efx_oword_t drv_ev_reg
;
794 EFX_POPULATE_OWORD_2(drv_ev_reg
,
795 DRV_EV_QID
, channel
->evqnum
,
797 EFX_QWORD_FIELD64(*event
, WHOLE_EVENT
));
798 falcon_write(channel
->efx
, &drv_ev_reg
, DRV_EV_REG_KER
);
801 /* Handle a transmit completion event
803 * Falcon batches TX completion events; the message we receive is of
804 * the form "complete all TX events up to this index".
806 static inline void falcon_handle_tx_event(struct efx_channel
*channel
,
809 unsigned int tx_ev_desc_ptr
;
810 unsigned int tx_ev_q_label
;
811 struct efx_tx_queue
*tx_queue
;
812 struct efx_nic
*efx
= channel
->efx
;
814 if (likely(EFX_QWORD_FIELD(*event
, TX_EV_COMP
))) {
815 /* Transmit completion */
816 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, TX_EV_DESC_PTR
);
817 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, TX_EV_Q_LABEL
);
818 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
819 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
);
820 } else if (EFX_QWORD_FIELD(*event
, TX_EV_WQ_FF_FULL
)) {
821 /* Rewrite the FIFO write pointer */
822 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, TX_EV_Q_LABEL
);
823 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
825 if (efx_dev_registered(efx
))
826 netif_tx_lock(efx
->net_dev
);
827 falcon_notify_tx_desc(tx_queue
);
828 if (efx_dev_registered(efx
))
829 netif_tx_unlock(efx
->net_dev
);
830 } else if (EFX_QWORD_FIELD(*event
, TX_EV_PKT_ERR
) &&
831 EFX_WORKAROUND_10727(efx
)) {
832 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
834 EFX_ERR(efx
, "channel %d unexpected TX event "
835 EFX_QWORD_FMT
"\n", channel
->channel
,
836 EFX_QWORD_VAL(*event
));
840 /* Check received packet's destination MAC address. */
841 static int check_dest_mac(struct efx_rx_queue
*rx_queue
,
842 const efx_qword_t
*event
)
844 struct efx_rx_buffer
*rx_buf
;
845 struct efx_nic
*efx
= rx_queue
->efx
;
849 if (efx
->promiscuous
)
852 rx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, RX_EV_DESC_PTR
);
853 rx_buf
= efx_rx_buffer(rx_queue
, rx_ev_desc_ptr
);
854 eh
= (struct ethhdr
*)rx_buf
->data
;
855 if (memcmp(eh
->h_dest
, efx
->net_dev
->dev_addr
, ETH_ALEN
))
860 /* Detect errors included in the rx_evt_pkt_ok bit. */
861 static void falcon_handle_rx_not_ok(struct efx_rx_queue
*rx_queue
,
862 const efx_qword_t
*event
,
863 unsigned *rx_ev_pkt_ok
,
864 int *discard
, int byte_count
)
866 struct efx_nic
*efx
= rx_queue
->efx
;
867 unsigned rx_ev_buf_owner_id_err
, rx_ev_ip_hdr_chksum_err
;
868 unsigned rx_ev_tcp_udp_chksum_err
, rx_ev_eth_crc_err
;
869 unsigned rx_ev_frm_trunc
, rx_ev_drib_nib
, rx_ev_tobe_disc
;
870 unsigned rx_ev_pkt_type
, rx_ev_other_err
, rx_ev_pause_frm
;
871 unsigned rx_ev_ip_frag_err
, rx_ev_hdr_type
, rx_ev_mcast_pkt
;
874 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, RX_EV_HDR_TYPE
);
875 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, RX_EV_MCAST_PKT
);
876 rx_ev_tobe_disc
= EFX_QWORD_FIELD(*event
, RX_EV_TOBE_DISC
);
877 rx_ev_pkt_type
= EFX_QWORD_FIELD(*event
, RX_EV_PKT_TYPE
);
878 rx_ev_buf_owner_id_err
= EFX_QWORD_FIELD(*event
,
879 RX_EV_BUF_OWNER_ID_ERR
);
880 rx_ev_ip_frag_err
= EFX_QWORD_FIELD(*event
, RX_EV_IF_FRAG_ERR
);
881 rx_ev_ip_hdr_chksum_err
= EFX_QWORD_FIELD(*event
,
882 RX_EV_IP_HDR_CHKSUM_ERR
);
883 rx_ev_tcp_udp_chksum_err
= EFX_QWORD_FIELD(*event
,
884 RX_EV_TCP_UDP_CHKSUM_ERR
);
885 rx_ev_eth_crc_err
= EFX_QWORD_FIELD(*event
, RX_EV_ETH_CRC_ERR
);
886 rx_ev_frm_trunc
= EFX_QWORD_FIELD(*event
, RX_EV_FRM_TRUNC
);
887 rx_ev_drib_nib
= ((falcon_rev(efx
) >= FALCON_REV_B0
) ?
888 0 : EFX_QWORD_FIELD(*event
, RX_EV_DRIB_NIB
));
889 rx_ev_pause_frm
= EFX_QWORD_FIELD(*event
, RX_EV_PAUSE_FRM_ERR
);
891 /* Every error apart from tobe_disc and pause_frm */
892 rx_ev_other_err
= (rx_ev_drib_nib
| rx_ev_tcp_udp_chksum_err
|
893 rx_ev_buf_owner_id_err
| rx_ev_eth_crc_err
|
894 rx_ev_frm_trunc
| rx_ev_ip_hdr_chksum_err
);
896 snap
= (rx_ev_pkt_type
== RX_EV_PKT_TYPE_LLC_DECODE
) ||
897 (rx_ev_pkt_type
== RX_EV_PKT_TYPE_VLAN_LLC_DECODE
);
898 non_ip
= (rx_ev_hdr_type
== RX_EV_HDR_TYPE_NON_IP_DECODE
);
900 /* SFC bug 5475/8970: The Falcon XMAC incorrectly calculates the
901 * length field of an LLC frame, which sets TOBE_DISC. We could set
902 * PASS_LEN_ERR, but we want the MAC to filter out short frames (to
903 * protect the RX block).
905 * bug5475 - LLC/SNAP: Falcon identifies SNAP packets.
906 * bug8970 - LLC/noSNAP: Falcon does not provide an LLC flag.
907 * LLC can't encapsulate IP, so by definition
908 * these packets are NON_IP.
910 * Unicast mismatch will also cause TOBE_DISC, so the driver needs
913 if (EFX_WORKAROUND_5475(efx
) && rx_ev_tobe_disc
&& (snap
|| non_ip
)) {
914 /* If all the other flags are zero then we can state the
915 * entire packet is ok, which will flag to the kernel not
916 * to recalculate checksums.
918 if (!(non_ip
| rx_ev_other_err
| rx_ev_pause_frm
))
923 /* TOBE_DISC is set for unicast mismatch. But given that
924 * we can't trust TOBE_DISC here, we must validate the dest
925 * MAC address ourselves.
927 if (!rx_ev_mcast_pkt
&& !check_dest_mac(rx_queue
, event
))
931 /* Count errors that are not in MAC stats. */
933 ++rx_queue
->channel
->n_rx_frm_trunc
;
934 else if (rx_ev_tobe_disc
)
935 ++rx_queue
->channel
->n_rx_tobe_disc
;
936 else if (rx_ev_ip_hdr_chksum_err
)
937 ++rx_queue
->channel
->n_rx_ip_hdr_chksum_err
;
938 else if (rx_ev_tcp_udp_chksum_err
)
939 ++rx_queue
->channel
->n_rx_tcp_udp_chksum_err
;
940 if (rx_ev_ip_frag_err
)
941 ++rx_queue
->channel
->n_rx_ip_frag_err
;
943 /* The frame must be discarded if any of these are true. */
944 *discard
= (rx_ev_eth_crc_err
| rx_ev_frm_trunc
| rx_ev_drib_nib
|
945 rx_ev_tobe_disc
| rx_ev_pause_frm
);
947 /* TOBE_DISC is expected on unicast mismatches; don't print out an
948 * error message. FRM_TRUNC indicates RXDP dropped the packet due
949 * to a FIFO overflow.
951 #ifdef EFX_ENABLE_DEBUG
952 if (rx_ev_other_err
) {
953 EFX_INFO_RL(efx
, " RX queue %d unexpected RX event "
954 EFX_QWORD_FMT
"%s%s%s%s%s%s%s%s%s\n",
955 rx_queue
->queue
, EFX_QWORD_VAL(*event
),
956 rx_ev_buf_owner_id_err
? " [OWNER_ID_ERR]" : "",
957 rx_ev_ip_hdr_chksum_err
?
958 " [IP_HDR_CHKSUM_ERR]" : "",
959 rx_ev_tcp_udp_chksum_err
?
960 " [TCP_UDP_CHKSUM_ERR]" : "",
961 rx_ev_eth_crc_err
? " [ETH_CRC_ERR]" : "",
962 rx_ev_frm_trunc
? " [FRM_TRUNC]" : "",
963 rx_ev_drib_nib
? " [DRIB_NIB]" : "",
964 rx_ev_tobe_disc
? " [TOBE_DISC]" : "",
965 rx_ev_pause_frm
? " [PAUSE]" : "",
966 snap
? " [SNAP/LLC]" : "");
970 if (unlikely(rx_ev_eth_crc_err
&& EFX_WORKAROUND_10750(efx
) &&
971 efx
->phy_type
== PHY_TYPE_10XPRESS
))
972 tenxpress_crc_err(efx
);
975 /* Handle receive events that are not in-order. */
976 static void falcon_handle_rx_bad_index(struct efx_rx_queue
*rx_queue
,
979 struct efx_nic
*efx
= rx_queue
->efx
;
980 unsigned expected
, dropped
;
982 expected
= rx_queue
->removed_count
& FALCON_RXD_RING_MASK
;
983 dropped
= ((index
+ FALCON_RXD_RING_SIZE
- expected
) &
984 FALCON_RXD_RING_MASK
);
985 EFX_INFO(efx
, "dropped %d events (index=%d expected=%d)\n",
986 dropped
, index
, expected
);
988 efx_schedule_reset(efx
, EFX_WORKAROUND_5676(efx
) ?
989 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
992 /* Handle a packet received event
994 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
995 * wrong destination address
996 * Also "is multicast" and "matches multicast filter" flags can be used to
997 * discard non-matching multicast packets.
999 static inline int falcon_handle_rx_event(struct efx_channel
*channel
,
1000 const efx_qword_t
*event
)
1002 unsigned int rx_ev_q_label
, rx_ev_desc_ptr
, rx_ev_byte_cnt
;
1003 unsigned int rx_ev_pkt_ok
, rx_ev_hdr_type
, rx_ev_mcast_pkt
;
1004 unsigned expected_ptr
;
1005 int discard
= 0, checksummed
;
1006 struct efx_rx_queue
*rx_queue
;
1007 struct efx_nic
*efx
= channel
->efx
;
1009 /* Basic packet information */
1010 rx_ev_byte_cnt
= EFX_QWORD_FIELD(*event
, RX_EV_BYTE_CNT
);
1011 rx_ev_pkt_ok
= EFX_QWORD_FIELD(*event
, RX_EV_PKT_OK
);
1012 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, RX_EV_HDR_TYPE
);
1013 WARN_ON(EFX_QWORD_FIELD(*event
, RX_EV_JUMBO_CONT
));
1014 WARN_ON(EFX_QWORD_FIELD(*event
, RX_EV_SOP
) != 1);
1016 rx_ev_q_label
= EFX_QWORD_FIELD(*event
, RX_EV_Q_LABEL
);
1017 rx_queue
= &efx
->rx_queue
[rx_ev_q_label
];
1019 rx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, RX_EV_DESC_PTR
);
1020 expected_ptr
= rx_queue
->removed_count
& FALCON_RXD_RING_MASK
;
1021 if (unlikely(rx_ev_desc_ptr
!= expected_ptr
)) {
1022 falcon_handle_rx_bad_index(rx_queue
, rx_ev_desc_ptr
);
1023 return rx_ev_q_label
;
1026 if (likely(rx_ev_pkt_ok
)) {
1027 /* If packet is marked as OK and packet type is TCP/IPv4 or
1028 * UDP/IPv4, then we can rely on the hardware checksum.
1030 checksummed
= RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type
);
1032 falcon_handle_rx_not_ok(rx_queue
, event
, &rx_ev_pkt_ok
,
1033 &discard
, rx_ev_byte_cnt
);
1037 /* Detect multicast packets that didn't match the filter */
1038 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, RX_EV_MCAST_PKT
);
1039 if (rx_ev_mcast_pkt
) {
1040 unsigned int rx_ev_mcast_hash_match
=
1041 EFX_QWORD_FIELD(*event
, RX_EV_MCAST_HASH_MATCH
);
1043 if (unlikely(!rx_ev_mcast_hash_match
))
1047 /* Handle received packet */
1048 efx_rx_packet(rx_queue
, rx_ev_desc_ptr
, rx_ev_byte_cnt
,
1049 checksummed
, discard
);
1051 return rx_ev_q_label
;
1054 /* Global events are basically PHY events */
1055 static void falcon_handle_global_event(struct efx_channel
*channel
,
1058 struct efx_nic
*efx
= channel
->efx
;
1059 int is_phy_event
= 0, handled
= 0;
1061 /* Check for interrupt on either port. Some boards have a
1062 * single PHY wired to the interrupt line for port 1. */
1063 if (EFX_QWORD_FIELD(*event
, G_PHY0_INTR
) ||
1064 EFX_QWORD_FIELD(*event
, G_PHY1_INTR
) ||
1065 EFX_QWORD_FIELD(*event
, XG_PHY_INTR
))
1068 if ((falcon_rev(efx
) >= FALCON_REV_B0
) &&
1069 EFX_OWORD_FIELD(*event
, XG_MNT_INTR_B0
))
1073 efx
->phy_op
->clear_interrupt(efx
);
1074 queue_work(efx
->workqueue
, &efx
->reconfigure_work
);
1078 if (EFX_QWORD_FIELD_VER(efx
, *event
, RX_RECOVERY
)) {
1079 EFX_ERR(efx
, "channel %d seen global RX_RESET "
1080 "event. Resetting.\n", channel
->channel
);
1082 atomic_inc(&efx
->rx_reset
);
1083 efx_schedule_reset(efx
, EFX_WORKAROUND_6555(efx
) ?
1084 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
1089 EFX_ERR(efx
, "channel %d unknown global event "
1090 EFX_QWORD_FMT
"\n", channel
->channel
,
1091 EFX_QWORD_VAL(*event
));
1094 static void falcon_handle_driver_event(struct efx_channel
*channel
,
1097 struct efx_nic
*efx
= channel
->efx
;
1098 unsigned int ev_sub_code
;
1099 unsigned int ev_sub_data
;
1101 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
1102 ev_sub_data
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_DATA
);
1104 switch (ev_sub_code
) {
1105 case TX_DESCQ_FLS_DONE_EV_DECODE
:
1106 EFX_TRACE(efx
, "channel %d TXQ %d flushed\n",
1107 channel
->channel
, ev_sub_data
);
1109 case RX_DESCQ_FLS_DONE_EV_DECODE
:
1110 EFX_TRACE(efx
, "channel %d RXQ %d flushed\n",
1111 channel
->channel
, ev_sub_data
);
1113 case EVQ_INIT_DONE_EV_DECODE
:
1114 EFX_LOG(efx
, "channel %d EVQ %d initialised\n",
1115 channel
->channel
, ev_sub_data
);
1117 case SRM_UPD_DONE_EV_DECODE
:
1118 EFX_TRACE(efx
, "channel %d SRAM update done\n",
1121 case WAKE_UP_EV_DECODE
:
1122 EFX_TRACE(efx
, "channel %d RXQ %d wakeup event\n",
1123 channel
->channel
, ev_sub_data
);
1125 case TIMER_EV_DECODE
:
1126 EFX_TRACE(efx
, "channel %d RX queue %d timer expired\n",
1127 channel
->channel
, ev_sub_data
);
1129 case RX_RECOVERY_EV_DECODE
:
1130 EFX_ERR(efx
, "channel %d seen DRIVER RX_RESET event. "
1131 "Resetting.\n", channel
->channel
);
1132 atomic_inc(&efx
->rx_reset
);
1133 efx_schedule_reset(efx
,
1134 EFX_WORKAROUND_6555(efx
) ?
1135 RESET_TYPE_RX_RECOVERY
:
1136 RESET_TYPE_DISABLE
);
1138 case RX_DSC_ERROR_EV_DECODE
:
1139 EFX_ERR(efx
, "RX DMA Q %d reports descriptor fetch error."
1140 " RX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
1141 efx_schedule_reset(efx
, RESET_TYPE_RX_DESC_FETCH
);
1143 case TX_DSC_ERROR_EV_DECODE
:
1144 EFX_ERR(efx
, "TX DMA Q %d reports descriptor fetch error."
1145 " TX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
1146 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
1149 EFX_TRACE(efx
, "channel %d unknown driver event code %d "
1150 "data %04x\n", channel
->channel
, ev_sub_code
,
1156 int falcon_process_eventq(struct efx_channel
*channel
, int *rx_quota
)
1158 unsigned int read_ptr
;
1159 efx_qword_t event
, *p_event
;
1164 read_ptr
= channel
->eventq_read_ptr
;
1167 p_event
= falcon_event(channel
, read_ptr
);
1170 if (!falcon_event_present(&event
))
1174 EFX_TRACE(channel
->efx
, "channel %d event is "EFX_QWORD_FMT
"\n",
1175 channel
->channel
, EFX_QWORD_VAL(event
));
1177 /* Clear this event by marking it all ones */
1178 EFX_SET_QWORD(*p_event
);
1180 ev_code
= EFX_QWORD_FIELD(event
, EV_CODE
);
1183 case RX_IP_EV_DECODE
:
1184 rxq
= falcon_handle_rx_event(channel
, &event
);
1185 rxdmaqs
|= (1 << rxq
);
1188 case TX_IP_EV_DECODE
:
1189 falcon_handle_tx_event(channel
, &event
);
1191 case DRV_GEN_EV_DECODE
:
1192 channel
->eventq_magic
1193 = EFX_QWORD_FIELD(event
, EVQ_MAGIC
);
1194 EFX_LOG(channel
->efx
, "channel %d received generated "
1195 "event "EFX_QWORD_FMT
"\n", channel
->channel
,
1196 EFX_QWORD_VAL(event
));
1198 case GLOBAL_EV_DECODE
:
1199 falcon_handle_global_event(channel
, &event
);
1201 case DRIVER_EV_DECODE
:
1202 falcon_handle_driver_event(channel
, &event
);
1205 EFX_ERR(channel
->efx
, "channel %d unknown event type %d"
1206 " (data " EFX_QWORD_FMT
")\n", channel
->channel
,
1207 ev_code
, EFX_QWORD_VAL(event
));
1210 /* Increment read pointer */
1211 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
1213 } while (*rx_quota
);
1215 channel
->eventq_read_ptr
= read_ptr
;
1219 void falcon_set_int_moderation(struct efx_channel
*channel
)
1221 efx_dword_t timer_cmd
;
1222 struct efx_nic
*efx
= channel
->efx
;
1224 /* Set timer register */
1225 if (channel
->irq_moderation
) {
1226 /* Round to resolution supported by hardware. The value we
1227 * program is based at 0. So actual interrupt moderation
1228 * achieved is ((x + 1) * res).
1230 unsigned int res
= 5;
1231 channel
->irq_moderation
-= (channel
->irq_moderation
% res
);
1232 if (channel
->irq_moderation
< res
)
1233 channel
->irq_moderation
= res
;
1234 EFX_POPULATE_DWORD_2(timer_cmd
,
1235 TIMER_MODE
, TIMER_MODE_INT_HLDOFF
,
1237 (channel
->irq_moderation
/ res
) - 1);
1239 EFX_POPULATE_DWORD_2(timer_cmd
,
1240 TIMER_MODE
, TIMER_MODE_DIS
,
1243 falcon_writel_page_locked(efx
, &timer_cmd
, TIMER_CMD_REG_KER
,
1248 /* Allocate buffer table entries for event queue */
1249 int falcon_probe_eventq(struct efx_channel
*channel
)
1251 struct efx_nic
*efx
= channel
->efx
;
1252 unsigned int evq_size
;
1254 evq_size
= FALCON_EVQ_SIZE
* sizeof(efx_qword_t
);
1255 return falcon_alloc_special_buffer(efx
, &channel
->eventq
, evq_size
);
1258 int falcon_init_eventq(struct efx_channel
*channel
)
1260 efx_oword_t evq_ptr
;
1261 struct efx_nic
*efx
= channel
->efx
;
1264 EFX_LOG(efx
, "channel %d event queue in special buffers %d-%d\n",
1265 channel
->channel
, channel
->eventq
.index
,
1266 channel
->eventq
.index
+ channel
->eventq
.entries
- 1);
1268 /* Pin event queue buffer */
1269 rc
= falcon_init_special_buffer(efx
, &channel
->eventq
);
1273 /* Fill event queue with all ones (i.e. empty events) */
1274 memset(channel
->eventq
.addr
, 0xff, channel
->eventq
.len
);
1276 /* Push event queue to card */
1277 EFX_POPULATE_OWORD_3(evq_ptr
,
1279 EVQ_SIZE
, FALCON_EVQ_ORDER
,
1280 EVQ_BUF_BASE_ID
, channel
->eventq
.index
);
1281 falcon_write_table(efx
, &evq_ptr
, efx
->type
->evq_ptr_tbl_base
,
1284 falcon_set_int_moderation(channel
);
1289 void falcon_fini_eventq(struct efx_channel
*channel
)
1291 efx_oword_t eventq_ptr
;
1292 struct efx_nic
*efx
= channel
->efx
;
1294 /* Remove event queue from card */
1295 EFX_ZERO_OWORD(eventq_ptr
);
1296 falcon_write_table(efx
, &eventq_ptr
, efx
->type
->evq_ptr_tbl_base
,
1299 /* Unpin event queue */
1300 falcon_fini_special_buffer(efx
, &channel
->eventq
);
1303 /* Free buffers backing event queue */
1304 void falcon_remove_eventq(struct efx_channel
*channel
)
1306 falcon_free_special_buffer(channel
->efx
, &channel
->eventq
);
1310 /* Generates a test event on the event queue. A subsequent call to
1311 * process_eventq() should pick up the event and place the value of
1312 * "magic" into channel->eventq_magic;
1314 void falcon_generate_test_event(struct efx_channel
*channel
, unsigned int magic
)
1316 efx_qword_t test_event
;
1318 EFX_POPULATE_QWORD_2(test_event
,
1319 EV_CODE
, DRV_GEN_EV_DECODE
,
1321 falcon_generate_event(channel
, &test_event
);
1325 /**************************************************************************
1327 * Falcon hardware interrupts
1328 * The hardware interrupt handler does very little work; all the event
1329 * queue processing is carried out by per-channel tasklets.
1331 **************************************************************************/
1333 /* Enable/disable/generate Falcon interrupts */
1334 static inline void falcon_interrupts(struct efx_nic
*efx
, int enabled
,
1337 efx_oword_t int_en_reg_ker
;
1339 EFX_POPULATE_OWORD_2(int_en_reg_ker
,
1341 DRV_INT_EN_KER
, enabled
);
1342 falcon_write(efx
, &int_en_reg_ker
, INT_EN_REG_KER
);
1345 void falcon_enable_interrupts(struct efx_nic
*efx
)
1347 efx_oword_t int_adr_reg_ker
;
1348 struct efx_channel
*channel
;
1350 EFX_ZERO_OWORD(*((efx_oword_t
*) efx
->irq_status
.addr
));
1351 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1353 /* Program address */
1354 EFX_POPULATE_OWORD_2(int_adr_reg_ker
,
1355 NORM_INT_VEC_DIS_KER
, EFX_INT_MODE_USE_MSI(efx
),
1356 INT_ADR_KER
, efx
->irq_status
.dma_addr
);
1357 falcon_write(efx
, &int_adr_reg_ker
, INT_ADR_REG_KER
);
1359 /* Enable interrupts */
1360 falcon_interrupts(efx
, 1, 0);
1362 /* Force processing of all the channels to get the EVQ RPTRs up to
1364 efx_for_each_channel_with_interrupt(channel
, efx
)
1365 efx_schedule_channel(channel
);
1368 void falcon_disable_interrupts(struct efx_nic
*efx
)
1370 /* Disable interrupts */
1371 falcon_interrupts(efx
, 0, 0);
1374 /* Generate a Falcon test interrupt
1375 * Interrupt must already have been enabled, otherwise nasty things
1378 void falcon_generate_interrupt(struct efx_nic
*efx
)
1380 falcon_interrupts(efx
, 1, 1);
1383 /* Acknowledge a legacy interrupt from Falcon
1385 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1387 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1388 * BIU. Interrupt acknowledge is read sensitive so must write instead
1389 * (then read to ensure the BIU collector is flushed)
1391 * NB most hardware supports MSI interrupts
1393 static inline void falcon_irq_ack_a1(struct efx_nic
*efx
)
1397 EFX_POPULATE_DWORD_1(reg
, INT_ACK_DUMMY_DATA
, 0xb7eb7e);
1398 falcon_writel(efx
, ®
, INT_ACK_REG_KER_A1
);
1399 falcon_readl(efx
, ®
, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1
);
1402 /* Process a fatal interrupt
1403 * Disable bus mastering ASAP and schedule a reset
1405 static irqreturn_t
falcon_fatal_interrupt(struct efx_nic
*efx
)
1407 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1408 efx_oword_t
*int_ker
= (efx_oword_t
*) efx
->irq_status
.addr
;
1409 efx_oword_t fatal_intr
;
1410 int error
, mem_perr
;
1411 static int n_int_errors
;
1413 falcon_read(efx
, &fatal_intr
, FATAL_INTR_REG_KER
);
1414 error
= EFX_OWORD_FIELD(fatal_intr
, INT_KER_ERROR
);
1416 EFX_ERR(efx
, "SYSTEM ERROR " EFX_OWORD_FMT
" status "
1417 EFX_OWORD_FMT
": %s\n", EFX_OWORD_VAL(*int_ker
),
1418 EFX_OWORD_VAL(fatal_intr
),
1419 error
? "disabling bus mastering" : "no recognised error");
1423 /* If this is a memory parity error dump which blocks are offending */
1424 mem_perr
= EFX_OWORD_FIELD(fatal_intr
, MEM_PERR_INT_KER
);
1427 falcon_read(efx
, ®
, MEM_STAT_REG_KER
);
1428 EFX_ERR(efx
, "SYSTEM ERROR: memory parity error "
1429 EFX_OWORD_FMT
"\n", EFX_OWORD_VAL(reg
));
1432 /* Disable DMA bus mastering on both devices */
1433 pci_disable_device(efx
->pci_dev
);
1434 if (FALCON_IS_DUAL_FUNC(efx
))
1435 pci_disable_device(nic_data
->pci_dev2
);
1437 if (++n_int_errors
< FALCON_MAX_INT_ERRORS
) {
1438 EFX_ERR(efx
, "SYSTEM ERROR - reset scheduled\n");
1439 efx_schedule_reset(efx
, RESET_TYPE_INT_ERROR
);
1441 EFX_ERR(efx
, "SYSTEM ERROR - max number of errors seen."
1442 "NIC will be disabled\n");
1443 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
1449 /* Handle a legacy interrupt from Falcon
1450 * Acknowledges the interrupt and schedule event queue processing.
1452 static irqreturn_t
falcon_legacy_interrupt_b0(int irq
, void *dev_id
)
1454 struct efx_nic
*efx
= (struct efx_nic
*)dev_id
;
1455 efx_oword_t
*int_ker
= (efx_oword_t
*) efx
->irq_status
.addr
;
1456 struct efx_channel
*channel
;
1461 /* Read the ISR which also ACKs the interrupts */
1462 falcon_readl(efx
, ®
, INT_ISR0_B0
);
1463 queues
= EFX_EXTRACT_DWORD(reg
, 0, 31);
1465 /* Check to see if we have a serious error condition */
1466 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1467 if (unlikely(syserr
))
1468 return falcon_fatal_interrupt(efx
);
1473 efx
->last_irq_cpu
= raw_smp_processor_id();
1474 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
1475 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
1477 /* Schedule processing of any interrupting queues */
1478 channel
= &efx
->channel
[0];
1481 efx_schedule_channel(channel
);
1490 static irqreturn_t
falcon_legacy_interrupt_a1(int irq
, void *dev_id
)
1492 struct efx_nic
*efx
= (struct efx_nic
*)dev_id
;
1493 efx_oword_t
*int_ker
= (efx_oword_t
*) efx
->irq_status
.addr
;
1494 struct efx_channel
*channel
;
1498 /* Check to see if this is our interrupt. If it isn't, we
1499 * exit without having touched the hardware.
1501 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker
))) {
1502 EFX_TRACE(efx
, "IRQ %d on CPU %d not for me\n", irq
,
1503 raw_smp_processor_id());
1506 efx
->last_irq_cpu
= raw_smp_processor_id();
1507 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
1508 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
1510 /* Check to see if we have a serious error condition */
1511 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1512 if (unlikely(syserr
))
1513 return falcon_fatal_interrupt(efx
);
1515 /* Determine interrupting queues, clear interrupt status
1516 * register and acknowledge the device interrupt.
1518 BUILD_BUG_ON(INT_EVQS_WIDTH
> EFX_MAX_CHANNELS
);
1519 queues
= EFX_OWORD_FIELD(*int_ker
, INT_EVQS
);
1520 EFX_ZERO_OWORD(*int_ker
);
1521 wmb(); /* Ensure the vector is cleared before interrupt ack */
1522 falcon_irq_ack_a1(efx
);
1524 /* Schedule processing of any interrupting queues */
1525 channel
= &efx
->channel
[0];
1528 efx_schedule_channel(channel
);
1536 /* Handle an MSI interrupt from Falcon
1538 * Handle an MSI hardware interrupt. This routine schedules event
1539 * queue processing. No interrupt acknowledgement cycle is necessary.
1540 * Also, we never need to check that the interrupt is for us, since
1541 * MSI interrupts cannot be shared.
1543 static irqreturn_t
falcon_msi_interrupt(int irq
, void *dev_id
)
1545 struct efx_channel
*channel
= (struct efx_channel
*)dev_id
;
1546 struct efx_nic
*efx
= channel
->efx
;
1547 efx_oword_t
*int_ker
= (efx_oword_t
*) efx
->irq_status
.addr
;
1550 efx
->last_irq_cpu
= raw_smp_processor_id();
1551 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
1552 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
1554 /* Check to see if we have a serious error condition */
1555 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1556 if (unlikely(syserr
))
1557 return falcon_fatal_interrupt(efx
);
1559 /* Schedule processing of the channel */
1560 efx_schedule_channel(channel
);
1566 /* Setup RSS indirection table.
1567 * This maps from the hash value of the packet to RXQ
1569 static void falcon_setup_rss_indir_table(struct efx_nic
*efx
)
1572 unsigned long offset
;
1575 if (falcon_rev(efx
) < FALCON_REV_B0
)
1578 for (offset
= RX_RSS_INDIR_TBL_B0
;
1579 offset
< RX_RSS_INDIR_TBL_B0
+ 0x800;
1581 EFX_POPULATE_DWORD_1(dword
, RX_RSS_INDIR_ENT_B0
,
1582 i
% efx
->rss_queues
);
1583 falcon_writel(efx
, &dword
, offset
);
1588 /* Hook interrupt handler(s)
1589 * Try MSI and then legacy interrupts.
1591 int falcon_init_interrupt(struct efx_nic
*efx
)
1593 struct efx_channel
*channel
;
1596 if (!EFX_INT_MODE_USE_MSI(efx
)) {
1597 irq_handler_t handler
;
1598 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1599 handler
= falcon_legacy_interrupt_b0
;
1601 handler
= falcon_legacy_interrupt_a1
;
1603 rc
= request_irq(efx
->legacy_irq
, handler
, IRQF_SHARED
,
1606 EFX_ERR(efx
, "failed to hook legacy IRQ %d\n",
1613 /* Hook MSI or MSI-X interrupt */
1614 efx_for_each_channel_with_interrupt(channel
, efx
) {
1615 rc
= request_irq(channel
->irq
, falcon_msi_interrupt
,
1616 IRQF_PROBE_SHARED
, /* Not shared */
1617 efx
->name
, channel
);
1619 EFX_ERR(efx
, "failed to hook IRQ %d\n", channel
->irq
);
1627 efx_for_each_channel_with_interrupt(channel
, efx
)
1628 free_irq(channel
->irq
, channel
);
1633 void falcon_fini_interrupt(struct efx_nic
*efx
)
1635 struct efx_channel
*channel
;
1638 /* Disable MSI/MSI-X interrupts */
1639 efx_for_each_channel_with_interrupt(channel
, efx
) {
1641 free_irq(channel
->irq
, channel
);
1644 /* ACK legacy interrupt */
1645 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1646 falcon_read(efx
, ®
, INT_ISR0_B0
);
1648 falcon_irq_ack_a1(efx
);
1650 /* Disable legacy interrupt */
1651 if (efx
->legacy_irq
)
1652 free_irq(efx
->legacy_irq
, efx
);
1655 /**************************************************************************
1659 **************************************************************************
1662 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1664 /* Wait for SPI command completion */
1665 static int falcon_spi_wait(struct efx_nic
*efx
)
1668 int cmd_en
, timer_active
;
1673 falcon_read(efx
, ®
, EE_SPI_HCMD_REG_KER
);
1674 cmd_en
= EFX_OWORD_FIELD(reg
, EE_SPI_HCMD_CMD_EN
);
1675 timer_active
= EFX_OWORD_FIELD(reg
, EE_WR_TIMER_ACTIVE
);
1676 if (!cmd_en
&& !timer_active
)
1679 } while (++count
< 10000); /* wait upto 100msec */
1680 EFX_ERR(efx
, "timed out waiting for SPI\n");
1685 falcon_spi_read(struct efx_nic
*efx
, int device_id
, unsigned int command
,
1686 unsigned int address
, unsigned int addr_len
,
1687 void *data
, unsigned int len
)
1692 BUG_ON(len
> FALCON_SPI_MAX_LEN
);
1694 /* Check SPI not currently being accessed */
1695 rc
= falcon_spi_wait(efx
);
1699 /* Program address register */
1700 EFX_POPULATE_OWORD_1(reg
, EE_SPI_HADR_ADR
, address
);
1701 falcon_write(efx
, ®
, EE_SPI_HADR_REG_KER
);
1703 /* Issue read command */
1704 EFX_POPULATE_OWORD_7(reg
,
1705 EE_SPI_HCMD_CMD_EN
, 1,
1706 EE_SPI_HCMD_SF_SEL
, device_id
,
1707 EE_SPI_HCMD_DABCNT
, len
,
1708 EE_SPI_HCMD_READ
, EE_SPI_READ
,
1709 EE_SPI_HCMD_DUBCNT
, 0,
1710 EE_SPI_HCMD_ADBCNT
, addr_len
,
1711 EE_SPI_HCMD_ENC
, command
);
1712 falcon_write(efx
, ®
, EE_SPI_HCMD_REG_KER
);
1714 /* Wait for read to complete */
1715 rc
= falcon_spi_wait(efx
);
1720 falcon_read(efx
, ®
, EE_SPI_HDATA_REG_KER
);
1721 memcpy(data
, ®
, len
);
1725 /**************************************************************************
1729 **************************************************************************
1731 void falcon_drain_tx_fifo(struct efx_nic
*efx
)
1736 if ((falcon_rev(efx
) < FALCON_REV_B0
) ||
1737 (efx
->loopback_mode
!= LOOPBACK_NONE
))
1740 falcon_read(efx
, &temp
, MAC0_CTRL_REG_KER
);
1741 /* There is no point in draining more than once */
1742 if (EFX_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
))
1745 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1746 * the drain sequence with the statistics fetch */
1747 spin_lock(&efx
->stats_lock
);
1749 EFX_SET_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
, 1);
1750 falcon_write(efx
, &temp
, MAC0_CTRL_REG_KER
);
1752 /* Reset the MAC and EM block. */
1753 falcon_read(efx
, &temp
, GLB_CTL_REG_KER
);
1754 EFX_SET_OWORD_FIELD(temp
, RST_XGTX
, 1);
1755 EFX_SET_OWORD_FIELD(temp
, RST_XGRX
, 1);
1756 EFX_SET_OWORD_FIELD(temp
, RST_EM
, 1);
1757 falcon_write(efx
, &temp
, GLB_CTL_REG_KER
);
1761 falcon_read(efx
, &temp
, GLB_CTL_REG_KER
);
1762 if (!EFX_OWORD_FIELD(temp
, RST_XGTX
) &&
1763 !EFX_OWORD_FIELD(temp
, RST_XGRX
) &&
1764 !EFX_OWORD_FIELD(temp
, RST_EM
)) {
1765 EFX_LOG(efx
, "Completed MAC reset after %d loops\n",
1770 EFX_ERR(efx
, "MAC reset failed\n");
1777 spin_unlock(&efx
->stats_lock
);
1779 /* If we've reset the EM block and the link is up, then
1780 * we'll have to kick the XAUI link so the PHY can recover */
1781 if (efx
->link_up
&& EFX_WORKAROUND_5147(efx
))
1782 falcon_reset_xaui(efx
);
1785 void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
)
1789 if (falcon_rev(efx
) < FALCON_REV_B0
)
1792 /* Isolate the MAC -> RX */
1793 falcon_read(efx
, &temp
, RX_CFG_REG_KER
);
1794 EFX_SET_OWORD_FIELD(temp
, RX_INGR_EN_B0
, 0);
1795 falcon_write(efx
, &temp
, RX_CFG_REG_KER
);
1798 falcon_drain_tx_fifo(efx
);
1801 void falcon_reconfigure_mac_wrapper(struct efx_nic
*efx
)
1807 if (efx
->link_options
& GM_LPA_10000
)
1809 else if (efx
->link_options
& GM_LPA_1000
)
1811 else if (efx
->link_options
& GM_LPA_100
)
1815 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1816 * as advertised. Disable to ensure packets are not
1817 * indefinitely held and TX queue can be flushed at any point
1818 * while the link is down. */
1819 EFX_POPULATE_OWORD_5(reg
,
1820 MAC_XOFF_VAL
, 0xffff /* max pause time */,
1822 MAC_UC_PROM
, efx
->promiscuous
,
1823 MAC_LINK_STATUS
, 1, /* always set */
1824 MAC_SPEED
, link_speed
);
1825 /* On B0, MAC backpressure can be disabled and packets get
1827 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
1828 EFX_SET_OWORD_FIELD(reg
, TXFIFO_DRAIN_EN_B0
,
1832 falcon_write(efx
, ®
, MAC0_CTRL_REG_KER
);
1834 /* Restore the multicast hash registers. */
1835 falcon_set_multicast_hash(efx
);
1837 /* Transmission of pause frames when RX crosses the threshold is
1838 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1839 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1840 tx_fc
= (efx
->flow_control
& EFX_FC_TX
) ? 1 : 0;
1841 falcon_read(efx
, ®
, RX_CFG_REG_KER
);
1842 EFX_SET_OWORD_FIELD_VER(efx
, reg
, RX_XOFF_MAC_EN
, tx_fc
);
1844 /* Unisolate the MAC -> RX */
1845 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1846 EFX_SET_OWORD_FIELD(reg
, RX_INGR_EN_B0
, 1);
1847 falcon_write(efx
, ®
, RX_CFG_REG_KER
);
1850 int falcon_dma_stats(struct efx_nic
*efx
, unsigned int done_offset
)
1856 if (disable_dma_stats
)
1859 /* Statistics fetch will fail if the MAC is in TX drain */
1860 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
1862 falcon_read(efx
, &temp
, MAC0_CTRL_REG_KER
);
1863 if (EFX_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
))
1867 dma_done
= (efx
->stats_buffer
.addr
+ done_offset
);
1868 *dma_done
= FALCON_STATS_NOT_DONE
;
1869 wmb(); /* ensure done flag is clear */
1871 /* Initiate DMA transfer of stats */
1872 EFX_POPULATE_OWORD_2(reg
,
1873 MAC_STAT_DMA_CMD
, 1,
1875 efx
->stats_buffer
.dma_addr
);
1876 falcon_write(efx
, ®
, MAC0_STAT_DMA_REG_KER
);
1878 /* Wait for transfer to complete */
1879 for (i
= 0; i
< 400; i
++) {
1880 if (*(volatile u32
*)dma_done
== FALCON_STATS_DONE
)
1885 EFX_ERR(efx
, "timed out waiting for statistics\n");
1889 /**************************************************************************
1891 * PHY access via GMII
1893 **************************************************************************
1896 /* Use the top bit of the MII PHY id to indicate the PHY type
1897 * (1G/10G), with the remaining bits as the actual PHY id.
1899 * This allows us to avoid leaking information from the mii_if_info
1900 * structure into other data structures.
1902 #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1903 #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1904 #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1905 #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1906 #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1909 /* Packing the clause 45 port and device fields into a single value */
1910 #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1911 #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1912 #define MD_DEV_ADR_COMP_LBN 0
1913 #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1916 /* Wait for GMII access to complete */
1917 static int falcon_gmii_wait(struct efx_nic
*efx
)
1919 efx_dword_t md_stat
;
1922 for (count
= 0; count
< 1000; count
++) { /* wait upto 10ms */
1923 falcon_readl(efx
, &md_stat
, MD_STAT_REG_KER
);
1924 if (EFX_DWORD_FIELD(md_stat
, MD_BSY
) == 0) {
1925 if (EFX_DWORD_FIELD(md_stat
, MD_LNFL
) != 0 ||
1926 EFX_DWORD_FIELD(md_stat
, MD_BSERR
) != 0) {
1927 EFX_ERR(efx
, "error from GMII access "
1929 EFX_DWORD_VAL(md_stat
));
1936 EFX_ERR(efx
, "timed out waiting for GMII\n");
1940 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
1941 static void falcon_mdio_write(struct net_device
*net_dev
, int phy_id
,
1942 int addr
, int value
)
1944 struct efx_nic
*efx
= (struct efx_nic
*)net_dev
->priv
;
1945 unsigned int phy_id2
= phy_id
& FALCON_PHY_ID_ID_MASK
;
1948 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
1949 * chosen so that the only current user, Falcon, can take the
1950 * packed value and use them directly.
1951 * Fail to build if this assumption is broken.
1953 BUILD_BUG_ON(FALCON_PHY_ID_10G
!= MDIO45_XPRT_ID_IS10G
);
1954 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH
!= MDIO45_PRT_DEV_WIDTH
);
1955 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN
!= MDIO45_PRT_ID_COMP_LBN
);
1956 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN
!= MDIO45_DEV_ID_COMP_LBN
);
1958 if (phy_id2
== PHY_ADDR_INVALID
)
1961 /* See falcon_mdio_read for an explanation. */
1962 if (!(phy_id
& FALCON_PHY_ID_10G
)) {
1963 int mmd
= ffs(efx
->phy_op
->mmds
) - 1;
1964 EFX_TRACE(efx
, "Fixing erroneous clause22 write\n");
1965 phy_id2
= mdio_clause45_pack(phy_id2
, mmd
)
1966 & FALCON_PHY_ID_ID_MASK
;
1969 EFX_REGDUMP(efx
, "writing GMII %d register %02x with %04x\n", phy_id
,
1972 spin_lock_bh(&efx
->phy_lock
);
1974 /* Check MII not currently being accessed */
1975 if (falcon_gmii_wait(efx
) != 0)
1978 /* Write the address/ID register */
1979 EFX_POPULATE_OWORD_1(reg
, MD_PHY_ADR
, addr
);
1980 falcon_write(efx
, ®
, MD_PHY_ADR_REG_KER
);
1982 EFX_POPULATE_OWORD_1(reg
, MD_PRT_DEV_ADR
, phy_id2
);
1983 falcon_write(efx
, ®
, MD_ID_REG_KER
);
1986 EFX_POPULATE_OWORD_1(reg
, MD_TXD
, value
);
1987 falcon_write(efx
, ®
, MD_TXD_REG_KER
);
1989 EFX_POPULATE_OWORD_2(reg
,
1992 falcon_write(efx
, ®
, MD_CS_REG_KER
);
1994 /* Wait for data to be written */
1995 if (falcon_gmii_wait(efx
) != 0) {
1996 /* Abort the write operation */
1997 EFX_POPULATE_OWORD_2(reg
,
2000 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2005 spin_unlock_bh(&efx
->phy_lock
);
2008 /* Reads a GMII register from a PHY connected to Falcon. If no value
2009 * could be read, -1 will be returned. */
2010 static int falcon_mdio_read(struct net_device
*net_dev
, int phy_id
, int addr
)
2012 struct efx_nic
*efx
= (struct efx_nic
*)net_dev
->priv
;
2013 unsigned int phy_addr
= phy_id
& FALCON_PHY_ID_ID_MASK
;
2017 if (phy_addr
== PHY_ADDR_INVALID
)
2020 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2021 * but the generic Linux code does not make any distinction or have
2022 * any state for this.
2023 * We spot the case where someone tried to talk 22 to a 45 PHY and
2024 * redirect the request to the lowest numbered MMD as a clause45
2025 * request. This is enough to allow simple queries like id and link
2026 * state to succeed. TODO: We may need to do more in future.
2028 if (!(phy_id
& FALCON_PHY_ID_10G
)) {
2029 int mmd
= ffs(efx
->phy_op
->mmds
) - 1;
2030 EFX_TRACE(efx
, "Fixing erroneous clause22 read\n");
2031 phy_addr
= mdio_clause45_pack(phy_addr
, mmd
)
2032 & FALCON_PHY_ID_ID_MASK
;
2035 spin_lock_bh(&efx
->phy_lock
);
2037 /* Check MII not currently being accessed */
2038 if (falcon_gmii_wait(efx
) != 0)
2041 EFX_POPULATE_OWORD_1(reg
, MD_PHY_ADR
, addr
);
2042 falcon_write(efx
, ®
, MD_PHY_ADR_REG_KER
);
2044 EFX_POPULATE_OWORD_1(reg
, MD_PRT_DEV_ADR
, phy_addr
);
2045 falcon_write(efx
, ®
, MD_ID_REG_KER
);
2047 /* Request data to be read */
2048 EFX_POPULATE_OWORD_2(reg
, MD_RDC
, 1, MD_GC
, 0);
2049 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2051 /* Wait for data to become available */
2052 value
= falcon_gmii_wait(efx
);
2054 falcon_read(efx
, ®
, MD_RXD_REG_KER
);
2055 value
= EFX_OWORD_FIELD(reg
, MD_RXD
);
2056 EFX_REGDUMP(efx
, "read from GMII %d register %02x, got %04x\n",
2057 phy_id
, addr
, value
);
2059 /* Abort the read operation */
2060 EFX_POPULATE_OWORD_2(reg
,
2063 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2065 EFX_LOG(efx
, "read from GMII 0x%x register %02x, got "
2066 "error %d\n", phy_id
, addr
, value
);
2070 spin_unlock_bh(&efx
->phy_lock
);
2075 static void falcon_init_mdio(struct mii_if_info
*gmii
)
2077 gmii
->mdio_read
= falcon_mdio_read
;
2078 gmii
->mdio_write
= falcon_mdio_write
;
2079 gmii
->phy_id_mask
= FALCON_PHY_ID_MASK
;
2080 gmii
->reg_num_mask
= ((1 << EFX_WIDTH(MD_PHY_ADR
)) - 1);
2083 static int falcon_probe_phy(struct efx_nic
*efx
)
2085 switch (efx
->phy_type
) {
2086 case PHY_TYPE_10XPRESS
:
2087 efx
->phy_op
= &falcon_tenxpress_phy_ops
;
2090 efx
->phy_op
= &falcon_xfp_phy_ops
;
2093 EFX_ERR(efx
, "Unknown PHY type %d\n",
2098 efx
->loopback_modes
= LOOPBACKS_10G_INTERNAL
| efx
->phy_op
->loopbacks
;
2102 /* This call is responsible for hooking in the MAC and PHY operations */
2103 int falcon_probe_port(struct efx_nic
*efx
)
2107 /* Hook in PHY operations table */
2108 rc
= falcon_probe_phy(efx
);
2112 /* Set up GMII structure for PHY */
2113 efx
->mii
.supports_gmii
= 1;
2114 falcon_init_mdio(&efx
->mii
);
2116 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2117 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2118 efx
->flow_control
= EFX_FC_RX
| EFX_FC_TX
;
2120 efx
->flow_control
= EFX_FC_RX
;
2122 /* Allocate buffer for stats */
2123 rc
= falcon_alloc_buffer(efx
, &efx
->stats_buffer
,
2124 FALCON_MAC_STATS_SIZE
);
2127 EFX_LOG(efx
, "stats buffer at %llx (virt %p phys %lx)\n",
2128 (unsigned long long)efx
->stats_buffer
.dma_addr
,
2129 efx
->stats_buffer
.addr
,
2130 virt_to_phys(efx
->stats_buffer
.addr
));
2135 void falcon_remove_port(struct efx_nic
*efx
)
2137 falcon_free_buffer(efx
, &efx
->stats_buffer
);
2140 /**************************************************************************
2142 * Multicast filtering
2144 **************************************************************************
2147 void falcon_set_multicast_hash(struct efx_nic
*efx
)
2149 union efx_multicast_hash
*mc_hash
= &efx
->multicast_hash
;
2151 /* Broadcast packets go through the multicast hash filter.
2152 * ether_crc_le() of the broadcast address is 0xbe2612ff
2153 * so we always add bit 0xff to the mask.
2155 set_bit_le(0xff, mc_hash
->byte
);
2157 falcon_write(efx
, &mc_hash
->oword
[0], MAC_MCAST_HASH_REG0_KER
);
2158 falcon_write(efx
, &mc_hash
->oword
[1], MAC_MCAST_HASH_REG1_KER
);
2161 /**************************************************************************
2165 **************************************************************************
2168 /* Resets NIC to known state. This routine must be called in process
2169 * context and is allowed to sleep. */
2170 int falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
)
2172 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2173 efx_oword_t glb_ctl_reg_ker
;
2176 EFX_LOG(efx
, "performing hardware reset (%d)\n", method
);
2178 /* Initiate device reset */
2179 if (method
== RESET_TYPE_WORLD
) {
2180 rc
= pci_save_state(efx
->pci_dev
);
2182 EFX_ERR(efx
, "failed to backup PCI state of primary "
2183 "function prior to hardware reset\n");
2186 if (FALCON_IS_DUAL_FUNC(efx
)) {
2187 rc
= pci_save_state(nic_data
->pci_dev2
);
2189 EFX_ERR(efx
, "failed to backup PCI state of "
2190 "secondary function prior to "
2191 "hardware reset\n");
2196 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker
,
2197 EXT_PHY_RST_DUR
, 0x7,
2200 int reset_phy
= (method
== RESET_TYPE_INVISIBLE
?
2201 EXCLUDE_FROM_RESET
: 0);
2203 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker
,
2204 EXT_PHY_RST_CTL
, reset_phy
,
2205 PCIE_CORE_RST_CTL
, EXCLUDE_FROM_RESET
,
2206 PCIE_NSTCK_RST_CTL
, EXCLUDE_FROM_RESET
,
2207 PCIE_SD_RST_CTL
, EXCLUDE_FROM_RESET
,
2208 EE_RST_CTL
, EXCLUDE_FROM_RESET
,
2209 EXT_PHY_RST_DUR
, 0x7 /* 10ms */,
2212 falcon_write(efx
, &glb_ctl_reg_ker
, GLB_CTL_REG_KER
);
2214 EFX_LOG(efx
, "waiting for hardware reset\n");
2215 schedule_timeout_uninterruptible(HZ
/ 20);
2217 /* Restore PCI configuration if needed */
2218 if (method
== RESET_TYPE_WORLD
) {
2219 if (FALCON_IS_DUAL_FUNC(efx
)) {
2220 rc
= pci_restore_state(nic_data
->pci_dev2
);
2222 EFX_ERR(efx
, "failed to restore PCI config for "
2223 "the secondary function\n");
2227 rc
= pci_restore_state(efx
->pci_dev
);
2229 EFX_ERR(efx
, "failed to restore PCI config for the "
2230 "primary function\n");
2233 EFX_LOG(efx
, "successfully restored PCI config\n");
2236 /* Assert that reset complete */
2237 falcon_read(efx
, &glb_ctl_reg_ker
, GLB_CTL_REG_KER
);
2238 if (EFX_OWORD_FIELD(glb_ctl_reg_ker
, SWRST
) != 0) {
2240 EFX_ERR(efx
, "timed out waiting for hardware reset\n");
2243 EFX_LOG(efx
, "hardware reset complete\n");
2247 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2250 pci_restore_state(efx
->pci_dev
);
2257 /* Zeroes out the SRAM contents. This routine must be called in
2258 * process context and is allowed to sleep.
2260 static int falcon_reset_sram(struct efx_nic
*efx
)
2262 efx_oword_t srm_cfg_reg_ker
, gpio_cfg_reg_ker
;
2265 /* Set the SRAM wake/sleep GPIO appropriately. */
2266 falcon_read(efx
, &gpio_cfg_reg_ker
, GPIO_CTL_REG_KER
);
2267 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, GPIO1_OEN
, 1);
2268 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, GPIO1_OUT
, 1);
2269 falcon_write(efx
, &gpio_cfg_reg_ker
, GPIO_CTL_REG_KER
);
2271 /* Initiate SRAM reset */
2272 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker
,
2273 SRAM_OOB_BT_INIT_EN
, 1,
2274 SRM_NUM_BANKS_AND_BANK_SIZE
, 0);
2275 falcon_write(efx
, &srm_cfg_reg_ker
, SRM_CFG_REG_KER
);
2277 /* Wait for SRAM reset to complete */
2280 EFX_LOG(efx
, "waiting for SRAM reset (attempt %d)...\n", count
);
2282 /* SRAM reset is slow; expect around 16ms */
2283 schedule_timeout_uninterruptible(HZ
/ 50);
2285 /* Check for reset complete */
2286 falcon_read(efx
, &srm_cfg_reg_ker
, SRM_CFG_REG_KER
);
2287 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker
, SRAM_OOB_BT_INIT_EN
)) {
2288 EFX_LOG(efx
, "SRAM reset complete\n");
2292 } while (++count
< 20); /* wait upto 0.4 sec */
2294 EFX_ERR(efx
, "timed out waiting for SRAM reset\n");
2298 /* Extract non-volatile configuration */
2299 static int falcon_probe_nvconfig(struct efx_nic
*efx
)
2301 struct falcon_nvconfig
*nvconfig
;
2302 efx_oword_t nic_stat
;
2306 int magic_num
, struct_ver
, board_rev
;
2309 /* Find the boot device. */
2310 falcon_read(efx
, &nic_stat
, NIC_STAT_REG
);
2311 if (EFX_OWORD_FIELD(nic_stat
, SF_PRST
)) {
2312 device_id
= EE_SPI_FLASH
;
2314 } else if (EFX_OWORD_FIELD(nic_stat
, EE_PRST
)) {
2315 device_id
= EE_SPI_EEPROM
;
2321 nvconfig
= kmalloc(sizeof(*nvconfig
), GFP_KERNEL
);
2323 /* Read the whole configuration structure into memory. */
2324 for (offset
= 0; offset
< sizeof(*nvconfig
); offset
+= len
) {
2325 len
= min(sizeof(*nvconfig
) - offset
,
2326 (size_t) FALCON_SPI_MAX_LEN
);
2327 rc
= falcon_spi_read(efx
, device_id
, SPI_READ
,
2328 NVCONFIG_BASE
+ offset
, addr_len
,
2329 (char *)nvconfig
+ offset
, len
);
2334 /* Read the MAC addresses */
2335 memcpy(efx
->mac_address
, nvconfig
->mac_address
[0], ETH_ALEN
);
2337 /* Read the board configuration. */
2338 magic_num
= le16_to_cpu(nvconfig
->board_magic_num
);
2339 struct_ver
= le16_to_cpu(nvconfig
->board_struct_ver
);
2341 if (magic_num
!= NVCONFIG_BOARD_MAGIC_NUM
|| struct_ver
< 2) {
2342 EFX_ERR(efx
, "Non volatile memory bad magic=%x ver=%x "
2343 "therefore using defaults\n", magic_num
, struct_ver
);
2344 efx
->phy_type
= PHY_TYPE_NONE
;
2345 efx
->mii
.phy_id
= PHY_ADDR_INVALID
;
2348 struct falcon_nvconfig_board_v2
*v2
= &nvconfig
->board_v2
;
2350 efx
->phy_type
= v2
->port0_phy_type
;
2351 efx
->mii
.phy_id
= v2
->port0_phy_addr
;
2352 board_rev
= le16_to_cpu(v2
->board_revision
);
2355 EFX_LOG(efx
, "PHY is %d phy_id %d\n", efx
->phy_type
, efx
->mii
.phy_id
);
2357 efx_set_board_info(efx
, board_rev
);
2364 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2365 * count, port speed). Set workaround and feature flags accordingly.
2367 static int falcon_probe_nic_variant(struct efx_nic
*efx
)
2369 efx_oword_t altera_build
;
2371 falcon_read(efx
, &altera_build
, ALTERA_BUILD_REG_KER
);
2372 if (EFX_OWORD_FIELD(altera_build
, VER_ALL
)) {
2373 EFX_ERR(efx
, "Falcon FPGA not supported\n");
2377 switch (falcon_rev(efx
)) {
2380 EFX_ERR(efx
, "Falcon rev A0 not supported\n");
2383 case FALCON_REV_A1
:{
2384 efx_oword_t nic_stat
;
2386 falcon_read(efx
, &nic_stat
, NIC_STAT_REG
);
2388 if (EFX_OWORD_FIELD(nic_stat
, STRAP_PCIE
) == 0) {
2389 EFX_ERR(efx
, "Falcon rev A1 PCI-X not supported\n");
2392 if (!EFX_OWORD_FIELD(nic_stat
, STRAP_10G
)) {
2393 EFX_ERR(efx
, "1G mode not supported\n");
2403 EFX_ERR(efx
, "Unknown Falcon rev %d\n", falcon_rev(efx
));
2410 int falcon_probe_nic(struct efx_nic
*efx
)
2412 struct falcon_nic_data
*nic_data
;
2415 /* Initialise I2C interface state */
2417 efx
->i2c
.op
= &falcon_i2c_bit_operations
;
2421 /* Allocate storage for hardware specific data */
2422 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
2423 efx
->nic_data
= (void *) nic_data
;
2425 /* Determine number of ports etc. */
2426 rc
= falcon_probe_nic_variant(efx
);
2430 /* Probe secondary function if expected */
2431 if (FALCON_IS_DUAL_FUNC(efx
)) {
2432 struct pci_dev
*dev
= pci_dev_get(efx
->pci_dev
);
2434 while ((dev
= pci_get_device(EFX_VENDID_SFC
, FALCON_A_S_DEVID
,
2436 if (dev
->bus
== efx
->pci_dev
->bus
&&
2437 dev
->devfn
== efx
->pci_dev
->devfn
+ 1) {
2438 nic_data
->pci_dev2
= dev
;
2442 if (!nic_data
->pci_dev2
) {
2443 EFX_ERR(efx
, "failed to find secondary function\n");
2449 /* Now we can reset the NIC */
2450 rc
= falcon_reset_hw(efx
, RESET_TYPE_ALL
);
2452 EFX_ERR(efx
, "failed to reset NIC\n");
2456 /* Allocate memory for INT_KER */
2457 rc
= falcon_alloc_buffer(efx
, &efx
->irq_status
, sizeof(efx_oword_t
));
2460 BUG_ON(efx
->irq_status
.dma_addr
& 0x0f);
2462 EFX_LOG(efx
, "INT_KER at %llx (virt %p phys %lx)\n",
2463 (unsigned long long)efx
->irq_status
.dma_addr
,
2464 efx
->irq_status
.addr
, virt_to_phys(efx
->irq_status
.addr
));
2466 /* Read in the non-volatile configuration */
2467 rc
= falcon_probe_nvconfig(efx
);
2474 falcon_free_buffer(efx
, &efx
->irq_status
);
2477 if (nic_data
->pci_dev2
) {
2478 pci_dev_put(nic_data
->pci_dev2
);
2479 nic_data
->pci_dev2
= NULL
;
2483 kfree(efx
->nic_data
);
2487 /* This call performs hardware-specific global initialisation, such as
2488 * defining the descriptor cache sizes and number of RSS channels.
2489 * It does not set up any buffers, descriptor rings or event queues.
2491 int falcon_init_nic(struct efx_nic
*efx
)
2493 struct falcon_nic_data
*data
;
2498 data
= (struct falcon_nic_data
*)efx
->nic_data
;
2500 /* Set up the address region register. This is only needed
2501 * for the B0 FPGA, but since we are just pushing in the
2502 * reset defaults this may as well be unconditional. */
2503 EFX_POPULATE_OWORD_4(temp
, ADR_REGION0
, 0,
2504 ADR_REGION1
, (1 << 16),
2505 ADR_REGION2
, (2 << 16),
2506 ADR_REGION3
, (3 << 16));
2507 falcon_write(efx
, &temp
, ADR_REGION_REG_KER
);
2509 /* Use on-chip SRAM */
2510 falcon_read(efx
, &temp
, NIC_STAT_REG
);
2511 EFX_SET_OWORD_FIELD(temp
, ONCHIP_SRAM
, 1);
2512 falcon_write(efx
, &temp
, NIC_STAT_REG
);
2514 /* Set buffer table mode */
2515 EFX_POPULATE_OWORD_1(temp
, BUF_TBL_MODE
, BUF_TBL_MODE_FULL
);
2516 falcon_write(efx
, &temp
, BUF_TBL_CFG_REG_KER
);
2518 rc
= falcon_reset_sram(efx
);
2522 /* Set positions of descriptor caches in SRAM. */
2523 EFX_POPULATE_OWORD_1(temp
, SRM_TX_DC_BASE_ADR
, TX_DC_BASE
/ 8);
2524 falcon_write(efx
, &temp
, SRM_TX_DC_CFG_REG_KER
);
2525 EFX_POPULATE_OWORD_1(temp
, SRM_RX_DC_BASE_ADR
, RX_DC_BASE
/ 8);
2526 falcon_write(efx
, &temp
, SRM_RX_DC_CFG_REG_KER
);
2528 /* Set TX descriptor cache size. */
2529 BUILD_BUG_ON(TX_DC_ENTRIES
!= (16 << TX_DC_ENTRIES_ORDER
));
2530 EFX_POPULATE_OWORD_1(temp
, TX_DC_SIZE
, TX_DC_ENTRIES_ORDER
);
2531 falcon_write(efx
, &temp
, TX_DC_CFG_REG_KER
);
2533 /* Set RX descriptor cache size. Set low watermark to size-8, as
2534 * this allows most efficient prefetching.
2536 BUILD_BUG_ON(RX_DC_ENTRIES
!= (16 << RX_DC_ENTRIES_ORDER
));
2537 EFX_POPULATE_OWORD_1(temp
, RX_DC_SIZE
, RX_DC_ENTRIES_ORDER
);
2538 falcon_write(efx
, &temp
, RX_DC_CFG_REG_KER
);
2539 EFX_POPULATE_OWORD_1(temp
, RX_DC_PF_LWM
, RX_DC_ENTRIES
- 8);
2540 falcon_write(efx
, &temp
, RX_DC_PF_WM_REG_KER
);
2542 /* Clear the parity enables on the TX data fifos as
2543 * they produce false parity errors because of timing issues
2545 if (EFX_WORKAROUND_5129(efx
)) {
2546 falcon_read(efx
, &temp
, SPARE_REG_KER
);
2547 EFX_SET_OWORD_FIELD(temp
, MEM_PERR_EN_TX_DATA
, 0);
2548 falcon_write(efx
, &temp
, SPARE_REG_KER
);
2551 /* Enable all the genuinely fatal interrupts. (They are still
2552 * masked by the overall interrupt mask, controlled by
2553 * falcon_interrupts()).
2555 * Note: All other fatal interrupts are enabled
2557 EFX_POPULATE_OWORD_3(temp
,
2558 ILL_ADR_INT_KER_EN
, 1,
2559 RBUF_OWN_INT_KER_EN
, 1,
2560 TBUF_OWN_INT_KER_EN
, 1);
2561 EFX_INVERT_OWORD(temp
);
2562 falcon_write(efx
, &temp
, FATAL_INTR_REG_KER
);
2564 /* Set number of RSS queues for receive path. */
2565 falcon_read(efx
, &temp
, RX_FILTER_CTL_REG
);
2566 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2567 EFX_SET_OWORD_FIELD(temp
, NUM_KER
, 0);
2569 EFX_SET_OWORD_FIELD(temp
, NUM_KER
, efx
->rss_queues
- 1);
2570 if (EFX_WORKAROUND_7244(efx
)) {
2571 EFX_SET_OWORD_FIELD(temp
, UDP_FULL_SRCH_LIMIT
, 8);
2572 EFX_SET_OWORD_FIELD(temp
, UDP_WILD_SRCH_LIMIT
, 8);
2573 EFX_SET_OWORD_FIELD(temp
, TCP_FULL_SRCH_LIMIT
, 8);
2574 EFX_SET_OWORD_FIELD(temp
, TCP_WILD_SRCH_LIMIT
, 8);
2576 falcon_write(efx
, &temp
, RX_FILTER_CTL_REG
);
2578 falcon_setup_rss_indir_table(efx
);
2580 /* Setup RX. Wait for descriptor is broken and must
2581 * be disabled. RXDP recovery shouldn't be needed, but is.
2583 falcon_read(efx
, &temp
, RX_SELF_RST_REG_KER
);
2584 EFX_SET_OWORD_FIELD(temp
, RX_NODESC_WAIT_DIS
, 1);
2585 EFX_SET_OWORD_FIELD(temp
, RX_RECOVERY_EN
, 1);
2586 if (EFX_WORKAROUND_5583(efx
))
2587 EFX_SET_OWORD_FIELD(temp
, RX_ISCSI_DIS
, 1);
2588 falcon_write(efx
, &temp
, RX_SELF_RST_REG_KER
);
2590 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2591 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2593 falcon_read(efx
, &temp
, TX_CFG2_REG_KER
);
2594 EFX_SET_OWORD_FIELD(temp
, TX_RX_SPACER
, 0xfe);
2595 EFX_SET_OWORD_FIELD(temp
, TX_RX_SPACER_EN
, 1);
2596 EFX_SET_OWORD_FIELD(temp
, TX_ONE_PKT_PER_Q
, 1);
2597 EFX_SET_OWORD_FIELD(temp
, TX_CSR_PUSH_EN
, 0);
2598 EFX_SET_OWORD_FIELD(temp
, TX_DIS_NON_IP_EV
, 1);
2599 /* Enable SW_EV to inherit in char driver - assume harmless here */
2600 EFX_SET_OWORD_FIELD(temp
, TX_SW_EV_EN
, 1);
2601 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2602 EFX_SET_OWORD_FIELD(temp
, TX_PREF_THRESHOLD
, 2);
2603 /* Squash TX of packets of 16 bytes or less */
2604 if (falcon_rev(efx
) >= FALCON_REV_B0
&& EFX_WORKAROUND_9141(efx
))
2605 EFX_SET_OWORD_FIELD(temp
, TX_FLUSH_MIN_LEN_EN_B0
, 1);
2606 falcon_write(efx
, &temp
, TX_CFG2_REG_KER
);
2608 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2609 * descriptors (which is bad).
2611 falcon_read(efx
, &temp
, TX_CFG_REG_KER
);
2612 EFX_SET_OWORD_FIELD(temp
, TX_NO_EOP_DISC_EN
, 0);
2613 falcon_write(efx
, &temp
, TX_CFG_REG_KER
);
2616 falcon_read(efx
, &temp
, RX_CFG_REG_KER
);
2617 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_DESC_PUSH_EN
, 0);
2618 if (EFX_WORKAROUND_7575(efx
))
2619 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_USR_BUF_SIZE
,
2621 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2622 EFX_SET_OWORD_FIELD(temp
, RX_INGR_EN_B0
, 1);
2624 /* RX FIFO flow control thresholds */
2625 thresh
= ((rx_xon_thresh_bytes
>= 0) ?
2626 rx_xon_thresh_bytes
: efx
->type
->rx_xon_thresh
);
2627 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XON_MAC_TH
, thresh
/ 256);
2628 thresh
= ((rx_xoff_thresh_bytes
>= 0) ?
2629 rx_xoff_thresh_bytes
: efx
->type
->rx_xoff_thresh
);
2630 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XOFF_MAC_TH
, thresh
/ 256);
2631 /* RX control FIFO thresholds [32 entries] */
2632 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XON_TX_TH
, 25);
2633 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XOFF_TX_TH
, 20);
2634 falcon_write(efx
, &temp
, RX_CFG_REG_KER
);
2636 /* Set destination of both TX and RX Flush events */
2637 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
2638 EFX_POPULATE_OWORD_1(temp
, FLS_EVQ_ID
, 0);
2639 falcon_write(efx
, &temp
, DP_CTRL_REG
);
2645 void falcon_remove_nic(struct efx_nic
*efx
)
2647 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2649 falcon_free_buffer(efx
, &efx
->irq_status
);
2651 falcon_reset_hw(efx
, RESET_TYPE_ALL
);
2653 /* Release the second function after the reset */
2654 if (nic_data
->pci_dev2
) {
2655 pci_dev_put(nic_data
->pci_dev2
);
2656 nic_data
->pci_dev2
= NULL
;
2659 /* Tear down the private nic state */
2660 kfree(efx
->nic_data
);
2661 efx
->nic_data
= NULL
;
2664 void falcon_update_nic_stats(struct efx_nic
*efx
)
2668 falcon_read(efx
, &cnt
, RX_NODESC_DROP_REG_KER
);
2669 efx
->n_rx_nodesc_drop_cnt
+= EFX_OWORD_FIELD(cnt
, RX_NODESC_DROP_CNT
);
2672 /**************************************************************************
2674 * Revision-dependent attributes used by efx.c
2676 **************************************************************************
2679 struct efx_nic_type falcon_a_nic_type
= {
2681 .mem_map_size
= 0x20000,
2682 .txd_ptr_tbl_base
= TX_DESC_PTR_TBL_KER_A1
,
2683 .rxd_ptr_tbl_base
= RX_DESC_PTR_TBL_KER_A1
,
2684 .buf_tbl_base
= BUF_TBL_KER_A1
,
2685 .evq_ptr_tbl_base
= EVQ_PTR_TBL_KER_A1
,
2686 .evq_rptr_tbl_base
= EVQ_RPTR_REG_KER_A1
,
2687 .txd_ring_mask
= FALCON_TXD_RING_MASK
,
2688 .rxd_ring_mask
= FALCON_RXD_RING_MASK
,
2689 .evq_size
= FALCON_EVQ_SIZE
,
2690 .max_dma_mask
= FALCON_DMA_MASK
,
2691 .tx_dma_mask
= FALCON_TX_DMA_MASK
,
2692 .bug5391_mask
= 0xf,
2693 .rx_xoff_thresh
= 2048,
2694 .rx_xon_thresh
= 512,
2695 .rx_buffer_padding
= 0x24,
2696 .max_interrupt_mode
= EFX_INT_MODE_MSI
,
2697 .phys_addr_channels
= 4,
2700 struct efx_nic_type falcon_b_nic_type
= {
2702 /* Map everything up to and including the RSS indirection
2703 * table. Don't map MSI-X table, MSI-X PBA since Linux
2704 * requires that they not be mapped. */
2705 .mem_map_size
= RX_RSS_INDIR_TBL_B0
+ 0x800,
2706 .txd_ptr_tbl_base
= TX_DESC_PTR_TBL_KER_B0
,
2707 .rxd_ptr_tbl_base
= RX_DESC_PTR_TBL_KER_B0
,
2708 .buf_tbl_base
= BUF_TBL_KER_B0
,
2709 .evq_ptr_tbl_base
= EVQ_PTR_TBL_KER_B0
,
2710 .evq_rptr_tbl_base
= EVQ_RPTR_REG_KER_B0
,
2711 .txd_ring_mask
= FALCON_TXD_RING_MASK
,
2712 .rxd_ring_mask
= FALCON_RXD_RING_MASK
,
2713 .evq_size
= FALCON_EVQ_SIZE
,
2714 .max_dma_mask
= FALCON_DMA_MASK
,
2715 .tx_dma_mask
= FALCON_TX_DMA_MASK
,
2717 .rx_xoff_thresh
= 54272, /* ~80Kb - 3*max MTU */
2718 .rx_xon_thresh
= 27648, /* ~3*max MTU */
2719 .rx_buffer_padding
= 0,
2720 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
2721 .phys_addr_channels
= 32, /* Hardware limit is 64, but the legacy
2722 * interrupt handler only supports 32