1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007-2009 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include <linux/delay.h>
11 #include <linux/rtnetlink.h>
12 #include <linux/seq_file.h>
18 #include "workarounds.h"
21 /* We expect these MMDs to be in the package. SFT9001 also has a
22 * clause 22 extension MMD, but since it doesn't have all the generic
23 * MMD registers it is pointless to include it here.
25 #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
30 #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
31 (1 << LOOPBACK_PCS) | \
32 (1 << LOOPBACK_PMAPMD) | \
33 (1 << LOOPBACK_PHYXS_WS))
35 #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
36 (1 << LOOPBACK_PHYXS) | \
37 (1 << LOOPBACK_PCS) | \
38 (1 << LOOPBACK_PMAPMD) | \
39 (1 << LOOPBACK_PHYXS_WS))
41 /* We complain if we fail to see the link partner as 10G capable this many
42 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
44 #define MAX_BAD_LP_TRIES (5)
46 /* Extended control register */
47 #define PMA_PMD_XCONTROL_REG 49152
48 #define PMA_PMD_EXT_GMII_EN_LBN 1
49 #define PMA_PMD_EXT_GMII_EN_WIDTH 1
50 #define PMA_PMD_EXT_CLK_OUT_LBN 2
51 #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
52 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
53 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
54 #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
55 #define PMA_PMD_EXT_CLK312_WIDTH 1
56 #define PMA_PMD_EXT_LPOWER_LBN 12
57 #define PMA_PMD_EXT_LPOWER_WIDTH 1
58 #define PMA_PMD_EXT_ROBUST_LBN 14
59 #define PMA_PMD_EXT_ROBUST_WIDTH 1
60 #define PMA_PMD_EXT_SSR_LBN 15
61 #define PMA_PMD_EXT_SSR_WIDTH 1
63 /* extended status register */
64 #define PMA_PMD_XSTATUS_REG 49153
65 #define PMA_PMD_XSTAT_MDIX_LBN 14
66 #define PMA_PMD_XSTAT_FLP_LBN (12)
68 /* LED control register */
69 #define PMA_PMD_LED_CTRL_REG 49159
70 #define PMA_PMA_LED_ACTIVITY_LBN (3)
72 /* LED function override register */
73 #define PMA_PMD_LED_OVERR_REG 49161
74 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
75 #define PMA_PMD_LED_LINK_LBN (0)
76 #define PMA_PMD_LED_SPEED_LBN (2)
77 #define PMA_PMD_LED_TX_LBN (4)
78 #define PMA_PMD_LED_RX_LBN (6)
79 /* Override settings */
80 #define PMA_PMD_LED_AUTO (0) /* H/W control */
81 #define PMA_PMD_LED_ON (1)
82 #define PMA_PMD_LED_OFF (2)
83 #define PMA_PMD_LED_FLASH (3)
84 #define PMA_PMD_LED_MASK 3
85 /* All LEDs under hardware control */
86 #define SFT9001_PMA_PMD_LED_DEFAULT 0
87 /* Green and Amber under hardware control, Red off */
88 #define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
90 #define PMA_PMD_SPEED_ENABLE_REG 49192
91 #define PMA_PMD_100TX_ADV_LBN 1
92 #define PMA_PMD_100TX_ADV_WIDTH 1
93 #define PMA_PMD_1000T_ADV_LBN 2
94 #define PMA_PMD_1000T_ADV_WIDTH 1
95 #define PMA_PMD_10000T_ADV_LBN 3
96 #define PMA_PMD_10000T_ADV_WIDTH 1
97 #define PMA_PMD_SPEED_LBN 4
98 #define PMA_PMD_SPEED_WIDTH 4
100 /* Cable diagnostics - SFT9001 only */
101 #define PMA_PMD_CDIAG_CTRL_REG 49213
102 #define CDIAG_CTRL_IMMED_LBN 15
103 #define CDIAG_CTRL_BRK_LINK_LBN 12
104 #define CDIAG_CTRL_IN_PROG_LBN 11
105 #define CDIAG_CTRL_LEN_UNIT_LBN 10
106 #define CDIAG_CTRL_LEN_METRES 1
107 #define PMA_PMD_CDIAG_RES_REG 49174
108 #define CDIAG_RES_A_LBN 12
109 #define CDIAG_RES_B_LBN 8
110 #define CDIAG_RES_C_LBN 4
111 #define CDIAG_RES_D_LBN 0
112 #define CDIAG_RES_WIDTH 4
113 #define CDIAG_RES_OPEN 2
114 #define CDIAG_RES_OK 1
115 #define CDIAG_RES_INVALID 0
116 /* Set of 4 registers for pairs A-D */
117 #define PMA_PMD_CDIAG_LEN_REG 49175
119 /* Serdes control registers - SFT9001 only */
120 #define PMA_PMD_CSERDES_CTRL_REG 64258
121 /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
122 #define PMA_PMD_CSERDES_DEFAULT 0x000f
124 /* Misc register defines - SFX7101 only */
125 #define PCS_CLOCK_CTRL_REG 55297
126 #define PLL312_RST_N_LBN 2
128 #define PCS_SOFT_RST2_REG 55302
129 #define SERDES_RST_N_LBN 13
130 #define XGXS_RST_N_LBN 12
132 #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
133 #define CLK312_EN_LBN 3
135 /* PHYXS registers */
136 #define PHYXS_XCONTROL_REG 49152
137 #define PHYXS_RESET_LBN 15
138 #define PHYXS_RESET_WIDTH 1
140 #define PHYXS_TEST1 (49162)
141 #define LOOPBACK_NEAR_LBN (8)
142 #define LOOPBACK_NEAR_WIDTH (1)
144 /* Boot status register */
145 #define PCS_BOOT_STATUS_REG 53248
146 #define PCS_BOOT_FATAL_ERROR_LBN 0
147 #define PCS_BOOT_PROGRESS_LBN 1
148 #define PCS_BOOT_PROGRESS_WIDTH 2
149 #define PCS_BOOT_PROGRESS_INIT 0
150 #define PCS_BOOT_PROGRESS_WAIT_MDIO 1
151 #define PCS_BOOT_PROGRESS_CHECKSUM 2
152 #define PCS_BOOT_PROGRESS_JUMP 3
153 #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
154 #define PCS_BOOT_CODE_STARTED_LBN 4
156 /* 100M/1G PHY registers */
157 #define GPHY_XCONTROL_REG 49152
158 #define GPHY_ISOLATE_LBN 10
159 #define GPHY_ISOLATE_WIDTH 1
160 #define GPHY_DUPLEX_LBN 8
161 #define GPHY_DUPLEX_WIDTH 1
162 #define GPHY_LOOPBACK_NEAR_LBN 14
163 #define GPHY_LOOPBACK_NEAR_WIDTH 1
165 #define C22EXT_STATUS_REG 49153
166 #define C22EXT_STATUS_LINK_LBN 2
167 #define C22EXT_STATUS_LINK_WIDTH 1
169 #define C22EXT_MSTSLV_CTRL 49161
170 #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
171 #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
173 #define C22EXT_MSTSLV_STATUS 49162
174 #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
175 #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
177 /* Time to wait between powering down the LNPGA and turning off the power
179 #define LNPGA_PDOWN_WAIT (HZ / 5)
181 struct tenxpress_phy_data
{
182 enum efx_loopback_mode loopback_mode
;
183 enum efx_phy_mode phy_mode
;
187 static ssize_t
show_phy_short_reach(struct device
*dev
,
188 struct device_attribute
*attr
, char *buf
)
190 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
193 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBT_TXPWR
);
194 return sprintf(buf
, "%d\n", !!(reg
& MDIO_PMA_10GBT_TXPWR_SHORT
));
197 static ssize_t
set_phy_short_reach(struct device
*dev
,
198 struct device_attribute
*attr
,
199 const char *buf
, size_t count
)
201 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
205 if (efx
->state
!= STATE_RUNNING
) {
208 efx_mdio_set_flag(efx
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBT_TXPWR
,
209 MDIO_PMA_10GBT_TXPWR_SHORT
,
210 count
!= 0 && *buf
!= '0');
211 rc
= efx_reconfigure_port(efx
);
215 return rc
< 0 ? rc
: (ssize_t
)count
;
218 static DEVICE_ATTR(phy_short_reach
, 0644, show_phy_short_reach
,
219 set_phy_short_reach
);
221 int sft9001_wait_boot(struct efx_nic
*efx
)
223 unsigned long timeout
= jiffies
+ HZ
+ 1;
227 boot_stat
= efx_mdio_read(efx
, MDIO_MMD_PCS
,
228 PCS_BOOT_STATUS_REG
);
229 if (boot_stat
>= 0) {
230 EFX_LOG(efx
, "PHY boot status = %#x\n", boot_stat
);
232 ((1 << PCS_BOOT_FATAL_ERROR_LBN
) |
233 (3 << PCS_BOOT_PROGRESS_LBN
) |
234 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
) |
235 (1 << PCS_BOOT_CODE_STARTED_LBN
))) {
236 case ((1 << PCS_BOOT_FATAL_ERROR_LBN
) |
237 (PCS_BOOT_PROGRESS_CHECKSUM
<<
238 PCS_BOOT_PROGRESS_LBN
)):
239 case ((1 << PCS_BOOT_FATAL_ERROR_LBN
) |
240 (PCS_BOOT_PROGRESS_INIT
<<
241 PCS_BOOT_PROGRESS_LBN
) |
242 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
)):
244 case ((PCS_BOOT_PROGRESS_WAIT_MDIO
<<
245 PCS_BOOT_PROGRESS_LBN
) |
246 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
)):
247 return (efx
->phy_mode
& PHY_MODE_SPECIAL
) ?
249 case ((PCS_BOOT_PROGRESS_JUMP
<<
250 PCS_BOOT_PROGRESS_LBN
) |
251 (1 << PCS_BOOT_CODE_STARTED_LBN
)):
252 case ((PCS_BOOT_PROGRESS_JUMP
<<
253 PCS_BOOT_PROGRESS_LBN
) |
254 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
) |
255 (1 << PCS_BOOT_CODE_STARTED_LBN
)):
256 return (efx
->phy_mode
& PHY_MODE_SPECIAL
) ?
259 if (boot_stat
& (1 << PCS_BOOT_FATAL_ERROR_LBN
))
265 if (time_after_eq(jiffies
, timeout
))
272 static int tenxpress_init(struct efx_nic
*efx
)
276 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
277 /* Enable 312.5 MHz clock */
278 efx_mdio_write(efx
, MDIO_MMD_PCS
, PCS_TEST_SELECT_REG
,
281 /* Enable 312.5 MHz clock and GMII */
282 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
);
283 reg
|= ((1 << PMA_PMD_EXT_GMII_EN_LBN
) |
284 (1 << PMA_PMD_EXT_CLK_OUT_LBN
) |
285 (1 << PMA_PMD_EXT_CLK312_LBN
) |
286 (1 << PMA_PMD_EXT_ROBUST_LBN
));
288 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
, reg
);
289 efx_mdio_set_flag(efx
, MDIO_MMD_C22EXT
,
290 GPHY_XCONTROL_REG
, 1 << GPHY_ISOLATE_LBN
,
294 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
295 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
296 efx_mdio_set_flag(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_LED_CTRL_REG
,
297 1 << PMA_PMA_LED_ACTIVITY_LBN
, true);
298 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_LED_OVERR_REG
,
299 SFX7101_PMA_PMD_LED_DEFAULT
);
305 static int tenxpress_phy_probe(struct efx_nic
*efx
)
307 struct tenxpress_phy_data
*phy_data
;
310 /* Allocate phy private storage */
311 phy_data
= kzalloc(sizeof(*phy_data
), GFP_KERNEL
);
314 efx
->phy_data
= phy_data
;
315 phy_data
->phy_mode
= efx
->phy_mode
;
317 /* Create any special files */
318 if (efx
->phy_type
== PHY_TYPE_SFT9001B
) {
319 rc
= device_create_file(&efx
->pci_dev
->dev
,
320 &dev_attr_phy_short_reach
);
325 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
326 efx
->mdio
.mmds
= TENXPRESS_REQUIRED_DEVS
;
327 efx
->mdio
.mode_support
= MDIO_SUPPORTS_C45
;
329 efx
->loopback_modes
= SFX7101_LOOPBACKS
| FALCON_XMAC_LOOPBACKS
;
331 efx
->link_advertising
= (ADVERTISED_TP
| ADVERTISED_Autoneg
|
332 ADVERTISED_10000baseT_Full
);
334 efx
->mdio
.mmds
= TENXPRESS_REQUIRED_DEVS
;
335 efx
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
337 efx
->loopback_modes
= (SFT9001_LOOPBACKS
|
338 FALCON_XMAC_LOOPBACKS
|
339 FALCON_GMAC_LOOPBACKS
);
341 efx
->link_advertising
= (ADVERTISED_TP
| ADVERTISED_Autoneg
|
342 ADVERTISED_10000baseT_Full
|
343 ADVERTISED_1000baseT_Full
|
344 ADVERTISED_100baseT_Full
);
350 kfree(efx
->phy_data
);
351 efx
->phy_data
= NULL
;
355 static int tenxpress_phy_init(struct efx_nic
*efx
)
359 falcon_board(efx
)->type
->init_phy(efx
);
361 if (!(efx
->phy_mode
& PHY_MODE_SPECIAL
)) {
362 if (efx
->phy_type
== PHY_TYPE_SFT9001A
) {
364 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
365 PMA_PMD_XCONTROL_REG
);
366 reg
|= (1 << PMA_PMD_EXT_SSR_LBN
);
367 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
,
368 PMA_PMD_XCONTROL_REG
, reg
);
372 rc
= efx_mdio_wait_reset_mmds(efx
, TENXPRESS_REQUIRED_DEVS
);
376 rc
= efx_mdio_check_mmds(efx
, TENXPRESS_REQUIRED_DEVS
, 0);
381 rc
= tenxpress_init(efx
);
385 /* Reinitialise flow control settings */
386 efx_link_set_wanted_fc(efx
, efx
->wanted_fc
);
387 efx_mdio_an_reconfigure(efx
);
389 schedule_timeout_uninterruptible(HZ
/ 5); /* 200ms */
391 /* Let XGXS and SerDes out of reset */
392 falcon_reset_xaui(efx
);
397 /* Perform a "special software reset" on the PHY. The caller is
398 * responsible for saving and restoring the PHY hardware registers
399 * properly, and masking/unmasking LASI */
400 static int tenxpress_special_reset(struct efx_nic
*efx
)
404 /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
405 * a special software reset can glitch the XGMAC sufficiently for stats
406 * requests to fail. */
407 falcon_stop_nic_stats(efx
);
410 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
);
411 reg
|= (1 << PMA_PMD_EXT_SSR_LBN
);
412 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
, reg
);
416 /* Wait for the blocks to come out of reset */
417 rc
= efx_mdio_wait_reset_mmds(efx
, TENXPRESS_REQUIRED_DEVS
);
421 /* Try and reconfigure the device */
422 rc
= tenxpress_init(efx
);
426 /* Wait for the XGXS state machine to churn */
429 falcon_start_nic_stats(efx
);
433 static void sfx7101_check_bad_lp(struct efx_nic
*efx
, bool link_ok
)
435 struct tenxpress_phy_data
*pd
= efx
->phy_data
;
442 /* Check that AN has started but not completed. */
443 reg
= efx_mdio_read(efx
, MDIO_MMD_AN
, MDIO_STAT1
);
444 if (!(reg
& MDIO_AN_STAT1_LPABLE
))
445 return; /* LP status is unknown */
446 bad_lp
= !(reg
& MDIO_AN_STAT1_COMPLETE
);
451 /* Nothing to do if all is well and was previously so. */
452 if (!pd
->bad_lp_tries
)
455 /* Use the RX (red) LED as an error indicator once we've seen AN
456 * failure several times in a row, and also log a message. */
457 if (!bad_lp
|| pd
->bad_lp_tries
== MAX_BAD_LP_TRIES
) {
458 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
459 PMA_PMD_LED_OVERR_REG
);
460 reg
&= ~(PMA_PMD_LED_MASK
<< PMA_PMD_LED_RX_LBN
);
462 reg
|= PMA_PMD_LED_OFF
<< PMA_PMD_LED_RX_LBN
;
464 reg
|= PMA_PMD_LED_FLASH
<< PMA_PMD_LED_RX_LBN
;
465 EFX_ERR(efx
, "appears to be plugged into a port"
466 " that is not 10GBASE-T capable. The PHY"
467 " supports 10GBASE-T ONLY, so no link can"
468 " be established\n");
470 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
,
471 PMA_PMD_LED_OVERR_REG
, reg
);
472 pd
->bad_lp_tries
= bad_lp
;
476 static bool sfx7101_link_ok(struct efx_nic
*efx
)
478 return efx_mdio_links_ok(efx
,
484 static bool sft9001_link_ok(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
)
488 if (efx_phy_mode_disabled(efx
->phy_mode
))
490 else if (efx
->loopback_mode
== LOOPBACK_GPHY
)
492 else if (efx
->loopback_mode
)
493 return efx_mdio_links_ok(efx
,
497 /* We must use the same definition of link state as LASI,
498 * otherwise we can miss a link state transition
500 if (ecmd
->speed
== 10000) {
501 reg
= efx_mdio_read(efx
, MDIO_MMD_PCS
, MDIO_PCS_10GBRT_STAT1
);
502 return reg
& MDIO_PCS_10GBRT_STAT1_BLKLK
;
504 reg
= efx_mdio_read(efx
, MDIO_MMD_C22EXT
, C22EXT_STATUS_REG
);
505 return reg
& (1 << C22EXT_STATUS_LINK_LBN
);
509 static void tenxpress_ext_loopback(struct efx_nic
*efx
)
511 efx_mdio_set_flag(efx
, MDIO_MMD_PHYXS
, PHYXS_TEST1
,
512 1 << LOOPBACK_NEAR_LBN
,
513 efx
->loopback_mode
== LOOPBACK_PHYXS
);
514 if (efx
->phy_type
!= PHY_TYPE_SFX7101
)
515 efx_mdio_set_flag(efx
, MDIO_MMD_C22EXT
, GPHY_XCONTROL_REG
,
516 1 << GPHY_LOOPBACK_NEAR_LBN
,
517 efx
->loopback_mode
== LOOPBACK_GPHY
);
520 static void tenxpress_low_power(struct efx_nic
*efx
)
522 if (efx
->phy_type
== PHY_TYPE_SFX7101
)
523 efx_mdio_set_mmds_lpower(
524 efx
, !!(efx
->phy_mode
& PHY_MODE_LOW_POWER
),
525 TENXPRESS_REQUIRED_DEVS
);
528 efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
,
529 1 << PMA_PMD_EXT_LPOWER_LBN
,
530 !!(efx
->phy_mode
& PHY_MODE_LOW_POWER
));
533 static int tenxpress_phy_reconfigure(struct efx_nic
*efx
)
535 struct tenxpress_phy_data
*phy_data
= efx
->phy_data
;
536 bool phy_mode_change
, loop_reset
;
538 if (efx
->phy_mode
& (PHY_MODE_OFF
| PHY_MODE_SPECIAL
)) {
539 phy_data
->phy_mode
= efx
->phy_mode
;
543 phy_mode_change
= (efx
->phy_mode
== PHY_MODE_NORMAL
&&
544 phy_data
->phy_mode
!= PHY_MODE_NORMAL
);
545 loop_reset
= (LOOPBACK_OUT_OF(phy_data
, efx
, LOOPBACKS_EXTERNAL(efx
)) ||
546 LOOPBACK_CHANGED(phy_data
, efx
, 1 << LOOPBACK_GPHY
));
548 if (loop_reset
|| phy_mode_change
) {
549 tenxpress_special_reset(efx
);
551 /* Reset XAUI if we were in 10G, and are staying
552 * in 10G. If we're moving into and out of 10G
553 * then xaui will be reset anyway */
555 falcon_reset_xaui(efx
);
558 tenxpress_low_power(efx
);
559 efx_mdio_transmit_disable(efx
);
560 efx_mdio_phy_reconfigure(efx
);
561 tenxpress_ext_loopback(efx
);
562 efx_mdio_an_reconfigure(efx
);
564 phy_data
->loopback_mode
= efx
->loopback_mode
;
565 phy_data
->phy_mode
= efx
->phy_mode
;
571 tenxpress_get_settings(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
);
573 /* Poll for link state changes */
574 static bool tenxpress_phy_poll(struct efx_nic
*efx
)
576 struct efx_link_state old_state
= efx
->link_state
;
578 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
579 efx
->link_state
.up
= sfx7101_link_ok(efx
);
580 efx
->link_state
.speed
= 10000;
581 efx
->link_state
.fd
= true;
582 efx
->link_state
.fc
= efx_mdio_get_pause(efx
);
584 sfx7101_check_bad_lp(efx
, efx
->link_state
.up
);
586 struct ethtool_cmd ecmd
;
588 /* Check the LASI alarm first */
589 if (efx
->loopback_mode
== LOOPBACK_NONE
&&
590 !(efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, MDIO_PMA_LASI_STAT
) &
591 MDIO_PMA_LASI_LSALARM
))
594 tenxpress_get_settings(efx
, &ecmd
);
596 efx
->link_state
.up
= sft9001_link_ok(efx
, &ecmd
);
597 efx
->link_state
.speed
= ecmd
.speed
;
598 efx
->link_state
.fd
= (ecmd
.duplex
== DUPLEX_FULL
);
599 efx
->link_state
.fc
= efx_mdio_get_pause(efx
);
602 return !efx_link_state_equal(&efx
->link_state
, &old_state
);
605 static void sfx7101_phy_fini(struct efx_nic
*efx
)
609 /* Power down the LNPGA */
610 reg
= (1 << PMA_PMD_LNPGA_POWERDOWN_LBN
);
611 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
, reg
);
613 /* Waiting here ensures that the board fini, which can turn
614 * off the power to the PHY, won't get run until the LNPGA
615 * powerdown has been given long enough to complete. */
616 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT
); /* 200 ms */
619 static void tenxpress_phy_remove(struct efx_nic
*efx
)
621 if (efx
->phy_type
== PHY_TYPE_SFT9001B
)
622 device_remove_file(&efx
->pci_dev
->dev
,
623 &dev_attr_phy_short_reach
);
625 kfree(efx
->phy_data
);
626 efx
->phy_data
= NULL
;
630 /* Override the RX, TX and link LEDs */
631 void tenxpress_set_id_led(struct efx_nic
*efx
, enum efx_led_mode mode
)
637 reg
= (PMA_PMD_LED_OFF
<< PMA_PMD_LED_TX_LBN
) |
638 (PMA_PMD_LED_OFF
<< PMA_PMD_LED_RX_LBN
) |
639 (PMA_PMD_LED_OFF
<< PMA_PMD_LED_LINK_LBN
);
642 reg
= (PMA_PMD_LED_ON
<< PMA_PMD_LED_TX_LBN
) |
643 (PMA_PMD_LED_ON
<< PMA_PMD_LED_RX_LBN
) |
644 (PMA_PMD_LED_ON
<< PMA_PMD_LED_LINK_LBN
);
647 if (efx
->phy_type
== PHY_TYPE_SFX7101
)
648 reg
= SFX7101_PMA_PMD_LED_DEFAULT
;
650 reg
= SFT9001_PMA_PMD_LED_DEFAULT
;
654 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_LED_OVERR_REG
, reg
);
657 static const char *const sfx7101_test_names
[] = {
661 static const char *sfx7101_test_name(struct efx_nic
*efx
, unsigned int index
)
663 if (index
< ARRAY_SIZE(sfx7101_test_names
))
664 return sfx7101_test_names
[index
];
669 sfx7101_run_tests(struct efx_nic
*efx
, int *results
, unsigned flags
)
673 if (!(flags
& ETH_TEST_FL_OFFLINE
))
676 /* BIST is automatically run after a special software reset */
677 rc
= tenxpress_special_reset(efx
);
678 results
[0] = rc
? -1 : 1;
680 efx_mdio_an_reconfigure(efx
);
685 static const char *const sft9001_test_names
[] = {
687 "cable.pairA.status",
688 "cable.pairB.status",
689 "cable.pairC.status",
690 "cable.pairD.status",
691 "cable.pairA.length",
692 "cable.pairB.length",
693 "cable.pairC.length",
694 "cable.pairD.length",
697 static const char *sft9001_test_name(struct efx_nic
*efx
, unsigned int index
)
699 if (index
< ARRAY_SIZE(sft9001_test_names
))
700 return sft9001_test_names
[index
];
704 static int sft9001_run_tests(struct efx_nic
*efx
, int *results
, unsigned flags
)
706 int rc
= 0, rc2
, i
, ctrl_reg
, res_reg
;
708 /* Initialise cable diagnostic results to unknown failure */
709 for (i
= 1; i
< 9; ++i
)
712 /* Run cable diagnostics; wait up to 5 seconds for them to complete.
713 * A cable fault is not a self-test failure, but a timeout is. */
714 ctrl_reg
= ((1 << CDIAG_CTRL_IMMED_LBN
) |
715 (CDIAG_CTRL_LEN_METRES
<< CDIAG_CTRL_LEN_UNIT_LBN
));
716 if (flags
& ETH_TEST_FL_OFFLINE
) {
717 /* Break the link in order to run full diagnostics. We
718 * must reset the PHY to resume normal service. */
719 ctrl_reg
|= (1 << CDIAG_CTRL_BRK_LINK_LBN
);
721 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_CDIAG_CTRL_REG
,
724 while (efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_CDIAG_CTRL_REG
) &
725 (1 << CDIAG_CTRL_IN_PROG_LBN
)) {
732 res_reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_CDIAG_RES_REG
);
733 for (i
= 0; i
< 4; i
++) {
735 (res_reg
>> (CDIAG_RES_A_LBN
- i
* CDIAG_RES_WIDTH
))
736 & ((1 << CDIAG_RES_WIDTH
) - 1);
737 int len_reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
738 PMA_PMD_CDIAG_LEN_REG
+ i
);
739 if (pair_res
== CDIAG_RES_OK
)
741 else if (pair_res
== CDIAG_RES_INVALID
)
744 results
[1 + i
] = -pair_res
;
745 if (pair_res
!= CDIAG_RES_INVALID
&&
746 pair_res
!= CDIAG_RES_OPEN
&&
748 results
[5 + i
] = len_reg
;
752 if (flags
& ETH_TEST_FL_OFFLINE
) {
753 /* Reset, running the BIST and then resuming normal service. */
754 rc2
= tenxpress_special_reset(efx
);
755 results
[0] = rc2
? -1 : 1;
759 efx_mdio_an_reconfigure(efx
);
766 tenxpress_get_settings(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
)
768 u32 adv
= 0, lpa
= 0;
771 if (efx
->phy_type
!= PHY_TYPE_SFX7101
) {
772 reg
= efx_mdio_read(efx
, MDIO_MMD_C22EXT
, C22EXT_MSTSLV_CTRL
);
773 if (reg
& (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN
))
774 adv
|= ADVERTISED_1000baseT_Full
;
775 reg
= efx_mdio_read(efx
, MDIO_MMD_C22EXT
, C22EXT_MSTSLV_STATUS
);
776 if (reg
& (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN
))
777 lpa
|= ADVERTISED_1000baseT_Half
;
778 if (reg
& (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN
))
779 lpa
|= ADVERTISED_1000baseT_Full
;
781 reg
= efx_mdio_read(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_CTRL
);
782 if (reg
& MDIO_AN_10GBT_CTRL_ADV10G
)
783 adv
|= ADVERTISED_10000baseT_Full
;
784 reg
= efx_mdio_read(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_STAT
);
785 if (reg
& MDIO_AN_10GBT_STAT_LP10G
)
786 lpa
|= ADVERTISED_10000baseT_Full
;
788 mdio45_ethtool_gset_npage(&efx
->mdio
, ecmd
, adv
, lpa
);
790 if (efx
->phy_type
!= PHY_TYPE_SFX7101
) {
791 ecmd
->supported
|= (SUPPORTED_100baseT_Full
|
792 SUPPORTED_1000baseT_Full
);
793 if (ecmd
->speed
!= SPEED_10000
) {
795 (efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
796 PMA_PMD_XSTATUS_REG
) &
797 (1 << PMA_PMD_XSTAT_MDIX_LBN
))
798 ? ETH_TP_MDI_X
: ETH_TP_MDI
;
802 /* In loopback, the PHY automatically brings up the correct interface,
803 * but doesn't advertise the correct speed. So override it */
804 if (efx
->loopback_mode
== LOOPBACK_GPHY
)
805 ecmd
->speed
= SPEED_1000
;
806 else if (LOOPBACK_EXTERNAL(efx
))
807 ecmd
->speed
= SPEED_10000
;
810 static int tenxpress_set_settings(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
)
815 return efx_mdio_set_settings(efx
, ecmd
);
818 static void sfx7101_set_npage_adv(struct efx_nic
*efx
, u32 advertising
)
820 efx_mdio_set_flag(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_CTRL
,
821 MDIO_AN_10GBT_CTRL_ADV10G
,
822 advertising
& ADVERTISED_10000baseT_Full
);
825 static void sft9001_set_npage_adv(struct efx_nic
*efx
, u32 advertising
)
827 efx_mdio_set_flag(efx
, MDIO_MMD_C22EXT
, C22EXT_MSTSLV_CTRL
,
828 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN
,
829 advertising
& ADVERTISED_1000baseT_Full
);
830 efx_mdio_set_flag(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_CTRL
,
831 MDIO_AN_10GBT_CTRL_ADV10G
,
832 advertising
& ADVERTISED_10000baseT_Full
);
835 struct efx_phy_operations falcon_sfx7101_phy_ops
= {
836 .probe
= tenxpress_phy_probe
,
837 .init
= tenxpress_phy_init
,
838 .reconfigure
= tenxpress_phy_reconfigure
,
839 .poll
= tenxpress_phy_poll
,
840 .fini
= sfx7101_phy_fini
,
841 .remove
= tenxpress_phy_remove
,
842 .get_settings
= tenxpress_get_settings
,
843 .set_settings
= tenxpress_set_settings
,
844 .set_npage_adv
= sfx7101_set_npage_adv
,
845 .test_alive
= efx_mdio_test_alive
,
846 .test_name
= sfx7101_test_name
,
847 .run_tests
= sfx7101_run_tests
,
850 struct efx_phy_operations falcon_sft9001_phy_ops
= {
851 .probe
= tenxpress_phy_probe
,
852 .init
= tenxpress_phy_init
,
853 .reconfigure
= tenxpress_phy_reconfigure
,
854 .poll
= tenxpress_phy_poll
,
855 .fini
= efx_port_dummy_op_void
,
856 .remove
= tenxpress_phy_remove
,
857 .get_settings
= tenxpress_get_settings
,
858 .set_settings
= tenxpress_set_settings
,
859 .set_npage_adv
= sft9001_set_npage_adv
,
860 .test_alive
= efx_mdio_test_alive
,
861 .test_name
= sft9001_test_name
,
862 .run_tests
= sft9001_run_tests
,