2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/slab.h>
35 #include <linux/ethtool.h>
36 #include <asm/cacheflush.h>
40 #define SH_ETH_DEF_MSG_ENABLE \
46 /* There is CPU dependent code */
47 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
48 #define SH_ETH_RESET_DEFAULT 1
49 static void sh_eth_set_duplex(struct net_device
*ndev
)
51 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
53 if (mdp
->duplex
) /* Full */
54 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
56 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
59 static void sh_eth_set_rate(struct net_device
*ndev
)
61 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
65 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_RTM
, ECMR
);
67 case 100:/* 100BASE */
68 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_RTM
, ECMR
);
76 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
77 .set_duplex
= sh_eth_set_duplex
,
78 .set_rate
= sh_eth_set_rate
,
80 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
81 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
82 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x01ff009f,
84 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
85 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
86 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
87 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
94 .rpadir_value
= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
96 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
97 #define SH_ETH_HAS_BOTH_MODULES 1
98 #define SH_ETH_HAS_TSU 1
99 static void sh_eth_set_duplex(struct net_device
*ndev
)
101 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
103 if (mdp
->duplex
) /* Full */
104 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
106 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
109 static void sh_eth_set_rate(struct net_device
*ndev
)
111 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
113 switch (mdp
->speed
) {
114 case 10: /* 10BASE */
115 sh_eth_write(ndev
, 0, RTRATE
);
117 case 100:/* 100BASE */
118 sh_eth_write(ndev
, 1, RTRATE
);
126 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
127 .set_duplex
= sh_eth_set_duplex
,
128 .set_rate
= sh_eth_set_rate
,
130 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
131 .rmcr_value
= 0x00000001,
133 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
134 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
135 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
136 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
145 #define SH_GIGA_ETH_BASE 0xfee00000
146 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
147 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
148 static void sh_eth_chip_reset_giga(struct net_device
*ndev
)
151 unsigned long mahr
[2], malr
[2];
153 /* save MAHR and MALR */
154 for (i
= 0; i
< 2; i
++) {
155 malr
[i
] = readl(GIGA_MALR(i
));
156 mahr
[i
] = readl(GIGA_MAHR(i
));
160 writel(ARSTR_ARSTR
, SH_GIGA_ETH_BASE
+ 0x1800);
163 /* restore MAHR and MALR */
164 for (i
= 0; i
< 2; i
++) {
165 writel(malr
[i
], GIGA_MALR(i
));
166 writel(mahr
[i
], GIGA_MAHR(i
));
170 static int sh_eth_is_gether(struct sh_eth_private
*mdp
);
171 static void sh_eth_reset(struct net_device
*ndev
)
173 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
176 if (sh_eth_is_gether(mdp
)) {
177 sh_eth_write(ndev
, 0x03, EDSR
);
178 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
,
181 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
187 printk(KERN_ERR
"Device reset fail\n");
190 sh_eth_write(ndev
, 0x0, TDLAR
);
191 sh_eth_write(ndev
, 0x0, TDFAR
);
192 sh_eth_write(ndev
, 0x0, TDFXR
);
193 sh_eth_write(ndev
, 0x0, TDFFR
);
194 sh_eth_write(ndev
, 0x0, RDLAR
);
195 sh_eth_write(ndev
, 0x0, RDFAR
);
196 sh_eth_write(ndev
, 0x0, RDFXR
);
197 sh_eth_write(ndev
, 0x0, RDFFR
);
199 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
,
202 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
,
207 static void sh_eth_set_duplex_giga(struct net_device
*ndev
)
209 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
211 if (mdp
->duplex
) /* Full */
212 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
214 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
217 static void sh_eth_set_rate_giga(struct net_device
*ndev
)
219 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
221 switch (mdp
->speed
) {
222 case 10: /* 10BASE */
223 sh_eth_write(ndev
, 0x00000000, GECMR
);
225 case 100:/* 100BASE */
226 sh_eth_write(ndev
, 0x00000010, GECMR
);
228 case 1000: /* 1000BASE */
229 sh_eth_write(ndev
, 0x00000020, GECMR
);
236 /* SH7757(GETHERC) */
237 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga
= {
238 .chip_reset
= sh_eth_chip_reset_giga
,
239 .set_duplex
= sh_eth_set_duplex_giga
,
240 .set_rate
= sh_eth_set_rate_giga
,
242 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
243 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
244 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
246 .tx_check
= EESR_TC1
| EESR_FTC
,
247 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
248 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
250 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
252 .fdr_value
= 0x0000072f,
253 .rmcr_value
= 0x00000001,
261 .rpadir_value
= 2 << 16,
266 static struct sh_eth_cpu_data
*sh_eth_get_cpu_data(struct sh_eth_private
*mdp
)
268 if (sh_eth_is_gether(mdp
))
269 return &sh_eth_my_cpu_data_giga
;
271 return &sh_eth_my_cpu_data
;
274 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
275 #define SH_ETH_HAS_TSU 1
276 static void sh_eth_chip_reset(struct net_device
*ndev
)
278 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
281 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
285 static void sh_eth_reset(struct net_device
*ndev
)
289 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
290 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
, EDMR
);
292 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
298 printk(KERN_ERR
"Device reset fail\n");
301 sh_eth_write(ndev
, 0x0, TDLAR
);
302 sh_eth_write(ndev
, 0x0, TDFAR
);
303 sh_eth_write(ndev
, 0x0, TDFXR
);
304 sh_eth_write(ndev
, 0x0, TDFFR
);
305 sh_eth_write(ndev
, 0x0, RDLAR
);
306 sh_eth_write(ndev
, 0x0, RDFAR
);
307 sh_eth_write(ndev
, 0x0, RDFXR
);
308 sh_eth_write(ndev
, 0x0, RDFFR
);
311 static void sh_eth_set_duplex(struct net_device
*ndev
)
313 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
315 if (mdp
->duplex
) /* Full */
316 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
318 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
321 static void sh_eth_set_rate(struct net_device
*ndev
)
323 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
325 switch (mdp
->speed
) {
326 case 10: /* 10BASE */
327 sh_eth_write(ndev
, GECMR_10
, GECMR
);
329 case 100:/* 100BASE */
330 sh_eth_write(ndev
, GECMR_100
, GECMR
);
332 case 1000: /* 1000BASE */
333 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
341 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
342 .chip_reset
= sh_eth_chip_reset
,
343 .set_duplex
= sh_eth_set_duplex
,
344 .set_rate
= sh_eth_set_rate
,
346 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
347 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
348 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
350 .tx_check
= EESR_TC1
| EESR_FTC
,
351 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
352 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
354 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
367 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
368 #define SH_ETH_RESET_DEFAULT 1
369 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
370 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
377 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
378 #define SH_ETH_RESET_DEFAULT 1
379 #define SH_ETH_HAS_TSU 1
380 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
381 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
386 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
389 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
391 if (!cd
->ecsipr_value
)
392 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
394 if (!cd
->fcftr_value
)
395 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
| \
396 DEFAULT_FIFO_F_D_RFD
;
399 cd
->fdr_value
= DEFAULT_FDR_INIT
;
402 cd
->rmcr_value
= DEFAULT_RMCR_VALUE
;
405 cd
->tx_check
= DEFAULT_TX_CHECK
;
407 if (!cd
->eesr_err_check
)
408 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
410 if (!cd
->tx_error_check
)
411 cd
->tx_error_check
= DEFAULT_TX_ERROR_CHECK
;
414 #if defined(SH_ETH_RESET_DEFAULT)
416 static void sh_eth_reset(struct net_device
*ndev
)
418 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
, EDMR
);
420 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
, EDMR
);
424 #if defined(CONFIG_CPU_SH4)
425 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
429 reserve
= SH4_SKB_RX_ALIGN
- ((u32
)skb
->data
& (SH4_SKB_RX_ALIGN
- 1));
431 skb_reserve(skb
, reserve
);
434 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
436 skb_reserve(skb
, SH2_SH3_SKB_RX_ALIGN
);
441 /* CPU <-> EDMAC endian convert */
442 static inline __u32
cpu_to_edmac(struct sh_eth_private
*mdp
, u32 x
)
444 switch (mdp
->edmac_endian
) {
445 case EDMAC_LITTLE_ENDIAN
:
446 return cpu_to_le32(x
);
447 case EDMAC_BIG_ENDIAN
:
448 return cpu_to_be32(x
);
453 static inline __u32
edmac_to_cpu(struct sh_eth_private
*mdp
, u32 x
)
455 switch (mdp
->edmac_endian
) {
456 case EDMAC_LITTLE_ENDIAN
:
457 return le32_to_cpu(x
);
458 case EDMAC_BIG_ENDIAN
:
459 return be32_to_cpu(x
);
465 * Program the hardware MAC address from dev->dev_addr.
467 static void update_mac_address(struct net_device
*ndev
)
470 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
471 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
473 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
477 * Get MAC address from SuperH MAC address register
479 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
480 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
481 * When you want use this device, you must set MAC address in bootloader.
484 static void read_mac_address(struct net_device
*ndev
, unsigned char *mac
)
486 if (mac
[0] || mac
[1] || mac
[2] || mac
[3] || mac
[4] || mac
[5]) {
487 memcpy(ndev
->dev_addr
, mac
, 6);
489 ndev
->dev_addr
[0] = (sh_eth_read(ndev
, MAHR
) >> 24);
490 ndev
->dev_addr
[1] = (sh_eth_read(ndev
, MAHR
) >> 16) & 0xFF;
491 ndev
->dev_addr
[2] = (sh_eth_read(ndev
, MAHR
) >> 8) & 0xFF;
492 ndev
->dev_addr
[3] = (sh_eth_read(ndev
, MAHR
) & 0xFF);
493 ndev
->dev_addr
[4] = (sh_eth_read(ndev
, MALR
) >> 8) & 0xFF;
494 ndev
->dev_addr
[5] = (sh_eth_read(ndev
, MALR
) & 0xFF);
498 static int sh_eth_is_gether(struct sh_eth_private
*mdp
)
500 if (mdp
->reg_offset
== sh_eth_offset_gigabit
)
506 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private
*mdp
)
508 if (sh_eth_is_gether(mdp
))
509 return EDTRR_TRNS_GETHER
;
511 return EDTRR_TRNS_ETHER
;
515 struct mdiobb_ctrl ctrl
;
517 u32 mmd_msk
;/* MMD */
524 static void bb_set(u32 addr
, u32 msk
)
526 writel(readl(addr
) | msk
, addr
);
530 static void bb_clr(u32 addr
, u32 msk
)
532 writel((readl(addr
) & ~msk
), addr
);
536 static int bb_read(u32 addr
, u32 msk
)
538 return (readl(addr
) & msk
) != 0;
541 /* Data I/O pin control */
542 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
544 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
546 bb_set(bitbang
->addr
, bitbang
->mmd_msk
);
548 bb_clr(bitbang
->addr
, bitbang
->mmd_msk
);
552 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
554 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
557 bb_set(bitbang
->addr
, bitbang
->mdo_msk
);
559 bb_clr(bitbang
->addr
, bitbang
->mdo_msk
);
563 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
565 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
566 return bb_read(bitbang
->addr
, bitbang
->mdi_msk
);
569 /* MDC pin control */
570 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
572 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
575 bb_set(bitbang
->addr
, bitbang
->mdc_msk
);
577 bb_clr(bitbang
->addr
, bitbang
->mdc_msk
);
580 /* mdio bus control struct */
581 static struct mdiobb_ops bb_ops
= {
582 .owner
= THIS_MODULE
,
583 .set_mdc
= sh_mdc_ctrl
,
584 .set_mdio_dir
= sh_mmd_ctrl
,
585 .set_mdio_data
= sh_set_mdio
,
586 .get_mdio_data
= sh_get_mdio
,
589 /* free skb and descriptor buffer */
590 static void sh_eth_ring_free(struct net_device
*ndev
)
592 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
595 /* Free Rx skb ringbuffer */
596 if (mdp
->rx_skbuff
) {
597 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
598 if (mdp
->rx_skbuff
[i
])
599 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
602 kfree(mdp
->rx_skbuff
);
604 /* Free Tx skb ringbuffer */
605 if (mdp
->tx_skbuff
) {
606 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
607 if (mdp
->tx_skbuff
[i
])
608 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
611 kfree(mdp
->tx_skbuff
);
614 /* format skb and descriptor buffer */
615 static void sh_eth_ring_format(struct net_device
*ndev
)
617 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
620 struct sh_eth_rxdesc
*rxdesc
= NULL
;
621 struct sh_eth_txdesc
*txdesc
= NULL
;
622 int rx_ringsize
= sizeof(*rxdesc
) * RX_RING_SIZE
;
623 int tx_ringsize
= sizeof(*txdesc
) * TX_RING_SIZE
;
625 mdp
->cur_rx
= mdp
->cur_tx
= 0;
626 mdp
->dirty_rx
= mdp
->dirty_tx
= 0;
628 memset(mdp
->rx_ring
, 0, rx_ringsize
);
630 /* build Rx ring buffer */
631 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
633 mdp
->rx_skbuff
[i
] = NULL
;
634 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
635 mdp
->rx_skbuff
[i
] = skb
;
638 dma_map_single(&ndev
->dev
, skb
->tail
, mdp
->rx_buf_sz
,
640 skb
->dev
= ndev
; /* Mark as being used by this device. */
641 sh_eth_set_receive_align(skb
);
644 rxdesc
= &mdp
->rx_ring
[i
];
645 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
646 rxdesc
->status
= cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
648 /* The size of the buffer is 16 byte boundary. */
649 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
650 /* Rx descriptor address set */
652 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDLAR
);
653 if (sh_eth_is_gether(mdp
))
654 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDFAR
);
658 mdp
->dirty_rx
= (u32
) (i
- RX_RING_SIZE
);
660 /* Mark the last entry as wrapping the ring. */
661 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RDEL
);
663 memset(mdp
->tx_ring
, 0, tx_ringsize
);
665 /* build Tx ring buffer */
666 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
667 mdp
->tx_skbuff
[i
] = NULL
;
668 txdesc
= &mdp
->tx_ring
[i
];
669 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
670 txdesc
->buffer_length
= 0;
672 /* Tx descriptor address set */
673 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDLAR
);
674 if (sh_eth_is_gether(mdp
))
675 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDFAR
);
679 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
682 /* Get skb and descriptor buffer */
683 static int sh_eth_ring_init(struct net_device
*ndev
)
685 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
686 int rx_ringsize
, tx_ringsize
, ret
= 0;
689 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
690 * card needs room to do 8 byte alignment, +2 so we can reserve
691 * the first 2 bytes, and +16 gets room for the status word from the
694 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
695 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
697 mdp
->rx_buf_sz
+= NET_IP_ALIGN
;
699 /* Allocate RX and TX skb rings */
700 mdp
->rx_skbuff
= kmalloc(sizeof(*mdp
->rx_skbuff
) * RX_RING_SIZE
,
702 if (!mdp
->rx_skbuff
) {
703 dev_err(&ndev
->dev
, "Cannot allocate Rx skb\n");
708 mdp
->tx_skbuff
= kmalloc(sizeof(*mdp
->tx_skbuff
) * TX_RING_SIZE
,
710 if (!mdp
->tx_skbuff
) {
711 dev_err(&ndev
->dev
, "Cannot allocate Tx skb\n");
716 /* Allocate all Rx descriptors. */
717 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
718 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
722 dev_err(&ndev
->dev
, "Cannot allocate Rx Ring (size %d bytes)\n",
730 /* Allocate all Tx descriptors. */
731 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
732 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
735 dev_err(&ndev
->dev
, "Cannot allocate Tx Ring (size %d bytes)\n",
743 /* free DMA buffer */
744 dma_free_coherent(NULL
, rx_ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
747 /* Free Rx and Tx skb ring buffer */
748 sh_eth_ring_free(ndev
);
753 static int sh_eth_dev_init(struct net_device
*ndev
)
756 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
757 u_int32_t rx_int_var
, tx_int_var
;
763 /* Descriptor format */
764 sh_eth_ring_format(ndev
);
766 sh_eth_write(ndev
, mdp
->cd
->rpadir_value
, RPADIR
);
768 /* all sh_eth int mask */
769 sh_eth_write(ndev
, 0, EESIPR
);
771 #if defined(__LITTLE_ENDIAN__)
772 if (mdp
->cd
->hw_swap
)
773 sh_eth_write(ndev
, EDMR_EL
, EDMR
);
776 sh_eth_write(ndev
, 0, EDMR
);
779 sh_eth_write(ndev
, mdp
->cd
->fdr_value
, FDR
);
780 sh_eth_write(ndev
, 0, TFTR
);
782 /* Frame recv control */
783 sh_eth_write(ndev
, mdp
->cd
->rmcr_value
, RMCR
);
785 rx_int_var
= mdp
->rx_int_var
= DESC_I_RINT8
| DESC_I_RINT5
;
786 tx_int_var
= mdp
->tx_int_var
= DESC_I_TINT2
;
787 sh_eth_write(ndev
, rx_int_var
| tx_int_var
, TRSCER
);
790 sh_eth_write(ndev
, 0x800, BCULR
); /* Burst sycle set */
792 sh_eth_write(ndev
, mdp
->cd
->fcftr_value
, FCFTR
);
794 if (!mdp
->cd
->no_trimd
)
795 sh_eth_write(ndev
, 0, TRIMD
);
797 /* Recv frame limit set register */
798 sh_eth_write(ndev
, RFLR_VALUE
, RFLR
);
800 sh_eth_write(ndev
, sh_eth_read(ndev
, EESR
), EESR
);
801 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
803 /* PAUSE Prohibition */
804 val
= (sh_eth_read(ndev
, ECMR
) & ECMR_DM
) |
805 ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) | ECMR_TE
| ECMR_RE
;
807 sh_eth_write(ndev
, val
, ECMR
);
809 if (mdp
->cd
->set_rate
)
810 mdp
->cd
->set_rate(ndev
);
812 /* E-MAC Status Register clear */
813 sh_eth_write(ndev
, mdp
->cd
->ecsr_value
, ECSR
);
815 /* E-MAC Interrupt Enable register */
816 sh_eth_write(ndev
, mdp
->cd
->ecsipr_value
, ECSIPR
);
818 /* Set MAC address */
819 update_mac_address(ndev
);
823 sh_eth_write(ndev
, APR_AP
, APR
);
825 sh_eth_write(ndev
, MPR_MP
, MPR
);
826 if (mdp
->cd
->tpauser
)
827 sh_eth_write(ndev
, TPAUSER_UNLIMITED
, TPAUSER
);
829 /* Setting the Rx mode will start the Rx process. */
830 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
832 netif_start_queue(ndev
);
837 /* free Tx skb function */
838 static int sh_eth_txfree(struct net_device
*ndev
)
840 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
841 struct sh_eth_txdesc
*txdesc
;
845 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
846 entry
= mdp
->dirty_tx
% TX_RING_SIZE
;
847 txdesc
= &mdp
->tx_ring
[entry
];
848 if (txdesc
->status
& cpu_to_edmac(mdp
, TD_TACT
))
850 /* Free the original skb. */
851 if (mdp
->tx_skbuff
[entry
]) {
852 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
853 mdp
->tx_skbuff
[entry
] = NULL
;
856 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
857 if (entry
>= TX_RING_SIZE
- 1)
858 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
860 mdp
->stats
.tx_packets
++;
861 mdp
->stats
.tx_bytes
+= txdesc
->buffer_length
;
866 /* Packet receive function */
867 static int sh_eth_rx(struct net_device
*ndev
)
869 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
870 struct sh_eth_rxdesc
*rxdesc
;
872 int entry
= mdp
->cur_rx
% RX_RING_SIZE
;
873 int boguscnt
= (mdp
->dirty_rx
+ RX_RING_SIZE
) - mdp
->cur_rx
;
878 rxdesc
= &mdp
->rx_ring
[entry
];
879 while (!(rxdesc
->status
& cpu_to_edmac(mdp
, RD_RACT
))) {
880 desc_status
= edmac_to_cpu(mdp
, rxdesc
->status
);
881 pkt_len
= rxdesc
->frame_length
;
886 if (!(desc_status
& RDFEND
))
887 mdp
->stats
.rx_length_errors
++;
889 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
890 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
891 mdp
->stats
.rx_errors
++;
892 if (desc_status
& RD_RFS1
)
893 mdp
->stats
.rx_crc_errors
++;
894 if (desc_status
& RD_RFS2
)
895 mdp
->stats
.rx_frame_errors
++;
896 if (desc_status
& RD_RFS3
)
897 mdp
->stats
.rx_length_errors
++;
898 if (desc_status
& RD_RFS4
)
899 mdp
->stats
.rx_length_errors
++;
900 if (desc_status
& RD_RFS6
)
901 mdp
->stats
.rx_missed_errors
++;
902 if (desc_status
& RD_RFS10
)
903 mdp
->stats
.rx_over_errors
++;
905 if (!mdp
->cd
->hw_swap
)
907 phys_to_virt(ALIGN(rxdesc
->addr
, 4)),
909 skb
= mdp
->rx_skbuff
[entry
];
910 mdp
->rx_skbuff
[entry
] = NULL
;
912 skb_reserve(skb
, NET_IP_ALIGN
);
913 skb_put(skb
, pkt_len
);
914 skb
->protocol
= eth_type_trans(skb
, ndev
);
916 mdp
->stats
.rx_packets
++;
917 mdp
->stats
.rx_bytes
+= pkt_len
;
919 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RACT
);
920 entry
= (++mdp
->cur_rx
) % RX_RING_SIZE
;
921 rxdesc
= &mdp
->rx_ring
[entry
];
924 /* Refill the Rx ring buffers. */
925 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
926 entry
= mdp
->dirty_rx
% RX_RING_SIZE
;
927 rxdesc
= &mdp
->rx_ring
[entry
];
928 /* The size of the buffer is 16 byte boundary. */
929 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
931 if (mdp
->rx_skbuff
[entry
] == NULL
) {
932 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
933 mdp
->rx_skbuff
[entry
] = skb
;
935 break; /* Better luck next round. */
936 dma_map_single(&ndev
->dev
, skb
->tail
, mdp
->rx_buf_sz
,
939 sh_eth_set_receive_align(skb
);
941 skb_checksum_none_assert(skb
);
942 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
944 if (entry
>= RX_RING_SIZE
- 1)
946 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
| RD_RDEL
);
949 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
952 /* Restart Rx engine if stopped. */
953 /* If we don't need to check status, don't. -KDU */
954 if (!(sh_eth_read(ndev
, EDRRR
) & EDRRR_R
))
955 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
960 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
)
962 /* disable tx and rx */
963 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) &
964 ~(ECMR_RE
| ECMR_TE
), ECMR
);
967 static void sh_eth_rcv_snd_enable(struct net_device
*ndev
)
969 /* enable tx and rx */
970 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) |
971 (ECMR_RE
| ECMR_TE
), ECMR
);
974 /* error control function */
975 static void sh_eth_error(struct net_device
*ndev
, int intr_status
)
977 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
982 if (intr_status
& EESR_ECI
) {
983 felic_stat
= sh_eth_read(ndev
, ECSR
);
984 sh_eth_write(ndev
, felic_stat
, ECSR
); /* clear int */
985 if (felic_stat
& ECSR_ICD
)
986 mdp
->stats
.tx_carrier_errors
++;
987 if (felic_stat
& ECSR_LCHNG
) {
989 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
) {
990 if (mdp
->link
== PHY_DOWN
)
993 link_stat
= PHY_ST_LINK
;
995 link_stat
= (sh_eth_read(ndev
, PSR
));
996 if (mdp
->ether_link_active_low
)
997 link_stat
= ~link_stat
;
999 if (!(link_stat
& PHY_ST_LINK
))
1000 sh_eth_rcv_snd_disable(ndev
);
1003 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) &
1004 ~DMAC_M_ECI
, EESIPR
);
1006 sh_eth_write(ndev
, sh_eth_read(ndev
, ECSR
),
1008 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) |
1009 DMAC_M_ECI
, EESIPR
);
1010 /* enable tx and rx */
1011 sh_eth_rcv_snd_enable(ndev
);
1016 if (intr_status
& EESR_TWB
) {
1017 /* Write buck end. unused write back interrupt */
1018 if (intr_status
& EESR_TABT
) /* Transmit Abort int */
1019 mdp
->stats
.tx_aborted_errors
++;
1020 if (netif_msg_tx_err(mdp
))
1021 dev_err(&ndev
->dev
, "Transmit Abort\n");
1024 if (intr_status
& EESR_RABT
) {
1025 /* Receive Abort int */
1026 if (intr_status
& EESR_RFRMER
) {
1027 /* Receive Frame Overflow int */
1028 mdp
->stats
.rx_frame_errors
++;
1029 if (netif_msg_rx_err(mdp
))
1030 dev_err(&ndev
->dev
, "Receive Abort\n");
1034 if (intr_status
& EESR_TDE
) {
1035 /* Transmit Descriptor Empty int */
1036 mdp
->stats
.tx_fifo_errors
++;
1037 if (netif_msg_tx_err(mdp
))
1038 dev_err(&ndev
->dev
, "Transmit Descriptor Empty\n");
1041 if (intr_status
& EESR_TFE
) {
1042 /* FIFO under flow */
1043 mdp
->stats
.tx_fifo_errors
++;
1044 if (netif_msg_tx_err(mdp
))
1045 dev_err(&ndev
->dev
, "Transmit FIFO Under flow\n");
1048 if (intr_status
& EESR_RDE
) {
1049 /* Receive Descriptor Empty int */
1050 mdp
->stats
.rx_over_errors
++;
1052 if (sh_eth_read(ndev
, EDRRR
) ^ EDRRR_R
)
1053 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1054 if (netif_msg_rx_err(mdp
))
1055 dev_err(&ndev
->dev
, "Receive Descriptor Empty\n");
1058 if (intr_status
& EESR_RFE
) {
1059 /* Receive FIFO Overflow int */
1060 mdp
->stats
.rx_fifo_errors
++;
1061 if (netif_msg_rx_err(mdp
))
1062 dev_err(&ndev
->dev
, "Receive FIFO Overflow\n");
1065 if (!mdp
->cd
->no_ade
&& (intr_status
& EESR_ADE
)) {
1067 mdp
->stats
.tx_fifo_errors
++;
1068 if (netif_msg_tx_err(mdp
))
1069 dev_err(&ndev
->dev
, "Address Error\n");
1072 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
1073 if (mdp
->cd
->no_ade
)
1075 if (intr_status
& mask
) {
1077 u32 edtrr
= sh_eth_read(ndev
, EDTRR
);
1079 dev_err(&ndev
->dev
, "TX error. status=%8.8x cur_tx=%8.8x ",
1080 intr_status
, mdp
->cur_tx
);
1081 dev_err(&ndev
->dev
, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1082 mdp
->dirty_tx
, (u32
) ndev
->state
, edtrr
);
1083 /* dirty buffer free */
1084 sh_eth_txfree(ndev
);
1087 if (edtrr
^ sh_eth_get_edtrr_trns(mdp
)) {
1089 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1092 netif_wake_queue(ndev
);
1096 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
1098 struct net_device
*ndev
= netdev
;
1099 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1100 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1101 irqreturn_t ret
= IRQ_NONE
;
1102 u32 intr_status
= 0;
1104 spin_lock(&mdp
->lock
);
1106 /* Get interrpt stat */
1107 intr_status
= sh_eth_read(ndev
, EESR
);
1108 /* Clear interrupt */
1109 if (intr_status
& (EESR_FRC
| EESR_RMAF
| EESR_RRF
|
1110 EESR_RTLF
| EESR_RTSF
| EESR_PRE
| EESR_CERF
|
1111 cd
->tx_check
| cd
->eesr_err_check
)) {
1112 sh_eth_write(ndev
, intr_status
, EESR
);
1117 if (intr_status
& (EESR_FRC
| /* Frame recv*/
1118 EESR_RMAF
| /* Multi cast address recv*/
1119 EESR_RRF
| /* Bit frame recv */
1120 EESR_RTLF
| /* Long frame recv*/
1121 EESR_RTSF
| /* short frame recv */
1122 EESR_PRE
| /* PHY-LSI recv error */
1123 EESR_CERF
)){ /* recv frame CRC error */
1128 if (intr_status
& cd
->tx_check
) {
1129 sh_eth_txfree(ndev
);
1130 netif_wake_queue(ndev
);
1133 if (intr_status
& cd
->eesr_err_check
)
1134 sh_eth_error(ndev
, intr_status
);
1137 spin_unlock(&mdp
->lock
);
1142 static void sh_eth_timer(unsigned long data
)
1144 struct net_device
*ndev
= (struct net_device
*)data
;
1145 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1147 mod_timer(&mdp
->timer
, jiffies
+ (10 * HZ
));
1150 /* PHY state control function */
1151 static void sh_eth_adjust_link(struct net_device
*ndev
)
1153 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1154 struct phy_device
*phydev
= mdp
->phydev
;
1157 if (phydev
->link
!= PHY_DOWN
) {
1158 if (phydev
->duplex
!= mdp
->duplex
) {
1160 mdp
->duplex
= phydev
->duplex
;
1161 if (mdp
->cd
->set_duplex
)
1162 mdp
->cd
->set_duplex(ndev
);
1165 if (phydev
->speed
!= mdp
->speed
) {
1167 mdp
->speed
= phydev
->speed
;
1168 if (mdp
->cd
->set_rate
)
1169 mdp
->cd
->set_rate(ndev
);
1171 if (mdp
->link
== PHY_DOWN
) {
1172 sh_eth_write(ndev
, (sh_eth_read(ndev
, ECMR
) & ~ECMR_TXF
)
1175 mdp
->link
= phydev
->link
;
1177 } else if (mdp
->link
) {
1179 mdp
->link
= PHY_DOWN
;
1184 if (new_state
&& netif_msg_link(mdp
))
1185 phy_print_status(phydev
);
1188 /* PHY init function */
1189 static int sh_eth_phy_init(struct net_device
*ndev
)
1191 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1192 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1193 struct phy_device
*phydev
= NULL
;
1195 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
1196 mdp
->mii_bus
->id
, mdp
->phy_id
);
1198 mdp
->link
= PHY_DOWN
;
1202 /* Try connect to PHY */
1203 phydev
= phy_connect(ndev
, phy_id
, sh_eth_adjust_link
,
1204 0, mdp
->phy_interface
);
1205 if (IS_ERR(phydev
)) {
1206 dev_err(&ndev
->dev
, "phy_connect failed\n");
1207 return PTR_ERR(phydev
);
1210 dev_info(&ndev
->dev
, "attached phy %i to driver %s\n",
1211 phydev
->addr
, phydev
->drv
->name
);
1213 mdp
->phydev
= phydev
;
1218 /* PHY control start function */
1219 static int sh_eth_phy_start(struct net_device
*ndev
)
1221 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1224 ret
= sh_eth_phy_init(ndev
);
1228 /* reset phy - this also wakes it from PDOWN */
1229 phy_write(mdp
->phydev
, MII_BMCR
, BMCR_RESET
);
1230 phy_start(mdp
->phydev
);
1235 static int sh_eth_get_settings(struct net_device
*ndev
,
1236 struct ethtool_cmd
*ecmd
)
1238 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1239 unsigned long flags
;
1242 spin_lock_irqsave(&mdp
->lock
, flags
);
1243 ret
= phy_ethtool_gset(mdp
->phydev
, ecmd
);
1244 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1249 static int sh_eth_set_settings(struct net_device
*ndev
,
1250 struct ethtool_cmd
*ecmd
)
1252 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1253 unsigned long flags
;
1256 spin_lock_irqsave(&mdp
->lock
, flags
);
1258 /* disable tx and rx */
1259 sh_eth_rcv_snd_disable(ndev
);
1261 ret
= phy_ethtool_sset(mdp
->phydev
, ecmd
);
1265 if (ecmd
->duplex
== DUPLEX_FULL
)
1270 if (mdp
->cd
->set_duplex
)
1271 mdp
->cd
->set_duplex(ndev
);
1276 /* enable tx and rx */
1277 sh_eth_rcv_snd_enable(ndev
);
1279 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1284 static int sh_eth_nway_reset(struct net_device
*ndev
)
1286 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1287 unsigned long flags
;
1290 spin_lock_irqsave(&mdp
->lock
, flags
);
1291 ret
= phy_start_aneg(mdp
->phydev
);
1292 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1297 static u32
sh_eth_get_msglevel(struct net_device
*ndev
)
1299 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1300 return mdp
->msg_enable
;
1303 static void sh_eth_set_msglevel(struct net_device
*ndev
, u32 value
)
1305 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1306 mdp
->msg_enable
= value
;
1309 static const char sh_eth_gstrings_stats
[][ETH_GSTRING_LEN
] = {
1310 "rx_current", "tx_current",
1311 "rx_dirty", "tx_dirty",
1313 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1315 static int sh_eth_get_sset_count(struct net_device
*netdev
, int sset
)
1319 return SH_ETH_STATS_LEN
;
1325 static void sh_eth_get_ethtool_stats(struct net_device
*ndev
,
1326 struct ethtool_stats
*stats
, u64
*data
)
1328 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1331 /* device-specific stats */
1332 data
[i
++] = mdp
->cur_rx
;
1333 data
[i
++] = mdp
->cur_tx
;
1334 data
[i
++] = mdp
->dirty_rx
;
1335 data
[i
++] = mdp
->dirty_tx
;
1338 static void sh_eth_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1340 switch (stringset
) {
1342 memcpy(data
, *sh_eth_gstrings_stats
,
1343 sizeof(sh_eth_gstrings_stats
));
1348 static struct ethtool_ops sh_eth_ethtool_ops
= {
1349 .get_settings
= sh_eth_get_settings
,
1350 .set_settings
= sh_eth_set_settings
,
1351 .nway_reset
= sh_eth_nway_reset
,
1352 .get_msglevel
= sh_eth_get_msglevel
,
1353 .set_msglevel
= sh_eth_set_msglevel
,
1354 .get_link
= ethtool_op_get_link
,
1355 .get_strings
= sh_eth_get_strings
,
1356 .get_ethtool_stats
= sh_eth_get_ethtool_stats
,
1357 .get_sset_count
= sh_eth_get_sset_count
,
1360 /* network device open function */
1361 static int sh_eth_open(struct net_device
*ndev
)
1364 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1366 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1368 ret
= request_irq(ndev
->irq
, sh_eth_interrupt
,
1369 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1370 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1371 defined(CONFIG_CPU_SUBTYPE_SH7757)
1378 dev_err(&ndev
->dev
, "Can not assign IRQ number\n");
1382 /* Descriptor set */
1383 ret
= sh_eth_ring_init(ndev
);
1388 ret
= sh_eth_dev_init(ndev
);
1392 /* PHY control start*/
1393 ret
= sh_eth_phy_start(ndev
);
1397 /* Set the timer to check for link beat. */
1398 init_timer(&mdp
->timer
);
1399 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1400 setup_timer(&mdp
->timer
, sh_eth_timer
, (unsigned long)ndev
);
1405 free_irq(ndev
->irq
, ndev
);
1406 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1410 /* Timeout function */
1411 static void sh_eth_tx_timeout(struct net_device
*ndev
)
1413 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1414 struct sh_eth_rxdesc
*rxdesc
;
1417 netif_stop_queue(ndev
);
1419 if (netif_msg_timer(mdp
))
1420 dev_err(&ndev
->dev
, "%s: transmit timed out, status %8.8x,"
1421 " resetting...\n", ndev
->name
, (int)sh_eth_read(ndev
, EESR
));
1423 /* tx_errors count up */
1424 mdp
->stats
.tx_errors
++;
1427 del_timer_sync(&mdp
->timer
);
1429 /* Free all the skbuffs in the Rx queue. */
1430 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1431 rxdesc
= &mdp
->rx_ring
[i
];
1433 rxdesc
->addr
= 0xBADF00D0;
1434 if (mdp
->rx_skbuff
[i
])
1435 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1436 mdp
->rx_skbuff
[i
] = NULL
;
1438 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1439 if (mdp
->tx_skbuff
[i
])
1440 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
1441 mdp
->tx_skbuff
[i
] = NULL
;
1445 sh_eth_dev_init(ndev
);
1448 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1449 add_timer(&mdp
->timer
);
1452 /* Packet transmit function */
1453 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1455 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1456 struct sh_eth_txdesc
*txdesc
;
1458 unsigned long flags
;
1460 spin_lock_irqsave(&mdp
->lock
, flags
);
1461 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (TX_RING_SIZE
- 4)) {
1462 if (!sh_eth_txfree(ndev
)) {
1463 if (netif_msg_tx_queued(mdp
))
1464 dev_warn(&ndev
->dev
, "TxFD exhausted.\n");
1465 netif_stop_queue(ndev
);
1466 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1467 return NETDEV_TX_BUSY
;
1470 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1472 entry
= mdp
->cur_tx
% TX_RING_SIZE
;
1473 mdp
->tx_skbuff
[entry
] = skb
;
1474 txdesc
= &mdp
->tx_ring
[entry
];
1475 txdesc
->addr
= virt_to_phys(skb
->data
);
1477 if (!mdp
->cd
->hw_swap
)
1478 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc
->addr
, 4)),
1481 __flush_purge_region(skb
->data
, skb
->len
);
1482 if (skb
->len
< ETHERSMALL
)
1483 txdesc
->buffer_length
= ETHERSMALL
;
1485 txdesc
->buffer_length
= skb
->len
;
1487 if (entry
>= TX_RING_SIZE
- 1)
1488 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
| TD_TDLE
);
1490 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
);
1494 if (!(sh_eth_read(ndev
, EDTRR
) & sh_eth_get_edtrr_trns(mdp
)))
1495 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1497 return NETDEV_TX_OK
;
1500 /* device close function */
1501 static int sh_eth_close(struct net_device
*ndev
)
1503 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1506 netif_stop_queue(ndev
);
1508 /* Disable interrupts by clearing the interrupt mask. */
1509 sh_eth_write(ndev
, 0x0000, EESIPR
);
1511 /* Stop the chip's Tx and Rx processes. */
1512 sh_eth_write(ndev
, 0, EDTRR
);
1513 sh_eth_write(ndev
, 0, EDRRR
);
1515 /* PHY Disconnect */
1517 phy_stop(mdp
->phydev
);
1518 phy_disconnect(mdp
->phydev
);
1521 free_irq(ndev
->irq
, ndev
);
1523 del_timer_sync(&mdp
->timer
);
1525 /* Free all the skbuffs in the Rx queue. */
1526 sh_eth_ring_free(ndev
);
1528 /* free DMA buffer */
1529 ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
1530 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
1532 /* free DMA buffer */
1533 ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
1534 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
, mdp
->tx_desc_dma
);
1536 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1541 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
1543 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1545 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1547 mdp
->stats
.tx_dropped
+= sh_eth_read(ndev
, TROCR
);
1548 sh_eth_write(ndev
, 0, TROCR
); /* (write clear) */
1549 mdp
->stats
.collisions
+= sh_eth_read(ndev
, CDCR
);
1550 sh_eth_write(ndev
, 0, CDCR
); /* (write clear) */
1551 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, LCCR
);
1552 sh_eth_write(ndev
, 0, LCCR
); /* (write clear) */
1553 if (sh_eth_is_gether(mdp
)) {
1554 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CERCR
);
1555 sh_eth_write(ndev
, 0, CERCR
); /* (write clear) */
1556 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CEECR
);
1557 sh_eth_write(ndev
, 0, CEECR
); /* (write clear) */
1559 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CNDCR
);
1560 sh_eth_write(ndev
, 0, CNDCR
); /* (write clear) */
1562 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1567 /* ioctl to device funciotn*/
1568 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
,
1571 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1572 struct phy_device
*phydev
= mdp
->phydev
;
1574 if (!netif_running(ndev
))
1580 return phy_mii_ioctl(phydev
, rq
, cmd
);
1583 #if defined(SH_ETH_HAS_TSU)
1584 /* Multicast reception directions set */
1585 static void sh_eth_set_multicast_list(struct net_device
*ndev
)
1587 if (ndev
->flags
& IFF_PROMISC
) {
1588 /* Set promiscuous. */
1589 sh_eth_write(ndev
, (sh_eth_read(ndev
, ECMR
) & ~ECMR_MCT
) |
1592 /* Normal, unicast/broadcast-only mode. */
1593 sh_eth_write(ndev
, (sh_eth_read(ndev
, ECMR
) & ~ECMR_PRM
) |
1597 #endif /* SH_ETH_HAS_TSU */
1599 /* SuperH's TSU register init function */
1600 static void sh_eth_tsu_init(struct sh_eth_private
*mdp
)
1602 sh_eth_tsu_write(mdp
, 0, TSU_FWEN0
); /* Disable forward(0->1) */
1603 sh_eth_tsu_write(mdp
, 0, TSU_FWEN1
); /* Disable forward(1->0) */
1604 sh_eth_tsu_write(mdp
, 0, TSU_FCM
); /* forward fifo 3k-3k */
1605 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL0
);
1606 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL1
);
1607 sh_eth_tsu_write(mdp
, 0, TSU_PRISL0
);
1608 sh_eth_tsu_write(mdp
, 0, TSU_PRISL1
);
1609 sh_eth_tsu_write(mdp
, 0, TSU_FWSL0
);
1610 sh_eth_tsu_write(mdp
, 0, TSU_FWSL1
);
1611 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, TSU_FWSLC
);
1612 if (sh_eth_is_gether(mdp
)) {
1613 sh_eth_tsu_write(mdp
, 0, TSU_QTAG0
); /* Disable QTAG(0->1) */
1614 sh_eth_tsu_write(mdp
, 0, TSU_QTAG1
); /* Disable QTAG(1->0) */
1616 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM0
); /* Disable QTAG(0->1) */
1617 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM1
); /* Disable QTAG(1->0) */
1619 sh_eth_tsu_write(mdp
, 0, TSU_FWSR
); /* all interrupt status clear */
1620 sh_eth_tsu_write(mdp
, 0, TSU_FWINMK
); /* Disable all interrupt */
1621 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
1622 sh_eth_tsu_write(mdp
, 0, TSU_POST1
); /* Disable CAM entry [ 0- 7] */
1623 sh_eth_tsu_write(mdp
, 0, TSU_POST2
); /* Disable CAM entry [ 8-15] */
1624 sh_eth_tsu_write(mdp
, 0, TSU_POST3
); /* Disable CAM entry [16-23] */
1625 sh_eth_tsu_write(mdp
, 0, TSU_POST4
); /* Disable CAM entry [24-31] */
1628 /* MDIO bus release function */
1629 static int sh_mdio_release(struct net_device
*ndev
)
1631 struct mii_bus
*bus
= dev_get_drvdata(&ndev
->dev
);
1633 /* unregister mdio bus */
1634 mdiobus_unregister(bus
);
1636 /* remove mdio bus info from net_device */
1637 dev_set_drvdata(&ndev
->dev
, NULL
);
1639 /* free interrupts memory */
1642 /* free bitbang info */
1643 free_mdio_bitbang(bus
);
1648 /* MDIO bus init function */
1649 static int sh_mdio_init(struct net_device
*ndev
, int id
)
1652 struct bb_info
*bitbang
;
1653 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1655 /* create bit control struct for PHY */
1656 bitbang
= kzalloc(sizeof(struct bb_info
), GFP_KERNEL
);
1663 bitbang
->addr
= ndev
->base_addr
+ mdp
->reg_offset
[PIR
];
1664 bitbang
->mdi_msk
= 0x08;
1665 bitbang
->mdo_msk
= 0x04;
1666 bitbang
->mmd_msk
= 0x02;/* MMD */
1667 bitbang
->mdc_msk
= 0x01;
1668 bitbang
->ctrl
.ops
= &bb_ops
;
1670 /* MII controller setting */
1671 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
1672 if (!mdp
->mii_bus
) {
1674 goto out_free_bitbang
;
1677 /* Hook up MII support for ethtool */
1678 mdp
->mii_bus
->name
= "sh_mii";
1679 mdp
->mii_bus
->parent
= &ndev
->dev
;
1680 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x", id
);
1683 mdp
->mii_bus
->irq
= kmalloc(sizeof(int)*PHY_MAX_ADDR
, GFP_KERNEL
);
1684 if (!mdp
->mii_bus
->irq
) {
1689 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1690 mdp
->mii_bus
->irq
[i
] = PHY_POLL
;
1692 /* regist mdio bus */
1693 ret
= mdiobus_register(mdp
->mii_bus
);
1697 dev_set_drvdata(&ndev
->dev
, mdp
->mii_bus
);
1702 kfree(mdp
->mii_bus
->irq
);
1705 free_mdio_bitbang(mdp
->mii_bus
);
1714 static const u16
*sh_eth_get_register_offset(int register_type
)
1716 const u16
*reg_offset
= NULL
;
1718 switch (register_type
) {
1719 case SH_ETH_REG_GIGABIT
:
1720 reg_offset
= sh_eth_offset_gigabit
;
1722 case SH_ETH_REG_FAST_SH4
:
1723 reg_offset
= sh_eth_offset_fast_sh4
;
1725 case SH_ETH_REG_FAST_SH3_SH2
:
1726 reg_offset
= sh_eth_offset_fast_sh3_sh2
;
1729 printk(KERN_ERR
"Unknown register type (%d)\n", register_type
);
1736 static const struct net_device_ops sh_eth_netdev_ops
= {
1737 .ndo_open
= sh_eth_open
,
1738 .ndo_stop
= sh_eth_close
,
1739 .ndo_start_xmit
= sh_eth_start_xmit
,
1740 .ndo_get_stats
= sh_eth_get_stats
,
1741 #if defined(SH_ETH_HAS_TSU)
1742 .ndo_set_multicast_list
= sh_eth_set_multicast_list
,
1744 .ndo_tx_timeout
= sh_eth_tx_timeout
,
1745 .ndo_do_ioctl
= sh_eth_do_ioctl
,
1746 .ndo_validate_addr
= eth_validate_addr
,
1747 .ndo_set_mac_address
= eth_mac_addr
,
1748 .ndo_change_mtu
= eth_change_mtu
,
1751 static int sh_eth_drv_probe(struct platform_device
*pdev
)
1754 struct resource
*res
;
1755 struct net_device
*ndev
= NULL
;
1756 struct sh_eth_private
*mdp
;
1757 struct sh_eth_plat_data
*pd
;
1760 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1761 if (unlikely(res
== NULL
)) {
1762 dev_err(&pdev
->dev
, "invalid resource\n");
1767 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
1769 dev_err(&pdev
->dev
, "Could not allocate device.\n");
1774 /* The sh Ether-specific entries in the device structure. */
1775 ndev
->base_addr
= res
->start
;
1781 ret
= platform_get_irq(pdev
, 0);
1788 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1790 /* Fill in the fields of the device structure with ethernet values. */
1793 mdp
= netdev_priv(ndev
);
1794 spin_lock_init(&mdp
->lock
);
1796 pm_runtime_enable(&pdev
->dev
);
1797 pm_runtime_resume(&pdev
->dev
);
1799 pd
= (struct sh_eth_plat_data
*)(pdev
->dev
.platform_data
);
1801 mdp
->phy_id
= pd
->phy
;
1802 mdp
->phy_interface
= pd
->phy_interface
;
1804 mdp
->edmac_endian
= pd
->edmac_endian
;
1805 mdp
->no_ether_link
= pd
->no_ether_link
;
1806 mdp
->ether_link_active_low
= pd
->ether_link_active_low
;
1807 mdp
->reg_offset
= sh_eth_get_register_offset(pd
->register_type
);
1810 #if defined(SH_ETH_HAS_BOTH_MODULES)
1811 mdp
->cd
= sh_eth_get_cpu_data(mdp
);
1813 mdp
->cd
= &sh_eth_my_cpu_data
;
1815 sh_eth_set_default_cpu_data(mdp
->cd
);
1818 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
1819 SET_ETHTOOL_OPS(ndev
, &sh_eth_ethtool_ops
);
1820 ndev
->watchdog_timeo
= TX_TIMEOUT
;
1822 /* debug message level */
1823 mdp
->msg_enable
= SH_ETH_DEF_MSG_ENABLE
;
1824 mdp
->post_rx
= POST_RX
>> (devno
<< 1);
1825 mdp
->post_fw
= POST_FW
>> (devno
<< 1);
1827 /* read and set MAC address */
1828 read_mac_address(ndev
, pd
->mac_addr
);
1830 /* First device only init */
1833 struct resource
*rtsu
;
1834 rtsu
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1836 dev_err(&pdev
->dev
, "Not found TSU resource\n");
1839 mdp
->tsu_addr
= ioremap(rtsu
->start
,
1840 resource_size(rtsu
));
1842 if (mdp
->cd
->chip_reset
)
1843 mdp
->cd
->chip_reset(ndev
);
1846 /* TSU init (Init only)*/
1847 sh_eth_tsu_init(mdp
);
1851 /* network device register */
1852 ret
= register_netdev(ndev
);
1857 ret
= sh_mdio_init(ndev
, pdev
->id
);
1859 goto out_unregister
;
1861 /* print device infomation */
1862 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1863 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
1865 platform_set_drvdata(pdev
, ndev
);
1870 unregister_netdev(ndev
);
1875 iounmap(mdp
->tsu_addr
);
1883 static int sh_eth_drv_remove(struct platform_device
*pdev
)
1885 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1886 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1888 iounmap(mdp
->tsu_addr
);
1889 sh_mdio_release(ndev
);
1890 unregister_netdev(ndev
);
1891 pm_runtime_disable(&pdev
->dev
);
1893 platform_set_drvdata(pdev
, NULL
);
1898 static int sh_eth_runtime_nop(struct device
*dev
)
1901 * Runtime PM callback shared between ->runtime_suspend()
1902 * and ->runtime_resume(). Simply returns success.
1904 * This driver re-initializes all registers after
1905 * pm_runtime_get_sync() anyway so there is no need
1906 * to save and restore registers here.
1911 static struct dev_pm_ops sh_eth_dev_pm_ops
= {
1912 .runtime_suspend
= sh_eth_runtime_nop
,
1913 .runtime_resume
= sh_eth_runtime_nop
,
1916 static struct platform_driver sh_eth_driver
= {
1917 .probe
= sh_eth_drv_probe
,
1918 .remove
= sh_eth_drv_remove
,
1921 .pm
= &sh_eth_dev_pm_ops
,
1925 static int __init
sh_eth_init(void)
1927 return platform_driver_register(&sh_eth_driver
);
1930 static void __exit
sh_eth_cleanup(void)
1932 platform_driver_unregister(&sh_eth_driver
);
1935 module_init(sh_eth_init
);
1936 module_exit(sh_eth_cleanup
);
1938 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1939 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1940 MODULE_LICENSE("GPL v2");