2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/mii.h>
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.11"
46 #define PFX DRV_NAME " "
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
60 #define LINK_HZ (HZ/2)
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION
);
67 static const u32 default_msg
68 = NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
71 static int debug
= -1; /* defaults above */
72 module_param(debug
, int, 0);
73 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
75 static const struct pci_device_id skge_id_table
[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940
) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940B
) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_GE
) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_YU
) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, PCI_DEVICE_ID_DLINK_DGE510T
) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET
, PCI_DEVICE_ID_CNET_GIGACARD
) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS
, PCI_DEVICE_ID_LINKSYS_EG1064
) },
86 { PCI_VENDOR_ID_LINKSYS
, 0x1032, PCI_ANY_ID
, 0x0015 },
89 MODULE_DEVICE_TABLE(pci
, skge_id_table
);
91 static int skge_up(struct net_device
*dev
);
92 static int skge_down(struct net_device
*dev
);
93 static void skge_phy_reset(struct skge_port
*skge
);
94 static void skge_tx_clean(struct net_device
*dev
);
95 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
96 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
97 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
);
98 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
);
99 static void yukon_init(struct skge_hw
*hw
, int port
);
100 static void genesis_mac_init(struct skge_hw
*hw
, int port
);
101 static void genesis_link_up(struct skge_port
*skge
);
103 /* Avoid conditionals by using array */
104 static const int txqaddr
[] = { Q_XA1
, Q_XA2
};
105 static const int rxqaddr
[] = { Q_R1
, Q_R2
};
106 static const u32 rxirqmask
[] = { IS_R1_F
, IS_R2_F
};
107 static const u32 txirqmask
[] = { IS_XA1_F
, IS_XA2_F
};
108 static const u32 napimask
[] = { IS_R1_F
|IS_XA1_F
, IS_R2_F
|IS_XA2_F
};
109 static const u32 portmask
[] = { IS_PORT_1
, IS_PORT_2
};
111 static int skge_get_regs_len(struct net_device
*dev
)
117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
121 static void skge_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
124 const struct skge_port
*skge
= netdev_priv(dev
);
125 const void __iomem
*io
= skge
->hw
->regs
;
128 memset(p
, 0, regs
->len
);
129 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
131 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
,
132 regs
->len
- B3_RI_WTO_R1
);
135 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
136 static u32
wol_supported(const struct skge_hw
*hw
)
138 if (hw
->chip_id
== CHIP_ID_GENESIS
)
141 if (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)
144 return WAKE_MAGIC
| WAKE_PHY
;
147 static u32
pci_wake_enabled(struct pci_dev
*dev
)
149 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
152 /* If device doesn't support PM Capabilities, but request is to disable
153 * wake events, it's a nop; otherwise fail */
157 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &value
);
159 value
&= PCI_PM_CAP_PME_MASK
;
160 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
165 static void skge_wol_init(struct skge_port
*skge
)
167 struct skge_hw
*hw
= skge
->hw
;
168 int port
= skge
->port
;
171 skge_write16(hw
, B0_CTST
, CS_RST_CLR
);
172 skge_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
175 skge_write8(hw
, B0_POWER_CTRL
,
176 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_ON
| PC_VCC_OFF
);
178 /* WA code for COMA mode -- clear PHY reset */
179 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
180 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
181 u32 reg
= skge_read32(hw
, B2_GP_IO
);
184 skge_write32(hw
, B2_GP_IO
, reg
);
187 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
),
189 GPC_HWCFG_M_3
| GPC_HWCFG_M_2
| GPC_HWCFG_M_1
| GPC_HWCFG_M_0
|
190 GPC_ANEG_1
| GPC_RST_SET
);
192 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
),
194 GPC_HWCFG_M_3
| GPC_HWCFG_M_2
| GPC_HWCFG_M_1
| GPC_HWCFG_M_0
|
195 GPC_ANEG_1
| GPC_RST_CLR
);
197 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
199 /* Force to 10/100 skge_reset will re-enable on resume */
200 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
201 PHY_AN_100FULL
| PHY_AN_100HALF
|
202 PHY_AN_10FULL
| PHY_AN_10HALF
| PHY_AN_CSMA
);
204 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, 0);
205 gm_phy_write(hw
, port
, PHY_MARV_CTRL
,
206 PHY_CT_RESET
| PHY_CT_SPS_LSB
| PHY_CT_ANE
|
207 PHY_CT_RE_CFG
| PHY_CT_DUP_MD
);
210 /* Set GMAC to no flow control and auto update for speed/duplex */
211 gma_write16(hw
, port
, GM_GP_CTRL
,
212 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
213 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
215 /* Set WOL address */
216 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
217 skge
->netdev
->dev_addr
, ETH_ALEN
);
219 /* Turn on appropriate WOL control bits */
220 skge_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
222 if (skge
->wol
& WAKE_PHY
)
223 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
225 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
227 if (skge
->wol
& WAKE_MAGIC
)
228 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
230 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
232 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
233 skge_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
236 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
239 static void skge_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
241 struct skge_port
*skge
= netdev_priv(dev
);
243 wol
->supported
= wol_supported(skge
->hw
);
244 wol
->wolopts
= skge
->wol
;
247 static int skge_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
249 struct skge_port
*skge
= netdev_priv(dev
);
250 struct skge_hw
*hw
= skge
->hw
;
252 if (wol
->wolopts
& ~wol_supported(hw
))
255 skge
->wol
= wol
->wolopts
;
259 /* Determine supported/advertised modes based on hardware.
260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
262 static u32
skge_supported_modes(const struct skge_hw
*hw
)
267 supported
= SUPPORTED_10baseT_Half
268 | SUPPORTED_10baseT_Full
269 | SUPPORTED_100baseT_Half
270 | SUPPORTED_100baseT_Full
271 | SUPPORTED_1000baseT_Half
272 | SUPPORTED_1000baseT_Full
273 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
275 if (hw
->chip_id
== CHIP_ID_GENESIS
)
276 supported
&= ~(SUPPORTED_10baseT_Half
277 | SUPPORTED_10baseT_Full
278 | SUPPORTED_100baseT_Half
279 | SUPPORTED_100baseT_Full
);
281 else if (hw
->chip_id
== CHIP_ID_YUKON
)
282 supported
&= ~SUPPORTED_1000baseT_Half
;
284 supported
= SUPPORTED_1000baseT_Full
| SUPPORTED_1000baseT_Half
285 | SUPPORTED_FIBRE
| SUPPORTED_Autoneg
;
290 static int skge_get_settings(struct net_device
*dev
,
291 struct ethtool_cmd
*ecmd
)
293 struct skge_port
*skge
= netdev_priv(dev
);
294 struct skge_hw
*hw
= skge
->hw
;
296 ecmd
->transceiver
= XCVR_INTERNAL
;
297 ecmd
->supported
= skge_supported_modes(hw
);
300 ecmd
->port
= PORT_TP
;
301 ecmd
->phy_address
= hw
->phy_addr
;
303 ecmd
->port
= PORT_FIBRE
;
305 ecmd
->advertising
= skge
->advertising
;
306 ecmd
->autoneg
= skge
->autoneg
;
307 ecmd
->speed
= skge
->speed
;
308 ecmd
->duplex
= skge
->duplex
;
312 static int skge_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
314 struct skge_port
*skge
= netdev_priv(dev
);
315 const struct skge_hw
*hw
= skge
->hw
;
316 u32 supported
= skge_supported_modes(hw
);
318 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
319 ecmd
->advertising
= supported
;
325 switch (ecmd
->speed
) {
327 if (ecmd
->duplex
== DUPLEX_FULL
)
328 setting
= SUPPORTED_1000baseT_Full
;
329 else if (ecmd
->duplex
== DUPLEX_HALF
)
330 setting
= SUPPORTED_1000baseT_Half
;
335 if (ecmd
->duplex
== DUPLEX_FULL
)
336 setting
= SUPPORTED_100baseT_Full
;
337 else if (ecmd
->duplex
== DUPLEX_HALF
)
338 setting
= SUPPORTED_100baseT_Half
;
344 if (ecmd
->duplex
== DUPLEX_FULL
)
345 setting
= SUPPORTED_10baseT_Full
;
346 else if (ecmd
->duplex
== DUPLEX_HALF
)
347 setting
= SUPPORTED_10baseT_Half
;
355 if ((setting
& supported
) == 0)
358 skge
->speed
= ecmd
->speed
;
359 skge
->duplex
= ecmd
->duplex
;
362 skge
->autoneg
= ecmd
->autoneg
;
363 skge
->advertising
= ecmd
->advertising
;
365 if (netif_running(dev
))
366 skge_phy_reset(skge
);
371 static void skge_get_drvinfo(struct net_device
*dev
,
372 struct ethtool_drvinfo
*info
)
374 struct skge_port
*skge
= netdev_priv(dev
);
376 strcpy(info
->driver
, DRV_NAME
);
377 strcpy(info
->version
, DRV_VERSION
);
378 strcpy(info
->fw_version
, "N/A");
379 strcpy(info
->bus_info
, pci_name(skge
->hw
->pdev
));
382 static const struct skge_stat
{
383 char name
[ETH_GSTRING_LEN
];
387 { "tx_bytes", XM_TXO_OK_HI
, GM_TXO_OK_HI
},
388 { "rx_bytes", XM_RXO_OK_HI
, GM_RXO_OK_HI
},
390 { "tx_broadcast", XM_TXF_BC_OK
, GM_TXF_BC_OK
},
391 { "rx_broadcast", XM_RXF_BC_OK
, GM_RXF_BC_OK
},
392 { "tx_multicast", XM_TXF_MC_OK
, GM_TXF_MC_OK
},
393 { "rx_multicast", XM_RXF_MC_OK
, GM_RXF_MC_OK
},
394 { "tx_unicast", XM_TXF_UC_OK
, GM_TXF_UC_OK
},
395 { "rx_unicast", XM_RXF_UC_OK
, GM_RXF_UC_OK
},
396 { "tx_mac_pause", XM_TXF_MPAUSE
, GM_TXF_MPAUSE
},
397 { "rx_mac_pause", XM_RXF_MPAUSE
, GM_RXF_MPAUSE
},
399 { "collisions", XM_TXF_SNG_COL
, GM_TXF_SNG_COL
},
400 { "multi_collisions", XM_TXF_MUL_COL
, GM_TXF_MUL_COL
},
401 { "aborted", XM_TXF_ABO_COL
, GM_TXF_ABO_COL
},
402 { "late_collision", XM_TXF_LAT_COL
, GM_TXF_LAT_COL
},
403 { "fifo_underrun", XM_TXE_FIFO_UR
, GM_TXE_FIFO_UR
},
404 { "fifo_overflow", XM_RXE_FIFO_OV
, GM_RXE_FIFO_OV
},
406 { "rx_toolong", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
407 { "rx_jabber", XM_RXF_JAB_PKT
, GM_RXF_JAB_PKT
},
408 { "rx_runt", XM_RXE_RUNT
, GM_RXE_FRAG
},
409 { "rx_too_long", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
410 { "rx_fcs_error", XM_RXF_FCS_ERR
, GM_RXF_FCS_ERR
},
413 static int skge_get_sset_count(struct net_device
*dev
, int sset
)
417 return ARRAY_SIZE(skge_stats
);
423 static void skge_get_ethtool_stats(struct net_device
*dev
,
424 struct ethtool_stats
*stats
, u64
*data
)
426 struct skge_port
*skge
= netdev_priv(dev
);
428 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
429 genesis_get_stats(skge
, data
);
431 yukon_get_stats(skge
, data
);
434 /* Use hardware MIB variables for critical path statistics and
435 * transmit feedback not reported at interrupt.
436 * Other errors are accounted for in interrupt handler.
438 static struct net_device_stats
*skge_get_stats(struct net_device
*dev
)
440 struct skge_port
*skge
= netdev_priv(dev
);
441 u64 data
[ARRAY_SIZE(skge_stats
)];
443 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
444 genesis_get_stats(skge
, data
);
446 yukon_get_stats(skge
, data
);
448 skge
->net_stats
.tx_bytes
= data
[0];
449 skge
->net_stats
.rx_bytes
= data
[1];
450 skge
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
451 skge
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
452 skge
->net_stats
.multicast
= data
[3] + data
[5];
453 skge
->net_stats
.collisions
= data
[10];
454 skge
->net_stats
.tx_aborted_errors
= data
[12];
456 return &skge
->net_stats
;
459 static void skge_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
465 for (i
= 0; i
< ARRAY_SIZE(skge_stats
); i
++)
466 memcpy(data
+ i
* ETH_GSTRING_LEN
,
467 skge_stats
[i
].name
, ETH_GSTRING_LEN
);
472 static void skge_get_ring_param(struct net_device
*dev
,
473 struct ethtool_ringparam
*p
)
475 struct skge_port
*skge
= netdev_priv(dev
);
477 p
->rx_max_pending
= MAX_RX_RING_SIZE
;
478 p
->tx_max_pending
= MAX_TX_RING_SIZE
;
479 p
->rx_mini_max_pending
= 0;
480 p
->rx_jumbo_max_pending
= 0;
482 p
->rx_pending
= skge
->rx_ring
.count
;
483 p
->tx_pending
= skge
->tx_ring
.count
;
484 p
->rx_mini_pending
= 0;
485 p
->rx_jumbo_pending
= 0;
488 static int skge_set_ring_param(struct net_device
*dev
,
489 struct ethtool_ringparam
*p
)
491 struct skge_port
*skge
= netdev_priv(dev
);
494 if (p
->rx_pending
== 0 || p
->rx_pending
> MAX_RX_RING_SIZE
||
495 p
->tx_pending
< TX_LOW_WATER
|| p
->tx_pending
> MAX_TX_RING_SIZE
)
498 skge
->rx_ring
.count
= p
->rx_pending
;
499 skge
->tx_ring
.count
= p
->tx_pending
;
501 if (netif_running(dev
)) {
511 static u32
skge_get_msglevel(struct net_device
*netdev
)
513 struct skge_port
*skge
= netdev_priv(netdev
);
514 return skge
->msg_enable
;
517 static void skge_set_msglevel(struct net_device
*netdev
, u32 value
)
519 struct skge_port
*skge
= netdev_priv(netdev
);
520 skge
->msg_enable
= value
;
523 static int skge_nway_reset(struct net_device
*dev
)
525 struct skge_port
*skge
= netdev_priv(dev
);
527 if (skge
->autoneg
!= AUTONEG_ENABLE
|| !netif_running(dev
))
530 skge_phy_reset(skge
);
534 static int skge_set_sg(struct net_device
*dev
, u32 data
)
536 struct skge_port
*skge
= netdev_priv(dev
);
537 struct skge_hw
*hw
= skge
->hw
;
539 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
541 return ethtool_op_set_sg(dev
, data
);
544 static int skge_set_tx_csum(struct net_device
*dev
, u32 data
)
546 struct skge_port
*skge
= netdev_priv(dev
);
547 struct skge_hw
*hw
= skge
->hw
;
549 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
552 return ethtool_op_set_tx_csum(dev
, data
);
555 static u32
skge_get_rx_csum(struct net_device
*dev
)
557 struct skge_port
*skge
= netdev_priv(dev
);
559 return skge
->rx_csum
;
562 /* Only Yukon supports checksum offload. */
563 static int skge_set_rx_csum(struct net_device
*dev
, u32 data
)
565 struct skge_port
*skge
= netdev_priv(dev
);
567 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
570 skge
->rx_csum
= data
;
574 static void skge_get_pauseparam(struct net_device
*dev
,
575 struct ethtool_pauseparam
*ecmd
)
577 struct skge_port
*skge
= netdev_priv(dev
);
579 ecmd
->rx_pause
= (skge
->flow_control
== FLOW_MODE_SYMMETRIC
)
580 || (skge
->flow_control
== FLOW_MODE_SYM_OR_REM
);
581 ecmd
->tx_pause
= ecmd
->rx_pause
|| (skge
->flow_control
== FLOW_MODE_LOC_SEND
);
583 ecmd
->autoneg
= ecmd
->rx_pause
|| ecmd
->tx_pause
;
586 static int skge_set_pauseparam(struct net_device
*dev
,
587 struct ethtool_pauseparam
*ecmd
)
589 struct skge_port
*skge
= netdev_priv(dev
);
590 struct ethtool_pauseparam old
;
592 skge_get_pauseparam(dev
, &old
);
594 if (ecmd
->autoneg
!= old
.autoneg
)
595 skge
->flow_control
= ecmd
->autoneg
? FLOW_MODE_NONE
: FLOW_MODE_SYMMETRIC
;
597 if (ecmd
->rx_pause
&& ecmd
->tx_pause
)
598 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
599 else if (ecmd
->rx_pause
&& !ecmd
->tx_pause
)
600 skge
->flow_control
= FLOW_MODE_SYM_OR_REM
;
601 else if (!ecmd
->rx_pause
&& ecmd
->tx_pause
)
602 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
604 skge
->flow_control
= FLOW_MODE_NONE
;
607 if (netif_running(dev
))
608 skge_phy_reset(skge
);
613 /* Chip internal frequency for clock calculations */
614 static inline u32
hwkhz(const struct skge_hw
*hw
)
616 return (hw
->chip_id
== CHIP_ID_GENESIS
) ? 53125 : 78125;
619 /* Chip HZ to microseconds */
620 static inline u32
skge_clk2usec(const struct skge_hw
*hw
, u32 ticks
)
622 return (ticks
* 1000) / hwkhz(hw
);
625 /* Microseconds to chip HZ */
626 static inline u32
skge_usecs2clk(const struct skge_hw
*hw
, u32 usec
)
628 return hwkhz(hw
) * usec
/ 1000;
631 static int skge_get_coalesce(struct net_device
*dev
,
632 struct ethtool_coalesce
*ecmd
)
634 struct skge_port
*skge
= netdev_priv(dev
);
635 struct skge_hw
*hw
= skge
->hw
;
636 int port
= skge
->port
;
638 ecmd
->rx_coalesce_usecs
= 0;
639 ecmd
->tx_coalesce_usecs
= 0;
641 if (skge_read32(hw
, B2_IRQM_CTRL
) & TIM_START
) {
642 u32 delay
= skge_clk2usec(hw
, skge_read32(hw
, B2_IRQM_INI
));
643 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
645 if (msk
& rxirqmask
[port
])
646 ecmd
->rx_coalesce_usecs
= delay
;
647 if (msk
& txirqmask
[port
])
648 ecmd
->tx_coalesce_usecs
= delay
;
654 /* Note: interrupt timer is per board, but can turn on/off per port */
655 static int skge_set_coalesce(struct net_device
*dev
,
656 struct ethtool_coalesce
*ecmd
)
658 struct skge_port
*skge
= netdev_priv(dev
);
659 struct skge_hw
*hw
= skge
->hw
;
660 int port
= skge
->port
;
661 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
664 if (ecmd
->rx_coalesce_usecs
== 0)
665 msk
&= ~rxirqmask
[port
];
666 else if (ecmd
->rx_coalesce_usecs
< 25 ||
667 ecmd
->rx_coalesce_usecs
> 33333)
670 msk
|= rxirqmask
[port
];
671 delay
= ecmd
->rx_coalesce_usecs
;
674 if (ecmd
->tx_coalesce_usecs
== 0)
675 msk
&= ~txirqmask
[port
];
676 else if (ecmd
->tx_coalesce_usecs
< 25 ||
677 ecmd
->tx_coalesce_usecs
> 33333)
680 msk
|= txirqmask
[port
];
681 delay
= min(delay
, ecmd
->rx_coalesce_usecs
);
684 skge_write32(hw
, B2_IRQM_MSK
, msk
);
686 skge_write32(hw
, B2_IRQM_CTRL
, TIM_STOP
);
688 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, delay
));
689 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
694 enum led_mode
{ LED_MODE_OFF
, LED_MODE_ON
, LED_MODE_TST
};
695 static void skge_led(struct skge_port
*skge
, enum led_mode mode
)
697 struct skge_hw
*hw
= skge
->hw
;
698 int port
= skge
->port
;
700 spin_lock_bh(&hw
->phy_lock
);
701 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
704 if (hw
->phy_type
== SK_PHY_BCOM
)
705 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_OFF
);
707 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 0);
708 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_T_OFF
);
710 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
711 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 0);
712 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_T_OFF
);
716 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_ON
);
717 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_LINKSYNC_ON
);
719 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
720 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
725 skge_write8(hw
, SK_REG(port
, RX_LED_TST
), LED_T_ON
);
726 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 100);
727 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
729 if (hw
->phy_type
== SK_PHY_BCOM
)
730 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_ON
);
732 skge_write8(hw
, SK_REG(port
, TX_LED_TST
), LED_T_ON
);
733 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 100);
734 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
741 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
742 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
743 PHY_M_LED_MO_DUP(MO_LED_OFF
) |
744 PHY_M_LED_MO_10(MO_LED_OFF
) |
745 PHY_M_LED_MO_100(MO_LED_OFF
) |
746 PHY_M_LED_MO_1000(MO_LED_OFF
) |
747 PHY_M_LED_MO_RX(MO_LED_OFF
));
750 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
,
751 PHY_M_LED_PULS_DUR(PULS_170MS
) |
752 PHY_M_LED_BLINK_RT(BLINK_84MS
) |
756 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
757 PHY_M_LED_MO_RX(MO_LED_OFF
) |
758 (skge
->speed
== SPEED_100
?
759 PHY_M_LED_MO_100(MO_LED_ON
) : 0));
762 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
763 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
764 PHY_M_LED_MO_DUP(MO_LED_ON
) |
765 PHY_M_LED_MO_10(MO_LED_ON
) |
766 PHY_M_LED_MO_100(MO_LED_ON
) |
767 PHY_M_LED_MO_1000(MO_LED_ON
) |
768 PHY_M_LED_MO_RX(MO_LED_ON
));
771 spin_unlock_bh(&hw
->phy_lock
);
774 /* blink LED's for finding board */
775 static int skge_phys_id(struct net_device
*dev
, u32 data
)
777 struct skge_port
*skge
= netdev_priv(dev
);
779 enum led_mode mode
= LED_MODE_TST
;
781 if (!data
|| data
> (u32
)(MAX_SCHEDULE_TIMEOUT
/ HZ
))
782 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
/ HZ
) * 1000;
787 skge_led(skge
, mode
);
788 mode
^= LED_MODE_TST
;
790 if (msleep_interruptible(BLINK_MS
))
795 /* back to regular LED state */
796 skge_led(skge
, netif_running(dev
) ? LED_MODE_ON
: LED_MODE_OFF
);
801 static const struct ethtool_ops skge_ethtool_ops
= {
802 .get_settings
= skge_get_settings
,
803 .set_settings
= skge_set_settings
,
804 .get_drvinfo
= skge_get_drvinfo
,
805 .get_regs_len
= skge_get_regs_len
,
806 .get_regs
= skge_get_regs
,
807 .get_wol
= skge_get_wol
,
808 .set_wol
= skge_set_wol
,
809 .get_msglevel
= skge_get_msglevel
,
810 .set_msglevel
= skge_set_msglevel
,
811 .nway_reset
= skge_nway_reset
,
812 .get_link
= ethtool_op_get_link
,
813 .get_ringparam
= skge_get_ring_param
,
814 .set_ringparam
= skge_set_ring_param
,
815 .get_pauseparam
= skge_get_pauseparam
,
816 .set_pauseparam
= skge_set_pauseparam
,
817 .get_coalesce
= skge_get_coalesce
,
818 .set_coalesce
= skge_set_coalesce
,
819 .set_sg
= skge_set_sg
,
820 .set_tx_csum
= skge_set_tx_csum
,
821 .get_rx_csum
= skge_get_rx_csum
,
822 .set_rx_csum
= skge_set_rx_csum
,
823 .get_strings
= skge_get_strings
,
824 .phys_id
= skge_phys_id
,
825 .get_sset_count
= skge_get_sset_count
,
826 .get_ethtool_stats
= skge_get_ethtool_stats
,
830 * Allocate ring elements and chain them together
831 * One-to-one association of board descriptors with ring elements
833 static int skge_ring_alloc(struct skge_ring
*ring
, void *vaddr
, u32 base
)
835 struct skge_tx_desc
*d
;
836 struct skge_element
*e
;
839 ring
->start
= kcalloc(ring
->count
, sizeof(*e
), GFP_KERNEL
);
843 for (i
= 0, e
= ring
->start
, d
= vaddr
; i
< ring
->count
; i
++, e
++, d
++) {
845 if (i
== ring
->count
- 1) {
846 e
->next
= ring
->start
;
847 d
->next_offset
= base
;
850 d
->next_offset
= base
+ (i
+1) * sizeof(*d
);
853 ring
->to_use
= ring
->to_clean
= ring
->start
;
858 /* Allocate and setup a new buffer for receiving */
859 static void skge_rx_setup(struct skge_port
*skge
, struct skge_element
*e
,
860 struct sk_buff
*skb
, unsigned int bufsize
)
862 struct skge_rx_desc
*rd
= e
->desc
;
865 map
= pci_map_single(skge
->hw
->pdev
, skb
->data
, bufsize
,
869 rd
->dma_hi
= map
>> 32;
871 rd
->csum1_start
= ETH_HLEN
;
872 rd
->csum2_start
= ETH_HLEN
;
878 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| bufsize
;
879 pci_unmap_addr_set(e
, mapaddr
, map
);
880 pci_unmap_len_set(e
, maplen
, bufsize
);
883 /* Resume receiving using existing skb,
884 * Note: DMA address is not changed by chip.
885 * MTU not changed while receiver active.
887 static inline void skge_rx_reuse(struct skge_element
*e
, unsigned int size
)
889 struct skge_rx_desc
*rd
= e
->desc
;
892 rd
->csum2_start
= ETH_HLEN
;
896 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| size
;
900 /* Free all buffers in receive ring, assumes receiver stopped */
901 static void skge_rx_clean(struct skge_port
*skge
)
903 struct skge_hw
*hw
= skge
->hw
;
904 struct skge_ring
*ring
= &skge
->rx_ring
;
905 struct skge_element
*e
;
909 struct skge_rx_desc
*rd
= e
->desc
;
912 pci_unmap_single(hw
->pdev
,
913 pci_unmap_addr(e
, mapaddr
),
914 pci_unmap_len(e
, maplen
),
916 dev_kfree_skb(e
->skb
);
919 } while ((e
= e
->next
) != ring
->start
);
923 /* Allocate buffers for receive ring
924 * For receive: to_clean is next received frame.
926 static int skge_rx_fill(struct net_device
*dev
)
928 struct skge_port
*skge
= netdev_priv(dev
);
929 struct skge_ring
*ring
= &skge
->rx_ring
;
930 struct skge_element
*e
;
936 skb
= __netdev_alloc_skb(dev
, skge
->rx_buf_size
+ NET_IP_ALIGN
,
941 skb_reserve(skb
, NET_IP_ALIGN
);
942 skge_rx_setup(skge
, e
, skb
, skge
->rx_buf_size
);
943 } while ( (e
= e
->next
) != ring
->start
);
945 ring
->to_clean
= ring
->start
;
949 static const char *skge_pause(enum pause_status status
)
954 case FLOW_STAT_REM_SEND
:
956 case FLOW_STAT_LOC_SEND
:
958 case FLOW_STAT_SYMMETRIC
: /* Both station may send PAUSE */
961 return "indeterminated";
966 static void skge_link_up(struct skge_port
*skge
)
968 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
),
969 LED_BLK_OFF
|LED_SYNC_OFF
|LED_ON
);
971 netif_carrier_on(skge
->netdev
);
972 netif_wake_queue(skge
->netdev
);
974 if (netif_msg_link(skge
)) {
976 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
977 skge
->netdev
->name
, skge
->speed
,
978 skge
->duplex
== DUPLEX_FULL
? "full" : "half",
979 skge_pause(skge
->flow_status
));
983 static void skge_link_down(struct skge_port
*skge
)
985 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
986 netif_carrier_off(skge
->netdev
);
987 netif_stop_queue(skge
->netdev
);
989 if (netif_msg_link(skge
))
990 printk(KERN_INFO PFX
"%s: Link is down.\n", skge
->netdev
->name
);
994 static void xm_link_down(struct skge_hw
*hw
, int port
)
996 struct net_device
*dev
= hw
->dev
[port
];
997 struct skge_port
*skge
= netdev_priv(dev
);
1000 if (hw
->phy_type
== SK_PHY_XMAC
) {
1001 msk
= xm_read16(hw
, port
, XM_IMSK
);
1002 msk
|= XM_IS_INP_ASS
| XM_IS_LIPA_RC
| XM_IS_RX_PAGE
| XM_IS_AND
;
1003 xm_write16(hw
, port
, XM_IMSK
, msk
);
1006 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1007 cmd
&= ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1008 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1009 /* dummy read to ensure writing */
1010 (void) xm_read16(hw
, port
, XM_MMU_CMD
);
1012 if (netif_carrier_ok(dev
))
1013 skge_link_down(skge
);
1016 static int __xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
1020 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
1021 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
1023 if (hw
->phy_type
== SK_PHY_XMAC
)
1026 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1027 if (xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_RDY
)
1034 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
1039 static u16
xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
1042 if (__xm_phy_read(hw
, port
, reg
, &v
))
1043 printk(KERN_WARNING PFX
"%s: phy read timed out\n",
1044 hw
->dev
[port
]->name
);
1048 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
1052 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
1053 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1054 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
1061 xm_write16(hw
, port
, XM_PHY_DATA
, val
);
1062 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1063 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
1070 static void genesis_init(struct skge_hw
*hw
)
1072 /* set blink source counter */
1073 skge_write32(hw
, B2_BSC_INI
, (SK_BLK_DUR
* SK_FACT_53
) / 100);
1074 skge_write8(hw
, B2_BSC_CTRL
, BSC_START
);
1076 /* configure mac arbiter */
1077 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
1079 /* configure mac arbiter timeout values */
1080 skge_write8(hw
, B3_MA_TOINI_RX1
, SK_MAC_TO_53
);
1081 skge_write8(hw
, B3_MA_TOINI_RX2
, SK_MAC_TO_53
);
1082 skge_write8(hw
, B3_MA_TOINI_TX1
, SK_MAC_TO_53
);
1083 skge_write8(hw
, B3_MA_TOINI_TX2
, SK_MAC_TO_53
);
1085 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
1086 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1087 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1088 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1090 /* configure packet arbiter timeout */
1091 skge_write16(hw
, B3_PA_CTRL
, PA_RST_CLR
);
1092 skge_write16(hw
, B3_PA_TOINI_RX1
, SK_PKT_TO_MAX
);
1093 skge_write16(hw
, B3_PA_TOINI_TX1
, SK_PKT_TO_MAX
);
1094 skge_write16(hw
, B3_PA_TOINI_RX2
, SK_PKT_TO_MAX
);
1095 skge_write16(hw
, B3_PA_TOINI_TX2
, SK_PKT_TO_MAX
);
1098 static void genesis_reset(struct skge_hw
*hw
, int port
)
1100 const u8 zero
[8] = { 0 };
1102 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
1104 /* reset the statistics module */
1105 xm_write32(hw
, port
, XM_GP_PORT
, XM_GP_RES_STAT
);
1106 xm_write16(hw
, port
, XM_IMSK
, 0xffff); /* disable XMAC IRQs */
1107 xm_write32(hw
, port
, XM_MODE
, 0); /* clear Mode Reg */
1108 xm_write16(hw
, port
, XM_TX_CMD
, 0); /* reset TX CMD Reg */
1109 xm_write16(hw
, port
, XM_RX_CMD
, 0); /* reset RX CMD Reg */
1111 /* disable Broadcom PHY IRQ */
1112 if (hw
->phy_type
== SK_PHY_BCOM
)
1113 xm_write16(hw
, port
, PHY_BCOM_INT_MASK
, 0xffff);
1115 xm_outhash(hw
, port
, XM_HSM
, zero
);
1119 /* Convert mode to MII values */
1120 static const u16 phy_pause_map
[] = {
1121 [FLOW_MODE_NONE
] = 0,
1122 [FLOW_MODE_LOC_SEND
] = PHY_AN_PAUSE_ASYM
,
1123 [FLOW_MODE_SYMMETRIC
] = PHY_AN_PAUSE_CAP
,
1124 [FLOW_MODE_SYM_OR_REM
] = PHY_AN_PAUSE_CAP
| PHY_AN_PAUSE_ASYM
,
1127 /* special defines for FIBER (88E1011S only) */
1128 static const u16 fiber_pause_map
[] = {
1129 [FLOW_MODE_NONE
] = PHY_X_P_NO_PAUSE
,
1130 [FLOW_MODE_LOC_SEND
] = PHY_X_P_ASYM_MD
,
1131 [FLOW_MODE_SYMMETRIC
] = PHY_X_P_SYM_MD
,
1132 [FLOW_MODE_SYM_OR_REM
] = PHY_X_P_BOTH_MD
,
1136 /* Check status of Broadcom phy link */
1137 static void bcom_check_link(struct skge_hw
*hw
, int port
)
1139 struct net_device
*dev
= hw
->dev
[port
];
1140 struct skge_port
*skge
= netdev_priv(dev
);
1143 /* read twice because of latch */
1144 (void) xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1145 status
= xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1147 if ((status
& PHY_ST_LSYNC
) == 0) {
1148 xm_link_down(hw
, port
);
1152 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1155 if (!(status
& PHY_ST_AN_OVER
))
1158 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1159 if (lpa
& PHY_B_AN_RF
) {
1160 printk(KERN_NOTICE PFX
"%s: remote fault\n",
1165 aux
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_STAT
);
1167 /* Check Duplex mismatch */
1168 switch (aux
& PHY_B_AS_AN_RES_MSK
) {
1169 case PHY_B_RES_1000FD
:
1170 skge
->duplex
= DUPLEX_FULL
;
1172 case PHY_B_RES_1000HD
:
1173 skge
->duplex
= DUPLEX_HALF
;
1176 printk(KERN_NOTICE PFX
"%s: duplex mismatch\n",
1181 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1182 switch (aux
& PHY_B_AS_PAUSE_MSK
) {
1183 case PHY_B_AS_PAUSE_MSK
:
1184 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
1187 skge
->flow_status
= FLOW_STAT_REM_SEND
;
1190 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
1193 skge
->flow_status
= FLOW_STAT_NONE
;
1195 skge
->speed
= SPEED_1000
;
1198 if (!netif_carrier_ok(dev
))
1199 genesis_link_up(skge
);
1202 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1203 * Phy on for 100 or 10Mbit operation
1205 static void bcom_phy_init(struct skge_port
*skge
)
1207 struct skge_hw
*hw
= skge
->hw
;
1208 int port
= skge
->port
;
1210 u16 id1
, r
, ext
, ctl
;
1212 /* magic workaround patterns for Broadcom */
1213 static const struct {
1217 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1218 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1219 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1220 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1222 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1223 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1226 /* read Id from external PHY (all have the same address) */
1227 id1
= xm_phy_read(hw
, port
, PHY_XMAC_ID1
);
1229 /* Optimize MDIO transfer by suppressing preamble. */
1230 r
= xm_read16(hw
, port
, XM_MMU_CMD
);
1232 xm_write16(hw
, port
, XM_MMU_CMD
,r
);
1235 case PHY_BCOM_ID1_C0
:
1237 * Workaround BCOM Errata for the C0 type.
1238 * Write magic patterns to reserved registers.
1240 for (i
= 0; i
< ARRAY_SIZE(C0hack
); i
++)
1241 xm_phy_write(hw
, port
,
1242 C0hack
[i
].reg
, C0hack
[i
].val
);
1245 case PHY_BCOM_ID1_A1
:
1247 * Workaround BCOM Errata for the A1 type.
1248 * Write magic patterns to reserved registers.
1250 for (i
= 0; i
< ARRAY_SIZE(A1hack
); i
++)
1251 xm_phy_write(hw
, port
,
1252 A1hack
[i
].reg
, A1hack
[i
].val
);
1257 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1258 * Disable Power Management after reset.
1260 r
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
);
1261 r
|= PHY_B_AC_DIS_PM
;
1262 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
, r
);
1265 xm_read16(hw
, port
, XM_ISRC
);
1267 ext
= PHY_B_PEC_EN_LTR
; /* enable tx led */
1268 ctl
= PHY_CT_SP1000
; /* always 1000mbit */
1270 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1272 * Workaround BCOM Errata #1 for the C5 type.
1273 * 1000Base-T Link Acquisition Failure in Slave Mode
1274 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1276 u16 adv
= PHY_B_1000C_RD
;
1277 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1278 adv
|= PHY_B_1000C_AHD
;
1279 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1280 adv
|= PHY_B_1000C_AFD
;
1281 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, adv
);
1283 ctl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1285 if (skge
->duplex
== DUPLEX_FULL
)
1286 ctl
|= PHY_CT_DUP_MD
;
1287 /* Force to slave */
1288 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, PHY_B_1000C_MSE
);
1291 /* Set autonegotiation pause parameters */
1292 xm_phy_write(hw
, port
, PHY_BCOM_AUNE_ADV
,
1293 phy_pause_map
[skge
->flow_control
] | PHY_AN_CSMA
);
1295 /* Handle Jumbo frames */
1296 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
1297 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1298 PHY_B_AC_TX_TST
| PHY_B_AC_LONG_PACK
);
1300 ext
|= PHY_B_PEC_HIGH_LA
;
1304 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, ext
);
1305 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
, ctl
);
1307 /* Use link status change interrupt */
1308 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1311 static void xm_phy_init(struct skge_port
*skge
)
1313 struct skge_hw
*hw
= skge
->hw
;
1314 int port
= skge
->port
;
1317 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1318 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1319 ctrl
|= PHY_X_AN_HD
;
1320 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1321 ctrl
|= PHY_X_AN_FD
;
1323 ctrl
|= fiber_pause_map
[skge
->flow_control
];
1325 xm_phy_write(hw
, port
, PHY_XMAC_AUNE_ADV
, ctrl
);
1327 /* Restart Auto-negotiation */
1328 ctrl
= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1330 /* Set DuplexMode in Config register */
1331 if (skge
->duplex
== DUPLEX_FULL
)
1332 ctrl
|= PHY_CT_DUP_MD
;
1334 * Do NOT enable Auto-negotiation here. This would hold
1335 * the link down because no IDLEs are transmitted
1339 xm_phy_write(hw
, port
, PHY_XMAC_CTRL
, ctrl
);
1341 /* Poll PHY for status changes */
1342 mod_timer(&skge
->link_timer
, jiffies
+ LINK_HZ
);
1345 static void xm_check_link(struct net_device
*dev
)
1347 struct skge_port
*skge
= netdev_priv(dev
);
1348 struct skge_hw
*hw
= skge
->hw
;
1349 int port
= skge
->port
;
1352 /* read twice because of latch */
1353 (void) xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1354 status
= xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1356 if ((status
& PHY_ST_LSYNC
) == 0) {
1357 xm_link_down(hw
, port
);
1361 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1364 if (!(status
& PHY_ST_AN_OVER
))
1367 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1368 if (lpa
& PHY_B_AN_RF
) {
1369 printk(KERN_NOTICE PFX
"%s: remote fault\n",
1374 res
= xm_phy_read(hw
, port
, PHY_XMAC_RES_ABI
);
1376 /* Check Duplex mismatch */
1377 switch (res
& (PHY_X_RS_HD
| PHY_X_RS_FD
)) {
1379 skge
->duplex
= DUPLEX_FULL
;
1382 skge
->duplex
= DUPLEX_HALF
;
1385 printk(KERN_NOTICE PFX
"%s: duplex mismatch\n",
1390 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1391 if ((skge
->flow_control
== FLOW_MODE_SYMMETRIC
||
1392 skge
->flow_control
== FLOW_MODE_SYM_OR_REM
) &&
1393 (lpa
& PHY_X_P_SYM_MD
))
1394 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
1395 else if (skge
->flow_control
== FLOW_MODE_SYM_OR_REM
&&
1396 (lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_ASYM_MD
)
1397 /* Enable PAUSE receive, disable PAUSE transmit */
1398 skge
->flow_status
= FLOW_STAT_REM_SEND
;
1399 else if (skge
->flow_control
== FLOW_MODE_LOC_SEND
&&
1400 (lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_BOTH_MD
)
1401 /* Disable PAUSE receive, enable PAUSE transmit */
1402 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
1404 skge
->flow_status
= FLOW_STAT_NONE
;
1406 skge
->speed
= SPEED_1000
;
1409 if (!netif_carrier_ok(dev
))
1410 genesis_link_up(skge
);
1413 /* Poll to check for link coming up.
1414 * Since internal PHY is wired to a level triggered pin, can't
1415 * get an interrupt when carrier is detected.
1417 static void xm_link_timer(unsigned long arg
)
1419 struct skge_port
*skge
= (struct skge_port
*) arg
;
1420 struct net_device
*dev
= skge
->netdev
;
1421 struct skge_hw
*hw
= skge
->hw
;
1422 int port
= skge
->port
;
1424 if (!netif_running(dev
))
1427 if (netif_carrier_ok(dev
)) {
1428 xm_read16(hw
, port
, XM_ISRC
);
1429 if (!(xm_read16(hw
, port
, XM_ISRC
) & XM_IS_INP_ASS
))
1432 if (xm_read32(hw
, port
, XM_GP_PORT
) & XM_GP_INP_ASS
)
1434 xm_read16(hw
, port
, XM_ISRC
);
1435 if (xm_read16(hw
, port
, XM_ISRC
) & XM_IS_INP_ASS
)
1439 spin_lock(&hw
->phy_lock
);
1441 spin_unlock(&hw
->phy_lock
);
1444 if (netif_running(dev
))
1445 mod_timer(&skge
->link_timer
, jiffies
+ LINK_HZ
);
1448 static void genesis_mac_init(struct skge_hw
*hw
, int port
)
1450 struct net_device
*dev
= hw
->dev
[port
];
1451 struct skge_port
*skge
= netdev_priv(dev
);
1452 int jumbo
= hw
->dev
[port
]->mtu
> ETH_DATA_LEN
;
1455 const u8 zero
[6] = { 0 };
1457 for (i
= 0; i
< 10; i
++) {
1458 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
1460 if (skge_read16(hw
, SK_REG(port
, TX_MFF_CTRL1
)) & MFF_SET_MAC_RST
)
1465 printk(KERN_WARNING PFX
"%s: genesis reset failed\n", dev
->name
);
1468 /* Unreset the XMAC. */
1469 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_CLR_MAC_RST
);
1472 * Perform additional initialization for external PHYs,
1473 * namely for the 1000baseTX cards that use the XMAC's
1476 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1477 /* Take external Phy out of reset */
1478 r
= skge_read32(hw
, B2_GP_IO
);
1480 r
|= GP_DIR_0
|GP_IO_0
;
1482 r
|= GP_DIR_2
|GP_IO_2
;
1484 skge_write32(hw
, B2_GP_IO
, r
);
1486 /* Enable GMII interface */
1487 xm_write16(hw
, port
, XM_HW_CFG
, XM_HW_GMII_MD
);
1491 switch(hw
->phy_type
) {
1496 bcom_phy_init(skge
);
1497 bcom_check_link(hw
, port
);
1500 /* Set Station Address */
1501 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
1503 /* We don't use match addresses so clear */
1504 for (i
= 1; i
< 16; i
++)
1505 xm_outaddr(hw
, port
, XM_EXM(i
), zero
);
1507 /* Clear MIB counters */
1508 xm_write16(hw
, port
, XM_STAT_CMD
,
1509 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1510 /* Clear two times according to Errata #3 */
1511 xm_write16(hw
, port
, XM_STAT_CMD
,
1512 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1514 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1515 xm_write16(hw
, port
, XM_RX_HI_WM
, 1450);
1517 /* We don't need the FCS appended to the packet. */
1518 r
= XM_RX_LENERR_OK
| XM_RX_STRIP_FCS
;
1520 r
|= XM_RX_BIG_PK_OK
;
1522 if (skge
->duplex
== DUPLEX_HALF
) {
1524 * If in manual half duplex mode the other side might be in
1525 * full duplex mode, so ignore if a carrier extension is not seen
1526 * on frames received
1528 r
|= XM_RX_DIS_CEXT
;
1530 xm_write16(hw
, port
, XM_RX_CMD
, r
);
1533 /* We want short frames padded to 60 bytes. */
1534 xm_write16(hw
, port
, XM_TX_CMD
, XM_TX_AUTO_PAD
);
1537 * Bump up the transmit threshold. This helps hold off transmit
1538 * underruns when we're blasting traffic from both ports at once.
1540 xm_write16(hw
, port
, XM_TX_THR
, 512);
1543 * Enable the reception of all error frames. This is is
1544 * a necessary evil due to the design of the XMAC. The
1545 * XMAC's receive FIFO is only 8K in size, however jumbo
1546 * frames can be up to 9000 bytes in length. When bad
1547 * frame filtering is enabled, the XMAC's RX FIFO operates
1548 * in 'store and forward' mode. For this to work, the
1549 * entire frame has to fit into the FIFO, but that means
1550 * that jumbo frames larger than 8192 bytes will be
1551 * truncated. Disabling all bad frame filtering causes
1552 * the RX FIFO to operate in streaming mode, in which
1553 * case the XMAC will start transferring frames out of the
1554 * RX FIFO as soon as the FIFO threshold is reached.
1556 xm_write32(hw
, port
, XM_MODE
, XM_DEF_MODE
);
1560 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1561 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1562 * and 'Octets Rx OK Hi Cnt Ov'.
1564 xm_write32(hw
, port
, XM_RX_EV_MSK
, XMR_DEF_MSK
);
1567 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1568 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1569 * and 'Octets Tx OK Hi Cnt Ov'.
1571 xm_write32(hw
, port
, XM_TX_EV_MSK
, XMT_DEF_MSK
);
1573 /* Configure MAC arbiter */
1574 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
1576 /* configure timeout values */
1577 skge_write8(hw
, B3_MA_TOINI_RX1
, 72);
1578 skge_write8(hw
, B3_MA_TOINI_RX2
, 72);
1579 skge_write8(hw
, B3_MA_TOINI_TX1
, 72);
1580 skge_write8(hw
, B3_MA_TOINI_TX2
, 72);
1582 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
1583 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1584 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1585 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1587 /* Configure Rx MAC FIFO */
1588 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_CLR
);
1589 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_TIM_PAT
);
1590 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1592 /* Configure Tx MAC FIFO */
1593 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_CLR
);
1594 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_TX_CTRL_DEF
);
1595 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1598 /* Enable frame flushing if jumbo frames used */
1599 skge_write16(hw
, SK_REG(port
,RX_MFF_CTRL1
), MFF_ENA_FLUSH
);
1601 /* enable timeout timers if normal frames */
1602 skge_write16(hw
, B3_PA_CTRL
,
1603 (port
== 0) ? PA_ENA_TO_TX1
: PA_ENA_TO_TX2
);
1607 static void genesis_stop(struct skge_port
*skge
)
1609 struct skge_hw
*hw
= skge
->hw
;
1610 int port
= skge
->port
;
1613 genesis_reset(hw
, port
);
1615 /* Clear Tx packet arbiter timeout IRQ */
1616 skge_write16(hw
, B3_PA_CTRL
,
1617 port
== 0 ? PA_CLR_TO_TX1
: PA_CLR_TO_TX2
);
1620 * If the transfer sticks at the MAC the STOP command will not
1621 * terminate if we don't flush the XMAC's transmit FIFO !
1623 xm_write32(hw
, port
, XM_MODE
,
1624 xm_read32(hw
, port
, XM_MODE
)|XM_MD_FTF
);
1628 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_SET_MAC_RST
);
1630 /* For external PHYs there must be special handling */
1631 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1632 reg
= skge_read32(hw
, B2_GP_IO
);
1640 skge_write32(hw
, B2_GP_IO
, reg
);
1641 skge_read32(hw
, B2_GP_IO
);
1644 xm_write16(hw
, port
, XM_MMU_CMD
,
1645 xm_read16(hw
, port
, XM_MMU_CMD
)
1646 & ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
));
1648 xm_read16(hw
, port
, XM_MMU_CMD
);
1652 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
)
1654 struct skge_hw
*hw
= skge
->hw
;
1655 int port
= skge
->port
;
1657 unsigned long timeout
= jiffies
+ HZ
;
1659 xm_write16(hw
, port
,
1660 XM_STAT_CMD
, XM_SC_SNP_TXC
| XM_SC_SNP_RXC
);
1662 /* wait for update to complete */
1663 while (xm_read16(hw
, port
, XM_STAT_CMD
)
1664 & (XM_SC_SNP_TXC
| XM_SC_SNP_RXC
)) {
1665 if (time_after(jiffies
, timeout
))
1670 /* special case for 64 bit octet counter */
1671 data
[0] = (u64
) xm_read32(hw
, port
, XM_TXO_OK_HI
) << 32
1672 | xm_read32(hw
, port
, XM_TXO_OK_LO
);
1673 data
[1] = (u64
) xm_read32(hw
, port
, XM_RXO_OK_HI
) << 32
1674 | xm_read32(hw
, port
, XM_RXO_OK_LO
);
1676 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
1677 data
[i
] = xm_read32(hw
, port
, skge_stats
[i
].xmac_offset
);
1680 static void genesis_mac_intr(struct skge_hw
*hw
, int port
)
1682 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1683 u16 status
= xm_read16(hw
, port
, XM_ISRC
);
1685 if (netif_msg_intr(skge
))
1686 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
1687 skge
->netdev
->name
, status
);
1689 if (hw
->phy_type
== SK_PHY_XMAC
&&
1690 (status
& (XM_IS_INP_ASS
| XM_IS_LIPA_RC
)))
1691 xm_link_down(hw
, port
);
1693 if (status
& XM_IS_TXF_UR
) {
1694 xm_write32(hw
, port
, XM_MODE
, XM_MD_FTF
);
1695 ++skge
->net_stats
.tx_fifo_errors
;
1697 if (status
& XM_IS_RXF_OV
) {
1698 xm_write32(hw
, port
, XM_MODE
, XM_MD_FRF
);
1699 ++skge
->net_stats
.rx_fifo_errors
;
1703 static void genesis_link_up(struct skge_port
*skge
)
1705 struct skge_hw
*hw
= skge
->hw
;
1706 int port
= skge
->port
;
1710 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1713 * enabling pause frame reception is required for 1000BT
1714 * because the XMAC is not reset if the link is going down
1716 if (skge
->flow_status
== FLOW_STAT_NONE
||
1717 skge
->flow_status
== FLOW_STAT_LOC_SEND
)
1718 /* Disable Pause Frame Reception */
1719 cmd
|= XM_MMU_IGN_PF
;
1721 /* Enable Pause Frame Reception */
1722 cmd
&= ~XM_MMU_IGN_PF
;
1724 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1726 mode
= xm_read32(hw
, port
, XM_MODE
);
1727 if (skge
->flow_status
== FLOW_STAT_SYMMETRIC
||
1728 skge
->flow_status
== FLOW_STAT_LOC_SEND
) {
1730 * Configure Pause Frame Generation
1731 * Use internal and external Pause Frame Generation.
1732 * Sending pause frames is edge triggered.
1733 * Send a Pause frame with the maximum pause time if
1734 * internal oder external FIFO full condition occurs.
1735 * Send a zero pause time frame to re-start transmission.
1737 /* XM_PAUSE_DA = '010000C28001' (default) */
1738 /* XM_MAC_PTIME = 0xffff (maximum) */
1739 /* remember this value is defined in big endian (!) */
1740 xm_write16(hw
, port
, XM_MAC_PTIME
, 0xffff);
1742 mode
|= XM_PAUSE_MODE
;
1743 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_PAUSE
);
1746 * disable pause frame generation is required for 1000BT
1747 * because the XMAC is not reset if the link is going down
1749 /* Disable Pause Mode in Mode Register */
1750 mode
&= ~XM_PAUSE_MODE
;
1752 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_DIS_PAUSE
);
1755 xm_write32(hw
, port
, XM_MODE
, mode
);
1757 if (hw
->phy_type
!= SK_PHY_XMAC
)
1758 msk
|= XM_IS_INP_ASS
; /* disable GP0 interrupt bit */
1760 xm_write16(hw
, port
, XM_IMSK
, msk
);
1761 xm_read16(hw
, port
, XM_ISRC
);
1763 /* get MMU Command Reg. */
1764 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1765 if (hw
->phy_type
!= SK_PHY_XMAC
&& skge
->duplex
== DUPLEX_FULL
)
1766 cmd
|= XM_MMU_GMII_FD
;
1769 * Workaround BCOM Errata (#10523) for all BCom Phys
1770 * Enable Power Management after link up
1772 if (hw
->phy_type
== SK_PHY_BCOM
) {
1773 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1774 xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
)
1775 & ~PHY_B_AC_DIS_PM
);
1776 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1780 xm_write16(hw
, port
, XM_MMU_CMD
,
1781 cmd
| XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1786 static inline void bcom_phy_intr(struct skge_port
*skge
)
1788 struct skge_hw
*hw
= skge
->hw
;
1789 int port
= skge
->port
;
1792 isrc
= xm_phy_read(hw
, port
, PHY_BCOM_INT_STAT
);
1793 if (netif_msg_intr(skge
))
1794 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x\n",
1795 skge
->netdev
->name
, isrc
);
1797 if (isrc
& PHY_B_IS_PSE
)
1798 printk(KERN_ERR PFX
"%s: uncorrectable pair swap error\n",
1799 hw
->dev
[port
]->name
);
1801 /* Workaround BCom Errata:
1802 * enable and disable loopback mode if "NO HCD" occurs.
1804 if (isrc
& PHY_B_IS_NO_HDCL
) {
1805 u16 ctrl
= xm_phy_read(hw
, port
, PHY_BCOM_CTRL
);
1806 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1807 ctrl
| PHY_CT_LOOP
);
1808 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1809 ctrl
& ~PHY_CT_LOOP
);
1812 if (isrc
& (PHY_B_IS_AN_PR
| PHY_B_IS_LST_CHANGE
))
1813 bcom_check_link(hw
, port
);
1817 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
1821 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
1822 gma_write16(hw
, port
, GM_SMI_CTRL
,
1823 GM_SMI_CT_PHY_AD(hw
->phy_addr
) | GM_SMI_CT_REG_AD(reg
));
1824 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1827 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
1831 printk(KERN_WARNING PFX
"%s: phy write timeout\n",
1832 hw
->dev
[port
]->name
);
1836 static int __gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
1840 gma_write16(hw
, port
, GM_SMI_CTRL
,
1841 GM_SMI_CT_PHY_AD(hw
->phy_addr
)
1842 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
1844 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1846 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
)
1852 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
1856 static u16
gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
1859 if (__gm_phy_read(hw
, port
, reg
, &v
))
1860 printk(KERN_WARNING PFX
"%s: phy read timeout\n",
1861 hw
->dev
[port
]->name
);
1865 /* Marvell Phy Initialization */
1866 static void yukon_init(struct skge_hw
*hw
, int port
)
1868 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1869 u16 ctrl
, ct1000
, adv
;
1871 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1872 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
1874 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
1875 PHY_M_EC_MAC_S_MSK
);
1876 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
1878 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1880 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
1883 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
1884 if (skge
->autoneg
== AUTONEG_DISABLE
)
1885 ctrl
&= ~PHY_CT_ANE
;
1887 ctrl
|= PHY_CT_RESET
;
1888 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1894 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1896 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1897 ct1000
|= PHY_M_1000C_AFD
;
1898 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1899 ct1000
|= PHY_M_1000C_AHD
;
1900 if (skge
->advertising
& ADVERTISED_100baseT_Full
)
1901 adv
|= PHY_M_AN_100_FD
;
1902 if (skge
->advertising
& ADVERTISED_100baseT_Half
)
1903 adv
|= PHY_M_AN_100_HD
;
1904 if (skge
->advertising
& ADVERTISED_10baseT_Full
)
1905 adv
|= PHY_M_AN_10_FD
;
1906 if (skge
->advertising
& ADVERTISED_10baseT_Half
)
1907 adv
|= PHY_M_AN_10_HD
;
1909 /* Set Flow-control capabilities */
1910 adv
|= phy_pause_map
[skge
->flow_control
];
1912 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1913 adv
|= PHY_M_AN_1000X_AFD
;
1914 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1915 adv
|= PHY_M_AN_1000X_AHD
;
1917 adv
|= fiber_pause_map
[skge
->flow_control
];
1920 /* Restart Auto-negotiation */
1921 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1923 /* forced speed/duplex settings */
1924 ct1000
= PHY_M_1000C_MSE
;
1926 if (skge
->duplex
== DUPLEX_FULL
)
1927 ctrl
|= PHY_CT_DUP_MD
;
1929 switch (skge
->speed
) {
1931 ctrl
|= PHY_CT_SP1000
;
1934 ctrl
|= PHY_CT_SP100
;
1938 ctrl
|= PHY_CT_RESET
;
1941 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
1943 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
1944 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1946 /* Enable phy interrupt on autonegotiation complete (or link up) */
1947 if (skge
->autoneg
== AUTONEG_ENABLE
)
1948 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_MSK
);
1950 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
1953 static void yukon_reset(struct skge_hw
*hw
, int port
)
1955 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);/* disable PHY IRQs */
1956 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
1957 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
1958 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
1959 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
1961 gma_write16(hw
, port
, GM_RX_CTRL
,
1962 gma_read16(hw
, port
, GM_RX_CTRL
)
1963 | GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
1966 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1967 static int is_yukon_lite_a0(struct skge_hw
*hw
)
1972 if (hw
->chip_id
!= CHIP_ID_YUKON
)
1975 reg
= skge_read32(hw
, B2_FAR
);
1976 skge_write8(hw
, B2_FAR
+ 3, 0xff);
1977 ret
= (skge_read8(hw
, B2_FAR
+ 3) != 0);
1978 skge_write32(hw
, B2_FAR
, reg
);
1982 static void yukon_mac_init(struct skge_hw
*hw
, int port
)
1984 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1987 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
1989 /* WA code for COMA mode -- set PHY reset */
1990 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1991 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
1992 reg
= skge_read32(hw
, B2_GP_IO
);
1993 reg
|= GP_DIR_9
| GP_IO_9
;
1994 skge_write32(hw
, B2_GP_IO
, reg
);
1998 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1999 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2001 /* WA code for COMA mode -- clear PHY reset */
2002 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
2003 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
2004 reg
= skge_read32(hw
, B2_GP_IO
);
2007 skge_write32(hw
, B2_GP_IO
, reg
);
2010 /* Set hardware config mode */
2011 reg
= GPC_INT_POL_HI
| GPC_DIS_FC
| GPC_DIS_SLEEP
|
2012 GPC_ENA_XC
| GPC_ANEG_ADV_ALL_M
| GPC_ENA_PAUSE
;
2013 reg
|= hw
->copper
? GPC_HWCFG_GMII_COP
: GPC_HWCFG_GMII_FIB
;
2015 /* Clear GMC reset */
2016 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_SET
);
2017 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_CLR
);
2018 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
| GMC_RST_CLR
);
2020 if (skge
->autoneg
== AUTONEG_DISABLE
) {
2021 reg
= GM_GPCR_AU_ALL_DIS
;
2022 gma_write16(hw
, port
, GM_GP_CTRL
,
2023 gma_read16(hw
, port
, GM_GP_CTRL
) | reg
);
2025 switch (skge
->speed
) {
2027 reg
&= ~GM_GPCR_SPEED_100
;
2028 reg
|= GM_GPCR_SPEED_1000
;
2031 reg
&= ~GM_GPCR_SPEED_1000
;
2032 reg
|= GM_GPCR_SPEED_100
;
2035 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
2039 if (skge
->duplex
== DUPLEX_FULL
)
2040 reg
|= GM_GPCR_DUP_FULL
;
2042 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
2044 switch (skge
->flow_control
) {
2045 case FLOW_MODE_NONE
:
2046 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2047 reg
|= GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
2049 case FLOW_MODE_LOC_SEND
:
2050 /* disable Rx flow-control */
2051 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
2053 case FLOW_MODE_SYMMETRIC
:
2054 case FLOW_MODE_SYM_OR_REM
:
2055 /* enable Tx & Rx flow-control */
2059 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2060 skge_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2062 yukon_init(hw
, port
);
2065 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
2066 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
2068 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
2069 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8*i
);
2070 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
2072 /* transmit control */
2073 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
2075 /* receive control reg: unicast + multicast + no FCS */
2076 gma_write16(hw
, port
, GM_RX_CTRL
,
2077 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
2079 /* transmit flow control */
2080 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
2082 /* transmit parameter */
2083 gma_write16(hw
, port
, GM_TX_PARAM
,
2084 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
2085 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
2086 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
));
2088 /* serial mode register */
2089 reg
= GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2090 if (hw
->dev
[port
]->mtu
> 1500)
2091 reg
|= GM_SMOD_JUMBO_ENA
;
2093 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
2095 /* physical address: used for pause frames */
2096 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
2097 /* virtual address for data */
2098 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
2100 /* enable interrupt mask for counter overflows */
2101 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
2102 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
2103 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
2105 /* Initialize Mac Fifo */
2107 /* Configure Rx MAC FIFO */
2108 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), RX_FF_FL_DEF_MSK
);
2109 reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
2111 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2112 if (is_yukon_lite_a0(hw
))
2113 reg
&= ~GMF_RX_F_FL_ON
;
2115 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
2116 skge_write16(hw
, SK_REG(port
, RX_GMF_CTRL_T
), reg
);
2118 * because Pause Packet Truncation in GMAC is not working
2119 * we have to increase the Flush Threshold to 64 bytes
2120 * in order to flush pause packets in Rx FIFO on Yukon-1
2122 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
2124 /* Configure Tx MAC FIFO */
2125 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
2126 skge_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
2129 /* Go into power down mode */
2130 static void yukon_suspend(struct skge_hw
*hw
, int port
)
2134 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2135 ctrl
|= PHY_M_PC_POL_R_DIS
;
2136 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
2138 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2139 ctrl
|= PHY_CT_RESET
;
2140 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2142 /* switch IEEE compatible power down mode on */
2143 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2144 ctrl
|= PHY_CT_PDOWN
;
2145 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2148 static void yukon_stop(struct skge_port
*skge
)
2150 struct skge_hw
*hw
= skge
->hw
;
2151 int port
= skge
->port
;
2153 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
2154 yukon_reset(hw
, port
);
2156 gma_write16(hw
, port
, GM_GP_CTRL
,
2157 gma_read16(hw
, port
, GM_GP_CTRL
)
2158 & ~(GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
));
2159 gma_read16(hw
, port
, GM_GP_CTRL
);
2161 yukon_suspend(hw
, port
);
2163 /* set GPHY Control reset */
2164 skge_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
2165 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2168 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
)
2170 struct skge_hw
*hw
= skge
->hw
;
2171 int port
= skge
->port
;
2174 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2175 | gma_read32(hw
, port
, GM_TXO_OK_LO
);
2176 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2177 | gma_read32(hw
, port
, GM_RXO_OK_LO
);
2179 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
2180 data
[i
] = gma_read32(hw
, port
,
2181 skge_stats
[i
].gma_offset
);
2184 static void yukon_mac_intr(struct skge_hw
*hw
, int port
)
2186 struct net_device
*dev
= hw
->dev
[port
];
2187 struct skge_port
*skge
= netdev_priv(dev
);
2188 u8 status
= skge_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2190 if (netif_msg_intr(skge
))
2191 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
2194 if (status
& GM_IS_RX_FF_OR
) {
2195 ++skge
->net_stats
.rx_fifo_errors
;
2196 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2199 if (status
& GM_IS_TX_FF_UR
) {
2200 ++skge
->net_stats
.tx_fifo_errors
;
2201 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2206 static u16
yukon_speed(const struct skge_hw
*hw
, u16 aux
)
2208 switch (aux
& PHY_M_PS_SPEED_MSK
) {
2209 case PHY_M_PS_SPEED_1000
:
2211 case PHY_M_PS_SPEED_100
:
2218 static void yukon_link_up(struct skge_port
*skge
)
2220 struct skge_hw
*hw
= skge
->hw
;
2221 int port
= skge
->port
;
2224 /* Enable Transmit FIFO Underrun */
2225 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
2227 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2228 if (skge
->duplex
== DUPLEX_FULL
|| skge
->autoneg
== AUTONEG_ENABLE
)
2229 reg
|= GM_GPCR_DUP_FULL
;
2232 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
2233 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2235 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
2239 static void yukon_link_down(struct skge_port
*skge
)
2241 struct skge_hw
*hw
= skge
->hw
;
2242 int port
= skge
->port
;
2245 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2246 ctrl
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2247 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
2249 if (skge
->flow_status
== FLOW_STAT_REM_SEND
) {
2250 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2251 ctrl
|= PHY_M_AN_ASP
;
2252 /* restore Asymmetric Pause bit */
2253 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, ctrl
);
2256 skge_link_down(skge
);
2258 yukon_init(hw
, port
);
2261 static void yukon_phy_intr(struct skge_port
*skge
)
2263 struct skge_hw
*hw
= skge
->hw
;
2264 int port
= skge
->port
;
2265 const char *reason
= NULL
;
2266 u16 istatus
, phystat
;
2268 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2269 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2271 if (netif_msg_intr(skge
))
2272 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x 0x%x\n",
2273 skge
->netdev
->name
, istatus
, phystat
);
2275 if (istatus
& PHY_M_IS_AN_COMPL
) {
2276 if (gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
)
2278 reason
= "remote fault";
2282 if (gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
2283 reason
= "master/slave fault";
2287 if (!(phystat
& PHY_M_PS_SPDUP_RES
)) {
2288 reason
= "speed/duplex";
2292 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
)
2293 ? DUPLEX_FULL
: DUPLEX_HALF
;
2294 skge
->speed
= yukon_speed(hw
, phystat
);
2296 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2297 switch (phystat
& PHY_M_PS_PAUSE_MSK
) {
2298 case PHY_M_PS_PAUSE_MSK
:
2299 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
2301 case PHY_M_PS_RX_P_EN
:
2302 skge
->flow_status
= FLOW_STAT_REM_SEND
;
2304 case PHY_M_PS_TX_P_EN
:
2305 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
2308 skge
->flow_status
= FLOW_STAT_NONE
;
2311 if (skge
->flow_status
== FLOW_STAT_NONE
||
2312 (skge
->speed
< SPEED_1000
&& skge
->duplex
== DUPLEX_HALF
))
2313 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2315 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2316 yukon_link_up(skge
);
2320 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2321 skge
->speed
= yukon_speed(hw
, phystat
);
2323 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2324 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2325 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2326 if (phystat
& PHY_M_PS_LINK_UP
)
2327 yukon_link_up(skge
);
2329 yukon_link_down(skge
);
2333 printk(KERN_ERR PFX
"%s: autonegotiation failed (%s)\n",
2334 skge
->netdev
->name
, reason
);
2336 /* XXX restart autonegotiation? */
2339 static void skge_phy_reset(struct skge_port
*skge
)
2341 struct skge_hw
*hw
= skge
->hw
;
2342 int port
= skge
->port
;
2343 struct net_device
*dev
= hw
->dev
[port
];
2345 netif_stop_queue(skge
->netdev
);
2346 netif_carrier_off(skge
->netdev
);
2348 spin_lock_bh(&hw
->phy_lock
);
2349 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2350 genesis_reset(hw
, port
);
2351 genesis_mac_init(hw
, port
);
2353 yukon_reset(hw
, port
);
2354 yukon_init(hw
, port
);
2356 spin_unlock_bh(&hw
->phy_lock
);
2358 dev
->set_multicast_list(dev
);
2361 /* Basic MII support */
2362 static int skge_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2364 struct mii_ioctl_data
*data
= if_mii(ifr
);
2365 struct skge_port
*skge
= netdev_priv(dev
);
2366 struct skge_hw
*hw
= skge
->hw
;
2367 int err
= -EOPNOTSUPP
;
2369 if (!netif_running(dev
))
2370 return -ENODEV
; /* Phy still in reset */
2374 data
->phy_id
= hw
->phy_addr
;
2379 spin_lock_bh(&hw
->phy_lock
);
2380 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2381 err
= __xm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2383 err
= __gm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2384 spin_unlock_bh(&hw
->phy_lock
);
2385 data
->val_out
= val
;
2390 if (!capable(CAP_NET_ADMIN
))
2393 spin_lock_bh(&hw
->phy_lock
);
2394 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2395 err
= xm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2398 err
= gm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2400 spin_unlock_bh(&hw
->phy_lock
);
2406 static void skge_ramset(struct skge_hw
*hw
, u16 q
, u32 start
, size_t len
)
2412 end
= start
+ len
- 1;
2414 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
2415 skge_write32(hw
, RB_ADDR(q
, RB_START
), start
);
2416 skge_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
2417 skge_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
2418 skge_write32(hw
, RB_ADDR(q
, RB_END
), end
);
2420 if (q
== Q_R1
|| q
== Q_R2
) {
2421 /* Set thresholds on receive queue's */
2422 skge_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
),
2424 skge_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
),
2427 /* Enable store & forward on Tx queue's because
2428 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2430 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
2433 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
2436 /* Setup Bus Memory Interface */
2437 static void skge_qset(struct skge_port
*skge
, u16 q
,
2438 const struct skge_element
*e
)
2440 struct skge_hw
*hw
= skge
->hw
;
2441 u32 watermark
= 0x600;
2442 u64 base
= skge
->dma
+ (e
->desc
- skge
->mem
);
2444 /* optimization to reduce window on 32bit/33mhz */
2445 if ((skge_read16(hw
, B0_CTST
) & (CS_BUS_CLOCK
| CS_BUS_SLOT_SZ
)) == 0)
2448 skge_write32(hw
, Q_ADDR(q
, Q_CSR
), CSR_CLR_RESET
);
2449 skge_write32(hw
, Q_ADDR(q
, Q_F
), watermark
);
2450 skge_write32(hw
, Q_ADDR(q
, Q_DA_H
), (u32
)(base
>> 32));
2451 skge_write32(hw
, Q_ADDR(q
, Q_DA_L
), (u32
)base
);
2454 static int skge_up(struct net_device
*dev
)
2456 struct skge_port
*skge
= netdev_priv(dev
);
2457 struct skge_hw
*hw
= skge
->hw
;
2458 int port
= skge
->port
;
2459 u32 chunk
, ram_addr
;
2460 size_t rx_size
, tx_size
;
2463 if (!is_valid_ether_addr(dev
->dev_addr
))
2466 if (netif_msg_ifup(skge
))
2467 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
2469 if (dev
->mtu
> RX_BUF_SIZE
)
2470 skge
->rx_buf_size
= dev
->mtu
+ ETH_HLEN
;
2472 skge
->rx_buf_size
= RX_BUF_SIZE
;
2475 rx_size
= skge
->rx_ring
.count
* sizeof(struct skge_rx_desc
);
2476 tx_size
= skge
->tx_ring
.count
* sizeof(struct skge_tx_desc
);
2477 skge
->mem_size
= tx_size
+ rx_size
;
2478 skge
->mem
= pci_alloc_consistent(hw
->pdev
, skge
->mem_size
, &skge
->dma
);
2482 BUG_ON(skge
->dma
& 7);
2484 if ((u64
)skge
->dma
>> 32 != ((u64
) skge
->dma
+ skge
->mem_size
) >> 32) {
2485 dev_err(&hw
->pdev
->dev
, "pci_alloc_consistent region crosses 4G boundary\n");
2490 memset(skge
->mem
, 0, skge
->mem_size
);
2492 err
= skge_ring_alloc(&skge
->rx_ring
, skge
->mem
, skge
->dma
);
2496 err
= skge_rx_fill(dev
);
2500 err
= skge_ring_alloc(&skge
->tx_ring
, skge
->mem
+ rx_size
,
2501 skge
->dma
+ rx_size
);
2505 /* Initialize MAC */
2506 spin_lock_bh(&hw
->phy_lock
);
2507 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2508 genesis_mac_init(hw
, port
);
2510 yukon_mac_init(hw
, port
);
2511 spin_unlock_bh(&hw
->phy_lock
);
2513 /* Configure RAMbuffers */
2514 chunk
= hw
->ram_size
/ ((hw
->ports
+ 1)*2);
2515 ram_addr
= hw
->ram_offset
+ 2 * chunk
* port
;
2517 skge_ramset(hw
, rxqaddr
[port
], ram_addr
, chunk
);
2518 skge_qset(skge
, rxqaddr
[port
], skge
->rx_ring
.to_clean
);
2520 BUG_ON(skge
->tx_ring
.to_use
!= skge
->tx_ring
.to_clean
);
2521 skge_ramset(hw
, txqaddr
[port
], ram_addr
+chunk
, chunk
);
2522 skge_qset(skge
, txqaddr
[port
], skge
->tx_ring
.to_use
);
2524 /* Start receiver BMU */
2526 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_START
| CSR_IRQ_CL_F
);
2527 skge_led(skge
, LED_MODE_ON
);
2529 spin_lock_irq(&hw
->hw_lock
);
2530 hw
->intr_mask
|= portmask
[port
];
2531 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2532 spin_unlock_irq(&hw
->hw_lock
);
2534 napi_enable(&skge
->napi
);
2538 skge_rx_clean(skge
);
2539 kfree(skge
->rx_ring
.start
);
2541 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2547 static int skge_down(struct net_device
*dev
)
2549 struct skge_port
*skge
= netdev_priv(dev
);
2550 struct skge_hw
*hw
= skge
->hw
;
2551 int port
= skge
->port
;
2553 if (skge
->mem
== NULL
)
2556 if (netif_msg_ifdown(skge
))
2557 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
2559 netif_stop_queue(dev
);
2561 if (hw
->chip_id
== CHIP_ID_GENESIS
&& hw
->phy_type
== SK_PHY_XMAC
)
2562 del_timer_sync(&skge
->link_timer
);
2564 napi_disable(&skge
->napi
);
2565 netif_carrier_off(dev
);
2567 spin_lock_irq(&hw
->hw_lock
);
2568 hw
->intr_mask
&= ~portmask
[port
];
2569 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2570 spin_unlock_irq(&hw
->hw_lock
);
2572 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
2573 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2578 /* Stop transmitter */
2579 skge_write8(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_STOP
);
2580 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
2581 RB_RST_SET
|RB_DIS_OP_MD
);
2584 /* Disable Force Sync bit and Enable Alloc bit */
2585 skge_write8(hw
, SK_REG(port
, TXA_CTRL
),
2586 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
2588 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2589 skge_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
2590 skge_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
2592 /* Reset PCI FIFO */
2593 skge_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2594 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
2596 /* Reset the RAM Buffer async Tx queue */
2597 skge_write8(hw
, RB_ADDR(port
== 0 ? Q_XA1
: Q_XA2
, RB_CTRL
), RB_RST_SET
);
2599 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_STOP
);
2600 skge_write32(hw
, RB_ADDR(port
? Q_R2
: Q_R1
, RB_CTRL
),
2601 RB_RST_SET
|RB_DIS_OP_MD
);
2602 skge_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2604 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2605 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_SET
);
2606 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_SET
);
2608 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
2609 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
2612 skge_led(skge
, LED_MODE_OFF
);
2614 netif_tx_lock_bh(dev
);
2616 netif_tx_unlock_bh(dev
);
2618 skge_rx_clean(skge
);
2620 kfree(skge
->rx_ring
.start
);
2621 kfree(skge
->tx_ring
.start
);
2622 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2627 static inline int skge_avail(const struct skge_ring
*ring
)
2630 return ((ring
->to_clean
> ring
->to_use
) ? 0 : ring
->count
)
2631 + (ring
->to_clean
- ring
->to_use
) - 1;
2634 static int skge_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
2636 struct skge_port
*skge
= netdev_priv(dev
);
2637 struct skge_hw
*hw
= skge
->hw
;
2638 struct skge_element
*e
;
2639 struct skge_tx_desc
*td
;
2644 if (skb_padto(skb
, ETH_ZLEN
))
2645 return NETDEV_TX_OK
;
2647 if (unlikely(skge_avail(&skge
->tx_ring
) < skb_shinfo(skb
)->nr_frags
+ 1))
2648 return NETDEV_TX_BUSY
;
2650 e
= skge
->tx_ring
.to_use
;
2652 BUG_ON(td
->control
& BMU_OWN
);
2654 len
= skb_headlen(skb
);
2655 map
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2656 pci_unmap_addr_set(e
, mapaddr
, map
);
2657 pci_unmap_len_set(e
, maplen
, len
);
2660 td
->dma_hi
= map
>> 32;
2662 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2663 const int offset
= skb_transport_offset(skb
);
2665 /* This seems backwards, but it is what the sk98lin
2666 * does. Looks like hardware is wrong?
2668 if (ipip_hdr(skb
)->protocol
== IPPROTO_UDP
2669 && hw
->chip_rev
== 0 && hw
->chip_id
== CHIP_ID_YUKON
)
2670 control
= BMU_TCP_CHECK
;
2672 control
= BMU_UDP_CHECK
;
2675 td
->csum_start
= offset
;
2676 td
->csum_write
= offset
+ skb
->csum_offset
;
2678 control
= BMU_CHECK
;
2680 if (!skb_shinfo(skb
)->nr_frags
) /* single buffer i.e. no fragments */
2681 control
|= BMU_EOF
| BMU_IRQ_EOF
;
2683 struct skge_tx_desc
*tf
= td
;
2685 control
|= BMU_STFWD
;
2686 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2687 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2689 map
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
2690 frag
->size
, PCI_DMA_TODEVICE
);
2695 BUG_ON(tf
->control
& BMU_OWN
);
2698 tf
->dma_hi
= (u64
) map
>> 32;
2699 pci_unmap_addr_set(e
, mapaddr
, map
);
2700 pci_unmap_len_set(e
, maplen
, frag
->size
);
2702 tf
->control
= BMU_OWN
| BMU_SW
| control
| frag
->size
;
2704 tf
->control
|= BMU_EOF
| BMU_IRQ_EOF
;
2706 /* Make sure all the descriptors written */
2708 td
->control
= BMU_OWN
| BMU_SW
| BMU_STF
| control
| len
;
2711 skge_write8(hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_START
);
2713 if (unlikely(netif_msg_tx_queued(skge
)))
2714 printk(KERN_DEBUG
"%s: tx queued, slot %td, len %d\n",
2715 dev
->name
, e
- skge
->tx_ring
.start
, skb
->len
);
2717 skge
->tx_ring
.to_use
= e
->next
;
2720 if (skge_avail(&skge
->tx_ring
) <= TX_LOW_WATER
) {
2721 pr_debug("%s: transmit queue full\n", dev
->name
);
2722 netif_stop_queue(dev
);
2725 dev
->trans_start
= jiffies
;
2727 return NETDEV_TX_OK
;
2731 /* Free resources associated with this reing element */
2732 static void skge_tx_free(struct skge_port
*skge
, struct skge_element
*e
,
2735 struct pci_dev
*pdev
= skge
->hw
->pdev
;
2737 /* skb header vs. fragment */
2738 if (control
& BMU_STF
)
2739 pci_unmap_single(pdev
, pci_unmap_addr(e
, mapaddr
),
2740 pci_unmap_len(e
, maplen
),
2743 pci_unmap_page(pdev
, pci_unmap_addr(e
, mapaddr
),
2744 pci_unmap_len(e
, maplen
),
2747 if (control
& BMU_EOF
) {
2748 if (unlikely(netif_msg_tx_done(skge
)))
2749 printk(KERN_DEBUG PFX
"%s: tx done slot %td\n",
2750 skge
->netdev
->name
, e
- skge
->tx_ring
.start
);
2752 dev_kfree_skb(e
->skb
);
2756 /* Free all buffers in transmit ring */
2757 static void skge_tx_clean(struct net_device
*dev
)
2759 struct skge_port
*skge
= netdev_priv(dev
);
2760 struct skge_element
*e
;
2762 for (e
= skge
->tx_ring
.to_clean
; e
!= skge
->tx_ring
.to_use
; e
= e
->next
) {
2763 struct skge_tx_desc
*td
= e
->desc
;
2764 skge_tx_free(skge
, e
, td
->control
);
2768 skge
->tx_ring
.to_clean
= e
;
2769 netif_wake_queue(dev
);
2772 static void skge_tx_timeout(struct net_device
*dev
)
2774 struct skge_port
*skge
= netdev_priv(dev
);
2776 if (netif_msg_timer(skge
))
2777 printk(KERN_DEBUG PFX
"%s: tx timeout\n", dev
->name
);
2779 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_STOP
);
2783 static int skge_change_mtu(struct net_device
*dev
, int new_mtu
)
2787 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2790 if (!netif_running(dev
)) {
2806 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2808 static void genesis_add_filter(u8 filter
[8], const u8
*addr
)
2812 crc
= ether_crc_le(ETH_ALEN
, addr
);
2814 filter
[bit
/8] |= 1 << (bit
%8);
2817 static void genesis_set_multicast(struct net_device
*dev
)
2819 struct skge_port
*skge
= netdev_priv(dev
);
2820 struct skge_hw
*hw
= skge
->hw
;
2821 int port
= skge
->port
;
2822 int i
, count
= dev
->mc_count
;
2823 struct dev_mc_list
*list
= dev
->mc_list
;
2827 mode
= xm_read32(hw
, port
, XM_MODE
);
2828 mode
|= XM_MD_ENA_HASH
;
2829 if (dev
->flags
& IFF_PROMISC
)
2830 mode
|= XM_MD_ENA_PROM
;
2832 mode
&= ~XM_MD_ENA_PROM
;
2834 if (dev
->flags
& IFF_ALLMULTI
)
2835 memset(filter
, 0xff, sizeof(filter
));
2837 memset(filter
, 0, sizeof(filter
));
2839 if (skge
->flow_status
== FLOW_STAT_REM_SEND
2840 || skge
->flow_status
== FLOW_STAT_SYMMETRIC
)
2841 genesis_add_filter(filter
, pause_mc_addr
);
2843 for (i
= 0; list
&& i
< count
; i
++, list
= list
->next
)
2844 genesis_add_filter(filter
, list
->dmi_addr
);
2847 xm_write32(hw
, port
, XM_MODE
, mode
);
2848 xm_outhash(hw
, port
, XM_HSM
, filter
);
2851 static void yukon_add_filter(u8 filter
[8], const u8
*addr
)
2853 u32 bit
= ether_crc(ETH_ALEN
, addr
) & 0x3f;
2854 filter
[bit
/8] |= 1 << (bit
%8);
2857 static void yukon_set_multicast(struct net_device
*dev
)
2859 struct skge_port
*skge
= netdev_priv(dev
);
2860 struct skge_hw
*hw
= skge
->hw
;
2861 int port
= skge
->port
;
2862 struct dev_mc_list
*list
= dev
->mc_list
;
2863 int rx_pause
= (skge
->flow_status
== FLOW_STAT_REM_SEND
2864 || skge
->flow_status
== FLOW_STAT_SYMMETRIC
);
2868 memset(filter
, 0, sizeof(filter
));
2870 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2871 reg
|= GM_RXCR_UCF_ENA
;
2873 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2874 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2875 else if (dev
->flags
& IFF_ALLMULTI
) /* all multicast */
2876 memset(filter
, 0xff, sizeof(filter
));
2877 else if (dev
->mc_count
== 0 && !rx_pause
)/* no multicast */
2878 reg
&= ~GM_RXCR_MCF_ENA
;
2881 reg
|= GM_RXCR_MCF_ENA
;
2884 yukon_add_filter(filter
, pause_mc_addr
);
2886 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
2887 yukon_add_filter(filter
, list
->dmi_addr
);
2891 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2892 (u16
)filter
[0] | ((u16
)filter
[1] << 8));
2893 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2894 (u16
)filter
[2] | ((u16
)filter
[3] << 8));
2895 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2896 (u16
)filter
[4] | ((u16
)filter
[5] << 8));
2897 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2898 (u16
)filter
[6] | ((u16
)filter
[7] << 8));
2900 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2903 static inline u16
phy_length(const struct skge_hw
*hw
, u32 status
)
2905 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2906 return status
>> XMR_FS_LEN_SHIFT
;
2908 return status
>> GMR_FS_LEN_SHIFT
;
2911 static inline int bad_phy_status(const struct skge_hw
*hw
, u32 status
)
2913 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2914 return (status
& (XMR_FS_ERR
| XMR_FS_2L_VLAN
)) != 0;
2916 return (status
& GMR_FS_ANY_ERR
) ||
2917 (status
& GMR_FS_RX_OK
) == 0;
2921 /* Get receive buffer from descriptor.
2922 * Handles copy of small buffers and reallocation failures
2924 static struct sk_buff
*skge_rx_get(struct net_device
*dev
,
2925 struct skge_element
*e
,
2926 u32 control
, u32 status
, u16 csum
)
2928 struct skge_port
*skge
= netdev_priv(dev
);
2929 struct sk_buff
*skb
;
2930 u16 len
= control
& BMU_BBC
;
2932 if (unlikely(netif_msg_rx_status(skge
)))
2933 printk(KERN_DEBUG PFX
"%s: rx slot %td status 0x%x len %d\n",
2934 dev
->name
, e
- skge
->rx_ring
.start
,
2937 if (len
> skge
->rx_buf_size
)
2940 if ((control
& (BMU_EOF
|BMU_STF
)) != (BMU_STF
|BMU_EOF
))
2943 if (bad_phy_status(skge
->hw
, status
))
2946 if (phy_length(skge
->hw
, status
) != len
)
2949 if (len
< RX_COPY_THRESHOLD
) {
2950 skb
= netdev_alloc_skb(dev
, len
+ 2);
2954 skb_reserve(skb
, 2);
2955 pci_dma_sync_single_for_cpu(skge
->hw
->pdev
,
2956 pci_unmap_addr(e
, mapaddr
),
2957 len
, PCI_DMA_FROMDEVICE
);
2958 skb_copy_from_linear_data(e
->skb
, skb
->data
, len
);
2959 pci_dma_sync_single_for_device(skge
->hw
->pdev
,
2960 pci_unmap_addr(e
, mapaddr
),
2961 len
, PCI_DMA_FROMDEVICE
);
2962 skge_rx_reuse(e
, skge
->rx_buf_size
);
2964 struct sk_buff
*nskb
;
2965 nskb
= netdev_alloc_skb(dev
, skge
->rx_buf_size
+ NET_IP_ALIGN
);
2969 skb_reserve(nskb
, NET_IP_ALIGN
);
2970 pci_unmap_single(skge
->hw
->pdev
,
2971 pci_unmap_addr(e
, mapaddr
),
2972 pci_unmap_len(e
, maplen
),
2973 PCI_DMA_FROMDEVICE
);
2975 prefetch(skb
->data
);
2976 skge_rx_setup(skge
, e
, nskb
, skge
->rx_buf_size
);
2980 if (skge
->rx_csum
) {
2982 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2985 skb
->protocol
= eth_type_trans(skb
, dev
);
2990 if (netif_msg_rx_err(skge
))
2991 printk(KERN_DEBUG PFX
"%s: rx err, slot %td control 0x%x status 0x%x\n",
2992 dev
->name
, e
- skge
->rx_ring
.start
,
2995 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
) {
2996 if (status
& (XMR_FS_RUNT
|XMR_FS_LNG_ERR
))
2997 skge
->net_stats
.rx_length_errors
++;
2998 if (status
& XMR_FS_FRA_ERR
)
2999 skge
->net_stats
.rx_frame_errors
++;
3000 if (status
& XMR_FS_FCS_ERR
)
3001 skge
->net_stats
.rx_crc_errors
++;
3003 if (status
& (GMR_FS_LONG_ERR
|GMR_FS_UN_SIZE
))
3004 skge
->net_stats
.rx_length_errors
++;
3005 if (status
& GMR_FS_FRAGMENT
)
3006 skge
->net_stats
.rx_frame_errors
++;
3007 if (status
& GMR_FS_CRC_ERR
)
3008 skge
->net_stats
.rx_crc_errors
++;
3012 skge_rx_reuse(e
, skge
->rx_buf_size
);
3016 /* Free all buffers in Tx ring which are no longer owned by device */
3017 static void skge_tx_done(struct net_device
*dev
)
3019 struct skge_port
*skge
= netdev_priv(dev
);
3020 struct skge_ring
*ring
= &skge
->tx_ring
;
3021 struct skge_element
*e
;
3023 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
3025 for (e
= ring
->to_clean
; e
!= ring
->to_use
; e
= e
->next
) {
3026 u32 control
= ((const struct skge_tx_desc
*) e
->desc
)->control
;
3028 if (control
& BMU_OWN
)
3031 skge_tx_free(skge
, e
, control
);
3033 skge
->tx_ring
.to_clean
= e
;
3035 /* Can run lockless until we need to synchronize to restart queue. */
3038 if (unlikely(netif_queue_stopped(dev
) &&
3039 skge_avail(&skge
->tx_ring
) > TX_LOW_WATER
)) {
3041 if (unlikely(netif_queue_stopped(dev
) &&
3042 skge_avail(&skge
->tx_ring
) > TX_LOW_WATER
)) {
3043 netif_wake_queue(dev
);
3046 netif_tx_unlock(dev
);
3050 static int skge_poll(struct napi_struct
*napi
, int to_do
)
3052 struct skge_port
*skge
= container_of(napi
, struct skge_port
, napi
);
3053 struct net_device
*dev
= skge
->netdev
;
3054 struct skge_hw
*hw
= skge
->hw
;
3055 struct skge_ring
*ring
= &skge
->rx_ring
;
3056 struct skge_element
*e
;
3061 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
3063 for (e
= ring
->to_clean
; prefetch(e
->next
), work_done
< to_do
; e
= e
->next
) {
3064 struct skge_rx_desc
*rd
= e
->desc
;
3065 struct sk_buff
*skb
;
3069 control
= rd
->control
;
3070 if (control
& BMU_OWN
)
3073 skb
= skge_rx_get(dev
, e
, control
, rd
->status
, rd
->csum2
);
3075 dev
->last_rx
= jiffies
;
3076 netif_receive_skb(skb
);
3083 /* restart receiver */
3085 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_START
);
3087 if (work_done
< to_do
) {
3088 spin_lock_irq(&hw
->hw_lock
);
3089 __netif_rx_complete(dev
, napi
);
3090 hw
->intr_mask
|= napimask
[skge
->port
];
3091 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3092 skge_read32(hw
, B0_IMSK
);
3093 spin_unlock_irq(&hw
->hw_lock
);
3099 /* Parity errors seem to happen when Genesis is connected to a switch
3100 * with no other ports present. Heartbeat error??
3102 static void skge_mac_parity(struct skge_hw
*hw
, int port
)
3104 struct net_device
*dev
= hw
->dev
[port
];
3107 struct skge_port
*skge
= netdev_priv(dev
);
3108 ++skge
->net_stats
.tx_heartbeat_errors
;
3111 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3112 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
3115 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3116 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
3117 (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)
3118 ? GMF_CLI_TX_FC
: GMF_CLI_TX_PE
);
3121 static void skge_mac_intr(struct skge_hw
*hw
, int port
)
3123 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3124 genesis_mac_intr(hw
, port
);
3126 yukon_mac_intr(hw
, port
);
3129 /* Handle device specific framing and timeout interrupts */
3130 static void skge_error_irq(struct skge_hw
*hw
)
3132 struct pci_dev
*pdev
= hw
->pdev
;
3133 u32 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
3135 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
3136 /* clear xmac errors */
3137 if (hwstatus
& (IS_NO_STAT_M1
|IS_NO_TIST_M1
))
3138 skge_write16(hw
, RX_MFF_CTRL1
, MFF_CLR_INSTAT
);
3139 if (hwstatus
& (IS_NO_STAT_M2
|IS_NO_TIST_M2
))
3140 skge_write16(hw
, RX_MFF_CTRL2
, MFF_CLR_INSTAT
);
3142 /* Timestamp (unused) overflow */
3143 if (hwstatus
& IS_IRQ_TIST_OV
)
3144 skge_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3147 if (hwstatus
& IS_RAM_RD_PAR
) {
3148 dev_err(&pdev
->dev
, "Ram read data parity error\n");
3149 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_RD_PERR
);
3152 if (hwstatus
& IS_RAM_WR_PAR
) {
3153 dev_err(&pdev
->dev
, "Ram write data parity error\n");
3154 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_WR_PERR
);
3157 if (hwstatus
& IS_M1_PAR_ERR
)
3158 skge_mac_parity(hw
, 0);
3160 if (hwstatus
& IS_M2_PAR_ERR
)
3161 skge_mac_parity(hw
, 1);
3163 if (hwstatus
& IS_R1_PAR_ERR
) {
3164 dev_err(&pdev
->dev
, "%s: receive queue parity error\n",
3166 skge_write32(hw
, B0_R1_CSR
, CSR_IRQ_CL_P
);
3169 if (hwstatus
& IS_R2_PAR_ERR
) {
3170 dev_err(&pdev
->dev
, "%s: receive queue parity error\n",
3172 skge_write32(hw
, B0_R2_CSR
, CSR_IRQ_CL_P
);
3175 if (hwstatus
& (IS_IRQ_MST_ERR
|IS_IRQ_STAT
)) {
3176 u16 pci_status
, pci_cmd
;
3178 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
3179 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
3181 dev_err(&pdev
->dev
, "PCI error cmd=%#x status=%#x\n",
3182 pci_cmd
, pci_status
);
3184 /* Write the error bits back to clear them. */
3185 pci_status
&= PCI_STATUS_ERROR_BITS
;
3186 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3187 pci_write_config_word(pdev
, PCI_COMMAND
,
3188 pci_cmd
| PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
);
3189 pci_write_config_word(pdev
, PCI_STATUS
, pci_status
);
3190 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3192 /* if error still set then just ignore it */
3193 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
3194 if (hwstatus
& IS_IRQ_STAT
) {
3195 dev_warn(&hw
->pdev
->dev
, "unable to clear error (so ignoring them)\n");
3196 hw
->intr_mask
&= ~IS_HW_ERR
;
3202 * Interrupt from PHY are handled in tasklet (softirq)
3203 * because accessing phy registers requires spin wait which might
3204 * cause excess interrupt latency.
3206 static void skge_extirq(unsigned long arg
)
3208 struct skge_hw
*hw
= (struct skge_hw
*) arg
;
3211 for (port
= 0; port
< hw
->ports
; port
++) {
3212 struct net_device
*dev
= hw
->dev
[port
];
3214 if (netif_running(dev
)) {
3215 struct skge_port
*skge
= netdev_priv(dev
);
3217 spin_lock(&hw
->phy_lock
);
3218 if (hw
->chip_id
!= CHIP_ID_GENESIS
)
3219 yukon_phy_intr(skge
);
3220 else if (hw
->phy_type
== SK_PHY_BCOM
)
3221 bcom_phy_intr(skge
);
3222 spin_unlock(&hw
->phy_lock
);
3226 spin_lock_irq(&hw
->hw_lock
);
3227 hw
->intr_mask
|= IS_EXT_REG
;
3228 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3229 skge_read32(hw
, B0_IMSK
);
3230 spin_unlock_irq(&hw
->hw_lock
);
3233 static irqreturn_t
skge_intr(int irq
, void *dev_id
)
3235 struct skge_hw
*hw
= dev_id
;
3239 spin_lock(&hw
->hw_lock
);
3240 /* Reading this register masks IRQ */
3241 status
= skge_read32(hw
, B0_SP_ISRC
);
3242 if (status
== 0 || status
== ~0)
3246 status
&= hw
->intr_mask
;
3247 if (status
& IS_EXT_REG
) {
3248 hw
->intr_mask
&= ~IS_EXT_REG
;
3249 tasklet_schedule(&hw
->phy_task
);
3252 if (status
& (IS_XA1_F
|IS_R1_F
)) {
3253 struct skge_port
*skge
= netdev_priv(hw
->dev
[0]);
3254 hw
->intr_mask
&= ~(IS_XA1_F
|IS_R1_F
);
3255 netif_rx_schedule(hw
->dev
[0], &skge
->napi
);
3258 if (status
& IS_PA_TO_TX1
)
3259 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX1
);
3261 if (status
& IS_PA_TO_RX1
) {
3262 struct skge_port
*skge
= netdev_priv(hw
->dev
[0]);
3264 ++skge
->net_stats
.rx_over_errors
;
3265 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX1
);
3269 if (status
& IS_MAC1
)
3270 skge_mac_intr(hw
, 0);
3273 struct skge_port
*skge
= netdev_priv(hw
->dev
[1]);
3275 if (status
& (IS_XA2_F
|IS_R2_F
)) {
3276 hw
->intr_mask
&= ~(IS_XA2_F
|IS_R2_F
);
3277 netif_rx_schedule(hw
->dev
[1], &skge
->napi
);
3280 if (status
& IS_PA_TO_RX2
) {
3281 ++skge
->net_stats
.rx_over_errors
;
3282 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX2
);
3285 if (status
& IS_PA_TO_TX2
)
3286 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX2
);
3288 if (status
& IS_MAC2
)
3289 skge_mac_intr(hw
, 1);
3292 if (status
& IS_HW_ERR
)
3295 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3296 skge_read32(hw
, B0_IMSK
);
3298 spin_unlock(&hw
->hw_lock
);
3300 return IRQ_RETVAL(handled
);
3303 #ifdef CONFIG_NET_POLL_CONTROLLER
3304 static void skge_netpoll(struct net_device
*dev
)
3306 struct skge_port
*skge
= netdev_priv(dev
);
3308 disable_irq(dev
->irq
);
3309 skge_intr(dev
->irq
, skge
->hw
);
3310 enable_irq(dev
->irq
);
3314 static int skge_set_mac_address(struct net_device
*dev
, void *p
)
3316 struct skge_port
*skge
= netdev_priv(dev
);
3317 struct skge_hw
*hw
= skge
->hw
;
3318 unsigned port
= skge
->port
;
3319 const struct sockaddr
*addr
= p
;
3322 if (!is_valid_ether_addr(addr
->sa_data
))
3323 return -EADDRNOTAVAIL
;
3325 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3327 if (!netif_running(dev
)) {
3328 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3329 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3332 spin_lock_bh(&hw
->phy_lock
);
3333 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
3334 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
& ~GM_GPCR_RX_ENA
);
3336 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3337 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3339 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3340 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
3342 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3343 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3346 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
3347 spin_unlock_bh(&hw
->phy_lock
);
3353 static const struct {
3357 { CHIP_ID_GENESIS
, "Genesis" },
3358 { CHIP_ID_YUKON
, "Yukon" },
3359 { CHIP_ID_YUKON_LITE
, "Yukon-Lite"},
3360 { CHIP_ID_YUKON_LP
, "Yukon-LP"},
3363 static const char *skge_board_name(const struct skge_hw
*hw
)
3366 static char buf
[16];
3368 for (i
= 0; i
< ARRAY_SIZE(skge_chips
); i
++)
3369 if (skge_chips
[i
].id
== hw
->chip_id
)
3370 return skge_chips
[i
].name
;
3372 snprintf(buf
, sizeof buf
, "chipid 0x%x", hw
->chip_id
);
3378 * Setup the board data structure, but don't bring up
3381 static int skge_reset(struct skge_hw
*hw
)
3384 u16 ctst
, pci_status
;
3385 u8 t8
, mac_cfg
, pmd_type
;
3388 ctst
= skge_read16(hw
, B0_CTST
);
3391 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3392 skge_write8(hw
, B0_CTST
, CS_RST_CLR
);
3394 /* clear PCI errors, if any */
3395 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3396 skge_write8(hw
, B2_TST_CTRL2
, 0);
3398 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &pci_status
);
3399 pci_write_config_word(hw
->pdev
, PCI_STATUS
,
3400 pci_status
| PCI_STATUS_ERROR_BITS
);
3401 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3402 skge_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3404 /* restore CLK_RUN bits (for Yukon-Lite) */
3405 skge_write16(hw
, B0_CTST
,
3406 ctst
& (CS_CLK_RUN_HOT
|CS_CLK_RUN_RST
|CS_CLK_RUN_ENA
));
3408 hw
->chip_id
= skge_read8(hw
, B2_CHIP_ID
);
3409 hw
->phy_type
= skge_read8(hw
, B2_E_1
) & 0xf;
3410 pmd_type
= skge_read8(hw
, B2_PMD_TYP
);
3411 hw
->copper
= (pmd_type
== 'T' || pmd_type
== '1');
3413 switch (hw
->chip_id
) {
3414 case CHIP_ID_GENESIS
:
3415 switch (hw
->phy_type
) {
3417 hw
->phy_addr
= PHY_ADDR_XMAC
;
3420 hw
->phy_addr
= PHY_ADDR_BCOM
;
3423 dev_err(&hw
->pdev
->dev
, "unsupported phy type 0x%x\n",
3430 case CHIP_ID_YUKON_LITE
:
3431 case CHIP_ID_YUKON_LP
:
3432 if (hw
->phy_type
< SK_PHY_MARV_COPPER
&& pmd_type
!= 'S')
3435 hw
->phy_addr
= PHY_ADDR_MARV
;
3439 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
3444 mac_cfg
= skge_read8(hw
, B2_MAC_CFG
);
3445 hw
->ports
= (mac_cfg
& CFG_SNG_MAC
) ? 1 : 2;
3446 hw
->chip_rev
= (mac_cfg
& CFG_CHIP_R_MSK
) >> 4;
3448 /* read the adapters RAM size */
3449 t8
= skge_read8(hw
, B2_E_0
);
3450 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
3452 /* special case: 4 x 64k x 36, offset = 0x80000 */
3453 hw
->ram_size
= 0x100000;
3454 hw
->ram_offset
= 0x80000;
3456 hw
->ram_size
= t8
* 512;
3459 hw
->ram_size
= 0x20000;
3461 hw
->ram_size
= t8
* 4096;
3463 hw
->intr_mask
= IS_HW_ERR
;
3465 /* Use PHY IRQ for all but fiber based Genesis board */
3466 if (!(hw
->chip_id
== CHIP_ID_GENESIS
&& hw
->phy_type
== SK_PHY_XMAC
))
3467 hw
->intr_mask
|= IS_EXT_REG
;
3469 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3472 /* switch power to VCC (WA for VAUX problem) */
3473 skge_write8(hw
, B0_POWER_CTRL
,
3474 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
3476 /* avoid boards with stuck Hardware error bits */
3477 if ((skge_read32(hw
, B0_ISRC
) & IS_HW_ERR
) &&
3478 (skge_read32(hw
, B0_HWE_ISRC
) & IS_IRQ_SENSOR
)) {
3479 dev_warn(&hw
->pdev
->dev
, "stuck hardware sensor bit\n");
3480 hw
->intr_mask
&= ~IS_HW_ERR
;
3483 /* Clear PHY COMA */
3484 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3485 pci_read_config_dword(hw
->pdev
, PCI_DEV_REG1
, ®
);
3486 reg
&= ~PCI_PHY_COMA
;
3487 pci_write_config_dword(hw
->pdev
, PCI_DEV_REG1
, reg
);
3488 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3491 for (i
= 0; i
< hw
->ports
; i
++) {
3492 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3493 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3497 /* turn off hardware timer (unused) */
3498 skge_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3499 skge_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3500 skge_write8(hw
, B0_LED
, LED_STAT_ON
);
3502 /* enable the Tx Arbiters */
3503 for (i
= 0; i
< hw
->ports
; i
++)
3504 skge_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3506 /* Initialize ram interface */
3507 skge_write16(hw
, B3_RI_CTRL
, RI_RST_CLR
);
3509 skge_write8(hw
, B3_RI_WTO_R1
, SK_RI_TO_53
);
3510 skge_write8(hw
, B3_RI_WTO_XA1
, SK_RI_TO_53
);
3511 skge_write8(hw
, B3_RI_WTO_XS1
, SK_RI_TO_53
);
3512 skge_write8(hw
, B3_RI_RTO_R1
, SK_RI_TO_53
);
3513 skge_write8(hw
, B3_RI_RTO_XA1
, SK_RI_TO_53
);
3514 skge_write8(hw
, B3_RI_RTO_XS1
, SK_RI_TO_53
);
3515 skge_write8(hw
, B3_RI_WTO_R2
, SK_RI_TO_53
);
3516 skge_write8(hw
, B3_RI_WTO_XA2
, SK_RI_TO_53
);
3517 skge_write8(hw
, B3_RI_WTO_XS2
, SK_RI_TO_53
);
3518 skge_write8(hw
, B3_RI_RTO_R2
, SK_RI_TO_53
);
3519 skge_write8(hw
, B3_RI_RTO_XA2
, SK_RI_TO_53
);
3520 skge_write8(hw
, B3_RI_RTO_XS2
, SK_RI_TO_53
);
3522 skge_write32(hw
, B0_HWE_IMSK
, IS_ERR_MSK
);
3524 /* Set interrupt moderation for Transmit only
3525 * Receive interrupts avoided by NAPI
3527 skge_write32(hw
, B2_IRQM_MSK
, IS_XA1_F
|IS_XA2_F
);
3528 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, 100));
3529 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
3531 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3533 for (i
= 0; i
< hw
->ports
; i
++) {
3534 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3535 genesis_reset(hw
, i
);
3543 /* Initialize network device */
3544 static struct net_device
*skge_devinit(struct skge_hw
*hw
, int port
,
3547 struct skge_port
*skge
;
3548 struct net_device
*dev
= alloc_etherdev(sizeof(*skge
));
3551 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
3555 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3556 dev
->open
= skge_up
;
3557 dev
->stop
= skge_down
;
3558 dev
->do_ioctl
= skge_ioctl
;
3559 dev
->hard_start_xmit
= skge_xmit_frame
;
3560 dev
->get_stats
= skge_get_stats
;
3561 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3562 dev
->set_multicast_list
= genesis_set_multicast
;
3564 dev
->set_multicast_list
= yukon_set_multicast
;
3566 dev
->set_mac_address
= skge_set_mac_address
;
3567 dev
->change_mtu
= skge_change_mtu
;
3568 SET_ETHTOOL_OPS(dev
, &skge_ethtool_ops
);
3569 dev
->tx_timeout
= skge_tx_timeout
;
3570 dev
->watchdog_timeo
= TX_WATCHDOG
;
3571 #ifdef CONFIG_NET_POLL_CONTROLLER
3572 dev
->poll_controller
= skge_netpoll
;
3574 dev
->irq
= hw
->pdev
->irq
;
3577 dev
->features
|= NETIF_F_HIGHDMA
;
3579 skge
= netdev_priv(dev
);
3580 netif_napi_add(dev
, &skge
->napi
, skge_poll
, NAPI_WEIGHT
);
3583 skge
->msg_enable
= netif_msg_init(debug
, default_msg
);
3585 skge
->tx_ring
.count
= DEFAULT_TX_RING_SIZE
;
3586 skge
->rx_ring
.count
= DEFAULT_RX_RING_SIZE
;
3588 /* Auto speed and flow control */
3589 skge
->autoneg
= AUTONEG_ENABLE
;
3590 skge
->flow_control
= FLOW_MODE_SYM_OR_REM
;
3593 skge
->advertising
= skge_supported_modes(hw
);
3595 if (pci_wake_enabled(hw
->pdev
))
3596 skge
->wol
= wol_supported(hw
) & WAKE_MAGIC
;
3598 hw
->dev
[port
] = dev
;
3602 /* Only used for Genesis XMAC */
3603 setup_timer(&skge
->link_timer
, xm_link_timer
, (unsigned long) skge
);
3605 if (hw
->chip_id
!= CHIP_ID_GENESIS
) {
3606 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3610 /* read the mac address */
3611 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
*8, ETH_ALEN
);
3612 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3614 /* device is off until link detection */
3615 netif_carrier_off(dev
);
3616 netif_stop_queue(dev
);
3621 static void __devinit
skge_show_addr(struct net_device
*dev
)
3623 const struct skge_port
*skge
= netdev_priv(dev
);
3624 DECLARE_MAC_BUF(mac
);
3626 if (netif_msg_probe(skge
))
3627 printk(KERN_INFO PFX
"%s: addr %s\n",
3628 dev
->name
, print_mac(mac
, dev
->dev_addr
));
3631 static int __devinit
skge_probe(struct pci_dev
*pdev
,
3632 const struct pci_device_id
*ent
)
3634 struct net_device
*dev
, *dev1
;
3636 int err
, using_dac
= 0;
3638 err
= pci_enable_device(pdev
);
3640 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3644 err
= pci_request_regions(pdev
, DRV_NAME
);
3646 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3647 goto err_out_disable_pdev
;
3650 pci_set_master(pdev
);
3652 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3654 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3655 } else if (!(err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
))) {
3657 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3661 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3662 goto err_out_free_regions
;
3666 /* byte swap descriptors in hardware */
3670 pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
3671 reg
|= PCI_REV_DESC
;
3672 pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
3677 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3679 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3680 goto err_out_free_regions
;
3684 spin_lock_init(&hw
->hw_lock
);
3685 spin_lock_init(&hw
->phy_lock
);
3686 tasklet_init(&hw
->phy_task
, &skge_extirq
, (unsigned long) hw
);
3688 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3690 dev_err(&pdev
->dev
, "cannot map device registers\n");
3691 goto err_out_free_hw
;
3694 err
= skge_reset(hw
);
3696 goto err_out_iounmap
;
3698 printk(KERN_INFO PFX DRV_VERSION
" addr 0x%llx irq %d chip %s rev %d\n",
3699 (unsigned long long)pci_resource_start(pdev
, 0), pdev
->irq
,
3700 skge_board_name(hw
), hw
->chip_rev
);
3702 dev
= skge_devinit(hw
, 0, using_dac
);
3704 goto err_out_led_off
;
3706 /* Some motherboards are broken and has zero in ROM. */
3707 if (!is_valid_ether_addr(dev
->dev_addr
))
3708 dev_warn(&pdev
->dev
, "bad (zero?) ethernet address in rom\n");
3710 err
= register_netdev(dev
);
3712 dev_err(&pdev
->dev
, "cannot register net device\n");
3713 goto err_out_free_netdev
;
3716 err
= request_irq(pdev
->irq
, skge_intr
, IRQF_SHARED
, dev
->name
, hw
);
3718 dev_err(&pdev
->dev
, "%s: cannot assign irq %d\n",
3719 dev
->name
, pdev
->irq
);
3720 goto err_out_unregister
;
3722 skge_show_addr(dev
);
3724 if (hw
->ports
> 1 && (dev1
= skge_devinit(hw
, 1, using_dac
))) {
3725 if (register_netdev(dev1
) == 0)
3726 skge_show_addr(dev1
);
3728 /* Failure to register second port need not be fatal */
3729 dev_warn(&pdev
->dev
, "register of second port failed\n");
3734 pci_set_drvdata(pdev
, hw
);
3739 unregister_netdev(dev
);
3740 err_out_free_netdev
:
3743 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3748 err_out_free_regions
:
3749 pci_release_regions(pdev
);
3750 err_out_disable_pdev
:
3751 pci_disable_device(pdev
);
3752 pci_set_drvdata(pdev
, NULL
);
3757 static void __devexit
skge_remove(struct pci_dev
*pdev
)
3759 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3760 struct net_device
*dev0
, *dev1
;
3765 flush_scheduled_work();
3767 if ((dev1
= hw
->dev
[1]))
3768 unregister_netdev(dev1
);
3770 unregister_netdev(dev0
);
3772 tasklet_disable(&hw
->phy_task
);
3774 spin_lock_irq(&hw
->hw_lock
);
3776 skge_write32(hw
, B0_IMSK
, 0);
3777 skge_read32(hw
, B0_IMSK
);
3778 spin_unlock_irq(&hw
->hw_lock
);
3780 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3781 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3783 free_irq(pdev
->irq
, hw
);
3784 pci_release_regions(pdev
);
3785 pci_disable_device(pdev
);
3792 pci_set_drvdata(pdev
, NULL
);
3796 static int skge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3798 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3799 int i
, err
, wol
= 0;
3804 err
= pci_save_state(pdev
);
3808 for (i
= 0; i
< hw
->ports
; i
++) {
3809 struct net_device
*dev
= hw
->dev
[i
];
3810 struct skge_port
*skge
= netdev_priv(dev
);
3812 if (netif_running(dev
))
3815 skge_wol_init(skge
);
3820 skge_write32(hw
, B0_IMSK
, 0);
3821 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3822 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3827 static int skge_resume(struct pci_dev
*pdev
)
3829 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3835 err
= pci_set_power_state(pdev
, PCI_D0
);
3839 err
= pci_restore_state(pdev
);
3843 pci_enable_wake(pdev
, PCI_D0
, 0);
3845 err
= skge_reset(hw
);
3849 for (i
= 0; i
< hw
->ports
; i
++) {
3850 struct net_device
*dev
= hw
->dev
[i
];
3852 if (netif_running(dev
)) {
3856 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3868 static void skge_shutdown(struct pci_dev
*pdev
)
3870 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3876 for (i
= 0; i
< hw
->ports
; i
++) {
3877 struct net_device
*dev
= hw
->dev
[i
];
3878 struct skge_port
*skge
= netdev_priv(dev
);
3881 skge_wol_init(skge
);
3885 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
3886 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
3888 pci_disable_device(pdev
);
3889 pci_set_power_state(pdev
, PCI_D3hot
);
3893 static struct pci_driver skge_driver
= {
3895 .id_table
= skge_id_table
,
3896 .probe
= skge_probe
,
3897 .remove
= __devexit_p(skge_remove
),
3899 .suspend
= skge_suspend
,
3900 .resume
= skge_resume
,
3902 .shutdown
= skge_shutdown
,
3905 static int __init
skge_init_module(void)
3907 return pci_register_driver(&skge_driver
);
3910 static void __exit
skge_cleanup_module(void)
3912 pci_unregister_driver(&skge_driver
);
3915 module_init(skge_init_module
);
3916 module_exit(skge_cleanup_module
);