2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/mii.h>
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.11"
46 #define PFX DRV_NAME " "
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION
);
67 static const u32 default_msg
68 = NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
71 static int debug
= -1; /* defaults above */
72 module_param(debug
, int, 0);
73 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
75 static const struct pci_device_id skge_id_table
[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940
) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940B
) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_GE
) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_YU
) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, PCI_DEVICE_ID_DLINK_DGE510T
) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET
, PCI_DEVICE_ID_CNET_GIGACARD
) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS
, PCI_DEVICE_ID_LINKSYS_EG1064
) },
86 { PCI_VENDOR_ID_LINKSYS
, 0x1032, PCI_ANY_ID
, 0x0015 },
89 MODULE_DEVICE_TABLE(pci
, skge_id_table
);
91 static int skge_up(struct net_device
*dev
);
92 static int skge_down(struct net_device
*dev
);
93 static void skge_phy_reset(struct skge_port
*skge
);
94 static void skge_tx_clean(struct net_device
*dev
);
95 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
96 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
97 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
);
98 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
);
99 static void yukon_init(struct skge_hw
*hw
, int port
);
100 static void genesis_mac_init(struct skge_hw
*hw
, int port
);
101 static void genesis_link_up(struct skge_port
*skge
);
103 /* Avoid conditionals by using array */
104 static const int txqaddr
[] = { Q_XA1
, Q_XA2
};
105 static const int rxqaddr
[] = { Q_R1
, Q_R2
};
106 static const u32 rxirqmask
[] = { IS_R1_F
, IS_R2_F
};
107 static const u32 txirqmask
[] = { IS_XA1_F
, IS_XA2_F
};
108 static const u32 napimask
[] = { IS_R1_F
|IS_XA1_F
, IS_R2_F
|IS_XA2_F
};
109 static const u32 portmask
[] = { IS_PORT_1
, IS_PORT_2
};
111 static int skge_get_regs_len(struct net_device
*dev
)
117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
121 static void skge_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
124 const struct skge_port
*skge
= netdev_priv(dev
);
125 const void __iomem
*io
= skge
->hw
->regs
;
128 memset(p
, 0, regs
->len
);
129 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
131 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
,
132 regs
->len
- B3_RI_WTO_R1
);
135 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
136 static u32
wol_supported(const struct skge_hw
*hw
)
138 if (hw
->chip_id
== CHIP_ID_GENESIS
)
141 if (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)
144 return WAKE_MAGIC
| WAKE_PHY
;
147 static u32
pci_wake_enabled(struct pci_dev
*dev
)
149 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
152 /* If device doesn't support PM Capabilities, but request is to disable
153 * wake events, it's a nop; otherwise fail */
157 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &value
);
159 value
&= PCI_PM_CAP_PME_MASK
;
160 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
165 static void skge_wol_init(struct skge_port
*skge
)
167 struct skge_hw
*hw
= skge
->hw
;
168 int port
= skge
->port
;
171 skge_write16(hw
, B0_CTST
, CS_RST_CLR
);
172 skge_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
175 skge_write8(hw
, B0_POWER_CTRL
,
176 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_ON
| PC_VCC_OFF
);
178 /* WA code for COMA mode -- clear PHY reset */
179 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
180 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
181 u32 reg
= skge_read32(hw
, B2_GP_IO
);
184 skge_write32(hw
, B2_GP_IO
, reg
);
187 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
),
189 GPC_HWCFG_M_3
| GPC_HWCFG_M_2
| GPC_HWCFG_M_1
| GPC_HWCFG_M_0
|
190 GPC_ANEG_1
| GPC_RST_SET
);
192 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
),
194 GPC_HWCFG_M_3
| GPC_HWCFG_M_2
| GPC_HWCFG_M_1
| GPC_HWCFG_M_0
|
195 GPC_ANEG_1
| GPC_RST_CLR
);
197 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
199 /* Force to 10/100 skge_reset will re-enable on resume */
200 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
201 PHY_AN_100FULL
| PHY_AN_100HALF
|
202 PHY_AN_10FULL
| PHY_AN_10HALF
| PHY_AN_CSMA
);
204 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, 0);
205 gm_phy_write(hw
, port
, PHY_MARV_CTRL
,
206 PHY_CT_RESET
| PHY_CT_SPS_LSB
| PHY_CT_ANE
|
207 PHY_CT_RE_CFG
| PHY_CT_DUP_MD
);
210 /* Set GMAC to no flow control and auto update for speed/duplex */
211 gma_write16(hw
, port
, GM_GP_CTRL
,
212 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
213 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
215 /* Set WOL address */
216 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
217 skge
->netdev
->dev_addr
, ETH_ALEN
);
219 /* Turn on appropriate WOL control bits */
220 skge_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
222 if (skge
->wol
& WAKE_PHY
)
223 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
225 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
227 if (skge
->wol
& WAKE_MAGIC
)
228 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
230 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
232 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
233 skge_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
236 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
239 static void skge_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
241 struct skge_port
*skge
= netdev_priv(dev
);
243 wol
->supported
= wol_supported(skge
->hw
);
244 wol
->wolopts
= skge
->wol
;
247 static int skge_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
249 struct skge_port
*skge
= netdev_priv(dev
);
250 struct skge_hw
*hw
= skge
->hw
;
252 if (wol
->wolopts
& ~wol_supported(hw
))
255 skge
->wol
= wol
->wolopts
;
259 /* Determine supported/advertised modes based on hardware.
260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
262 static u32
skge_supported_modes(const struct skge_hw
*hw
)
267 supported
= SUPPORTED_10baseT_Half
268 | SUPPORTED_10baseT_Full
269 | SUPPORTED_100baseT_Half
270 | SUPPORTED_100baseT_Full
271 | SUPPORTED_1000baseT_Half
272 | SUPPORTED_1000baseT_Full
273 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
275 if (hw
->chip_id
== CHIP_ID_GENESIS
)
276 supported
&= ~(SUPPORTED_10baseT_Half
277 | SUPPORTED_10baseT_Full
278 | SUPPORTED_100baseT_Half
279 | SUPPORTED_100baseT_Full
);
281 else if (hw
->chip_id
== CHIP_ID_YUKON
)
282 supported
&= ~SUPPORTED_1000baseT_Half
;
284 supported
= SUPPORTED_1000baseT_Full
| SUPPORTED_1000baseT_Half
285 | SUPPORTED_FIBRE
| SUPPORTED_Autoneg
;
290 static int skge_get_settings(struct net_device
*dev
,
291 struct ethtool_cmd
*ecmd
)
293 struct skge_port
*skge
= netdev_priv(dev
);
294 struct skge_hw
*hw
= skge
->hw
;
296 ecmd
->transceiver
= XCVR_INTERNAL
;
297 ecmd
->supported
= skge_supported_modes(hw
);
300 ecmd
->port
= PORT_TP
;
301 ecmd
->phy_address
= hw
->phy_addr
;
303 ecmd
->port
= PORT_FIBRE
;
305 ecmd
->advertising
= skge
->advertising
;
306 ecmd
->autoneg
= skge
->autoneg
;
307 ecmd
->speed
= skge
->speed
;
308 ecmd
->duplex
= skge
->duplex
;
312 static int skge_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
314 struct skge_port
*skge
= netdev_priv(dev
);
315 const struct skge_hw
*hw
= skge
->hw
;
316 u32 supported
= skge_supported_modes(hw
);
318 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
319 ecmd
->advertising
= supported
;
325 switch (ecmd
->speed
) {
327 if (ecmd
->duplex
== DUPLEX_FULL
)
328 setting
= SUPPORTED_1000baseT_Full
;
329 else if (ecmd
->duplex
== DUPLEX_HALF
)
330 setting
= SUPPORTED_1000baseT_Half
;
335 if (ecmd
->duplex
== DUPLEX_FULL
)
336 setting
= SUPPORTED_100baseT_Full
;
337 else if (ecmd
->duplex
== DUPLEX_HALF
)
338 setting
= SUPPORTED_100baseT_Half
;
344 if (ecmd
->duplex
== DUPLEX_FULL
)
345 setting
= SUPPORTED_10baseT_Full
;
346 else if (ecmd
->duplex
== DUPLEX_HALF
)
347 setting
= SUPPORTED_10baseT_Half
;
355 if ((setting
& supported
) == 0)
358 skge
->speed
= ecmd
->speed
;
359 skge
->duplex
= ecmd
->duplex
;
362 skge
->autoneg
= ecmd
->autoneg
;
363 skge
->advertising
= ecmd
->advertising
;
365 if (netif_running(dev
))
366 skge_phy_reset(skge
);
371 static void skge_get_drvinfo(struct net_device
*dev
,
372 struct ethtool_drvinfo
*info
)
374 struct skge_port
*skge
= netdev_priv(dev
);
376 strcpy(info
->driver
, DRV_NAME
);
377 strcpy(info
->version
, DRV_VERSION
);
378 strcpy(info
->fw_version
, "N/A");
379 strcpy(info
->bus_info
, pci_name(skge
->hw
->pdev
));
382 static const struct skge_stat
{
383 char name
[ETH_GSTRING_LEN
];
387 { "tx_bytes", XM_TXO_OK_HI
, GM_TXO_OK_HI
},
388 { "rx_bytes", XM_RXO_OK_HI
, GM_RXO_OK_HI
},
390 { "tx_broadcast", XM_TXF_BC_OK
, GM_TXF_BC_OK
},
391 { "rx_broadcast", XM_RXF_BC_OK
, GM_RXF_BC_OK
},
392 { "tx_multicast", XM_TXF_MC_OK
, GM_TXF_MC_OK
},
393 { "rx_multicast", XM_RXF_MC_OK
, GM_RXF_MC_OK
},
394 { "tx_unicast", XM_TXF_UC_OK
, GM_TXF_UC_OK
},
395 { "rx_unicast", XM_RXF_UC_OK
, GM_RXF_UC_OK
},
396 { "tx_mac_pause", XM_TXF_MPAUSE
, GM_TXF_MPAUSE
},
397 { "rx_mac_pause", XM_RXF_MPAUSE
, GM_RXF_MPAUSE
},
399 { "collisions", XM_TXF_SNG_COL
, GM_TXF_SNG_COL
},
400 { "multi_collisions", XM_TXF_MUL_COL
, GM_TXF_MUL_COL
},
401 { "aborted", XM_TXF_ABO_COL
, GM_TXF_ABO_COL
},
402 { "late_collision", XM_TXF_LAT_COL
, GM_TXF_LAT_COL
},
403 { "fifo_underrun", XM_TXE_FIFO_UR
, GM_TXE_FIFO_UR
},
404 { "fifo_overflow", XM_RXE_FIFO_OV
, GM_RXE_FIFO_OV
},
406 { "rx_toolong", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
407 { "rx_jabber", XM_RXF_JAB_PKT
, GM_RXF_JAB_PKT
},
408 { "rx_runt", XM_RXE_RUNT
, GM_RXE_FRAG
},
409 { "rx_too_long", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
410 { "rx_fcs_error", XM_RXF_FCS_ERR
, GM_RXF_FCS_ERR
},
413 static int skge_get_sset_count(struct net_device
*dev
, int sset
)
417 return ARRAY_SIZE(skge_stats
);
423 static void skge_get_ethtool_stats(struct net_device
*dev
,
424 struct ethtool_stats
*stats
, u64
*data
)
426 struct skge_port
*skge
= netdev_priv(dev
);
428 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
429 genesis_get_stats(skge
, data
);
431 yukon_get_stats(skge
, data
);
434 /* Use hardware MIB variables for critical path statistics and
435 * transmit feedback not reported at interrupt.
436 * Other errors are accounted for in interrupt handler.
438 static struct net_device_stats
*skge_get_stats(struct net_device
*dev
)
440 struct skge_port
*skge
= netdev_priv(dev
);
441 u64 data
[ARRAY_SIZE(skge_stats
)];
443 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
444 genesis_get_stats(skge
, data
);
446 yukon_get_stats(skge
, data
);
448 skge
->net_stats
.tx_bytes
= data
[0];
449 skge
->net_stats
.rx_bytes
= data
[1];
450 skge
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
451 skge
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
452 skge
->net_stats
.multicast
= data
[3] + data
[5];
453 skge
->net_stats
.collisions
= data
[10];
454 skge
->net_stats
.tx_aborted_errors
= data
[12];
456 return &skge
->net_stats
;
459 static void skge_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
465 for (i
= 0; i
< ARRAY_SIZE(skge_stats
); i
++)
466 memcpy(data
+ i
* ETH_GSTRING_LEN
,
467 skge_stats
[i
].name
, ETH_GSTRING_LEN
);
472 static void skge_get_ring_param(struct net_device
*dev
,
473 struct ethtool_ringparam
*p
)
475 struct skge_port
*skge
= netdev_priv(dev
);
477 p
->rx_max_pending
= MAX_RX_RING_SIZE
;
478 p
->tx_max_pending
= MAX_TX_RING_SIZE
;
479 p
->rx_mini_max_pending
= 0;
480 p
->rx_jumbo_max_pending
= 0;
482 p
->rx_pending
= skge
->rx_ring
.count
;
483 p
->tx_pending
= skge
->tx_ring
.count
;
484 p
->rx_mini_pending
= 0;
485 p
->rx_jumbo_pending
= 0;
488 static int skge_set_ring_param(struct net_device
*dev
,
489 struct ethtool_ringparam
*p
)
491 struct skge_port
*skge
= netdev_priv(dev
);
494 if (p
->rx_pending
== 0 || p
->rx_pending
> MAX_RX_RING_SIZE
||
495 p
->tx_pending
< TX_LOW_WATER
|| p
->tx_pending
> MAX_TX_RING_SIZE
)
498 skge
->rx_ring
.count
= p
->rx_pending
;
499 skge
->tx_ring
.count
= p
->tx_pending
;
501 if (netif_running(dev
)) {
511 static u32
skge_get_msglevel(struct net_device
*netdev
)
513 struct skge_port
*skge
= netdev_priv(netdev
);
514 return skge
->msg_enable
;
517 static void skge_set_msglevel(struct net_device
*netdev
, u32 value
)
519 struct skge_port
*skge
= netdev_priv(netdev
);
520 skge
->msg_enable
= value
;
523 static int skge_nway_reset(struct net_device
*dev
)
525 struct skge_port
*skge
= netdev_priv(dev
);
527 if (skge
->autoneg
!= AUTONEG_ENABLE
|| !netif_running(dev
))
530 skge_phy_reset(skge
);
534 static int skge_set_sg(struct net_device
*dev
, u32 data
)
536 struct skge_port
*skge
= netdev_priv(dev
);
537 struct skge_hw
*hw
= skge
->hw
;
539 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
541 return ethtool_op_set_sg(dev
, data
);
544 static int skge_set_tx_csum(struct net_device
*dev
, u32 data
)
546 struct skge_port
*skge
= netdev_priv(dev
);
547 struct skge_hw
*hw
= skge
->hw
;
549 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
552 return ethtool_op_set_tx_csum(dev
, data
);
555 static u32
skge_get_rx_csum(struct net_device
*dev
)
557 struct skge_port
*skge
= netdev_priv(dev
);
559 return skge
->rx_csum
;
562 /* Only Yukon supports checksum offload. */
563 static int skge_set_rx_csum(struct net_device
*dev
, u32 data
)
565 struct skge_port
*skge
= netdev_priv(dev
);
567 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
570 skge
->rx_csum
= data
;
574 static void skge_get_pauseparam(struct net_device
*dev
,
575 struct ethtool_pauseparam
*ecmd
)
577 struct skge_port
*skge
= netdev_priv(dev
);
579 ecmd
->rx_pause
= (skge
->flow_control
== FLOW_MODE_SYMMETRIC
)
580 || (skge
->flow_control
== FLOW_MODE_SYM_OR_REM
);
581 ecmd
->tx_pause
= ecmd
->rx_pause
|| (skge
->flow_control
== FLOW_MODE_LOC_SEND
);
583 ecmd
->autoneg
= ecmd
->rx_pause
|| ecmd
->tx_pause
;
586 static int skge_set_pauseparam(struct net_device
*dev
,
587 struct ethtool_pauseparam
*ecmd
)
589 struct skge_port
*skge
= netdev_priv(dev
);
590 struct ethtool_pauseparam old
;
592 skge_get_pauseparam(dev
, &old
);
594 if (ecmd
->autoneg
!= old
.autoneg
)
595 skge
->flow_control
= ecmd
->autoneg
? FLOW_MODE_NONE
: FLOW_MODE_SYMMETRIC
;
597 if (ecmd
->rx_pause
&& ecmd
->tx_pause
)
598 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
599 else if (ecmd
->rx_pause
&& !ecmd
->tx_pause
)
600 skge
->flow_control
= FLOW_MODE_SYM_OR_REM
;
601 else if (!ecmd
->rx_pause
&& ecmd
->tx_pause
)
602 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
604 skge
->flow_control
= FLOW_MODE_NONE
;
607 if (netif_running(dev
))
608 skge_phy_reset(skge
);
613 /* Chip internal frequency for clock calculations */
614 static inline u32
hwkhz(const struct skge_hw
*hw
)
616 return (hw
->chip_id
== CHIP_ID_GENESIS
) ? 53125 : 78125;
619 /* Chip HZ to microseconds */
620 static inline u32
skge_clk2usec(const struct skge_hw
*hw
, u32 ticks
)
622 return (ticks
* 1000) / hwkhz(hw
);
625 /* Microseconds to chip HZ */
626 static inline u32
skge_usecs2clk(const struct skge_hw
*hw
, u32 usec
)
628 return hwkhz(hw
) * usec
/ 1000;
631 static int skge_get_coalesce(struct net_device
*dev
,
632 struct ethtool_coalesce
*ecmd
)
634 struct skge_port
*skge
= netdev_priv(dev
);
635 struct skge_hw
*hw
= skge
->hw
;
636 int port
= skge
->port
;
638 ecmd
->rx_coalesce_usecs
= 0;
639 ecmd
->tx_coalesce_usecs
= 0;
641 if (skge_read32(hw
, B2_IRQM_CTRL
) & TIM_START
) {
642 u32 delay
= skge_clk2usec(hw
, skge_read32(hw
, B2_IRQM_INI
));
643 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
645 if (msk
& rxirqmask
[port
])
646 ecmd
->rx_coalesce_usecs
= delay
;
647 if (msk
& txirqmask
[port
])
648 ecmd
->tx_coalesce_usecs
= delay
;
654 /* Note: interrupt timer is per board, but can turn on/off per port */
655 static int skge_set_coalesce(struct net_device
*dev
,
656 struct ethtool_coalesce
*ecmd
)
658 struct skge_port
*skge
= netdev_priv(dev
);
659 struct skge_hw
*hw
= skge
->hw
;
660 int port
= skge
->port
;
661 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
664 if (ecmd
->rx_coalesce_usecs
== 0)
665 msk
&= ~rxirqmask
[port
];
666 else if (ecmd
->rx_coalesce_usecs
< 25 ||
667 ecmd
->rx_coalesce_usecs
> 33333)
670 msk
|= rxirqmask
[port
];
671 delay
= ecmd
->rx_coalesce_usecs
;
674 if (ecmd
->tx_coalesce_usecs
== 0)
675 msk
&= ~txirqmask
[port
];
676 else if (ecmd
->tx_coalesce_usecs
< 25 ||
677 ecmd
->tx_coalesce_usecs
> 33333)
680 msk
|= txirqmask
[port
];
681 delay
= min(delay
, ecmd
->rx_coalesce_usecs
);
684 skge_write32(hw
, B2_IRQM_MSK
, msk
);
686 skge_write32(hw
, B2_IRQM_CTRL
, TIM_STOP
);
688 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, delay
));
689 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
694 enum led_mode
{ LED_MODE_OFF
, LED_MODE_ON
, LED_MODE_TST
};
695 static void skge_led(struct skge_port
*skge
, enum led_mode mode
)
697 struct skge_hw
*hw
= skge
->hw
;
698 int port
= skge
->port
;
700 spin_lock_bh(&hw
->phy_lock
);
701 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
704 if (hw
->phy_type
== SK_PHY_BCOM
)
705 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_OFF
);
707 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 0);
708 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_T_OFF
);
710 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
711 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 0);
712 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_T_OFF
);
716 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_ON
);
717 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_LINKSYNC_ON
);
719 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
720 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
725 skge_write8(hw
, SK_REG(port
, RX_LED_TST
), LED_T_ON
);
726 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 100);
727 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
729 if (hw
->phy_type
== SK_PHY_BCOM
)
730 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_ON
);
732 skge_write8(hw
, SK_REG(port
, TX_LED_TST
), LED_T_ON
);
733 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 100);
734 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
741 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
742 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
743 PHY_M_LED_MO_DUP(MO_LED_OFF
) |
744 PHY_M_LED_MO_10(MO_LED_OFF
) |
745 PHY_M_LED_MO_100(MO_LED_OFF
) |
746 PHY_M_LED_MO_1000(MO_LED_OFF
) |
747 PHY_M_LED_MO_RX(MO_LED_OFF
));
750 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
,
751 PHY_M_LED_PULS_DUR(PULS_170MS
) |
752 PHY_M_LED_BLINK_RT(BLINK_84MS
) |
756 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
757 PHY_M_LED_MO_RX(MO_LED_OFF
) |
758 (skge
->speed
== SPEED_100
?
759 PHY_M_LED_MO_100(MO_LED_ON
) : 0));
762 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
763 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
764 PHY_M_LED_MO_DUP(MO_LED_ON
) |
765 PHY_M_LED_MO_10(MO_LED_ON
) |
766 PHY_M_LED_MO_100(MO_LED_ON
) |
767 PHY_M_LED_MO_1000(MO_LED_ON
) |
768 PHY_M_LED_MO_RX(MO_LED_ON
));
771 spin_unlock_bh(&hw
->phy_lock
);
774 /* blink LED's for finding board */
775 static int skge_phys_id(struct net_device
*dev
, u32 data
)
777 struct skge_port
*skge
= netdev_priv(dev
);
779 enum led_mode mode
= LED_MODE_TST
;
781 if (!data
|| data
> (u32
)(MAX_SCHEDULE_TIMEOUT
/ HZ
))
782 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
/ HZ
) * 1000;
787 skge_led(skge
, mode
);
788 mode
^= LED_MODE_TST
;
790 if (msleep_interruptible(BLINK_MS
))
795 /* back to regular LED state */
796 skge_led(skge
, netif_running(dev
) ? LED_MODE_ON
: LED_MODE_OFF
);
801 static const struct ethtool_ops skge_ethtool_ops
= {
802 .get_settings
= skge_get_settings
,
803 .set_settings
= skge_set_settings
,
804 .get_drvinfo
= skge_get_drvinfo
,
805 .get_regs_len
= skge_get_regs_len
,
806 .get_regs
= skge_get_regs
,
807 .get_wol
= skge_get_wol
,
808 .set_wol
= skge_set_wol
,
809 .get_msglevel
= skge_get_msglevel
,
810 .set_msglevel
= skge_set_msglevel
,
811 .nway_reset
= skge_nway_reset
,
812 .get_link
= ethtool_op_get_link
,
813 .get_ringparam
= skge_get_ring_param
,
814 .set_ringparam
= skge_set_ring_param
,
815 .get_pauseparam
= skge_get_pauseparam
,
816 .set_pauseparam
= skge_set_pauseparam
,
817 .get_coalesce
= skge_get_coalesce
,
818 .set_coalesce
= skge_set_coalesce
,
819 .set_sg
= skge_set_sg
,
820 .set_tx_csum
= skge_set_tx_csum
,
821 .get_rx_csum
= skge_get_rx_csum
,
822 .set_rx_csum
= skge_set_rx_csum
,
823 .get_strings
= skge_get_strings
,
824 .phys_id
= skge_phys_id
,
825 .get_sset_count
= skge_get_sset_count
,
826 .get_ethtool_stats
= skge_get_ethtool_stats
,
830 * Allocate ring elements and chain them together
831 * One-to-one association of board descriptors with ring elements
833 static int skge_ring_alloc(struct skge_ring
*ring
, void *vaddr
, u32 base
)
835 struct skge_tx_desc
*d
;
836 struct skge_element
*e
;
839 ring
->start
= kcalloc(ring
->count
, sizeof(*e
), GFP_KERNEL
);
843 for (i
= 0, e
= ring
->start
, d
= vaddr
; i
< ring
->count
; i
++, e
++, d
++) {
845 if (i
== ring
->count
- 1) {
846 e
->next
= ring
->start
;
847 d
->next_offset
= base
;
850 d
->next_offset
= base
+ (i
+1) * sizeof(*d
);
853 ring
->to_use
= ring
->to_clean
= ring
->start
;
858 /* Allocate and setup a new buffer for receiving */
859 static void skge_rx_setup(struct skge_port
*skge
, struct skge_element
*e
,
860 struct sk_buff
*skb
, unsigned int bufsize
)
862 struct skge_rx_desc
*rd
= e
->desc
;
865 map
= pci_map_single(skge
->hw
->pdev
, skb
->data
, bufsize
,
869 rd
->dma_hi
= map
>> 32;
871 rd
->csum1_start
= ETH_HLEN
;
872 rd
->csum2_start
= ETH_HLEN
;
878 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| bufsize
;
879 pci_unmap_addr_set(e
, mapaddr
, map
);
880 pci_unmap_len_set(e
, maplen
, bufsize
);
883 /* Resume receiving using existing skb,
884 * Note: DMA address is not changed by chip.
885 * MTU not changed while receiver active.
887 static inline void skge_rx_reuse(struct skge_element
*e
, unsigned int size
)
889 struct skge_rx_desc
*rd
= e
->desc
;
892 rd
->csum2_start
= ETH_HLEN
;
896 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| size
;
900 /* Free all buffers in receive ring, assumes receiver stopped */
901 static void skge_rx_clean(struct skge_port
*skge
)
903 struct skge_hw
*hw
= skge
->hw
;
904 struct skge_ring
*ring
= &skge
->rx_ring
;
905 struct skge_element
*e
;
909 struct skge_rx_desc
*rd
= e
->desc
;
912 pci_unmap_single(hw
->pdev
,
913 pci_unmap_addr(e
, mapaddr
),
914 pci_unmap_len(e
, maplen
),
916 dev_kfree_skb(e
->skb
);
919 } while ((e
= e
->next
) != ring
->start
);
923 /* Allocate buffers for receive ring
924 * For receive: to_clean is next received frame.
926 static int skge_rx_fill(struct net_device
*dev
)
928 struct skge_port
*skge
= netdev_priv(dev
);
929 struct skge_ring
*ring
= &skge
->rx_ring
;
930 struct skge_element
*e
;
936 skb
= __netdev_alloc_skb(dev
, skge
->rx_buf_size
+ NET_IP_ALIGN
,
941 skb_reserve(skb
, NET_IP_ALIGN
);
942 skge_rx_setup(skge
, e
, skb
, skge
->rx_buf_size
);
943 } while ( (e
= e
->next
) != ring
->start
);
945 ring
->to_clean
= ring
->start
;
949 static const char *skge_pause(enum pause_status status
)
954 case FLOW_STAT_REM_SEND
:
956 case FLOW_STAT_LOC_SEND
:
958 case FLOW_STAT_SYMMETRIC
: /* Both station may send PAUSE */
961 return "indeterminated";
966 static void skge_link_up(struct skge_port
*skge
)
968 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
),
969 LED_BLK_OFF
|LED_SYNC_OFF
|LED_ON
);
971 netif_carrier_on(skge
->netdev
);
972 netif_wake_queue(skge
->netdev
);
974 if (netif_msg_link(skge
)) {
976 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
977 skge
->netdev
->name
, skge
->speed
,
978 skge
->duplex
== DUPLEX_FULL
? "full" : "half",
979 skge_pause(skge
->flow_status
));
983 static void skge_link_down(struct skge_port
*skge
)
985 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
986 netif_carrier_off(skge
->netdev
);
987 netif_stop_queue(skge
->netdev
);
989 if (netif_msg_link(skge
))
990 printk(KERN_INFO PFX
"%s: Link is down.\n", skge
->netdev
->name
);
994 static void xm_link_down(struct skge_hw
*hw
, int port
)
996 struct net_device
*dev
= hw
->dev
[port
];
997 struct skge_port
*skge
= netdev_priv(dev
);
998 u16 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1000 xm_write16(hw
, port
, XM_IMSK
, XM_IMSK_DISABLE
);
1002 cmd
&= ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1003 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1005 /* dummy read to ensure writing */
1006 xm_read16(hw
, port
, XM_MMU_CMD
);
1008 if (netif_carrier_ok(dev
))
1009 skge_link_down(skge
);
1012 static int __xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
1016 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
1017 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
1019 if (hw
->phy_type
== SK_PHY_XMAC
)
1022 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1023 if (xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_RDY
)
1030 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
1035 static u16
xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
1038 if (__xm_phy_read(hw
, port
, reg
, &v
))
1039 printk(KERN_WARNING PFX
"%s: phy read timed out\n",
1040 hw
->dev
[port
]->name
);
1044 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
1048 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
1049 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1050 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
1057 xm_write16(hw
, port
, XM_PHY_DATA
, val
);
1058 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1059 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
1066 static void genesis_init(struct skge_hw
*hw
)
1068 /* set blink source counter */
1069 skge_write32(hw
, B2_BSC_INI
, (SK_BLK_DUR
* SK_FACT_53
) / 100);
1070 skge_write8(hw
, B2_BSC_CTRL
, BSC_START
);
1072 /* configure mac arbiter */
1073 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
1075 /* configure mac arbiter timeout values */
1076 skge_write8(hw
, B3_MA_TOINI_RX1
, SK_MAC_TO_53
);
1077 skge_write8(hw
, B3_MA_TOINI_RX2
, SK_MAC_TO_53
);
1078 skge_write8(hw
, B3_MA_TOINI_TX1
, SK_MAC_TO_53
);
1079 skge_write8(hw
, B3_MA_TOINI_TX2
, SK_MAC_TO_53
);
1081 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
1082 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1083 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1084 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1086 /* configure packet arbiter timeout */
1087 skge_write16(hw
, B3_PA_CTRL
, PA_RST_CLR
);
1088 skge_write16(hw
, B3_PA_TOINI_RX1
, SK_PKT_TO_MAX
);
1089 skge_write16(hw
, B3_PA_TOINI_TX1
, SK_PKT_TO_MAX
);
1090 skge_write16(hw
, B3_PA_TOINI_RX2
, SK_PKT_TO_MAX
);
1091 skge_write16(hw
, B3_PA_TOINI_TX2
, SK_PKT_TO_MAX
);
1094 static void genesis_reset(struct skge_hw
*hw
, int port
)
1096 const u8 zero
[8] = { 0 };
1098 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
1100 /* reset the statistics module */
1101 xm_write32(hw
, port
, XM_GP_PORT
, XM_GP_RES_STAT
);
1102 xm_write16(hw
, port
, XM_IMSK
, XM_IMSK_DISABLE
);
1103 xm_write32(hw
, port
, XM_MODE
, 0); /* clear Mode Reg */
1104 xm_write16(hw
, port
, XM_TX_CMD
, 0); /* reset TX CMD Reg */
1105 xm_write16(hw
, port
, XM_RX_CMD
, 0); /* reset RX CMD Reg */
1107 /* disable Broadcom PHY IRQ */
1108 if (hw
->phy_type
== SK_PHY_BCOM
)
1109 xm_write16(hw
, port
, PHY_BCOM_INT_MASK
, 0xffff);
1111 xm_outhash(hw
, port
, XM_HSM
, zero
);
1115 /* Convert mode to MII values */
1116 static const u16 phy_pause_map
[] = {
1117 [FLOW_MODE_NONE
] = 0,
1118 [FLOW_MODE_LOC_SEND
] = PHY_AN_PAUSE_ASYM
,
1119 [FLOW_MODE_SYMMETRIC
] = PHY_AN_PAUSE_CAP
,
1120 [FLOW_MODE_SYM_OR_REM
] = PHY_AN_PAUSE_CAP
| PHY_AN_PAUSE_ASYM
,
1123 /* special defines for FIBER (88E1011S only) */
1124 static const u16 fiber_pause_map
[] = {
1125 [FLOW_MODE_NONE
] = PHY_X_P_NO_PAUSE
,
1126 [FLOW_MODE_LOC_SEND
] = PHY_X_P_ASYM_MD
,
1127 [FLOW_MODE_SYMMETRIC
] = PHY_X_P_SYM_MD
,
1128 [FLOW_MODE_SYM_OR_REM
] = PHY_X_P_BOTH_MD
,
1132 /* Check status of Broadcom phy link */
1133 static void bcom_check_link(struct skge_hw
*hw
, int port
)
1135 struct net_device
*dev
= hw
->dev
[port
];
1136 struct skge_port
*skge
= netdev_priv(dev
);
1139 /* read twice because of latch */
1140 xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1141 status
= xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1143 if ((status
& PHY_ST_LSYNC
) == 0) {
1144 xm_link_down(hw
, port
);
1148 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1151 if (!(status
& PHY_ST_AN_OVER
))
1154 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1155 if (lpa
& PHY_B_AN_RF
) {
1156 printk(KERN_NOTICE PFX
"%s: remote fault\n",
1161 aux
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_STAT
);
1163 /* Check Duplex mismatch */
1164 switch (aux
& PHY_B_AS_AN_RES_MSK
) {
1165 case PHY_B_RES_1000FD
:
1166 skge
->duplex
= DUPLEX_FULL
;
1168 case PHY_B_RES_1000HD
:
1169 skge
->duplex
= DUPLEX_HALF
;
1172 printk(KERN_NOTICE PFX
"%s: duplex mismatch\n",
1177 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1178 switch (aux
& PHY_B_AS_PAUSE_MSK
) {
1179 case PHY_B_AS_PAUSE_MSK
:
1180 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
1183 skge
->flow_status
= FLOW_STAT_REM_SEND
;
1186 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
1189 skge
->flow_status
= FLOW_STAT_NONE
;
1191 skge
->speed
= SPEED_1000
;
1194 if (!netif_carrier_ok(dev
))
1195 genesis_link_up(skge
);
1198 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1199 * Phy on for 100 or 10Mbit operation
1201 static void bcom_phy_init(struct skge_port
*skge
)
1203 struct skge_hw
*hw
= skge
->hw
;
1204 int port
= skge
->port
;
1206 u16 id1
, r
, ext
, ctl
;
1208 /* magic workaround patterns for Broadcom */
1209 static const struct {
1213 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1214 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1215 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1216 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1218 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1219 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1222 /* read Id from external PHY (all have the same address) */
1223 id1
= xm_phy_read(hw
, port
, PHY_XMAC_ID1
);
1225 /* Optimize MDIO transfer by suppressing preamble. */
1226 r
= xm_read16(hw
, port
, XM_MMU_CMD
);
1228 xm_write16(hw
, port
, XM_MMU_CMD
,r
);
1231 case PHY_BCOM_ID1_C0
:
1233 * Workaround BCOM Errata for the C0 type.
1234 * Write magic patterns to reserved registers.
1236 for (i
= 0; i
< ARRAY_SIZE(C0hack
); i
++)
1237 xm_phy_write(hw
, port
,
1238 C0hack
[i
].reg
, C0hack
[i
].val
);
1241 case PHY_BCOM_ID1_A1
:
1243 * Workaround BCOM Errata for the A1 type.
1244 * Write magic patterns to reserved registers.
1246 for (i
= 0; i
< ARRAY_SIZE(A1hack
); i
++)
1247 xm_phy_write(hw
, port
,
1248 A1hack
[i
].reg
, A1hack
[i
].val
);
1253 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1254 * Disable Power Management after reset.
1256 r
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
);
1257 r
|= PHY_B_AC_DIS_PM
;
1258 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
, r
);
1261 xm_read16(hw
, port
, XM_ISRC
);
1263 ext
= PHY_B_PEC_EN_LTR
; /* enable tx led */
1264 ctl
= PHY_CT_SP1000
; /* always 1000mbit */
1266 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1268 * Workaround BCOM Errata #1 for the C5 type.
1269 * 1000Base-T Link Acquisition Failure in Slave Mode
1270 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1272 u16 adv
= PHY_B_1000C_RD
;
1273 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1274 adv
|= PHY_B_1000C_AHD
;
1275 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1276 adv
|= PHY_B_1000C_AFD
;
1277 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, adv
);
1279 ctl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1281 if (skge
->duplex
== DUPLEX_FULL
)
1282 ctl
|= PHY_CT_DUP_MD
;
1283 /* Force to slave */
1284 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, PHY_B_1000C_MSE
);
1287 /* Set autonegotiation pause parameters */
1288 xm_phy_write(hw
, port
, PHY_BCOM_AUNE_ADV
,
1289 phy_pause_map
[skge
->flow_control
] | PHY_AN_CSMA
);
1291 /* Handle Jumbo frames */
1292 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
1293 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1294 PHY_B_AC_TX_TST
| PHY_B_AC_LONG_PACK
);
1296 ext
|= PHY_B_PEC_HIGH_LA
;
1300 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, ext
);
1301 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
, ctl
);
1303 /* Use link status change interrupt */
1304 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1307 static void xm_phy_init(struct skge_port
*skge
)
1309 struct skge_hw
*hw
= skge
->hw
;
1310 int port
= skge
->port
;
1313 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1314 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1315 ctrl
|= PHY_X_AN_HD
;
1316 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1317 ctrl
|= PHY_X_AN_FD
;
1319 ctrl
|= fiber_pause_map
[skge
->flow_control
];
1321 xm_phy_write(hw
, port
, PHY_XMAC_AUNE_ADV
, ctrl
);
1323 /* Restart Auto-negotiation */
1324 ctrl
= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1326 /* Set DuplexMode in Config register */
1327 if (skge
->duplex
== DUPLEX_FULL
)
1328 ctrl
|= PHY_CT_DUP_MD
;
1330 * Do NOT enable Auto-negotiation here. This would hold
1331 * the link down because no IDLEs are transmitted
1335 xm_phy_write(hw
, port
, PHY_XMAC_CTRL
, ctrl
);
1337 /* Poll PHY for status changes */
1338 mod_timer(&skge
->link_timer
, jiffies
+ LINK_HZ
);
1341 static int xm_check_link(struct net_device
*dev
)
1343 struct skge_port
*skge
= netdev_priv(dev
);
1344 struct skge_hw
*hw
= skge
->hw
;
1345 int port
= skge
->port
;
1348 /* read twice because of latch */
1349 xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1350 status
= xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1352 if ((status
& PHY_ST_LSYNC
) == 0) {
1353 xm_link_down(hw
, port
);
1357 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1360 if (!(status
& PHY_ST_AN_OVER
))
1363 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1364 if (lpa
& PHY_B_AN_RF
) {
1365 printk(KERN_NOTICE PFX
"%s: remote fault\n",
1370 res
= xm_phy_read(hw
, port
, PHY_XMAC_RES_ABI
);
1372 /* Check Duplex mismatch */
1373 switch (res
& (PHY_X_RS_HD
| PHY_X_RS_FD
)) {
1375 skge
->duplex
= DUPLEX_FULL
;
1378 skge
->duplex
= DUPLEX_HALF
;
1381 printk(KERN_NOTICE PFX
"%s: duplex mismatch\n",
1386 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1387 if ((skge
->flow_control
== FLOW_MODE_SYMMETRIC
||
1388 skge
->flow_control
== FLOW_MODE_SYM_OR_REM
) &&
1389 (lpa
& PHY_X_P_SYM_MD
))
1390 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
1391 else if (skge
->flow_control
== FLOW_MODE_SYM_OR_REM
&&
1392 (lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_ASYM_MD
)
1393 /* Enable PAUSE receive, disable PAUSE transmit */
1394 skge
->flow_status
= FLOW_STAT_REM_SEND
;
1395 else if (skge
->flow_control
== FLOW_MODE_LOC_SEND
&&
1396 (lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_BOTH_MD
)
1397 /* Disable PAUSE receive, enable PAUSE transmit */
1398 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
1400 skge
->flow_status
= FLOW_STAT_NONE
;
1402 skge
->speed
= SPEED_1000
;
1405 if (!netif_carrier_ok(dev
))
1406 genesis_link_up(skge
);
1410 /* Poll to check for link coming up.
1412 * Since internal PHY is wired to a level triggered pin, can't
1413 * get an interrupt when carrier is detected, need to poll for
1416 static void xm_link_timer(unsigned long arg
)
1418 struct skge_port
*skge
= (struct skge_port
*) arg
;
1419 struct net_device
*dev
= skge
->netdev
;
1420 struct skge_hw
*hw
= skge
->hw
;
1421 int port
= skge
->port
;
1423 unsigned long flags
;
1425 if (!netif_running(dev
))
1428 spin_lock_irqsave(&hw
->phy_lock
, flags
);
1431 * Verify that the link by checking GPIO register three times.
1432 * This pin has the signal from the link_sync pin connected to it.
1434 for (i
= 0; i
< 3; i
++) {
1435 if (xm_read16(hw
, port
, XM_GP_PORT
) & XM_GP_INP_ASS
)
1439 /* Re-enable interrupt to detect link down */
1440 if (xm_check_link(dev
)) {
1441 u16 msk
= xm_read16(hw
, port
, XM_IMSK
);
1442 msk
&= ~XM_IS_INP_ASS
;
1443 xm_write16(hw
, port
, XM_IMSK
, msk
);
1444 xm_read16(hw
, port
, XM_ISRC
);
1447 mod_timer(&skge
->link_timer
,
1448 round_jiffies(jiffies
+ LINK_HZ
));
1450 spin_unlock_irqrestore(&hw
->phy_lock
, flags
);
1453 static void genesis_mac_init(struct skge_hw
*hw
, int port
)
1455 struct net_device
*dev
= hw
->dev
[port
];
1456 struct skge_port
*skge
= netdev_priv(dev
);
1457 int jumbo
= hw
->dev
[port
]->mtu
> ETH_DATA_LEN
;
1460 const u8 zero
[6] = { 0 };
1462 for (i
= 0; i
< 10; i
++) {
1463 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
1465 if (skge_read16(hw
, SK_REG(port
, TX_MFF_CTRL1
)) & MFF_SET_MAC_RST
)
1470 printk(KERN_WARNING PFX
"%s: genesis reset failed\n", dev
->name
);
1473 /* Unreset the XMAC. */
1474 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_CLR_MAC_RST
);
1477 * Perform additional initialization for external PHYs,
1478 * namely for the 1000baseTX cards that use the XMAC's
1481 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1482 /* Take external Phy out of reset */
1483 r
= skge_read32(hw
, B2_GP_IO
);
1485 r
|= GP_DIR_0
|GP_IO_0
;
1487 r
|= GP_DIR_2
|GP_IO_2
;
1489 skge_write32(hw
, B2_GP_IO
, r
);
1491 /* Enable GMII interface */
1492 xm_write16(hw
, port
, XM_HW_CFG
, XM_HW_GMII_MD
);
1496 switch(hw
->phy_type
) {
1501 bcom_phy_init(skge
);
1502 bcom_check_link(hw
, port
);
1505 /* Set Station Address */
1506 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
1508 /* We don't use match addresses so clear */
1509 for (i
= 1; i
< 16; i
++)
1510 xm_outaddr(hw
, port
, XM_EXM(i
), zero
);
1512 /* Clear MIB counters */
1513 xm_write16(hw
, port
, XM_STAT_CMD
,
1514 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1515 /* Clear two times according to Errata #3 */
1516 xm_write16(hw
, port
, XM_STAT_CMD
,
1517 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1519 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1520 xm_write16(hw
, port
, XM_RX_HI_WM
, 1450);
1522 /* We don't need the FCS appended to the packet. */
1523 r
= XM_RX_LENERR_OK
| XM_RX_STRIP_FCS
;
1525 r
|= XM_RX_BIG_PK_OK
;
1527 if (skge
->duplex
== DUPLEX_HALF
) {
1529 * If in manual half duplex mode the other side might be in
1530 * full duplex mode, so ignore if a carrier extension is not seen
1531 * on frames received
1533 r
|= XM_RX_DIS_CEXT
;
1535 xm_write16(hw
, port
, XM_RX_CMD
, r
);
1538 /* We want short frames padded to 60 bytes. */
1539 xm_write16(hw
, port
, XM_TX_CMD
, XM_TX_AUTO_PAD
);
1542 * Bump up the transmit threshold. This helps hold off transmit
1543 * underruns when we're blasting traffic from both ports at once.
1545 xm_write16(hw
, port
, XM_TX_THR
, 512);
1548 * Enable the reception of all error frames. This is is
1549 * a necessary evil due to the design of the XMAC. The
1550 * XMAC's receive FIFO is only 8K in size, however jumbo
1551 * frames can be up to 9000 bytes in length. When bad
1552 * frame filtering is enabled, the XMAC's RX FIFO operates
1553 * in 'store and forward' mode. For this to work, the
1554 * entire frame has to fit into the FIFO, but that means
1555 * that jumbo frames larger than 8192 bytes will be
1556 * truncated. Disabling all bad frame filtering causes
1557 * the RX FIFO to operate in streaming mode, in which
1558 * case the XMAC will start transferring frames out of the
1559 * RX FIFO as soon as the FIFO threshold is reached.
1561 xm_write32(hw
, port
, XM_MODE
, XM_DEF_MODE
);
1565 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1566 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1567 * and 'Octets Rx OK Hi Cnt Ov'.
1569 xm_write32(hw
, port
, XM_RX_EV_MSK
, XMR_DEF_MSK
);
1572 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1573 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1574 * and 'Octets Tx OK Hi Cnt Ov'.
1576 xm_write32(hw
, port
, XM_TX_EV_MSK
, XMT_DEF_MSK
);
1578 /* Configure MAC arbiter */
1579 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
1581 /* configure timeout values */
1582 skge_write8(hw
, B3_MA_TOINI_RX1
, 72);
1583 skge_write8(hw
, B3_MA_TOINI_RX2
, 72);
1584 skge_write8(hw
, B3_MA_TOINI_TX1
, 72);
1585 skge_write8(hw
, B3_MA_TOINI_TX2
, 72);
1587 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
1588 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1589 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1590 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1592 /* Configure Rx MAC FIFO */
1593 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_CLR
);
1594 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_TIM_PAT
);
1595 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1597 /* Configure Tx MAC FIFO */
1598 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_CLR
);
1599 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_TX_CTRL_DEF
);
1600 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1603 /* Enable frame flushing if jumbo frames used */
1604 skge_write16(hw
, SK_REG(port
,RX_MFF_CTRL1
), MFF_ENA_FLUSH
);
1606 /* enable timeout timers if normal frames */
1607 skge_write16(hw
, B3_PA_CTRL
,
1608 (port
== 0) ? PA_ENA_TO_TX1
: PA_ENA_TO_TX2
);
1612 static void genesis_stop(struct skge_port
*skge
)
1614 struct skge_hw
*hw
= skge
->hw
;
1615 int port
= skge
->port
;
1618 genesis_reset(hw
, port
);
1620 /* Clear Tx packet arbiter timeout IRQ */
1621 skge_write16(hw
, B3_PA_CTRL
,
1622 port
== 0 ? PA_CLR_TO_TX1
: PA_CLR_TO_TX2
);
1625 * If the transfer sticks at the MAC the STOP command will not
1626 * terminate if we don't flush the XMAC's transmit FIFO !
1628 xm_write32(hw
, port
, XM_MODE
,
1629 xm_read32(hw
, port
, XM_MODE
)|XM_MD_FTF
);
1633 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_SET_MAC_RST
);
1635 /* For external PHYs there must be special handling */
1636 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1637 reg
= skge_read32(hw
, B2_GP_IO
);
1645 skge_write32(hw
, B2_GP_IO
, reg
);
1646 skge_read32(hw
, B2_GP_IO
);
1649 xm_write16(hw
, port
, XM_MMU_CMD
,
1650 xm_read16(hw
, port
, XM_MMU_CMD
)
1651 & ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
));
1653 xm_read16(hw
, port
, XM_MMU_CMD
);
1657 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
)
1659 struct skge_hw
*hw
= skge
->hw
;
1660 int port
= skge
->port
;
1662 unsigned long timeout
= jiffies
+ HZ
;
1664 xm_write16(hw
, port
,
1665 XM_STAT_CMD
, XM_SC_SNP_TXC
| XM_SC_SNP_RXC
);
1667 /* wait for update to complete */
1668 while (xm_read16(hw
, port
, XM_STAT_CMD
)
1669 & (XM_SC_SNP_TXC
| XM_SC_SNP_RXC
)) {
1670 if (time_after(jiffies
, timeout
))
1675 /* special case for 64 bit octet counter */
1676 data
[0] = (u64
) xm_read32(hw
, port
, XM_TXO_OK_HI
) << 32
1677 | xm_read32(hw
, port
, XM_TXO_OK_LO
);
1678 data
[1] = (u64
) xm_read32(hw
, port
, XM_RXO_OK_HI
) << 32
1679 | xm_read32(hw
, port
, XM_RXO_OK_LO
);
1681 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
1682 data
[i
] = xm_read32(hw
, port
, skge_stats
[i
].xmac_offset
);
1685 static void genesis_mac_intr(struct skge_hw
*hw
, int port
)
1687 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1688 u16 status
= xm_read16(hw
, port
, XM_ISRC
);
1690 if (netif_msg_intr(skge
))
1691 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
1692 skge
->netdev
->name
, status
);
1694 if (hw
->phy_type
== SK_PHY_XMAC
&& (status
& XM_IS_INP_ASS
)) {
1695 xm_link_down(hw
, port
);
1696 mod_timer(&skge
->link_timer
, jiffies
+ 1);
1699 if (status
& XM_IS_TXF_UR
) {
1700 xm_write32(hw
, port
, XM_MODE
, XM_MD_FTF
);
1701 ++skge
->net_stats
.tx_fifo_errors
;
1704 if (status
& XM_IS_RXF_OV
) {
1705 xm_write32(hw
, port
, XM_MODE
, XM_MD_FRF
);
1706 ++skge
->net_stats
.rx_fifo_errors
;
1710 static void genesis_link_up(struct skge_port
*skge
)
1712 struct skge_hw
*hw
= skge
->hw
;
1713 int port
= skge
->port
;
1717 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1720 * enabling pause frame reception is required for 1000BT
1721 * because the XMAC is not reset if the link is going down
1723 if (skge
->flow_status
== FLOW_STAT_NONE
||
1724 skge
->flow_status
== FLOW_STAT_LOC_SEND
)
1725 /* Disable Pause Frame Reception */
1726 cmd
|= XM_MMU_IGN_PF
;
1728 /* Enable Pause Frame Reception */
1729 cmd
&= ~XM_MMU_IGN_PF
;
1731 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1733 mode
= xm_read32(hw
, port
, XM_MODE
);
1734 if (skge
->flow_status
== FLOW_STAT_SYMMETRIC
||
1735 skge
->flow_status
== FLOW_STAT_LOC_SEND
) {
1737 * Configure Pause Frame Generation
1738 * Use internal and external Pause Frame Generation.
1739 * Sending pause frames is edge triggered.
1740 * Send a Pause frame with the maximum pause time if
1741 * internal oder external FIFO full condition occurs.
1742 * Send a zero pause time frame to re-start transmission.
1744 /* XM_PAUSE_DA = '010000C28001' (default) */
1745 /* XM_MAC_PTIME = 0xffff (maximum) */
1746 /* remember this value is defined in big endian (!) */
1747 xm_write16(hw
, port
, XM_MAC_PTIME
, 0xffff);
1749 mode
|= XM_PAUSE_MODE
;
1750 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_PAUSE
);
1753 * disable pause frame generation is required for 1000BT
1754 * because the XMAC is not reset if the link is going down
1756 /* Disable Pause Mode in Mode Register */
1757 mode
&= ~XM_PAUSE_MODE
;
1759 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_DIS_PAUSE
);
1762 xm_write32(hw
, port
, XM_MODE
, mode
);
1764 /* Turn on detection of Tx underrun, Rx overrun */
1765 msk
= xm_read16(hw
, port
, XM_IMSK
);
1766 msk
&= ~(XM_IS_RXF_OV
| XM_IS_TXF_UR
);
1767 xm_write16(hw
, port
, XM_IMSK
, msk
);
1769 xm_read16(hw
, port
, XM_ISRC
);
1771 /* get MMU Command Reg. */
1772 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1773 if (hw
->phy_type
!= SK_PHY_XMAC
&& skge
->duplex
== DUPLEX_FULL
)
1774 cmd
|= XM_MMU_GMII_FD
;
1777 * Workaround BCOM Errata (#10523) for all BCom Phys
1778 * Enable Power Management after link up
1780 if (hw
->phy_type
== SK_PHY_BCOM
) {
1781 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1782 xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
)
1783 & ~PHY_B_AC_DIS_PM
);
1784 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1788 xm_write16(hw
, port
, XM_MMU_CMD
,
1789 cmd
| XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1794 static inline void bcom_phy_intr(struct skge_port
*skge
)
1796 struct skge_hw
*hw
= skge
->hw
;
1797 int port
= skge
->port
;
1800 isrc
= xm_phy_read(hw
, port
, PHY_BCOM_INT_STAT
);
1801 if (netif_msg_intr(skge
))
1802 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x\n",
1803 skge
->netdev
->name
, isrc
);
1805 if (isrc
& PHY_B_IS_PSE
)
1806 printk(KERN_ERR PFX
"%s: uncorrectable pair swap error\n",
1807 hw
->dev
[port
]->name
);
1809 /* Workaround BCom Errata:
1810 * enable and disable loopback mode if "NO HCD" occurs.
1812 if (isrc
& PHY_B_IS_NO_HDCL
) {
1813 u16 ctrl
= xm_phy_read(hw
, port
, PHY_BCOM_CTRL
);
1814 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1815 ctrl
| PHY_CT_LOOP
);
1816 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1817 ctrl
& ~PHY_CT_LOOP
);
1820 if (isrc
& (PHY_B_IS_AN_PR
| PHY_B_IS_LST_CHANGE
))
1821 bcom_check_link(hw
, port
);
1825 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
1829 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
1830 gma_write16(hw
, port
, GM_SMI_CTRL
,
1831 GM_SMI_CT_PHY_AD(hw
->phy_addr
) | GM_SMI_CT_REG_AD(reg
));
1832 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1835 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
1839 printk(KERN_WARNING PFX
"%s: phy write timeout\n",
1840 hw
->dev
[port
]->name
);
1844 static int __gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
1848 gma_write16(hw
, port
, GM_SMI_CTRL
,
1849 GM_SMI_CT_PHY_AD(hw
->phy_addr
)
1850 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
1852 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1854 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
)
1860 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
1864 static u16
gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
1867 if (__gm_phy_read(hw
, port
, reg
, &v
))
1868 printk(KERN_WARNING PFX
"%s: phy read timeout\n",
1869 hw
->dev
[port
]->name
);
1873 /* Marvell Phy Initialization */
1874 static void yukon_init(struct skge_hw
*hw
, int port
)
1876 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1877 u16 ctrl
, ct1000
, adv
;
1879 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1880 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
1882 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
1883 PHY_M_EC_MAC_S_MSK
);
1884 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
1886 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1888 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
1891 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
1892 if (skge
->autoneg
== AUTONEG_DISABLE
)
1893 ctrl
&= ~PHY_CT_ANE
;
1895 ctrl
|= PHY_CT_RESET
;
1896 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1902 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1904 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1905 ct1000
|= PHY_M_1000C_AFD
;
1906 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1907 ct1000
|= PHY_M_1000C_AHD
;
1908 if (skge
->advertising
& ADVERTISED_100baseT_Full
)
1909 adv
|= PHY_M_AN_100_FD
;
1910 if (skge
->advertising
& ADVERTISED_100baseT_Half
)
1911 adv
|= PHY_M_AN_100_HD
;
1912 if (skge
->advertising
& ADVERTISED_10baseT_Full
)
1913 adv
|= PHY_M_AN_10_FD
;
1914 if (skge
->advertising
& ADVERTISED_10baseT_Half
)
1915 adv
|= PHY_M_AN_10_HD
;
1917 /* Set Flow-control capabilities */
1918 adv
|= phy_pause_map
[skge
->flow_control
];
1920 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1921 adv
|= PHY_M_AN_1000X_AFD
;
1922 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1923 adv
|= PHY_M_AN_1000X_AHD
;
1925 adv
|= fiber_pause_map
[skge
->flow_control
];
1928 /* Restart Auto-negotiation */
1929 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1931 /* forced speed/duplex settings */
1932 ct1000
= PHY_M_1000C_MSE
;
1934 if (skge
->duplex
== DUPLEX_FULL
)
1935 ctrl
|= PHY_CT_DUP_MD
;
1937 switch (skge
->speed
) {
1939 ctrl
|= PHY_CT_SP1000
;
1942 ctrl
|= PHY_CT_SP100
;
1946 ctrl
|= PHY_CT_RESET
;
1949 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
1951 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
1952 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1954 /* Enable phy interrupt on autonegotiation complete (or link up) */
1955 if (skge
->autoneg
== AUTONEG_ENABLE
)
1956 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_MSK
);
1958 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
1961 static void yukon_reset(struct skge_hw
*hw
, int port
)
1963 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);/* disable PHY IRQs */
1964 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
1965 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
1966 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
1967 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
1969 gma_write16(hw
, port
, GM_RX_CTRL
,
1970 gma_read16(hw
, port
, GM_RX_CTRL
)
1971 | GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
1974 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1975 static int is_yukon_lite_a0(struct skge_hw
*hw
)
1980 if (hw
->chip_id
!= CHIP_ID_YUKON
)
1983 reg
= skge_read32(hw
, B2_FAR
);
1984 skge_write8(hw
, B2_FAR
+ 3, 0xff);
1985 ret
= (skge_read8(hw
, B2_FAR
+ 3) != 0);
1986 skge_write32(hw
, B2_FAR
, reg
);
1990 static void yukon_mac_init(struct skge_hw
*hw
, int port
)
1992 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1995 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
1997 /* WA code for COMA mode -- set PHY reset */
1998 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1999 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
2000 reg
= skge_read32(hw
, B2_GP_IO
);
2001 reg
|= GP_DIR_9
| GP_IO_9
;
2002 skge_write32(hw
, B2_GP_IO
, reg
);
2006 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
2007 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2009 /* WA code for COMA mode -- clear PHY reset */
2010 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
2011 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
2012 reg
= skge_read32(hw
, B2_GP_IO
);
2015 skge_write32(hw
, B2_GP_IO
, reg
);
2018 /* Set hardware config mode */
2019 reg
= GPC_INT_POL_HI
| GPC_DIS_FC
| GPC_DIS_SLEEP
|
2020 GPC_ENA_XC
| GPC_ANEG_ADV_ALL_M
| GPC_ENA_PAUSE
;
2021 reg
|= hw
->copper
? GPC_HWCFG_GMII_COP
: GPC_HWCFG_GMII_FIB
;
2023 /* Clear GMC reset */
2024 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_SET
);
2025 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_CLR
);
2026 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
| GMC_RST_CLR
);
2028 if (skge
->autoneg
== AUTONEG_DISABLE
) {
2029 reg
= GM_GPCR_AU_ALL_DIS
;
2030 gma_write16(hw
, port
, GM_GP_CTRL
,
2031 gma_read16(hw
, port
, GM_GP_CTRL
) | reg
);
2033 switch (skge
->speed
) {
2035 reg
&= ~GM_GPCR_SPEED_100
;
2036 reg
|= GM_GPCR_SPEED_1000
;
2039 reg
&= ~GM_GPCR_SPEED_1000
;
2040 reg
|= GM_GPCR_SPEED_100
;
2043 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
2047 if (skge
->duplex
== DUPLEX_FULL
)
2048 reg
|= GM_GPCR_DUP_FULL
;
2050 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
2052 switch (skge
->flow_control
) {
2053 case FLOW_MODE_NONE
:
2054 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2055 reg
|= GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
2057 case FLOW_MODE_LOC_SEND
:
2058 /* disable Rx flow-control */
2059 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
2061 case FLOW_MODE_SYMMETRIC
:
2062 case FLOW_MODE_SYM_OR_REM
:
2063 /* enable Tx & Rx flow-control */
2067 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2068 skge_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2070 yukon_init(hw
, port
);
2073 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
2074 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
2076 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
2077 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8*i
);
2078 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
2080 /* transmit control */
2081 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
2083 /* receive control reg: unicast + multicast + no FCS */
2084 gma_write16(hw
, port
, GM_RX_CTRL
,
2085 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
2087 /* transmit flow control */
2088 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
2090 /* transmit parameter */
2091 gma_write16(hw
, port
, GM_TX_PARAM
,
2092 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
2093 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
2094 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
));
2096 /* serial mode register */
2097 reg
= GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2098 if (hw
->dev
[port
]->mtu
> 1500)
2099 reg
|= GM_SMOD_JUMBO_ENA
;
2101 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
2103 /* physical address: used for pause frames */
2104 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
2105 /* virtual address for data */
2106 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
2108 /* enable interrupt mask for counter overflows */
2109 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
2110 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
2111 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
2113 /* Initialize Mac Fifo */
2115 /* Configure Rx MAC FIFO */
2116 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), RX_FF_FL_DEF_MSK
);
2117 reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
2119 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2120 if (is_yukon_lite_a0(hw
))
2121 reg
&= ~GMF_RX_F_FL_ON
;
2123 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
2124 skge_write16(hw
, SK_REG(port
, RX_GMF_CTRL_T
), reg
);
2126 * because Pause Packet Truncation in GMAC is not working
2127 * we have to increase the Flush Threshold to 64 bytes
2128 * in order to flush pause packets in Rx FIFO on Yukon-1
2130 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
2132 /* Configure Tx MAC FIFO */
2133 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
2134 skge_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
2137 /* Go into power down mode */
2138 static void yukon_suspend(struct skge_hw
*hw
, int port
)
2142 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2143 ctrl
|= PHY_M_PC_POL_R_DIS
;
2144 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
2146 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2147 ctrl
|= PHY_CT_RESET
;
2148 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2150 /* switch IEEE compatible power down mode on */
2151 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2152 ctrl
|= PHY_CT_PDOWN
;
2153 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2156 static void yukon_stop(struct skge_port
*skge
)
2158 struct skge_hw
*hw
= skge
->hw
;
2159 int port
= skge
->port
;
2161 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
2162 yukon_reset(hw
, port
);
2164 gma_write16(hw
, port
, GM_GP_CTRL
,
2165 gma_read16(hw
, port
, GM_GP_CTRL
)
2166 & ~(GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
));
2167 gma_read16(hw
, port
, GM_GP_CTRL
);
2169 yukon_suspend(hw
, port
);
2171 /* set GPHY Control reset */
2172 skge_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
2173 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2176 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
)
2178 struct skge_hw
*hw
= skge
->hw
;
2179 int port
= skge
->port
;
2182 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2183 | gma_read32(hw
, port
, GM_TXO_OK_LO
);
2184 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2185 | gma_read32(hw
, port
, GM_RXO_OK_LO
);
2187 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
2188 data
[i
] = gma_read32(hw
, port
,
2189 skge_stats
[i
].gma_offset
);
2192 static void yukon_mac_intr(struct skge_hw
*hw
, int port
)
2194 struct net_device
*dev
= hw
->dev
[port
];
2195 struct skge_port
*skge
= netdev_priv(dev
);
2196 u8 status
= skge_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2198 if (netif_msg_intr(skge
))
2199 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
2202 if (status
& GM_IS_RX_FF_OR
) {
2203 ++skge
->net_stats
.rx_fifo_errors
;
2204 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2207 if (status
& GM_IS_TX_FF_UR
) {
2208 ++skge
->net_stats
.tx_fifo_errors
;
2209 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2214 static u16
yukon_speed(const struct skge_hw
*hw
, u16 aux
)
2216 switch (aux
& PHY_M_PS_SPEED_MSK
) {
2217 case PHY_M_PS_SPEED_1000
:
2219 case PHY_M_PS_SPEED_100
:
2226 static void yukon_link_up(struct skge_port
*skge
)
2228 struct skge_hw
*hw
= skge
->hw
;
2229 int port
= skge
->port
;
2232 /* Enable Transmit FIFO Underrun */
2233 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
2235 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2236 if (skge
->duplex
== DUPLEX_FULL
|| skge
->autoneg
== AUTONEG_ENABLE
)
2237 reg
|= GM_GPCR_DUP_FULL
;
2240 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
2241 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2243 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
2247 static void yukon_link_down(struct skge_port
*skge
)
2249 struct skge_hw
*hw
= skge
->hw
;
2250 int port
= skge
->port
;
2253 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2254 ctrl
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2255 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
2257 if (skge
->flow_status
== FLOW_STAT_REM_SEND
) {
2258 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2259 ctrl
|= PHY_M_AN_ASP
;
2260 /* restore Asymmetric Pause bit */
2261 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, ctrl
);
2264 skge_link_down(skge
);
2266 yukon_init(hw
, port
);
2269 static void yukon_phy_intr(struct skge_port
*skge
)
2271 struct skge_hw
*hw
= skge
->hw
;
2272 int port
= skge
->port
;
2273 const char *reason
= NULL
;
2274 u16 istatus
, phystat
;
2276 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2277 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2279 if (netif_msg_intr(skge
))
2280 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x 0x%x\n",
2281 skge
->netdev
->name
, istatus
, phystat
);
2283 if (istatus
& PHY_M_IS_AN_COMPL
) {
2284 if (gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
)
2286 reason
= "remote fault";
2290 if (gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
2291 reason
= "master/slave fault";
2295 if (!(phystat
& PHY_M_PS_SPDUP_RES
)) {
2296 reason
= "speed/duplex";
2300 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
)
2301 ? DUPLEX_FULL
: DUPLEX_HALF
;
2302 skge
->speed
= yukon_speed(hw
, phystat
);
2304 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2305 switch (phystat
& PHY_M_PS_PAUSE_MSK
) {
2306 case PHY_M_PS_PAUSE_MSK
:
2307 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
2309 case PHY_M_PS_RX_P_EN
:
2310 skge
->flow_status
= FLOW_STAT_REM_SEND
;
2312 case PHY_M_PS_TX_P_EN
:
2313 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
2316 skge
->flow_status
= FLOW_STAT_NONE
;
2319 if (skge
->flow_status
== FLOW_STAT_NONE
||
2320 (skge
->speed
< SPEED_1000
&& skge
->duplex
== DUPLEX_HALF
))
2321 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2323 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2324 yukon_link_up(skge
);
2328 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2329 skge
->speed
= yukon_speed(hw
, phystat
);
2331 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2332 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2333 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2334 if (phystat
& PHY_M_PS_LINK_UP
)
2335 yukon_link_up(skge
);
2337 yukon_link_down(skge
);
2341 printk(KERN_ERR PFX
"%s: autonegotiation failed (%s)\n",
2342 skge
->netdev
->name
, reason
);
2344 /* XXX restart autonegotiation? */
2347 static void skge_phy_reset(struct skge_port
*skge
)
2349 struct skge_hw
*hw
= skge
->hw
;
2350 int port
= skge
->port
;
2351 struct net_device
*dev
= hw
->dev
[port
];
2353 netif_stop_queue(skge
->netdev
);
2354 netif_carrier_off(skge
->netdev
);
2356 spin_lock_bh(&hw
->phy_lock
);
2357 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2358 genesis_reset(hw
, port
);
2359 genesis_mac_init(hw
, port
);
2361 yukon_reset(hw
, port
);
2362 yukon_init(hw
, port
);
2364 spin_unlock_bh(&hw
->phy_lock
);
2366 dev
->set_multicast_list(dev
);
2369 /* Basic MII support */
2370 static int skge_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2372 struct mii_ioctl_data
*data
= if_mii(ifr
);
2373 struct skge_port
*skge
= netdev_priv(dev
);
2374 struct skge_hw
*hw
= skge
->hw
;
2375 int err
= -EOPNOTSUPP
;
2377 if (!netif_running(dev
))
2378 return -ENODEV
; /* Phy still in reset */
2382 data
->phy_id
= hw
->phy_addr
;
2387 spin_lock_bh(&hw
->phy_lock
);
2388 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2389 err
= __xm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2391 err
= __gm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2392 spin_unlock_bh(&hw
->phy_lock
);
2393 data
->val_out
= val
;
2398 if (!capable(CAP_NET_ADMIN
))
2401 spin_lock_bh(&hw
->phy_lock
);
2402 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2403 err
= xm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2406 err
= gm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2408 spin_unlock_bh(&hw
->phy_lock
);
2414 /* Assign Ram Buffer allocation to queue */
2415 static void skge_ramset(struct skge_hw
*hw
, u16 q
, u32 start
, u32 space
)
2419 /* convert from K bytes to qwords used for hw register */
2422 end
= start
+ space
- 1;
2424 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
2425 skge_write32(hw
, RB_ADDR(q
, RB_START
), start
);
2426 skge_write32(hw
, RB_ADDR(q
, RB_END
), end
);
2427 skge_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
2428 skge_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
2430 if (q
== Q_R1
|| q
== Q_R2
) {
2431 u32 tp
= space
- space
/4;
2433 /* Set thresholds on receive queue's */
2434 skge_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
2435 skge_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
2436 } else if (hw
->chip_id
!= CHIP_ID_GENESIS
)
2437 /* Genesis Tx Fifo is too small for normal store/forward */
2438 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
2440 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
2443 /* Setup Bus Memory Interface */
2444 static void skge_qset(struct skge_port
*skge
, u16 q
,
2445 const struct skge_element
*e
)
2447 struct skge_hw
*hw
= skge
->hw
;
2448 u32 watermark
= 0x600;
2449 u64 base
= skge
->dma
+ (e
->desc
- skge
->mem
);
2451 /* optimization to reduce window on 32bit/33mhz */
2452 if ((skge_read16(hw
, B0_CTST
) & (CS_BUS_CLOCK
| CS_BUS_SLOT_SZ
)) == 0)
2455 skge_write32(hw
, Q_ADDR(q
, Q_CSR
), CSR_CLR_RESET
);
2456 skge_write32(hw
, Q_ADDR(q
, Q_F
), watermark
);
2457 skge_write32(hw
, Q_ADDR(q
, Q_DA_H
), (u32
)(base
>> 32));
2458 skge_write32(hw
, Q_ADDR(q
, Q_DA_L
), (u32
)base
);
2461 static int skge_up(struct net_device
*dev
)
2463 struct skge_port
*skge
= netdev_priv(dev
);
2464 struct skge_hw
*hw
= skge
->hw
;
2465 int port
= skge
->port
;
2466 u32 ramaddr
, ramsize
, rxspace
;
2467 size_t rx_size
, tx_size
;
2470 if (!is_valid_ether_addr(dev
->dev_addr
))
2473 if (netif_msg_ifup(skge
))
2474 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
2476 if (dev
->mtu
> RX_BUF_SIZE
)
2477 skge
->rx_buf_size
= dev
->mtu
+ ETH_HLEN
;
2479 skge
->rx_buf_size
= RX_BUF_SIZE
;
2482 rx_size
= skge
->rx_ring
.count
* sizeof(struct skge_rx_desc
);
2483 tx_size
= skge
->tx_ring
.count
* sizeof(struct skge_tx_desc
);
2484 skge
->mem_size
= tx_size
+ rx_size
;
2485 skge
->mem
= pci_alloc_consistent(hw
->pdev
, skge
->mem_size
, &skge
->dma
);
2489 BUG_ON(skge
->dma
& 7);
2491 if ((u64
)skge
->dma
>> 32 != ((u64
) skge
->dma
+ skge
->mem_size
) >> 32) {
2492 dev_err(&hw
->pdev
->dev
, "pci_alloc_consistent region crosses 4G boundary\n");
2497 memset(skge
->mem
, 0, skge
->mem_size
);
2499 err
= skge_ring_alloc(&skge
->rx_ring
, skge
->mem
, skge
->dma
);
2503 err
= skge_rx_fill(dev
);
2507 err
= skge_ring_alloc(&skge
->tx_ring
, skge
->mem
+ rx_size
,
2508 skge
->dma
+ rx_size
);
2512 /* Initialize MAC */
2513 spin_lock_bh(&hw
->phy_lock
);
2514 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2515 genesis_mac_init(hw
, port
);
2517 yukon_mac_init(hw
, port
);
2518 spin_unlock_bh(&hw
->phy_lock
);
2520 /* Configure RAMbuffers */
2521 ramsize
= (hw
->ram_size
- hw
->ram_offset
) / hw
->ports
;
2522 ramaddr
= hw
->ram_offset
+ port
* ramsize
;
2523 rxspace
= 8 + (2*(ramsize
- 16))/3;
2525 skge_ramset(hw
, rxqaddr
[port
], ramaddr
, rxspace
);
2526 skge_ramset(hw
, txqaddr
[port
], ramaddr
+ rxspace
, ramsize
- rxspace
);
2528 skge_qset(skge
, rxqaddr
[port
], skge
->rx_ring
.to_clean
);
2529 BUG_ON(skge
->tx_ring
.to_use
!= skge
->tx_ring
.to_clean
);
2530 skge_qset(skge
, txqaddr
[port
], skge
->tx_ring
.to_use
);
2532 /* Start receiver BMU */
2534 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_START
| CSR_IRQ_CL_F
);
2535 skge_led(skge
, LED_MODE_ON
);
2537 spin_lock_irq(&hw
->hw_lock
);
2538 hw
->intr_mask
|= portmask
[port
];
2539 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2540 spin_unlock_irq(&hw
->hw_lock
);
2542 napi_enable(&skge
->napi
);
2546 skge_rx_clean(skge
);
2547 kfree(skge
->rx_ring
.start
);
2549 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2556 static void skge_rx_stop(struct skge_hw
*hw
, int port
)
2558 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_STOP
);
2559 skge_write32(hw
, RB_ADDR(port
? Q_R2
: Q_R1
, RB_CTRL
),
2560 RB_RST_SET
|RB_DIS_OP_MD
);
2561 skge_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2564 static int skge_down(struct net_device
*dev
)
2566 struct skge_port
*skge
= netdev_priv(dev
);
2567 struct skge_hw
*hw
= skge
->hw
;
2568 int port
= skge
->port
;
2570 if (skge
->mem
== NULL
)
2573 if (netif_msg_ifdown(skge
))
2574 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
2576 netif_stop_queue(dev
);
2578 if (hw
->chip_id
== CHIP_ID_GENESIS
&& hw
->phy_type
== SK_PHY_XMAC
)
2579 del_timer_sync(&skge
->link_timer
);
2581 napi_disable(&skge
->napi
);
2582 netif_carrier_off(dev
);
2584 spin_lock_irq(&hw
->hw_lock
);
2585 hw
->intr_mask
&= ~portmask
[port
];
2586 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2587 spin_unlock_irq(&hw
->hw_lock
);
2589 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
2590 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2595 /* Stop transmitter */
2596 skge_write8(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_STOP
);
2597 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
2598 RB_RST_SET
|RB_DIS_OP_MD
);
2601 /* Disable Force Sync bit and Enable Alloc bit */
2602 skge_write8(hw
, SK_REG(port
, TXA_CTRL
),
2603 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
2605 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2606 skge_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
2607 skge_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
2609 /* Reset PCI FIFO */
2610 skge_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2611 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
2613 /* Reset the RAM Buffer async Tx queue */
2614 skge_write8(hw
, RB_ADDR(port
== 0 ? Q_XA1
: Q_XA2
, RB_CTRL
), RB_RST_SET
);
2616 skge_rx_stop(hw
, port
);
2618 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2619 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_SET
);
2620 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_SET
);
2622 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
2623 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
2626 skge_led(skge
, LED_MODE_OFF
);
2628 netif_tx_lock_bh(dev
);
2630 netif_tx_unlock_bh(dev
);
2632 skge_rx_clean(skge
);
2634 kfree(skge
->rx_ring
.start
);
2635 kfree(skge
->tx_ring
.start
);
2636 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2641 static inline int skge_avail(const struct skge_ring
*ring
)
2644 return ((ring
->to_clean
> ring
->to_use
) ? 0 : ring
->count
)
2645 + (ring
->to_clean
- ring
->to_use
) - 1;
2648 static int skge_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
2650 struct skge_port
*skge
= netdev_priv(dev
);
2651 struct skge_hw
*hw
= skge
->hw
;
2652 struct skge_element
*e
;
2653 struct skge_tx_desc
*td
;
2658 if (skb_padto(skb
, ETH_ZLEN
))
2659 return NETDEV_TX_OK
;
2661 if (unlikely(skge_avail(&skge
->tx_ring
) < skb_shinfo(skb
)->nr_frags
+ 1))
2662 return NETDEV_TX_BUSY
;
2664 e
= skge
->tx_ring
.to_use
;
2666 BUG_ON(td
->control
& BMU_OWN
);
2668 len
= skb_headlen(skb
);
2669 map
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2670 pci_unmap_addr_set(e
, mapaddr
, map
);
2671 pci_unmap_len_set(e
, maplen
, len
);
2674 td
->dma_hi
= map
>> 32;
2676 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2677 const int offset
= skb_transport_offset(skb
);
2679 /* This seems backwards, but it is what the sk98lin
2680 * does. Looks like hardware is wrong?
2682 if (ipip_hdr(skb
)->protocol
== IPPROTO_UDP
2683 && hw
->chip_rev
== 0 && hw
->chip_id
== CHIP_ID_YUKON
)
2684 control
= BMU_TCP_CHECK
;
2686 control
= BMU_UDP_CHECK
;
2689 td
->csum_start
= offset
;
2690 td
->csum_write
= offset
+ skb
->csum_offset
;
2692 control
= BMU_CHECK
;
2694 if (!skb_shinfo(skb
)->nr_frags
) /* single buffer i.e. no fragments */
2695 control
|= BMU_EOF
| BMU_IRQ_EOF
;
2697 struct skge_tx_desc
*tf
= td
;
2699 control
|= BMU_STFWD
;
2700 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2701 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2703 map
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
2704 frag
->size
, PCI_DMA_TODEVICE
);
2709 BUG_ON(tf
->control
& BMU_OWN
);
2712 tf
->dma_hi
= (u64
) map
>> 32;
2713 pci_unmap_addr_set(e
, mapaddr
, map
);
2714 pci_unmap_len_set(e
, maplen
, frag
->size
);
2716 tf
->control
= BMU_OWN
| BMU_SW
| control
| frag
->size
;
2718 tf
->control
|= BMU_EOF
| BMU_IRQ_EOF
;
2720 /* Make sure all the descriptors written */
2722 td
->control
= BMU_OWN
| BMU_SW
| BMU_STF
| control
| len
;
2725 skge_write8(hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_START
);
2727 if (unlikely(netif_msg_tx_queued(skge
)))
2728 printk(KERN_DEBUG
"%s: tx queued, slot %td, len %d\n",
2729 dev
->name
, e
- skge
->tx_ring
.start
, skb
->len
);
2731 skge
->tx_ring
.to_use
= e
->next
;
2734 if (skge_avail(&skge
->tx_ring
) <= TX_LOW_WATER
) {
2735 pr_debug("%s: transmit queue full\n", dev
->name
);
2736 netif_stop_queue(dev
);
2739 dev
->trans_start
= jiffies
;
2741 return NETDEV_TX_OK
;
2745 /* Free resources associated with this reing element */
2746 static void skge_tx_free(struct skge_port
*skge
, struct skge_element
*e
,
2749 struct pci_dev
*pdev
= skge
->hw
->pdev
;
2751 /* skb header vs. fragment */
2752 if (control
& BMU_STF
)
2753 pci_unmap_single(pdev
, pci_unmap_addr(e
, mapaddr
),
2754 pci_unmap_len(e
, maplen
),
2757 pci_unmap_page(pdev
, pci_unmap_addr(e
, mapaddr
),
2758 pci_unmap_len(e
, maplen
),
2761 if (control
& BMU_EOF
) {
2762 if (unlikely(netif_msg_tx_done(skge
)))
2763 printk(KERN_DEBUG PFX
"%s: tx done slot %td\n",
2764 skge
->netdev
->name
, e
- skge
->tx_ring
.start
);
2766 dev_kfree_skb(e
->skb
);
2770 /* Free all buffers in transmit ring */
2771 static void skge_tx_clean(struct net_device
*dev
)
2773 struct skge_port
*skge
= netdev_priv(dev
);
2774 struct skge_element
*e
;
2776 for (e
= skge
->tx_ring
.to_clean
; e
!= skge
->tx_ring
.to_use
; e
= e
->next
) {
2777 struct skge_tx_desc
*td
= e
->desc
;
2778 skge_tx_free(skge
, e
, td
->control
);
2782 skge
->tx_ring
.to_clean
= e
;
2783 netif_wake_queue(dev
);
2786 static void skge_tx_timeout(struct net_device
*dev
)
2788 struct skge_port
*skge
= netdev_priv(dev
);
2790 if (netif_msg_timer(skge
))
2791 printk(KERN_DEBUG PFX
"%s: tx timeout\n", dev
->name
);
2793 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_STOP
);
2797 static int skge_change_mtu(struct net_device
*dev
, int new_mtu
)
2799 struct skge_port
*skge
= netdev_priv(dev
);
2800 struct skge_hw
*hw
= skge
->hw
;
2801 int port
= skge
->port
;
2805 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2808 if (!netif_running(dev
)) {
2813 skge_write32(hw
, B0_IMSK
, 0);
2814 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2815 netif_stop_queue(dev
);
2816 napi_disable(&skge
->napi
);
2818 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2819 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2821 skge_rx_clean(skge
);
2822 skge_rx_stop(hw
, port
);
2826 reg
= GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2828 reg
|= GM_SMOD_JUMBO_ENA
;
2829 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
2831 skge_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2833 err
= skge_rx_fill(dev
);
2836 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_START
| CSR_IRQ_CL_F
);
2837 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2842 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2844 napi_enable(&skge
->napi
);
2845 netif_wake_queue(dev
);
2851 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2853 static void genesis_add_filter(u8 filter
[8], const u8
*addr
)
2857 crc
= ether_crc_le(ETH_ALEN
, addr
);
2859 filter
[bit
/8] |= 1 << (bit
%8);
2862 static void genesis_set_multicast(struct net_device
*dev
)
2864 struct skge_port
*skge
= netdev_priv(dev
);
2865 struct skge_hw
*hw
= skge
->hw
;
2866 int port
= skge
->port
;
2867 int i
, count
= dev
->mc_count
;
2868 struct dev_mc_list
*list
= dev
->mc_list
;
2872 mode
= xm_read32(hw
, port
, XM_MODE
);
2873 mode
|= XM_MD_ENA_HASH
;
2874 if (dev
->flags
& IFF_PROMISC
)
2875 mode
|= XM_MD_ENA_PROM
;
2877 mode
&= ~XM_MD_ENA_PROM
;
2879 if (dev
->flags
& IFF_ALLMULTI
)
2880 memset(filter
, 0xff, sizeof(filter
));
2882 memset(filter
, 0, sizeof(filter
));
2884 if (skge
->flow_status
== FLOW_STAT_REM_SEND
2885 || skge
->flow_status
== FLOW_STAT_SYMMETRIC
)
2886 genesis_add_filter(filter
, pause_mc_addr
);
2888 for (i
= 0; list
&& i
< count
; i
++, list
= list
->next
)
2889 genesis_add_filter(filter
, list
->dmi_addr
);
2892 xm_write32(hw
, port
, XM_MODE
, mode
);
2893 xm_outhash(hw
, port
, XM_HSM
, filter
);
2896 static void yukon_add_filter(u8 filter
[8], const u8
*addr
)
2898 u32 bit
= ether_crc(ETH_ALEN
, addr
) & 0x3f;
2899 filter
[bit
/8] |= 1 << (bit
%8);
2902 static void yukon_set_multicast(struct net_device
*dev
)
2904 struct skge_port
*skge
= netdev_priv(dev
);
2905 struct skge_hw
*hw
= skge
->hw
;
2906 int port
= skge
->port
;
2907 struct dev_mc_list
*list
= dev
->mc_list
;
2908 int rx_pause
= (skge
->flow_status
== FLOW_STAT_REM_SEND
2909 || skge
->flow_status
== FLOW_STAT_SYMMETRIC
);
2913 memset(filter
, 0, sizeof(filter
));
2915 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2916 reg
|= GM_RXCR_UCF_ENA
;
2918 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2919 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2920 else if (dev
->flags
& IFF_ALLMULTI
) /* all multicast */
2921 memset(filter
, 0xff, sizeof(filter
));
2922 else if (dev
->mc_count
== 0 && !rx_pause
)/* no multicast */
2923 reg
&= ~GM_RXCR_MCF_ENA
;
2926 reg
|= GM_RXCR_MCF_ENA
;
2929 yukon_add_filter(filter
, pause_mc_addr
);
2931 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
2932 yukon_add_filter(filter
, list
->dmi_addr
);
2936 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2937 (u16
)filter
[0] | ((u16
)filter
[1] << 8));
2938 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2939 (u16
)filter
[2] | ((u16
)filter
[3] << 8));
2940 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2941 (u16
)filter
[4] | ((u16
)filter
[5] << 8));
2942 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2943 (u16
)filter
[6] | ((u16
)filter
[7] << 8));
2945 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2948 static inline u16
phy_length(const struct skge_hw
*hw
, u32 status
)
2950 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2951 return status
>> XMR_FS_LEN_SHIFT
;
2953 return status
>> GMR_FS_LEN_SHIFT
;
2956 static inline int bad_phy_status(const struct skge_hw
*hw
, u32 status
)
2958 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2959 return (status
& (XMR_FS_ERR
| XMR_FS_2L_VLAN
)) != 0;
2961 return (status
& GMR_FS_ANY_ERR
) ||
2962 (status
& GMR_FS_RX_OK
) == 0;
2966 /* Get receive buffer from descriptor.
2967 * Handles copy of small buffers and reallocation failures
2969 static struct sk_buff
*skge_rx_get(struct net_device
*dev
,
2970 struct skge_element
*e
,
2971 u32 control
, u32 status
, u16 csum
)
2973 struct skge_port
*skge
= netdev_priv(dev
);
2974 struct sk_buff
*skb
;
2975 u16 len
= control
& BMU_BBC
;
2977 if (unlikely(netif_msg_rx_status(skge
)))
2978 printk(KERN_DEBUG PFX
"%s: rx slot %td status 0x%x len %d\n",
2979 dev
->name
, e
- skge
->rx_ring
.start
,
2982 if (len
> skge
->rx_buf_size
)
2985 if ((control
& (BMU_EOF
|BMU_STF
)) != (BMU_STF
|BMU_EOF
))
2988 if (bad_phy_status(skge
->hw
, status
))
2991 if (phy_length(skge
->hw
, status
) != len
)
2994 if (len
< RX_COPY_THRESHOLD
) {
2995 skb
= netdev_alloc_skb(dev
, len
+ 2);
2999 skb_reserve(skb
, 2);
3000 pci_dma_sync_single_for_cpu(skge
->hw
->pdev
,
3001 pci_unmap_addr(e
, mapaddr
),
3002 len
, PCI_DMA_FROMDEVICE
);
3003 skb_copy_from_linear_data(e
->skb
, skb
->data
, len
);
3004 pci_dma_sync_single_for_device(skge
->hw
->pdev
,
3005 pci_unmap_addr(e
, mapaddr
),
3006 len
, PCI_DMA_FROMDEVICE
);
3007 skge_rx_reuse(e
, skge
->rx_buf_size
);
3009 struct sk_buff
*nskb
;
3010 nskb
= netdev_alloc_skb(dev
, skge
->rx_buf_size
+ NET_IP_ALIGN
);
3014 skb_reserve(nskb
, NET_IP_ALIGN
);
3015 pci_unmap_single(skge
->hw
->pdev
,
3016 pci_unmap_addr(e
, mapaddr
),
3017 pci_unmap_len(e
, maplen
),
3018 PCI_DMA_FROMDEVICE
);
3020 prefetch(skb
->data
);
3021 skge_rx_setup(skge
, e
, nskb
, skge
->rx_buf_size
);
3025 if (skge
->rx_csum
) {
3027 skb
->ip_summed
= CHECKSUM_COMPLETE
;
3030 skb
->protocol
= eth_type_trans(skb
, dev
);
3035 if (netif_msg_rx_err(skge
))
3036 printk(KERN_DEBUG PFX
"%s: rx err, slot %td control 0x%x status 0x%x\n",
3037 dev
->name
, e
- skge
->rx_ring
.start
,
3040 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
) {
3041 if (status
& (XMR_FS_RUNT
|XMR_FS_LNG_ERR
))
3042 skge
->net_stats
.rx_length_errors
++;
3043 if (status
& XMR_FS_FRA_ERR
)
3044 skge
->net_stats
.rx_frame_errors
++;
3045 if (status
& XMR_FS_FCS_ERR
)
3046 skge
->net_stats
.rx_crc_errors
++;
3048 if (status
& (GMR_FS_LONG_ERR
|GMR_FS_UN_SIZE
))
3049 skge
->net_stats
.rx_length_errors
++;
3050 if (status
& GMR_FS_FRAGMENT
)
3051 skge
->net_stats
.rx_frame_errors
++;
3052 if (status
& GMR_FS_CRC_ERR
)
3053 skge
->net_stats
.rx_crc_errors
++;
3057 skge_rx_reuse(e
, skge
->rx_buf_size
);
3061 /* Free all buffers in Tx ring which are no longer owned by device */
3062 static void skge_tx_done(struct net_device
*dev
)
3064 struct skge_port
*skge
= netdev_priv(dev
);
3065 struct skge_ring
*ring
= &skge
->tx_ring
;
3066 struct skge_element
*e
;
3068 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
3070 for (e
= ring
->to_clean
; e
!= ring
->to_use
; e
= e
->next
) {
3071 u32 control
= ((const struct skge_tx_desc
*) e
->desc
)->control
;
3073 if (control
& BMU_OWN
)
3076 skge_tx_free(skge
, e
, control
);
3078 skge
->tx_ring
.to_clean
= e
;
3080 /* Can run lockless until we need to synchronize to restart queue. */
3083 if (unlikely(netif_queue_stopped(dev
) &&
3084 skge_avail(&skge
->tx_ring
) > TX_LOW_WATER
)) {
3086 if (unlikely(netif_queue_stopped(dev
) &&
3087 skge_avail(&skge
->tx_ring
) > TX_LOW_WATER
)) {
3088 netif_wake_queue(dev
);
3091 netif_tx_unlock(dev
);
3095 static int skge_poll(struct napi_struct
*napi
, int to_do
)
3097 struct skge_port
*skge
= container_of(napi
, struct skge_port
, napi
);
3098 struct net_device
*dev
= skge
->netdev
;
3099 struct skge_hw
*hw
= skge
->hw
;
3100 struct skge_ring
*ring
= &skge
->rx_ring
;
3101 struct skge_element
*e
;
3106 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
3108 for (e
= ring
->to_clean
; prefetch(e
->next
), work_done
< to_do
; e
= e
->next
) {
3109 struct skge_rx_desc
*rd
= e
->desc
;
3110 struct sk_buff
*skb
;
3114 control
= rd
->control
;
3115 if (control
& BMU_OWN
)
3118 skb
= skge_rx_get(dev
, e
, control
, rd
->status
, rd
->csum2
);
3120 dev
->last_rx
= jiffies
;
3121 netif_receive_skb(skb
);
3128 /* restart receiver */
3130 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_START
);
3132 if (work_done
< to_do
) {
3133 spin_lock_irq(&hw
->hw_lock
);
3134 __netif_rx_complete(dev
, napi
);
3135 hw
->intr_mask
|= napimask
[skge
->port
];
3136 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3137 skge_read32(hw
, B0_IMSK
);
3138 spin_unlock_irq(&hw
->hw_lock
);
3144 /* Parity errors seem to happen when Genesis is connected to a switch
3145 * with no other ports present. Heartbeat error??
3147 static void skge_mac_parity(struct skge_hw
*hw
, int port
)
3149 struct net_device
*dev
= hw
->dev
[port
];
3152 struct skge_port
*skge
= netdev_priv(dev
);
3153 ++skge
->net_stats
.tx_heartbeat_errors
;
3156 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3157 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
3160 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3161 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
3162 (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)
3163 ? GMF_CLI_TX_FC
: GMF_CLI_TX_PE
);
3166 static void skge_mac_intr(struct skge_hw
*hw
, int port
)
3168 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3169 genesis_mac_intr(hw
, port
);
3171 yukon_mac_intr(hw
, port
);
3174 /* Handle device specific framing and timeout interrupts */
3175 static void skge_error_irq(struct skge_hw
*hw
)
3177 struct pci_dev
*pdev
= hw
->pdev
;
3178 u32 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
3180 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
3181 /* clear xmac errors */
3182 if (hwstatus
& (IS_NO_STAT_M1
|IS_NO_TIST_M1
))
3183 skge_write16(hw
, RX_MFF_CTRL1
, MFF_CLR_INSTAT
);
3184 if (hwstatus
& (IS_NO_STAT_M2
|IS_NO_TIST_M2
))
3185 skge_write16(hw
, RX_MFF_CTRL2
, MFF_CLR_INSTAT
);
3187 /* Timestamp (unused) overflow */
3188 if (hwstatus
& IS_IRQ_TIST_OV
)
3189 skge_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3192 if (hwstatus
& IS_RAM_RD_PAR
) {
3193 dev_err(&pdev
->dev
, "Ram read data parity error\n");
3194 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_RD_PERR
);
3197 if (hwstatus
& IS_RAM_WR_PAR
) {
3198 dev_err(&pdev
->dev
, "Ram write data parity error\n");
3199 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_WR_PERR
);
3202 if (hwstatus
& IS_M1_PAR_ERR
)
3203 skge_mac_parity(hw
, 0);
3205 if (hwstatus
& IS_M2_PAR_ERR
)
3206 skge_mac_parity(hw
, 1);
3208 if (hwstatus
& IS_R1_PAR_ERR
) {
3209 dev_err(&pdev
->dev
, "%s: receive queue parity error\n",
3211 skge_write32(hw
, B0_R1_CSR
, CSR_IRQ_CL_P
);
3214 if (hwstatus
& IS_R2_PAR_ERR
) {
3215 dev_err(&pdev
->dev
, "%s: receive queue parity error\n",
3217 skge_write32(hw
, B0_R2_CSR
, CSR_IRQ_CL_P
);
3220 if (hwstatus
& (IS_IRQ_MST_ERR
|IS_IRQ_STAT
)) {
3221 u16 pci_status
, pci_cmd
;
3223 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
3224 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
3226 dev_err(&pdev
->dev
, "PCI error cmd=%#x status=%#x\n",
3227 pci_cmd
, pci_status
);
3229 /* Write the error bits back to clear them. */
3230 pci_status
&= PCI_STATUS_ERROR_BITS
;
3231 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3232 pci_write_config_word(pdev
, PCI_COMMAND
,
3233 pci_cmd
| PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
);
3234 pci_write_config_word(pdev
, PCI_STATUS
, pci_status
);
3235 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3237 /* if error still set then just ignore it */
3238 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
3239 if (hwstatus
& IS_IRQ_STAT
) {
3240 dev_warn(&hw
->pdev
->dev
, "unable to clear error (so ignoring them)\n");
3241 hw
->intr_mask
&= ~IS_HW_ERR
;
3247 * Interrupt from PHY are handled in tasklet (softirq)
3248 * because accessing phy registers requires spin wait which might
3249 * cause excess interrupt latency.
3251 static void skge_extirq(unsigned long arg
)
3253 struct skge_hw
*hw
= (struct skge_hw
*) arg
;
3256 for (port
= 0; port
< hw
->ports
; port
++) {
3257 struct net_device
*dev
= hw
->dev
[port
];
3259 if (netif_running(dev
)) {
3260 struct skge_port
*skge
= netdev_priv(dev
);
3262 spin_lock(&hw
->phy_lock
);
3263 if (hw
->chip_id
!= CHIP_ID_GENESIS
)
3264 yukon_phy_intr(skge
);
3265 else if (hw
->phy_type
== SK_PHY_BCOM
)
3266 bcom_phy_intr(skge
);
3267 spin_unlock(&hw
->phy_lock
);
3271 spin_lock_irq(&hw
->hw_lock
);
3272 hw
->intr_mask
|= IS_EXT_REG
;
3273 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3274 skge_read32(hw
, B0_IMSK
);
3275 spin_unlock_irq(&hw
->hw_lock
);
3278 static irqreturn_t
skge_intr(int irq
, void *dev_id
)
3280 struct skge_hw
*hw
= dev_id
;
3284 spin_lock(&hw
->hw_lock
);
3285 /* Reading this register masks IRQ */
3286 status
= skge_read32(hw
, B0_SP_ISRC
);
3287 if (status
== 0 || status
== ~0)
3291 status
&= hw
->intr_mask
;
3292 if (status
& IS_EXT_REG
) {
3293 hw
->intr_mask
&= ~IS_EXT_REG
;
3294 tasklet_schedule(&hw
->phy_task
);
3297 if (status
& (IS_XA1_F
|IS_R1_F
)) {
3298 struct skge_port
*skge
= netdev_priv(hw
->dev
[0]);
3299 hw
->intr_mask
&= ~(IS_XA1_F
|IS_R1_F
);
3300 netif_rx_schedule(hw
->dev
[0], &skge
->napi
);
3303 if (status
& IS_PA_TO_TX1
)
3304 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX1
);
3306 if (status
& IS_PA_TO_RX1
) {
3307 struct skge_port
*skge
= netdev_priv(hw
->dev
[0]);
3309 ++skge
->net_stats
.rx_over_errors
;
3310 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX1
);
3314 if (status
& IS_MAC1
)
3315 skge_mac_intr(hw
, 0);
3318 struct skge_port
*skge
= netdev_priv(hw
->dev
[1]);
3320 if (status
& (IS_XA2_F
|IS_R2_F
)) {
3321 hw
->intr_mask
&= ~(IS_XA2_F
|IS_R2_F
);
3322 netif_rx_schedule(hw
->dev
[1], &skge
->napi
);
3325 if (status
& IS_PA_TO_RX2
) {
3326 ++skge
->net_stats
.rx_over_errors
;
3327 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX2
);
3330 if (status
& IS_PA_TO_TX2
)
3331 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX2
);
3333 if (status
& IS_MAC2
)
3334 skge_mac_intr(hw
, 1);
3337 if (status
& IS_HW_ERR
)
3340 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3341 skge_read32(hw
, B0_IMSK
);
3343 spin_unlock(&hw
->hw_lock
);
3345 return IRQ_RETVAL(handled
);
3348 #ifdef CONFIG_NET_POLL_CONTROLLER
3349 static void skge_netpoll(struct net_device
*dev
)
3351 struct skge_port
*skge
= netdev_priv(dev
);
3353 disable_irq(dev
->irq
);
3354 skge_intr(dev
->irq
, skge
->hw
);
3355 enable_irq(dev
->irq
);
3359 static int skge_set_mac_address(struct net_device
*dev
, void *p
)
3361 struct skge_port
*skge
= netdev_priv(dev
);
3362 struct skge_hw
*hw
= skge
->hw
;
3363 unsigned port
= skge
->port
;
3364 const struct sockaddr
*addr
= p
;
3367 if (!is_valid_ether_addr(addr
->sa_data
))
3368 return -EADDRNOTAVAIL
;
3370 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3372 if (!netif_running(dev
)) {
3373 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3374 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3377 spin_lock_bh(&hw
->phy_lock
);
3378 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
3379 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
& ~GM_GPCR_RX_ENA
);
3381 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3382 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
*8, dev
->dev_addr
, ETH_ALEN
);
3384 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3385 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
3387 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3388 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3391 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
3392 spin_unlock_bh(&hw
->phy_lock
);
3398 static const struct {
3402 { CHIP_ID_GENESIS
, "Genesis" },
3403 { CHIP_ID_YUKON
, "Yukon" },
3404 { CHIP_ID_YUKON_LITE
, "Yukon-Lite"},
3405 { CHIP_ID_YUKON_LP
, "Yukon-LP"},
3408 static const char *skge_board_name(const struct skge_hw
*hw
)
3411 static char buf
[16];
3413 for (i
= 0; i
< ARRAY_SIZE(skge_chips
); i
++)
3414 if (skge_chips
[i
].id
== hw
->chip_id
)
3415 return skge_chips
[i
].name
;
3417 snprintf(buf
, sizeof buf
, "chipid 0x%x", hw
->chip_id
);
3423 * Setup the board data structure, but don't bring up
3426 static int skge_reset(struct skge_hw
*hw
)
3429 u16 ctst
, pci_status
;
3430 u8 t8
, mac_cfg
, pmd_type
;
3433 ctst
= skge_read16(hw
, B0_CTST
);
3436 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3437 skge_write8(hw
, B0_CTST
, CS_RST_CLR
);
3439 /* clear PCI errors, if any */
3440 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3441 skge_write8(hw
, B2_TST_CTRL2
, 0);
3443 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &pci_status
);
3444 pci_write_config_word(hw
->pdev
, PCI_STATUS
,
3445 pci_status
| PCI_STATUS_ERROR_BITS
);
3446 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3447 skge_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3449 /* restore CLK_RUN bits (for Yukon-Lite) */
3450 skge_write16(hw
, B0_CTST
,
3451 ctst
& (CS_CLK_RUN_HOT
|CS_CLK_RUN_RST
|CS_CLK_RUN_ENA
));
3453 hw
->chip_id
= skge_read8(hw
, B2_CHIP_ID
);
3454 hw
->phy_type
= skge_read8(hw
, B2_E_1
) & 0xf;
3455 pmd_type
= skge_read8(hw
, B2_PMD_TYP
);
3456 hw
->copper
= (pmd_type
== 'T' || pmd_type
== '1');
3458 switch (hw
->chip_id
) {
3459 case CHIP_ID_GENESIS
:
3460 switch (hw
->phy_type
) {
3462 hw
->phy_addr
= PHY_ADDR_XMAC
;
3465 hw
->phy_addr
= PHY_ADDR_BCOM
;
3468 dev_err(&hw
->pdev
->dev
, "unsupported phy type 0x%x\n",
3475 case CHIP_ID_YUKON_LITE
:
3476 case CHIP_ID_YUKON_LP
:
3477 if (hw
->phy_type
< SK_PHY_MARV_COPPER
&& pmd_type
!= 'S')
3480 hw
->phy_addr
= PHY_ADDR_MARV
;
3484 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
3489 mac_cfg
= skge_read8(hw
, B2_MAC_CFG
);
3490 hw
->ports
= (mac_cfg
& CFG_SNG_MAC
) ? 1 : 2;
3491 hw
->chip_rev
= (mac_cfg
& CFG_CHIP_R_MSK
) >> 4;
3493 /* read the adapters RAM size */
3494 t8
= skge_read8(hw
, B2_E_0
);
3495 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
3497 /* special case: 4 x 64k x 36, offset = 0x80000 */
3498 hw
->ram_size
= 1024;
3499 hw
->ram_offset
= 512;
3501 hw
->ram_size
= t8
* 512;
3503 hw
->ram_size
= t8
? t8
* 4 : 128;
3505 hw
->intr_mask
= IS_HW_ERR
;
3507 /* Use PHY IRQ for all but fiber based Genesis board */
3508 if (!(hw
->chip_id
== CHIP_ID_GENESIS
&& hw
->phy_type
== SK_PHY_XMAC
))
3509 hw
->intr_mask
|= IS_EXT_REG
;
3511 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3514 /* switch power to VCC (WA for VAUX problem) */
3515 skge_write8(hw
, B0_POWER_CTRL
,
3516 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
3518 /* avoid boards with stuck Hardware error bits */
3519 if ((skge_read32(hw
, B0_ISRC
) & IS_HW_ERR
) &&
3520 (skge_read32(hw
, B0_HWE_ISRC
) & IS_IRQ_SENSOR
)) {
3521 dev_warn(&hw
->pdev
->dev
, "stuck hardware sensor bit\n");
3522 hw
->intr_mask
&= ~IS_HW_ERR
;
3525 /* Clear PHY COMA */
3526 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3527 pci_read_config_dword(hw
->pdev
, PCI_DEV_REG1
, ®
);
3528 reg
&= ~PCI_PHY_COMA
;
3529 pci_write_config_dword(hw
->pdev
, PCI_DEV_REG1
, reg
);
3530 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3533 for (i
= 0; i
< hw
->ports
; i
++) {
3534 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3535 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3539 /* turn off hardware timer (unused) */
3540 skge_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3541 skge_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3542 skge_write8(hw
, B0_LED
, LED_STAT_ON
);
3544 /* enable the Tx Arbiters */
3545 for (i
= 0; i
< hw
->ports
; i
++)
3546 skge_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3548 /* Initialize ram interface */
3549 skge_write16(hw
, B3_RI_CTRL
, RI_RST_CLR
);
3551 skge_write8(hw
, B3_RI_WTO_R1
, SK_RI_TO_53
);
3552 skge_write8(hw
, B3_RI_WTO_XA1
, SK_RI_TO_53
);
3553 skge_write8(hw
, B3_RI_WTO_XS1
, SK_RI_TO_53
);
3554 skge_write8(hw
, B3_RI_RTO_R1
, SK_RI_TO_53
);
3555 skge_write8(hw
, B3_RI_RTO_XA1
, SK_RI_TO_53
);
3556 skge_write8(hw
, B3_RI_RTO_XS1
, SK_RI_TO_53
);
3557 skge_write8(hw
, B3_RI_WTO_R2
, SK_RI_TO_53
);
3558 skge_write8(hw
, B3_RI_WTO_XA2
, SK_RI_TO_53
);
3559 skge_write8(hw
, B3_RI_WTO_XS2
, SK_RI_TO_53
);
3560 skge_write8(hw
, B3_RI_RTO_R2
, SK_RI_TO_53
);
3561 skge_write8(hw
, B3_RI_RTO_XA2
, SK_RI_TO_53
);
3562 skge_write8(hw
, B3_RI_RTO_XS2
, SK_RI_TO_53
);
3564 skge_write32(hw
, B0_HWE_IMSK
, IS_ERR_MSK
);
3566 /* Set interrupt moderation for Transmit only
3567 * Receive interrupts avoided by NAPI
3569 skge_write32(hw
, B2_IRQM_MSK
, IS_XA1_F
|IS_XA2_F
);
3570 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, 100));
3571 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
3573 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3575 for (i
= 0; i
< hw
->ports
; i
++) {
3576 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3577 genesis_reset(hw
, i
);
3585 /* Initialize network device */
3586 static struct net_device
*skge_devinit(struct skge_hw
*hw
, int port
,
3589 struct skge_port
*skge
;
3590 struct net_device
*dev
= alloc_etherdev(sizeof(*skge
));
3593 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
3597 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3598 dev
->open
= skge_up
;
3599 dev
->stop
= skge_down
;
3600 dev
->do_ioctl
= skge_ioctl
;
3601 dev
->hard_start_xmit
= skge_xmit_frame
;
3602 dev
->get_stats
= skge_get_stats
;
3603 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3604 dev
->set_multicast_list
= genesis_set_multicast
;
3606 dev
->set_multicast_list
= yukon_set_multicast
;
3608 dev
->set_mac_address
= skge_set_mac_address
;
3609 dev
->change_mtu
= skge_change_mtu
;
3610 SET_ETHTOOL_OPS(dev
, &skge_ethtool_ops
);
3611 dev
->tx_timeout
= skge_tx_timeout
;
3612 dev
->watchdog_timeo
= TX_WATCHDOG
;
3613 #ifdef CONFIG_NET_POLL_CONTROLLER
3614 dev
->poll_controller
= skge_netpoll
;
3616 dev
->irq
= hw
->pdev
->irq
;
3619 dev
->features
|= NETIF_F_HIGHDMA
;
3621 skge
= netdev_priv(dev
);
3622 netif_napi_add(dev
, &skge
->napi
, skge_poll
, NAPI_WEIGHT
);
3625 skge
->msg_enable
= netif_msg_init(debug
, default_msg
);
3627 skge
->tx_ring
.count
= DEFAULT_TX_RING_SIZE
;
3628 skge
->rx_ring
.count
= DEFAULT_RX_RING_SIZE
;
3630 /* Auto speed and flow control */
3631 skge
->autoneg
= AUTONEG_ENABLE
;
3632 skge
->flow_control
= FLOW_MODE_SYM_OR_REM
;
3635 skge
->advertising
= skge_supported_modes(hw
);
3637 if (pci_wake_enabled(hw
->pdev
))
3638 skge
->wol
= wol_supported(hw
) & WAKE_MAGIC
;
3640 hw
->dev
[port
] = dev
;
3644 /* Only used for Genesis XMAC */
3645 setup_timer(&skge
->link_timer
, xm_link_timer
, (unsigned long) skge
);
3647 if (hw
->chip_id
!= CHIP_ID_GENESIS
) {
3648 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3652 /* read the mac address */
3653 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
*8, ETH_ALEN
);
3654 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3656 /* device is off until link detection */
3657 netif_carrier_off(dev
);
3658 netif_stop_queue(dev
);
3663 static void __devinit
skge_show_addr(struct net_device
*dev
)
3665 const struct skge_port
*skge
= netdev_priv(dev
);
3666 DECLARE_MAC_BUF(mac
);
3668 if (netif_msg_probe(skge
))
3669 printk(KERN_INFO PFX
"%s: addr %s\n",
3670 dev
->name
, print_mac(mac
, dev
->dev_addr
));
3673 static int __devinit
skge_probe(struct pci_dev
*pdev
,
3674 const struct pci_device_id
*ent
)
3676 struct net_device
*dev
, *dev1
;
3678 int err
, using_dac
= 0;
3680 err
= pci_enable_device(pdev
);
3682 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3686 err
= pci_request_regions(pdev
, DRV_NAME
);
3688 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3689 goto err_out_disable_pdev
;
3692 pci_set_master(pdev
);
3694 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3696 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3697 } else if (!(err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
))) {
3699 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3703 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3704 goto err_out_free_regions
;
3708 /* byte swap descriptors in hardware */
3712 pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
3713 reg
|= PCI_REV_DESC
;
3714 pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
3719 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3721 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3722 goto err_out_free_regions
;
3726 spin_lock_init(&hw
->hw_lock
);
3727 spin_lock_init(&hw
->phy_lock
);
3728 tasklet_init(&hw
->phy_task
, &skge_extirq
, (unsigned long) hw
);
3730 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3732 dev_err(&pdev
->dev
, "cannot map device registers\n");
3733 goto err_out_free_hw
;
3736 err
= skge_reset(hw
);
3738 goto err_out_iounmap
;
3740 printk(KERN_INFO PFX DRV_VERSION
" addr 0x%llx irq %d chip %s rev %d\n",
3741 (unsigned long long)pci_resource_start(pdev
, 0), pdev
->irq
,
3742 skge_board_name(hw
), hw
->chip_rev
);
3744 dev
= skge_devinit(hw
, 0, using_dac
);
3746 goto err_out_led_off
;
3748 /* Some motherboards are broken and has zero in ROM. */
3749 if (!is_valid_ether_addr(dev
->dev_addr
))
3750 dev_warn(&pdev
->dev
, "bad (zero?) ethernet address in rom\n");
3752 err
= register_netdev(dev
);
3754 dev_err(&pdev
->dev
, "cannot register net device\n");
3755 goto err_out_free_netdev
;
3758 err
= request_irq(pdev
->irq
, skge_intr
, IRQF_SHARED
, dev
->name
, hw
);
3760 dev_err(&pdev
->dev
, "%s: cannot assign irq %d\n",
3761 dev
->name
, pdev
->irq
);
3762 goto err_out_unregister
;
3764 skge_show_addr(dev
);
3766 if (hw
->ports
> 1 && (dev1
= skge_devinit(hw
, 1, using_dac
))) {
3767 if (register_netdev(dev1
) == 0)
3768 skge_show_addr(dev1
);
3770 /* Failure to register second port need not be fatal */
3771 dev_warn(&pdev
->dev
, "register of second port failed\n");
3776 pci_set_drvdata(pdev
, hw
);
3781 unregister_netdev(dev
);
3782 err_out_free_netdev
:
3785 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3790 err_out_free_regions
:
3791 pci_release_regions(pdev
);
3792 err_out_disable_pdev
:
3793 pci_disable_device(pdev
);
3794 pci_set_drvdata(pdev
, NULL
);
3799 static void __devexit
skge_remove(struct pci_dev
*pdev
)
3801 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3802 struct net_device
*dev0
, *dev1
;
3807 flush_scheduled_work();
3809 if ((dev1
= hw
->dev
[1]))
3810 unregister_netdev(dev1
);
3812 unregister_netdev(dev0
);
3814 tasklet_disable(&hw
->phy_task
);
3816 spin_lock_irq(&hw
->hw_lock
);
3818 skge_write32(hw
, B0_IMSK
, 0);
3819 skge_read32(hw
, B0_IMSK
);
3820 spin_unlock_irq(&hw
->hw_lock
);
3822 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3823 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3825 free_irq(pdev
->irq
, hw
);
3826 pci_release_regions(pdev
);
3827 pci_disable_device(pdev
);
3834 pci_set_drvdata(pdev
, NULL
);
3838 static int skge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3840 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3841 int i
, err
, wol
= 0;
3846 err
= pci_save_state(pdev
);
3850 for (i
= 0; i
< hw
->ports
; i
++) {
3851 struct net_device
*dev
= hw
->dev
[i
];
3852 struct skge_port
*skge
= netdev_priv(dev
);
3854 if (netif_running(dev
))
3857 skge_wol_init(skge
);
3862 skge_write32(hw
, B0_IMSK
, 0);
3863 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3864 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3869 static int skge_resume(struct pci_dev
*pdev
)
3871 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3877 err
= pci_set_power_state(pdev
, PCI_D0
);
3881 err
= pci_restore_state(pdev
);
3885 pci_enable_wake(pdev
, PCI_D0
, 0);
3887 err
= skge_reset(hw
);
3891 for (i
= 0; i
< hw
->ports
; i
++) {
3892 struct net_device
*dev
= hw
->dev
[i
];
3894 if (netif_running(dev
)) {
3898 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3910 static void skge_shutdown(struct pci_dev
*pdev
)
3912 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3918 for (i
= 0; i
< hw
->ports
; i
++) {
3919 struct net_device
*dev
= hw
->dev
[i
];
3920 struct skge_port
*skge
= netdev_priv(dev
);
3923 skge_wol_init(skge
);
3927 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
3928 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
3930 pci_disable_device(pdev
);
3931 pci_set_power_state(pdev
, PCI_D3hot
);
3935 static struct pci_driver skge_driver
= {
3937 .id_table
= skge_id_table
,
3938 .probe
= skge_probe
,
3939 .remove
= __devexit_p(skge_remove
),
3941 .suspend
= skge_suspend
,
3942 .resume
= skge_resume
,
3944 .shutdown
= skge_shutdown
,
3947 static int __init
skge_init_module(void)
3949 return pci_register_driver(&skge_driver
);
3952 static void __exit
skge_cleanup_module(void)
3954 pci_unregister_driver(&skge_driver
);
3957 module_init(skge_init_module
);
3958 module_exit(skge_cleanup_module
);