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Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-mmc
[mirror_ubuntu-bionic-kernel.git] / drivers / net / skge.c
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/in.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/mii.h>
41 #include <asm/irq.h>
42
43 #include "skge.h"
44
45 #define DRV_NAME "skge"
46 #define DRV_VERSION "1.6"
47 #define PFX DRV_NAME " "
48
49 #define DEFAULT_TX_RING_SIZE 128
50 #define DEFAULT_RX_RING_SIZE 512
51 #define MAX_TX_RING_SIZE 1024
52 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
60 #define BLINK_MS 250
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
87 { 0 }
88 };
89 MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91 static int skge_up(struct net_device *dev);
92 static int skge_down(struct net_device *dev);
93 static void skge_phy_reset(struct skge_port *skge);
94 static void skge_tx_clean(struct skge_port *skge);
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static void genesis_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
102
103 /* Avoid conditionals by using array */
104 static const int txqaddr[] = { Q_XA1, Q_XA2 };
105 static const int rxqaddr[] = { Q_R1, Q_R2 };
106 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108
109 static int skge_get_regs_len(struct net_device *dev)
110 {
111 return 0x4000;
112 }
113
114 /*
115 * Returns copy of whole control register region
116 * Note: skip RAM address register because accessing it will
117 * cause bus hangs!
118 */
119 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121 {
122 const struct skge_port *skge = netdev_priv(dev);
123 const void __iomem *io = skge->hw->regs;
124
125 regs->version = 1;
126 memset(p, 0, regs->len);
127 memcpy_fromio(p, io, B3_RAM_ADDR);
128
129 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
130 regs->len - B3_RI_WTO_R1);
131 }
132
133 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
134 static int wol_supported(const struct skge_hw *hw)
135 {
136 return !((hw->chip_id == CHIP_ID_GENESIS ||
137 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
138 }
139
140 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
141 {
142 struct skge_port *skge = netdev_priv(dev);
143
144 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
145 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
146 }
147
148 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
149 {
150 struct skge_port *skge = netdev_priv(dev);
151 struct skge_hw *hw = skge->hw;
152
153 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
154 return -EOPNOTSUPP;
155
156 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
157 return -EOPNOTSUPP;
158
159 skge->wol = wol->wolopts == WAKE_MAGIC;
160
161 if (skge->wol) {
162 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
163
164 skge_write16(hw, WOL_CTRL_STAT,
165 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
166 WOL_CTL_ENA_MAGIC_PKT_UNIT);
167 } else
168 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
169
170 return 0;
171 }
172
173 /* Determine supported/advertised modes based on hardware.
174 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
175 */
176 static u32 skge_supported_modes(const struct skge_hw *hw)
177 {
178 u32 supported;
179
180 if (hw->copper) {
181 supported = SUPPORTED_10baseT_Half
182 | SUPPORTED_10baseT_Full
183 | SUPPORTED_100baseT_Half
184 | SUPPORTED_100baseT_Full
185 | SUPPORTED_1000baseT_Half
186 | SUPPORTED_1000baseT_Full
187 | SUPPORTED_Autoneg| SUPPORTED_TP;
188
189 if (hw->chip_id == CHIP_ID_GENESIS)
190 supported &= ~(SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full);
194
195 else if (hw->chip_id == CHIP_ID_YUKON)
196 supported &= ~SUPPORTED_1000baseT_Half;
197 } else
198 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
199 | SUPPORTED_Autoneg;
200
201 return supported;
202 }
203
204 static int skge_get_settings(struct net_device *dev,
205 struct ethtool_cmd *ecmd)
206 {
207 struct skge_port *skge = netdev_priv(dev);
208 struct skge_hw *hw = skge->hw;
209
210 ecmd->transceiver = XCVR_INTERNAL;
211 ecmd->supported = skge_supported_modes(hw);
212
213 if (hw->copper) {
214 ecmd->port = PORT_TP;
215 ecmd->phy_address = hw->phy_addr;
216 } else
217 ecmd->port = PORT_FIBRE;
218
219 ecmd->advertising = skge->advertising;
220 ecmd->autoneg = skge->autoneg;
221 ecmd->speed = skge->speed;
222 ecmd->duplex = skge->duplex;
223 return 0;
224 }
225
226 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227 {
228 struct skge_port *skge = netdev_priv(dev);
229 const struct skge_hw *hw = skge->hw;
230 u32 supported = skge_supported_modes(hw);
231
232 if (ecmd->autoneg == AUTONEG_ENABLE) {
233 ecmd->advertising = supported;
234 skge->duplex = -1;
235 skge->speed = -1;
236 } else {
237 u32 setting;
238
239 switch (ecmd->speed) {
240 case SPEED_1000:
241 if (ecmd->duplex == DUPLEX_FULL)
242 setting = SUPPORTED_1000baseT_Full;
243 else if (ecmd->duplex == DUPLEX_HALF)
244 setting = SUPPORTED_1000baseT_Half;
245 else
246 return -EINVAL;
247 break;
248 case SPEED_100:
249 if (ecmd->duplex == DUPLEX_FULL)
250 setting = SUPPORTED_100baseT_Full;
251 else if (ecmd->duplex == DUPLEX_HALF)
252 setting = SUPPORTED_100baseT_Half;
253 else
254 return -EINVAL;
255 break;
256
257 case SPEED_10:
258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_10baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_10baseT_Half;
262 else
263 return -EINVAL;
264 break;
265 default:
266 return -EINVAL;
267 }
268
269 if ((setting & supported) == 0)
270 return -EINVAL;
271
272 skge->speed = ecmd->speed;
273 skge->duplex = ecmd->duplex;
274 }
275
276 skge->autoneg = ecmd->autoneg;
277 skge->advertising = ecmd->advertising;
278
279 if (netif_running(dev))
280 skge_phy_reset(skge);
281
282 return (0);
283 }
284
285 static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
287 {
288 struct skge_port *skge = netdev_priv(dev);
289
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
294 }
295
296 static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
298 u16 xmac_offset;
299 u16 gma_offset;
300 } skge_stats[] = {
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
325 };
326
327 static int skge_get_stats_count(struct net_device *dev)
328 {
329 return ARRAY_SIZE(skge_stats);
330 }
331
332 static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
334 {
335 struct skge_port *skge = netdev_priv(dev);
336
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
339 else
340 yukon_get_stats(skge, data);
341 }
342
343 /* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
346 */
347 static struct net_device_stats *skge_get_stats(struct net_device *dev)
348 {
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
351
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
354 else
355 yukon_get_stats(skge, data);
356
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[3] + data[5];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
364
365 return &skge->net_stats;
366 }
367
368 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
369 {
370 int i;
371
372 switch (stringset) {
373 case ETH_SS_STATS:
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
377 break;
378 }
379 }
380
381 static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
383 {
384 struct skge_port *skge = netdev_priv(dev);
385
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
390
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
395 }
396
397 static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
399 {
400 struct skge_port *skge = netdev_priv(dev);
401 int err;
402
403 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
404 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
405 return -EINVAL;
406
407 skge->rx_ring.count = p->rx_pending;
408 skge->tx_ring.count = p->tx_pending;
409
410 if (netif_running(dev)) {
411 skge_down(dev);
412 err = skge_up(dev);
413 if (err)
414 dev_close(dev);
415 }
416
417 return 0;
418 }
419
420 static u32 skge_get_msglevel(struct net_device *netdev)
421 {
422 struct skge_port *skge = netdev_priv(netdev);
423 return skge->msg_enable;
424 }
425
426 static void skge_set_msglevel(struct net_device *netdev, u32 value)
427 {
428 struct skge_port *skge = netdev_priv(netdev);
429 skge->msg_enable = value;
430 }
431
432 static int skge_nway_reset(struct net_device *dev)
433 {
434 struct skge_port *skge = netdev_priv(dev);
435
436 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
437 return -EINVAL;
438
439 skge_phy_reset(skge);
440 return 0;
441 }
442
443 static int skge_set_sg(struct net_device *dev, u32 data)
444 {
445 struct skge_port *skge = netdev_priv(dev);
446 struct skge_hw *hw = skge->hw;
447
448 if (hw->chip_id == CHIP_ID_GENESIS && data)
449 return -EOPNOTSUPP;
450 return ethtool_op_set_sg(dev, data);
451 }
452
453 static int skge_set_tx_csum(struct net_device *dev, u32 data)
454 {
455 struct skge_port *skge = netdev_priv(dev);
456 struct skge_hw *hw = skge->hw;
457
458 if (hw->chip_id == CHIP_ID_GENESIS && data)
459 return -EOPNOTSUPP;
460
461 return ethtool_op_set_tx_csum(dev, data);
462 }
463
464 static u32 skge_get_rx_csum(struct net_device *dev)
465 {
466 struct skge_port *skge = netdev_priv(dev);
467
468 return skge->rx_csum;
469 }
470
471 /* Only Yukon supports checksum offload. */
472 static int skge_set_rx_csum(struct net_device *dev, u32 data)
473 {
474 struct skge_port *skge = netdev_priv(dev);
475
476 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
477 return -EOPNOTSUPP;
478
479 skge->rx_csum = data;
480 return 0;
481 }
482
483 static void skge_get_pauseparam(struct net_device *dev,
484 struct ethtool_pauseparam *ecmd)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487
488 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
489 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
490 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492
493 ecmd->autoneg = skge->autoneg;
494 }
495
496 static int skge_set_pauseparam(struct net_device *dev,
497 struct ethtool_pauseparam *ecmd)
498 {
499 struct skge_port *skge = netdev_priv(dev);
500
501 skge->autoneg = ecmd->autoneg;
502 if (ecmd->rx_pause && ecmd->tx_pause)
503 skge->flow_control = FLOW_MODE_SYMMETRIC;
504 else if (ecmd->rx_pause && !ecmd->tx_pause)
505 skge->flow_control = FLOW_MODE_REM_SEND;
506 else if (!ecmd->rx_pause && ecmd->tx_pause)
507 skge->flow_control = FLOW_MODE_LOC_SEND;
508 else
509 skge->flow_control = FLOW_MODE_NONE;
510
511 if (netif_running(dev))
512 skge_phy_reset(skge);
513 return 0;
514 }
515
516 /* Chip internal frequency for clock calculations */
517 static inline u32 hwkhz(const struct skge_hw *hw)
518 {
519 if (hw->chip_id == CHIP_ID_GENESIS)
520 return 53215; /* or: 53.125 MHz */
521 else
522 return 78215; /* or: 78.125 MHz */
523 }
524
525 /* Chip HZ to microseconds */
526 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
527 {
528 return (ticks * 1000) / hwkhz(hw);
529 }
530
531 /* Microseconds to chip HZ */
532 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
533 {
534 return hwkhz(hw) * usec / 1000;
535 }
536
537 static int skge_get_coalesce(struct net_device *dev,
538 struct ethtool_coalesce *ecmd)
539 {
540 struct skge_port *skge = netdev_priv(dev);
541 struct skge_hw *hw = skge->hw;
542 int port = skge->port;
543
544 ecmd->rx_coalesce_usecs = 0;
545 ecmd->tx_coalesce_usecs = 0;
546
547 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
548 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
549 u32 msk = skge_read32(hw, B2_IRQM_MSK);
550
551 if (msk & rxirqmask[port])
552 ecmd->rx_coalesce_usecs = delay;
553 if (msk & txirqmask[port])
554 ecmd->tx_coalesce_usecs = delay;
555 }
556
557 return 0;
558 }
559
560 /* Note: interrupt timer is per board, but can turn on/off per port */
561 static int skge_set_coalesce(struct net_device *dev,
562 struct ethtool_coalesce *ecmd)
563 {
564 struct skge_port *skge = netdev_priv(dev);
565 struct skge_hw *hw = skge->hw;
566 int port = skge->port;
567 u32 msk = skge_read32(hw, B2_IRQM_MSK);
568 u32 delay = 25;
569
570 if (ecmd->rx_coalesce_usecs == 0)
571 msk &= ~rxirqmask[port];
572 else if (ecmd->rx_coalesce_usecs < 25 ||
573 ecmd->rx_coalesce_usecs > 33333)
574 return -EINVAL;
575 else {
576 msk |= rxirqmask[port];
577 delay = ecmd->rx_coalesce_usecs;
578 }
579
580 if (ecmd->tx_coalesce_usecs == 0)
581 msk &= ~txirqmask[port];
582 else if (ecmd->tx_coalesce_usecs < 25 ||
583 ecmd->tx_coalesce_usecs > 33333)
584 return -EINVAL;
585 else {
586 msk |= txirqmask[port];
587 delay = min(delay, ecmd->rx_coalesce_usecs);
588 }
589
590 skge_write32(hw, B2_IRQM_MSK, msk);
591 if (msk == 0)
592 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
593 else {
594 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
595 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
596 }
597 return 0;
598 }
599
600 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
601 static void skge_led(struct skge_port *skge, enum led_mode mode)
602 {
603 struct skge_hw *hw = skge->hw;
604 int port = skge->port;
605
606 mutex_lock(&hw->phy_mutex);
607 if (hw->chip_id == CHIP_ID_GENESIS) {
608 switch (mode) {
609 case LED_MODE_OFF:
610 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
611 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
612 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
613 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
614 break;
615
616 case LED_MODE_ON:
617 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
618 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
619
620 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
621 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
622
623 break;
624
625 case LED_MODE_TST:
626 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
627 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
628 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
629
630 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
631 break;
632 }
633 } else {
634 switch (mode) {
635 case LED_MODE_OFF:
636 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
637 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
638 PHY_M_LED_MO_DUP(MO_LED_OFF) |
639 PHY_M_LED_MO_10(MO_LED_OFF) |
640 PHY_M_LED_MO_100(MO_LED_OFF) |
641 PHY_M_LED_MO_1000(MO_LED_OFF) |
642 PHY_M_LED_MO_RX(MO_LED_OFF));
643 break;
644 case LED_MODE_ON:
645 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
646 PHY_M_LED_PULS_DUR(PULS_170MS) |
647 PHY_M_LED_BLINK_RT(BLINK_84MS) |
648 PHY_M_LEDC_TX_CTRL |
649 PHY_M_LEDC_DP_CTRL);
650
651 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
652 PHY_M_LED_MO_RX(MO_LED_OFF) |
653 (skge->speed == SPEED_100 ?
654 PHY_M_LED_MO_100(MO_LED_ON) : 0));
655 break;
656 case LED_MODE_TST:
657 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
658 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
659 PHY_M_LED_MO_DUP(MO_LED_ON) |
660 PHY_M_LED_MO_10(MO_LED_ON) |
661 PHY_M_LED_MO_100(MO_LED_ON) |
662 PHY_M_LED_MO_1000(MO_LED_ON) |
663 PHY_M_LED_MO_RX(MO_LED_ON));
664 }
665 }
666 mutex_unlock(&hw->phy_mutex);
667 }
668
669 /* blink LED's for finding board */
670 static int skge_phys_id(struct net_device *dev, u32 data)
671 {
672 struct skge_port *skge = netdev_priv(dev);
673 unsigned long ms;
674 enum led_mode mode = LED_MODE_TST;
675
676 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
677 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
678 else
679 ms = data * 1000;
680
681 while (ms > 0) {
682 skge_led(skge, mode);
683 mode ^= LED_MODE_TST;
684
685 if (msleep_interruptible(BLINK_MS))
686 break;
687 ms -= BLINK_MS;
688 }
689
690 /* back to regular LED state */
691 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
692
693 return 0;
694 }
695
696 static struct ethtool_ops skge_ethtool_ops = {
697 .get_settings = skge_get_settings,
698 .set_settings = skge_set_settings,
699 .get_drvinfo = skge_get_drvinfo,
700 .get_regs_len = skge_get_regs_len,
701 .get_regs = skge_get_regs,
702 .get_wol = skge_get_wol,
703 .set_wol = skge_set_wol,
704 .get_msglevel = skge_get_msglevel,
705 .set_msglevel = skge_set_msglevel,
706 .nway_reset = skge_nway_reset,
707 .get_link = ethtool_op_get_link,
708 .get_ringparam = skge_get_ring_param,
709 .set_ringparam = skge_set_ring_param,
710 .get_pauseparam = skge_get_pauseparam,
711 .set_pauseparam = skge_set_pauseparam,
712 .get_coalesce = skge_get_coalesce,
713 .set_coalesce = skge_set_coalesce,
714 .get_sg = ethtool_op_get_sg,
715 .set_sg = skge_set_sg,
716 .get_tx_csum = ethtool_op_get_tx_csum,
717 .set_tx_csum = skge_set_tx_csum,
718 .get_rx_csum = skge_get_rx_csum,
719 .set_rx_csum = skge_set_rx_csum,
720 .get_strings = skge_get_strings,
721 .phys_id = skge_phys_id,
722 .get_stats_count = skge_get_stats_count,
723 .get_ethtool_stats = skge_get_ethtool_stats,
724 .get_perm_addr = ethtool_op_get_perm_addr,
725 };
726
727 /*
728 * Allocate ring elements and chain them together
729 * One-to-one association of board descriptors with ring elements
730 */
731 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
732 {
733 struct skge_tx_desc *d;
734 struct skge_element *e;
735 int i;
736
737 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
738 if (!ring->start)
739 return -ENOMEM;
740
741 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
742 e->desc = d;
743 if (i == ring->count - 1) {
744 e->next = ring->start;
745 d->next_offset = base;
746 } else {
747 e->next = e + 1;
748 d->next_offset = base + (i+1) * sizeof(*d);
749 }
750 }
751 ring->to_use = ring->to_clean = ring->start;
752
753 return 0;
754 }
755
756 /* Allocate and setup a new buffer for receiving */
757 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
758 struct sk_buff *skb, unsigned int bufsize)
759 {
760 struct skge_rx_desc *rd = e->desc;
761 u64 map;
762
763 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
764 PCI_DMA_FROMDEVICE);
765
766 rd->dma_lo = map;
767 rd->dma_hi = map >> 32;
768 e->skb = skb;
769 rd->csum1_start = ETH_HLEN;
770 rd->csum2_start = ETH_HLEN;
771 rd->csum1 = 0;
772 rd->csum2 = 0;
773
774 wmb();
775
776 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
777 pci_unmap_addr_set(e, mapaddr, map);
778 pci_unmap_len_set(e, maplen, bufsize);
779 }
780
781 /* Resume receiving using existing skb,
782 * Note: DMA address is not changed by chip.
783 * MTU not changed while receiver active.
784 */
785 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
786 {
787 struct skge_rx_desc *rd = e->desc;
788
789 rd->csum2 = 0;
790 rd->csum2_start = ETH_HLEN;
791
792 wmb();
793
794 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
795 }
796
797
798 /* Free all buffers in receive ring, assumes receiver stopped */
799 static void skge_rx_clean(struct skge_port *skge)
800 {
801 struct skge_hw *hw = skge->hw;
802 struct skge_ring *ring = &skge->rx_ring;
803 struct skge_element *e;
804
805 e = ring->start;
806 do {
807 struct skge_rx_desc *rd = e->desc;
808 rd->control = 0;
809 if (e->skb) {
810 pci_unmap_single(hw->pdev,
811 pci_unmap_addr(e, mapaddr),
812 pci_unmap_len(e, maplen),
813 PCI_DMA_FROMDEVICE);
814 dev_kfree_skb(e->skb);
815 e->skb = NULL;
816 }
817 } while ((e = e->next) != ring->start);
818 }
819
820
821 /* Allocate buffers for receive ring
822 * For receive: to_clean is next received frame.
823 */
824 static int skge_rx_fill(struct skge_port *skge)
825 {
826 struct skge_ring *ring = &skge->rx_ring;
827 struct skge_element *e;
828
829 e = ring->start;
830 do {
831 struct sk_buff *skb;
832
833 skb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_KERNEL);
834 if (!skb)
835 return -ENOMEM;
836
837 skb_reserve(skb, NET_IP_ALIGN);
838 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
839 } while ( (e = e->next) != ring->start);
840
841 ring->to_clean = ring->start;
842 return 0;
843 }
844
845 static void skge_link_up(struct skge_port *skge)
846 {
847 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
848 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
849
850 netif_carrier_on(skge->netdev);
851 netif_wake_queue(skge->netdev);
852
853 if (netif_msg_link(skge))
854 printk(KERN_INFO PFX
855 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
856 skge->netdev->name, skge->speed,
857 skge->duplex == DUPLEX_FULL ? "full" : "half",
858 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
859 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
860 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
861 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
862 "unknown");
863 }
864
865 static void skge_link_down(struct skge_port *skge)
866 {
867 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
868 netif_carrier_off(skge->netdev);
869 netif_stop_queue(skge->netdev);
870
871 if (netif_msg_link(skge))
872 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
873 }
874
875 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
876 {
877 int i;
878
879 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
880 *val = xm_read16(hw, port, XM_PHY_DATA);
881
882 for (i = 0; i < PHY_RETRIES; i++) {
883 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
884 goto ready;
885 udelay(1);
886 }
887
888 return -ETIMEDOUT;
889 ready:
890 *val = xm_read16(hw, port, XM_PHY_DATA);
891
892 return 0;
893 }
894
895 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
896 {
897 u16 v = 0;
898 if (__xm_phy_read(hw, port, reg, &v))
899 printk(KERN_WARNING PFX "%s: phy read timed out\n",
900 hw->dev[port]->name);
901 return v;
902 }
903
904 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
905 {
906 int i;
907
908 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
909 for (i = 0; i < PHY_RETRIES; i++) {
910 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
911 goto ready;
912 udelay(1);
913 }
914 return -EIO;
915
916 ready:
917 xm_write16(hw, port, XM_PHY_DATA, val);
918 for (i = 0; i < PHY_RETRIES; i++) {
919 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
920 return 0;
921 udelay(1);
922 }
923 return -ETIMEDOUT;
924 }
925
926 static void genesis_init(struct skge_hw *hw)
927 {
928 /* set blink source counter */
929 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
930 skge_write8(hw, B2_BSC_CTRL, BSC_START);
931
932 /* configure mac arbiter */
933 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
934
935 /* configure mac arbiter timeout values */
936 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
937 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
939 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
940
941 skge_write8(hw, B3_MA_RCINI_RX1, 0);
942 skge_write8(hw, B3_MA_RCINI_RX2, 0);
943 skge_write8(hw, B3_MA_RCINI_TX1, 0);
944 skge_write8(hw, B3_MA_RCINI_TX2, 0);
945
946 /* configure packet arbiter timeout */
947 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
948 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
949 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
950 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
951 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
952 }
953
954 static void genesis_reset(struct skge_hw *hw, int port)
955 {
956 const u8 zero[8] = { 0 };
957
958 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
959
960 /* reset the statistics module */
961 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
962 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
963 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
964 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
965 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
966
967 /* disable Broadcom PHY IRQ */
968 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
969
970 xm_outhash(hw, port, XM_HSM, zero);
971 }
972
973
974 /* Convert mode to MII values */
975 static const u16 phy_pause_map[] = {
976 [FLOW_MODE_NONE] = 0,
977 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
978 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
979 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
980 };
981
982
983 /* Check status of Broadcom phy link */
984 static void bcom_check_link(struct skge_hw *hw, int port)
985 {
986 struct net_device *dev = hw->dev[port];
987 struct skge_port *skge = netdev_priv(dev);
988 u16 status;
989
990 /* read twice because of latch */
991 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
992 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
993
994 if ((status & PHY_ST_LSYNC) == 0) {
995 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
996 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
997 xm_write16(hw, port, XM_MMU_CMD, cmd);
998 /* dummy read to ensure writing */
999 (void) xm_read16(hw, port, XM_MMU_CMD);
1000
1001 if (netif_carrier_ok(dev))
1002 skge_link_down(skge);
1003 } else {
1004 if (skge->autoneg == AUTONEG_ENABLE &&
1005 (status & PHY_ST_AN_OVER)) {
1006 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1007 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1008
1009 if (lpa & PHY_B_AN_RF) {
1010 printk(KERN_NOTICE PFX "%s: remote fault\n",
1011 dev->name);
1012 return;
1013 }
1014
1015 /* Check Duplex mismatch */
1016 switch (aux & PHY_B_AS_AN_RES_MSK) {
1017 case PHY_B_RES_1000FD:
1018 skge->duplex = DUPLEX_FULL;
1019 break;
1020 case PHY_B_RES_1000HD:
1021 skge->duplex = DUPLEX_HALF;
1022 break;
1023 default:
1024 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1025 dev->name);
1026 return;
1027 }
1028
1029
1030 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1031 switch (aux & PHY_B_AS_PAUSE_MSK) {
1032 case PHY_B_AS_PAUSE_MSK:
1033 skge->flow_control = FLOW_MODE_SYMMETRIC;
1034 break;
1035 case PHY_B_AS_PRR:
1036 skge->flow_control = FLOW_MODE_REM_SEND;
1037 break;
1038 case PHY_B_AS_PRT:
1039 skge->flow_control = FLOW_MODE_LOC_SEND;
1040 break;
1041 default:
1042 skge->flow_control = FLOW_MODE_NONE;
1043 }
1044
1045 skge->speed = SPEED_1000;
1046 }
1047
1048 if (!netif_carrier_ok(dev))
1049 genesis_link_up(skge);
1050 }
1051 }
1052
1053 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1054 * Phy on for 100 or 10Mbit operation
1055 */
1056 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1057 {
1058 struct skge_hw *hw = skge->hw;
1059 int port = skge->port;
1060 int i;
1061 u16 id1, r, ext, ctl;
1062
1063 /* magic workaround patterns for Broadcom */
1064 static const struct {
1065 u16 reg;
1066 u16 val;
1067 } A1hack[] = {
1068 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1069 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1070 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1071 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1072 }, C0hack[] = {
1073 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1074 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1075 };
1076
1077 /* read Id from external PHY (all have the same address) */
1078 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1079
1080 /* Optimize MDIO transfer by suppressing preamble. */
1081 r = xm_read16(hw, port, XM_MMU_CMD);
1082 r |= XM_MMU_NO_PRE;
1083 xm_write16(hw, port, XM_MMU_CMD,r);
1084
1085 switch (id1) {
1086 case PHY_BCOM_ID1_C0:
1087 /*
1088 * Workaround BCOM Errata for the C0 type.
1089 * Write magic patterns to reserved registers.
1090 */
1091 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1092 xm_phy_write(hw, port,
1093 C0hack[i].reg, C0hack[i].val);
1094
1095 break;
1096 case PHY_BCOM_ID1_A1:
1097 /*
1098 * Workaround BCOM Errata for the A1 type.
1099 * Write magic patterns to reserved registers.
1100 */
1101 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1102 xm_phy_write(hw, port,
1103 A1hack[i].reg, A1hack[i].val);
1104 break;
1105 }
1106
1107 /*
1108 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1109 * Disable Power Management after reset.
1110 */
1111 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1112 r |= PHY_B_AC_DIS_PM;
1113 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1114
1115 /* Dummy read */
1116 xm_read16(hw, port, XM_ISRC);
1117
1118 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1119 ctl = PHY_CT_SP1000; /* always 1000mbit */
1120
1121 if (skge->autoneg == AUTONEG_ENABLE) {
1122 /*
1123 * Workaround BCOM Errata #1 for the C5 type.
1124 * 1000Base-T Link Acquisition Failure in Slave Mode
1125 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1126 */
1127 u16 adv = PHY_B_1000C_RD;
1128 if (skge->advertising & ADVERTISED_1000baseT_Half)
1129 adv |= PHY_B_1000C_AHD;
1130 if (skge->advertising & ADVERTISED_1000baseT_Full)
1131 adv |= PHY_B_1000C_AFD;
1132 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1133
1134 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1135 } else {
1136 if (skge->duplex == DUPLEX_FULL)
1137 ctl |= PHY_CT_DUP_MD;
1138 /* Force to slave */
1139 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1140 }
1141
1142 /* Set autonegotiation pause parameters */
1143 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1144 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1145
1146 /* Handle Jumbo frames */
1147 if (jumbo) {
1148 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1149 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1150
1151 ext |= PHY_B_PEC_HIGH_LA;
1152
1153 }
1154
1155 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1156 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1157
1158 /* Use link status change interrupt */
1159 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1160
1161 bcom_check_link(hw, port);
1162 }
1163
1164 static void genesis_mac_init(struct skge_hw *hw, int port)
1165 {
1166 struct net_device *dev = hw->dev[port];
1167 struct skge_port *skge = netdev_priv(dev);
1168 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1169 int i;
1170 u32 r;
1171 const u8 zero[6] = { 0 };
1172
1173 for (i = 0; i < 10; i++) {
1174 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1175 MFF_SET_MAC_RST);
1176 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1177 goto reset_ok;
1178 udelay(1);
1179 }
1180
1181 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1182
1183 reset_ok:
1184 /* Unreset the XMAC. */
1185 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1186
1187 /*
1188 * Perform additional initialization for external PHYs,
1189 * namely for the 1000baseTX cards that use the XMAC's
1190 * GMII mode.
1191 */
1192 /* Take external Phy out of reset */
1193 r = skge_read32(hw, B2_GP_IO);
1194 if (port == 0)
1195 r |= GP_DIR_0|GP_IO_0;
1196 else
1197 r |= GP_DIR_2|GP_IO_2;
1198
1199 skge_write32(hw, B2_GP_IO, r);
1200
1201
1202 /* Enable GMII interface */
1203 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1204
1205 bcom_phy_init(skge, jumbo);
1206
1207 /* Set Station Address */
1208 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1209
1210 /* We don't use match addresses so clear */
1211 for (i = 1; i < 16; i++)
1212 xm_outaddr(hw, port, XM_EXM(i), zero);
1213
1214 /* Clear MIB counters */
1215 xm_write16(hw, port, XM_STAT_CMD,
1216 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1217 /* Clear two times according to Errata #3 */
1218 xm_write16(hw, port, XM_STAT_CMD,
1219 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1220
1221 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1222 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1223
1224 /* We don't need the FCS appended to the packet. */
1225 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1226 if (jumbo)
1227 r |= XM_RX_BIG_PK_OK;
1228
1229 if (skge->duplex == DUPLEX_HALF) {
1230 /*
1231 * If in manual half duplex mode the other side might be in
1232 * full duplex mode, so ignore if a carrier extension is not seen
1233 * on frames received
1234 */
1235 r |= XM_RX_DIS_CEXT;
1236 }
1237 xm_write16(hw, port, XM_RX_CMD, r);
1238
1239
1240 /* We want short frames padded to 60 bytes. */
1241 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1242
1243 /*
1244 * Bump up the transmit threshold. This helps hold off transmit
1245 * underruns when we're blasting traffic from both ports at once.
1246 */
1247 xm_write16(hw, port, XM_TX_THR, 512);
1248
1249 /*
1250 * Enable the reception of all error frames. This is is
1251 * a necessary evil due to the design of the XMAC. The
1252 * XMAC's receive FIFO is only 8K in size, however jumbo
1253 * frames can be up to 9000 bytes in length. When bad
1254 * frame filtering is enabled, the XMAC's RX FIFO operates
1255 * in 'store and forward' mode. For this to work, the
1256 * entire frame has to fit into the FIFO, but that means
1257 * that jumbo frames larger than 8192 bytes will be
1258 * truncated. Disabling all bad frame filtering causes
1259 * the RX FIFO to operate in streaming mode, in which
1260 * case the XMAC will start transferring frames out of the
1261 * RX FIFO as soon as the FIFO threshold is reached.
1262 */
1263 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1264
1265
1266 /*
1267 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1268 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1269 * and 'Octets Rx OK Hi Cnt Ov'.
1270 */
1271 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1272
1273 /*
1274 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1275 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1276 * and 'Octets Tx OK Hi Cnt Ov'.
1277 */
1278 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1279
1280 /* Configure MAC arbiter */
1281 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1282
1283 /* configure timeout values */
1284 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1285 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1286 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1287 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1288
1289 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1290 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1291 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1292 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1293
1294 /* Configure Rx MAC FIFO */
1295 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1296 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1297 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1298
1299 /* Configure Tx MAC FIFO */
1300 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1301 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1302 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1303
1304 if (jumbo) {
1305 /* Enable frame flushing if jumbo frames used */
1306 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1307 } else {
1308 /* enable timeout timers if normal frames */
1309 skge_write16(hw, B3_PA_CTRL,
1310 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1311 }
1312 }
1313
1314 static void genesis_stop(struct skge_port *skge)
1315 {
1316 struct skge_hw *hw = skge->hw;
1317 int port = skge->port;
1318 u32 reg;
1319
1320 genesis_reset(hw, port);
1321
1322 /* Clear Tx packet arbiter timeout IRQ */
1323 skge_write16(hw, B3_PA_CTRL,
1324 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1325
1326 /*
1327 * If the transfer sticks at the MAC the STOP command will not
1328 * terminate if we don't flush the XMAC's transmit FIFO !
1329 */
1330 xm_write32(hw, port, XM_MODE,
1331 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1332
1333
1334 /* Reset the MAC */
1335 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1336
1337 /* For external PHYs there must be special handling */
1338 reg = skge_read32(hw, B2_GP_IO);
1339 if (port == 0) {
1340 reg |= GP_DIR_0;
1341 reg &= ~GP_IO_0;
1342 } else {
1343 reg |= GP_DIR_2;
1344 reg &= ~GP_IO_2;
1345 }
1346 skge_write32(hw, B2_GP_IO, reg);
1347 skge_read32(hw, B2_GP_IO);
1348
1349 xm_write16(hw, port, XM_MMU_CMD,
1350 xm_read16(hw, port, XM_MMU_CMD)
1351 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1352
1353 xm_read16(hw, port, XM_MMU_CMD);
1354 }
1355
1356
1357 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1358 {
1359 struct skge_hw *hw = skge->hw;
1360 int port = skge->port;
1361 int i;
1362 unsigned long timeout = jiffies + HZ;
1363
1364 xm_write16(hw, port,
1365 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1366
1367 /* wait for update to complete */
1368 while (xm_read16(hw, port, XM_STAT_CMD)
1369 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1370 if (time_after(jiffies, timeout))
1371 break;
1372 udelay(10);
1373 }
1374
1375 /* special case for 64 bit octet counter */
1376 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1377 | xm_read32(hw, port, XM_TXO_OK_LO);
1378 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1379 | xm_read32(hw, port, XM_RXO_OK_LO);
1380
1381 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1382 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1383 }
1384
1385 static void genesis_mac_intr(struct skge_hw *hw, int port)
1386 {
1387 struct skge_port *skge = netdev_priv(hw->dev[port]);
1388 u16 status = xm_read16(hw, port, XM_ISRC);
1389
1390 if (netif_msg_intr(skge))
1391 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1392 skge->netdev->name, status);
1393
1394 if (status & XM_IS_TXF_UR) {
1395 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1396 ++skge->net_stats.tx_fifo_errors;
1397 }
1398 if (status & XM_IS_RXF_OV) {
1399 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1400 ++skge->net_stats.rx_fifo_errors;
1401 }
1402 }
1403
1404 static void genesis_link_up(struct skge_port *skge)
1405 {
1406 struct skge_hw *hw = skge->hw;
1407 int port = skge->port;
1408 u16 cmd;
1409 u32 mode, msk;
1410
1411 cmd = xm_read16(hw, port, XM_MMU_CMD);
1412
1413 /*
1414 * enabling pause frame reception is required for 1000BT
1415 * because the XMAC is not reset if the link is going down
1416 */
1417 if (skge->flow_control == FLOW_MODE_NONE ||
1418 skge->flow_control == FLOW_MODE_LOC_SEND)
1419 /* Disable Pause Frame Reception */
1420 cmd |= XM_MMU_IGN_PF;
1421 else
1422 /* Enable Pause Frame Reception */
1423 cmd &= ~XM_MMU_IGN_PF;
1424
1425 xm_write16(hw, port, XM_MMU_CMD, cmd);
1426
1427 mode = xm_read32(hw, port, XM_MODE);
1428 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1429 skge->flow_control == FLOW_MODE_LOC_SEND) {
1430 /*
1431 * Configure Pause Frame Generation
1432 * Use internal and external Pause Frame Generation.
1433 * Sending pause frames is edge triggered.
1434 * Send a Pause frame with the maximum pause time if
1435 * internal oder external FIFO full condition occurs.
1436 * Send a zero pause time frame to re-start transmission.
1437 */
1438 /* XM_PAUSE_DA = '010000C28001' (default) */
1439 /* XM_MAC_PTIME = 0xffff (maximum) */
1440 /* remember this value is defined in big endian (!) */
1441 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1442
1443 mode |= XM_PAUSE_MODE;
1444 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1445 } else {
1446 /*
1447 * disable pause frame generation is required for 1000BT
1448 * because the XMAC is not reset if the link is going down
1449 */
1450 /* Disable Pause Mode in Mode Register */
1451 mode &= ~XM_PAUSE_MODE;
1452
1453 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1454 }
1455
1456 xm_write32(hw, port, XM_MODE, mode);
1457
1458 msk = XM_DEF_MSK;
1459 /* disable GP0 interrupt bit for external Phy */
1460 msk |= XM_IS_INP_ASS;
1461
1462 xm_write16(hw, port, XM_IMSK, msk);
1463 xm_read16(hw, port, XM_ISRC);
1464
1465 /* get MMU Command Reg. */
1466 cmd = xm_read16(hw, port, XM_MMU_CMD);
1467 if (skge->duplex == DUPLEX_FULL)
1468 cmd |= XM_MMU_GMII_FD;
1469
1470 /*
1471 * Workaround BCOM Errata (#10523) for all BCom Phys
1472 * Enable Power Management after link up
1473 */
1474 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1475 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1476 & ~PHY_B_AC_DIS_PM);
1477 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1478
1479 /* enable Rx/Tx */
1480 xm_write16(hw, port, XM_MMU_CMD,
1481 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1482 skge_link_up(skge);
1483 }
1484
1485
1486 static inline void bcom_phy_intr(struct skge_port *skge)
1487 {
1488 struct skge_hw *hw = skge->hw;
1489 int port = skge->port;
1490 u16 isrc;
1491
1492 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1493 if (netif_msg_intr(skge))
1494 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1495 skge->netdev->name, isrc);
1496
1497 if (isrc & PHY_B_IS_PSE)
1498 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1499 hw->dev[port]->name);
1500
1501 /* Workaround BCom Errata:
1502 * enable and disable loopback mode if "NO HCD" occurs.
1503 */
1504 if (isrc & PHY_B_IS_NO_HDCL) {
1505 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1506 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1507 ctrl | PHY_CT_LOOP);
1508 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1509 ctrl & ~PHY_CT_LOOP);
1510 }
1511
1512 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1513 bcom_check_link(hw, port);
1514
1515 }
1516
1517 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1518 {
1519 int i;
1520
1521 gma_write16(hw, port, GM_SMI_DATA, val);
1522 gma_write16(hw, port, GM_SMI_CTRL,
1523 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1524 for (i = 0; i < PHY_RETRIES; i++) {
1525 udelay(1);
1526
1527 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1528 return 0;
1529 }
1530
1531 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1532 hw->dev[port]->name);
1533 return -EIO;
1534 }
1535
1536 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1537 {
1538 int i;
1539
1540 gma_write16(hw, port, GM_SMI_CTRL,
1541 GM_SMI_CT_PHY_AD(hw->phy_addr)
1542 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1543
1544 for (i = 0; i < PHY_RETRIES; i++) {
1545 udelay(1);
1546 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1547 goto ready;
1548 }
1549
1550 return -ETIMEDOUT;
1551 ready:
1552 *val = gma_read16(hw, port, GM_SMI_DATA);
1553 return 0;
1554 }
1555
1556 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1557 {
1558 u16 v = 0;
1559 if (__gm_phy_read(hw, port, reg, &v))
1560 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1561 hw->dev[port]->name);
1562 return v;
1563 }
1564
1565 /* Marvell Phy Initialization */
1566 static void yukon_init(struct skge_hw *hw, int port)
1567 {
1568 struct skge_port *skge = netdev_priv(hw->dev[port]);
1569 u16 ctrl, ct1000, adv;
1570
1571 if (skge->autoneg == AUTONEG_ENABLE) {
1572 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1573
1574 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1575 PHY_M_EC_MAC_S_MSK);
1576 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1577
1578 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1579
1580 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1581 }
1582
1583 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1584 if (skge->autoneg == AUTONEG_DISABLE)
1585 ctrl &= ~PHY_CT_ANE;
1586
1587 ctrl |= PHY_CT_RESET;
1588 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1589
1590 ctrl = 0;
1591 ct1000 = 0;
1592 adv = PHY_AN_CSMA;
1593
1594 if (skge->autoneg == AUTONEG_ENABLE) {
1595 if (hw->copper) {
1596 if (skge->advertising & ADVERTISED_1000baseT_Full)
1597 ct1000 |= PHY_M_1000C_AFD;
1598 if (skge->advertising & ADVERTISED_1000baseT_Half)
1599 ct1000 |= PHY_M_1000C_AHD;
1600 if (skge->advertising & ADVERTISED_100baseT_Full)
1601 adv |= PHY_M_AN_100_FD;
1602 if (skge->advertising & ADVERTISED_100baseT_Half)
1603 adv |= PHY_M_AN_100_HD;
1604 if (skge->advertising & ADVERTISED_10baseT_Full)
1605 adv |= PHY_M_AN_10_FD;
1606 if (skge->advertising & ADVERTISED_10baseT_Half)
1607 adv |= PHY_M_AN_10_HD;
1608 } else /* special defines for FIBER (88E1011S only) */
1609 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1610
1611 /* Set Flow-control capabilities */
1612 adv |= phy_pause_map[skge->flow_control];
1613
1614 /* Restart Auto-negotiation */
1615 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1616 } else {
1617 /* forced speed/duplex settings */
1618 ct1000 = PHY_M_1000C_MSE;
1619
1620 if (skge->duplex == DUPLEX_FULL)
1621 ctrl |= PHY_CT_DUP_MD;
1622
1623 switch (skge->speed) {
1624 case SPEED_1000:
1625 ctrl |= PHY_CT_SP1000;
1626 break;
1627 case SPEED_100:
1628 ctrl |= PHY_CT_SP100;
1629 break;
1630 }
1631
1632 ctrl |= PHY_CT_RESET;
1633 }
1634
1635 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1636
1637 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1638 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1639
1640 /* Enable phy interrupt on autonegotiation complete (or link up) */
1641 if (skge->autoneg == AUTONEG_ENABLE)
1642 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1643 else
1644 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1645 }
1646
1647 static void yukon_reset(struct skge_hw *hw, int port)
1648 {
1649 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1650 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1651 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1652 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1653 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1654
1655 gma_write16(hw, port, GM_RX_CTRL,
1656 gma_read16(hw, port, GM_RX_CTRL)
1657 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1658 }
1659
1660 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1661 static int is_yukon_lite_a0(struct skge_hw *hw)
1662 {
1663 u32 reg;
1664 int ret;
1665
1666 if (hw->chip_id != CHIP_ID_YUKON)
1667 return 0;
1668
1669 reg = skge_read32(hw, B2_FAR);
1670 skge_write8(hw, B2_FAR + 3, 0xff);
1671 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1672 skge_write32(hw, B2_FAR, reg);
1673 return ret;
1674 }
1675
1676 static void yukon_mac_init(struct skge_hw *hw, int port)
1677 {
1678 struct skge_port *skge = netdev_priv(hw->dev[port]);
1679 int i;
1680 u32 reg;
1681 const u8 *addr = hw->dev[port]->dev_addr;
1682
1683 /* WA code for COMA mode -- set PHY reset */
1684 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1685 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1686 reg = skge_read32(hw, B2_GP_IO);
1687 reg |= GP_DIR_9 | GP_IO_9;
1688 skge_write32(hw, B2_GP_IO, reg);
1689 }
1690
1691 /* hard reset */
1692 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1693 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1694
1695 /* WA code for COMA mode -- clear PHY reset */
1696 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1697 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1698 reg = skge_read32(hw, B2_GP_IO);
1699 reg |= GP_DIR_9;
1700 reg &= ~GP_IO_9;
1701 skge_write32(hw, B2_GP_IO, reg);
1702 }
1703
1704 /* Set hardware config mode */
1705 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1706 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1707 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1708
1709 /* Clear GMC reset */
1710 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1711 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1712 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1713
1714 if (skge->autoneg == AUTONEG_DISABLE) {
1715 reg = GM_GPCR_AU_ALL_DIS;
1716 gma_write16(hw, port, GM_GP_CTRL,
1717 gma_read16(hw, port, GM_GP_CTRL) | reg);
1718
1719 switch (skge->speed) {
1720 case SPEED_1000:
1721 reg &= ~GM_GPCR_SPEED_100;
1722 reg |= GM_GPCR_SPEED_1000;
1723 break;
1724 case SPEED_100:
1725 reg &= ~GM_GPCR_SPEED_1000;
1726 reg |= GM_GPCR_SPEED_100;
1727 break;
1728 case SPEED_10:
1729 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1730 break;
1731 }
1732
1733 if (skge->duplex == DUPLEX_FULL)
1734 reg |= GM_GPCR_DUP_FULL;
1735 } else
1736 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1737
1738 switch (skge->flow_control) {
1739 case FLOW_MODE_NONE:
1740 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1741 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1742 break;
1743 case FLOW_MODE_LOC_SEND:
1744 /* disable Rx flow-control */
1745 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1746 }
1747
1748 gma_write16(hw, port, GM_GP_CTRL, reg);
1749 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1750
1751 yukon_init(hw, port);
1752
1753 /* MIB clear */
1754 reg = gma_read16(hw, port, GM_PHY_ADDR);
1755 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1756
1757 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1758 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1759 gma_write16(hw, port, GM_PHY_ADDR, reg);
1760
1761 /* transmit control */
1762 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1763
1764 /* receive control reg: unicast + multicast + no FCS */
1765 gma_write16(hw, port, GM_RX_CTRL,
1766 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1767
1768 /* transmit flow control */
1769 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1770
1771 /* transmit parameter */
1772 gma_write16(hw, port, GM_TX_PARAM,
1773 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1774 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1775 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1776
1777 /* serial mode register */
1778 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1779 if (hw->dev[port]->mtu > 1500)
1780 reg |= GM_SMOD_JUMBO_ENA;
1781
1782 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1783
1784 /* physical address: used for pause frames */
1785 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1786 /* virtual address for data */
1787 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1788
1789 /* enable interrupt mask for counter overflows */
1790 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1791 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1792 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1793
1794 /* Initialize Mac Fifo */
1795
1796 /* Configure Rx MAC FIFO */
1797 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1798 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1799
1800 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1801 if (is_yukon_lite_a0(hw))
1802 reg &= ~GMF_RX_F_FL_ON;
1803
1804 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1805 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1806 /*
1807 * because Pause Packet Truncation in GMAC is not working
1808 * we have to increase the Flush Threshold to 64 bytes
1809 * in order to flush pause packets in Rx FIFO on Yukon-1
1810 */
1811 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1812
1813 /* Configure Tx MAC FIFO */
1814 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1815 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1816 }
1817
1818 /* Go into power down mode */
1819 static void yukon_suspend(struct skge_hw *hw, int port)
1820 {
1821 u16 ctrl;
1822
1823 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1824 ctrl |= PHY_M_PC_POL_R_DIS;
1825 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1826
1827 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1828 ctrl |= PHY_CT_RESET;
1829 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1830
1831 /* switch IEEE compatible power down mode on */
1832 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1833 ctrl |= PHY_CT_PDOWN;
1834 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1835 }
1836
1837 static void yukon_stop(struct skge_port *skge)
1838 {
1839 struct skge_hw *hw = skge->hw;
1840 int port = skge->port;
1841
1842 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1843 yukon_reset(hw, port);
1844
1845 gma_write16(hw, port, GM_GP_CTRL,
1846 gma_read16(hw, port, GM_GP_CTRL)
1847 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1848 gma_read16(hw, port, GM_GP_CTRL);
1849
1850 yukon_suspend(hw, port);
1851
1852 /* set GPHY Control reset */
1853 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1854 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1855 }
1856
1857 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1858 {
1859 struct skge_hw *hw = skge->hw;
1860 int port = skge->port;
1861 int i;
1862
1863 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1864 | gma_read32(hw, port, GM_TXO_OK_LO);
1865 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1866 | gma_read32(hw, port, GM_RXO_OK_LO);
1867
1868 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1869 data[i] = gma_read32(hw, port,
1870 skge_stats[i].gma_offset);
1871 }
1872
1873 static void yukon_mac_intr(struct skge_hw *hw, int port)
1874 {
1875 struct net_device *dev = hw->dev[port];
1876 struct skge_port *skge = netdev_priv(dev);
1877 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1878
1879 if (netif_msg_intr(skge))
1880 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1881 dev->name, status);
1882
1883 if (status & GM_IS_RX_FF_OR) {
1884 ++skge->net_stats.rx_fifo_errors;
1885 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1886 }
1887
1888 if (status & GM_IS_TX_FF_UR) {
1889 ++skge->net_stats.tx_fifo_errors;
1890 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1891 }
1892
1893 }
1894
1895 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1896 {
1897 switch (aux & PHY_M_PS_SPEED_MSK) {
1898 case PHY_M_PS_SPEED_1000:
1899 return SPEED_1000;
1900 case PHY_M_PS_SPEED_100:
1901 return SPEED_100;
1902 default:
1903 return SPEED_10;
1904 }
1905 }
1906
1907 static void yukon_link_up(struct skge_port *skge)
1908 {
1909 struct skge_hw *hw = skge->hw;
1910 int port = skge->port;
1911 u16 reg;
1912
1913 /* Enable Transmit FIFO Underrun */
1914 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1915
1916 reg = gma_read16(hw, port, GM_GP_CTRL);
1917 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1918 reg |= GM_GPCR_DUP_FULL;
1919
1920 /* enable Rx/Tx */
1921 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1922 gma_write16(hw, port, GM_GP_CTRL, reg);
1923
1924 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1925 skge_link_up(skge);
1926 }
1927
1928 static void yukon_link_down(struct skge_port *skge)
1929 {
1930 struct skge_hw *hw = skge->hw;
1931 int port = skge->port;
1932 u16 ctrl;
1933
1934 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1935
1936 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1937 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1938 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1939
1940 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1941 /* restore Asymmetric Pause bit */
1942 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1943 gm_phy_read(hw, port,
1944 PHY_MARV_AUNE_ADV)
1945 | PHY_M_AN_ASP);
1946
1947 }
1948
1949 yukon_reset(hw, port);
1950 skge_link_down(skge);
1951
1952 yukon_init(hw, port);
1953 }
1954
1955 static void yukon_phy_intr(struct skge_port *skge)
1956 {
1957 struct skge_hw *hw = skge->hw;
1958 int port = skge->port;
1959 const char *reason = NULL;
1960 u16 istatus, phystat;
1961
1962 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1963 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1964
1965 if (netif_msg_intr(skge))
1966 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1967 skge->netdev->name, istatus, phystat);
1968
1969 if (istatus & PHY_M_IS_AN_COMPL) {
1970 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1971 & PHY_M_AN_RF) {
1972 reason = "remote fault";
1973 goto failed;
1974 }
1975
1976 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1977 reason = "master/slave fault";
1978 goto failed;
1979 }
1980
1981 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1982 reason = "speed/duplex";
1983 goto failed;
1984 }
1985
1986 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1987 ? DUPLEX_FULL : DUPLEX_HALF;
1988 skge->speed = yukon_speed(hw, phystat);
1989
1990 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1991 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1992 case PHY_M_PS_PAUSE_MSK:
1993 skge->flow_control = FLOW_MODE_SYMMETRIC;
1994 break;
1995 case PHY_M_PS_RX_P_EN:
1996 skge->flow_control = FLOW_MODE_REM_SEND;
1997 break;
1998 case PHY_M_PS_TX_P_EN:
1999 skge->flow_control = FLOW_MODE_LOC_SEND;
2000 break;
2001 default:
2002 skge->flow_control = FLOW_MODE_NONE;
2003 }
2004
2005 if (skge->flow_control == FLOW_MODE_NONE ||
2006 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2007 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2008 else
2009 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2010 yukon_link_up(skge);
2011 return;
2012 }
2013
2014 if (istatus & PHY_M_IS_LSP_CHANGE)
2015 skge->speed = yukon_speed(hw, phystat);
2016
2017 if (istatus & PHY_M_IS_DUP_CHANGE)
2018 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2019 if (istatus & PHY_M_IS_LST_CHANGE) {
2020 if (phystat & PHY_M_PS_LINK_UP)
2021 yukon_link_up(skge);
2022 else
2023 yukon_link_down(skge);
2024 }
2025 return;
2026 failed:
2027 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2028 skge->netdev->name, reason);
2029
2030 /* XXX restart autonegotiation? */
2031 }
2032
2033 static void skge_phy_reset(struct skge_port *skge)
2034 {
2035 struct skge_hw *hw = skge->hw;
2036 int port = skge->port;
2037
2038 netif_stop_queue(skge->netdev);
2039 netif_carrier_off(skge->netdev);
2040
2041 mutex_lock(&hw->phy_mutex);
2042 if (hw->chip_id == CHIP_ID_GENESIS) {
2043 genesis_reset(hw, port);
2044 genesis_mac_init(hw, port);
2045 } else {
2046 yukon_reset(hw, port);
2047 yukon_init(hw, port);
2048 }
2049 mutex_unlock(&hw->phy_mutex);
2050 }
2051
2052 /* Basic MII support */
2053 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2054 {
2055 struct mii_ioctl_data *data = if_mii(ifr);
2056 struct skge_port *skge = netdev_priv(dev);
2057 struct skge_hw *hw = skge->hw;
2058 int err = -EOPNOTSUPP;
2059
2060 if (!netif_running(dev))
2061 return -ENODEV; /* Phy still in reset */
2062
2063 switch(cmd) {
2064 case SIOCGMIIPHY:
2065 data->phy_id = hw->phy_addr;
2066
2067 /* fallthru */
2068 case SIOCGMIIREG: {
2069 u16 val = 0;
2070 mutex_lock(&hw->phy_mutex);
2071 if (hw->chip_id == CHIP_ID_GENESIS)
2072 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2073 else
2074 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2075 mutex_unlock(&hw->phy_mutex);
2076 data->val_out = val;
2077 break;
2078 }
2079
2080 case SIOCSMIIREG:
2081 if (!capable(CAP_NET_ADMIN))
2082 return -EPERM;
2083
2084 mutex_lock(&hw->phy_mutex);
2085 if (hw->chip_id == CHIP_ID_GENESIS)
2086 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2087 data->val_in);
2088 else
2089 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2090 data->val_in);
2091 mutex_unlock(&hw->phy_mutex);
2092 break;
2093 }
2094 return err;
2095 }
2096
2097 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2098 {
2099 u32 end;
2100
2101 start /= 8;
2102 len /= 8;
2103 end = start + len - 1;
2104
2105 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2106 skge_write32(hw, RB_ADDR(q, RB_START), start);
2107 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2108 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2109 skge_write32(hw, RB_ADDR(q, RB_END), end);
2110
2111 if (q == Q_R1 || q == Q_R2) {
2112 /* Set thresholds on receive queue's */
2113 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2114 start + (2*len)/3);
2115 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2116 start + (len/3));
2117 } else {
2118 /* Enable store & forward on Tx queue's because
2119 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2120 */
2121 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2122 }
2123
2124 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2125 }
2126
2127 /* Setup Bus Memory Interface */
2128 static void skge_qset(struct skge_port *skge, u16 q,
2129 const struct skge_element *e)
2130 {
2131 struct skge_hw *hw = skge->hw;
2132 u32 watermark = 0x600;
2133 u64 base = skge->dma + (e->desc - skge->mem);
2134
2135 /* optimization to reduce window on 32bit/33mhz */
2136 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2137 watermark /= 2;
2138
2139 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2140 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2141 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2142 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2143 }
2144
2145 static int skge_up(struct net_device *dev)
2146 {
2147 struct skge_port *skge = netdev_priv(dev);
2148 struct skge_hw *hw = skge->hw;
2149 int port = skge->port;
2150 u32 chunk, ram_addr;
2151 size_t rx_size, tx_size;
2152 int err;
2153
2154 if (netif_msg_ifup(skge))
2155 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2156
2157 if (dev->mtu > RX_BUF_SIZE)
2158 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2159 else
2160 skge->rx_buf_size = RX_BUF_SIZE;
2161
2162
2163 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2164 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2165 skge->mem_size = tx_size + rx_size;
2166 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2167 if (!skge->mem)
2168 return -ENOMEM;
2169
2170 BUG_ON(skge->dma & 7);
2171
2172 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2173 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2174 err = -EINVAL;
2175 goto free_pci_mem;
2176 }
2177
2178 memset(skge->mem, 0, skge->mem_size);
2179
2180 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2181 if (err)
2182 goto free_pci_mem;
2183
2184 err = skge_rx_fill(skge);
2185 if (err)
2186 goto free_rx_ring;
2187
2188 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2189 skge->dma + rx_size);
2190 if (err)
2191 goto free_rx_ring;
2192
2193 /* Initialize MAC */
2194 mutex_lock(&hw->phy_mutex);
2195 if (hw->chip_id == CHIP_ID_GENESIS)
2196 genesis_mac_init(hw, port);
2197 else
2198 yukon_mac_init(hw, port);
2199 mutex_unlock(&hw->phy_mutex);
2200
2201 /* Configure RAMbuffers */
2202 chunk = hw->ram_size / ((hw->ports + 1)*2);
2203 ram_addr = hw->ram_offset + 2 * chunk * port;
2204
2205 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2206 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2207
2208 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2209 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2210 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2211
2212 /* Start receiver BMU */
2213 wmb();
2214 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2215 skge_led(skge, LED_MODE_ON);
2216
2217 return 0;
2218
2219 free_rx_ring:
2220 skge_rx_clean(skge);
2221 kfree(skge->rx_ring.start);
2222 free_pci_mem:
2223 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2224 skge->mem = NULL;
2225
2226 return err;
2227 }
2228
2229 static int skge_down(struct net_device *dev)
2230 {
2231 struct skge_port *skge = netdev_priv(dev);
2232 struct skge_hw *hw = skge->hw;
2233 int port = skge->port;
2234
2235 if (skge->mem == NULL)
2236 return 0;
2237
2238 if (netif_msg_ifdown(skge))
2239 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2240
2241 netif_stop_queue(dev);
2242
2243 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2244 if (hw->chip_id == CHIP_ID_GENESIS)
2245 genesis_stop(skge);
2246 else
2247 yukon_stop(skge);
2248
2249 /* Stop transmitter */
2250 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2251 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2252 RB_RST_SET|RB_DIS_OP_MD);
2253
2254
2255 /* Disable Force Sync bit and Enable Alloc bit */
2256 skge_write8(hw, SK_REG(port, TXA_CTRL),
2257 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2258
2259 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2260 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2261 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2262
2263 /* Reset PCI FIFO */
2264 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2265 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2266
2267 /* Reset the RAM Buffer async Tx queue */
2268 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2269 /* stop receiver */
2270 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2271 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2272 RB_RST_SET|RB_DIS_OP_MD);
2273 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2274
2275 if (hw->chip_id == CHIP_ID_GENESIS) {
2276 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2277 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2278 } else {
2279 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2280 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2281 }
2282
2283 skge_led(skge, LED_MODE_OFF);
2284
2285 skge_tx_clean(skge);
2286 skge_rx_clean(skge);
2287
2288 kfree(skge->rx_ring.start);
2289 kfree(skge->tx_ring.start);
2290 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2291 skge->mem = NULL;
2292 return 0;
2293 }
2294
2295 static inline int skge_avail(const struct skge_ring *ring)
2296 {
2297 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2298 + (ring->to_clean - ring->to_use) - 1;
2299 }
2300
2301 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2302 {
2303 struct skge_port *skge = netdev_priv(dev);
2304 struct skge_hw *hw = skge->hw;
2305 struct skge_element *e;
2306 struct skge_tx_desc *td;
2307 int i;
2308 u32 control, len;
2309 u64 map;
2310 unsigned long flags;
2311
2312 if (skb_padto(skb, ETH_ZLEN))
2313 return NETDEV_TX_OK;
2314
2315 if (!spin_trylock_irqsave(&skge->tx_lock, flags))
2316 /* Collision - tell upper layer to requeue */
2317 return NETDEV_TX_LOCKED;
2318
2319 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) {
2320 if (!netif_queue_stopped(dev)) {
2321 netif_stop_queue(dev);
2322
2323 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2324 dev->name);
2325 }
2326 spin_unlock_irqrestore(&skge->tx_lock, flags);
2327 return NETDEV_TX_BUSY;
2328 }
2329
2330 e = skge->tx_ring.to_use;
2331 td = e->desc;
2332 BUG_ON(td->control & BMU_OWN);
2333 e->skb = skb;
2334 len = skb_headlen(skb);
2335 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2336 pci_unmap_addr_set(e, mapaddr, map);
2337 pci_unmap_len_set(e, maplen, len);
2338
2339 td->dma_lo = map;
2340 td->dma_hi = map >> 32;
2341
2342 if (skb->ip_summed == CHECKSUM_HW) {
2343 int offset = skb->h.raw - skb->data;
2344
2345 /* This seems backwards, but it is what the sk98lin
2346 * does. Looks like hardware is wrong?
2347 */
2348 if (skb->h.ipiph->protocol == IPPROTO_UDP
2349 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2350 control = BMU_TCP_CHECK;
2351 else
2352 control = BMU_UDP_CHECK;
2353
2354 td->csum_offs = 0;
2355 td->csum_start = offset;
2356 td->csum_write = offset + skb->csum;
2357 } else
2358 control = BMU_CHECK;
2359
2360 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2361 control |= BMU_EOF| BMU_IRQ_EOF;
2362 else {
2363 struct skge_tx_desc *tf = td;
2364
2365 control |= BMU_STFWD;
2366 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2367 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2368
2369 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2370 frag->size, PCI_DMA_TODEVICE);
2371
2372 e = e->next;
2373 e->skb = skb;
2374 tf = e->desc;
2375 BUG_ON(tf->control & BMU_OWN);
2376
2377 tf->dma_lo = map;
2378 tf->dma_hi = (u64) map >> 32;
2379 pci_unmap_addr_set(e, mapaddr, map);
2380 pci_unmap_len_set(e, maplen, frag->size);
2381
2382 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2383 }
2384 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2385 }
2386 /* Make sure all the descriptors written */
2387 wmb();
2388 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2389 wmb();
2390
2391 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2392
2393 if (unlikely(netif_msg_tx_queued(skge)))
2394 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2395 dev->name, e - skge->tx_ring.start, skb->len);
2396
2397 skge->tx_ring.to_use = e->next;
2398 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2399 pr_debug("%s: transmit queue full\n", dev->name);
2400 netif_stop_queue(dev);
2401 }
2402
2403 spin_unlock_irqrestore(&skge->tx_lock, flags);
2404
2405 dev->trans_start = jiffies;
2406
2407 return NETDEV_TX_OK;
2408 }
2409
2410
2411 /* Free resources associated with this reing element */
2412 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2413 u32 control)
2414 {
2415 struct pci_dev *pdev = skge->hw->pdev;
2416
2417 BUG_ON(!e->skb);
2418
2419 /* skb header vs. fragment */
2420 if (control & BMU_STF)
2421 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2422 pci_unmap_len(e, maplen),
2423 PCI_DMA_TODEVICE);
2424 else
2425 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2426 pci_unmap_len(e, maplen),
2427 PCI_DMA_TODEVICE);
2428
2429 if (control & BMU_EOF) {
2430 if (unlikely(netif_msg_tx_done(skge)))
2431 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2432 skge->netdev->name, e - skge->tx_ring.start);
2433
2434 dev_kfree_skb_any(e->skb);
2435 }
2436 e->skb = NULL;
2437 }
2438
2439 /* Free all buffers in transmit ring */
2440 static void skge_tx_clean(struct skge_port *skge)
2441 {
2442 struct skge_element *e;
2443 unsigned long flags;
2444
2445 spin_lock_irqsave(&skge->tx_lock, flags);
2446 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2447 struct skge_tx_desc *td = e->desc;
2448 skge_tx_free(skge, e, td->control);
2449 td->control = 0;
2450 }
2451
2452 skge->tx_ring.to_clean = e;
2453 netif_wake_queue(skge->netdev);
2454 spin_unlock_irqrestore(&skge->tx_lock, flags);
2455 }
2456
2457 static void skge_tx_timeout(struct net_device *dev)
2458 {
2459 struct skge_port *skge = netdev_priv(dev);
2460
2461 if (netif_msg_timer(skge))
2462 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2463
2464 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2465 skge_tx_clean(skge);
2466 }
2467
2468 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2469 {
2470 int err;
2471
2472 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2473 return -EINVAL;
2474
2475 if (!netif_running(dev)) {
2476 dev->mtu = new_mtu;
2477 return 0;
2478 }
2479
2480 skge_down(dev);
2481
2482 dev->mtu = new_mtu;
2483
2484 err = skge_up(dev);
2485 if (err)
2486 dev_close(dev);
2487
2488 return err;
2489 }
2490
2491 static void genesis_set_multicast(struct net_device *dev)
2492 {
2493 struct skge_port *skge = netdev_priv(dev);
2494 struct skge_hw *hw = skge->hw;
2495 int port = skge->port;
2496 int i, count = dev->mc_count;
2497 struct dev_mc_list *list = dev->mc_list;
2498 u32 mode;
2499 u8 filter[8];
2500
2501 mode = xm_read32(hw, port, XM_MODE);
2502 mode |= XM_MD_ENA_HASH;
2503 if (dev->flags & IFF_PROMISC)
2504 mode |= XM_MD_ENA_PROM;
2505 else
2506 mode &= ~XM_MD_ENA_PROM;
2507
2508 if (dev->flags & IFF_ALLMULTI)
2509 memset(filter, 0xff, sizeof(filter));
2510 else {
2511 memset(filter, 0, sizeof(filter));
2512 for (i = 0; list && i < count; i++, list = list->next) {
2513 u32 crc, bit;
2514 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2515 bit = ~crc & 0x3f;
2516 filter[bit/8] |= 1 << (bit%8);
2517 }
2518 }
2519
2520 xm_write32(hw, port, XM_MODE, mode);
2521 xm_outhash(hw, port, XM_HSM, filter);
2522 }
2523
2524 static void yukon_set_multicast(struct net_device *dev)
2525 {
2526 struct skge_port *skge = netdev_priv(dev);
2527 struct skge_hw *hw = skge->hw;
2528 int port = skge->port;
2529 struct dev_mc_list *list = dev->mc_list;
2530 u16 reg;
2531 u8 filter[8];
2532
2533 memset(filter, 0, sizeof(filter));
2534
2535 reg = gma_read16(hw, port, GM_RX_CTRL);
2536 reg |= GM_RXCR_UCF_ENA;
2537
2538 if (dev->flags & IFF_PROMISC) /* promiscuous */
2539 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2540 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2541 memset(filter, 0xff, sizeof(filter));
2542 else if (dev->mc_count == 0) /* no multicast */
2543 reg &= ~GM_RXCR_MCF_ENA;
2544 else {
2545 int i;
2546 reg |= GM_RXCR_MCF_ENA;
2547
2548 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2549 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2550 filter[bit/8] |= 1 << (bit%8);
2551 }
2552 }
2553
2554
2555 gma_write16(hw, port, GM_MC_ADDR_H1,
2556 (u16)filter[0] | ((u16)filter[1] << 8));
2557 gma_write16(hw, port, GM_MC_ADDR_H2,
2558 (u16)filter[2] | ((u16)filter[3] << 8));
2559 gma_write16(hw, port, GM_MC_ADDR_H3,
2560 (u16)filter[4] | ((u16)filter[5] << 8));
2561 gma_write16(hw, port, GM_MC_ADDR_H4,
2562 (u16)filter[6] | ((u16)filter[7] << 8));
2563
2564 gma_write16(hw, port, GM_RX_CTRL, reg);
2565 }
2566
2567 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2568 {
2569 if (hw->chip_id == CHIP_ID_GENESIS)
2570 return status >> XMR_FS_LEN_SHIFT;
2571 else
2572 return status >> GMR_FS_LEN_SHIFT;
2573 }
2574
2575 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2576 {
2577 if (hw->chip_id == CHIP_ID_GENESIS)
2578 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2579 else
2580 return (status & GMR_FS_ANY_ERR) ||
2581 (status & GMR_FS_RX_OK) == 0;
2582 }
2583
2584
2585 /* Get receive buffer from descriptor.
2586 * Handles copy of small buffers and reallocation failures
2587 */
2588 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2589 struct skge_element *e,
2590 u32 control, u32 status, u16 csum)
2591 {
2592 struct sk_buff *skb;
2593 u16 len = control & BMU_BBC;
2594
2595 if (unlikely(netif_msg_rx_status(skge)))
2596 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2597 skge->netdev->name, e - skge->rx_ring.start,
2598 status, len);
2599
2600 if (len > skge->rx_buf_size)
2601 goto error;
2602
2603 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2604 goto error;
2605
2606 if (bad_phy_status(skge->hw, status))
2607 goto error;
2608
2609 if (phy_length(skge->hw, status) != len)
2610 goto error;
2611
2612 if (len < RX_COPY_THRESHOLD) {
2613 skb = alloc_skb(len + 2, GFP_ATOMIC);
2614 if (!skb)
2615 goto resubmit;
2616
2617 skb_reserve(skb, 2);
2618 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2619 pci_unmap_addr(e, mapaddr),
2620 len, PCI_DMA_FROMDEVICE);
2621 memcpy(skb->data, e->skb->data, len);
2622 pci_dma_sync_single_for_device(skge->hw->pdev,
2623 pci_unmap_addr(e, mapaddr),
2624 len, PCI_DMA_FROMDEVICE);
2625 skge_rx_reuse(e, skge->rx_buf_size);
2626 } else {
2627 struct sk_buff *nskb;
2628 nskb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_ATOMIC);
2629 if (!nskb)
2630 goto resubmit;
2631
2632 skb_reserve(nskb, NET_IP_ALIGN);
2633 pci_unmap_single(skge->hw->pdev,
2634 pci_unmap_addr(e, mapaddr),
2635 pci_unmap_len(e, maplen),
2636 PCI_DMA_FROMDEVICE);
2637 skb = e->skb;
2638 prefetch(skb->data);
2639 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2640 }
2641
2642 skb_put(skb, len);
2643 skb->dev = skge->netdev;
2644 if (skge->rx_csum) {
2645 skb->csum = csum;
2646 skb->ip_summed = CHECKSUM_HW;
2647 }
2648
2649 skb->protocol = eth_type_trans(skb, skge->netdev);
2650
2651 return skb;
2652 error:
2653
2654 if (netif_msg_rx_err(skge))
2655 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2656 skge->netdev->name, e - skge->rx_ring.start,
2657 control, status);
2658
2659 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2660 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2661 skge->net_stats.rx_length_errors++;
2662 if (status & XMR_FS_FRA_ERR)
2663 skge->net_stats.rx_frame_errors++;
2664 if (status & XMR_FS_FCS_ERR)
2665 skge->net_stats.rx_crc_errors++;
2666 } else {
2667 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2668 skge->net_stats.rx_length_errors++;
2669 if (status & GMR_FS_FRAGMENT)
2670 skge->net_stats.rx_frame_errors++;
2671 if (status & GMR_FS_CRC_ERR)
2672 skge->net_stats.rx_crc_errors++;
2673 }
2674
2675 resubmit:
2676 skge_rx_reuse(e, skge->rx_buf_size);
2677 return NULL;
2678 }
2679
2680 /* Free all buffers in Tx ring which are no longer owned by device */
2681 static void skge_txirq(struct net_device *dev)
2682 {
2683 struct skge_port *skge = netdev_priv(dev);
2684 struct skge_ring *ring = &skge->tx_ring;
2685 struct skge_element *e;
2686
2687 rmb();
2688
2689 spin_lock(&skge->tx_lock);
2690 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2691 struct skge_tx_desc *td = e->desc;
2692
2693 if (td->control & BMU_OWN)
2694 break;
2695
2696 skge_tx_free(skge, e, td->control);
2697 }
2698 skge->tx_ring.to_clean = e;
2699
2700 if (netif_queue_stopped(skge->netdev)
2701 && skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2702 netif_wake_queue(skge->netdev);
2703
2704 spin_unlock(&skge->tx_lock);
2705 }
2706
2707 static int skge_poll(struct net_device *dev, int *budget)
2708 {
2709 struct skge_port *skge = netdev_priv(dev);
2710 struct skge_hw *hw = skge->hw;
2711 struct skge_ring *ring = &skge->rx_ring;
2712 struct skge_element *e;
2713 int to_do = min(dev->quota, *budget);
2714 int work_done = 0;
2715
2716 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2717 struct skge_rx_desc *rd = e->desc;
2718 struct sk_buff *skb;
2719 u32 control;
2720
2721 rmb();
2722 control = rd->control;
2723 if (control & BMU_OWN)
2724 break;
2725
2726 skb = skge_rx_get(skge, e, control, rd->status, rd->csum2);
2727 if (likely(skb)) {
2728 dev->last_rx = jiffies;
2729 netif_receive_skb(skb);
2730
2731 ++work_done;
2732 }
2733 }
2734 ring->to_clean = e;
2735
2736 /* restart receiver */
2737 wmb();
2738 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2739
2740 *budget -= work_done;
2741 dev->quota -= work_done;
2742
2743 if (work_done >= to_do)
2744 return 1; /* not done */
2745
2746 netif_rx_complete(dev);
2747
2748 spin_lock_irq(&hw->hw_lock);
2749 hw->intr_mask |= rxirqmask[skge->port];
2750 skge_write32(hw, B0_IMSK, hw->intr_mask);
2751 mmiowb();
2752 spin_unlock_irq(&hw->hw_lock);
2753
2754 return 0;
2755 }
2756
2757 /* Parity errors seem to happen when Genesis is connected to a switch
2758 * with no other ports present. Heartbeat error??
2759 */
2760 static void skge_mac_parity(struct skge_hw *hw, int port)
2761 {
2762 struct net_device *dev = hw->dev[port];
2763
2764 if (dev) {
2765 struct skge_port *skge = netdev_priv(dev);
2766 ++skge->net_stats.tx_heartbeat_errors;
2767 }
2768
2769 if (hw->chip_id == CHIP_ID_GENESIS)
2770 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2771 MFF_CLR_PERR);
2772 else
2773 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2774 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2775 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2776 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2777 }
2778
2779 static void skge_mac_intr(struct skge_hw *hw, int port)
2780 {
2781 if (hw->chip_id == CHIP_ID_GENESIS)
2782 genesis_mac_intr(hw, port);
2783 else
2784 yukon_mac_intr(hw, port);
2785 }
2786
2787 /* Handle device specific framing and timeout interrupts */
2788 static void skge_error_irq(struct skge_hw *hw)
2789 {
2790 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2791
2792 if (hw->chip_id == CHIP_ID_GENESIS) {
2793 /* clear xmac errors */
2794 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2795 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2796 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2797 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2798 } else {
2799 /* Timestamp (unused) overflow */
2800 if (hwstatus & IS_IRQ_TIST_OV)
2801 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2802 }
2803
2804 if (hwstatus & IS_RAM_RD_PAR) {
2805 printk(KERN_ERR PFX "Ram read data parity error\n");
2806 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2807 }
2808
2809 if (hwstatus & IS_RAM_WR_PAR) {
2810 printk(KERN_ERR PFX "Ram write data parity error\n");
2811 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2812 }
2813
2814 if (hwstatus & IS_M1_PAR_ERR)
2815 skge_mac_parity(hw, 0);
2816
2817 if (hwstatus & IS_M2_PAR_ERR)
2818 skge_mac_parity(hw, 1);
2819
2820 if (hwstatus & IS_R1_PAR_ERR) {
2821 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2822 hw->dev[0]->name);
2823 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2824 }
2825
2826 if (hwstatus & IS_R2_PAR_ERR) {
2827 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2828 hw->dev[1]->name);
2829 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2830 }
2831
2832 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2833 u16 pci_status, pci_cmd;
2834
2835 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
2836 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
2837
2838 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
2839 pci_name(hw->pdev), pci_cmd, pci_status);
2840
2841 /* Write the error bits back to clear them. */
2842 pci_status &= PCI_STATUS_ERROR_BITS;
2843 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2844 pci_write_config_word(hw->pdev, PCI_COMMAND,
2845 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2846 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
2847 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2848
2849 /* if error still set then just ignore it */
2850 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2851 if (hwstatus & IS_IRQ_STAT) {
2852 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
2853 hw->intr_mask &= ~IS_HW_ERR;
2854 }
2855 }
2856 }
2857
2858 /*
2859 * Interrupt from PHY are handled in work queue
2860 * because accessing phy registers requires spin wait which might
2861 * cause excess interrupt latency.
2862 */
2863 static void skge_extirq(void *arg)
2864 {
2865 struct skge_hw *hw = arg;
2866 int port;
2867
2868 mutex_lock(&hw->phy_mutex);
2869 for (port = 0; port < hw->ports; port++) {
2870 struct net_device *dev = hw->dev[port];
2871 struct skge_port *skge = netdev_priv(dev);
2872
2873 if (netif_running(dev)) {
2874 if (hw->chip_id != CHIP_ID_GENESIS)
2875 yukon_phy_intr(skge);
2876 else
2877 bcom_phy_intr(skge);
2878 }
2879 }
2880 mutex_unlock(&hw->phy_mutex);
2881
2882 spin_lock_irq(&hw->hw_lock);
2883 hw->intr_mask |= IS_EXT_REG;
2884 skge_write32(hw, B0_IMSK, hw->intr_mask);
2885 spin_unlock_irq(&hw->hw_lock);
2886 }
2887
2888 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2889 {
2890 struct skge_hw *hw = dev_id;
2891 u32 status;
2892
2893 /* Reading this register masks IRQ */
2894 status = skge_read32(hw, B0_SP_ISRC);
2895 if (status == 0)
2896 return IRQ_NONE;
2897
2898 spin_lock(&hw->hw_lock);
2899 status &= hw->intr_mask;
2900 if (status & IS_EXT_REG) {
2901 hw->intr_mask &= ~IS_EXT_REG;
2902 schedule_work(&hw->phy_work);
2903 }
2904
2905 if (status & IS_XA1_F) {
2906 skge_write8(hw, Q_ADDR(Q_XA1, Q_CSR), CSR_IRQ_CL_F);
2907 skge_txirq(hw->dev[0]);
2908 }
2909
2910 if (status & IS_R1_F) {
2911 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2912 hw->intr_mask &= ~IS_R1_F;
2913 netif_rx_schedule(hw->dev[0]);
2914 }
2915
2916 if (status & IS_PA_TO_TX1)
2917 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2918
2919 if (status & IS_PA_TO_RX1) {
2920 struct skge_port *skge = netdev_priv(hw->dev[0]);
2921
2922 ++skge->net_stats.rx_over_errors;
2923 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2924 }
2925
2926
2927 if (status & IS_MAC1)
2928 skge_mac_intr(hw, 0);
2929
2930 if (hw->dev[1]) {
2931 if (status & IS_XA2_F) {
2932 skge_write8(hw, Q_ADDR(Q_XA2, Q_CSR), CSR_IRQ_CL_F);
2933 skge_txirq(hw->dev[1]);
2934 }
2935
2936 if (status & IS_R2_F) {
2937 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2938 hw->intr_mask &= ~IS_R2_F;
2939 netif_rx_schedule(hw->dev[1]);
2940 }
2941
2942 if (status & IS_PA_TO_RX2) {
2943 struct skge_port *skge = netdev_priv(hw->dev[1]);
2944 ++skge->net_stats.rx_over_errors;
2945 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2946 }
2947
2948 if (status & IS_PA_TO_TX2)
2949 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2950
2951 if (status & IS_MAC2)
2952 skge_mac_intr(hw, 1);
2953 }
2954
2955 if (status & IS_HW_ERR)
2956 skge_error_irq(hw);
2957
2958 skge_write32(hw, B0_IMSK, hw->intr_mask);
2959 spin_unlock(&hw->hw_lock);
2960
2961 return IRQ_HANDLED;
2962 }
2963
2964 #ifdef CONFIG_NET_POLL_CONTROLLER
2965 static void skge_netpoll(struct net_device *dev)
2966 {
2967 struct skge_port *skge = netdev_priv(dev);
2968
2969 disable_irq(dev->irq);
2970 skge_intr(dev->irq, skge->hw, NULL);
2971 enable_irq(dev->irq);
2972 }
2973 #endif
2974
2975 static int skge_set_mac_address(struct net_device *dev, void *p)
2976 {
2977 struct skge_port *skge = netdev_priv(dev);
2978 struct skge_hw *hw = skge->hw;
2979 unsigned port = skge->port;
2980 const struct sockaddr *addr = p;
2981
2982 if (!is_valid_ether_addr(addr->sa_data))
2983 return -EADDRNOTAVAIL;
2984
2985 mutex_lock(&hw->phy_mutex);
2986 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2987 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2988 dev->dev_addr, ETH_ALEN);
2989 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2990 dev->dev_addr, ETH_ALEN);
2991
2992 if (hw->chip_id == CHIP_ID_GENESIS)
2993 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2994 else {
2995 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2996 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2997 }
2998 mutex_unlock(&hw->phy_mutex);
2999
3000 return 0;
3001 }
3002
3003 static const struct {
3004 u8 id;
3005 const char *name;
3006 } skge_chips[] = {
3007 { CHIP_ID_GENESIS, "Genesis" },
3008 { CHIP_ID_YUKON, "Yukon" },
3009 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3010 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3011 };
3012
3013 static const char *skge_board_name(const struct skge_hw *hw)
3014 {
3015 int i;
3016 static char buf[16];
3017
3018 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3019 if (skge_chips[i].id == hw->chip_id)
3020 return skge_chips[i].name;
3021
3022 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3023 return buf;
3024 }
3025
3026
3027 /*
3028 * Setup the board data structure, but don't bring up
3029 * the port(s)
3030 */
3031 static int skge_reset(struct skge_hw *hw)
3032 {
3033 u32 reg;
3034 u16 ctst, pci_status;
3035 u8 t8, mac_cfg, pmd_type, phy_type;
3036 int i;
3037
3038 ctst = skge_read16(hw, B0_CTST);
3039
3040 /* do a SW reset */
3041 skge_write8(hw, B0_CTST, CS_RST_SET);
3042 skge_write8(hw, B0_CTST, CS_RST_CLR);
3043
3044 /* clear PCI errors, if any */
3045 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3046 skge_write8(hw, B2_TST_CTRL2, 0);
3047
3048 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3049 pci_write_config_word(hw->pdev, PCI_STATUS,
3050 pci_status | PCI_STATUS_ERROR_BITS);
3051 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3052 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3053
3054 /* restore CLK_RUN bits (for Yukon-Lite) */
3055 skge_write16(hw, B0_CTST,
3056 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3057
3058 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3059 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3060 pmd_type = skge_read8(hw, B2_PMD_TYP);
3061 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3062
3063 switch (hw->chip_id) {
3064 case CHIP_ID_GENESIS:
3065 switch (phy_type) {
3066 case SK_PHY_BCOM:
3067 hw->phy_addr = PHY_ADDR_BCOM;
3068 break;
3069 default:
3070 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3071 pci_name(hw->pdev), phy_type);
3072 return -EOPNOTSUPP;
3073 }
3074 break;
3075
3076 case CHIP_ID_YUKON:
3077 case CHIP_ID_YUKON_LITE:
3078 case CHIP_ID_YUKON_LP:
3079 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3080 hw->copper = 1;
3081
3082 hw->phy_addr = PHY_ADDR_MARV;
3083 break;
3084
3085 default:
3086 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3087 pci_name(hw->pdev), hw->chip_id);
3088 return -EOPNOTSUPP;
3089 }
3090
3091 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3092 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3093 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3094
3095 /* read the adapters RAM size */
3096 t8 = skge_read8(hw, B2_E_0);
3097 if (hw->chip_id == CHIP_ID_GENESIS) {
3098 if (t8 == 3) {
3099 /* special case: 4 x 64k x 36, offset = 0x80000 */
3100 hw->ram_size = 0x100000;
3101 hw->ram_offset = 0x80000;
3102 } else
3103 hw->ram_size = t8 * 512;
3104 }
3105 else if (t8 == 0)
3106 hw->ram_size = 0x20000;
3107 else
3108 hw->ram_size = t8 * 4096;
3109
3110 spin_lock_init(&hw->hw_lock);
3111 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3112 if (hw->ports > 1)
3113 hw->intr_mask |= IS_PORT_2;
3114
3115 if (hw->chip_id == CHIP_ID_GENESIS)
3116 genesis_init(hw);
3117 else {
3118 /* switch power to VCC (WA for VAUX problem) */
3119 skge_write8(hw, B0_POWER_CTRL,
3120 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3121
3122 /* avoid boards with stuck Hardware error bits */
3123 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3124 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3125 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3126 hw->intr_mask &= ~IS_HW_ERR;
3127 }
3128
3129 /* Clear PHY COMA */
3130 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3131 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3132 reg &= ~PCI_PHY_COMA;
3133 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3134 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3135
3136
3137 for (i = 0; i < hw->ports; i++) {
3138 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3139 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3140 }
3141 }
3142
3143 /* turn off hardware timer (unused) */
3144 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3145 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3146 skge_write8(hw, B0_LED, LED_STAT_ON);
3147
3148 /* enable the Tx Arbiters */
3149 for (i = 0; i < hw->ports; i++)
3150 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3151
3152 /* Initialize ram interface */
3153 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3154
3155 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3156 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3157 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3158 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3159 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3160 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3161 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3162 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3163 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3164 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3165 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3166 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3167
3168 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3169
3170 /* Set interrupt moderation for Transmit only
3171 * Receive interrupts avoided by NAPI
3172 */
3173 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3174 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3175 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3176
3177 skge_write32(hw, B0_IMSK, hw->intr_mask);
3178
3179 mutex_lock(&hw->phy_mutex);
3180 for (i = 0; i < hw->ports; i++) {
3181 if (hw->chip_id == CHIP_ID_GENESIS)
3182 genesis_reset(hw, i);
3183 else
3184 yukon_reset(hw, i);
3185 }
3186 mutex_unlock(&hw->phy_mutex);
3187
3188 return 0;
3189 }
3190
3191 /* Initialize network device */
3192 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3193 int highmem)
3194 {
3195 struct skge_port *skge;
3196 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3197
3198 if (!dev) {
3199 printk(KERN_ERR "skge etherdev alloc failed");
3200 return NULL;
3201 }
3202
3203 SET_MODULE_OWNER(dev);
3204 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3205 dev->open = skge_up;
3206 dev->stop = skge_down;
3207 dev->do_ioctl = skge_ioctl;
3208 dev->hard_start_xmit = skge_xmit_frame;
3209 dev->get_stats = skge_get_stats;
3210 if (hw->chip_id == CHIP_ID_GENESIS)
3211 dev->set_multicast_list = genesis_set_multicast;
3212 else
3213 dev->set_multicast_list = yukon_set_multicast;
3214
3215 dev->set_mac_address = skge_set_mac_address;
3216 dev->change_mtu = skge_change_mtu;
3217 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3218 dev->tx_timeout = skge_tx_timeout;
3219 dev->watchdog_timeo = TX_WATCHDOG;
3220 dev->poll = skge_poll;
3221 dev->weight = NAPI_WEIGHT;
3222 #ifdef CONFIG_NET_POLL_CONTROLLER
3223 dev->poll_controller = skge_netpoll;
3224 #endif
3225 dev->irq = hw->pdev->irq;
3226 dev->features = NETIF_F_LLTX;
3227 if (highmem)
3228 dev->features |= NETIF_F_HIGHDMA;
3229
3230 skge = netdev_priv(dev);
3231 skge->netdev = dev;
3232 skge->hw = hw;
3233 skge->msg_enable = netif_msg_init(debug, default_msg);
3234 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3235 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3236
3237 /* Auto speed and flow control */
3238 skge->autoneg = AUTONEG_ENABLE;
3239 skge->flow_control = FLOW_MODE_SYMMETRIC;
3240 skge->duplex = -1;
3241 skge->speed = -1;
3242 skge->advertising = skge_supported_modes(hw);
3243
3244 hw->dev[port] = dev;
3245
3246 skge->port = port;
3247
3248 spin_lock_init(&skge->tx_lock);
3249
3250 if (hw->chip_id != CHIP_ID_GENESIS) {
3251 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3252 skge->rx_csum = 1;
3253 }
3254
3255 /* read the mac address */
3256 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3257 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3258
3259 /* device is off until link detection */
3260 netif_carrier_off(dev);
3261 netif_stop_queue(dev);
3262
3263 return dev;
3264 }
3265
3266 static void __devinit skge_show_addr(struct net_device *dev)
3267 {
3268 const struct skge_port *skge = netdev_priv(dev);
3269
3270 if (netif_msg_probe(skge))
3271 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3272 dev->name,
3273 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3274 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3275 }
3276
3277 static int __devinit skge_probe(struct pci_dev *pdev,
3278 const struct pci_device_id *ent)
3279 {
3280 struct net_device *dev, *dev1;
3281 struct skge_hw *hw;
3282 int err, using_dac = 0;
3283
3284 err = pci_enable_device(pdev);
3285 if (err) {
3286 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3287 pci_name(pdev));
3288 goto err_out;
3289 }
3290
3291 err = pci_request_regions(pdev, DRV_NAME);
3292 if (err) {
3293 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3294 pci_name(pdev));
3295 goto err_out_disable_pdev;
3296 }
3297
3298 pci_set_master(pdev);
3299
3300 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3301 using_dac = 1;
3302 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3303 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3304 using_dac = 0;
3305 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3306 }
3307
3308 if (err) {
3309 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3310 pci_name(pdev));
3311 goto err_out_free_regions;
3312 }
3313
3314 #ifdef __BIG_ENDIAN
3315 /* byte swap descriptors in hardware */
3316 {
3317 u32 reg;
3318
3319 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3320 reg |= PCI_REV_DESC;
3321 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3322 }
3323 #endif
3324
3325 err = -ENOMEM;
3326 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3327 if (!hw) {
3328 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3329 pci_name(pdev));
3330 goto err_out_free_regions;
3331 }
3332
3333 hw->pdev = pdev;
3334 mutex_init(&hw->phy_mutex);
3335 INIT_WORK(&hw->phy_work, skge_extirq, hw);
3336
3337 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3338 if (!hw->regs) {
3339 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3340 pci_name(pdev));
3341 goto err_out_free_hw;
3342 }
3343
3344 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, DRV_NAME, hw);
3345 if (err) {
3346 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3347 pci_name(pdev), pdev->irq);
3348 goto err_out_iounmap;
3349 }
3350 pci_set_drvdata(pdev, hw);
3351
3352 err = skge_reset(hw);
3353 if (err)
3354 goto err_out_free_irq;
3355
3356 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3357 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3358 skge_board_name(hw), hw->chip_rev);
3359
3360 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3361 goto err_out_led_off;
3362
3363 if (!is_valid_ether_addr(dev->dev_addr)) {
3364 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3365 pci_name(pdev));
3366 err = -EIO;
3367 goto err_out_free_netdev;
3368 }
3369
3370
3371 err = register_netdev(dev);
3372 if (err) {
3373 printk(KERN_ERR PFX "%s: cannot register net device\n",
3374 pci_name(pdev));
3375 goto err_out_free_netdev;
3376 }
3377
3378 skge_show_addr(dev);
3379
3380 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3381 if (register_netdev(dev1) == 0)
3382 skge_show_addr(dev1);
3383 else {
3384 /* Failure to register second port need not be fatal */
3385 printk(KERN_WARNING PFX "register of second port failed\n");
3386 hw->dev[1] = NULL;
3387 free_netdev(dev1);
3388 }
3389 }
3390
3391 return 0;
3392
3393 err_out_free_netdev:
3394 free_netdev(dev);
3395 err_out_led_off:
3396 skge_write16(hw, B0_LED, LED_STAT_OFF);
3397 err_out_free_irq:
3398 free_irq(pdev->irq, hw);
3399 err_out_iounmap:
3400 iounmap(hw->regs);
3401 err_out_free_hw:
3402 kfree(hw);
3403 err_out_free_regions:
3404 pci_release_regions(pdev);
3405 err_out_disable_pdev:
3406 pci_disable_device(pdev);
3407 pci_set_drvdata(pdev, NULL);
3408 err_out:
3409 return err;
3410 }
3411
3412 static void __devexit skge_remove(struct pci_dev *pdev)
3413 {
3414 struct skge_hw *hw = pci_get_drvdata(pdev);
3415 struct net_device *dev0, *dev1;
3416
3417 if (!hw)
3418 return;
3419
3420 if ((dev1 = hw->dev[1]))
3421 unregister_netdev(dev1);
3422 dev0 = hw->dev[0];
3423 unregister_netdev(dev0);
3424
3425 spin_lock_irq(&hw->hw_lock);
3426 hw->intr_mask = 0;
3427 skge_write32(hw, B0_IMSK, 0);
3428 spin_unlock_irq(&hw->hw_lock);
3429
3430 skge_write16(hw, B0_LED, LED_STAT_OFF);
3431 skge_write8(hw, B0_CTST, CS_RST_SET);
3432
3433 flush_scheduled_work();
3434
3435 free_irq(pdev->irq, hw);
3436 pci_release_regions(pdev);
3437 pci_disable_device(pdev);
3438 if (dev1)
3439 free_netdev(dev1);
3440 free_netdev(dev0);
3441
3442 iounmap(hw->regs);
3443 kfree(hw);
3444 pci_set_drvdata(pdev, NULL);
3445 }
3446
3447 #ifdef CONFIG_PM
3448 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3449 {
3450 struct skge_hw *hw = pci_get_drvdata(pdev);
3451 int i, wol = 0;
3452
3453 for (i = 0; i < 2; i++) {
3454 struct net_device *dev = hw->dev[i];
3455
3456 if (dev) {
3457 struct skge_port *skge = netdev_priv(dev);
3458 if (netif_running(dev)) {
3459 netif_carrier_off(dev);
3460 if (skge->wol)
3461 netif_stop_queue(dev);
3462 else
3463 skge_down(dev);
3464 }
3465 netif_device_detach(dev);
3466 wol |= skge->wol;
3467 }
3468 }
3469
3470 pci_save_state(pdev);
3471 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3472 pci_disable_device(pdev);
3473 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3474
3475 return 0;
3476 }
3477
3478 static int skge_resume(struct pci_dev *pdev)
3479 {
3480 struct skge_hw *hw = pci_get_drvdata(pdev);
3481 int i;
3482
3483 pci_set_power_state(pdev, PCI_D0);
3484 pci_restore_state(pdev);
3485 pci_enable_wake(pdev, PCI_D0, 0);
3486
3487 skge_reset(hw);
3488
3489 for (i = 0; i < 2; i++) {
3490 struct net_device *dev = hw->dev[i];
3491 if (dev) {
3492 netif_device_attach(dev);
3493 if (netif_running(dev) && skge_up(dev))
3494 dev_close(dev);
3495 }
3496 }
3497 return 0;
3498 }
3499 #endif
3500
3501 static struct pci_driver skge_driver = {
3502 .name = DRV_NAME,
3503 .id_table = skge_id_table,
3504 .probe = skge_probe,
3505 .remove = __devexit_p(skge_remove),
3506 #ifdef CONFIG_PM
3507 .suspend = skge_suspend,
3508 .resume = skge_resume,
3509 #endif
3510 };
3511
3512 static int __init skge_init_module(void)
3513 {
3514 return pci_module_init(&skge_driver);
3515 }
3516
3517 static void __exit skge_cleanup_module(void)
3518 {
3519 pci_unregister_driver(&skge_driver);
3520 }
3521
3522 module_init(skge_init_module);
3523 module_exit(skge_cleanup_module);
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