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[PATCH] sky2: phy processing in workqueue rather than tasklet
[mirror_ubuntu-jammy-kernel.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 /*
27 * TOTEST
28 * - speed setting
29 * - suspend/resume
30 */
31
32 #include <linux/config.h>
33 #include <linux/crc32.h>
34 #include <linux/kernel.h>
35 #include <linux/version.h>
36 #include <linux/module.h>
37 #include <linux/netdevice.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/etherdevice.h>
40 #include <linux/ethtool.h>
41 #include <linux/pci.h>
42 #include <linux/ip.h>
43 #include <linux/tcp.h>
44 #include <linux/in.h>
45 #include <linux/delay.h>
46 #include <linux/workqueue.h>
47 #include <linux/if_vlan.h>
48 #include <linux/mii.h>
49
50 #include <asm/irq.h>
51
52 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
53 #define SKY2_VLAN_TAG_USED 1
54 #endif
55
56 #include "sky2.h"
57
58 #define DRV_NAME "sky2"
59 #define DRV_VERSION "0.9"
60 #define PFX DRV_NAME " "
61
62 /*
63 * The Yukon II chipset takes 64 bit command blocks (called list elements)
64 * that are organized into three (receive, transmit, status) different rings
65 * similar to Tigon3. A transmit can require several elements;
66 * a receive requires one (or two if using 64 bit dma).
67 */
68
69 #define is_ec_a1(hw) \
70 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
71 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
72
73 #define RX_LE_SIZE 512
74 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
75 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
76 #define RX_DEF_PENDING RX_MAX_PENDING
77
78 #define TX_RING_SIZE 512
79 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
80 #define TX_MIN_PENDING 64
81 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
82
83 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
84 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
85 #define ETH_JUMBO_MTU 9000
86 #define TX_WATCHDOG (5 * HZ)
87 #define NAPI_WEIGHT 64
88 #define PHY_RETRIES 1000
89
90 static const u32 default_msg =
91 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
92 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
93 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
94
95 static int debug = -1; /* defaults above */
96 module_param(debug, int, 0);
97 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
98
99 static int copybreak __read_mostly = 256;
100 module_param(copybreak, int, 0);
101 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
102
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
123 { 0 }
124 };
125
126 MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
131
132 /* This driver supports yukon2 chipset only */
133 static const char *yukon2_name[] = {
134 "XL", /* 0xb3 */
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
137 "EC", /* 0xb6 */
138 "FE", /* 0xb7 */
139 };
140
141 /* Access to external PHY */
142 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
143 {
144 int i;
145
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
149
150 for (i = 0; i < PHY_RETRIES; i++) {
151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
152 return 0;
153 udelay(1);
154 }
155
156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
157 return -ETIMEDOUT;
158 }
159
160 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
161 {
162 int i;
163
164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
166
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
170 return 0;
171 }
172
173 udelay(1);
174 }
175
176 return -ETIMEDOUT;
177 }
178
179 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
180 {
181 u16 v;
182
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
185 return v;
186 }
187
188 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
189 {
190 u16 power_control;
191 u32 reg1;
192 int vaux;
193 int ret = 0;
194
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
197
198 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
199 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold);
201
202 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
203
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
206
207 switch (state) {
208 case PCI_D0:
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224
225 /* Turn off phy power saving */
226 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
228
229 /* looks like this XL is back asswards .. */
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
232 if (hw->ports > 1)
233 reg1 |= PCI_Y2_PHY2_COMA;
234 }
235 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
236 break;
237
238 case PCI_D3hot:
239 case PCI_D3cold:
240 /* Turn on phy power saving */
241 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
242 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
243 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
244 else
245 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
247
248 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
249 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
250 else
251 /* enable bits are inverted */
252 sky2_write8(hw, B2_Y2_CLK_GATE,
253 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
254 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
255 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
256
257 /* switch power to VAUX */
258 if (vaux && state != PCI_D3cold)
259 sky2_write8(hw, B0_POWER_CTRL,
260 (PC_VAUX_ENA | PC_VCC_ENA |
261 PC_VAUX_ON | PC_VCC_OFF));
262 break;
263 default:
264 printk(KERN_ERR PFX "Unknown power state %d\n", state);
265 ret = -1;
266 }
267
268 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
269 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
270 return ret;
271 }
272
273 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
274 {
275 u16 reg;
276
277 /* disable all GMAC IRQ's */
278 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
279 /* disable PHY IRQs */
280 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
281
282 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
283 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
284 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
285 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
286
287 reg = gma_read16(hw, port, GM_RX_CTRL);
288 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
289 gma_write16(hw, port, GM_RX_CTRL, reg);
290 }
291
292 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
293 {
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
296
297 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
298 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
299
300 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
301 PHY_M_EC_MAC_S_MSK);
302 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
303
304 if (hw->chip_id == CHIP_ID_YUKON_EC)
305 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
306 else
307 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
308
309 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
310 }
311
312 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
313 if (hw->copper) {
314 if (hw->chip_id == CHIP_ID_YUKON_FE) {
315 /* enable automatic crossover */
316 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
317 } else {
318 /* disable energy detect */
319 ctrl &= ~PHY_M_PC_EN_DET_MSK;
320
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
323
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 hw->chip_id == CHIP_ID_YUKON_XL) {
326 ctrl &= ~PHY_M_PC_DSC_MSK;
327 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
328 }
329 }
330 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
331 } else {
332 /* workaround for deviation #4.88 (CRC errors) */
333 /* disable Automatic Crossover */
334
335 ctrl &= ~PHY_M_PC_MDIX_MSK;
336 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
337
338 if (hw->chip_id == CHIP_ID_YUKON_XL) {
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 /* select page 1 to access Fiber registers */
347 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
348 }
349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
352 if (sky2->autoneg == AUTONEG_DISABLE)
353 ctrl &= ~PHY_CT_ANE;
354 else
355 ctrl |= PHY_CT_ANE;
356
357 ctrl |= PHY_CT_RESET;
358 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
359
360 ctrl = 0;
361 ct1000 = 0;
362 adv = PHY_AN_CSMA;
363
364 if (sky2->autoneg == AUTONEG_ENABLE) {
365 if (hw->copper) {
366 if (sky2->advertising & ADVERTISED_1000baseT_Full)
367 ct1000 |= PHY_M_1000C_AFD;
368 if (sky2->advertising & ADVERTISED_1000baseT_Half)
369 ct1000 |= PHY_M_1000C_AHD;
370 if (sky2->advertising & ADVERTISED_100baseT_Full)
371 adv |= PHY_M_AN_100_FD;
372 if (sky2->advertising & ADVERTISED_100baseT_Half)
373 adv |= PHY_M_AN_100_HD;
374 if (sky2->advertising & ADVERTISED_10baseT_Full)
375 adv |= PHY_M_AN_10_FD;
376 if (sky2->advertising & ADVERTISED_10baseT_Half)
377 adv |= PHY_M_AN_10_HD;
378 } else /* special defines for FIBER (88E1011S only) */
379 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
380
381 /* Set Flow-control capabilities */
382 if (sky2->tx_pause && sky2->rx_pause)
383 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
384 else if (sky2->rx_pause && !sky2->tx_pause)
385 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
386 else if (!sky2->rx_pause && sky2->tx_pause)
387 adv |= PHY_AN_PAUSE_ASYM; /* local */
388
389 /* Restart Auto-negotiation */
390 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
391 } else {
392 /* forced speed/duplex settings */
393 ct1000 = PHY_M_1000C_MSE;
394
395 if (sky2->duplex == DUPLEX_FULL)
396 ctrl |= PHY_CT_DUP_MD;
397
398 switch (sky2->speed) {
399 case SPEED_1000:
400 ctrl |= PHY_CT_SP1000;
401 break;
402 case SPEED_100:
403 ctrl |= PHY_CT_SP100;
404 break;
405 }
406
407 ctrl |= PHY_CT_RESET;
408 }
409
410 if (hw->chip_id != CHIP_ID_YUKON_FE)
411 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
412
413 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
414 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
415
416 /* Setup Phy LED's */
417 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
418 ledover = 0;
419
420 switch (hw->chip_id) {
421 case CHIP_ID_YUKON_FE:
422 /* on 88E3082 these bits are at 11..9 (shifted left) */
423 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
424
425 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
426
427 /* delete ACT LED control bits */
428 ctrl &= ~PHY_M_FELP_LED1_MSK;
429 /* change ACT LED control to blink mode */
430 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
431 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
432 break;
433
434 case CHIP_ID_YUKON_XL:
435 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
436
437 /* select page 3 to access LED control register */
438 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
439
440 /* set LED Function Control register */
441 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
442 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
443 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
444 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
445
446 /* set Polarity Control register */
447 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
448 (PHY_M_POLC_LS1_P_MIX(4) |
449 PHY_M_POLC_IS0_P_MIX(4) |
450 PHY_M_POLC_LOS_CTRL(2) |
451 PHY_M_POLC_INIT_CTRL(2) |
452 PHY_M_POLC_STA1_CTRL(2) |
453 PHY_M_POLC_STA0_CTRL(2)));
454
455 /* restore page register */
456 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
457 break;
458
459 default:
460 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
461 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
462 /* turn off the Rx LED (LED_RX) */
463 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
464 }
465
466 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
467
468 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
469 /* turn on 100 Mbps LED (LED_LINK100) */
470 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
471 }
472
473 if (ledover)
474 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
475
476 /* Enable phy interrupt on auto-negotiation complete (or link up) */
477 if (sky2->autoneg == AUTONEG_ENABLE)
478 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
479 else
480 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
481 }
482
483 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
484 {
485 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
486 u16 reg;
487 int i;
488 const u8 *addr = hw->dev[port]->dev_addr;
489
490 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
491 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
492
493 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
494
495 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
496 /* WA DEV_472 -- looks like crossed wires on port 2 */
497 /* clear GMAC 1 Control reset */
498 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
499 do {
500 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
501 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
502 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
503 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
504 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
505 }
506
507 if (sky2->autoneg == AUTONEG_DISABLE) {
508 reg = gma_read16(hw, port, GM_GP_CTRL);
509 reg |= GM_GPCR_AU_ALL_DIS;
510 gma_write16(hw, port, GM_GP_CTRL, reg);
511 gma_read16(hw, port, GM_GP_CTRL);
512
513 switch (sky2->speed) {
514 case SPEED_1000:
515 reg |= GM_GPCR_SPEED_1000;
516 /* fallthru */
517 case SPEED_100:
518 reg |= GM_GPCR_SPEED_100;
519 }
520
521 if (sky2->duplex == DUPLEX_FULL)
522 reg |= GM_GPCR_DUP_FULL;
523 } else
524 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
525
526 if (!sky2->tx_pause && !sky2->rx_pause) {
527 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
528 reg |=
529 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
530 } else if (sky2->tx_pause && !sky2->rx_pause) {
531 /* disable Rx flow-control */
532 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
533 }
534
535 gma_write16(hw, port, GM_GP_CTRL, reg);
536
537 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
538
539 down(&sky2->phy_sema);
540 sky2_phy_init(hw, port);
541 up(&sky2->phy_sema);
542
543 /* MIB clear */
544 reg = gma_read16(hw, port, GM_PHY_ADDR);
545 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
546
547 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
548 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
549 gma_write16(hw, port, GM_PHY_ADDR, reg);
550
551 /* transmit control */
552 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
553
554 /* receive control reg: unicast + multicast + no FCS */
555 gma_write16(hw, port, GM_RX_CTRL,
556 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
557
558 /* transmit flow control */
559 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
560
561 /* transmit parameter */
562 gma_write16(hw, port, GM_TX_PARAM,
563 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
564 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
565 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
566 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
567
568 /* serial mode register */
569 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
570 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
571
572 if (hw->dev[port]->mtu > ETH_DATA_LEN)
573 reg |= GM_SMOD_JUMBO_ENA;
574
575 gma_write16(hw, port, GM_SERIAL_MODE, reg);
576
577 /* virtual address for data */
578 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
579
580 /* physical address: used for pause frames */
581 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
582
583 /* ignore counter overflows */
584 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
585 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
586 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
587
588 /* Configure Rx MAC FIFO */
589 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
590 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
591 GMF_RX_CTRL_DEF);
592
593 /* Flush Rx MAC FIFO on any flow control or error */
594 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
595
596 /* Set threshold to 0xa (64 bytes)
597 * ASF disabled so no need to do WA dev #4.30
598 */
599 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
600
601 /* Configure Tx MAC FIFO */
602 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
603 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
604
605 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
606 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
607 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
608 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
609 /* set Tx GMAC FIFO Almost Empty Threshold */
610 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
611 /* Disable Store & Forward mode for TX */
612 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
613 }
614 }
615
616 }
617
618 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
619 {
620 u32 end;
621
622 start /= 8;
623 len /= 8;
624 end = start + len - 1;
625
626 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
627 sky2_write32(hw, RB_ADDR(q, RB_START), start);
628 sky2_write32(hw, RB_ADDR(q, RB_END), end);
629 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
630 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
631
632 if (q == Q_R1 || q == Q_R2) {
633 u32 rxup, rxlo;
634
635 rxlo = len/2;
636 rxup = rxlo + len/4;
637
638 /* Set thresholds on receive queue's */
639 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
640 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
641 } else {
642 /* Enable store & forward on Tx queue's because
643 * Tx FIFO is only 1K on Yukon
644 */
645 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
646 }
647
648 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
649 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
650 }
651
652 /* Setup Bus Memory Interface */
653 static void sky2_qset(struct sky2_hw *hw, u16 q)
654 {
655 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
656 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
657 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
658 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
659 }
660
661 /* Setup prefetch unit registers. This is the interface between
662 * hardware and driver list elements
663 */
664 static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
665 u64 addr, u32 last)
666 {
667 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
668 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
669 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
670 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
671 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
672 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
673
674 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
675 }
676
677 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
678 {
679 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
680
681 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
682 return le;
683 }
684
685 /*
686 * This is a workaround code taken from SysKonnect sk98lin driver
687 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
688 */
689 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
690 u16 idx, u16 *last, u16 size)
691 {
692 if (is_ec_a1(hw) && idx < *last) {
693 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
694
695 if (hwget == 0) {
696 /* Start prefetching again */
697 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
698 goto setnew;
699 }
700
701 if (hwget == size - 1) {
702 /* set watermark to one list element */
703 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
704
705 /* set put index to first list element */
706 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
707 } else /* have hardware go to end of list */
708 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
709 size - 1);
710 } else {
711 setnew:
712 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
713 }
714 *last = idx;
715 }
716
717
718 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
719 {
720 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
721 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
722 return le;
723 }
724
725 /* Return high part of DMA address (could be 32 or 64 bit) */
726 static inline u32 high32(dma_addr_t a)
727 {
728 return (a >> 16) >> 16;
729 }
730
731 /* Build description to hardware about buffer */
732 static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
733 {
734 struct sky2_rx_le *le;
735 u32 hi = high32(re->mapaddr);
736
737 re->idx = sky2->rx_put;
738 if (sky2->rx_addr64 != hi) {
739 le = sky2_next_rx(sky2);
740 le->addr = cpu_to_le32(hi);
741 le->ctrl = 0;
742 le->opcode = OP_ADDR64 | HW_OWNER;
743 sky2->rx_addr64 = high32(re->mapaddr + re->maplen);
744 }
745
746 le = sky2_next_rx(sky2);
747 le->addr = cpu_to_le32((u32) re->mapaddr);
748 le->length = cpu_to_le16(re->maplen);
749 le->ctrl = 0;
750 le->opcode = OP_PACKET | HW_OWNER;
751 }
752
753
754 /* Tell chip where to start receive checksum.
755 * Actually has two checksums, but set both same to avoid possible byte
756 * order problems.
757 */
758 static void rx_set_checksum(struct sky2_port *sky2)
759 {
760 struct sky2_rx_le *le;
761
762 le = sky2_next_rx(sky2);
763 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
764 le->ctrl = 0;
765 le->opcode = OP_TCPSTART | HW_OWNER;
766
767 sky2_write32(sky2->hw,
768 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
769 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
770
771 }
772
773 /*
774 * The RX Stop command will not work for Yukon-2 if the BMU does not
775 * reach the end of packet and since we can't make sure that we have
776 * incoming data, we must reset the BMU while it is not doing a DMA
777 * transfer. Since it is possible that the RX path is still active,
778 * the RX RAM buffer will be stopped first, so any possible incoming
779 * data will not trigger a DMA. After the RAM buffer is stopped, the
780 * BMU is polled until any DMA in progress is ended and only then it
781 * will be reset.
782 */
783 static void sky2_rx_stop(struct sky2_port *sky2)
784 {
785 struct sky2_hw *hw = sky2->hw;
786 unsigned rxq = rxqaddr[sky2->port];
787 int i;
788
789 /* disable the RAM Buffer receive queue */
790 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
791
792 for (i = 0; i < 0xffff; i++)
793 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
794 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
795 goto stopped;
796
797 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
798 sky2->netdev->name);
799 stopped:
800 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
801
802 /* reset the Rx prefetch unit */
803 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
804 }
805
806 /* Clean out receive buffer area, assumes receiver hardware stopped */
807 static void sky2_rx_clean(struct sky2_port *sky2)
808 {
809 unsigned i;
810
811 memset(sky2->rx_le, 0, RX_LE_BYTES);
812 for (i = 0; i < sky2->rx_pending; i++) {
813 struct ring_info *re = sky2->rx_ring + i;
814
815 if (re->skb) {
816 pci_unmap_single(sky2->hw->pdev,
817 re->mapaddr, re->maplen,
818 PCI_DMA_FROMDEVICE);
819 kfree_skb(re->skb);
820 re->skb = NULL;
821 }
822 }
823 }
824
825 /* Basic MII support */
826 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
827 {
828 struct mii_ioctl_data *data = if_mii(ifr);
829 struct sky2_port *sky2 = netdev_priv(dev);
830 struct sky2_hw *hw = sky2->hw;
831 int err = -EOPNOTSUPP;
832
833 if (!netif_running(dev))
834 return -ENODEV; /* Phy still in reset */
835
836 switch(cmd) {
837 case SIOCGMIIPHY:
838 data->phy_id = PHY_ADDR_MARV;
839
840 /* fallthru */
841 case SIOCGMIIREG: {
842 u16 val = 0;
843
844 down(&sky2->phy_sema);
845 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
846 up(&sky2->phy_sema);
847
848 data->val_out = val;
849 break;
850 }
851
852 case SIOCSMIIREG:
853 if (!capable(CAP_NET_ADMIN))
854 return -EPERM;
855
856 down(&sky2->phy_sema);
857 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
858 data->val_in);
859 up(&sky2->phy_sema);
860 break;
861 }
862 return err;
863 }
864
865 #ifdef SKY2_VLAN_TAG_USED
866 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
867 {
868 struct sky2_port *sky2 = netdev_priv(dev);
869 struct sky2_hw *hw = sky2->hw;
870 u16 port = sky2->port;
871 unsigned long flags;
872
873 spin_lock_irqsave(&sky2->tx_lock, flags);
874
875 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
876 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
877 sky2->vlgrp = grp;
878
879 spin_unlock_irqrestore(&sky2->tx_lock, flags);
880 }
881
882 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
883 {
884 struct sky2_port *sky2 = netdev_priv(dev);
885 struct sky2_hw *hw = sky2->hw;
886 u16 port = sky2->port;
887 unsigned long flags;
888
889 spin_lock_irqsave(&sky2->tx_lock, flags);
890
891 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
892 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
893 if (sky2->vlgrp)
894 sky2->vlgrp->vlan_devices[vid] = NULL;
895
896 spin_unlock_irqrestore(&sky2->tx_lock, flags);
897 }
898 #endif
899
900 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
901 static inline unsigned rx_size(const struct sky2_port *sky2)
902 {
903 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
904 }
905
906 /*
907 * Allocate and setup receiver buffer pool.
908 * In case of 64 bit dma, there are 2X as many list elements
909 * available as ring entries
910 * and need to reserve one list element so we don't wrap around.
911 *
912 * It appears the hardware has a bug in the FIFO logic that
913 * cause it to hang if the FIFO gets overrun and the receive buffer
914 * is not aligned. This means we can't use skb_reserve to align
915 * the IP header.
916 */
917 static int sky2_rx_start(struct sky2_port *sky2)
918 {
919 struct sky2_hw *hw = sky2->hw;
920 unsigned size = rx_size(sky2);
921 unsigned rxq = rxqaddr[sky2->port];
922 int i;
923
924 sky2->rx_put = sky2->rx_next = 0;
925 sky2_qset(hw, rxq);
926 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
927
928 rx_set_checksum(sky2);
929 for (i = 0; i < sky2->rx_pending; i++) {
930 struct ring_info *re = sky2->rx_ring + i;
931
932 re->skb = dev_alloc_skb(size);
933 if (!re->skb)
934 goto nomem;
935
936 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
937 size, PCI_DMA_FROMDEVICE);
938 re->maplen = size;
939 sky2_rx_add(sky2, re);
940 }
941
942 /* Tell chip about available buffers */
943 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
944 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
945 return 0;
946 nomem:
947 sky2_rx_clean(sky2);
948 return -ENOMEM;
949 }
950
951 /* Bring up network interface. */
952 static int sky2_up(struct net_device *dev)
953 {
954 struct sky2_port *sky2 = netdev_priv(dev);
955 struct sky2_hw *hw = sky2->hw;
956 unsigned port = sky2->port;
957 u32 ramsize, rxspace;
958 int err = -ENOMEM;
959
960 if (netif_msg_ifup(sky2))
961 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
962
963 /* must be power of 2 */
964 sky2->tx_le = pci_alloc_consistent(hw->pdev,
965 TX_RING_SIZE *
966 sizeof(struct sky2_tx_le),
967 &sky2->tx_le_map);
968 if (!sky2->tx_le)
969 goto err_out;
970
971 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
972 GFP_KERNEL);
973 if (!sky2->tx_ring)
974 goto err_out;
975 sky2->tx_prod = sky2->tx_cons = 0;
976
977 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
978 &sky2->rx_le_map);
979 if (!sky2->rx_le)
980 goto err_out;
981 memset(sky2->rx_le, 0, RX_LE_BYTES);
982
983 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
984 GFP_KERNEL);
985 if (!sky2->rx_ring)
986 goto err_out;
987
988 sky2_mac_init(hw, port);
989
990 /* Configure RAM buffers */
991 if (hw->chip_id == CHIP_ID_YUKON_FE ||
992 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
993 ramsize = 4096;
994 else {
995 u8 e0 = sky2_read8(hw, B2_E_0);
996 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
997 }
998
999 /* 2/3 for Rx */
1000 rxspace = (2 * ramsize) / 3;
1001 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1002 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1003
1004 /* Make sure SyncQ is disabled */
1005 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1006 RB_RST_SET);
1007
1008 sky2_qset(hw, txqaddr[port]);
1009 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1010 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1011
1012
1013 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1014 TX_RING_SIZE - 1);
1015
1016 err = sky2_rx_start(sky2);
1017 if (err)
1018 goto err_out;
1019
1020 /* Enable interrupts from phy/mac for port */
1021 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1022 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1023 return 0;
1024
1025 err_out:
1026 if (sky2->rx_le)
1027 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1028 sky2->rx_le, sky2->rx_le_map);
1029 if (sky2->tx_le)
1030 pci_free_consistent(hw->pdev,
1031 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1032 sky2->tx_le, sky2->tx_le_map);
1033 if (sky2->tx_ring)
1034 kfree(sky2->tx_ring);
1035 if (sky2->rx_ring)
1036 kfree(sky2->rx_ring);
1037
1038 return err;
1039 }
1040
1041 /* Modular subtraction in ring */
1042 static inline int tx_dist(unsigned tail, unsigned head)
1043 {
1044 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
1045 }
1046
1047 /* Number of list elements available for next tx */
1048 static inline int tx_avail(const struct sky2_port *sky2)
1049 {
1050 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1051 }
1052
1053 /* Estimate of number of transmit list elements required */
1054 static inline unsigned tx_le_req(const struct sk_buff *skb)
1055 {
1056 unsigned count;
1057
1058 count = sizeof(dma_addr_t) / sizeof(u32);
1059 count += skb_shinfo(skb)->nr_frags * count;
1060
1061 if (skb_shinfo(skb)->tso_size)
1062 ++count;
1063
1064 if (skb->ip_summed)
1065 ++count;
1066
1067 return count;
1068 }
1069
1070 /*
1071 * Put one packet in ring for transmit.
1072 * A single packet can generate multiple list elements, and
1073 * the number of ring elements will probably be less than the number
1074 * of list elements used.
1075 */
1076 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1077 {
1078 struct sky2_port *sky2 = netdev_priv(dev);
1079 struct sky2_hw *hw = sky2->hw;
1080 struct sky2_tx_le *le = NULL;
1081 struct ring_info *re;
1082 unsigned long flags;
1083 unsigned i, len;
1084 dma_addr_t mapping;
1085 u32 addr64;
1086 u16 mss;
1087 u8 ctrl;
1088
1089 local_irq_save(flags);
1090 if (!spin_trylock(&sky2->tx_lock)) {
1091 local_irq_restore(flags);
1092 return NETDEV_TX_LOCKED;
1093 }
1094
1095 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1096 netif_stop_queue(dev);
1097 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1098
1099 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1100 dev->name);
1101 return NETDEV_TX_BUSY;
1102 }
1103
1104 if (unlikely(netif_msg_tx_queued(sky2)))
1105 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1106 dev->name, sky2->tx_prod, skb->len);
1107
1108 len = skb_headlen(skb);
1109 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1110 addr64 = high32(mapping);
1111
1112 re = sky2->tx_ring + sky2->tx_prod;
1113
1114 /* Send high bits if changed or crosses boundary */
1115 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1116 le = get_tx_le(sky2);
1117 le->tx.addr = cpu_to_le32(addr64);
1118 le->ctrl = 0;
1119 le->opcode = OP_ADDR64 | HW_OWNER;
1120 sky2->tx_addr64 = high32(mapping + len);
1121 }
1122
1123 /* Check for TCP Segmentation Offload */
1124 mss = skb_shinfo(skb)->tso_size;
1125 if (mss != 0) {
1126 /* just drop the packet if non-linear expansion fails */
1127 if (skb_header_cloned(skb) &&
1128 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1129 dev_kfree_skb_any(skb);
1130 goto out_unlock;
1131 }
1132
1133 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1134 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1135 mss += ETH_HLEN;
1136 }
1137
1138 if (mss != sky2->tx_last_mss) {
1139 le = get_tx_le(sky2);
1140 le->tx.tso.size = cpu_to_le16(mss);
1141 le->tx.tso.rsvd = 0;
1142 le->opcode = OP_LRGLEN | HW_OWNER;
1143 le->ctrl = 0;
1144 sky2->tx_last_mss = mss;
1145 }
1146
1147 ctrl = 0;
1148 #ifdef SKY2_VLAN_TAG_USED
1149 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1150 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1151 if (!le) {
1152 le = get_tx_le(sky2);
1153 le->tx.addr = 0;
1154 le->opcode = OP_VLAN|HW_OWNER;
1155 le->ctrl = 0;
1156 } else
1157 le->opcode |= OP_VLAN;
1158 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1159 ctrl |= INS_VLAN;
1160 }
1161 #endif
1162
1163 /* Handle TCP checksum offload */
1164 if (skb->ip_summed == CHECKSUM_HW) {
1165 u16 hdr = skb->h.raw - skb->data;
1166 u16 offset = hdr + skb->csum;
1167
1168 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1169 if (skb->nh.iph->protocol == IPPROTO_UDP)
1170 ctrl |= UDPTCP;
1171
1172 le = get_tx_le(sky2);
1173 le->tx.csum.start = cpu_to_le16(hdr);
1174 le->tx.csum.offset = cpu_to_le16(offset);
1175 le->length = 0; /* initial checksum value */
1176 le->ctrl = 1; /* one packet */
1177 le->opcode = OP_TCPLISW | HW_OWNER;
1178 }
1179
1180 le = get_tx_le(sky2);
1181 le->tx.addr = cpu_to_le32((u32) mapping);
1182 le->length = cpu_to_le16(len);
1183 le->ctrl = ctrl;
1184 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1185
1186 /* Record the transmit mapping info */
1187 re->skb = skb;
1188 re->mapaddr = mapping;
1189 re->maplen = len;
1190
1191 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1192 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1193 struct ring_info *fre;
1194
1195 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1196 frag->size, PCI_DMA_TODEVICE);
1197 addr64 = (mapping >> 16) >> 16;
1198 if (addr64 != sky2->tx_addr64) {
1199 le = get_tx_le(sky2);
1200 le->tx.addr = cpu_to_le32(addr64);
1201 le->ctrl = 0;
1202 le->opcode = OP_ADDR64 | HW_OWNER;
1203 sky2->tx_addr64 = addr64;
1204 }
1205
1206 le = get_tx_le(sky2);
1207 le->tx.addr = cpu_to_le32((u32) mapping);
1208 le->length = cpu_to_le16(frag->size);
1209 le->ctrl = ctrl;
1210 le->opcode = OP_BUFFER | HW_OWNER;
1211
1212 fre = sky2->tx_ring
1213 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1214 fre->skb = NULL;
1215 fre->mapaddr = mapping;
1216 fre->maplen = frag->size;
1217 }
1218 re->idx = sky2->tx_prod;
1219 le->ctrl |= EOP;
1220
1221 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1222 &sky2->tx_last_put, TX_RING_SIZE);
1223
1224 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1225 netif_stop_queue(dev);
1226
1227 out_unlock:
1228 mmiowb();
1229 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1230
1231 dev->trans_start = jiffies;
1232 return NETDEV_TX_OK;
1233 }
1234
1235 /*
1236 * Free ring elements from starting at tx_cons until "done"
1237 *
1238 * NB: the hardware will tell us about partial completion of multi-part
1239 * buffers; these are deferred until completion.
1240 */
1241 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1242 {
1243 struct net_device *dev = sky2->netdev;
1244 unsigned i;
1245
1246 if (done == sky2->tx_cons)
1247 return;
1248
1249 if (unlikely(netif_msg_tx_done(sky2)))
1250 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1251 dev->name, done);
1252
1253 spin_lock(&sky2->tx_lock);
1254
1255 while (sky2->tx_cons != done) {
1256 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1257 struct sk_buff *skb;
1258
1259 /* Check for partial status */
1260 if (tx_dist(sky2->tx_cons, done)
1261 < tx_dist(sky2->tx_cons, re->idx))
1262 goto out;
1263
1264 skb = re->skb;
1265 pci_unmap_single(sky2->hw->pdev,
1266 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1267
1268 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1269 struct ring_info *fre;
1270 fre =
1271 sky2->tx_ring + (sky2->tx_cons + i +
1272 1) % TX_RING_SIZE;
1273 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1274 fre->maplen, PCI_DMA_TODEVICE);
1275 }
1276
1277 dev_kfree_skb_any(skb);
1278
1279 sky2->tx_cons = re->idx;
1280 }
1281 out:
1282
1283 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1284 netif_wake_queue(dev);
1285 spin_unlock(&sky2->tx_lock);
1286 }
1287
1288 /* Cleanup all untransmitted buffers, assume transmitter not running */
1289 static inline void sky2_tx_clean(struct sky2_port *sky2)
1290 {
1291 sky2_tx_complete(sky2, sky2->tx_prod);
1292 }
1293
1294 /* Network shutdown */
1295 static int sky2_down(struct net_device *dev)
1296 {
1297 struct sky2_port *sky2 = netdev_priv(dev);
1298 struct sky2_hw *hw = sky2->hw;
1299 unsigned port = sky2->port;
1300 u16 ctrl;
1301
1302 if (netif_msg_ifdown(sky2))
1303 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1304
1305 /* Stop more packets from being queued */
1306 netif_stop_queue(dev);
1307
1308 /* Disable port IRQ */
1309 local_irq_disable();
1310 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1311 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1312 local_irq_enable();
1313
1314 flush_scheduled_work();
1315
1316 sky2_phy_reset(hw, port);
1317
1318 /* Stop transmitter */
1319 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1320 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1321
1322 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1323 RB_RST_SET | RB_DIS_OP_MD);
1324
1325 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1326 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1327 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1328
1329 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1330
1331 /* Workaround shared GMAC reset */
1332 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1333 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1334 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1335
1336 /* Disable Force Sync bit and Enable Alloc bit */
1337 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1338 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1339
1340 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1341 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1342 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1343
1344 /* Reset the PCI FIFO of the async Tx queue */
1345 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1346 BMU_RST_SET | BMU_FIFO_RST);
1347
1348 /* Reset the Tx prefetch units */
1349 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1350 PREF_UNIT_RST_SET);
1351
1352 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1353
1354 sky2_rx_stop(sky2);
1355
1356 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1357 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1358
1359 /* turn off LED's */
1360 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1361
1362 synchronize_irq(hw->pdev->irq);
1363
1364 sky2_tx_clean(sky2);
1365 sky2_rx_clean(sky2);
1366
1367 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1368 sky2->rx_le, sky2->rx_le_map);
1369 kfree(sky2->rx_ring);
1370
1371 pci_free_consistent(hw->pdev,
1372 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1373 sky2->tx_le, sky2->tx_le_map);
1374 kfree(sky2->tx_ring);
1375
1376 return 0;
1377 }
1378
1379 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1380 {
1381 if (!hw->copper)
1382 return SPEED_1000;
1383
1384 if (hw->chip_id == CHIP_ID_YUKON_FE)
1385 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1386
1387 switch (aux & PHY_M_PS_SPEED_MSK) {
1388 case PHY_M_PS_SPEED_1000:
1389 return SPEED_1000;
1390 case PHY_M_PS_SPEED_100:
1391 return SPEED_100;
1392 default:
1393 return SPEED_10;
1394 }
1395 }
1396
1397 static void sky2_link_up(struct sky2_port *sky2)
1398 {
1399 struct sky2_hw *hw = sky2->hw;
1400 unsigned port = sky2->port;
1401 u16 reg;
1402
1403 /* Enable Transmit FIFO Underrun */
1404 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1405
1406 reg = gma_read16(hw, port, GM_GP_CTRL);
1407 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1408 reg |= GM_GPCR_DUP_FULL;
1409
1410 /* enable Rx/Tx */
1411 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1412 gma_write16(hw, port, GM_GP_CTRL, reg);
1413 gma_read16(hw, port, GM_GP_CTRL);
1414
1415 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1416
1417 netif_carrier_on(sky2->netdev);
1418 netif_wake_queue(sky2->netdev);
1419
1420 /* Turn on link LED */
1421 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1422 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1423
1424 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1425 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1426
1427 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1428 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1429 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1430 SPEED_10 ? 7 : 0) |
1431 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1432 SPEED_100 ? 7 : 0) |
1433 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1434 SPEED_1000 ? 7 : 0));
1435 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1436 }
1437
1438 if (netif_msg_link(sky2))
1439 printk(KERN_INFO PFX
1440 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1441 sky2->netdev->name, sky2->speed,
1442 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1443 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1444 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1445 }
1446
1447 static void sky2_link_down(struct sky2_port *sky2)
1448 {
1449 struct sky2_hw *hw = sky2->hw;
1450 unsigned port = sky2->port;
1451 u16 reg;
1452
1453 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1454
1455 reg = gma_read16(hw, port, GM_GP_CTRL);
1456 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1457 gma_write16(hw, port, GM_GP_CTRL, reg);
1458 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1459
1460 if (sky2->rx_pause && !sky2->tx_pause) {
1461 /* restore Asymmetric Pause bit */
1462 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1463 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1464 | PHY_M_AN_ASP);
1465 }
1466
1467 sky2_phy_reset(hw, port);
1468
1469 netif_carrier_off(sky2->netdev);
1470 netif_stop_queue(sky2->netdev);
1471
1472 /* Turn on link LED */
1473 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1474
1475 if (netif_msg_link(sky2))
1476 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1477 sky2_phy_init(hw, port);
1478 }
1479
1480 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1481 {
1482 struct sky2_hw *hw = sky2->hw;
1483 unsigned port = sky2->port;
1484 u16 lpa;
1485
1486 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1487
1488 if (lpa & PHY_M_AN_RF) {
1489 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1490 return -1;
1491 }
1492
1493 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1494 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1495 printk(KERN_ERR PFX "%s: master/slave fault",
1496 sky2->netdev->name);
1497 return -1;
1498 }
1499
1500 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1501 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1502 sky2->netdev->name);
1503 return -1;
1504 }
1505
1506 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1507
1508 sky2->speed = sky2_phy_speed(hw, aux);
1509
1510 /* Pause bits are offset (9..8) */
1511 if (hw->chip_id == CHIP_ID_YUKON_XL)
1512 aux >>= 6;
1513
1514 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1515 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1516
1517 if ((sky2->tx_pause || sky2->rx_pause)
1518 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1519 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1520 else
1521 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1522
1523 return 0;
1524 }
1525
1526 /*
1527 * Interrupt from PHY are handled outside of interrupt context
1528 * because accessing phy registers requires spin wait which might
1529 * cause excess interrupt latency.
1530 */
1531 static void sky2_phy_task(void *arg)
1532 {
1533 struct sky2_port *sky2 = arg;
1534 struct sky2_hw *hw = sky2->hw;
1535 u16 istatus, phystat;
1536
1537 down(&sky2->phy_sema);
1538 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1539 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1540
1541 if (netif_msg_intr(sky2))
1542 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1543 sky2->netdev->name, istatus, phystat);
1544
1545 if (istatus & PHY_M_IS_AN_COMPL) {
1546 if (sky2_autoneg_done(sky2, phystat) == 0)
1547 sky2_link_up(sky2);
1548 goto out;
1549 }
1550
1551 if (istatus & PHY_M_IS_LSP_CHANGE)
1552 sky2->speed = sky2_phy_speed(hw, phystat);
1553
1554 if (istatus & PHY_M_IS_DUP_CHANGE)
1555 sky2->duplex =
1556 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1557
1558 if (istatus & PHY_M_IS_LST_CHANGE) {
1559 if (phystat & PHY_M_PS_LINK_UP)
1560 sky2_link_up(sky2);
1561 else
1562 sky2_link_down(sky2);
1563 }
1564 out:
1565 up(&sky2->phy_sema);
1566
1567 local_irq_disable();
1568 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1569 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1570 local_irq_enable();
1571 }
1572
1573 static void sky2_tx_timeout(struct net_device *dev)
1574 {
1575 struct sky2_port *sky2 = netdev_priv(dev);
1576
1577 if (netif_msg_timer(sky2))
1578 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1579
1580 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1581 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1582
1583 sky2_tx_clean(sky2);
1584 }
1585
1586 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1587 {
1588 struct sky2_port *sky2 = netdev_priv(dev);
1589 struct sky2_hw *hw = sky2->hw;
1590 int err;
1591 u16 ctl, mode;
1592
1593 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1594 return -EINVAL;
1595
1596 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1597 return -EINVAL;
1598
1599 if (!netif_running(dev)) {
1600 dev->mtu = new_mtu;
1601 return 0;
1602 }
1603
1604 sky2_write32(hw, B0_IMSK, 0);
1605
1606 dev->trans_start = jiffies; /* prevent tx timeout */
1607 netif_stop_queue(dev);
1608 netif_poll_disable(hw->dev[0]);
1609
1610 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1611 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1612 sky2_rx_stop(sky2);
1613 sky2_rx_clean(sky2);
1614
1615 dev->mtu = new_mtu;
1616 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1617 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1618
1619 if (dev->mtu > ETH_DATA_LEN)
1620 mode |= GM_SMOD_JUMBO_ENA;
1621
1622 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1623
1624 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1625
1626 err = sky2_rx_start(sky2);
1627 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1628
1629 netif_poll_disable(hw->dev[0]);
1630 netif_wake_queue(dev);
1631 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1632
1633 return err;
1634 }
1635
1636 /*
1637 * Receive one packet.
1638 * For small packets or errors, just reuse existing skb.
1639 * For larger packets, get new buffer.
1640 */
1641 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1642 u16 length, u32 status)
1643 {
1644 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1645 struct sk_buff *skb = NULL;
1646 const unsigned int bufsize = rx_size(sky2);
1647
1648 if (unlikely(netif_msg_rx_status(sky2)))
1649 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1650 sky2->netdev->name, sky2->rx_next, status, length);
1651
1652 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1653
1654 if (status & GMR_FS_ANY_ERR)
1655 goto error;
1656
1657 if (!(status & GMR_FS_RX_OK))
1658 goto resubmit;
1659
1660 if (length < copybreak) {
1661 skb = alloc_skb(length + 2, GFP_ATOMIC);
1662 if (!skb)
1663 goto resubmit;
1664
1665 skb_reserve(skb, 2);
1666 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1667 length, PCI_DMA_FROMDEVICE);
1668 memcpy(skb->data, re->skb->data, length);
1669 skb->ip_summed = re->skb->ip_summed;
1670 skb->csum = re->skb->csum;
1671 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1672 length, PCI_DMA_FROMDEVICE);
1673 } else {
1674 struct sk_buff *nskb;
1675
1676 nskb = dev_alloc_skb(bufsize);
1677 if (!nskb)
1678 goto resubmit;
1679
1680 skb = re->skb;
1681 re->skb = nskb;
1682 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1683 re->maplen, PCI_DMA_FROMDEVICE);
1684 prefetch(skb->data);
1685
1686 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1687 bufsize, PCI_DMA_FROMDEVICE);
1688 re->maplen = bufsize;
1689 }
1690
1691 skb_put(skb, length);
1692 resubmit:
1693 re->skb->ip_summed = CHECKSUM_NONE;
1694 sky2_rx_add(sky2, re);
1695
1696 /* Tell receiver about new buffers. */
1697 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1698 &sky2->rx_last_put, RX_LE_SIZE);
1699
1700 return skb;
1701
1702 error:
1703 if (netif_msg_rx_err(sky2))
1704 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1705 sky2->netdev->name, status, length);
1706
1707 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1708 sky2->net_stats.rx_length_errors++;
1709 if (status & GMR_FS_FRAGMENT)
1710 sky2->net_stats.rx_frame_errors++;
1711 if (status & GMR_FS_CRC_ERR)
1712 sky2->net_stats.rx_crc_errors++;
1713 if (status & GMR_FS_RX_FF_OV)
1714 sky2->net_stats.rx_fifo_errors++;
1715
1716 goto resubmit;
1717 }
1718
1719 /*
1720 * Check for transmit complete
1721 */
1722 static inline void sky2_tx_check(struct sky2_hw *hw, int port)
1723 {
1724 struct net_device *dev = hw->dev[port];
1725
1726 if (dev && netif_running(dev)) {
1727 sky2_tx_complete(netdev_priv(dev),
1728 sky2_read16(hw, port == 0
1729 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX));
1730 }
1731 }
1732
1733 /*
1734 * Both ports share the same status interrupt, therefore there is only
1735 * one poll routine.
1736 */
1737 static int sky2_poll(struct net_device *dev0, int *budget)
1738 {
1739 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1740 unsigned int to_do = min(dev0->quota, *budget);
1741 unsigned int work_done = 0;
1742 u16 hwidx;
1743
1744 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1745 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1746 BUG_ON(hwidx >= STATUS_RING_SIZE);
1747 rmb();
1748
1749 while (hwidx != hw->st_idx) {
1750 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1751 struct net_device *dev;
1752 struct sky2_port *sky2;
1753 struct sk_buff *skb;
1754 u32 status;
1755 u16 length;
1756 u8 op;
1757
1758 le = hw->st_le + hw->st_idx;
1759 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1760 prefetch(hw->st_le + hw->st_idx);
1761
1762 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
1763
1764 BUG_ON(le->link >= 2);
1765 dev = hw->dev[le->link];
1766 if (dev == NULL || !netif_running(dev))
1767 continue;
1768
1769 sky2 = netdev_priv(dev);
1770 status = le32_to_cpu(le->status);
1771 length = le16_to_cpu(le->length);
1772 op = le->opcode & ~HW_OWNER;
1773 le->opcode = 0;
1774
1775 switch (op) {
1776 case OP_RXSTAT:
1777 skb = sky2_receive(sky2, length, status);
1778 if (!skb)
1779 break;
1780
1781 skb->dev = dev;
1782 skb->protocol = eth_type_trans(skb, dev);
1783 dev->last_rx = jiffies;
1784
1785 #ifdef SKY2_VLAN_TAG_USED
1786 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1787 vlan_hwaccel_receive_skb(skb,
1788 sky2->vlgrp,
1789 be16_to_cpu(sky2->rx_tag));
1790 } else
1791 #endif
1792 netif_receive_skb(skb);
1793
1794 if (++work_done >= to_do)
1795 goto exit_loop;
1796 break;
1797
1798 #ifdef SKY2_VLAN_TAG_USED
1799 case OP_RXVLAN:
1800 sky2->rx_tag = length;
1801 break;
1802
1803 case OP_RXCHKSVLAN:
1804 sky2->rx_tag = length;
1805 /* fall through */
1806 #endif
1807 case OP_RXCHKS:
1808 skb = sky2->rx_ring[sky2->rx_next].skb;
1809 skb->ip_summed = CHECKSUM_HW;
1810 skb->csum = le16_to_cpu(status);
1811 break;
1812
1813 case OP_TXINDEXLE:
1814 /* pick up transmit status later */
1815 break;
1816
1817 default:
1818 if (net_ratelimit())
1819 printk(KERN_WARNING PFX
1820 "unknown status opcode 0x%x\n", op);
1821 break;
1822 }
1823 }
1824
1825 exit_loop:
1826 sky2_tx_check(hw, 0);
1827 sky2_tx_check(hw, 1);
1828
1829 mmiowb();
1830
1831 if (work_done < to_do) {
1832 /*
1833 * Another chip workaround, need to restart TX timer if status
1834 * LE was handled. WA_DEV_43_418
1835 */
1836 if (is_ec_a1(hw)) {
1837 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1838 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1839 }
1840
1841 netif_rx_complete(dev0);
1842 hw->intr_mask |= Y2_IS_STAT_BMU;
1843 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1844 mmiowb();
1845 return 0;
1846 } else {
1847 *budget -= work_done;
1848 dev0->quota -= work_done;
1849 return 1;
1850 }
1851 }
1852
1853 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1854 {
1855 struct net_device *dev = hw->dev[port];
1856
1857 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1858 dev->name, status);
1859
1860 if (status & Y2_IS_PAR_RD1) {
1861 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1862 dev->name);
1863 /* Clear IRQ */
1864 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1865 }
1866
1867 if (status & Y2_IS_PAR_WR1) {
1868 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1869 dev->name);
1870
1871 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1872 }
1873
1874 if (status & Y2_IS_PAR_MAC1) {
1875 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1876 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1877 }
1878
1879 if (status & Y2_IS_PAR_RX1) {
1880 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1881 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1882 }
1883
1884 if (status & Y2_IS_TCP_TXA1) {
1885 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1886 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1887 }
1888 }
1889
1890 static void sky2_hw_intr(struct sky2_hw *hw)
1891 {
1892 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1893
1894 if (status & Y2_IS_TIST_OV)
1895 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1896
1897 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1898 u16 pci_err;
1899
1900 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1901 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1902 pci_name(hw->pdev), pci_err);
1903
1904 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1905 pci_write_config_word(hw->pdev, PCI_STATUS,
1906 pci_err | PCI_STATUS_ERROR_BITS);
1907 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1908 }
1909
1910 if (status & Y2_IS_PCI_EXP) {
1911 /* PCI-Express uncorrectable Error occurred */
1912 u32 pex_err;
1913
1914 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1915
1916 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1917 pci_name(hw->pdev), pex_err);
1918
1919 /* clear the interrupt */
1920 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1921 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1922 0xffffffffUL);
1923 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1924
1925 if (pex_err & PEX_FATAL_ERRORS) {
1926 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1927 hwmsk &= ~Y2_IS_PCI_EXP;
1928 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1929 }
1930 }
1931
1932 if (status & Y2_HWE_L1_MASK)
1933 sky2_hw_error(hw, 0, status);
1934 status >>= 8;
1935 if (status & Y2_HWE_L1_MASK)
1936 sky2_hw_error(hw, 1, status);
1937 }
1938
1939 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1940 {
1941 struct net_device *dev = hw->dev[port];
1942 struct sky2_port *sky2 = netdev_priv(dev);
1943 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1944
1945 if (netif_msg_intr(sky2))
1946 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1947 dev->name, status);
1948
1949 if (status & GM_IS_RX_FF_OR) {
1950 ++sky2->net_stats.rx_fifo_errors;
1951 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1952 }
1953
1954 if (status & GM_IS_TX_FF_UR) {
1955 ++sky2->net_stats.tx_fifo_errors;
1956 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1957 }
1958 }
1959
1960 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1961 {
1962 struct net_device *dev = hw->dev[port];
1963 struct sky2_port *sky2 = netdev_priv(dev);
1964
1965 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1966 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1967 schedule_work(&sky2->phy_task);
1968 }
1969
1970 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1971 {
1972 struct sky2_hw *hw = dev_id;
1973 struct net_device *dev0 = hw->dev[0];
1974 u32 status;
1975
1976 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1977 if (status == 0 || status == ~0)
1978 return IRQ_NONE;
1979
1980 if (status & Y2_IS_HW_ERR)
1981 sky2_hw_intr(hw);
1982
1983 /* Do NAPI for Rx and Tx status */
1984 if (status & Y2_IS_STAT_BMU) {
1985 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1986 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1987
1988 if (likely(__netif_rx_schedule_prep(dev0))) {
1989 prefetch(&hw->st_le[hw->st_idx]);
1990 __netif_rx_schedule(dev0);
1991 }
1992 }
1993
1994 if (status & Y2_IS_IRQ_PHY1)
1995 sky2_phy_intr(hw, 0);
1996
1997 if (status & Y2_IS_IRQ_PHY2)
1998 sky2_phy_intr(hw, 1);
1999
2000 if (status & Y2_IS_IRQ_MAC1)
2001 sky2_mac_intr(hw, 0);
2002
2003 if (status & Y2_IS_IRQ_MAC2)
2004 sky2_mac_intr(hw, 1);
2005
2006 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2007
2008 sky2_read32(hw, B0_IMSK);
2009
2010 return IRQ_HANDLED;
2011 }
2012
2013 #ifdef CONFIG_NET_POLL_CONTROLLER
2014 static void sky2_netpoll(struct net_device *dev)
2015 {
2016 struct sky2_port *sky2 = netdev_priv(dev);
2017
2018 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2019 }
2020 #endif
2021
2022 /* Chip internal frequency for clock calculations */
2023 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2024 {
2025 switch (hw->chip_id) {
2026 case CHIP_ID_YUKON_EC:
2027 case CHIP_ID_YUKON_EC_U:
2028 return 125; /* 125 Mhz */
2029 case CHIP_ID_YUKON_FE:
2030 return 100; /* 100 Mhz */
2031 default: /* YUKON_XL */
2032 return 156; /* 156 Mhz */
2033 }
2034 }
2035
2036 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2037 {
2038 return sky2_mhz(hw) * us;
2039 }
2040
2041 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2042 {
2043 return clk / sky2_mhz(hw);
2044 }
2045
2046
2047 static int sky2_reset(struct sky2_hw *hw)
2048 {
2049 u32 ctst;
2050 u16 status;
2051 u8 t8, pmd_type;
2052 int i;
2053
2054 ctst = sky2_read32(hw, B0_CTST);
2055
2056 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2057 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2058 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2059 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2060 pci_name(hw->pdev), hw->chip_id);
2061 return -EOPNOTSUPP;
2062 }
2063
2064 /* ring for status responses */
2065 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2066 &hw->st_dma);
2067 if (!hw->st_le)
2068 return -ENOMEM;
2069
2070 /* disable ASF */
2071 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2072 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2073 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2074 }
2075
2076 /* do a SW reset */
2077 sky2_write8(hw, B0_CTST, CS_RST_SET);
2078 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2079
2080 /* clear PCI errors, if any */
2081 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2082 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2083 pci_write_config_word(hw->pdev, PCI_STATUS,
2084 status | PCI_STATUS_ERROR_BITS);
2085
2086 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2087
2088 /* clear any PEX errors */
2089 if (is_pciex(hw)) {
2090 u16 lstat;
2091 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2092 0xffffffffUL);
2093 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
2094 }
2095
2096 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2097 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2098
2099 hw->ports = 1;
2100 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2101 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2102 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2103 ++hw->ports;
2104 }
2105 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2106
2107 sky2_set_power_state(hw, PCI_D0);
2108
2109 for (i = 0; i < hw->ports; i++) {
2110 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2111 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2112 }
2113
2114 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2115
2116 /* Clear I2C IRQ noise */
2117 sky2_write32(hw, B2_I2C_IRQ, 1);
2118
2119 /* turn off hardware timer (unused) */
2120 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2121 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2122
2123 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2124
2125 /* Turn on descriptor polling (every 75us) */
2126 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2127 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2128
2129 /* Turn off receive timestamp */
2130 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2131 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2132
2133 /* enable the Tx Arbiters */
2134 for (i = 0; i < hw->ports; i++)
2135 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2136
2137 /* Initialize ram interface */
2138 for (i = 0; i < hw->ports; i++) {
2139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2140
2141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2144 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2145 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2146 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2147 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2148 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2149 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2150 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2151 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2152 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2153 }
2154
2155 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2156
2157 for (i = 0; i < hw->ports; i++)
2158 sky2_phy_reset(hw, i);
2159
2160 memset(hw->st_le, 0, STATUS_LE_BYTES);
2161 hw->st_idx = 0;
2162
2163 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2164 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2165
2166 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2167 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2168
2169 /* Set the list last index */
2170 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2171
2172 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2173
2174 /* These status setup values are copied from SysKonnect's driver */
2175 if (is_ec_a1(hw)) {
2176 /* WA for dev. #4.3 */
2177 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2178
2179 /* set Status-FIFO watermark */
2180 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2181
2182 /* set Status-FIFO ISR watermark */
2183 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2184
2185 } else {
2186 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2187
2188 /* set Status-FIFO watermark */
2189 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2190
2191 /* set Status-FIFO ISR watermark */
2192 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2193 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2194
2195 else /* WA dev 4.109 */
2196 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2197
2198 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2199 }
2200
2201 /* enable status unit */
2202 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2203
2204 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2205 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2206 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2207
2208 return 0;
2209 }
2210
2211 static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2212 {
2213 u32 modes;
2214 if (hw->copper) {
2215 modes = SUPPORTED_10baseT_Half
2216 | SUPPORTED_10baseT_Full
2217 | SUPPORTED_100baseT_Half
2218 | SUPPORTED_100baseT_Full
2219 | SUPPORTED_Autoneg | SUPPORTED_TP;
2220
2221 if (hw->chip_id != CHIP_ID_YUKON_FE)
2222 modes |= SUPPORTED_1000baseT_Half
2223 | SUPPORTED_1000baseT_Full;
2224 } else
2225 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2226 | SUPPORTED_Autoneg;
2227 return modes;
2228 }
2229
2230 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2231 {
2232 struct sky2_port *sky2 = netdev_priv(dev);
2233 struct sky2_hw *hw = sky2->hw;
2234
2235 ecmd->transceiver = XCVR_INTERNAL;
2236 ecmd->supported = sky2_supported_modes(hw);
2237 ecmd->phy_address = PHY_ADDR_MARV;
2238 if (hw->copper) {
2239 ecmd->supported = SUPPORTED_10baseT_Half
2240 | SUPPORTED_10baseT_Full
2241 | SUPPORTED_100baseT_Half
2242 | SUPPORTED_100baseT_Full
2243 | SUPPORTED_1000baseT_Half
2244 | SUPPORTED_1000baseT_Full
2245 | SUPPORTED_Autoneg | SUPPORTED_TP;
2246 ecmd->port = PORT_TP;
2247 } else
2248 ecmd->port = PORT_FIBRE;
2249
2250 ecmd->advertising = sky2->advertising;
2251 ecmd->autoneg = sky2->autoneg;
2252 ecmd->speed = sky2->speed;
2253 ecmd->duplex = sky2->duplex;
2254 return 0;
2255 }
2256
2257 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2258 {
2259 struct sky2_port *sky2 = netdev_priv(dev);
2260 const struct sky2_hw *hw = sky2->hw;
2261 u32 supported = sky2_supported_modes(hw);
2262
2263 if (ecmd->autoneg == AUTONEG_ENABLE) {
2264 ecmd->advertising = supported;
2265 sky2->duplex = -1;
2266 sky2->speed = -1;
2267 } else {
2268 u32 setting;
2269
2270 switch (ecmd->speed) {
2271 case SPEED_1000:
2272 if (ecmd->duplex == DUPLEX_FULL)
2273 setting = SUPPORTED_1000baseT_Full;
2274 else if (ecmd->duplex == DUPLEX_HALF)
2275 setting = SUPPORTED_1000baseT_Half;
2276 else
2277 return -EINVAL;
2278 break;
2279 case SPEED_100:
2280 if (ecmd->duplex == DUPLEX_FULL)
2281 setting = SUPPORTED_100baseT_Full;
2282 else if (ecmd->duplex == DUPLEX_HALF)
2283 setting = SUPPORTED_100baseT_Half;
2284 else
2285 return -EINVAL;
2286 break;
2287
2288 case SPEED_10:
2289 if (ecmd->duplex == DUPLEX_FULL)
2290 setting = SUPPORTED_10baseT_Full;
2291 else if (ecmd->duplex == DUPLEX_HALF)
2292 setting = SUPPORTED_10baseT_Half;
2293 else
2294 return -EINVAL;
2295 break;
2296 default:
2297 return -EINVAL;
2298 }
2299
2300 if ((setting & supported) == 0)
2301 return -EINVAL;
2302
2303 sky2->speed = ecmd->speed;
2304 sky2->duplex = ecmd->duplex;
2305 }
2306
2307 sky2->autoneg = ecmd->autoneg;
2308 sky2->advertising = ecmd->advertising;
2309
2310 if (netif_running(dev)) {
2311 sky2_down(dev);
2312 sky2_up(dev);
2313 }
2314
2315 return 0;
2316 }
2317
2318 static void sky2_get_drvinfo(struct net_device *dev,
2319 struct ethtool_drvinfo *info)
2320 {
2321 struct sky2_port *sky2 = netdev_priv(dev);
2322
2323 strcpy(info->driver, DRV_NAME);
2324 strcpy(info->version, DRV_VERSION);
2325 strcpy(info->fw_version, "N/A");
2326 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2327 }
2328
2329 static const struct sky2_stat {
2330 char name[ETH_GSTRING_LEN];
2331 u16 offset;
2332 } sky2_stats[] = {
2333 { "tx_bytes", GM_TXO_OK_HI },
2334 { "rx_bytes", GM_RXO_OK_HI },
2335 { "tx_broadcast", GM_TXF_BC_OK },
2336 { "rx_broadcast", GM_RXF_BC_OK },
2337 { "tx_multicast", GM_TXF_MC_OK },
2338 { "rx_multicast", GM_RXF_MC_OK },
2339 { "tx_unicast", GM_TXF_UC_OK },
2340 { "rx_unicast", GM_RXF_UC_OK },
2341 { "tx_mac_pause", GM_TXF_MPAUSE },
2342 { "rx_mac_pause", GM_RXF_MPAUSE },
2343 { "collisions", GM_TXF_SNG_COL },
2344 { "late_collision",GM_TXF_LAT_COL },
2345 { "aborted", GM_TXF_ABO_COL },
2346 { "multi_collisions", GM_TXF_MUL_COL },
2347 { "fifo_underrun", GM_TXE_FIFO_UR },
2348 { "fifo_overflow", GM_RXE_FIFO_OV },
2349 { "rx_toolong", GM_RXF_LNG_ERR },
2350 { "rx_jabber", GM_RXF_JAB_PKT },
2351 { "rx_runt", GM_RXE_FRAG },
2352 { "rx_too_long", GM_RXF_LNG_ERR },
2353 { "rx_fcs_error", GM_RXF_FCS_ERR },
2354 };
2355
2356 static u32 sky2_get_rx_csum(struct net_device *dev)
2357 {
2358 struct sky2_port *sky2 = netdev_priv(dev);
2359
2360 return sky2->rx_csum;
2361 }
2362
2363 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2364 {
2365 struct sky2_port *sky2 = netdev_priv(dev);
2366
2367 sky2->rx_csum = data;
2368
2369 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2370 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2371
2372 return 0;
2373 }
2374
2375 static u32 sky2_get_msglevel(struct net_device *netdev)
2376 {
2377 struct sky2_port *sky2 = netdev_priv(netdev);
2378 return sky2->msg_enable;
2379 }
2380
2381 static int sky2_nway_reset(struct net_device *dev)
2382 {
2383 struct sky2_port *sky2 = netdev_priv(dev);
2384 struct sky2_hw *hw = sky2->hw;
2385
2386 if (sky2->autoneg != AUTONEG_ENABLE)
2387 return -EINVAL;
2388
2389 netif_stop_queue(dev);
2390
2391 down(&sky2->phy_sema);
2392 sky2_phy_reset(hw, sky2->port);
2393 sky2_phy_init(hw, sky2->port);
2394 up(&sky2->phy_sema);
2395
2396 return 0;
2397 }
2398
2399 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2400 {
2401 struct sky2_hw *hw = sky2->hw;
2402 unsigned port = sky2->port;
2403 int i;
2404
2405 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2406 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2407 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2408 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2409
2410 for (i = 2; i < count; i++)
2411 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2412 }
2413
2414 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2415 {
2416 struct sky2_port *sky2 = netdev_priv(netdev);
2417 sky2->msg_enable = value;
2418 }
2419
2420 static int sky2_get_stats_count(struct net_device *dev)
2421 {
2422 return ARRAY_SIZE(sky2_stats);
2423 }
2424
2425 static void sky2_get_ethtool_stats(struct net_device *dev,
2426 struct ethtool_stats *stats, u64 * data)
2427 {
2428 struct sky2_port *sky2 = netdev_priv(dev);
2429
2430 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2431 }
2432
2433 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2434 {
2435 int i;
2436
2437 switch (stringset) {
2438 case ETH_SS_STATS:
2439 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2440 memcpy(data + i * ETH_GSTRING_LEN,
2441 sky2_stats[i].name, ETH_GSTRING_LEN);
2442 break;
2443 }
2444 }
2445
2446 /* Use hardware MIB variables for critical path statistics and
2447 * transmit feedback not reported at interrupt.
2448 * Other errors are accounted for in interrupt handler.
2449 */
2450 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2451 {
2452 struct sky2_port *sky2 = netdev_priv(dev);
2453 u64 data[13];
2454
2455 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2456
2457 sky2->net_stats.tx_bytes = data[0];
2458 sky2->net_stats.rx_bytes = data[1];
2459 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2460 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2461 sky2->net_stats.multicast = data[5] + data[7];
2462 sky2->net_stats.collisions = data[10];
2463 sky2->net_stats.tx_aborted_errors = data[12];
2464
2465 return &sky2->net_stats;
2466 }
2467
2468 static int sky2_set_mac_address(struct net_device *dev, void *p)
2469 {
2470 struct sky2_port *sky2 = netdev_priv(dev);
2471 struct sockaddr *addr = p;
2472 int err = 0;
2473
2474 if (!is_valid_ether_addr(addr->sa_data))
2475 return -EADDRNOTAVAIL;
2476
2477 sky2_down(dev);
2478 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2479 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2480 dev->dev_addr, ETH_ALEN);
2481 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2482 dev->dev_addr, ETH_ALEN);
2483 if (dev->flags & IFF_UP)
2484 err = sky2_up(dev);
2485 return err;
2486 }
2487
2488 static void sky2_set_multicast(struct net_device *dev)
2489 {
2490 struct sky2_port *sky2 = netdev_priv(dev);
2491 struct sky2_hw *hw = sky2->hw;
2492 unsigned port = sky2->port;
2493 struct dev_mc_list *list = dev->mc_list;
2494 u16 reg;
2495 u8 filter[8];
2496
2497 memset(filter, 0, sizeof(filter));
2498
2499 reg = gma_read16(hw, port, GM_RX_CTRL);
2500 reg |= GM_RXCR_UCF_ENA;
2501
2502 if (dev->flags & IFF_PROMISC) /* promiscuous */
2503 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2504 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2505 memset(filter, 0xff, sizeof(filter));
2506 else if (dev->mc_count == 0) /* no multicast */
2507 reg &= ~GM_RXCR_MCF_ENA;
2508 else {
2509 int i;
2510 reg |= GM_RXCR_MCF_ENA;
2511
2512 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2513 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2514 filter[bit / 8] |= 1 << (bit % 8);
2515 }
2516 }
2517
2518 gma_write16(hw, port, GM_MC_ADDR_H1,
2519 (u16) filter[0] | ((u16) filter[1] << 8));
2520 gma_write16(hw, port, GM_MC_ADDR_H2,
2521 (u16) filter[2] | ((u16) filter[3] << 8));
2522 gma_write16(hw, port, GM_MC_ADDR_H3,
2523 (u16) filter[4] | ((u16) filter[5] << 8));
2524 gma_write16(hw, port, GM_MC_ADDR_H4,
2525 (u16) filter[6] | ((u16) filter[7] << 8));
2526
2527 gma_write16(hw, port, GM_RX_CTRL, reg);
2528 }
2529
2530 /* Can have one global because blinking is controlled by
2531 * ethtool and that is always under RTNL mutex
2532 */
2533 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2534 {
2535 u16 pg;
2536
2537 switch (hw->chip_id) {
2538 case CHIP_ID_YUKON_XL:
2539 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2541 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2542 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2543 PHY_M_LEDC_INIT_CTRL(7) |
2544 PHY_M_LEDC_STA1_CTRL(7) |
2545 PHY_M_LEDC_STA0_CTRL(7))
2546 : 0);
2547
2548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2549 break;
2550
2551 default:
2552 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2553 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2554 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2555 PHY_M_LED_MO_10(MO_LED_ON) |
2556 PHY_M_LED_MO_100(MO_LED_ON) |
2557 PHY_M_LED_MO_1000(MO_LED_ON) |
2558 PHY_M_LED_MO_RX(MO_LED_ON)
2559 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2560 PHY_M_LED_MO_10(MO_LED_OFF) |
2561 PHY_M_LED_MO_100(MO_LED_OFF) |
2562 PHY_M_LED_MO_1000(MO_LED_OFF) |
2563 PHY_M_LED_MO_RX(MO_LED_OFF));
2564
2565 }
2566 }
2567
2568 /* blink LED's for finding board */
2569 static int sky2_phys_id(struct net_device *dev, u32 data)
2570 {
2571 struct sky2_port *sky2 = netdev_priv(dev);
2572 struct sky2_hw *hw = sky2->hw;
2573 unsigned port = sky2->port;
2574 u16 ledctrl, ledover = 0;
2575 long ms;
2576 int interrupted;
2577 int onoff = 1;
2578
2579 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2580 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2581 else
2582 ms = data * 1000;
2583
2584 /* save initial values */
2585 down(&sky2->phy_sema);
2586 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2587 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2589 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2591 } else {
2592 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2593 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2594 }
2595
2596 interrupted = 0;
2597 while (!interrupted && ms > 0) {
2598 sky2_led(hw, port, onoff);
2599 onoff = !onoff;
2600
2601 up(&sky2->phy_sema);
2602 interrupted = msleep_interruptible(250);
2603 down(&sky2->phy_sema);
2604
2605 ms -= 250;
2606 }
2607
2608 /* resume regularly scheduled programming */
2609 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2610 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2612 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2613 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2614 } else {
2615 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2616 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2617 }
2618 up(&sky2->phy_sema);
2619
2620 return 0;
2621 }
2622
2623 static void sky2_get_pauseparam(struct net_device *dev,
2624 struct ethtool_pauseparam *ecmd)
2625 {
2626 struct sky2_port *sky2 = netdev_priv(dev);
2627
2628 ecmd->tx_pause = sky2->tx_pause;
2629 ecmd->rx_pause = sky2->rx_pause;
2630 ecmd->autoneg = sky2->autoneg;
2631 }
2632
2633 static int sky2_set_pauseparam(struct net_device *dev,
2634 struct ethtool_pauseparam *ecmd)
2635 {
2636 struct sky2_port *sky2 = netdev_priv(dev);
2637 int err = 0;
2638
2639 sky2->autoneg = ecmd->autoneg;
2640 sky2->tx_pause = ecmd->tx_pause != 0;
2641 sky2->rx_pause = ecmd->rx_pause != 0;
2642
2643 if (netif_running(dev)) {
2644 sky2_down(dev);
2645 err = sky2_up(dev);
2646 }
2647
2648 return err;
2649 }
2650
2651 #ifdef CONFIG_PM
2652 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2653 {
2654 struct sky2_port *sky2 = netdev_priv(dev);
2655
2656 wol->supported = WAKE_MAGIC;
2657 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2658 }
2659
2660 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2661 {
2662 struct sky2_port *sky2 = netdev_priv(dev);
2663 struct sky2_hw *hw = sky2->hw;
2664
2665 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2666 return -EOPNOTSUPP;
2667
2668 sky2->wol = wol->wolopts == WAKE_MAGIC;
2669
2670 if (sky2->wol) {
2671 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2672
2673 sky2_write16(hw, WOL_CTRL_STAT,
2674 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2675 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2676 } else
2677 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2678
2679 return 0;
2680 }
2681 #endif
2682
2683 static int sky2_get_coalesce(struct net_device *dev,
2684 struct ethtool_coalesce *ecmd)
2685 {
2686 struct sky2_port *sky2 = netdev_priv(dev);
2687 struct sky2_hw *hw = sky2->hw;
2688
2689 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2690 ecmd->tx_coalesce_usecs = 0;
2691 else {
2692 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2693 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2694 }
2695 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2696
2697 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2698 ecmd->rx_coalesce_usecs = 0;
2699 else {
2700 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2701 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2702 }
2703 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2704
2705 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2706 ecmd->rx_coalesce_usecs_irq = 0;
2707 else {
2708 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2709 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2710 }
2711
2712 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2713
2714 return 0;
2715 }
2716
2717 /* Note: this affect both ports */
2718 static int sky2_set_coalesce(struct net_device *dev,
2719 struct ethtool_coalesce *ecmd)
2720 {
2721 struct sky2_port *sky2 = netdev_priv(dev);
2722 struct sky2_hw *hw = sky2->hw;
2723 const u32 tmin = sky2_clk2us(hw, 1);
2724 const u32 tmax = 5000;
2725
2726 if (ecmd->tx_coalesce_usecs != 0 &&
2727 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2728 return -EINVAL;
2729
2730 if (ecmd->rx_coalesce_usecs != 0 &&
2731 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2732 return -EINVAL;
2733
2734 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2735 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2736 return -EINVAL;
2737
2738 if (ecmd->tx_max_coalesced_frames > 0xffff)
2739 return -EINVAL;
2740 if (ecmd->rx_max_coalesced_frames > 0xff)
2741 return -EINVAL;
2742 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2743 return -EINVAL;
2744
2745 if (ecmd->tx_coalesce_usecs == 0)
2746 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2747 else {
2748 sky2_write32(hw, STAT_TX_TIMER_INI,
2749 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2750 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2751 }
2752 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2753
2754 if (ecmd->rx_coalesce_usecs == 0)
2755 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2756 else {
2757 sky2_write32(hw, STAT_LEV_TIMER_INI,
2758 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2759 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2760 }
2761 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2762
2763 if (ecmd->rx_coalesce_usecs_irq == 0)
2764 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2765 else {
2766 sky2_write32(hw, STAT_TX_TIMER_INI,
2767 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2768 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2769 }
2770 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2771 return 0;
2772 }
2773
2774 static void sky2_get_ringparam(struct net_device *dev,
2775 struct ethtool_ringparam *ering)
2776 {
2777 struct sky2_port *sky2 = netdev_priv(dev);
2778
2779 ering->rx_max_pending = RX_MAX_PENDING;
2780 ering->rx_mini_max_pending = 0;
2781 ering->rx_jumbo_max_pending = 0;
2782 ering->tx_max_pending = TX_RING_SIZE - 1;
2783
2784 ering->rx_pending = sky2->rx_pending;
2785 ering->rx_mini_pending = 0;
2786 ering->rx_jumbo_pending = 0;
2787 ering->tx_pending = sky2->tx_pending;
2788 }
2789
2790 static int sky2_set_ringparam(struct net_device *dev,
2791 struct ethtool_ringparam *ering)
2792 {
2793 struct sky2_port *sky2 = netdev_priv(dev);
2794 int err = 0;
2795
2796 if (ering->rx_pending > RX_MAX_PENDING ||
2797 ering->rx_pending < 8 ||
2798 ering->tx_pending < MAX_SKB_TX_LE ||
2799 ering->tx_pending > TX_RING_SIZE - 1)
2800 return -EINVAL;
2801
2802 if (netif_running(dev))
2803 sky2_down(dev);
2804
2805 sky2->rx_pending = ering->rx_pending;
2806 sky2->tx_pending = ering->tx_pending;
2807
2808 if (netif_running(dev))
2809 err = sky2_up(dev);
2810
2811 return err;
2812 }
2813
2814 static int sky2_get_regs_len(struct net_device *dev)
2815 {
2816 return 0x4000;
2817 }
2818
2819 /*
2820 * Returns copy of control register region
2821 * Note: access to the RAM address register set will cause timeouts.
2822 */
2823 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2824 void *p)
2825 {
2826 const struct sky2_port *sky2 = netdev_priv(dev);
2827 const void __iomem *io = sky2->hw->regs;
2828
2829 BUG_ON(regs->len < B3_RI_WTO_R1);
2830 regs->version = 1;
2831 memset(p, 0, regs->len);
2832
2833 memcpy_fromio(p, io, B3_RAM_ADDR);
2834
2835 memcpy_fromio(p + B3_RI_WTO_R1,
2836 io + B3_RI_WTO_R1,
2837 regs->len - B3_RI_WTO_R1);
2838 }
2839
2840 static struct ethtool_ops sky2_ethtool_ops = {
2841 .get_settings = sky2_get_settings,
2842 .set_settings = sky2_set_settings,
2843 .get_drvinfo = sky2_get_drvinfo,
2844 .get_msglevel = sky2_get_msglevel,
2845 .set_msglevel = sky2_set_msglevel,
2846 .nway_reset = sky2_nway_reset,
2847 .get_regs_len = sky2_get_regs_len,
2848 .get_regs = sky2_get_regs,
2849 .get_link = ethtool_op_get_link,
2850 .get_sg = ethtool_op_get_sg,
2851 .set_sg = ethtool_op_set_sg,
2852 .get_tx_csum = ethtool_op_get_tx_csum,
2853 .set_tx_csum = ethtool_op_set_tx_csum,
2854 .get_tso = ethtool_op_get_tso,
2855 .set_tso = ethtool_op_set_tso,
2856 .get_rx_csum = sky2_get_rx_csum,
2857 .set_rx_csum = sky2_set_rx_csum,
2858 .get_strings = sky2_get_strings,
2859 .get_coalesce = sky2_get_coalesce,
2860 .set_coalesce = sky2_set_coalesce,
2861 .get_ringparam = sky2_get_ringparam,
2862 .set_ringparam = sky2_set_ringparam,
2863 .get_pauseparam = sky2_get_pauseparam,
2864 .set_pauseparam = sky2_set_pauseparam,
2865 #ifdef CONFIG_PM
2866 .get_wol = sky2_get_wol,
2867 .set_wol = sky2_set_wol,
2868 #endif
2869 .phys_id = sky2_phys_id,
2870 .get_stats_count = sky2_get_stats_count,
2871 .get_ethtool_stats = sky2_get_ethtool_stats,
2872 .get_perm_addr = ethtool_op_get_perm_addr,
2873 };
2874
2875 /* Initialize network device */
2876 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2877 unsigned port, int highmem)
2878 {
2879 struct sky2_port *sky2;
2880 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2881
2882 if (!dev) {
2883 printk(KERN_ERR "sky2 etherdev alloc failed");
2884 return NULL;
2885 }
2886
2887 SET_MODULE_OWNER(dev);
2888 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2889 dev->irq = hw->pdev->irq;
2890 dev->open = sky2_up;
2891 dev->stop = sky2_down;
2892 dev->do_ioctl = sky2_ioctl;
2893 dev->hard_start_xmit = sky2_xmit_frame;
2894 dev->get_stats = sky2_get_stats;
2895 dev->set_multicast_list = sky2_set_multicast;
2896 dev->set_mac_address = sky2_set_mac_address;
2897 dev->change_mtu = sky2_change_mtu;
2898 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2899 dev->tx_timeout = sky2_tx_timeout;
2900 dev->watchdog_timeo = TX_WATCHDOG;
2901 if (port == 0)
2902 dev->poll = sky2_poll;
2903 dev->weight = NAPI_WEIGHT;
2904 #ifdef CONFIG_NET_POLL_CONTROLLER
2905 dev->poll_controller = sky2_netpoll;
2906 #endif
2907
2908 sky2 = netdev_priv(dev);
2909 sky2->netdev = dev;
2910 sky2->hw = hw;
2911 sky2->msg_enable = netif_msg_init(debug, default_msg);
2912
2913 spin_lock_init(&sky2->tx_lock);
2914 /* Auto speed and flow control */
2915 sky2->autoneg = AUTONEG_ENABLE;
2916 sky2->tx_pause = 0;
2917 sky2->rx_pause = 1;
2918 sky2->duplex = -1;
2919 sky2->speed = -1;
2920 sky2->advertising = sky2_supported_modes(hw);
2921 sky2->rx_csum = 1;
2922 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
2923 init_MUTEX(&sky2->phy_sema);
2924 sky2->tx_pending = TX_DEF_PENDING;
2925 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2926
2927 hw->dev[port] = dev;
2928
2929 sky2->port = port;
2930
2931 dev->features |= NETIF_F_LLTX;
2932 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2933 dev->features |= NETIF_F_TSO;
2934 if (highmem)
2935 dev->features |= NETIF_F_HIGHDMA;
2936 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2937
2938 #ifdef SKY2_VLAN_TAG_USED
2939 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2940 dev->vlan_rx_register = sky2_vlan_rx_register;
2941 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2942 #endif
2943
2944 /* read the mac address */
2945 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2946 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2947
2948 /* device is off until link detection */
2949 netif_carrier_off(dev);
2950 netif_stop_queue(dev);
2951
2952 return dev;
2953 }
2954
2955 static inline void sky2_show_addr(struct net_device *dev)
2956 {
2957 const struct sky2_port *sky2 = netdev_priv(dev);
2958
2959 if (netif_msg_probe(sky2))
2960 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2961 dev->name,
2962 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2963 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2964 }
2965
2966 static int __devinit sky2_probe(struct pci_dev *pdev,
2967 const struct pci_device_id *ent)
2968 {
2969 struct net_device *dev, *dev1 = NULL;
2970 struct sky2_hw *hw;
2971 int err, pm_cap, using_dac = 0;
2972
2973 err = pci_enable_device(pdev);
2974 if (err) {
2975 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2976 pci_name(pdev));
2977 goto err_out;
2978 }
2979
2980 err = pci_request_regions(pdev, DRV_NAME);
2981 if (err) {
2982 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2983 pci_name(pdev));
2984 goto err_out;
2985 }
2986
2987 pci_set_master(pdev);
2988
2989 /* Find power-management capability. */
2990 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2991 if (pm_cap == 0) {
2992 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2993 "aborting.\n");
2994 err = -EIO;
2995 goto err_out_free_regions;
2996 }
2997
2998 if (sizeof(dma_addr_t) > sizeof(u32)) {
2999 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3000 if (!err)
3001 using_dac = 1;
3002 }
3003
3004 if (!using_dac) {
3005 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3006 if (err) {
3007 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3008 pci_name(pdev));
3009 goto err_out_free_regions;
3010 }
3011 }
3012 #ifdef __BIG_ENDIAN
3013 /* byte swap descriptors in hardware */
3014 {
3015 u32 reg;
3016
3017 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3018 reg |= PCI_REV_DESC;
3019 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3020 }
3021 #endif
3022
3023 err = -ENOMEM;
3024 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3025 if (!hw) {
3026 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3027 pci_name(pdev));
3028 goto err_out_free_regions;
3029 }
3030
3031 memset(hw, 0, sizeof(*hw));
3032 hw->pdev = pdev;
3033
3034 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3035 if (!hw->regs) {
3036 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3037 pci_name(pdev));
3038 goto err_out_free_hw;
3039 }
3040 hw->pm_cap = pm_cap;
3041
3042 err = sky2_reset(hw);
3043 if (err)
3044 goto err_out_iounmap;
3045
3046 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3047 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3048 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3049 hw->chip_id, hw->chip_rev);
3050
3051 dev = sky2_init_netdev(hw, 0, using_dac);
3052 if (!dev)
3053 goto err_out_free_pci;
3054
3055 err = register_netdev(dev);
3056 if (err) {
3057 printk(KERN_ERR PFX "%s: cannot register net device\n",
3058 pci_name(pdev));
3059 goto err_out_free_netdev;
3060 }
3061
3062 sky2_show_addr(dev);
3063
3064 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3065 if (register_netdev(dev1) == 0)
3066 sky2_show_addr(dev1);
3067 else {
3068 /* Failure to register second port need not be fatal */
3069 printk(KERN_WARNING PFX
3070 "register of second port failed\n");
3071 hw->dev[1] = NULL;
3072 free_netdev(dev1);
3073 }
3074 }
3075
3076 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3077 if (err) {
3078 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3079 pci_name(pdev), pdev->irq);
3080 goto err_out_unregister;
3081 }
3082
3083 hw->intr_mask = Y2_IS_BASE;
3084 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3085
3086 pci_set_drvdata(pdev, hw);
3087
3088 return 0;
3089
3090 err_out_unregister:
3091 if (dev1) {
3092 unregister_netdev(dev1);
3093 free_netdev(dev1);
3094 }
3095 unregister_netdev(dev);
3096 err_out_free_netdev:
3097 free_netdev(dev);
3098 err_out_free_pci:
3099 sky2_write8(hw, B0_CTST, CS_RST_SET);
3100 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3101 err_out_iounmap:
3102 iounmap(hw->regs);
3103 err_out_free_hw:
3104 kfree(hw);
3105 err_out_free_regions:
3106 pci_release_regions(pdev);
3107 pci_disable_device(pdev);
3108 err_out:
3109 return err;
3110 }
3111
3112 static void __devexit sky2_remove(struct pci_dev *pdev)
3113 {
3114 struct sky2_hw *hw = pci_get_drvdata(pdev);
3115 struct net_device *dev0, *dev1;
3116
3117 if (!hw)
3118 return;
3119
3120 dev0 = hw->dev[0];
3121 dev1 = hw->dev[1];
3122 if (dev1)
3123 unregister_netdev(dev1);
3124 unregister_netdev(dev0);
3125
3126 sky2_write32(hw, B0_IMSK, 0);
3127 sky2_set_power_state(hw, PCI_D3hot);
3128 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3129 sky2_write8(hw, B0_CTST, CS_RST_SET);
3130 sky2_read8(hw, B0_CTST);
3131
3132 free_irq(pdev->irq, hw);
3133 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3134 pci_release_regions(pdev);
3135 pci_disable_device(pdev);
3136
3137 if (dev1)
3138 free_netdev(dev1);
3139 free_netdev(dev0);
3140 iounmap(hw->regs);
3141 kfree(hw);
3142
3143 pci_set_drvdata(pdev, NULL);
3144 }
3145
3146 #ifdef CONFIG_PM
3147 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3148 {
3149 struct sky2_hw *hw = pci_get_drvdata(pdev);
3150 int i;
3151
3152 for (i = 0; i < 2; i++) {
3153 struct net_device *dev = hw->dev[i];
3154
3155 if (dev) {
3156 if (!netif_running(dev))
3157 continue;
3158
3159 sky2_down(dev);
3160 netif_device_detach(dev);
3161 }
3162 }
3163
3164 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3165 }
3166
3167 static int sky2_resume(struct pci_dev *pdev)
3168 {
3169 struct sky2_hw *hw = pci_get_drvdata(pdev);
3170 int i;
3171
3172 pci_restore_state(pdev);
3173 pci_enable_wake(pdev, PCI_D0, 0);
3174 sky2_set_power_state(hw, PCI_D0);
3175
3176 sky2_reset(hw);
3177
3178 for (i = 0; i < 2; i++) {
3179 struct net_device *dev = hw->dev[i];
3180 if (dev) {
3181 if (netif_running(dev)) {
3182 netif_device_attach(dev);
3183 sky2_up(dev);
3184 }
3185 }
3186 }
3187 return 0;
3188 }
3189 #endif
3190
3191 static struct pci_driver sky2_driver = {
3192 .name = DRV_NAME,
3193 .id_table = sky2_id_table,
3194 .probe = sky2_probe,
3195 .remove = __devexit_p(sky2_remove),
3196 #ifdef CONFIG_PM
3197 .suspend = sky2_suspend,
3198 .resume = sky2_resume,
3199 #endif
3200 };
3201
3202 static int __init sky2_init_module(void)
3203 {
3204 return pci_register_driver(&sky2_driver);
3205 }
3206
3207 static void __exit sky2_cleanup_module(void)
3208 {
3209 pci_unregister_driver(&sky2_driver);
3210 }
3211
3212 module_init(sky2_init_module);
3213 module_exit(sky2_cleanup_module);
3214
3215 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3216 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3217 MODULE_LICENSE("GPL");
3218 MODULE_VERSION(DRV_VERSION);
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