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sky2: put PHY in sleep when down
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.21"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { 0 }
140 };
141
142 MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144 /* Avoid conditionals by using array */
145 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
148
149 /* This driver supports yukon2 chipset only */
150 static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
153 "Extreme", /* 0xb5 */
154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
156 "FE+", /* 0xb8 */
157 "Supreme", /* 0xb9 */
158 };
159
160 static void sky2_set_multicast(struct net_device *dev);
161
162 /* Access to PHY via serial interconnect */
163 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
164 {
165 int i;
166
167 gma_write16(hw, port, GM_SMI_DATA, val);
168 gma_write16(hw, port, GM_SMI_CTRL,
169 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
170
171 for (i = 0; i < PHY_RETRIES; i++) {
172 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
173 if (ctrl == 0xffff)
174 goto io_error;
175
176 if (!(ctrl & GM_SMI_CT_BUSY))
177 return 0;
178
179 udelay(10);
180 }
181
182 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
183 return -ETIMEDOUT;
184
185 io_error:
186 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
187 return -EIO;
188 }
189
190 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
191 {
192 int i;
193
194 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
195 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
196
197 for (i = 0; i < PHY_RETRIES; i++) {
198 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
199 if (ctrl == 0xffff)
200 goto io_error;
201
202 if (ctrl & GM_SMI_CT_RD_VAL) {
203 *val = gma_read16(hw, port, GM_SMI_DATA);
204 return 0;
205 }
206
207 udelay(10);
208 }
209
210 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
211 return -ETIMEDOUT;
212 io_error:
213 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
214 return -EIO;
215 }
216
217 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
218 {
219 u16 v;
220 __gm_phy_read(hw, port, reg, &v);
221 return v;
222 }
223
224
225 static void sky2_power_on(struct sky2_hw *hw)
226 {
227 /* switch power to VCC (WA for VAUX problem) */
228 sky2_write8(hw, B0_POWER_CTRL,
229 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
230
231 /* disable Core Clock Division, */
232 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
233
234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240 else
241 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
242
243 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
244 u32 reg;
245
246 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
247
248 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
249 /* set all bits to 0 except bits 15..12 and 8 */
250 reg &= P_ASPM_CONTROL_MSK;
251 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
252
253 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
254 /* set all bits to 0 except bits 28 & 27 */
255 reg &= P_CTL_TIM_VMAIN_AV_MSK;
256 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
257
258 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
259
260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 reg = sky2_read32(hw, B2_GP_IO);
262 reg |= GLB_GPIO_STAT_RACE_DIS;
263 sky2_write32(hw, B2_GP_IO, reg);
264
265 sky2_read32(hw, B2_GP_IO);
266 }
267 }
268
269 static void sky2_power_aux(struct sky2_hw *hw)
270 {
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
280 /* switch power to VAUX */
281 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
285 }
286
287 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
288 {
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
293
294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302 }
303
304 /* flow control to advertise bits */
305 static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310 };
311
312 /* flow control to advertise bits when using 1000BaseX */
313 static const u16 fiber_fc_adv[] = {
314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
318 };
319
320 /* flow control to GMA disable bits */
321 static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326 };
327
328
329 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330 {
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
333
334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
339 PHY_M_EC_MAC_S_MSK);
340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
343 if (hw->chip_id == CHIP_ID_YUKON_EC)
344 /* set downshift counter to 3x and enable downshift */
345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 if (sky2_is_copper(hw)) {
355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
375 /* downshift on PHY 88E1112 and 88E1149 is changed */
376 if (sky2->autoneg == AUTONEG_ENABLE
377 && (hw->flags & SKY2_HW_NEWER_PHY)) {
378 /* set downshift counter to 3x and enable downshift */
379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
388 }
389
390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
395
396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
411 }
412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
414 }
415
416 ctrl = PHY_CT_RESET;
417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
419 reg = 0;
420
421 if (sky2->autoneg == AUTONEG_ENABLE) {
422 if (sky2_is_copper(hw)) {
423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
435
436 adv |= copper_fc_adv[sky2->flow_mode];
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
442
443 adv |= fiber_fc_adv[sky2->flow_mode];
444 }
445
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 } else {
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
451
452 /* Disable auto update for duplex flow control and speed */
453 reg |= GM_GPCR_AU_ALL_DIS;
454
455 switch (sky2->speed) {
456 case SPEED_1000:
457 ctrl |= PHY_CT_SP1000;
458 reg |= GM_GPCR_SPEED_1000;
459 break;
460 case SPEED_100:
461 ctrl |= PHY_CT_SP100;
462 reg |= GM_GPCR_SPEED_100;
463 break;
464 }
465
466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
471
472
473 reg |= gm_fc_disable[sky2->flow_mode];
474
475 /* Forward pause packets to GMAC? */
476 if (sky2->flow_mode & FC_RX)
477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
478 else
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
480 }
481
482 gma_write16(hw, port, GM_GP_CTRL, reg);
483
484 if (hw->flags & SKY2_HW_GIGABIT)
485 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
486
487 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
488 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
489
490 /* Setup Phy LED's */
491 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
492 ledover = 0;
493
494 switch (hw->chip_id) {
495 case CHIP_ID_YUKON_FE:
496 /* on 88E3082 these bits are at 11..9 (shifted left) */
497 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
498
499 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
500
501 /* delete ACT LED control bits */
502 ctrl &= ~PHY_M_FELP_LED1_MSK;
503 /* change ACT LED control to blink mode */
504 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
506 break;
507
508 case CHIP_ID_YUKON_FE_P:
509 /* Enable Link Partner Next Page */
510 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
511 ctrl |= PHY_M_PC_ENA_LIP_NP;
512
513 /* disable Energy Detect and enable scrambler */
514 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
516
517 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
518 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
519 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
520 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
521
522 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
523 break;
524
525 case CHIP_ID_YUKON_XL:
526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
527
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
530
531 /* set LED Function Control register */
532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
537
538 /* set Polarity Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
540 (PHY_M_POLC_LS1_P_MIX(4) |
541 PHY_M_POLC_IS0_P_MIX(4) |
542 PHY_M_POLC_LOS_CTRL(2) |
543 PHY_M_POLC_INIT_CTRL(2) |
544 PHY_M_POLC_STA1_CTRL(2) |
545 PHY_M_POLC_STA0_CTRL(2)));
546
547 /* restore page register */
548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
549 break;
550
551 case CHIP_ID_YUKON_EC_U:
552 case CHIP_ID_YUKON_EX:
553 case CHIP_ID_YUKON_SUPR:
554 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
555
556 /* select page 3 to access LED control register */
557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
558
559 /* set LED Function Control register */
560 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
561 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
562 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
563 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
564 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
565
566 /* set Blink Rate in LED Timer Control Register */
567 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
568 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
569 /* restore page register */
570 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
571 break;
572
573 default:
574 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
575 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
576
577 /* turn off the Rx LED (LED_RX) */
578 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
579 }
580
581 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
582 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
583 /* apply fixes in PHY AFE */
584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
585
586 /* increase differential signal amplitude in 10BASE-T */
587 gm_phy_write(hw, port, 0x18, 0xaa99);
588 gm_phy_write(hw, port, 0x17, 0x2011);
589
590 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
591 gm_phy_write(hw, port, 0x18, 0xa204);
592 gm_phy_write(hw, port, 0x17, 0x2002);
593
594 /* set page register to 0 */
595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
596 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
597 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
598 /* apply workaround for integrated resistors calibration */
599 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
600 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
601 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
602 /* no effect on Yukon-XL */
603 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
604
605 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
606 /* turn on 100 Mbps LED (LED_LINK100) */
607 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
608 }
609
610 if (ledover)
611 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
612
613 }
614
615 /* Enable phy interrupt on auto-negotiation complete (or link up) */
616 if (sky2->autoneg == AUTONEG_ENABLE)
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
618 else
619 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
620 }
621
622 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
623 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
624
625 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
626 {
627 u32 reg1;
628
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
630 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
631 reg1 &= ~phy_power[port];
632
633 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
634 reg1 |= coma_mode[port];
635
636 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
637 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
638 sky2_pci_read32(hw, PCI_DEV_REG1);
639 }
640
641 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
642 {
643 u32 reg1;
644 u16 ctrl;
645
646 /* release GPHY Control reset */
647 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
648
649 /* release GMAC reset */
650 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
651
652 if (hw->flags & SKY2_HW_NEWER_PHY) {
653 /* select page 2 to access MAC control register */
654 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
655
656 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
657 /* allow GMII Power Down */
658 ctrl &= ~PHY_M_MAC_GMIF_PUP;
659 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
660
661 /* set page register back to 0 */
662 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
663 }
664
665 /* setup General Purpose Control Register */
666 gma_write16(hw, port, GM_GP_CTRL,
667 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
668
669 if (hw->chip_id != CHIP_ID_YUKON_EC) {
670 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
672
673 /* enable Power Down */
674 ctrl |= PHY_M_PC_POW_D_ENA;
675 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
676 }
677
678 /* set IEEE compatible Power Down Mode (dev. #4.99) */
679 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
680 }
681
682 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
683 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
684 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
685 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
686 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
687 }
688
689 /* Force a renegotiation */
690 static void sky2_phy_reinit(struct sky2_port *sky2)
691 {
692 spin_lock_bh(&sky2->phy_lock);
693 sky2_phy_init(sky2->hw, sky2->port);
694 spin_unlock_bh(&sky2->phy_lock);
695 }
696
697 /* Put device in state to listen for Wake On Lan */
698 static void sky2_wol_init(struct sky2_port *sky2)
699 {
700 struct sky2_hw *hw = sky2->hw;
701 unsigned port = sky2->port;
702 enum flow_control save_mode;
703 u16 ctrl;
704 u32 reg1;
705
706 /* Bring hardware out of reset */
707 sky2_write16(hw, B0_CTST, CS_RST_CLR);
708 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
709
710 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
711 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
712
713 /* Force to 10/100
714 * sky2_reset will re-enable on resume
715 */
716 save_mode = sky2->flow_mode;
717 ctrl = sky2->advertising;
718
719 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
720 sky2->flow_mode = FC_NONE;
721
722 spin_lock_bh(&sky2->phy_lock);
723 sky2_phy_power_up(hw, port);
724 sky2_phy_init(hw, port);
725 spin_unlock_bh(&sky2->phy_lock);
726
727 sky2->flow_mode = save_mode;
728 sky2->advertising = ctrl;
729
730 /* Set GMAC to no flow control and auto update for speed/duplex */
731 gma_write16(hw, port, GM_GP_CTRL,
732 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
733 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
734
735 /* Set WOL address */
736 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
737 sky2->netdev->dev_addr, ETH_ALEN);
738
739 /* Turn on appropriate WOL control bits */
740 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
741 ctrl = 0;
742 if (sky2->wol & WAKE_PHY)
743 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
744 else
745 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
746
747 if (sky2->wol & WAKE_MAGIC)
748 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
749 else
750 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
751
752 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
753 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
754
755 /* Turn on legacy PCI-Express PME mode */
756 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
757 reg1 |= PCI_Y2_PME_LEGACY;
758 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
759
760 /* block receiver */
761 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
762
763 }
764
765 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
766 {
767 struct net_device *dev = hw->dev[port];
768
769 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
770 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
771 hw->chip_id == CHIP_ID_YUKON_FE_P ||
772 hw->chip_id == CHIP_ID_YUKON_SUPR) {
773 /* Yukon-Extreme B0 and further Extreme devices */
774 /* enable Store & Forward mode for TX */
775
776 if (dev->mtu <= ETH_DATA_LEN)
777 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
778 TX_JUMBO_DIS | TX_STFW_ENA);
779
780 else
781 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
782 TX_JUMBO_ENA| TX_STFW_ENA);
783 } else {
784 if (dev->mtu <= ETH_DATA_LEN)
785 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
786 else {
787 /* set Tx GMAC FIFO Almost Empty Threshold */
788 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
789 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
790
791 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
792
793 /* Can't do offload because of lack of store/forward */
794 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
795 }
796 }
797 }
798
799 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
800 {
801 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
802 u16 reg;
803 u32 rx_reg;
804 int i;
805 const u8 *addr = hw->dev[port]->dev_addr;
806
807 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
808 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
809
810 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
811
812 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
813 /* WA DEV_472 -- looks like crossed wires on port 2 */
814 /* clear GMAC 1 Control reset */
815 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
816 do {
817 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
818 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
819 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
820 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
821 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
822 }
823
824 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
825
826 /* Enable Transmit FIFO Underrun */
827 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
828
829 spin_lock_bh(&sky2->phy_lock);
830 sky2_phy_power_up(hw, port);
831 sky2_phy_init(hw, port);
832 spin_unlock_bh(&sky2->phy_lock);
833
834 /* MIB clear */
835 reg = gma_read16(hw, port, GM_PHY_ADDR);
836 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
837
838 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
839 gma_read16(hw, port, i);
840 gma_write16(hw, port, GM_PHY_ADDR, reg);
841
842 /* transmit control */
843 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
844
845 /* receive control reg: unicast + multicast + no FCS */
846 gma_write16(hw, port, GM_RX_CTRL,
847 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
848
849 /* transmit flow control */
850 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
851
852 /* transmit parameter */
853 gma_write16(hw, port, GM_TX_PARAM,
854 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
855 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
856 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
857 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
858
859 /* serial mode register */
860 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
861 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
862
863 if (hw->dev[port]->mtu > ETH_DATA_LEN)
864 reg |= GM_SMOD_JUMBO_ENA;
865
866 gma_write16(hw, port, GM_SERIAL_MODE, reg);
867
868 /* virtual address for data */
869 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
870
871 /* physical address: used for pause frames */
872 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
873
874 /* ignore counter overflows */
875 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
876 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
877 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
878
879 /* Configure Rx MAC FIFO */
880 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
881 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
882 if (hw->chip_id == CHIP_ID_YUKON_EX ||
883 hw->chip_id == CHIP_ID_YUKON_FE_P)
884 rx_reg |= GMF_RX_OVER_ON;
885
886 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
887
888 if (hw->chip_id == CHIP_ID_YUKON_XL) {
889 /* Hardware errata - clear flush mask */
890 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
891 } else {
892 /* Flush Rx MAC FIFO on any flow control or error */
893 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
894 }
895
896 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
897 reg = RX_GMF_FL_THR_DEF + 1;
898 /* Another magic mystery workaround from sk98lin */
899 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
900 hw->chip_rev == CHIP_REV_YU_FE2_A0)
901 reg = 0x178;
902 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
903
904 /* Configure Tx MAC FIFO */
905 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
906 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
907
908 /* On chips without ram buffer, pause is controled by MAC level */
909 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
910 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
911 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
912
913 sky2_set_tx_stfwd(hw, port);
914 }
915
916 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
917 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
918 /* disable dynamic watermark */
919 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
920 reg &= ~TX_DYN_WM_ENA;
921 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
922 }
923 }
924
925 /* Assign Ram Buffer allocation to queue */
926 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
927 {
928 u32 end;
929
930 /* convert from K bytes to qwords used for hw register */
931 start *= 1024/8;
932 space *= 1024/8;
933 end = start + space - 1;
934
935 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
936 sky2_write32(hw, RB_ADDR(q, RB_START), start);
937 sky2_write32(hw, RB_ADDR(q, RB_END), end);
938 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
939 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
940
941 if (q == Q_R1 || q == Q_R2) {
942 u32 tp = space - space/4;
943
944 /* On receive queue's set the thresholds
945 * give receiver priority when > 3/4 full
946 * send pause when down to 2K
947 */
948 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
949 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
950
951 tp = space - 2048/8;
952 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
953 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
954 } else {
955 /* Enable store & forward on Tx queue's because
956 * Tx FIFO is only 1K on Yukon
957 */
958 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
959 }
960
961 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
962 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
963 }
964
965 /* Setup Bus Memory Interface */
966 static void sky2_qset(struct sky2_hw *hw, u16 q)
967 {
968 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
969 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
971 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
972 }
973
974 /* Setup prefetch unit registers. This is the interface between
975 * hardware and driver list elements
976 */
977 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
978 u64 addr, u32 last)
979 {
980 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
981 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
984 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
986
987 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
988 }
989
990 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
991 {
992 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
993
994 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
995 le->ctrl = 0;
996 return le;
997 }
998
999 static void tx_init(struct sky2_port *sky2)
1000 {
1001 struct sky2_tx_le *le;
1002
1003 sky2->tx_prod = sky2->tx_cons = 0;
1004 sky2->tx_tcpsum = 0;
1005 sky2->tx_last_mss = 0;
1006
1007 le = get_tx_le(sky2);
1008 le->addr = 0;
1009 le->opcode = OP_ADDR64 | HW_OWNER;
1010 }
1011
1012 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1013 struct sky2_tx_le *le)
1014 {
1015 return sky2->tx_ring + (le - sky2->tx_le);
1016 }
1017
1018 /* Update chip's next pointer */
1019 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1020 {
1021 /* Make sure write' to descriptors are complete before we tell hardware */
1022 wmb();
1023 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1024
1025 /* Synchronize I/O on since next processor may write to tail */
1026 mmiowb();
1027 }
1028
1029
1030 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1031 {
1032 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1033 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1034 le->ctrl = 0;
1035 return le;
1036 }
1037
1038 /* Build description to hardware for one receive segment */
1039 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1040 dma_addr_t map, unsigned len)
1041 {
1042 struct sky2_rx_le *le;
1043
1044 if (sizeof(dma_addr_t) > sizeof(u32)) {
1045 le = sky2_next_rx(sky2);
1046 le->addr = cpu_to_le32(upper_32_bits(map));
1047 le->opcode = OP_ADDR64 | HW_OWNER;
1048 }
1049
1050 le = sky2_next_rx(sky2);
1051 le->addr = cpu_to_le32((u32) map);
1052 le->length = cpu_to_le16(len);
1053 le->opcode = op | HW_OWNER;
1054 }
1055
1056 /* Build description to hardware for one possibly fragmented skb */
1057 static void sky2_rx_submit(struct sky2_port *sky2,
1058 const struct rx_ring_info *re)
1059 {
1060 int i;
1061
1062 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1063
1064 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1065 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1066 }
1067
1068
1069 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1070 unsigned size)
1071 {
1072 struct sk_buff *skb = re->skb;
1073 int i;
1074
1075 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1076 pci_unmap_len_set(re, data_size, size);
1077
1078 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1079 re->frag_addr[i] = pci_map_page(pdev,
1080 skb_shinfo(skb)->frags[i].page,
1081 skb_shinfo(skb)->frags[i].page_offset,
1082 skb_shinfo(skb)->frags[i].size,
1083 PCI_DMA_FROMDEVICE);
1084 }
1085
1086 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1087 {
1088 struct sk_buff *skb = re->skb;
1089 int i;
1090
1091 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1092 PCI_DMA_FROMDEVICE);
1093
1094 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1095 pci_unmap_page(pdev, re->frag_addr[i],
1096 skb_shinfo(skb)->frags[i].size,
1097 PCI_DMA_FROMDEVICE);
1098 }
1099
1100 /* Tell chip where to start receive checksum.
1101 * Actually has two checksums, but set both same to avoid possible byte
1102 * order problems.
1103 */
1104 static void rx_set_checksum(struct sky2_port *sky2)
1105 {
1106 struct sky2_rx_le *le = sky2_next_rx(sky2);
1107
1108 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1109 le->ctrl = 0;
1110 le->opcode = OP_TCPSTART | HW_OWNER;
1111
1112 sky2_write32(sky2->hw,
1113 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1114 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1115 }
1116
1117 /*
1118 * The RX Stop command will not work for Yukon-2 if the BMU does not
1119 * reach the end of packet and since we can't make sure that we have
1120 * incoming data, we must reset the BMU while it is not doing a DMA
1121 * transfer. Since it is possible that the RX path is still active,
1122 * the RX RAM buffer will be stopped first, so any possible incoming
1123 * data will not trigger a DMA. After the RAM buffer is stopped, the
1124 * BMU is polled until any DMA in progress is ended and only then it
1125 * will be reset.
1126 */
1127 static void sky2_rx_stop(struct sky2_port *sky2)
1128 {
1129 struct sky2_hw *hw = sky2->hw;
1130 unsigned rxq = rxqaddr[sky2->port];
1131 int i;
1132
1133 /* disable the RAM Buffer receive queue */
1134 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1135
1136 for (i = 0; i < 0xffff; i++)
1137 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1138 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1139 goto stopped;
1140
1141 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1142 sky2->netdev->name);
1143 stopped:
1144 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1145
1146 /* reset the Rx prefetch unit */
1147 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1148 mmiowb();
1149 }
1150
1151 /* Clean out receive buffer area, assumes receiver hardware stopped */
1152 static void sky2_rx_clean(struct sky2_port *sky2)
1153 {
1154 unsigned i;
1155
1156 memset(sky2->rx_le, 0, RX_LE_BYTES);
1157 for (i = 0; i < sky2->rx_pending; i++) {
1158 struct rx_ring_info *re = sky2->rx_ring + i;
1159
1160 if (re->skb) {
1161 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1162 kfree_skb(re->skb);
1163 re->skb = NULL;
1164 }
1165 }
1166 }
1167
1168 /* Basic MII support */
1169 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1170 {
1171 struct mii_ioctl_data *data = if_mii(ifr);
1172 struct sky2_port *sky2 = netdev_priv(dev);
1173 struct sky2_hw *hw = sky2->hw;
1174 int err = -EOPNOTSUPP;
1175
1176 if (!netif_running(dev))
1177 return -ENODEV; /* Phy still in reset */
1178
1179 switch (cmd) {
1180 case SIOCGMIIPHY:
1181 data->phy_id = PHY_ADDR_MARV;
1182
1183 /* fallthru */
1184 case SIOCGMIIREG: {
1185 u16 val = 0;
1186
1187 spin_lock_bh(&sky2->phy_lock);
1188 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1189 spin_unlock_bh(&sky2->phy_lock);
1190
1191 data->val_out = val;
1192 break;
1193 }
1194
1195 case SIOCSMIIREG:
1196 if (!capable(CAP_NET_ADMIN))
1197 return -EPERM;
1198
1199 spin_lock_bh(&sky2->phy_lock);
1200 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1201 data->val_in);
1202 spin_unlock_bh(&sky2->phy_lock);
1203 break;
1204 }
1205 return err;
1206 }
1207
1208 #ifdef SKY2_VLAN_TAG_USED
1209 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1210 {
1211 if (onoff) {
1212 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1213 RX_VLAN_STRIP_ON);
1214 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1215 TX_VLAN_TAG_ON);
1216 } else {
1217 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1218 RX_VLAN_STRIP_OFF);
1219 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1220 TX_VLAN_TAG_OFF);
1221 }
1222 }
1223
1224 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1225 {
1226 struct sky2_port *sky2 = netdev_priv(dev);
1227 struct sky2_hw *hw = sky2->hw;
1228 u16 port = sky2->port;
1229
1230 netif_tx_lock_bh(dev);
1231 napi_disable(&hw->napi);
1232
1233 sky2->vlgrp = grp;
1234 sky2_set_vlan_mode(hw, port, grp != NULL);
1235
1236 sky2_read32(hw, B0_Y2_SP_LISR);
1237 napi_enable(&hw->napi);
1238 netif_tx_unlock_bh(dev);
1239 }
1240 #endif
1241
1242 /*
1243 * Allocate an skb for receiving. If the MTU is large enough
1244 * make the skb non-linear with a fragment list of pages.
1245 */
1246 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1247 {
1248 struct sk_buff *skb;
1249 int i;
1250
1251 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1252 unsigned char *start;
1253 /*
1254 * Workaround for a bug in FIFO that cause hang
1255 * if the FIFO if the receive buffer is not 64 byte aligned.
1256 * The buffer returned from netdev_alloc_skb is
1257 * aligned except if slab debugging is enabled.
1258 */
1259 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1260 if (!skb)
1261 goto nomem;
1262 start = PTR_ALIGN(skb->data, 8);
1263 skb_reserve(skb, start - skb->data);
1264 } else {
1265 skb = netdev_alloc_skb(sky2->netdev,
1266 sky2->rx_data_size + NET_IP_ALIGN);
1267 if (!skb)
1268 goto nomem;
1269 skb_reserve(skb, NET_IP_ALIGN);
1270 }
1271
1272 for (i = 0; i < sky2->rx_nfrags; i++) {
1273 struct page *page = alloc_page(GFP_ATOMIC);
1274
1275 if (!page)
1276 goto free_partial;
1277 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1278 }
1279
1280 return skb;
1281 free_partial:
1282 kfree_skb(skb);
1283 nomem:
1284 return NULL;
1285 }
1286
1287 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1288 {
1289 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1290 }
1291
1292 /*
1293 * Allocate and setup receiver buffer pool.
1294 * Normal case this ends up creating one list element for skb
1295 * in the receive ring. Worst case if using large MTU and each
1296 * allocation falls on a different 64 bit region, that results
1297 * in 6 list elements per ring entry.
1298 * One element is used for checksum enable/disable, and one
1299 * extra to avoid wrap.
1300 */
1301 static int sky2_rx_start(struct sky2_port *sky2)
1302 {
1303 struct sky2_hw *hw = sky2->hw;
1304 struct rx_ring_info *re;
1305 unsigned rxq = rxqaddr[sky2->port];
1306 unsigned i, size, thresh;
1307
1308 sky2->rx_put = sky2->rx_next = 0;
1309 sky2_qset(hw, rxq);
1310
1311 /* On PCI express lowering the watermark gives better performance */
1312 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1313 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1314
1315 /* These chips have no ram buffer?
1316 * MAC Rx RAM Read is controlled by hardware */
1317 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1318 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1319 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1320 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1321
1322 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1323
1324 if (!(hw->flags & SKY2_HW_NEW_LE))
1325 rx_set_checksum(sky2);
1326
1327 /* Space needed for frame data + headers rounded up */
1328 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1329
1330 /* Stopping point for hardware truncation */
1331 thresh = (size - 8) / sizeof(u32);
1332
1333 sky2->rx_nfrags = size >> PAGE_SHIFT;
1334 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1335
1336 /* Compute residue after pages */
1337 size -= sky2->rx_nfrags << PAGE_SHIFT;
1338
1339 /* Optimize to handle small packets and headers */
1340 if (size < copybreak)
1341 size = copybreak;
1342 if (size < ETH_HLEN)
1343 size = ETH_HLEN;
1344
1345 sky2->rx_data_size = size;
1346
1347 /* Fill Rx ring */
1348 for (i = 0; i < sky2->rx_pending; i++) {
1349 re = sky2->rx_ring + i;
1350
1351 re->skb = sky2_rx_alloc(sky2);
1352 if (!re->skb)
1353 goto nomem;
1354
1355 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1356 sky2_rx_submit(sky2, re);
1357 }
1358
1359 /*
1360 * The receiver hangs if it receives frames larger than the
1361 * packet buffer. As a workaround, truncate oversize frames, but
1362 * the register is limited to 9 bits, so if you do frames > 2052
1363 * you better get the MTU right!
1364 */
1365 if (thresh > 0x1ff)
1366 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1367 else {
1368 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1369 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1370 }
1371
1372 /* Tell chip about available buffers */
1373 sky2_rx_update(sky2, rxq);
1374 return 0;
1375 nomem:
1376 sky2_rx_clean(sky2);
1377 return -ENOMEM;
1378 }
1379
1380 /* Bring up network interface. */
1381 static int sky2_up(struct net_device *dev)
1382 {
1383 struct sky2_port *sky2 = netdev_priv(dev);
1384 struct sky2_hw *hw = sky2->hw;
1385 unsigned port = sky2->port;
1386 u32 imask, ramsize;
1387 int cap, err = -ENOMEM;
1388 struct net_device *otherdev = hw->dev[sky2->port^1];
1389
1390 /*
1391 * On dual port PCI-X card, there is an problem where status
1392 * can be received out of order due to split transactions
1393 */
1394 if (otherdev && netif_running(otherdev) &&
1395 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1396 u16 cmd;
1397
1398 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1399 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1400 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1401
1402 }
1403
1404 if (netif_msg_ifup(sky2))
1405 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1406
1407 netif_carrier_off(dev);
1408
1409 /* must be power of 2 */
1410 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1411 TX_RING_SIZE *
1412 sizeof(struct sky2_tx_le),
1413 &sky2->tx_le_map);
1414 if (!sky2->tx_le)
1415 goto err_out;
1416
1417 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1418 GFP_KERNEL);
1419 if (!sky2->tx_ring)
1420 goto err_out;
1421
1422 tx_init(sky2);
1423
1424 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1425 &sky2->rx_le_map);
1426 if (!sky2->rx_le)
1427 goto err_out;
1428 memset(sky2->rx_le, 0, RX_LE_BYTES);
1429
1430 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1431 GFP_KERNEL);
1432 if (!sky2->rx_ring)
1433 goto err_out;
1434
1435 sky2_mac_init(hw, port);
1436
1437 /* Register is number of 4K blocks on internal RAM buffer. */
1438 ramsize = sky2_read8(hw, B2_E_0) * 4;
1439 if (ramsize > 0) {
1440 u32 rxspace;
1441
1442 hw->flags |= SKY2_HW_RAM_BUFFER;
1443 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1444 if (ramsize < 16)
1445 rxspace = ramsize / 2;
1446 else
1447 rxspace = 8 + (2*(ramsize - 16))/3;
1448
1449 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1450 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1451
1452 /* Make sure SyncQ is disabled */
1453 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1454 RB_RST_SET);
1455 }
1456
1457 sky2_qset(hw, txqaddr[port]);
1458
1459 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1460 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1461 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1462
1463 /* Set almost empty threshold */
1464 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1465 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1466 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1467
1468 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1469 TX_RING_SIZE - 1);
1470
1471 #ifdef SKY2_VLAN_TAG_USED
1472 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1473 #endif
1474
1475 err = sky2_rx_start(sky2);
1476 if (err)
1477 goto err_out;
1478
1479 /* Enable interrupts from phy/mac for port */
1480 imask = sky2_read32(hw, B0_IMSK);
1481 imask |= portirq_msk[port];
1482 sky2_write32(hw, B0_IMSK, imask);
1483
1484 sky2_set_multicast(dev);
1485 return 0;
1486
1487 err_out:
1488 if (sky2->rx_le) {
1489 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1490 sky2->rx_le, sky2->rx_le_map);
1491 sky2->rx_le = NULL;
1492 }
1493 if (sky2->tx_le) {
1494 pci_free_consistent(hw->pdev,
1495 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1496 sky2->tx_le, sky2->tx_le_map);
1497 sky2->tx_le = NULL;
1498 }
1499 kfree(sky2->tx_ring);
1500 kfree(sky2->rx_ring);
1501
1502 sky2->tx_ring = NULL;
1503 sky2->rx_ring = NULL;
1504 return err;
1505 }
1506
1507 /* Modular subtraction in ring */
1508 static inline int tx_dist(unsigned tail, unsigned head)
1509 {
1510 return (head - tail) & (TX_RING_SIZE - 1);
1511 }
1512
1513 /* Number of list elements available for next tx */
1514 static inline int tx_avail(const struct sky2_port *sky2)
1515 {
1516 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1517 }
1518
1519 /* Estimate of number of transmit list elements required */
1520 static unsigned tx_le_req(const struct sk_buff *skb)
1521 {
1522 unsigned count;
1523
1524 count = sizeof(dma_addr_t) / sizeof(u32);
1525 count += skb_shinfo(skb)->nr_frags * count;
1526
1527 if (skb_is_gso(skb))
1528 ++count;
1529
1530 if (skb->ip_summed == CHECKSUM_PARTIAL)
1531 ++count;
1532
1533 return count;
1534 }
1535
1536 /*
1537 * Put one packet in ring for transmit.
1538 * A single packet can generate multiple list elements, and
1539 * the number of ring elements will probably be less than the number
1540 * of list elements used.
1541 */
1542 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1543 {
1544 struct sky2_port *sky2 = netdev_priv(dev);
1545 struct sky2_hw *hw = sky2->hw;
1546 struct sky2_tx_le *le = NULL;
1547 struct tx_ring_info *re;
1548 unsigned i, len;
1549 dma_addr_t mapping;
1550 u16 mss;
1551 u8 ctrl;
1552
1553 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1554 return NETDEV_TX_BUSY;
1555
1556 if (unlikely(netif_msg_tx_queued(sky2)))
1557 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1558 dev->name, sky2->tx_prod, skb->len);
1559
1560 len = skb_headlen(skb);
1561 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1562
1563 /* Send high bits if needed */
1564 if (sizeof(dma_addr_t) > sizeof(u32)) {
1565 le = get_tx_le(sky2);
1566 le->addr = cpu_to_le32(upper_32_bits(mapping));
1567 le->opcode = OP_ADDR64 | HW_OWNER;
1568 }
1569
1570 /* Check for TCP Segmentation Offload */
1571 mss = skb_shinfo(skb)->gso_size;
1572 if (mss != 0) {
1573
1574 if (!(hw->flags & SKY2_HW_NEW_LE))
1575 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1576
1577 if (mss != sky2->tx_last_mss) {
1578 le = get_tx_le(sky2);
1579 le->addr = cpu_to_le32(mss);
1580
1581 if (hw->flags & SKY2_HW_NEW_LE)
1582 le->opcode = OP_MSS | HW_OWNER;
1583 else
1584 le->opcode = OP_LRGLEN | HW_OWNER;
1585 sky2->tx_last_mss = mss;
1586 }
1587 }
1588
1589 ctrl = 0;
1590 #ifdef SKY2_VLAN_TAG_USED
1591 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1592 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1593 if (!le) {
1594 le = get_tx_le(sky2);
1595 le->addr = 0;
1596 le->opcode = OP_VLAN|HW_OWNER;
1597 } else
1598 le->opcode |= OP_VLAN;
1599 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1600 ctrl |= INS_VLAN;
1601 }
1602 #endif
1603
1604 /* Handle TCP checksum offload */
1605 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1606 /* On Yukon EX (some versions) encoding change. */
1607 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1608 ctrl |= CALSUM; /* auto checksum */
1609 else {
1610 const unsigned offset = skb_transport_offset(skb);
1611 u32 tcpsum;
1612
1613 tcpsum = offset << 16; /* sum start */
1614 tcpsum |= offset + skb->csum_offset; /* sum write */
1615
1616 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1617 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1618 ctrl |= UDPTCP;
1619
1620 if (tcpsum != sky2->tx_tcpsum) {
1621 sky2->tx_tcpsum = tcpsum;
1622
1623 le = get_tx_le(sky2);
1624 le->addr = cpu_to_le32(tcpsum);
1625 le->length = 0; /* initial checksum value */
1626 le->ctrl = 1; /* one packet */
1627 le->opcode = OP_TCPLISW | HW_OWNER;
1628 }
1629 }
1630 }
1631
1632 le = get_tx_le(sky2);
1633 le->addr = cpu_to_le32((u32) mapping);
1634 le->length = cpu_to_le16(len);
1635 le->ctrl = ctrl;
1636 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1637
1638 re = tx_le_re(sky2, le);
1639 re->skb = skb;
1640 pci_unmap_addr_set(re, mapaddr, mapping);
1641 pci_unmap_len_set(re, maplen, len);
1642
1643 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1644 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1645
1646 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1647 frag->size, PCI_DMA_TODEVICE);
1648
1649 if (sizeof(dma_addr_t) > sizeof(u32)) {
1650 le = get_tx_le(sky2);
1651 le->addr = cpu_to_le32(upper_32_bits(mapping));
1652 le->ctrl = 0;
1653 le->opcode = OP_ADDR64 | HW_OWNER;
1654 }
1655
1656 le = get_tx_le(sky2);
1657 le->addr = cpu_to_le32((u32) mapping);
1658 le->length = cpu_to_le16(frag->size);
1659 le->ctrl = ctrl;
1660 le->opcode = OP_BUFFER | HW_OWNER;
1661
1662 re = tx_le_re(sky2, le);
1663 re->skb = skb;
1664 pci_unmap_addr_set(re, mapaddr, mapping);
1665 pci_unmap_len_set(re, maplen, frag->size);
1666 }
1667
1668 le->ctrl |= EOP;
1669
1670 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1671 netif_stop_queue(dev);
1672
1673 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1674
1675 dev->trans_start = jiffies;
1676 return NETDEV_TX_OK;
1677 }
1678
1679 /*
1680 * Free ring elements from starting at tx_cons until "done"
1681 *
1682 * NB: the hardware will tell us about partial completion of multi-part
1683 * buffers so make sure not to free skb to early.
1684 */
1685 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1686 {
1687 struct net_device *dev = sky2->netdev;
1688 struct pci_dev *pdev = sky2->hw->pdev;
1689 unsigned idx;
1690
1691 BUG_ON(done >= TX_RING_SIZE);
1692
1693 for (idx = sky2->tx_cons; idx != done;
1694 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1695 struct sky2_tx_le *le = sky2->tx_le + idx;
1696 struct tx_ring_info *re = sky2->tx_ring + idx;
1697
1698 switch(le->opcode & ~HW_OWNER) {
1699 case OP_LARGESEND:
1700 case OP_PACKET:
1701 pci_unmap_single(pdev,
1702 pci_unmap_addr(re, mapaddr),
1703 pci_unmap_len(re, maplen),
1704 PCI_DMA_TODEVICE);
1705 break;
1706 case OP_BUFFER:
1707 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1708 pci_unmap_len(re, maplen),
1709 PCI_DMA_TODEVICE);
1710 break;
1711 }
1712
1713 if (le->ctrl & EOP) {
1714 if (unlikely(netif_msg_tx_done(sky2)))
1715 printk(KERN_DEBUG "%s: tx done %u\n",
1716 dev->name, idx);
1717
1718 dev->stats.tx_packets++;
1719 dev->stats.tx_bytes += re->skb->len;
1720
1721 dev_kfree_skb_any(re->skb);
1722 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1723 }
1724 }
1725
1726 sky2->tx_cons = idx;
1727 smp_mb();
1728
1729 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1730 netif_wake_queue(dev);
1731 }
1732
1733 /* Cleanup all untransmitted buffers, assume transmitter not running */
1734 static void sky2_tx_clean(struct net_device *dev)
1735 {
1736 struct sky2_port *sky2 = netdev_priv(dev);
1737
1738 netif_tx_lock_bh(dev);
1739 sky2_tx_complete(sky2, sky2->tx_prod);
1740 netif_tx_unlock_bh(dev);
1741 }
1742
1743 /* Network shutdown */
1744 static int sky2_down(struct net_device *dev)
1745 {
1746 struct sky2_port *sky2 = netdev_priv(dev);
1747 struct sky2_hw *hw = sky2->hw;
1748 unsigned port = sky2->port;
1749 u16 ctrl;
1750 u32 imask;
1751
1752 /* Never really got started! */
1753 if (!sky2->tx_le)
1754 return 0;
1755
1756 if (netif_msg_ifdown(sky2))
1757 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1758
1759 /* Stop more packets from being queued */
1760 netif_stop_queue(dev);
1761
1762 /* Disable port IRQ */
1763 imask = sky2_read32(hw, B0_IMSK);
1764 imask &= ~portirq_msk[port];
1765 sky2_write32(hw, B0_IMSK, imask);
1766
1767 synchronize_irq(hw->pdev->irq);
1768
1769 sky2_gmac_reset(hw, port);
1770
1771 /* Stop transmitter */
1772 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1773 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1774
1775 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1776 RB_RST_SET | RB_DIS_OP_MD);
1777
1778 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1779 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1780 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1781
1782 /* Make sure no packets are pending */
1783 napi_synchronize(&hw->napi);
1784
1785 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1786
1787 /* Workaround shared GMAC reset */
1788 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1789 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1790 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1791
1792 /* Disable Force Sync bit and Enable Alloc bit */
1793 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1794 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1795
1796 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1797 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1798 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1799
1800 /* Reset the PCI FIFO of the async Tx queue */
1801 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1802 BMU_RST_SET | BMU_FIFO_RST);
1803
1804 /* Reset the Tx prefetch units */
1805 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1806 PREF_UNIT_RST_SET);
1807
1808 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1809
1810 sky2_rx_stop(sky2);
1811
1812 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1813 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1814
1815 sky2_phy_power_down(hw, port);
1816
1817 netif_carrier_off(dev);
1818
1819 /* turn off LED's */
1820 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1821
1822 sky2_tx_clean(dev);
1823 sky2_rx_clean(sky2);
1824
1825 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1826 sky2->rx_le, sky2->rx_le_map);
1827 kfree(sky2->rx_ring);
1828
1829 pci_free_consistent(hw->pdev,
1830 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1831 sky2->tx_le, sky2->tx_le_map);
1832 kfree(sky2->tx_ring);
1833
1834 sky2->tx_le = NULL;
1835 sky2->rx_le = NULL;
1836
1837 sky2->rx_ring = NULL;
1838 sky2->tx_ring = NULL;
1839
1840 return 0;
1841 }
1842
1843 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1844 {
1845 if (hw->flags & SKY2_HW_FIBRE_PHY)
1846 return SPEED_1000;
1847
1848 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1849 if (aux & PHY_M_PS_SPEED_100)
1850 return SPEED_100;
1851 else
1852 return SPEED_10;
1853 }
1854
1855 switch (aux & PHY_M_PS_SPEED_MSK) {
1856 case PHY_M_PS_SPEED_1000:
1857 return SPEED_1000;
1858 case PHY_M_PS_SPEED_100:
1859 return SPEED_100;
1860 default:
1861 return SPEED_10;
1862 }
1863 }
1864
1865 static void sky2_link_up(struct sky2_port *sky2)
1866 {
1867 struct sky2_hw *hw = sky2->hw;
1868 unsigned port = sky2->port;
1869 u16 reg;
1870 static const char *fc_name[] = {
1871 [FC_NONE] = "none",
1872 [FC_TX] = "tx",
1873 [FC_RX] = "rx",
1874 [FC_BOTH] = "both",
1875 };
1876
1877 /* enable Rx/Tx */
1878 reg = gma_read16(hw, port, GM_GP_CTRL);
1879 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1880 gma_write16(hw, port, GM_GP_CTRL, reg);
1881
1882 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1883
1884 netif_carrier_on(sky2->netdev);
1885
1886 mod_timer(&hw->watchdog_timer, jiffies + 1);
1887
1888 /* Turn on link LED */
1889 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1890 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1891
1892 if (netif_msg_link(sky2))
1893 printk(KERN_INFO PFX
1894 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1895 sky2->netdev->name, sky2->speed,
1896 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1897 fc_name[sky2->flow_status]);
1898 }
1899
1900 static void sky2_link_down(struct sky2_port *sky2)
1901 {
1902 struct sky2_hw *hw = sky2->hw;
1903 unsigned port = sky2->port;
1904 u16 reg;
1905
1906 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1907
1908 reg = gma_read16(hw, port, GM_GP_CTRL);
1909 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1910 gma_write16(hw, port, GM_GP_CTRL, reg);
1911
1912 netif_carrier_off(sky2->netdev);
1913
1914 /* Turn on link LED */
1915 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1916
1917 if (netif_msg_link(sky2))
1918 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1919
1920 sky2_phy_init(hw, port);
1921 }
1922
1923 static enum flow_control sky2_flow(int rx, int tx)
1924 {
1925 if (rx)
1926 return tx ? FC_BOTH : FC_RX;
1927 else
1928 return tx ? FC_TX : FC_NONE;
1929 }
1930
1931 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1932 {
1933 struct sky2_hw *hw = sky2->hw;
1934 unsigned port = sky2->port;
1935 u16 advert, lpa;
1936
1937 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1938 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1939 if (lpa & PHY_M_AN_RF) {
1940 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1941 return -1;
1942 }
1943
1944 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1945 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1946 sky2->netdev->name);
1947 return -1;
1948 }
1949
1950 sky2->speed = sky2_phy_speed(hw, aux);
1951 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1952
1953 /* Since the pause result bits seem to in different positions on
1954 * different chips. look at registers.
1955 */
1956 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1957 /* Shift for bits in fiber PHY */
1958 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1959 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1960
1961 if (advert & ADVERTISE_1000XPAUSE)
1962 advert |= ADVERTISE_PAUSE_CAP;
1963 if (advert & ADVERTISE_1000XPSE_ASYM)
1964 advert |= ADVERTISE_PAUSE_ASYM;
1965 if (lpa & LPA_1000XPAUSE)
1966 lpa |= LPA_PAUSE_CAP;
1967 if (lpa & LPA_1000XPAUSE_ASYM)
1968 lpa |= LPA_PAUSE_ASYM;
1969 }
1970
1971 sky2->flow_status = FC_NONE;
1972 if (advert & ADVERTISE_PAUSE_CAP) {
1973 if (lpa & LPA_PAUSE_CAP)
1974 sky2->flow_status = FC_BOTH;
1975 else if (advert & ADVERTISE_PAUSE_ASYM)
1976 sky2->flow_status = FC_RX;
1977 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1978 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1979 sky2->flow_status = FC_TX;
1980 }
1981
1982 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1983 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1984 sky2->flow_status = FC_NONE;
1985
1986 if (sky2->flow_status & FC_TX)
1987 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1988 else
1989 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1990
1991 return 0;
1992 }
1993
1994 /* Interrupt from PHY */
1995 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1996 {
1997 struct net_device *dev = hw->dev[port];
1998 struct sky2_port *sky2 = netdev_priv(dev);
1999 u16 istatus, phystat;
2000
2001 if (!netif_running(dev))
2002 return;
2003
2004 spin_lock(&sky2->phy_lock);
2005 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2006 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2007
2008 if (netif_msg_intr(sky2))
2009 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2010 sky2->netdev->name, istatus, phystat);
2011
2012 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2013 if (sky2_autoneg_done(sky2, phystat) == 0)
2014 sky2_link_up(sky2);
2015 goto out;
2016 }
2017
2018 if (istatus & PHY_M_IS_LSP_CHANGE)
2019 sky2->speed = sky2_phy_speed(hw, phystat);
2020
2021 if (istatus & PHY_M_IS_DUP_CHANGE)
2022 sky2->duplex =
2023 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2024
2025 if (istatus & PHY_M_IS_LST_CHANGE) {
2026 if (phystat & PHY_M_PS_LINK_UP)
2027 sky2_link_up(sky2);
2028 else
2029 sky2_link_down(sky2);
2030 }
2031 out:
2032 spin_unlock(&sky2->phy_lock);
2033 }
2034
2035 /* Transmit timeout is only called if we are running, carrier is up
2036 * and tx queue is full (stopped).
2037 */
2038 static void sky2_tx_timeout(struct net_device *dev)
2039 {
2040 struct sky2_port *sky2 = netdev_priv(dev);
2041 struct sky2_hw *hw = sky2->hw;
2042
2043 if (netif_msg_timer(sky2))
2044 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2045
2046 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2047 dev->name, sky2->tx_cons, sky2->tx_prod,
2048 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2049 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2050
2051 /* can't restart safely under softirq */
2052 schedule_work(&hw->restart_work);
2053 }
2054
2055 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2056 {
2057 struct sky2_port *sky2 = netdev_priv(dev);
2058 struct sky2_hw *hw = sky2->hw;
2059 unsigned port = sky2->port;
2060 int err;
2061 u16 ctl, mode;
2062 u32 imask;
2063
2064 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2065 return -EINVAL;
2066
2067 if (new_mtu > ETH_DATA_LEN &&
2068 (hw->chip_id == CHIP_ID_YUKON_FE ||
2069 hw->chip_id == CHIP_ID_YUKON_FE_P))
2070 return -EINVAL;
2071
2072 if (!netif_running(dev)) {
2073 dev->mtu = new_mtu;
2074 return 0;
2075 }
2076
2077 imask = sky2_read32(hw, B0_IMSK);
2078 sky2_write32(hw, B0_IMSK, 0);
2079
2080 dev->trans_start = jiffies; /* prevent tx timeout */
2081 netif_stop_queue(dev);
2082 napi_disable(&hw->napi);
2083
2084 synchronize_irq(hw->pdev->irq);
2085
2086 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2087 sky2_set_tx_stfwd(hw, port);
2088
2089 ctl = gma_read16(hw, port, GM_GP_CTRL);
2090 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2091 sky2_rx_stop(sky2);
2092 sky2_rx_clean(sky2);
2093
2094 dev->mtu = new_mtu;
2095
2096 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2097 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2098
2099 if (dev->mtu > ETH_DATA_LEN)
2100 mode |= GM_SMOD_JUMBO_ENA;
2101
2102 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2103
2104 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2105
2106 err = sky2_rx_start(sky2);
2107 sky2_write32(hw, B0_IMSK, imask);
2108
2109 sky2_read32(hw, B0_Y2_SP_LISR);
2110 napi_enable(&hw->napi);
2111
2112 if (err)
2113 dev_close(dev);
2114 else {
2115 gma_write16(hw, port, GM_GP_CTRL, ctl);
2116
2117 netif_wake_queue(dev);
2118 }
2119
2120 return err;
2121 }
2122
2123 /* For small just reuse existing skb for next receive */
2124 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2125 const struct rx_ring_info *re,
2126 unsigned length)
2127 {
2128 struct sk_buff *skb;
2129
2130 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2131 if (likely(skb)) {
2132 skb_reserve(skb, 2);
2133 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2134 length, PCI_DMA_FROMDEVICE);
2135 skb_copy_from_linear_data(re->skb, skb->data, length);
2136 skb->ip_summed = re->skb->ip_summed;
2137 skb->csum = re->skb->csum;
2138 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2139 length, PCI_DMA_FROMDEVICE);
2140 re->skb->ip_summed = CHECKSUM_NONE;
2141 skb_put(skb, length);
2142 }
2143 return skb;
2144 }
2145
2146 /* Adjust length of skb with fragments to match received data */
2147 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2148 unsigned int length)
2149 {
2150 int i, num_frags;
2151 unsigned int size;
2152
2153 /* put header into skb */
2154 size = min(length, hdr_space);
2155 skb->tail += size;
2156 skb->len += size;
2157 length -= size;
2158
2159 num_frags = skb_shinfo(skb)->nr_frags;
2160 for (i = 0; i < num_frags; i++) {
2161 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2162
2163 if (length == 0) {
2164 /* don't need this page */
2165 __free_page(frag->page);
2166 --skb_shinfo(skb)->nr_frags;
2167 } else {
2168 size = min(length, (unsigned) PAGE_SIZE);
2169
2170 frag->size = size;
2171 skb->data_len += size;
2172 skb->truesize += size;
2173 skb->len += size;
2174 length -= size;
2175 }
2176 }
2177 }
2178
2179 /* Normal packet - take skb from ring element and put in a new one */
2180 static struct sk_buff *receive_new(struct sky2_port *sky2,
2181 struct rx_ring_info *re,
2182 unsigned int length)
2183 {
2184 struct sk_buff *skb, *nskb;
2185 unsigned hdr_space = sky2->rx_data_size;
2186
2187 /* Don't be tricky about reusing pages (yet) */
2188 nskb = sky2_rx_alloc(sky2);
2189 if (unlikely(!nskb))
2190 return NULL;
2191
2192 skb = re->skb;
2193 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2194
2195 prefetch(skb->data);
2196 re->skb = nskb;
2197 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2198
2199 if (skb_shinfo(skb)->nr_frags)
2200 skb_put_frags(skb, hdr_space, length);
2201 else
2202 skb_put(skb, length);
2203 return skb;
2204 }
2205
2206 /*
2207 * Receive one packet.
2208 * For larger packets, get new buffer.
2209 */
2210 static struct sk_buff *sky2_receive(struct net_device *dev,
2211 u16 length, u32 status)
2212 {
2213 struct sky2_port *sky2 = netdev_priv(dev);
2214 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2215 struct sk_buff *skb = NULL;
2216 u16 count = (status & GMR_FS_LEN) >> 16;
2217
2218 #ifdef SKY2_VLAN_TAG_USED
2219 /* Account for vlan tag */
2220 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2221 count -= VLAN_HLEN;
2222 #endif
2223
2224 if (unlikely(netif_msg_rx_status(sky2)))
2225 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2226 dev->name, sky2->rx_next, status, length);
2227
2228 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2229 prefetch(sky2->rx_ring + sky2->rx_next);
2230
2231 /* This chip has hardware problems that generates bogus status.
2232 * So do only marginal checking and expect higher level protocols
2233 * to handle crap frames.
2234 */
2235 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2236 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2237 length != count)
2238 goto okay;
2239
2240 if (status & GMR_FS_ANY_ERR)
2241 goto error;
2242
2243 if (!(status & GMR_FS_RX_OK))
2244 goto resubmit;
2245
2246 /* if length reported by DMA does not match PHY, packet was truncated */
2247 if (length != count)
2248 goto len_error;
2249
2250 okay:
2251 if (length < copybreak)
2252 skb = receive_copy(sky2, re, length);
2253 else
2254 skb = receive_new(sky2, re, length);
2255 resubmit:
2256 sky2_rx_submit(sky2, re);
2257
2258 return skb;
2259
2260 len_error:
2261 /* Truncation of overlength packets
2262 causes PHY length to not match MAC length */
2263 ++dev->stats.rx_length_errors;
2264 if (netif_msg_rx_err(sky2) && net_ratelimit())
2265 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2266 dev->name, status, length);
2267 goto resubmit;
2268
2269 error:
2270 ++dev->stats.rx_errors;
2271 if (status & GMR_FS_RX_FF_OV) {
2272 dev->stats.rx_over_errors++;
2273 goto resubmit;
2274 }
2275
2276 if (netif_msg_rx_err(sky2) && net_ratelimit())
2277 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2278 dev->name, status, length);
2279
2280 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2281 dev->stats.rx_length_errors++;
2282 if (status & GMR_FS_FRAGMENT)
2283 dev->stats.rx_frame_errors++;
2284 if (status & GMR_FS_CRC_ERR)
2285 dev->stats.rx_crc_errors++;
2286
2287 goto resubmit;
2288 }
2289
2290 /* Transmit complete */
2291 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2292 {
2293 struct sky2_port *sky2 = netdev_priv(dev);
2294
2295 if (netif_running(dev)) {
2296 netif_tx_lock(dev);
2297 sky2_tx_complete(sky2, last);
2298 netif_tx_unlock(dev);
2299 }
2300 }
2301
2302 /* Process status response ring */
2303 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2304 {
2305 int work_done = 0;
2306 unsigned rx[2] = { 0, 0 };
2307
2308 rmb();
2309 do {
2310 struct sky2_port *sky2;
2311 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2312 unsigned port;
2313 struct net_device *dev;
2314 struct sk_buff *skb;
2315 u32 status;
2316 u16 length;
2317 u8 opcode = le->opcode;
2318
2319 if (!(opcode & HW_OWNER))
2320 break;
2321
2322 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2323
2324 port = le->css & CSS_LINK_BIT;
2325 dev = hw->dev[port];
2326 sky2 = netdev_priv(dev);
2327 length = le16_to_cpu(le->length);
2328 status = le32_to_cpu(le->status);
2329
2330 le->opcode = 0;
2331 switch (opcode & ~HW_OWNER) {
2332 case OP_RXSTAT:
2333 ++rx[port];
2334 skb = sky2_receive(dev, length, status);
2335 if (unlikely(!skb)) {
2336 dev->stats.rx_dropped++;
2337 break;
2338 }
2339
2340 /* This chip reports checksum status differently */
2341 if (hw->flags & SKY2_HW_NEW_LE) {
2342 if (sky2->rx_csum &&
2343 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2344 (le->css & CSS_TCPUDPCSOK))
2345 skb->ip_summed = CHECKSUM_UNNECESSARY;
2346 else
2347 skb->ip_summed = CHECKSUM_NONE;
2348 }
2349
2350 skb->protocol = eth_type_trans(skb, dev);
2351 dev->stats.rx_packets++;
2352 dev->stats.rx_bytes += skb->len;
2353 dev->last_rx = jiffies;
2354
2355 #ifdef SKY2_VLAN_TAG_USED
2356 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2357 vlan_hwaccel_receive_skb(skb,
2358 sky2->vlgrp,
2359 be16_to_cpu(sky2->rx_tag));
2360 } else
2361 #endif
2362 netif_receive_skb(skb);
2363
2364 /* Stop after net poll weight */
2365 if (++work_done >= to_do)
2366 goto exit_loop;
2367 break;
2368
2369 #ifdef SKY2_VLAN_TAG_USED
2370 case OP_RXVLAN:
2371 sky2->rx_tag = length;
2372 break;
2373
2374 case OP_RXCHKSVLAN:
2375 sky2->rx_tag = length;
2376 /* fall through */
2377 #endif
2378 case OP_RXCHKS:
2379 if (!sky2->rx_csum)
2380 break;
2381
2382 /* If this happens then driver assuming wrong format */
2383 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2384 if (net_ratelimit())
2385 printk(KERN_NOTICE "%s: unexpected"
2386 " checksum status\n",
2387 dev->name);
2388 break;
2389 }
2390
2391 /* Both checksum counters are programmed to start at
2392 * the same offset, so unless there is a problem they
2393 * should match. This failure is an early indication that
2394 * hardware receive checksumming won't work.
2395 */
2396 if (likely(status >> 16 == (status & 0xffff))) {
2397 skb = sky2->rx_ring[sky2->rx_next].skb;
2398 skb->ip_summed = CHECKSUM_COMPLETE;
2399 skb->csum = status & 0xffff;
2400 } else {
2401 printk(KERN_NOTICE PFX "%s: hardware receive "
2402 "checksum problem (status = %#x)\n",
2403 dev->name, status);
2404 sky2->rx_csum = 0;
2405 sky2_write32(sky2->hw,
2406 Q_ADDR(rxqaddr[port], Q_CSR),
2407 BMU_DIS_RX_CHKSUM);
2408 }
2409 break;
2410
2411 case OP_TXINDEXLE:
2412 /* TX index reports status for both ports */
2413 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2414 sky2_tx_done(hw->dev[0], status & 0xfff);
2415 if (hw->dev[1])
2416 sky2_tx_done(hw->dev[1],
2417 ((status >> 24) & 0xff)
2418 | (u16)(length & 0xf) << 8);
2419 break;
2420
2421 default:
2422 if (net_ratelimit())
2423 printk(KERN_WARNING PFX
2424 "unknown status opcode 0x%x\n", opcode);
2425 }
2426 } while (hw->st_idx != idx);
2427
2428 /* Fully processed status ring so clear irq */
2429 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2430
2431 exit_loop:
2432 if (rx[0])
2433 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2434
2435 if (rx[1])
2436 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2437
2438 return work_done;
2439 }
2440
2441 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2442 {
2443 struct net_device *dev = hw->dev[port];
2444
2445 if (net_ratelimit())
2446 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2447 dev->name, status);
2448
2449 if (status & Y2_IS_PAR_RD1) {
2450 if (net_ratelimit())
2451 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2452 dev->name);
2453 /* Clear IRQ */
2454 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2455 }
2456
2457 if (status & Y2_IS_PAR_WR1) {
2458 if (net_ratelimit())
2459 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2460 dev->name);
2461
2462 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2463 }
2464
2465 if (status & Y2_IS_PAR_MAC1) {
2466 if (net_ratelimit())
2467 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2468 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2469 }
2470
2471 if (status & Y2_IS_PAR_RX1) {
2472 if (net_ratelimit())
2473 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2474 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2475 }
2476
2477 if (status & Y2_IS_TCP_TXA1) {
2478 if (net_ratelimit())
2479 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2480 dev->name);
2481 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2482 }
2483 }
2484
2485 static void sky2_hw_intr(struct sky2_hw *hw)
2486 {
2487 struct pci_dev *pdev = hw->pdev;
2488 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2489 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2490
2491 status &= hwmsk;
2492
2493 if (status & Y2_IS_TIST_OV)
2494 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2495
2496 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2497 u16 pci_err;
2498
2499 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2500 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2501 if (net_ratelimit())
2502 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2503 pci_err);
2504
2505 sky2_pci_write16(hw, PCI_STATUS,
2506 pci_err | PCI_STATUS_ERROR_BITS);
2507 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2508 }
2509
2510 if (status & Y2_IS_PCI_EXP) {
2511 /* PCI-Express uncorrectable Error occurred */
2512 u32 err;
2513
2514 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2515 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2516 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2517 0xfffffffful);
2518 if (net_ratelimit())
2519 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2520
2521 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2522 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2523 }
2524
2525 if (status & Y2_HWE_L1_MASK)
2526 sky2_hw_error(hw, 0, status);
2527 status >>= 8;
2528 if (status & Y2_HWE_L1_MASK)
2529 sky2_hw_error(hw, 1, status);
2530 }
2531
2532 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2533 {
2534 struct net_device *dev = hw->dev[port];
2535 struct sky2_port *sky2 = netdev_priv(dev);
2536 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2537
2538 if (netif_msg_intr(sky2))
2539 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2540 dev->name, status);
2541
2542 if (status & GM_IS_RX_CO_OV)
2543 gma_read16(hw, port, GM_RX_IRQ_SRC);
2544
2545 if (status & GM_IS_TX_CO_OV)
2546 gma_read16(hw, port, GM_TX_IRQ_SRC);
2547
2548 if (status & GM_IS_RX_FF_OR) {
2549 ++dev->stats.rx_fifo_errors;
2550 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2551 }
2552
2553 if (status & GM_IS_TX_FF_UR) {
2554 ++dev->stats.tx_fifo_errors;
2555 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2556 }
2557 }
2558
2559 /* This should never happen it is a bug. */
2560 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2561 u16 q, unsigned ring_size)
2562 {
2563 struct net_device *dev = hw->dev[port];
2564 struct sky2_port *sky2 = netdev_priv(dev);
2565 unsigned idx;
2566 const u64 *le = (q == Q_R1 || q == Q_R2)
2567 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2568
2569 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2570 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2571 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2572 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2573
2574 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2575 }
2576
2577 static int sky2_rx_hung(struct net_device *dev)
2578 {
2579 struct sky2_port *sky2 = netdev_priv(dev);
2580 struct sky2_hw *hw = sky2->hw;
2581 unsigned port = sky2->port;
2582 unsigned rxq = rxqaddr[port];
2583 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2584 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2585 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2586 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2587
2588 /* If idle and MAC or PCI is stuck */
2589 if (sky2->check.last == dev->last_rx &&
2590 ((mac_rp == sky2->check.mac_rp &&
2591 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2592 /* Check if the PCI RX hang */
2593 (fifo_rp == sky2->check.fifo_rp &&
2594 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2595 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2596 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2597 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2598 return 1;
2599 } else {
2600 sky2->check.last = dev->last_rx;
2601 sky2->check.mac_rp = mac_rp;
2602 sky2->check.mac_lev = mac_lev;
2603 sky2->check.fifo_rp = fifo_rp;
2604 sky2->check.fifo_lev = fifo_lev;
2605 return 0;
2606 }
2607 }
2608
2609 static void sky2_watchdog(unsigned long arg)
2610 {
2611 struct sky2_hw *hw = (struct sky2_hw *) arg;
2612
2613 /* Check for lost IRQ once a second */
2614 if (sky2_read32(hw, B0_ISRC)) {
2615 napi_schedule(&hw->napi);
2616 } else {
2617 int i, active = 0;
2618
2619 for (i = 0; i < hw->ports; i++) {
2620 struct net_device *dev = hw->dev[i];
2621 if (!netif_running(dev))
2622 continue;
2623 ++active;
2624
2625 /* For chips with Rx FIFO, check if stuck */
2626 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2627 sky2_rx_hung(dev)) {
2628 pr_info(PFX "%s: receiver hang detected\n",
2629 dev->name);
2630 schedule_work(&hw->restart_work);
2631 return;
2632 }
2633 }
2634
2635 if (active == 0)
2636 return;
2637 }
2638
2639 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2640 }
2641
2642 /* Hardware/software error handling */
2643 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2644 {
2645 if (net_ratelimit())
2646 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2647
2648 if (status & Y2_IS_HW_ERR)
2649 sky2_hw_intr(hw);
2650
2651 if (status & Y2_IS_IRQ_MAC1)
2652 sky2_mac_intr(hw, 0);
2653
2654 if (status & Y2_IS_IRQ_MAC2)
2655 sky2_mac_intr(hw, 1);
2656
2657 if (status & Y2_IS_CHK_RX1)
2658 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2659
2660 if (status & Y2_IS_CHK_RX2)
2661 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2662
2663 if (status & Y2_IS_CHK_TXA1)
2664 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2665
2666 if (status & Y2_IS_CHK_TXA2)
2667 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2668 }
2669
2670 static int sky2_poll(struct napi_struct *napi, int work_limit)
2671 {
2672 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2673 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2674 int work_done = 0;
2675 u16 idx;
2676
2677 if (unlikely(status & Y2_IS_ERROR))
2678 sky2_err_intr(hw, status);
2679
2680 if (status & Y2_IS_IRQ_PHY1)
2681 sky2_phy_intr(hw, 0);
2682
2683 if (status & Y2_IS_IRQ_PHY2)
2684 sky2_phy_intr(hw, 1);
2685
2686 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2687 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2688
2689 if (work_done >= work_limit)
2690 goto done;
2691 }
2692
2693 /* Bug/Errata workaround?
2694 * Need to kick the TX irq moderation timer.
2695 */
2696 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2697 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2698 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2699 }
2700 napi_complete(napi);
2701 sky2_read32(hw, B0_Y2_SP_LISR);
2702 done:
2703
2704 return work_done;
2705 }
2706
2707 static irqreturn_t sky2_intr(int irq, void *dev_id)
2708 {
2709 struct sky2_hw *hw = dev_id;
2710 u32 status;
2711
2712 /* Reading this mask interrupts as side effect */
2713 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2714 if (status == 0 || status == ~0)
2715 return IRQ_NONE;
2716
2717 prefetch(&hw->st_le[hw->st_idx]);
2718
2719 napi_schedule(&hw->napi);
2720
2721 return IRQ_HANDLED;
2722 }
2723
2724 #ifdef CONFIG_NET_POLL_CONTROLLER
2725 static void sky2_netpoll(struct net_device *dev)
2726 {
2727 struct sky2_port *sky2 = netdev_priv(dev);
2728
2729 napi_schedule(&sky2->hw->napi);
2730 }
2731 #endif
2732
2733 /* Chip internal frequency for clock calculations */
2734 static u32 sky2_mhz(const struct sky2_hw *hw)
2735 {
2736 switch (hw->chip_id) {
2737 case CHIP_ID_YUKON_EC:
2738 case CHIP_ID_YUKON_EC_U:
2739 case CHIP_ID_YUKON_EX:
2740 case CHIP_ID_YUKON_SUPR:
2741 return 125;
2742
2743 case CHIP_ID_YUKON_FE:
2744 return 100;
2745
2746 case CHIP_ID_YUKON_FE_P:
2747 return 50;
2748
2749 case CHIP_ID_YUKON_XL:
2750 return 156;
2751
2752 default:
2753 BUG();
2754 }
2755 }
2756
2757 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2758 {
2759 return sky2_mhz(hw) * us;
2760 }
2761
2762 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2763 {
2764 return clk / sky2_mhz(hw);
2765 }
2766
2767
2768 static int __devinit sky2_init(struct sky2_hw *hw)
2769 {
2770 u8 t8;
2771
2772 /* Enable all clocks and check for bad PCI access */
2773 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2774
2775 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2776
2777 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2778 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2779
2780 switch(hw->chip_id) {
2781 case CHIP_ID_YUKON_XL:
2782 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2783 break;
2784
2785 case CHIP_ID_YUKON_EC_U:
2786 hw->flags = SKY2_HW_GIGABIT
2787 | SKY2_HW_NEWER_PHY
2788 | SKY2_HW_ADV_POWER_CTL;
2789 break;
2790
2791 case CHIP_ID_YUKON_EX:
2792 hw->flags = SKY2_HW_GIGABIT
2793 | SKY2_HW_NEWER_PHY
2794 | SKY2_HW_NEW_LE
2795 | SKY2_HW_ADV_POWER_CTL;
2796
2797 /* New transmit checksum */
2798 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2799 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2800 break;
2801
2802 case CHIP_ID_YUKON_EC:
2803 /* This rev is really old, and requires untested workarounds */
2804 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2805 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2806 return -EOPNOTSUPP;
2807 }
2808 hw->flags = SKY2_HW_GIGABIT;
2809 break;
2810
2811 case CHIP_ID_YUKON_FE:
2812 break;
2813
2814 case CHIP_ID_YUKON_FE_P:
2815 hw->flags = SKY2_HW_NEWER_PHY
2816 | SKY2_HW_NEW_LE
2817 | SKY2_HW_AUTO_TX_SUM
2818 | SKY2_HW_ADV_POWER_CTL;
2819 break;
2820
2821 case CHIP_ID_YUKON_SUPR:
2822 hw->flags = SKY2_HW_GIGABIT
2823 | SKY2_HW_NEWER_PHY
2824 | SKY2_HW_NEW_LE
2825 | SKY2_HW_AUTO_TX_SUM
2826 | SKY2_HW_ADV_POWER_CTL;
2827 break;
2828
2829 default:
2830 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2831 hw->chip_id);
2832 return -EOPNOTSUPP;
2833 }
2834
2835 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2836 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2837 hw->flags |= SKY2_HW_FIBRE_PHY;
2838
2839
2840 hw->ports = 1;
2841 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2842 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2843 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2844 ++hw->ports;
2845 }
2846
2847 return 0;
2848 }
2849
2850 static void sky2_reset(struct sky2_hw *hw)
2851 {
2852 struct pci_dev *pdev = hw->pdev;
2853 u16 status;
2854 int i, cap;
2855 u32 hwe_mask = Y2_HWE_ALL_MASK;
2856
2857 /* disable ASF */
2858 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2859 status = sky2_read16(hw, HCU_CCSR);
2860 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2861 HCU_CCSR_UC_STATE_MSK);
2862 sky2_write16(hw, HCU_CCSR, status);
2863 } else
2864 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2865 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2866
2867 /* do a SW reset */
2868 sky2_write8(hw, B0_CTST, CS_RST_SET);
2869 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2870
2871 /* allow writes to PCI config */
2872 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2873
2874 /* clear PCI errors, if any */
2875 status = sky2_pci_read16(hw, PCI_STATUS);
2876 status |= PCI_STATUS_ERROR_BITS;
2877 sky2_pci_write16(hw, PCI_STATUS, status);
2878
2879 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2880
2881 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2882 if (cap) {
2883 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2884 0xfffffffful);
2885
2886 /* If error bit is stuck on ignore it */
2887 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2888 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2889 else
2890 hwe_mask |= Y2_IS_PCI_EXP;
2891 }
2892
2893 sky2_power_on(hw);
2894 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2895
2896 for (i = 0; i < hw->ports; i++) {
2897 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2898 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2899
2900 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2901 hw->chip_id == CHIP_ID_YUKON_SUPR)
2902 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2903 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2904 | GMC_BYP_RETR_ON);
2905 }
2906
2907 /* Clear I2C IRQ noise */
2908 sky2_write32(hw, B2_I2C_IRQ, 1);
2909
2910 /* turn off hardware timer (unused) */
2911 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2912 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2913
2914 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2915
2916 /* Turn off descriptor polling */
2917 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2918
2919 /* Turn off receive timestamp */
2920 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2921 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2922
2923 /* enable the Tx Arbiters */
2924 for (i = 0; i < hw->ports; i++)
2925 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2926
2927 /* Initialize ram interface */
2928 for (i = 0; i < hw->ports; i++) {
2929 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2930
2931 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2932 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2933 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2934 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2935 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2936 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2937 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2938 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2939 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2940 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2941 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2942 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2943 }
2944
2945 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2946
2947 for (i = 0; i < hw->ports; i++)
2948 sky2_gmac_reset(hw, i);
2949
2950 memset(hw->st_le, 0, STATUS_LE_BYTES);
2951 hw->st_idx = 0;
2952
2953 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2954 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2955
2956 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2957 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2958
2959 /* Set the list last index */
2960 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2961
2962 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2963 sky2_write8(hw, STAT_FIFO_WM, 16);
2964
2965 /* set Status-FIFO ISR watermark */
2966 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2967 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2968 else
2969 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2970
2971 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2972 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2973 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2974
2975 /* enable status unit */
2976 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2977
2978 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2979 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2980 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2981 }
2982
2983 static void sky2_restart(struct work_struct *work)
2984 {
2985 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2986 struct net_device *dev;
2987 int i, err;
2988
2989 rtnl_lock();
2990 for (i = 0; i < hw->ports; i++) {
2991 dev = hw->dev[i];
2992 if (netif_running(dev))
2993 sky2_down(dev);
2994 }
2995
2996 napi_disable(&hw->napi);
2997 sky2_write32(hw, B0_IMSK, 0);
2998 sky2_reset(hw);
2999 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3000 napi_enable(&hw->napi);
3001
3002 for (i = 0; i < hw->ports; i++) {
3003 dev = hw->dev[i];
3004 if (netif_running(dev)) {
3005 err = sky2_up(dev);
3006 if (err) {
3007 printk(KERN_INFO PFX "%s: could not restart %d\n",
3008 dev->name, err);
3009 dev_close(dev);
3010 }
3011 }
3012 }
3013
3014 rtnl_unlock();
3015 }
3016
3017 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3018 {
3019 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3020 }
3021
3022 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3023 {
3024 const struct sky2_port *sky2 = netdev_priv(dev);
3025
3026 wol->supported = sky2_wol_supported(sky2->hw);
3027 wol->wolopts = sky2->wol;
3028 }
3029
3030 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3031 {
3032 struct sky2_port *sky2 = netdev_priv(dev);
3033 struct sky2_hw *hw = sky2->hw;
3034
3035 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3036 return -EOPNOTSUPP;
3037
3038 sky2->wol = wol->wolopts;
3039
3040 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3041 hw->chip_id == CHIP_ID_YUKON_EX ||
3042 hw->chip_id == CHIP_ID_YUKON_FE_P)
3043 sky2_write32(hw, B0_CTST, sky2->wol
3044 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3045
3046 if (!netif_running(dev))
3047 sky2_wol_init(sky2);
3048 return 0;
3049 }
3050
3051 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3052 {
3053 if (sky2_is_copper(hw)) {
3054 u32 modes = SUPPORTED_10baseT_Half
3055 | SUPPORTED_10baseT_Full
3056 | SUPPORTED_100baseT_Half
3057 | SUPPORTED_100baseT_Full
3058 | SUPPORTED_Autoneg | SUPPORTED_TP;
3059
3060 if (hw->flags & SKY2_HW_GIGABIT)
3061 modes |= SUPPORTED_1000baseT_Half
3062 | SUPPORTED_1000baseT_Full;
3063 return modes;
3064 } else
3065 return SUPPORTED_1000baseT_Half
3066 | SUPPORTED_1000baseT_Full
3067 | SUPPORTED_Autoneg
3068 | SUPPORTED_FIBRE;
3069 }
3070
3071 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3072 {
3073 struct sky2_port *sky2 = netdev_priv(dev);
3074 struct sky2_hw *hw = sky2->hw;
3075
3076 ecmd->transceiver = XCVR_INTERNAL;
3077 ecmd->supported = sky2_supported_modes(hw);
3078 ecmd->phy_address = PHY_ADDR_MARV;
3079 if (sky2_is_copper(hw)) {
3080 ecmd->port = PORT_TP;
3081 ecmd->speed = sky2->speed;
3082 } else {
3083 ecmd->speed = SPEED_1000;
3084 ecmd->port = PORT_FIBRE;
3085 }
3086
3087 ecmd->advertising = sky2->advertising;
3088 ecmd->autoneg = sky2->autoneg;
3089 ecmd->duplex = sky2->duplex;
3090 return 0;
3091 }
3092
3093 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3094 {
3095 struct sky2_port *sky2 = netdev_priv(dev);
3096 const struct sky2_hw *hw = sky2->hw;
3097 u32 supported = sky2_supported_modes(hw);
3098
3099 if (ecmd->autoneg == AUTONEG_ENABLE) {
3100 ecmd->advertising = supported;
3101 sky2->duplex = -1;
3102 sky2->speed = -1;
3103 } else {
3104 u32 setting;
3105
3106 switch (ecmd->speed) {
3107 case SPEED_1000:
3108 if (ecmd->duplex == DUPLEX_FULL)
3109 setting = SUPPORTED_1000baseT_Full;
3110 else if (ecmd->duplex == DUPLEX_HALF)
3111 setting = SUPPORTED_1000baseT_Half;
3112 else
3113 return -EINVAL;
3114 break;
3115 case SPEED_100:
3116 if (ecmd->duplex == DUPLEX_FULL)
3117 setting = SUPPORTED_100baseT_Full;
3118 else if (ecmd->duplex == DUPLEX_HALF)
3119 setting = SUPPORTED_100baseT_Half;
3120 else
3121 return -EINVAL;
3122 break;
3123
3124 case SPEED_10:
3125 if (ecmd->duplex == DUPLEX_FULL)
3126 setting = SUPPORTED_10baseT_Full;
3127 else if (ecmd->duplex == DUPLEX_HALF)
3128 setting = SUPPORTED_10baseT_Half;
3129 else
3130 return -EINVAL;
3131 break;
3132 default:
3133 return -EINVAL;
3134 }
3135
3136 if ((setting & supported) == 0)
3137 return -EINVAL;
3138
3139 sky2->speed = ecmd->speed;
3140 sky2->duplex = ecmd->duplex;
3141 }
3142
3143 sky2->autoneg = ecmd->autoneg;
3144 sky2->advertising = ecmd->advertising;
3145
3146 if (netif_running(dev)) {
3147 sky2_phy_reinit(sky2);
3148 sky2_set_multicast(dev);
3149 }
3150
3151 return 0;
3152 }
3153
3154 static void sky2_get_drvinfo(struct net_device *dev,
3155 struct ethtool_drvinfo *info)
3156 {
3157 struct sky2_port *sky2 = netdev_priv(dev);
3158
3159 strcpy(info->driver, DRV_NAME);
3160 strcpy(info->version, DRV_VERSION);
3161 strcpy(info->fw_version, "N/A");
3162 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3163 }
3164
3165 static const struct sky2_stat {
3166 char name[ETH_GSTRING_LEN];
3167 u16 offset;
3168 } sky2_stats[] = {
3169 { "tx_bytes", GM_TXO_OK_HI },
3170 { "rx_bytes", GM_RXO_OK_HI },
3171 { "tx_broadcast", GM_TXF_BC_OK },
3172 { "rx_broadcast", GM_RXF_BC_OK },
3173 { "tx_multicast", GM_TXF_MC_OK },
3174 { "rx_multicast", GM_RXF_MC_OK },
3175 { "tx_unicast", GM_TXF_UC_OK },
3176 { "rx_unicast", GM_RXF_UC_OK },
3177 { "tx_mac_pause", GM_TXF_MPAUSE },
3178 { "rx_mac_pause", GM_RXF_MPAUSE },
3179 { "collisions", GM_TXF_COL },
3180 { "late_collision",GM_TXF_LAT_COL },
3181 { "aborted", GM_TXF_ABO_COL },
3182 { "single_collisions", GM_TXF_SNG_COL },
3183 { "multi_collisions", GM_TXF_MUL_COL },
3184
3185 { "rx_short", GM_RXF_SHT },
3186 { "rx_runt", GM_RXE_FRAG },
3187 { "rx_64_byte_packets", GM_RXF_64B },
3188 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3189 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3190 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3191 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3192 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3193 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3194 { "rx_too_long", GM_RXF_LNG_ERR },
3195 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3196 { "rx_jabber", GM_RXF_JAB_PKT },
3197 { "rx_fcs_error", GM_RXF_FCS_ERR },
3198
3199 { "tx_64_byte_packets", GM_TXF_64B },
3200 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3201 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3202 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3203 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3204 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3205 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3206 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3207 };
3208
3209 static u32 sky2_get_rx_csum(struct net_device *dev)
3210 {
3211 struct sky2_port *sky2 = netdev_priv(dev);
3212
3213 return sky2->rx_csum;
3214 }
3215
3216 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3217 {
3218 struct sky2_port *sky2 = netdev_priv(dev);
3219
3220 sky2->rx_csum = data;
3221
3222 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3223 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3224
3225 return 0;
3226 }
3227
3228 static u32 sky2_get_msglevel(struct net_device *netdev)
3229 {
3230 struct sky2_port *sky2 = netdev_priv(netdev);
3231 return sky2->msg_enable;
3232 }
3233
3234 static int sky2_nway_reset(struct net_device *dev)
3235 {
3236 struct sky2_port *sky2 = netdev_priv(dev);
3237
3238 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3239 return -EINVAL;
3240
3241 sky2_phy_reinit(sky2);
3242 sky2_set_multicast(dev);
3243
3244 return 0;
3245 }
3246
3247 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3248 {
3249 struct sky2_hw *hw = sky2->hw;
3250 unsigned port = sky2->port;
3251 int i;
3252
3253 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3254 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3255 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3256 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3257
3258 for (i = 2; i < count; i++)
3259 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3260 }
3261
3262 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3263 {
3264 struct sky2_port *sky2 = netdev_priv(netdev);
3265 sky2->msg_enable = value;
3266 }
3267
3268 static int sky2_get_sset_count(struct net_device *dev, int sset)
3269 {
3270 switch (sset) {
3271 case ETH_SS_STATS:
3272 return ARRAY_SIZE(sky2_stats);
3273 default:
3274 return -EOPNOTSUPP;
3275 }
3276 }
3277
3278 static void sky2_get_ethtool_stats(struct net_device *dev,
3279 struct ethtool_stats *stats, u64 * data)
3280 {
3281 struct sky2_port *sky2 = netdev_priv(dev);
3282
3283 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3284 }
3285
3286 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3287 {
3288 int i;
3289
3290 switch (stringset) {
3291 case ETH_SS_STATS:
3292 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3293 memcpy(data + i * ETH_GSTRING_LEN,
3294 sky2_stats[i].name, ETH_GSTRING_LEN);
3295 break;
3296 }
3297 }
3298
3299 static int sky2_set_mac_address(struct net_device *dev, void *p)
3300 {
3301 struct sky2_port *sky2 = netdev_priv(dev);
3302 struct sky2_hw *hw = sky2->hw;
3303 unsigned port = sky2->port;
3304 const struct sockaddr *addr = p;
3305
3306 if (!is_valid_ether_addr(addr->sa_data))
3307 return -EADDRNOTAVAIL;
3308
3309 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3310 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3311 dev->dev_addr, ETH_ALEN);
3312 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3313 dev->dev_addr, ETH_ALEN);
3314
3315 /* virtual address for data */
3316 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3317
3318 /* physical address: used for pause frames */
3319 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3320
3321 return 0;
3322 }
3323
3324 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3325 {
3326 u32 bit;
3327
3328 bit = ether_crc(ETH_ALEN, addr) & 63;
3329 filter[bit >> 3] |= 1 << (bit & 7);
3330 }
3331
3332 static void sky2_set_multicast(struct net_device *dev)
3333 {
3334 struct sky2_port *sky2 = netdev_priv(dev);
3335 struct sky2_hw *hw = sky2->hw;
3336 unsigned port = sky2->port;
3337 struct dev_mc_list *list = dev->mc_list;
3338 u16 reg;
3339 u8 filter[8];
3340 int rx_pause;
3341 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3342
3343 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3344 memset(filter, 0, sizeof(filter));
3345
3346 reg = gma_read16(hw, port, GM_RX_CTRL);
3347 reg |= GM_RXCR_UCF_ENA;
3348
3349 if (dev->flags & IFF_PROMISC) /* promiscuous */
3350 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3351 else if (dev->flags & IFF_ALLMULTI)
3352 memset(filter, 0xff, sizeof(filter));
3353 else if (dev->mc_count == 0 && !rx_pause)
3354 reg &= ~GM_RXCR_MCF_ENA;
3355 else {
3356 int i;
3357 reg |= GM_RXCR_MCF_ENA;
3358
3359 if (rx_pause)
3360 sky2_add_filter(filter, pause_mc_addr);
3361
3362 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3363 sky2_add_filter(filter, list->dmi_addr);
3364 }
3365
3366 gma_write16(hw, port, GM_MC_ADDR_H1,
3367 (u16) filter[0] | ((u16) filter[1] << 8));
3368 gma_write16(hw, port, GM_MC_ADDR_H2,
3369 (u16) filter[2] | ((u16) filter[3] << 8));
3370 gma_write16(hw, port, GM_MC_ADDR_H3,
3371 (u16) filter[4] | ((u16) filter[5] << 8));
3372 gma_write16(hw, port, GM_MC_ADDR_H4,
3373 (u16) filter[6] | ((u16) filter[7] << 8));
3374
3375 gma_write16(hw, port, GM_RX_CTRL, reg);
3376 }
3377
3378 /* Can have one global because blinking is controlled by
3379 * ethtool and that is always under RTNL mutex
3380 */
3381 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3382 {
3383 struct sky2_hw *hw = sky2->hw;
3384 unsigned port = sky2->port;
3385
3386 spin_lock_bh(&sky2->phy_lock);
3387 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3388 hw->chip_id == CHIP_ID_YUKON_EX ||
3389 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3390 u16 pg;
3391 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3392 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3393
3394 switch (mode) {
3395 case MO_LED_OFF:
3396 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3397 PHY_M_LEDC_LOS_CTRL(8) |
3398 PHY_M_LEDC_INIT_CTRL(8) |
3399 PHY_M_LEDC_STA1_CTRL(8) |
3400 PHY_M_LEDC_STA0_CTRL(8));
3401 break;
3402 case MO_LED_ON:
3403 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3404 PHY_M_LEDC_LOS_CTRL(9) |
3405 PHY_M_LEDC_INIT_CTRL(9) |
3406 PHY_M_LEDC_STA1_CTRL(9) |
3407 PHY_M_LEDC_STA0_CTRL(9));
3408 break;
3409 case MO_LED_BLINK:
3410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3411 PHY_M_LEDC_LOS_CTRL(0xa) |
3412 PHY_M_LEDC_INIT_CTRL(0xa) |
3413 PHY_M_LEDC_STA1_CTRL(0xa) |
3414 PHY_M_LEDC_STA0_CTRL(0xa));
3415 break;
3416 case MO_LED_NORM:
3417 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3418 PHY_M_LEDC_LOS_CTRL(1) |
3419 PHY_M_LEDC_INIT_CTRL(8) |
3420 PHY_M_LEDC_STA1_CTRL(7) |
3421 PHY_M_LEDC_STA0_CTRL(7));
3422 }
3423
3424 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3425 } else
3426 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3427 PHY_M_LED_MO_DUP(mode) |
3428 PHY_M_LED_MO_10(mode) |
3429 PHY_M_LED_MO_100(mode) |
3430 PHY_M_LED_MO_1000(mode) |
3431 PHY_M_LED_MO_RX(mode) |
3432 PHY_M_LED_MO_TX(mode));
3433
3434 spin_unlock_bh(&sky2->phy_lock);
3435 }
3436
3437 /* blink LED's for finding board */
3438 static int sky2_phys_id(struct net_device *dev, u32 data)
3439 {
3440 struct sky2_port *sky2 = netdev_priv(dev);
3441 unsigned int i;
3442
3443 if (data == 0)
3444 data = UINT_MAX;
3445
3446 for (i = 0; i < data; i++) {
3447 sky2_led(sky2, MO_LED_ON);
3448 if (msleep_interruptible(500))
3449 break;
3450 sky2_led(sky2, MO_LED_OFF);
3451 if (msleep_interruptible(500))
3452 break;
3453 }
3454 sky2_led(sky2, MO_LED_NORM);
3455
3456 return 0;
3457 }
3458
3459 static void sky2_get_pauseparam(struct net_device *dev,
3460 struct ethtool_pauseparam *ecmd)
3461 {
3462 struct sky2_port *sky2 = netdev_priv(dev);
3463
3464 switch (sky2->flow_mode) {
3465 case FC_NONE:
3466 ecmd->tx_pause = ecmd->rx_pause = 0;
3467 break;
3468 case FC_TX:
3469 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3470 break;
3471 case FC_RX:
3472 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3473 break;
3474 case FC_BOTH:
3475 ecmd->tx_pause = ecmd->rx_pause = 1;
3476 }
3477
3478 ecmd->autoneg = sky2->autoneg;
3479 }
3480
3481 static int sky2_set_pauseparam(struct net_device *dev,
3482 struct ethtool_pauseparam *ecmd)
3483 {
3484 struct sky2_port *sky2 = netdev_priv(dev);
3485
3486 sky2->autoneg = ecmd->autoneg;
3487 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3488
3489 if (netif_running(dev))
3490 sky2_phy_reinit(sky2);
3491
3492 return 0;
3493 }
3494
3495 static int sky2_get_coalesce(struct net_device *dev,
3496 struct ethtool_coalesce *ecmd)
3497 {
3498 struct sky2_port *sky2 = netdev_priv(dev);
3499 struct sky2_hw *hw = sky2->hw;
3500
3501 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3502 ecmd->tx_coalesce_usecs = 0;
3503 else {
3504 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3505 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3506 }
3507 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3508
3509 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3510 ecmd->rx_coalesce_usecs = 0;
3511 else {
3512 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3513 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3514 }
3515 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3516
3517 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3518 ecmd->rx_coalesce_usecs_irq = 0;
3519 else {
3520 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3521 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3522 }
3523
3524 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3525
3526 return 0;
3527 }
3528
3529 /* Note: this affect both ports */
3530 static int sky2_set_coalesce(struct net_device *dev,
3531 struct ethtool_coalesce *ecmd)
3532 {
3533 struct sky2_port *sky2 = netdev_priv(dev);
3534 struct sky2_hw *hw = sky2->hw;
3535 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3536
3537 if (ecmd->tx_coalesce_usecs > tmax ||
3538 ecmd->rx_coalesce_usecs > tmax ||
3539 ecmd->rx_coalesce_usecs_irq > tmax)
3540 return -EINVAL;
3541
3542 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3543 return -EINVAL;
3544 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3545 return -EINVAL;
3546 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3547 return -EINVAL;
3548
3549 if (ecmd->tx_coalesce_usecs == 0)
3550 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3551 else {
3552 sky2_write32(hw, STAT_TX_TIMER_INI,
3553 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3554 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3555 }
3556 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3557
3558 if (ecmd->rx_coalesce_usecs == 0)
3559 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3560 else {
3561 sky2_write32(hw, STAT_LEV_TIMER_INI,
3562 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3563 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3564 }
3565 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3566
3567 if (ecmd->rx_coalesce_usecs_irq == 0)
3568 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3569 else {
3570 sky2_write32(hw, STAT_ISR_TIMER_INI,
3571 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3572 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3573 }
3574 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3575 return 0;
3576 }
3577
3578 static void sky2_get_ringparam(struct net_device *dev,
3579 struct ethtool_ringparam *ering)
3580 {
3581 struct sky2_port *sky2 = netdev_priv(dev);
3582
3583 ering->rx_max_pending = RX_MAX_PENDING;
3584 ering->rx_mini_max_pending = 0;
3585 ering->rx_jumbo_max_pending = 0;
3586 ering->tx_max_pending = TX_RING_SIZE - 1;
3587
3588 ering->rx_pending = sky2->rx_pending;
3589 ering->rx_mini_pending = 0;
3590 ering->rx_jumbo_pending = 0;
3591 ering->tx_pending = sky2->tx_pending;
3592 }
3593
3594 static int sky2_set_ringparam(struct net_device *dev,
3595 struct ethtool_ringparam *ering)
3596 {
3597 struct sky2_port *sky2 = netdev_priv(dev);
3598 int err = 0;
3599
3600 if (ering->rx_pending > RX_MAX_PENDING ||
3601 ering->rx_pending < 8 ||
3602 ering->tx_pending < MAX_SKB_TX_LE ||
3603 ering->tx_pending > TX_RING_SIZE - 1)
3604 return -EINVAL;
3605
3606 if (netif_running(dev))
3607 sky2_down(dev);
3608
3609 sky2->rx_pending = ering->rx_pending;
3610 sky2->tx_pending = ering->tx_pending;
3611
3612 if (netif_running(dev)) {
3613 err = sky2_up(dev);
3614 if (err)
3615 dev_close(dev);
3616 }
3617
3618 return err;
3619 }
3620
3621 static int sky2_get_regs_len(struct net_device *dev)
3622 {
3623 return 0x4000;
3624 }
3625
3626 /*
3627 * Returns copy of control register region
3628 * Note: ethtool_get_regs always provides full size (16k) buffer
3629 */
3630 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3631 void *p)
3632 {
3633 const struct sky2_port *sky2 = netdev_priv(dev);
3634 const void __iomem *io = sky2->hw->regs;
3635 unsigned int b;
3636
3637 regs->version = 1;
3638
3639 for (b = 0; b < 128; b++) {
3640 /* This complicated switch statement is to make sure and
3641 * only access regions that are unreserved.
3642 * Some blocks are only valid on dual port cards.
3643 * and block 3 has some special diagnostic registers that
3644 * are poison.
3645 */
3646 switch (b) {
3647 case 3:
3648 /* skip diagnostic ram region */
3649 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3650 break;
3651
3652 /* dual port cards only */
3653 case 5: /* Tx Arbiter 2 */
3654 case 9: /* RX2 */
3655 case 14 ... 15: /* TX2 */
3656 case 17: case 19: /* Ram Buffer 2 */
3657 case 22 ... 23: /* Tx Ram Buffer 2 */
3658 case 25: /* Rx MAC Fifo 1 */
3659 case 27: /* Tx MAC Fifo 2 */
3660 case 31: /* GPHY 2 */
3661 case 40 ... 47: /* Pattern Ram 2 */
3662 case 52: case 54: /* TCP Segmentation 2 */
3663 case 112 ... 116: /* GMAC 2 */
3664 if (sky2->hw->ports == 1)
3665 goto reserved;
3666 /* fall through */
3667 case 0: /* Control */
3668 case 2: /* Mac address */
3669 case 4: /* Tx Arbiter 1 */
3670 case 7: /* PCI express reg */
3671 case 8: /* RX1 */
3672 case 12 ... 13: /* TX1 */
3673 case 16: case 18:/* Rx Ram Buffer 1 */
3674 case 20 ... 21: /* Tx Ram Buffer 1 */
3675 case 24: /* Rx MAC Fifo 1 */
3676 case 26: /* Tx MAC Fifo 1 */
3677 case 28 ... 29: /* Descriptor and status unit */
3678 case 30: /* GPHY 1*/
3679 case 32 ... 39: /* Pattern Ram 1 */
3680 case 48: case 50: /* TCP Segmentation 1 */
3681 case 56 ... 60: /* PCI space */
3682 case 80 ... 84: /* GMAC 1 */
3683 memcpy_fromio(p, io, 128);
3684 break;
3685 default:
3686 reserved:
3687 memset(p, 0, 128);
3688 }
3689
3690 p += 128;
3691 io += 128;
3692 }
3693 }
3694
3695 /* In order to do Jumbo packets on these chips, need to turn off the
3696 * transmit store/forward. Therefore checksum offload won't work.
3697 */
3698 static int no_tx_offload(struct net_device *dev)
3699 {
3700 const struct sky2_port *sky2 = netdev_priv(dev);
3701 const struct sky2_hw *hw = sky2->hw;
3702
3703 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3704 }
3705
3706 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3707 {
3708 if (data && no_tx_offload(dev))
3709 return -EINVAL;
3710
3711 return ethtool_op_set_tx_csum(dev, data);
3712 }
3713
3714
3715 static int sky2_set_tso(struct net_device *dev, u32 data)
3716 {
3717 if (data && no_tx_offload(dev))
3718 return -EINVAL;
3719
3720 return ethtool_op_set_tso(dev, data);
3721 }
3722
3723 static int sky2_get_eeprom_len(struct net_device *dev)
3724 {
3725 struct sky2_port *sky2 = netdev_priv(dev);
3726 struct sky2_hw *hw = sky2->hw;
3727 u16 reg2;
3728
3729 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3730 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3731 }
3732
3733 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3734 {
3735 u32 val;
3736
3737 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3738
3739 do {
3740 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3741 } while (!(offset & PCI_VPD_ADDR_F));
3742
3743 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3744 return val;
3745 }
3746
3747 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3748 {
3749 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3750 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3751 do {
3752 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3753 } while (offset & PCI_VPD_ADDR_F);
3754 }
3755
3756 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3757 u8 *data)
3758 {
3759 struct sky2_port *sky2 = netdev_priv(dev);
3760 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3761 int length = eeprom->len;
3762 u16 offset = eeprom->offset;
3763
3764 if (!cap)
3765 return -EINVAL;
3766
3767 eeprom->magic = SKY2_EEPROM_MAGIC;
3768
3769 while (length > 0) {
3770 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3771 int n = min_t(int, length, sizeof(val));
3772
3773 memcpy(data, &val, n);
3774 length -= n;
3775 data += n;
3776 offset += n;
3777 }
3778 return 0;
3779 }
3780
3781 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3782 u8 *data)
3783 {
3784 struct sky2_port *sky2 = netdev_priv(dev);
3785 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3786 int length = eeprom->len;
3787 u16 offset = eeprom->offset;
3788
3789 if (!cap)
3790 return -EINVAL;
3791
3792 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3793 return -EINVAL;
3794
3795 while (length > 0) {
3796 u32 val;
3797 int n = min_t(int, length, sizeof(val));
3798
3799 if (n < sizeof(val))
3800 val = sky2_vpd_read(sky2->hw, cap, offset);
3801 memcpy(&val, data, n);
3802
3803 sky2_vpd_write(sky2->hw, cap, offset, val);
3804
3805 length -= n;
3806 data += n;
3807 offset += n;
3808 }
3809 return 0;
3810 }
3811
3812
3813 static const struct ethtool_ops sky2_ethtool_ops = {
3814 .get_settings = sky2_get_settings,
3815 .set_settings = sky2_set_settings,
3816 .get_drvinfo = sky2_get_drvinfo,
3817 .get_wol = sky2_get_wol,
3818 .set_wol = sky2_set_wol,
3819 .get_msglevel = sky2_get_msglevel,
3820 .set_msglevel = sky2_set_msglevel,
3821 .nway_reset = sky2_nway_reset,
3822 .get_regs_len = sky2_get_regs_len,
3823 .get_regs = sky2_get_regs,
3824 .get_link = ethtool_op_get_link,
3825 .get_eeprom_len = sky2_get_eeprom_len,
3826 .get_eeprom = sky2_get_eeprom,
3827 .set_eeprom = sky2_set_eeprom,
3828 .set_sg = ethtool_op_set_sg,
3829 .set_tx_csum = sky2_set_tx_csum,
3830 .set_tso = sky2_set_tso,
3831 .get_rx_csum = sky2_get_rx_csum,
3832 .set_rx_csum = sky2_set_rx_csum,
3833 .get_strings = sky2_get_strings,
3834 .get_coalesce = sky2_get_coalesce,
3835 .set_coalesce = sky2_set_coalesce,
3836 .get_ringparam = sky2_get_ringparam,
3837 .set_ringparam = sky2_set_ringparam,
3838 .get_pauseparam = sky2_get_pauseparam,
3839 .set_pauseparam = sky2_set_pauseparam,
3840 .phys_id = sky2_phys_id,
3841 .get_sset_count = sky2_get_sset_count,
3842 .get_ethtool_stats = sky2_get_ethtool_stats,
3843 };
3844
3845 #ifdef CONFIG_SKY2_DEBUG
3846
3847 static struct dentry *sky2_debug;
3848
3849 static int sky2_debug_show(struct seq_file *seq, void *v)
3850 {
3851 struct net_device *dev = seq->private;
3852 const struct sky2_port *sky2 = netdev_priv(dev);
3853 struct sky2_hw *hw = sky2->hw;
3854 unsigned port = sky2->port;
3855 unsigned idx, last;
3856 int sop;
3857
3858 if (!netif_running(dev))
3859 return -ENETDOWN;
3860
3861 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3862 sky2_read32(hw, B0_ISRC),
3863 sky2_read32(hw, B0_IMSK),
3864 sky2_read32(hw, B0_Y2_SP_ICR));
3865
3866 napi_disable(&hw->napi);
3867 last = sky2_read16(hw, STAT_PUT_IDX);
3868
3869 if (hw->st_idx == last)
3870 seq_puts(seq, "Status ring (empty)\n");
3871 else {
3872 seq_puts(seq, "Status ring\n");
3873 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3874 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3875 const struct sky2_status_le *le = hw->st_le + idx;
3876 seq_printf(seq, "[%d] %#x %d %#x\n",
3877 idx, le->opcode, le->length, le->status);
3878 }
3879 seq_puts(seq, "\n");
3880 }
3881
3882 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3883 sky2->tx_cons, sky2->tx_prod,
3884 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3885 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3886
3887 /* Dump contents of tx ring */
3888 sop = 1;
3889 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3890 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3891 const struct sky2_tx_le *le = sky2->tx_le + idx;
3892 u32 a = le32_to_cpu(le->addr);
3893
3894 if (sop)
3895 seq_printf(seq, "%u:", idx);
3896 sop = 0;
3897
3898 switch(le->opcode & ~HW_OWNER) {
3899 case OP_ADDR64:
3900 seq_printf(seq, " %#x:", a);
3901 break;
3902 case OP_LRGLEN:
3903 seq_printf(seq, " mtu=%d", a);
3904 break;
3905 case OP_VLAN:
3906 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3907 break;
3908 case OP_TCPLISW:
3909 seq_printf(seq, " csum=%#x", a);
3910 break;
3911 case OP_LARGESEND:
3912 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3913 break;
3914 case OP_PACKET:
3915 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3916 break;
3917 case OP_BUFFER:
3918 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3919 break;
3920 default:
3921 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3922 a, le16_to_cpu(le->length));
3923 }
3924
3925 if (le->ctrl & EOP) {
3926 seq_putc(seq, '\n');
3927 sop = 1;
3928 }
3929 }
3930
3931 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3932 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3933 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3934 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3935
3936 sky2_read32(hw, B0_Y2_SP_LISR);
3937 napi_enable(&hw->napi);
3938 return 0;
3939 }
3940
3941 static int sky2_debug_open(struct inode *inode, struct file *file)
3942 {
3943 return single_open(file, sky2_debug_show, inode->i_private);
3944 }
3945
3946 static const struct file_operations sky2_debug_fops = {
3947 .owner = THIS_MODULE,
3948 .open = sky2_debug_open,
3949 .read = seq_read,
3950 .llseek = seq_lseek,
3951 .release = single_release,
3952 };
3953
3954 /*
3955 * Use network device events to create/remove/rename
3956 * debugfs file entries
3957 */
3958 static int sky2_device_event(struct notifier_block *unused,
3959 unsigned long event, void *ptr)
3960 {
3961 struct net_device *dev = ptr;
3962 struct sky2_port *sky2 = netdev_priv(dev);
3963
3964 if (dev->open != sky2_up || !sky2_debug)
3965 return NOTIFY_DONE;
3966
3967 switch(event) {
3968 case NETDEV_CHANGENAME:
3969 if (sky2->debugfs) {
3970 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3971 sky2_debug, dev->name);
3972 }
3973 break;
3974
3975 case NETDEV_GOING_DOWN:
3976 if (sky2->debugfs) {
3977 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3978 dev->name);
3979 debugfs_remove(sky2->debugfs);
3980 sky2->debugfs = NULL;
3981 }
3982 break;
3983
3984 case NETDEV_UP:
3985 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3986 sky2_debug, dev,
3987 &sky2_debug_fops);
3988 if (IS_ERR(sky2->debugfs))
3989 sky2->debugfs = NULL;
3990 }
3991
3992 return NOTIFY_DONE;
3993 }
3994
3995 static struct notifier_block sky2_notifier = {
3996 .notifier_call = sky2_device_event,
3997 };
3998
3999
4000 static __init void sky2_debug_init(void)
4001 {
4002 struct dentry *ent;
4003
4004 ent = debugfs_create_dir("sky2", NULL);
4005 if (!ent || IS_ERR(ent))
4006 return;
4007
4008 sky2_debug = ent;
4009 register_netdevice_notifier(&sky2_notifier);
4010 }
4011
4012 static __exit void sky2_debug_cleanup(void)
4013 {
4014 if (sky2_debug) {
4015 unregister_netdevice_notifier(&sky2_notifier);
4016 debugfs_remove(sky2_debug);
4017 sky2_debug = NULL;
4018 }
4019 }
4020
4021 #else
4022 #define sky2_debug_init()
4023 #define sky2_debug_cleanup()
4024 #endif
4025
4026
4027 /* Initialize network device */
4028 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4029 unsigned port,
4030 int highmem, int wol)
4031 {
4032 struct sky2_port *sky2;
4033 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4034
4035 if (!dev) {
4036 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4037 return NULL;
4038 }
4039
4040 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4041 dev->irq = hw->pdev->irq;
4042 dev->open = sky2_up;
4043 dev->stop = sky2_down;
4044 dev->do_ioctl = sky2_ioctl;
4045 dev->hard_start_xmit = sky2_xmit_frame;
4046 dev->set_multicast_list = sky2_set_multicast;
4047 dev->set_mac_address = sky2_set_mac_address;
4048 dev->change_mtu = sky2_change_mtu;
4049 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4050 dev->tx_timeout = sky2_tx_timeout;
4051 dev->watchdog_timeo = TX_WATCHDOG;
4052 #ifdef CONFIG_NET_POLL_CONTROLLER
4053 if (port == 0)
4054 dev->poll_controller = sky2_netpoll;
4055 #endif
4056
4057 sky2 = netdev_priv(dev);
4058 sky2->netdev = dev;
4059 sky2->hw = hw;
4060 sky2->msg_enable = netif_msg_init(debug, default_msg);
4061
4062 /* Auto speed and flow control */
4063 sky2->autoneg = AUTONEG_ENABLE;
4064 sky2->flow_mode = FC_BOTH;
4065
4066 sky2->duplex = -1;
4067 sky2->speed = -1;
4068 sky2->advertising = sky2_supported_modes(hw);
4069 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4070 sky2->wol = wol;
4071
4072 spin_lock_init(&sky2->phy_lock);
4073 sky2->tx_pending = TX_DEF_PENDING;
4074 sky2->rx_pending = RX_DEF_PENDING;
4075
4076 hw->dev[port] = dev;
4077
4078 sky2->port = port;
4079
4080 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4081 if (highmem)
4082 dev->features |= NETIF_F_HIGHDMA;
4083
4084 #ifdef SKY2_VLAN_TAG_USED
4085 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4086 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4087 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4088 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4089 dev->vlan_rx_register = sky2_vlan_rx_register;
4090 }
4091 #endif
4092
4093 /* read the mac address */
4094 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4095 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4096
4097 return dev;
4098 }
4099
4100 static void __devinit sky2_show_addr(struct net_device *dev)
4101 {
4102 const struct sky2_port *sky2 = netdev_priv(dev);
4103 DECLARE_MAC_BUF(mac);
4104
4105 if (netif_msg_probe(sky2))
4106 printk(KERN_INFO PFX "%s: addr %s\n",
4107 dev->name, print_mac(mac, dev->dev_addr));
4108 }
4109
4110 /* Handle software interrupt used during MSI test */
4111 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4112 {
4113 struct sky2_hw *hw = dev_id;
4114 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4115
4116 if (status == 0)
4117 return IRQ_NONE;
4118
4119 if (status & Y2_IS_IRQ_SW) {
4120 hw->flags |= SKY2_HW_USE_MSI;
4121 wake_up(&hw->msi_wait);
4122 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4123 }
4124 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4125
4126 return IRQ_HANDLED;
4127 }
4128
4129 /* Test interrupt path by forcing a a software IRQ */
4130 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4131 {
4132 struct pci_dev *pdev = hw->pdev;
4133 int err;
4134
4135 init_waitqueue_head (&hw->msi_wait);
4136
4137 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4138
4139 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4140 if (err) {
4141 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4142 return err;
4143 }
4144
4145 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4146 sky2_read8(hw, B0_CTST);
4147
4148 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4149
4150 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4151 /* MSI test failed, go back to INTx mode */
4152 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4153 "switching to INTx mode.\n");
4154
4155 err = -EOPNOTSUPP;
4156 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4157 }
4158
4159 sky2_write32(hw, B0_IMSK, 0);
4160 sky2_read32(hw, B0_IMSK);
4161
4162 free_irq(pdev->irq, hw);
4163
4164 return err;
4165 }
4166
4167 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4168 {
4169 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4170 u16 value;
4171
4172 if (!pm)
4173 return 0;
4174 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4175 return 0;
4176 return value & PCI_PM_CTRL_PME_ENABLE;
4177 }
4178
4179 static int __devinit sky2_probe(struct pci_dev *pdev,
4180 const struct pci_device_id *ent)
4181 {
4182 struct net_device *dev;
4183 struct sky2_hw *hw;
4184 int err, using_dac = 0, wol_default;
4185
4186 err = pci_enable_device(pdev);
4187 if (err) {
4188 dev_err(&pdev->dev, "cannot enable PCI device\n");
4189 goto err_out;
4190 }
4191
4192 err = pci_request_regions(pdev, DRV_NAME);
4193 if (err) {
4194 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4195 goto err_out_disable;
4196 }
4197
4198 pci_set_master(pdev);
4199
4200 if (sizeof(dma_addr_t) > sizeof(u32) &&
4201 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4202 using_dac = 1;
4203 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4204 if (err < 0) {
4205 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4206 "for consistent allocations\n");
4207 goto err_out_free_regions;
4208 }
4209 } else {
4210 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4211 if (err) {
4212 dev_err(&pdev->dev, "no usable DMA configuration\n");
4213 goto err_out_free_regions;
4214 }
4215 }
4216
4217 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4218
4219 err = -ENOMEM;
4220 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4221 if (!hw) {
4222 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4223 goto err_out_free_regions;
4224 }
4225
4226 hw->pdev = pdev;
4227
4228 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4229 if (!hw->regs) {
4230 dev_err(&pdev->dev, "cannot map device registers\n");
4231 goto err_out_free_hw;
4232 }
4233
4234 #ifdef __BIG_ENDIAN
4235 /* The sk98lin vendor driver uses hardware byte swapping but
4236 * this driver uses software swapping.
4237 */
4238 {
4239 u32 reg;
4240 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4241 reg &= ~PCI_REV_DESC;
4242 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4243 }
4244 #endif
4245
4246 /* ring for status responses */
4247 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4248 if (!hw->st_le)
4249 goto err_out_iounmap;
4250
4251 err = sky2_init(hw);
4252 if (err)
4253 goto err_out_iounmap;
4254
4255 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4256 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4257 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4258 hw->chip_id, hw->chip_rev);
4259
4260 sky2_reset(hw);
4261
4262 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4263 if (!dev) {
4264 err = -ENOMEM;
4265 goto err_out_free_pci;
4266 }
4267
4268 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4269 err = sky2_test_msi(hw);
4270 if (err == -EOPNOTSUPP)
4271 pci_disable_msi(pdev);
4272 else if (err)
4273 goto err_out_free_netdev;
4274 }
4275
4276 err = register_netdev(dev);
4277 if (err) {
4278 dev_err(&pdev->dev, "cannot register net device\n");
4279 goto err_out_free_netdev;
4280 }
4281
4282 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4283
4284 err = request_irq(pdev->irq, sky2_intr,
4285 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4286 dev->name, hw);
4287 if (err) {
4288 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4289 goto err_out_unregister;
4290 }
4291 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4292 napi_enable(&hw->napi);
4293
4294 sky2_show_addr(dev);
4295
4296 if (hw->ports > 1) {
4297 struct net_device *dev1;
4298
4299 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4300 if (!dev1)
4301 dev_warn(&pdev->dev, "allocation for second device failed\n");
4302 else if ((err = register_netdev(dev1))) {
4303 dev_warn(&pdev->dev,
4304 "register of second port failed (%d)\n", err);
4305 hw->dev[1] = NULL;
4306 free_netdev(dev1);
4307 } else
4308 sky2_show_addr(dev1);
4309 }
4310
4311 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4312 INIT_WORK(&hw->restart_work, sky2_restart);
4313
4314 pci_set_drvdata(pdev, hw);
4315
4316 return 0;
4317
4318 err_out_unregister:
4319 if (hw->flags & SKY2_HW_USE_MSI)
4320 pci_disable_msi(pdev);
4321 unregister_netdev(dev);
4322 err_out_free_netdev:
4323 free_netdev(dev);
4324 err_out_free_pci:
4325 sky2_write8(hw, B0_CTST, CS_RST_SET);
4326 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4327 err_out_iounmap:
4328 iounmap(hw->regs);
4329 err_out_free_hw:
4330 kfree(hw);
4331 err_out_free_regions:
4332 pci_release_regions(pdev);
4333 err_out_disable:
4334 pci_disable_device(pdev);
4335 err_out:
4336 pci_set_drvdata(pdev, NULL);
4337 return err;
4338 }
4339
4340 static void __devexit sky2_remove(struct pci_dev *pdev)
4341 {
4342 struct sky2_hw *hw = pci_get_drvdata(pdev);
4343 int i;
4344
4345 if (!hw)
4346 return;
4347
4348 del_timer_sync(&hw->watchdog_timer);
4349 cancel_work_sync(&hw->restart_work);
4350
4351 for (i = hw->ports-1; i >= 0; --i)
4352 unregister_netdev(hw->dev[i]);
4353
4354 sky2_write32(hw, B0_IMSK, 0);
4355
4356 sky2_power_aux(hw);
4357
4358 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4359 sky2_write8(hw, B0_CTST, CS_RST_SET);
4360 sky2_read8(hw, B0_CTST);
4361
4362 free_irq(pdev->irq, hw);
4363 if (hw->flags & SKY2_HW_USE_MSI)
4364 pci_disable_msi(pdev);
4365 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4366 pci_release_regions(pdev);
4367 pci_disable_device(pdev);
4368
4369 for (i = hw->ports-1; i >= 0; --i)
4370 free_netdev(hw->dev[i]);
4371
4372 iounmap(hw->regs);
4373 kfree(hw);
4374
4375 pci_set_drvdata(pdev, NULL);
4376 }
4377
4378 #ifdef CONFIG_PM
4379 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4380 {
4381 struct sky2_hw *hw = pci_get_drvdata(pdev);
4382 int i, wol = 0;
4383
4384 if (!hw)
4385 return 0;
4386
4387 del_timer_sync(&hw->watchdog_timer);
4388 cancel_work_sync(&hw->restart_work);
4389
4390 for (i = 0; i < hw->ports; i++) {
4391 struct net_device *dev = hw->dev[i];
4392 struct sky2_port *sky2 = netdev_priv(dev);
4393
4394 netif_device_detach(dev);
4395 if (netif_running(dev))
4396 sky2_down(dev);
4397
4398 if (sky2->wol)
4399 sky2_wol_init(sky2);
4400
4401 wol |= sky2->wol;
4402 }
4403
4404 sky2_write32(hw, B0_IMSK, 0);
4405 napi_disable(&hw->napi);
4406 sky2_power_aux(hw);
4407
4408 pci_save_state(pdev);
4409 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4410 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4411
4412 return 0;
4413 }
4414
4415 static int sky2_resume(struct pci_dev *pdev)
4416 {
4417 struct sky2_hw *hw = pci_get_drvdata(pdev);
4418 int i, err;
4419
4420 if (!hw)
4421 return 0;
4422
4423 err = pci_set_power_state(pdev, PCI_D0);
4424 if (err)
4425 goto out;
4426
4427 err = pci_restore_state(pdev);
4428 if (err)
4429 goto out;
4430
4431 pci_enable_wake(pdev, PCI_D0, 0);
4432
4433 /* Re-enable all clocks */
4434 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4435 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4436 hw->chip_id == CHIP_ID_YUKON_FE_P)
4437 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4438
4439 sky2_reset(hw);
4440 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4441 napi_enable(&hw->napi);
4442
4443 for (i = 0; i < hw->ports; i++) {
4444 struct net_device *dev = hw->dev[i];
4445
4446 netif_device_attach(dev);
4447 if (netif_running(dev)) {
4448 err = sky2_up(dev);
4449 if (err) {
4450 printk(KERN_ERR PFX "%s: could not up: %d\n",
4451 dev->name, err);
4452 dev_close(dev);
4453 goto out;
4454 }
4455 }
4456 }
4457
4458 return 0;
4459 out:
4460 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4461 pci_disable_device(pdev);
4462 return err;
4463 }
4464 #endif
4465
4466 static void sky2_shutdown(struct pci_dev *pdev)
4467 {
4468 struct sky2_hw *hw = pci_get_drvdata(pdev);
4469 int i, wol = 0;
4470
4471 if (!hw)
4472 return;
4473
4474 del_timer_sync(&hw->watchdog_timer);
4475
4476 for (i = 0; i < hw->ports; i++) {
4477 struct net_device *dev = hw->dev[i];
4478 struct sky2_port *sky2 = netdev_priv(dev);
4479
4480 if (sky2->wol) {
4481 wol = 1;
4482 sky2_wol_init(sky2);
4483 }
4484 }
4485
4486 if (wol)
4487 sky2_power_aux(hw);
4488
4489 pci_enable_wake(pdev, PCI_D3hot, wol);
4490 pci_enable_wake(pdev, PCI_D3cold, wol);
4491
4492 pci_disable_device(pdev);
4493 pci_set_power_state(pdev, PCI_D3hot);
4494
4495 }
4496
4497 static struct pci_driver sky2_driver = {
4498 .name = DRV_NAME,
4499 .id_table = sky2_id_table,
4500 .probe = sky2_probe,
4501 .remove = __devexit_p(sky2_remove),
4502 #ifdef CONFIG_PM
4503 .suspend = sky2_suspend,
4504 .resume = sky2_resume,
4505 #endif
4506 .shutdown = sky2_shutdown,
4507 };
4508
4509 static int __init sky2_init_module(void)
4510 {
4511 sky2_debug_init();
4512 return pci_register_driver(&sky2_driver);
4513 }
4514
4515 static void __exit sky2_cleanup_module(void)
4516 {
4517 pci_unregister_driver(&sky2_driver);
4518 sky2_debug_cleanup();
4519 }
4520
4521 module_init(sky2_init_module);
4522 module_exit(sky2_cleanup_module);
4523
4524 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4525 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4526 MODULE_LICENSE("GPL");
4527 MODULE_VERSION(DRV_VERSION);
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