2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.17"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg
=
86 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
87 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
90 static int debug
= -1; /* defaults above */
91 module_param(debug
, int, 0);
92 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly
= 128;
95 module_param(copybreak
, int, 0);
96 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
98 static int disable_msi
= 0;
99 module_param(disable_msi
, int, 0);
100 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
102 static const struct pci_device_id sky2_id_table
[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
136 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
138 /* Avoid conditionals by using array */
139 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
140 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
141 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
143 /* This driver supports yukon2 chipset only */
144 static const char *yukon2_name
[] = {
146 "EC Ultra", /* 0xb4 */
147 "Extreme", /* 0xb5 */
152 static void sky2_set_multicast(struct net_device
*dev
);
154 /* Access to external PHY */
155 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
159 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
160 gma_write16(hw
, port
, GM_SMI_CTRL
,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
163 for (i
= 0; i
< PHY_RETRIES
; i
++) {
164 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
169 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
173 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
177 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
178 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
180 for (i
= 0; i
< PHY_RETRIES
; i
++) {
181 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
182 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
192 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
196 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
197 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
202 static void sky2_power_on(struct sky2_hw
*hw
)
204 /* switch power to VCC (WA for VAUX problem) */
205 sky2_write8(hw
, B0_POWER_CTRL
,
206 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
208 /* disable Core Clock Division, */
209 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
211 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
212 /* enable bits are inverted */
213 sky2_write8(hw
, B2_Y2_CLK_GATE
,
214 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
215 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
216 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
218 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
220 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
221 hw
->chip_id
== CHIP_ID_YUKON_EX
) {
224 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
226 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
227 /* set all bits to 0 except bits 15..12 and 8 */
228 reg
&= P_ASPM_CONTROL_MSK
;
229 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
231 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
232 /* set all bits to 0 except bits 28 & 27 */
233 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
234 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
236 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
238 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
239 reg
= sky2_read32(hw
, B2_GP_IO
);
240 reg
|= GLB_GPIO_STAT_RACE_DIS
;
241 sky2_write32(hw
, B2_GP_IO
, reg
);
243 sky2_read32(hw
, B2_GP_IO
);
247 static void sky2_power_aux(struct sky2_hw
*hw
)
249 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
250 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
252 /* enable bits are inverted */
253 sky2_write8(hw
, B2_Y2_CLK_GATE
,
254 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
255 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
256 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
258 /* switch power to VAUX */
259 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
260 sky2_write8(hw
, B0_POWER_CTRL
,
261 (PC_VAUX_ENA
| PC_VCC_ENA
|
262 PC_VAUX_ON
| PC_VCC_OFF
));
265 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
269 /* disable all GMAC IRQ's */
270 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
271 /* disable PHY IRQs */
272 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
274 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
275 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
276 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
277 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
279 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
280 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
281 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
284 /* flow control to advertise bits */
285 static const u16 copper_fc_adv
[] = {
287 [FC_TX
] = PHY_M_AN_ASP
,
288 [FC_RX
] = PHY_M_AN_PC
,
289 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
292 /* flow control to advertise bits when using 1000BaseX */
293 static const u16 fiber_fc_adv
[] = {
294 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
295 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
296 [FC_RX
] = PHY_M_P_SYM_MD_X
,
297 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
300 /* flow control to GMA disable bits */
301 static const u16 gm_fc_disable
[] = {
302 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
303 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
304 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
309 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
311 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
312 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
314 if (sky2
->autoneg
== AUTONEG_ENABLE
315 && !(hw
->chip_id
== CHIP_ID_YUKON_XL
316 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
317 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
318 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
320 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
322 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
324 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
325 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
326 /* set downshift counter to 3x and enable downshift */
327 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
329 /* set master & slave downshift counter to 1x */
330 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
332 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
335 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
336 if (sky2_is_copper(hw
)) {
337 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
338 /* enable automatic crossover */
339 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
341 /* disable energy detect */
342 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
344 /* enable automatic crossover */
345 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
347 /* downshift on PHY 88E1112 and 88E1149 is changed */
348 if (sky2
->autoneg
== AUTONEG_ENABLE
349 && (hw
->chip_id
== CHIP_ID_YUKON_XL
350 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
351 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
352 /* set downshift counter to 3x and enable downshift */
353 ctrl
&= ~PHY_M_PC_DSC_MSK
;
354 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
358 /* workaround for deviation #4.88 (CRC errors) */
359 /* disable Automatic Crossover */
361 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
364 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
366 /* special setup for PHY 88E1112 Fiber */
367 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
368 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
370 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
371 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
372 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
373 ctrl
&= ~PHY_M_MAC_MD_MSK
;
374 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
375 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
377 if (hw
->pmd_type
== 'P') {
378 /* select page 1 to access Fiber registers */
379 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
381 /* for SFP-module set SIGDET polarity to low */
382 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
383 ctrl
|= PHY_M_FIB_SIGD_POL
;
384 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
387 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
395 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
396 if (sky2_is_copper(hw
)) {
397 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
398 ct1000
|= PHY_M_1000C_AFD
;
399 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
400 ct1000
|= PHY_M_1000C_AHD
;
401 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
402 adv
|= PHY_M_AN_100_FD
;
403 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
404 adv
|= PHY_M_AN_100_HD
;
405 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
406 adv
|= PHY_M_AN_10_FD
;
407 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
408 adv
|= PHY_M_AN_10_HD
;
410 adv
|= copper_fc_adv
[sky2
->flow_mode
];
411 } else { /* special defines for FIBER (88E1040S only) */
412 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
413 adv
|= PHY_M_AN_1000X_AFD
;
414 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
415 adv
|= PHY_M_AN_1000X_AHD
;
417 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
420 /* Restart Auto-negotiation */
421 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
423 /* forced speed/duplex settings */
424 ct1000
= PHY_M_1000C_MSE
;
426 /* Disable auto update for duplex flow control and speed */
427 reg
|= GM_GPCR_AU_ALL_DIS
;
429 switch (sky2
->speed
) {
431 ctrl
|= PHY_CT_SP1000
;
432 reg
|= GM_GPCR_SPEED_1000
;
435 ctrl
|= PHY_CT_SP100
;
436 reg
|= GM_GPCR_SPEED_100
;
440 if (sky2
->duplex
== DUPLEX_FULL
) {
441 reg
|= GM_GPCR_DUP_FULL
;
442 ctrl
|= PHY_CT_DUP_MD
;
443 } else if (sky2
->speed
< SPEED_1000
)
444 sky2
->flow_mode
= FC_NONE
;
447 reg
|= gm_fc_disable
[sky2
->flow_mode
];
449 /* Forward pause packets to GMAC? */
450 if (sky2
->flow_mode
& FC_RX
)
451 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
453 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
456 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
458 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
459 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
461 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
462 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
464 /* Setup Phy LED's */
465 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
468 switch (hw
->chip_id
) {
469 case CHIP_ID_YUKON_FE
:
470 /* on 88E3082 these bits are at 11..9 (shifted left) */
471 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
473 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
475 /* delete ACT LED control bits */
476 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
477 /* change ACT LED control to blink mode */
478 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
479 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
482 case CHIP_ID_YUKON_XL
:
483 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
485 /* select page 3 to access LED control register */
486 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
488 /* set LED Function Control register */
489 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
490 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
491 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
492 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
493 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
495 /* set Polarity Control register */
496 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
497 (PHY_M_POLC_LS1_P_MIX(4) |
498 PHY_M_POLC_IS0_P_MIX(4) |
499 PHY_M_POLC_LOS_CTRL(2) |
500 PHY_M_POLC_INIT_CTRL(2) |
501 PHY_M_POLC_STA1_CTRL(2) |
502 PHY_M_POLC_STA0_CTRL(2)));
504 /* restore page register */
505 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
508 case CHIP_ID_YUKON_EC_U
:
509 case CHIP_ID_YUKON_EX
:
510 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
512 /* select page 3 to access LED control register */
513 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
515 /* set LED Function Control register */
516 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
517 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
518 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
519 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
520 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
522 /* set Blink Rate in LED Timer Control Register */
523 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
524 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
525 /* restore page register */
526 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
530 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
531 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
532 /* turn off the Rx LED (LED_RX) */
533 ledover
&= ~PHY_M_LED_MO_RX
;
536 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
537 hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
) {
538 /* apply fixes in PHY AFE */
539 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
541 /* increase differential signal amplitude in 10BASE-T */
542 gm_phy_write(hw
, port
, 0x18, 0xaa99);
543 gm_phy_write(hw
, port
, 0x17, 0x2011);
545 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
546 gm_phy_write(hw
, port
, 0x18, 0xa204);
547 gm_phy_write(hw
, port
, 0x17, 0x2002);
549 /* set page register to 0 */
550 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
551 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
552 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
554 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
555 /* turn on 100 Mbps LED (LED_LINK100) */
556 ledover
|= PHY_M_LED_MO_100
;
560 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
564 /* Enable phy interrupt on auto-negotiation complete (or link up) */
565 if (sky2
->autoneg
== AUTONEG_ENABLE
)
566 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
568 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
571 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
574 static const u32 phy_power
[]
575 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
577 /* looks like this XL is back asswards .. */
578 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
581 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
582 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
584 /* Turn off phy power saving */
585 reg1
&= ~phy_power
[port
];
587 reg1
|= phy_power
[port
];
589 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
590 sky2_pci_read32(hw
, PCI_DEV_REG1
);
591 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
595 /* Force a renegotiation */
596 static void sky2_phy_reinit(struct sky2_port
*sky2
)
598 spin_lock_bh(&sky2
->phy_lock
);
599 sky2_phy_init(sky2
->hw
, sky2
->port
);
600 spin_unlock_bh(&sky2
->phy_lock
);
603 /* Put device in state to listen for Wake On Lan */
604 static void sky2_wol_init(struct sky2_port
*sky2
)
606 struct sky2_hw
*hw
= sky2
->hw
;
607 unsigned port
= sky2
->port
;
608 enum flow_control save_mode
;
612 /* Bring hardware out of reset */
613 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
614 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
616 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
617 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
620 * sky2_reset will re-enable on resume
622 save_mode
= sky2
->flow_mode
;
623 ctrl
= sky2
->advertising
;
625 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
626 sky2
->flow_mode
= FC_NONE
;
627 sky2_phy_power(hw
, port
, 1);
628 sky2_phy_reinit(sky2
);
630 sky2
->flow_mode
= save_mode
;
631 sky2
->advertising
= ctrl
;
633 /* Set GMAC to no flow control and auto update for speed/duplex */
634 gma_write16(hw
, port
, GM_GP_CTRL
,
635 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
636 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
638 /* Set WOL address */
639 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
640 sky2
->netdev
->dev_addr
, ETH_ALEN
);
642 /* Turn on appropriate WOL control bits */
643 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
645 if (sky2
->wol
& WAKE_PHY
)
646 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
648 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
650 if (sky2
->wol
& WAKE_MAGIC
)
651 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
653 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
655 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
656 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
658 /* Turn on legacy PCI-Express PME mode */
659 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
660 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
661 reg1
|= PCI_Y2_PME_LEGACY
;
662 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
663 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
666 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
670 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
672 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) {
673 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
675 (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) ? TX_JUMBO_ENA
: TX_JUMBO_DIS
);
677 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
678 /* set Tx GMAC FIFO Almost Empty Threshold */
679 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
680 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
682 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
683 TX_JUMBO_ENA
| TX_STFW_DIS
);
685 /* Can't do offload because of lack of store/forward */
686 hw
->dev
[port
]->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
689 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
690 TX_JUMBO_DIS
| TX_STFW_ENA
);
694 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
696 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
700 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
702 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
703 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
705 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
707 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
708 /* WA DEV_472 -- looks like crossed wires on port 2 */
709 /* clear GMAC 1 Control reset */
710 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
712 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
713 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
714 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
715 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
716 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
719 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
721 /* Enable Transmit FIFO Underrun */
722 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
724 spin_lock_bh(&sky2
->phy_lock
);
725 sky2_phy_init(hw
, port
);
726 spin_unlock_bh(&sky2
->phy_lock
);
729 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
730 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
732 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
733 gma_read16(hw
, port
, i
);
734 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
736 /* transmit control */
737 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
739 /* receive control reg: unicast + multicast + no FCS */
740 gma_write16(hw
, port
, GM_RX_CTRL
,
741 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
743 /* transmit flow control */
744 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
746 /* transmit parameter */
747 gma_write16(hw
, port
, GM_TX_PARAM
,
748 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
749 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
750 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
751 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
753 /* serial mode register */
754 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
755 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
757 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
758 reg
|= GM_SMOD_JUMBO_ENA
;
760 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
762 /* virtual address for data */
763 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
765 /* physical address: used for pause frames */
766 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
768 /* ignore counter overflows */
769 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
770 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
771 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
773 /* Configure Rx MAC FIFO */
774 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
775 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
776 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
777 rx_reg
|= GMF_RX_OVER_ON
;
779 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
781 /* Flush Rx MAC FIFO on any flow control or error */
782 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
784 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
785 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
787 /* Configure Tx MAC FIFO */
788 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
789 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
791 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
792 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
793 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
795 sky2_set_tx_stfwd(hw
, port
);
800 /* Assign Ram Buffer allocation to queue */
801 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
805 /* convert from K bytes to qwords used for hw register */
808 end
= start
+ space
- 1;
810 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
811 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
812 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
813 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
814 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
816 if (q
== Q_R1
|| q
== Q_R2
) {
817 u32 tp
= space
- space
/4;
819 /* On receive queue's set the thresholds
820 * give receiver priority when > 3/4 full
821 * send pause when down to 2K
823 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
824 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
827 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
828 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
830 /* Enable store & forward on Tx queue's because
831 * Tx FIFO is only 1K on Yukon
833 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
836 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
837 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
840 /* Setup Bus Memory Interface */
841 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
843 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
844 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
845 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
846 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
849 /* Setup prefetch unit registers. This is the interface between
850 * hardware and driver list elements
852 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
855 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
856 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
857 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
858 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
859 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
860 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
862 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
865 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
867 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
869 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
874 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
875 struct sky2_tx_le
*le
)
877 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
880 /* Update chip's next pointer */
881 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
883 /* Make sure write' to descriptors are complete before we tell hardware */
885 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
887 /* Synchronize I/O on since next processor may write to tail */
892 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
894 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
895 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
900 /* Build description to hardware for one receive segment */
901 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
902 dma_addr_t map
, unsigned len
)
904 struct sky2_rx_le
*le
;
905 u32 hi
= upper_32_bits(map
);
907 if (sky2
->rx_addr64
!= hi
) {
908 le
= sky2_next_rx(sky2
);
909 le
->addr
= cpu_to_le32(hi
);
910 le
->opcode
= OP_ADDR64
| HW_OWNER
;
911 sky2
->rx_addr64
= upper_32_bits(map
+ len
);
914 le
= sky2_next_rx(sky2
);
915 le
->addr
= cpu_to_le32((u32
) map
);
916 le
->length
= cpu_to_le16(len
);
917 le
->opcode
= op
| HW_OWNER
;
920 /* Build description to hardware for one possibly fragmented skb */
921 static void sky2_rx_submit(struct sky2_port
*sky2
,
922 const struct rx_ring_info
*re
)
926 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
928 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
929 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
933 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
936 struct sk_buff
*skb
= re
->skb
;
939 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
940 pci_unmap_len_set(re
, data_size
, size
);
942 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
943 re
->frag_addr
[i
] = pci_map_page(pdev
,
944 skb_shinfo(skb
)->frags
[i
].page
,
945 skb_shinfo(skb
)->frags
[i
].page_offset
,
946 skb_shinfo(skb
)->frags
[i
].size
,
950 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
952 struct sk_buff
*skb
= re
->skb
;
955 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
958 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
959 pci_unmap_page(pdev
, re
->frag_addr
[i
],
960 skb_shinfo(skb
)->frags
[i
].size
,
964 /* Tell chip where to start receive checksum.
965 * Actually has two checksums, but set both same to avoid possible byte
968 static void rx_set_checksum(struct sky2_port
*sky2
)
970 struct sky2_rx_le
*le
;
972 if (sky2
->hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
973 le
= sky2_next_rx(sky2
);
974 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
976 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
978 sky2_write32(sky2
->hw
,
979 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
980 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
986 * The RX Stop command will not work for Yukon-2 if the BMU does not
987 * reach the end of packet and since we can't make sure that we have
988 * incoming data, we must reset the BMU while it is not doing a DMA
989 * transfer. Since it is possible that the RX path is still active,
990 * the RX RAM buffer will be stopped first, so any possible incoming
991 * data will not trigger a DMA. After the RAM buffer is stopped, the
992 * BMU is polled until any DMA in progress is ended and only then it
995 static void sky2_rx_stop(struct sky2_port
*sky2
)
997 struct sky2_hw
*hw
= sky2
->hw
;
998 unsigned rxq
= rxqaddr
[sky2
->port
];
1001 /* disable the RAM Buffer receive queue */
1002 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1004 for (i
= 0; i
< 0xffff; i
++)
1005 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1006 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1009 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1010 sky2
->netdev
->name
);
1012 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1014 /* reset the Rx prefetch unit */
1015 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1019 /* Clean out receive buffer area, assumes receiver hardware stopped */
1020 static void sky2_rx_clean(struct sky2_port
*sky2
)
1024 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1025 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1026 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1029 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1036 /* Basic MII support */
1037 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1039 struct mii_ioctl_data
*data
= if_mii(ifr
);
1040 struct sky2_port
*sky2
= netdev_priv(dev
);
1041 struct sky2_hw
*hw
= sky2
->hw
;
1042 int err
= -EOPNOTSUPP
;
1044 if (!netif_running(dev
))
1045 return -ENODEV
; /* Phy still in reset */
1049 data
->phy_id
= PHY_ADDR_MARV
;
1055 spin_lock_bh(&sky2
->phy_lock
);
1056 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1057 spin_unlock_bh(&sky2
->phy_lock
);
1059 data
->val_out
= val
;
1064 if (!capable(CAP_NET_ADMIN
))
1067 spin_lock_bh(&sky2
->phy_lock
);
1068 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1070 spin_unlock_bh(&sky2
->phy_lock
);
1076 #ifdef SKY2_VLAN_TAG_USED
1077 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1079 struct sky2_port
*sky2
= netdev_priv(dev
);
1080 struct sky2_hw
*hw
= sky2
->hw
;
1081 u16 port
= sky2
->port
;
1083 netif_tx_lock_bh(dev
);
1084 netif_poll_disable(sky2
->hw
->dev
[0]);
1088 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1090 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1093 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1095 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1099 netif_poll_enable(sky2
->hw
->dev
[0]);
1100 netif_tx_unlock_bh(dev
);
1105 * Allocate an skb for receiving. If the MTU is large enough
1106 * make the skb non-linear with a fragment list of pages.
1108 * It appears the hardware has a bug in the FIFO logic that
1109 * cause it to hang if the FIFO gets overrun and the receive buffer
1110 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1111 * aligned except if slab debugging is enabled.
1113 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1115 struct sk_buff
*skb
;
1119 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1123 p
= (unsigned long) skb
->data
;
1124 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1126 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1127 struct page
*page
= alloc_page(GFP_ATOMIC
);
1131 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1141 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1143 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1147 * Allocate and setup receiver buffer pool.
1148 * Normal case this ends up creating one list element for skb
1149 * in the receive ring. Worst case if using large MTU and each
1150 * allocation falls on a different 64 bit region, that results
1151 * in 6 list elements per ring entry.
1152 * One element is used for checksum enable/disable, and one
1153 * extra to avoid wrap.
1155 static int sky2_rx_start(struct sky2_port
*sky2
)
1157 struct sky2_hw
*hw
= sky2
->hw
;
1158 struct rx_ring_info
*re
;
1159 unsigned rxq
= rxqaddr
[sky2
->port
];
1160 unsigned i
, size
, space
, thresh
;
1162 sky2
->rx_put
= sky2
->rx_next
= 0;
1165 /* On PCI express lowering the watermark gives better performance */
1166 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1167 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1169 /* These chips have no ram buffer?
1170 * MAC Rx RAM Read is controlled by hardware */
1171 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1172 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1173 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1174 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1176 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1178 rx_set_checksum(sky2
);
1180 /* Space needed for frame data + headers rounded up */
1181 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1183 /* Stopping point for hardware truncation */
1184 thresh
= (size
- 8) / sizeof(u32
);
1186 /* Account for overhead of skb - to avoid order > 0 allocation */
1187 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1188 + sizeof(struct skb_shared_info
);
1190 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1191 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1193 if (sky2
->rx_nfrags
!= 0) {
1194 /* Compute residue after pages */
1195 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1202 /* Optimize to handle small packets and headers */
1203 if (size
< copybreak
)
1205 if (size
< ETH_HLEN
)
1208 sky2
->rx_data_size
= size
;
1211 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1212 re
= sky2
->rx_ring
+ i
;
1214 re
->skb
= sky2_rx_alloc(sky2
);
1218 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1219 sky2_rx_submit(sky2
, re
);
1223 * The receiver hangs if it receives frames larger than the
1224 * packet buffer. As a workaround, truncate oversize frames, but
1225 * the register is limited to 9 bits, so if you do frames > 2052
1226 * you better get the MTU right!
1229 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1231 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1232 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1235 /* Tell chip about available buffers */
1236 sky2_rx_update(sky2
, rxq
);
1239 sky2_rx_clean(sky2
);
1243 /* Bring up network interface. */
1244 static int sky2_up(struct net_device
*dev
)
1246 struct sky2_port
*sky2
= netdev_priv(dev
);
1247 struct sky2_hw
*hw
= sky2
->hw
;
1248 unsigned port
= sky2
->port
;
1250 int cap
, err
= -ENOMEM
;
1251 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1254 * On dual port PCI-X card, there is an problem where status
1255 * can be received out of order due to split transactions
1257 if (otherdev
&& netif_running(otherdev
) &&
1258 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1259 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1262 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1263 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1264 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1270 if (netif_msg_ifup(sky2
))
1271 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1273 netif_carrier_off(dev
);
1275 /* must be power of 2 */
1276 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1278 sizeof(struct sky2_tx_le
),
1283 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1287 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1289 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1293 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1295 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1300 sky2_phy_power(hw
, port
, 1);
1302 sky2_mac_init(hw
, port
);
1304 /* Register is number of 4K blocks on internal RAM buffer. */
1305 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1306 printk(KERN_INFO PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1312 rxspace
= ramsize
/ 2;
1314 rxspace
= 8 + (2*(ramsize
- 16))/3;
1316 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1317 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1319 /* Make sure SyncQ is disabled */
1320 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1324 sky2_qset(hw
, txqaddr
[port
]);
1326 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1327 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1328 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1330 /* Set almost empty threshold */
1331 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1332 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1333 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1335 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1338 err
= sky2_rx_start(sky2
);
1342 /* Enable interrupts from phy/mac for port */
1343 imask
= sky2_read32(hw
, B0_IMSK
);
1344 imask
|= portirq_msk
[port
];
1345 sky2_write32(hw
, B0_IMSK
, imask
);
1351 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1352 sky2
->rx_le
, sky2
->rx_le_map
);
1356 pci_free_consistent(hw
->pdev
,
1357 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1358 sky2
->tx_le
, sky2
->tx_le_map
);
1361 kfree(sky2
->tx_ring
);
1362 kfree(sky2
->rx_ring
);
1364 sky2
->tx_ring
= NULL
;
1365 sky2
->rx_ring
= NULL
;
1369 /* Modular subtraction in ring */
1370 static inline int tx_dist(unsigned tail
, unsigned head
)
1372 return (head
- tail
) & (TX_RING_SIZE
- 1);
1375 /* Number of list elements available for next tx */
1376 static inline int tx_avail(const struct sky2_port
*sky2
)
1378 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1381 /* Estimate of number of transmit list elements required */
1382 static unsigned tx_le_req(const struct sk_buff
*skb
)
1386 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1387 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1389 if (skb_is_gso(skb
))
1392 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1399 * Put one packet in ring for transmit.
1400 * A single packet can generate multiple list elements, and
1401 * the number of ring elements will probably be less than the number
1402 * of list elements used.
1404 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1406 struct sky2_port
*sky2
= netdev_priv(dev
);
1407 struct sky2_hw
*hw
= sky2
->hw
;
1408 struct sky2_tx_le
*le
= NULL
;
1409 struct tx_ring_info
*re
;
1416 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1417 return NETDEV_TX_BUSY
;
1419 if (unlikely(netif_msg_tx_queued(sky2
)))
1420 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1421 dev
->name
, sky2
->tx_prod
, skb
->len
);
1423 len
= skb_headlen(skb
);
1424 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1425 addr64
= upper_32_bits(mapping
);
1427 /* Send high bits if changed or crosses boundary */
1428 if (addr64
!= sky2
->tx_addr64
||
1429 upper_32_bits(mapping
+ len
) != sky2
->tx_addr64
) {
1430 le
= get_tx_le(sky2
);
1431 le
->addr
= cpu_to_le32(addr64
);
1432 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1433 sky2
->tx_addr64
= upper_32_bits(mapping
+ len
);
1436 /* Check for TCP Segmentation Offload */
1437 mss
= skb_shinfo(skb
)->gso_size
;
1439 if (hw
->chip_id
!= CHIP_ID_YUKON_EX
)
1440 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1442 if (mss
!= sky2
->tx_last_mss
) {
1443 le
= get_tx_le(sky2
);
1444 le
->addr
= cpu_to_le32(mss
);
1445 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
1446 le
->opcode
= OP_MSS
| HW_OWNER
;
1448 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1449 sky2
->tx_last_mss
= mss
;
1454 #ifdef SKY2_VLAN_TAG_USED
1455 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1456 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1458 le
= get_tx_le(sky2
);
1460 le
->opcode
= OP_VLAN
|HW_OWNER
;
1462 le
->opcode
|= OP_VLAN
;
1463 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1468 /* Handle TCP checksum offload */
1469 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1470 /* On Yukon EX (some versions) encoding change. */
1471 if (hw
->chip_id
== CHIP_ID_YUKON_EX
1472 && hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
1473 ctrl
|= CALSUM
; /* auto checksum */
1475 const unsigned offset
= skb_transport_offset(skb
);
1478 tcpsum
= offset
<< 16; /* sum start */
1479 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1481 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1482 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1485 if (tcpsum
!= sky2
->tx_tcpsum
) {
1486 sky2
->tx_tcpsum
= tcpsum
;
1488 le
= get_tx_le(sky2
);
1489 le
->addr
= cpu_to_le32(tcpsum
);
1490 le
->length
= 0; /* initial checksum value */
1491 le
->ctrl
= 1; /* one packet */
1492 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1497 le
= get_tx_le(sky2
);
1498 le
->addr
= cpu_to_le32((u32
) mapping
);
1499 le
->length
= cpu_to_le16(len
);
1501 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1503 re
= tx_le_re(sky2
, le
);
1505 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1506 pci_unmap_len_set(re
, maplen
, len
);
1508 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1509 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1511 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1512 frag
->size
, PCI_DMA_TODEVICE
);
1513 addr64
= upper_32_bits(mapping
);
1514 if (addr64
!= sky2
->tx_addr64
) {
1515 le
= get_tx_le(sky2
);
1516 le
->addr
= cpu_to_le32(addr64
);
1518 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1519 sky2
->tx_addr64
= addr64
;
1522 le
= get_tx_le(sky2
);
1523 le
->addr
= cpu_to_le32((u32
) mapping
);
1524 le
->length
= cpu_to_le16(frag
->size
);
1526 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1528 re
= tx_le_re(sky2
, le
);
1530 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1531 pci_unmap_len_set(re
, maplen
, frag
->size
);
1536 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1537 netif_stop_queue(dev
);
1539 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1541 dev
->trans_start
= jiffies
;
1542 return NETDEV_TX_OK
;
1546 * Free ring elements from starting at tx_cons until "done"
1548 * NB: the hardware will tell us about partial completion of multi-part
1549 * buffers so make sure not to free skb to early.
1551 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1553 struct net_device
*dev
= sky2
->netdev
;
1554 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1557 BUG_ON(done
>= TX_RING_SIZE
);
1559 for (idx
= sky2
->tx_cons
; idx
!= done
;
1560 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1561 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1562 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1564 switch(le
->opcode
& ~HW_OWNER
) {
1567 pci_unmap_single(pdev
,
1568 pci_unmap_addr(re
, mapaddr
),
1569 pci_unmap_len(re
, maplen
),
1573 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1574 pci_unmap_len(re
, maplen
),
1579 if (le
->ctrl
& EOP
) {
1580 if (unlikely(netif_msg_tx_done(sky2
)))
1581 printk(KERN_DEBUG
"%s: tx done %u\n",
1584 sky2
->net_stats
.tx_packets
++;
1585 sky2
->net_stats
.tx_bytes
+= re
->skb
->len
;
1587 dev_kfree_skb_any(re
->skb
);
1588 sky2
->tx_next
= RING_NEXT(idx
, TX_RING_SIZE
);
1592 sky2
->tx_cons
= idx
;
1595 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1596 netif_wake_queue(dev
);
1599 /* Cleanup all untransmitted buffers, assume transmitter not running */
1600 static void sky2_tx_clean(struct net_device
*dev
)
1602 struct sky2_port
*sky2
= netdev_priv(dev
);
1604 netif_tx_lock_bh(dev
);
1605 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1606 netif_tx_unlock_bh(dev
);
1609 /* Network shutdown */
1610 static int sky2_down(struct net_device
*dev
)
1612 struct sky2_port
*sky2
= netdev_priv(dev
);
1613 struct sky2_hw
*hw
= sky2
->hw
;
1614 unsigned port
= sky2
->port
;
1618 /* Never really got started! */
1622 if (netif_msg_ifdown(sky2
))
1623 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1625 if (netif_carrier_ok(dev
) && --hw
->active
== 0)
1626 del_timer(&hw
->watchdog_timer
);
1628 /* Stop more packets from being queued */
1629 netif_stop_queue(dev
);
1631 /* Disable port IRQ */
1632 imask
= sky2_read32(hw
, B0_IMSK
);
1633 imask
&= ~portirq_msk
[port
];
1634 sky2_write32(hw
, B0_IMSK
, imask
);
1636 sky2_gmac_reset(hw
, port
);
1638 /* Stop transmitter */
1639 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1640 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1642 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1643 RB_RST_SET
| RB_DIS_OP_MD
);
1645 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1646 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1647 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1649 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1651 /* Workaround shared GMAC reset */
1652 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1653 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1654 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1656 /* Disable Force Sync bit and Enable Alloc bit */
1657 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1658 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1660 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1661 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1662 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1664 /* Reset the PCI FIFO of the async Tx queue */
1665 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1666 BMU_RST_SET
| BMU_FIFO_RST
);
1668 /* Reset the Tx prefetch units */
1669 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1672 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1676 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1677 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1679 sky2_phy_power(hw
, port
, 0);
1681 netif_carrier_off(dev
);
1683 /* turn off LED's */
1684 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1686 synchronize_irq(hw
->pdev
->irq
);
1689 sky2_rx_clean(sky2
);
1691 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1692 sky2
->rx_le
, sky2
->rx_le_map
);
1693 kfree(sky2
->rx_ring
);
1695 pci_free_consistent(hw
->pdev
,
1696 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1697 sky2
->tx_le
, sky2
->tx_le_map
);
1698 kfree(sky2
->tx_ring
);
1703 sky2
->rx_ring
= NULL
;
1704 sky2
->tx_ring
= NULL
;
1709 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1711 if (!sky2_is_copper(hw
))
1714 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1715 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1717 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1718 case PHY_M_PS_SPEED_1000
:
1720 case PHY_M_PS_SPEED_100
:
1727 static void sky2_link_up(struct sky2_port
*sky2
)
1729 struct sky2_hw
*hw
= sky2
->hw
;
1730 unsigned port
= sky2
->port
;
1732 static const char *fc_name
[] = {
1740 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1741 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1742 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1744 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1746 netif_carrier_on(sky2
->netdev
);
1748 if (hw
->active
++ == 0)
1749 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
1752 /* Turn on link LED */
1753 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1754 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1756 if (hw
->chip_id
== CHIP_ID_YUKON_XL
1757 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
1758 || hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1759 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1760 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1762 switch(sky2
->speed
) {
1764 led
|= PHY_M_LEDC_INIT_CTRL(7);
1768 led
|= PHY_M_LEDC_STA1_CTRL(7);
1772 led
|= PHY_M_LEDC_STA0_CTRL(7);
1776 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1777 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1778 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1781 if (netif_msg_link(sky2
))
1782 printk(KERN_INFO PFX
1783 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1784 sky2
->netdev
->name
, sky2
->speed
,
1785 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1786 fc_name
[sky2
->flow_status
]);
1789 static void sky2_link_down(struct sky2_port
*sky2
)
1791 struct sky2_hw
*hw
= sky2
->hw
;
1792 unsigned port
= sky2
->port
;
1795 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1797 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1798 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1799 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1801 netif_carrier_off(sky2
->netdev
);
1803 /* Stop watchdog if both ports are not active */
1804 if (--hw
->active
== 0)
1805 del_timer(&hw
->watchdog_timer
);
1808 /* Turn on link LED */
1809 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1811 if (netif_msg_link(sky2
))
1812 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1814 sky2_phy_init(hw
, port
);
1817 static enum flow_control
sky2_flow(int rx
, int tx
)
1820 return tx
? FC_BOTH
: FC_RX
;
1822 return tx
? FC_TX
: FC_NONE
;
1825 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1827 struct sky2_hw
*hw
= sky2
->hw
;
1828 unsigned port
= sky2
->port
;
1831 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1832 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1833 if (lpa
& PHY_M_AN_RF
) {
1834 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1838 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1839 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1840 sky2
->netdev
->name
);
1844 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1845 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1847 /* Since the pause result bits seem to in different positions on
1848 * different chips. look at registers.
1850 if (!sky2_is_copper(hw
)) {
1851 /* Shift for bits in fiber PHY */
1852 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1853 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1855 if (advert
& ADVERTISE_1000XPAUSE
)
1856 advert
|= ADVERTISE_PAUSE_CAP
;
1857 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1858 advert
|= ADVERTISE_PAUSE_ASYM
;
1859 if (lpa
& LPA_1000XPAUSE
)
1860 lpa
|= LPA_PAUSE_CAP
;
1861 if (lpa
& LPA_1000XPAUSE_ASYM
)
1862 lpa
|= LPA_PAUSE_ASYM
;
1865 sky2
->flow_status
= FC_NONE
;
1866 if (advert
& ADVERTISE_PAUSE_CAP
) {
1867 if (lpa
& LPA_PAUSE_CAP
)
1868 sky2
->flow_status
= FC_BOTH
;
1869 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1870 sky2
->flow_status
= FC_RX
;
1871 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1872 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1873 sky2
->flow_status
= FC_TX
;
1876 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1877 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1878 sky2
->flow_status
= FC_NONE
;
1880 if (sky2
->flow_status
& FC_TX
)
1881 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1883 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1888 /* Interrupt from PHY */
1889 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1891 struct net_device
*dev
= hw
->dev
[port
];
1892 struct sky2_port
*sky2
= netdev_priv(dev
);
1893 u16 istatus
, phystat
;
1895 if (!netif_running(dev
))
1898 spin_lock(&sky2
->phy_lock
);
1899 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1900 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1902 if (netif_msg_intr(sky2
))
1903 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1904 sky2
->netdev
->name
, istatus
, phystat
);
1906 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1907 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1912 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1913 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1915 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1917 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1919 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1920 if (phystat
& PHY_M_PS_LINK_UP
)
1923 sky2_link_down(sky2
);
1926 spin_unlock(&sky2
->phy_lock
);
1929 /* Transmit timeout is only called if we are running, carrier is up
1930 * and tx queue is full (stopped).
1932 static void sky2_tx_timeout(struct net_device
*dev
)
1934 struct sky2_port
*sky2
= netdev_priv(dev
);
1935 struct sky2_hw
*hw
= sky2
->hw
;
1937 if (netif_msg_timer(sky2
))
1938 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1940 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1941 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
1942 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
1943 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
1945 /* can't restart safely under softirq */
1946 schedule_work(&hw
->restart_work
);
1949 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1951 struct sky2_port
*sky2
= netdev_priv(dev
);
1952 struct sky2_hw
*hw
= sky2
->hw
;
1953 unsigned port
= sky2
->port
;
1958 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1961 if (new_mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_FE
)
1964 if (!netif_running(dev
)) {
1969 imask
= sky2_read32(hw
, B0_IMSK
);
1970 sky2_write32(hw
, B0_IMSK
, 0);
1972 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1973 netif_stop_queue(dev
);
1974 netif_poll_disable(hw
->dev
[0]);
1976 synchronize_irq(hw
->pdev
->irq
);
1978 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
)
1979 sky2_set_tx_stfwd(hw
, port
);
1981 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1982 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1984 sky2_rx_clean(sky2
);
1988 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1989 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1991 if (dev
->mtu
> ETH_DATA_LEN
)
1992 mode
|= GM_SMOD_JUMBO_ENA
;
1994 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
1996 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
1998 err
= sky2_rx_start(sky2
);
1999 sky2_write32(hw
, B0_IMSK
, imask
);
2004 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2006 netif_poll_enable(hw
->dev
[0]);
2007 netif_wake_queue(dev
);
2013 /* For small just reuse existing skb for next receive */
2014 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2015 const struct rx_ring_info
*re
,
2018 struct sk_buff
*skb
;
2020 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
2022 skb_reserve(skb
, 2);
2023 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2024 length
, PCI_DMA_FROMDEVICE
);
2025 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2026 skb
->ip_summed
= re
->skb
->ip_summed
;
2027 skb
->csum
= re
->skb
->csum
;
2028 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2029 length
, PCI_DMA_FROMDEVICE
);
2030 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2031 skb_put(skb
, length
);
2036 /* Adjust length of skb with fragments to match received data */
2037 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2038 unsigned int length
)
2043 /* put header into skb */
2044 size
= min(length
, hdr_space
);
2049 num_frags
= skb_shinfo(skb
)->nr_frags
;
2050 for (i
= 0; i
< num_frags
; i
++) {
2051 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2054 /* don't need this page */
2055 __free_page(frag
->page
);
2056 --skb_shinfo(skb
)->nr_frags
;
2058 size
= min(length
, (unsigned) PAGE_SIZE
);
2061 skb
->data_len
+= size
;
2062 skb
->truesize
+= size
;
2069 /* Normal packet - take skb from ring element and put in a new one */
2070 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2071 struct rx_ring_info
*re
,
2072 unsigned int length
)
2074 struct sk_buff
*skb
, *nskb
;
2075 unsigned hdr_space
= sky2
->rx_data_size
;
2077 /* Don't be tricky about reusing pages (yet) */
2078 nskb
= sky2_rx_alloc(sky2
);
2079 if (unlikely(!nskb
))
2083 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2085 prefetch(skb
->data
);
2087 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2089 if (skb_shinfo(skb
)->nr_frags
)
2090 skb_put_frags(skb
, hdr_space
, length
);
2092 skb_put(skb
, length
);
2097 * Receive one packet.
2098 * For larger packets, get new buffer.
2100 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2101 u16 length
, u32 status
)
2103 struct sky2_port
*sky2
= netdev_priv(dev
);
2104 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2105 struct sk_buff
*skb
= NULL
;
2107 if (unlikely(netif_msg_rx_status(sky2
)))
2108 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2109 dev
->name
, sky2
->rx_next
, status
, length
);
2111 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2112 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2114 if (status
& GMR_FS_ANY_ERR
)
2117 if (!(status
& GMR_FS_RX_OK
))
2120 if (status
>> 16 != length
)
2123 if (length
< copybreak
)
2124 skb
= receive_copy(sky2
, re
, length
);
2126 skb
= receive_new(sky2
, re
, length
);
2128 sky2_rx_submit(sky2
, re
);
2133 /* Truncation of overlength packets
2134 causes PHY length to not match MAC length */
2135 ++sky2
->net_stats
.rx_length_errors
;
2138 ++sky2
->net_stats
.rx_errors
;
2139 if (status
& GMR_FS_RX_FF_OV
) {
2140 sky2
->net_stats
.rx_over_errors
++;
2144 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2145 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2146 dev
->name
, status
, length
);
2148 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2149 sky2
->net_stats
.rx_length_errors
++;
2150 if (status
& GMR_FS_FRAGMENT
)
2151 sky2
->net_stats
.rx_frame_errors
++;
2152 if (status
& GMR_FS_CRC_ERR
)
2153 sky2
->net_stats
.rx_crc_errors
++;
2158 /* Transmit complete */
2159 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2161 struct sky2_port
*sky2
= netdev_priv(dev
);
2163 if (netif_running(dev
)) {
2165 sky2_tx_complete(sky2
, last
);
2166 netif_tx_unlock(dev
);
2170 /* Process status response ring */
2171 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2174 unsigned rx
[2] = { 0, 0 };
2175 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2179 while (hw
->st_idx
!= hwidx
) {
2180 struct sky2_port
*sky2
;
2181 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2182 unsigned port
= le
->css
& CSS_LINK_BIT
;
2183 struct net_device
*dev
;
2184 struct sk_buff
*skb
;
2188 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2190 dev
= hw
->dev
[port
];
2191 sky2
= netdev_priv(dev
);
2192 length
= le16_to_cpu(le
->length
);
2193 status
= le32_to_cpu(le
->status
);
2195 switch (le
->opcode
& ~HW_OWNER
) {
2198 skb
= sky2_receive(dev
, length
, status
);
2199 if (unlikely(!skb
)) {
2200 sky2
->net_stats
.rx_dropped
++;
2204 /* This chip reports checksum status differently */
2205 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2206 if (sky2
->rx_csum
&&
2207 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2208 (le
->css
& CSS_TCPUDPCSOK
))
2209 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2211 skb
->ip_summed
= CHECKSUM_NONE
;
2214 skb
->protocol
= eth_type_trans(skb
, dev
);
2215 sky2
->net_stats
.rx_packets
++;
2216 sky2
->net_stats
.rx_bytes
+= skb
->len
;
2217 dev
->last_rx
= jiffies
;
2219 #ifdef SKY2_VLAN_TAG_USED
2220 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2221 vlan_hwaccel_receive_skb(skb
,
2223 be16_to_cpu(sky2
->rx_tag
));
2226 netif_receive_skb(skb
);
2228 /* Stop after net poll weight */
2229 if (++work_done
>= to_do
)
2233 #ifdef SKY2_VLAN_TAG_USED
2235 sky2
->rx_tag
= length
;
2239 sky2
->rx_tag
= length
;
2246 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2249 /* Both checksum counters are programmed to start at
2250 * the same offset, so unless there is a problem they
2251 * should match. This failure is an early indication that
2252 * hardware receive checksumming won't work.
2254 if (likely(status
>> 16 == (status
& 0xffff))) {
2255 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2256 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2257 skb
->csum
= status
& 0xffff;
2259 printk(KERN_NOTICE PFX
"%s: hardware receive "
2260 "checksum problem (status = %#x)\n",
2263 sky2_write32(sky2
->hw
,
2264 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2270 /* TX index reports status for both ports */
2271 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2272 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2274 sky2_tx_done(hw
->dev
[1],
2275 ((status
>> 24) & 0xff)
2276 | (u16
)(length
& 0xf) << 8);
2280 if (net_ratelimit())
2281 printk(KERN_WARNING PFX
2282 "unknown status opcode 0x%x\n", le
->opcode
);
2286 /* Fully processed status ring so clear irq */
2287 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2291 sky2_rx_update(netdev_priv(hw
->dev
[0]), Q_R1
);
2294 sky2_rx_update(netdev_priv(hw
->dev
[1]), Q_R2
);
2299 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2301 struct net_device
*dev
= hw
->dev
[port
];
2303 if (net_ratelimit())
2304 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2307 if (status
& Y2_IS_PAR_RD1
) {
2308 if (net_ratelimit())
2309 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2312 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2315 if (status
& Y2_IS_PAR_WR1
) {
2316 if (net_ratelimit())
2317 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2320 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2323 if (status
& Y2_IS_PAR_MAC1
) {
2324 if (net_ratelimit())
2325 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2326 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2329 if (status
& Y2_IS_PAR_RX1
) {
2330 if (net_ratelimit())
2331 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2332 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2335 if (status
& Y2_IS_TCP_TXA1
) {
2336 if (net_ratelimit())
2337 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2339 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2343 static void sky2_hw_intr(struct sky2_hw
*hw
)
2345 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2347 if (status
& Y2_IS_TIST_OV
)
2348 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2350 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2353 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2354 if (net_ratelimit())
2355 dev_err(&hw
->pdev
->dev
, "PCI hardware error (0x%x)\n",
2358 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2359 sky2_pci_write16(hw
, PCI_STATUS
,
2360 pci_err
| PCI_STATUS_ERROR_BITS
);
2361 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2364 if (status
& Y2_IS_PCI_EXP
) {
2365 /* PCI-Express uncorrectable Error occurred */
2368 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2370 if (net_ratelimit())
2371 dev_err(&hw
->pdev
->dev
, "PCI Express error (0x%x)\n",
2374 /* clear the interrupt */
2375 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2376 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2378 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2380 if (pex_err
& PEX_FATAL_ERRORS
) {
2381 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2382 hwmsk
&= ~Y2_IS_PCI_EXP
;
2383 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2387 if (status
& Y2_HWE_L1_MASK
)
2388 sky2_hw_error(hw
, 0, status
);
2390 if (status
& Y2_HWE_L1_MASK
)
2391 sky2_hw_error(hw
, 1, status
);
2394 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2396 struct net_device
*dev
= hw
->dev
[port
];
2397 struct sky2_port
*sky2
= netdev_priv(dev
);
2398 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2400 if (netif_msg_intr(sky2
))
2401 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2404 if (status
& GM_IS_RX_CO_OV
)
2405 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2407 if (status
& GM_IS_TX_CO_OV
)
2408 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2410 if (status
& GM_IS_RX_FF_OR
) {
2411 ++sky2
->net_stats
.rx_fifo_errors
;
2412 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2415 if (status
& GM_IS_TX_FF_UR
) {
2416 ++sky2
->net_stats
.tx_fifo_errors
;
2417 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2421 /* This should never happen it is a bug. */
2422 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2423 u16 q
, unsigned ring_size
)
2425 struct net_device
*dev
= hw
->dev
[port
];
2426 struct sky2_port
*sky2
= netdev_priv(dev
);
2428 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2429 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2431 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2432 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2433 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2434 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2436 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2439 /* Check for lost IRQ once a second */
2440 static void sky2_watchdog(unsigned long arg
)
2442 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2444 if (sky2_read32(hw
, B0_ISRC
)) {
2445 struct net_device
*dev
= hw
->dev
[0];
2447 if (__netif_rx_schedule_prep(dev
))
2448 __netif_rx_schedule(dev
);
2452 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2455 /* Hardware/software error handling */
2456 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2458 if (net_ratelimit())
2459 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2461 if (status
& Y2_IS_HW_ERR
)
2464 if (status
& Y2_IS_IRQ_MAC1
)
2465 sky2_mac_intr(hw
, 0);
2467 if (status
& Y2_IS_IRQ_MAC2
)
2468 sky2_mac_intr(hw
, 1);
2470 if (status
& Y2_IS_CHK_RX1
)
2471 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2473 if (status
& Y2_IS_CHK_RX2
)
2474 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2476 if (status
& Y2_IS_CHK_TXA1
)
2477 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2479 if (status
& Y2_IS_CHK_TXA2
)
2480 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2483 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2485 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2487 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2489 if (unlikely(status
& Y2_IS_ERROR
))
2490 sky2_err_intr(hw
, status
);
2492 if (status
& Y2_IS_IRQ_PHY1
)
2493 sky2_phy_intr(hw
, 0);
2495 if (status
& Y2_IS_IRQ_PHY2
)
2496 sky2_phy_intr(hw
, 1);
2498 work_done
= sky2_status_intr(hw
, min(dev0
->quota
, *budget
));
2499 *budget
-= work_done
;
2500 dev0
->quota
-= work_done
;
2503 if (hw
->st_idx
!= sky2_read16(hw
, STAT_PUT_IDX
))
2506 /* Bug/Errata workaround?
2507 * Need to kick the TX irq moderation timer.
2509 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_START
) {
2510 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2511 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2513 netif_rx_complete(dev0
);
2515 sky2_read32(hw
, B0_Y2_SP_LISR
);
2519 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2521 struct sky2_hw
*hw
= dev_id
;
2522 struct net_device
*dev0
= hw
->dev
[0];
2525 /* Reading this mask interrupts as side effect */
2526 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2527 if (status
== 0 || status
== ~0)
2530 prefetch(&hw
->st_le
[hw
->st_idx
]);
2531 if (likely(__netif_rx_schedule_prep(dev0
)))
2532 __netif_rx_schedule(dev0
);
2537 #ifdef CONFIG_NET_POLL_CONTROLLER
2538 static void sky2_netpoll(struct net_device
*dev
)
2540 struct sky2_port
*sky2
= netdev_priv(dev
);
2541 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2543 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2544 __netif_rx_schedule(dev0
);
2548 /* Chip internal frequency for clock calculations */
2549 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2551 switch (hw
->chip_id
) {
2552 case CHIP_ID_YUKON_EC
:
2553 case CHIP_ID_YUKON_EC_U
:
2554 case CHIP_ID_YUKON_EX
:
2555 return 125; /* 125 Mhz */
2556 case CHIP_ID_YUKON_FE
:
2557 return 100; /* 100 Mhz */
2558 default: /* YUKON_XL */
2559 return 156; /* 156 Mhz */
2563 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2565 return sky2_mhz(hw
) * us
;
2568 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2570 return clk
/ sky2_mhz(hw
);
2574 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2578 /* Enable all clocks */
2579 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2581 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2583 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2584 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2585 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2590 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2592 /* This rev is really old, and requires untested workarounds */
2593 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2594 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2595 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2596 hw
->chip_id
, hw
->chip_rev
);
2600 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2602 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2603 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2604 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2611 static void sky2_reset(struct sky2_hw
*hw
)
2617 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2618 status
= sky2_read16(hw
, HCU_CCSR
);
2619 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2620 HCU_CCSR_UC_STATE_MSK
);
2621 sky2_write16(hw
, HCU_CCSR
, status
);
2623 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2624 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2627 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2628 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2630 /* clear PCI errors, if any */
2631 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2633 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2634 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2637 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2639 /* clear any PEX errors */
2640 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2641 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2646 for (i
= 0; i
< hw
->ports
; i
++) {
2647 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2648 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2650 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2651 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
2652 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
2656 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2658 /* Clear I2C IRQ noise */
2659 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2661 /* turn off hardware timer (unused) */
2662 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2663 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2665 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2667 /* Turn off descriptor polling */
2668 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2670 /* Turn off receive timestamp */
2671 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2672 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2674 /* enable the Tx Arbiters */
2675 for (i
= 0; i
< hw
->ports
; i
++)
2676 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2678 /* Initialize ram interface */
2679 for (i
= 0; i
< hw
->ports
; i
++) {
2680 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2682 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2683 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2684 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2685 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2686 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2687 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2688 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2689 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2690 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2691 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2692 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2693 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2696 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2698 for (i
= 0; i
< hw
->ports
; i
++)
2699 sky2_gmac_reset(hw
, i
);
2701 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2704 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2705 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2707 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2708 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2710 /* Set the list last index */
2711 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2713 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2714 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2716 /* set Status-FIFO ISR watermark */
2717 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2718 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2720 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2722 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2723 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2724 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2726 /* enable status unit */
2727 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2729 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2730 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2731 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2734 static void sky2_restart(struct work_struct
*work
)
2736 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2737 struct net_device
*dev
;
2741 sky2_write32(hw
, B0_IMSK
, 0);
2742 sky2_read32(hw
, B0_IMSK
);
2744 netif_poll_disable(hw
->dev
[0]);
2746 for (i
= 0; i
< hw
->ports
; i
++) {
2748 if (netif_running(dev
))
2753 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2754 netif_poll_enable(hw
->dev
[0]);
2756 for (i
= 0; i
< hw
->ports
; i
++) {
2758 if (netif_running(dev
)) {
2761 printk(KERN_INFO PFX
"%s: could not restart %d\n",
2771 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2773 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2776 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2778 const struct sky2_port
*sky2
= netdev_priv(dev
);
2780 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2781 wol
->wolopts
= sky2
->wol
;
2784 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2786 struct sky2_port
*sky2
= netdev_priv(dev
);
2787 struct sky2_hw
*hw
= sky2
->hw
;
2789 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2792 sky2
->wol
= wol
->wolopts
;
2794 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
)
2795 sky2_write32(hw
, B0_CTST
, sky2
->wol
2796 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2798 if (!netif_running(dev
))
2799 sky2_wol_init(sky2
);
2803 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2805 if (sky2_is_copper(hw
)) {
2806 u32 modes
= SUPPORTED_10baseT_Half
2807 | SUPPORTED_10baseT_Full
2808 | SUPPORTED_100baseT_Half
2809 | SUPPORTED_100baseT_Full
2810 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2812 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2813 modes
|= SUPPORTED_1000baseT_Half
2814 | SUPPORTED_1000baseT_Full
;
2817 return SUPPORTED_1000baseT_Half
2818 | SUPPORTED_1000baseT_Full
2823 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2825 struct sky2_port
*sky2
= netdev_priv(dev
);
2826 struct sky2_hw
*hw
= sky2
->hw
;
2828 ecmd
->transceiver
= XCVR_INTERNAL
;
2829 ecmd
->supported
= sky2_supported_modes(hw
);
2830 ecmd
->phy_address
= PHY_ADDR_MARV
;
2831 if (sky2_is_copper(hw
)) {
2832 ecmd
->supported
= SUPPORTED_10baseT_Half
2833 | SUPPORTED_10baseT_Full
2834 | SUPPORTED_100baseT_Half
2835 | SUPPORTED_100baseT_Full
2836 | SUPPORTED_1000baseT_Half
2837 | SUPPORTED_1000baseT_Full
2838 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2839 ecmd
->port
= PORT_TP
;
2840 ecmd
->speed
= sky2
->speed
;
2842 ecmd
->speed
= SPEED_1000
;
2843 ecmd
->port
= PORT_FIBRE
;
2846 ecmd
->advertising
= sky2
->advertising
;
2847 ecmd
->autoneg
= sky2
->autoneg
;
2848 ecmd
->duplex
= sky2
->duplex
;
2852 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2854 struct sky2_port
*sky2
= netdev_priv(dev
);
2855 const struct sky2_hw
*hw
= sky2
->hw
;
2856 u32 supported
= sky2_supported_modes(hw
);
2858 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2859 ecmd
->advertising
= supported
;
2865 switch (ecmd
->speed
) {
2867 if (ecmd
->duplex
== DUPLEX_FULL
)
2868 setting
= SUPPORTED_1000baseT_Full
;
2869 else if (ecmd
->duplex
== DUPLEX_HALF
)
2870 setting
= SUPPORTED_1000baseT_Half
;
2875 if (ecmd
->duplex
== DUPLEX_FULL
)
2876 setting
= SUPPORTED_100baseT_Full
;
2877 else if (ecmd
->duplex
== DUPLEX_HALF
)
2878 setting
= SUPPORTED_100baseT_Half
;
2884 if (ecmd
->duplex
== DUPLEX_FULL
)
2885 setting
= SUPPORTED_10baseT_Full
;
2886 else if (ecmd
->duplex
== DUPLEX_HALF
)
2887 setting
= SUPPORTED_10baseT_Half
;
2895 if ((setting
& supported
) == 0)
2898 sky2
->speed
= ecmd
->speed
;
2899 sky2
->duplex
= ecmd
->duplex
;
2902 sky2
->autoneg
= ecmd
->autoneg
;
2903 sky2
->advertising
= ecmd
->advertising
;
2905 if (netif_running(dev
)) {
2906 sky2_phy_reinit(sky2
);
2907 sky2_set_multicast(dev
);
2913 static void sky2_get_drvinfo(struct net_device
*dev
,
2914 struct ethtool_drvinfo
*info
)
2916 struct sky2_port
*sky2
= netdev_priv(dev
);
2918 strcpy(info
->driver
, DRV_NAME
);
2919 strcpy(info
->version
, DRV_VERSION
);
2920 strcpy(info
->fw_version
, "N/A");
2921 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2924 static const struct sky2_stat
{
2925 char name
[ETH_GSTRING_LEN
];
2928 { "tx_bytes", GM_TXO_OK_HI
},
2929 { "rx_bytes", GM_RXO_OK_HI
},
2930 { "tx_broadcast", GM_TXF_BC_OK
},
2931 { "rx_broadcast", GM_RXF_BC_OK
},
2932 { "tx_multicast", GM_TXF_MC_OK
},
2933 { "rx_multicast", GM_RXF_MC_OK
},
2934 { "tx_unicast", GM_TXF_UC_OK
},
2935 { "rx_unicast", GM_RXF_UC_OK
},
2936 { "tx_mac_pause", GM_TXF_MPAUSE
},
2937 { "rx_mac_pause", GM_RXF_MPAUSE
},
2938 { "collisions", GM_TXF_COL
},
2939 { "late_collision",GM_TXF_LAT_COL
},
2940 { "aborted", GM_TXF_ABO_COL
},
2941 { "single_collisions", GM_TXF_SNG_COL
},
2942 { "multi_collisions", GM_TXF_MUL_COL
},
2944 { "rx_short", GM_RXF_SHT
},
2945 { "rx_runt", GM_RXE_FRAG
},
2946 { "rx_64_byte_packets", GM_RXF_64B
},
2947 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2948 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2949 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2950 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2951 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2952 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2953 { "rx_too_long", GM_RXF_LNG_ERR
},
2954 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2955 { "rx_jabber", GM_RXF_JAB_PKT
},
2956 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2958 { "tx_64_byte_packets", GM_TXF_64B
},
2959 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2960 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2961 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2962 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2963 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2964 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2965 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2968 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2970 struct sky2_port
*sky2
= netdev_priv(dev
);
2972 return sky2
->rx_csum
;
2975 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2977 struct sky2_port
*sky2
= netdev_priv(dev
);
2979 sky2
->rx_csum
= data
;
2981 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2982 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2987 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2989 struct sky2_port
*sky2
= netdev_priv(netdev
);
2990 return sky2
->msg_enable
;
2993 static int sky2_nway_reset(struct net_device
*dev
)
2995 struct sky2_port
*sky2
= netdev_priv(dev
);
2997 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
3000 sky2_phy_reinit(sky2
);
3001 sky2_set_multicast(dev
);
3006 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3008 struct sky2_hw
*hw
= sky2
->hw
;
3009 unsigned port
= sky2
->port
;
3012 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3013 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3014 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3015 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3017 for (i
= 2; i
< count
; i
++)
3018 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3021 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3023 struct sky2_port
*sky2
= netdev_priv(netdev
);
3024 sky2
->msg_enable
= value
;
3027 static int sky2_get_stats_count(struct net_device
*dev
)
3029 return ARRAY_SIZE(sky2_stats
);
3032 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3033 struct ethtool_stats
*stats
, u64
* data
)
3035 struct sky2_port
*sky2
= netdev_priv(dev
);
3037 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3040 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3044 switch (stringset
) {
3046 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3047 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3048 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3053 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
3055 struct sky2_port
*sky2
= netdev_priv(dev
);
3056 return &sky2
->net_stats
;
3059 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3061 struct sky2_port
*sky2
= netdev_priv(dev
);
3062 struct sky2_hw
*hw
= sky2
->hw
;
3063 unsigned port
= sky2
->port
;
3064 const struct sockaddr
*addr
= p
;
3066 if (!is_valid_ether_addr(addr
->sa_data
))
3067 return -EADDRNOTAVAIL
;
3069 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3070 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3071 dev
->dev_addr
, ETH_ALEN
);
3072 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3073 dev
->dev_addr
, ETH_ALEN
);
3075 /* virtual address for data */
3076 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3078 /* physical address: used for pause frames */
3079 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3084 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3088 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3089 filter
[bit
>> 3] |= 1 << (bit
& 7);
3092 static void sky2_set_multicast(struct net_device
*dev
)
3094 struct sky2_port
*sky2
= netdev_priv(dev
);
3095 struct sky2_hw
*hw
= sky2
->hw
;
3096 unsigned port
= sky2
->port
;
3097 struct dev_mc_list
*list
= dev
->mc_list
;
3101 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3103 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3104 memset(filter
, 0, sizeof(filter
));
3106 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3107 reg
|= GM_RXCR_UCF_ENA
;
3109 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3110 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3111 else if (dev
->flags
& IFF_ALLMULTI
)
3112 memset(filter
, 0xff, sizeof(filter
));
3113 else if (dev
->mc_count
== 0 && !rx_pause
)
3114 reg
&= ~GM_RXCR_MCF_ENA
;
3117 reg
|= GM_RXCR_MCF_ENA
;
3120 sky2_add_filter(filter
, pause_mc_addr
);
3122 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3123 sky2_add_filter(filter
, list
->dmi_addr
);
3126 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3127 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3128 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3129 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3130 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3131 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3132 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3133 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3135 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3138 /* Can have one global because blinking is controlled by
3139 * ethtool and that is always under RTNL mutex
3141 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
3145 switch (hw
->chip_id
) {
3146 case CHIP_ID_YUKON_XL
:
3147 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3148 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3149 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3150 on
? (PHY_M_LEDC_LOS_CTRL(1) |
3151 PHY_M_LEDC_INIT_CTRL(7) |
3152 PHY_M_LEDC_STA1_CTRL(7) |
3153 PHY_M_LEDC_STA0_CTRL(7))
3156 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3160 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3161 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3162 on
? PHY_M_LED_ALL
: 0);
3166 /* blink LED's for finding board */
3167 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3169 struct sky2_port
*sky2
= netdev_priv(dev
);
3170 struct sky2_hw
*hw
= sky2
->hw
;
3171 unsigned port
= sky2
->port
;
3172 u16 ledctrl
, ledover
= 0;
3177 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3178 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3182 /* save initial values */
3183 spin_lock_bh(&sky2
->phy_lock
);
3184 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3185 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3186 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3187 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3188 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3190 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3191 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3195 while (!interrupted
&& ms
> 0) {
3196 sky2_led(hw
, port
, onoff
);
3199 spin_unlock_bh(&sky2
->phy_lock
);
3200 interrupted
= msleep_interruptible(250);
3201 spin_lock_bh(&sky2
->phy_lock
);
3206 /* resume regularly scheduled programming */
3207 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3208 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3209 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3210 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3211 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3213 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3214 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3216 spin_unlock_bh(&sky2
->phy_lock
);
3221 static void sky2_get_pauseparam(struct net_device
*dev
,
3222 struct ethtool_pauseparam
*ecmd
)
3224 struct sky2_port
*sky2
= netdev_priv(dev
);
3226 switch (sky2
->flow_mode
) {
3228 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3231 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3234 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3237 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3240 ecmd
->autoneg
= sky2
->autoneg
;
3243 static int sky2_set_pauseparam(struct net_device
*dev
,
3244 struct ethtool_pauseparam
*ecmd
)
3246 struct sky2_port
*sky2
= netdev_priv(dev
);
3248 sky2
->autoneg
= ecmd
->autoneg
;
3249 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3251 if (netif_running(dev
))
3252 sky2_phy_reinit(sky2
);
3257 static int sky2_get_coalesce(struct net_device
*dev
,
3258 struct ethtool_coalesce
*ecmd
)
3260 struct sky2_port
*sky2
= netdev_priv(dev
);
3261 struct sky2_hw
*hw
= sky2
->hw
;
3263 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3264 ecmd
->tx_coalesce_usecs
= 0;
3266 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3267 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3269 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3271 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3272 ecmd
->rx_coalesce_usecs
= 0;
3274 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3275 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3277 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3279 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3280 ecmd
->rx_coalesce_usecs_irq
= 0;
3282 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3283 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3286 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3291 /* Note: this affect both ports */
3292 static int sky2_set_coalesce(struct net_device
*dev
,
3293 struct ethtool_coalesce
*ecmd
)
3295 struct sky2_port
*sky2
= netdev_priv(dev
);
3296 struct sky2_hw
*hw
= sky2
->hw
;
3297 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3299 if (ecmd
->tx_coalesce_usecs
> tmax
||
3300 ecmd
->rx_coalesce_usecs
> tmax
||
3301 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3304 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3306 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3308 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3311 if (ecmd
->tx_coalesce_usecs
== 0)
3312 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3314 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3315 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3316 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3318 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3320 if (ecmd
->rx_coalesce_usecs
== 0)
3321 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3323 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3324 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3325 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3327 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3329 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3330 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3332 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3333 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3334 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3336 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3340 static void sky2_get_ringparam(struct net_device
*dev
,
3341 struct ethtool_ringparam
*ering
)
3343 struct sky2_port
*sky2
= netdev_priv(dev
);
3345 ering
->rx_max_pending
= RX_MAX_PENDING
;
3346 ering
->rx_mini_max_pending
= 0;
3347 ering
->rx_jumbo_max_pending
= 0;
3348 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3350 ering
->rx_pending
= sky2
->rx_pending
;
3351 ering
->rx_mini_pending
= 0;
3352 ering
->rx_jumbo_pending
= 0;
3353 ering
->tx_pending
= sky2
->tx_pending
;
3356 static int sky2_set_ringparam(struct net_device
*dev
,
3357 struct ethtool_ringparam
*ering
)
3359 struct sky2_port
*sky2
= netdev_priv(dev
);
3362 if (ering
->rx_pending
> RX_MAX_PENDING
||
3363 ering
->rx_pending
< 8 ||
3364 ering
->tx_pending
< MAX_SKB_TX_LE
||
3365 ering
->tx_pending
> TX_RING_SIZE
- 1)
3368 if (netif_running(dev
))
3371 sky2
->rx_pending
= ering
->rx_pending
;
3372 sky2
->tx_pending
= ering
->tx_pending
;
3374 if (netif_running(dev
)) {
3379 sky2_set_multicast(dev
);
3385 static int sky2_get_regs_len(struct net_device
*dev
)
3391 * Returns copy of control register region
3392 * Note: ethtool_get_regs always provides full size (16k) buffer
3394 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3397 const struct sky2_port
*sky2
= netdev_priv(dev
);
3398 const void __iomem
*io
= sky2
->hw
->regs
;
3401 memset(p
, 0, regs
->len
);
3403 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3405 /* skip diagnostic ram region */
3406 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
, 0x2000 - B3_RI_WTO_R1
);
3408 /* copy GMAC registers */
3409 memcpy_fromio(p
+ BASE_GMAC_1
, io
+ BASE_GMAC_1
, 0x1000);
3410 if (sky2
->hw
->ports
> 1)
3411 memcpy_fromio(p
+ BASE_GMAC_2
, io
+ BASE_GMAC_2
, 0x1000);
3415 /* In order to do Jumbo packets on these chips, need to turn off the
3416 * transmit store/forward. Therefore checksum offload won't work.
3418 static int no_tx_offload(struct net_device
*dev
)
3420 const struct sky2_port
*sky2
= netdev_priv(dev
);
3421 const struct sky2_hw
*hw
= sky2
->hw
;
3423 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3426 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3428 if (data
&& no_tx_offload(dev
))
3431 return ethtool_op_set_tx_csum(dev
, data
);
3435 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3437 if (data
&& no_tx_offload(dev
))
3440 return ethtool_op_set_tso(dev
, data
);
3443 static int sky2_get_eeprom_len(struct net_device
*dev
)
3445 struct sky2_port
*sky2
= netdev_priv(dev
);
3448 reg2
= sky2_pci_read32(sky2
->hw
, PCI_DEV_REG2
);
3449 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3452 static u32
sky2_vpd_read(struct sky2_hw
*hw
, int cap
, u16 offset
)
3454 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
3456 while (!(sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
))
3458 return sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
3461 static void sky2_vpd_write(struct sky2_hw
*hw
, int cap
, u16 offset
, u32 val
)
3463 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
3464 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
3467 } while (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
);
3470 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3473 struct sky2_port
*sky2
= netdev_priv(dev
);
3474 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3475 int length
= eeprom
->len
;
3476 u16 offset
= eeprom
->offset
;
3481 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
3483 while (length
> 0) {
3484 u32 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3485 int n
= min_t(int, length
, sizeof(val
));
3487 memcpy(data
, &val
, n
);
3495 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3498 struct sky2_port
*sky2
= netdev_priv(dev
);
3499 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3500 int length
= eeprom
->len
;
3501 u16 offset
= eeprom
->offset
;
3506 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
3509 while (length
> 0) {
3511 int n
= min_t(int, length
, sizeof(val
));
3513 if (n
< sizeof(val
))
3514 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3515 memcpy(&val
, data
, n
);
3517 sky2_vpd_write(sky2
->hw
, cap
, offset
, val
);
3527 static const struct ethtool_ops sky2_ethtool_ops
= {
3528 .get_settings
= sky2_get_settings
,
3529 .set_settings
= sky2_set_settings
,
3530 .get_drvinfo
= sky2_get_drvinfo
,
3531 .get_wol
= sky2_get_wol
,
3532 .set_wol
= sky2_set_wol
,
3533 .get_msglevel
= sky2_get_msglevel
,
3534 .set_msglevel
= sky2_set_msglevel
,
3535 .nway_reset
= sky2_nway_reset
,
3536 .get_regs_len
= sky2_get_regs_len
,
3537 .get_regs
= sky2_get_regs
,
3538 .get_link
= ethtool_op_get_link
,
3539 .get_eeprom_len
= sky2_get_eeprom_len
,
3540 .get_eeprom
= sky2_get_eeprom
,
3541 .set_eeprom
= sky2_set_eeprom
,
3542 .get_sg
= ethtool_op_get_sg
,
3543 .set_sg
= ethtool_op_set_sg
,
3544 .get_tx_csum
= ethtool_op_get_tx_csum
,
3545 .set_tx_csum
= sky2_set_tx_csum
,
3546 .get_tso
= ethtool_op_get_tso
,
3547 .set_tso
= sky2_set_tso
,
3548 .get_rx_csum
= sky2_get_rx_csum
,
3549 .set_rx_csum
= sky2_set_rx_csum
,
3550 .get_strings
= sky2_get_strings
,
3551 .get_coalesce
= sky2_get_coalesce
,
3552 .set_coalesce
= sky2_set_coalesce
,
3553 .get_ringparam
= sky2_get_ringparam
,
3554 .set_ringparam
= sky2_set_ringparam
,
3555 .get_pauseparam
= sky2_get_pauseparam
,
3556 .set_pauseparam
= sky2_set_pauseparam
,
3557 .phys_id
= sky2_phys_id
,
3558 .get_stats_count
= sky2_get_stats_count
,
3559 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3562 #ifdef CONFIG_SKY2_DEBUG
3564 static struct dentry
*sky2_debug
;
3566 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
3568 struct net_device
*dev
= seq
->private;
3569 const struct sky2_port
*sky2
= netdev_priv(dev
);
3570 const struct sky2_hw
*hw
= sky2
->hw
;
3571 unsigned port
= sky2
->port
;
3575 if (!netif_running(dev
))
3578 seq_printf(seq
, "IRQ src=%x mask=%x control=%x\n",
3579 sky2_read32(hw
, B0_ISRC
),
3580 sky2_read32(hw
, B0_IMSK
),
3581 sky2_read32(hw
, B0_Y2_SP_ICR
));
3583 netif_poll_disable(hw
->dev
[0]);
3584 last
= sky2_read16(hw
, STAT_PUT_IDX
);
3586 if (hw
->st_idx
== last
)
3587 seq_puts(seq
, "Status ring (empty)\n");
3589 seq_puts(seq
, "Status ring\n");
3590 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
3591 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
3592 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
3593 seq_printf(seq
, "[%d] %#x %d %#x\n",
3594 idx
, le
->opcode
, le
->length
, le
->status
);
3596 seq_puts(seq
, "\n");
3599 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
3600 sky2
->tx_cons
, sky2
->tx_prod
,
3601 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
3602 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
3604 /* Dump contents of tx ring */
3606 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< TX_RING_SIZE
;
3607 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
3608 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
3609 u32 a
= le32_to_cpu(le
->addr
);
3612 seq_printf(seq
, "%u:", idx
);
3615 switch(le
->opcode
& ~HW_OWNER
) {
3617 seq_printf(seq
, " %#x:", a
);
3620 seq_printf(seq
, " mtu=%d", a
);
3623 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
3626 seq_printf(seq
, " csum=%#x", a
);
3629 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
3632 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
3635 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
3638 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
3639 a
, le16_to_cpu(le
->length
));
3642 if (le
->ctrl
& EOP
) {
3643 seq_putc(seq
, '\n');
3648 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
3649 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
3650 last
= sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
3651 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
3653 netif_poll_enable(hw
->dev
[0]);
3657 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
3659 return single_open(file
, sky2_debug_show
, inode
->i_private
);
3662 static const struct file_operations sky2_debug_fops
= {
3663 .owner
= THIS_MODULE
,
3664 .open
= sky2_debug_open
,
3666 .llseek
= seq_lseek
,
3667 .release
= single_release
,
3671 * Use network device events to create/remove/rename
3672 * debugfs file entries
3674 static int sky2_device_event(struct notifier_block
*unused
,
3675 unsigned long event
, void *ptr
)
3677 struct net_device
*dev
= ptr
;
3679 if (dev
->open
== sky2_up
) {
3680 struct sky2_port
*sky2
= netdev_priv(dev
);
3683 case NETDEV_CHANGENAME
:
3684 if (!netif_running(dev
))
3688 case NETDEV_GOING_DOWN
:
3689 if (sky2
->debugfs
) {
3690 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
3692 debugfs_remove(sky2
->debugfs
);
3693 sky2
->debugfs
= NULL
;
3696 if (event
!= NETDEV_CHANGENAME
)
3698 /* fallthrough for changename */
3702 d
= debugfs_create_file(dev
->name
, S_IRUGO
,
3705 if (d
== NULL
|| IS_ERR(d
))
3706 printk(KERN_INFO PFX
3707 "%s: debugfs create failed\n",
3719 static struct notifier_block sky2_notifier
= {
3720 .notifier_call
= sky2_device_event
,
3724 static __init
void sky2_debug_init(void)
3728 ent
= debugfs_create_dir("sky2", NULL
);
3729 if (!ent
|| IS_ERR(ent
))
3733 register_netdevice_notifier(&sky2_notifier
);
3736 static __exit
void sky2_debug_cleanup(void)
3739 unregister_netdevice_notifier(&sky2_notifier
);
3740 debugfs_remove(sky2_debug
);
3746 #define sky2_debug_init()
3747 #define sky2_debug_cleanup()
3751 /* Initialize network device */
3752 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3754 int highmem
, int wol
)
3756 struct sky2_port
*sky2
;
3757 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3760 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed");
3764 SET_MODULE_OWNER(dev
);
3765 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3766 dev
->irq
= hw
->pdev
->irq
;
3767 dev
->open
= sky2_up
;
3768 dev
->stop
= sky2_down
;
3769 dev
->do_ioctl
= sky2_ioctl
;
3770 dev
->hard_start_xmit
= sky2_xmit_frame
;
3771 dev
->get_stats
= sky2_get_stats
;
3772 dev
->set_multicast_list
= sky2_set_multicast
;
3773 dev
->set_mac_address
= sky2_set_mac_address
;
3774 dev
->change_mtu
= sky2_change_mtu
;
3775 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3776 dev
->tx_timeout
= sky2_tx_timeout
;
3777 dev
->watchdog_timeo
= TX_WATCHDOG
;
3779 dev
->poll
= sky2_poll
;
3780 dev
->weight
= NAPI_WEIGHT
;
3781 #ifdef CONFIG_NET_POLL_CONTROLLER
3782 /* Network console (only works on port 0)
3783 * because netpoll makes assumptions about NAPI
3786 dev
->poll_controller
= sky2_netpoll
;
3789 sky2
= netdev_priv(dev
);
3792 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3794 /* Auto speed and flow control */
3795 sky2
->autoneg
= AUTONEG_ENABLE
;
3796 sky2
->flow_mode
= FC_BOTH
;
3800 sky2
->advertising
= sky2_supported_modes(hw
);
3804 spin_lock_init(&sky2
->phy_lock
);
3805 sky2
->tx_pending
= TX_DEF_PENDING
;
3806 sky2
->rx_pending
= RX_DEF_PENDING
;
3808 hw
->dev
[port
] = dev
;
3812 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
3814 dev
->features
|= NETIF_F_HIGHDMA
;
3816 #ifdef SKY2_VLAN_TAG_USED
3817 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3818 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3821 /* read the mac address */
3822 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3823 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3828 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3830 const struct sky2_port
*sky2
= netdev_priv(dev
);
3832 if (netif_msg_probe(sky2
))
3833 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3835 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3836 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3839 /* Handle software interrupt used during MSI test */
3840 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3842 struct sky2_hw
*hw
= dev_id
;
3843 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3848 if (status
& Y2_IS_IRQ_SW
) {
3850 wake_up(&hw
->msi_wait
);
3851 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3853 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3858 /* Test interrupt path by forcing a a software IRQ */
3859 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3861 struct pci_dev
*pdev
= hw
->pdev
;
3864 init_waitqueue_head (&hw
->msi_wait
);
3866 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3868 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
3870 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3874 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3875 sky2_read8(hw
, B0_CTST
);
3877 wait_event_timeout(hw
->msi_wait
, hw
->msi
, HZ
/10);
3880 /* MSI test failed, go back to INTx mode */
3881 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
3882 "switching to INTx mode.\n");
3885 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3888 sky2_write32(hw
, B0_IMSK
, 0);
3889 sky2_read32(hw
, B0_IMSK
);
3891 free_irq(pdev
->irq
, hw
);
3896 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
3898 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3903 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
3905 return value
& PCI_PM_CTRL_PME_ENABLE
;
3908 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3909 const struct pci_device_id
*ent
)
3911 struct net_device
*dev
;
3913 int err
, using_dac
= 0, wol_default
;
3915 err
= pci_enable_device(pdev
);
3917 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3921 err
= pci_request_regions(pdev
, DRV_NAME
);
3923 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3924 goto err_out_disable
;
3927 pci_set_master(pdev
);
3929 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3930 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3932 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3934 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
3935 "for consistent allocations\n");
3936 goto err_out_free_regions
;
3939 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3941 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3942 goto err_out_free_regions
;
3946 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
3949 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3951 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3952 goto err_out_free_regions
;
3957 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3959 dev_err(&pdev
->dev
, "cannot map device registers\n");
3960 goto err_out_free_hw
;
3964 /* The sk98lin vendor driver uses hardware byte swapping but
3965 * this driver uses software swapping.
3969 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3970 reg
&= ~PCI_REV_DESC
;
3971 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3975 /* ring for status responses */
3976 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3979 goto err_out_iounmap
;
3981 err
= sky2_init(hw
);
3983 goto err_out_iounmap
;
3985 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3986 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3987 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3988 hw
->chip_id
, hw
->chip_rev
);
3992 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
3995 goto err_out_free_pci
;
3998 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3999 err
= sky2_test_msi(hw
);
4000 if (err
== -EOPNOTSUPP
)
4001 pci_disable_msi(pdev
);
4003 goto err_out_free_netdev
;
4006 err
= register_netdev(dev
);
4008 dev_err(&pdev
->dev
, "cannot register net device\n");
4009 goto err_out_free_netdev
;
4012 err
= request_irq(pdev
->irq
, sky2_intr
, hw
->msi
? 0 : IRQF_SHARED
,
4015 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4016 goto err_out_unregister
;
4018 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4020 sky2_show_addr(dev
);
4022 if (hw
->ports
> 1) {
4023 struct net_device
*dev1
;
4025 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4027 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
4028 else if ((err
= register_netdev(dev1
))) {
4029 dev_warn(&pdev
->dev
,
4030 "register of second port failed (%d)\n", err
);
4034 sky2_show_addr(dev1
);
4037 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
4038 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4040 pci_set_drvdata(pdev
, hw
);
4046 pci_disable_msi(pdev
);
4047 unregister_netdev(dev
);
4048 err_out_free_netdev
:
4051 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4052 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4057 err_out_free_regions
:
4058 pci_release_regions(pdev
);
4060 pci_disable_device(pdev
);
4062 pci_set_drvdata(pdev
, NULL
);
4066 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4068 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4069 struct net_device
*dev0
, *dev1
;
4074 del_timer_sync(&hw
->watchdog_timer
);
4076 flush_scheduled_work();
4078 sky2_write32(hw
, B0_IMSK
, 0);
4079 synchronize_irq(hw
->pdev
->irq
);
4084 unregister_netdev(dev1
);
4085 unregister_netdev(dev0
);
4089 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
4090 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4091 sky2_read8(hw
, B0_CTST
);
4093 free_irq(pdev
->irq
, hw
);
4095 pci_disable_msi(pdev
);
4096 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4097 pci_release_regions(pdev
);
4098 pci_disable_device(pdev
);
4106 pci_set_drvdata(pdev
, NULL
);
4110 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4112 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4118 netif_poll_disable(hw
->dev
[0]);
4120 for (i
= 0; i
< hw
->ports
; i
++) {
4121 struct net_device
*dev
= hw
->dev
[i
];
4122 struct sky2_port
*sky2
= netdev_priv(dev
);
4124 if (netif_running(dev
))
4128 sky2_wol_init(sky2
);
4133 sky2_write32(hw
, B0_IMSK
, 0);
4136 pci_save_state(pdev
);
4137 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4138 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4143 static int sky2_resume(struct pci_dev
*pdev
)
4145 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4151 err
= pci_set_power_state(pdev
, PCI_D0
);
4155 err
= pci_restore_state(pdev
);
4159 pci_enable_wake(pdev
, PCI_D0
, 0);
4161 /* Re-enable all clocks */
4162 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
4163 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4167 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4169 for (i
= 0; i
< hw
->ports
; i
++) {
4170 struct net_device
*dev
= hw
->dev
[i
];
4171 if (netif_running(dev
)) {
4174 printk(KERN_ERR PFX
"%s: could not up: %d\n",
4180 sky2_set_multicast(dev
);
4184 netif_poll_enable(hw
->dev
[0]);
4188 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4189 pci_disable_device(pdev
);
4194 static void sky2_shutdown(struct pci_dev
*pdev
)
4196 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4202 netif_poll_disable(hw
->dev
[0]);
4204 for (i
= 0; i
< hw
->ports
; i
++) {
4205 struct net_device
*dev
= hw
->dev
[i
];
4206 struct sky2_port
*sky2
= netdev_priv(dev
);
4210 sky2_wol_init(sky2
);
4217 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4218 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4220 pci_disable_device(pdev
);
4221 pci_set_power_state(pdev
, PCI_D3hot
);
4225 static struct pci_driver sky2_driver
= {
4227 .id_table
= sky2_id_table
,
4228 .probe
= sky2_probe
,
4229 .remove
= __devexit_p(sky2_remove
),
4231 .suspend
= sky2_suspend
,
4232 .resume
= sky2_resume
,
4234 .shutdown
= sky2_shutdown
,
4237 static int __init
sky2_init_module(void)
4240 return pci_register_driver(&sky2_driver
);
4243 static void __exit
sky2_cleanup_module(void)
4245 pci_unregister_driver(&sky2_driver
);
4246 sky2_debug_cleanup();
4249 module_init(sky2_init_module
);
4250 module_exit(sky2_cleanup_module
);
4252 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4253 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4254 MODULE_LICENSE("GPL");
4255 MODULE_VERSION(DRV_VERSION
);