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net: fix network drivers ndo_start_xmit() return values (part 8)
[mirror_ubuntu-zesty-kernel.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <net/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.22"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66
67 #define TX_RING_SIZE 512
68 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
69 #define TX_MIN_PENDING 64
70 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
71
72 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
73 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
74 #define TX_WATCHDOG (5 * HZ)
75 #define NAPI_WEIGHT 64
76 #define PHY_RETRIES 1000
77
78 #define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
100 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 static void sky2_set_multicast(struct net_device *dev);
151
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 {
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
167 return 0;
168
169 udelay(10);
170 }
171
172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
173 return -ETIMEDOUT;
174
175 io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
178 }
179
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 {
182 int i;
183
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
197 udelay(10);
198 }
199
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
201 return -ETIMEDOUT;
202 io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
205 }
206
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
208 {
209 u16 v;
210 __gm_phy_read(hw, port, reg, &v);
211 return v;
212 }
213
214
215 static void sky2_power_on(struct sky2_hw *hw)
216 {
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
234 u32 reg;
235
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
242
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
247
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
254
255 sky2_read32(hw, B2_GP_IO);
256 }
257 }
258
259 static void sky2_power_aux(struct sky2_hw *hw)
260 {
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
275 }
276
277 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
278 {
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
283
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292 }
293
294 /* flow control to advertise bits */
295 static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300 };
301
302 /* flow control to advertise bits when using 1000BaseX */
303 static const u16 fiber_fc_adv[] = {
304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
308 };
309
310 /* flow control to GMA disable bits */
311 static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316 };
317
318
319 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320 {
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
323
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
329 PHY_M_EC_MAC_S_MSK);
330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
333 if (hw->chip_id == CHIP_ID_YUKON_EC)
334 /* set downshift counter to 3x and enable downshift */
335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 if (sky2_is_copper(hw)) {
345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
365 /* downshift on PHY 88E1112 and 88E1149 is changed */
366 if (sky2->autoneg == AUTONEG_ENABLE
367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
368 /* set downshift counter to 3x and enable downshift */
369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
378 }
379
380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
385
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401 }
402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
404 }
405
406 ctrl = PHY_CT_RESET;
407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
409 reg = 0;
410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
412 if (sky2_is_copper(hw)) {
413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
425
426 adv |= copper_fc_adv[sky2->flow_mode];
427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
432
433 adv |= fiber_fc_adv[sky2->flow_mode];
434 }
435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
448 reg |= GM_GPCR_SPEED_1000;
449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
452 reg |= GM_GPCR_SPEED_100;
453 break;
454 }
455
456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
461
462
463 reg |= gm_fc_disable[sky2->flow_mode];
464
465 /* Forward pause packets to GMAC? */
466 if (sky2->flow_mode & FC_RX)
467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
470 }
471
472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
474 if (hw->flags & SKY2_HW_GIGABIT)
475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
515 case CHIP_ID_YUKON_XL:
516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
536
537 /* restore page register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
539 break;
540
541 case CHIP_ID_YUKON_EC_U:
542 case CHIP_ID_YUKON_EX:
543 case CHIP_ID_YUKON_SUPR:
544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
566
567 /* turn off the Rx LED (LED_RX) */
568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
569 }
570
571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
572 /* apply fixes in PHY AFE */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
575 /* increase differential signal amplitude in 10BASE-T */
576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
578
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
584
585 /* set page register to 0 */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
594 /* no effect on Yukon-XL */
595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
596
597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
600 }
601
602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
606
607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612 }
613
614 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
618 {
619 u32 reg1;
620
621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
623 reg1 &= ~phy_power[port];
624
625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
626 reg1 |= coma_mode[port];
627
628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
636 }
637
638 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639 {
640 u32 reg1;
641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
670
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
689 }
690
691 /* Force a renegotiation */
692 static void sky2_phy_reinit(struct sky2_port *sky2)
693 {
694 spin_lock_bh(&sky2->phy_lock);
695 sky2_phy_init(sky2->hw, sky2->port);
696 spin_unlock_bh(&sky2->phy_lock);
697 }
698
699 /* Put device in state to listen for Wake On Lan */
700 static void sky2_wol_init(struct sky2_port *sky2)
701 {
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
759 reg1 |= PCI_Y2_PME_LEGACY;
760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765 }
766
767 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768 {
769 struct net_device *dev = hw->dev[port];
770
771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
777
778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
781
782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
792
793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
798 }
799 }
800
801 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802 {
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
805 u32 rx_reg;
806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
827
828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
831 spin_lock_bh(&sky2->phy_lock);
832 sky2_phy_power_up(hw, port);
833 sky2_phy_init(hw, port);
834 spin_unlock_bh(&sky2->phy_lock);
835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
864
865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
886 rx_reg |= GMF_RX_OVER_ON;
887
888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
889
890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
897
898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
909
910 /* On chips without ram buffer, pause is controled by MAC level */
911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
914
915 sky2_set_tx_stfwd(hw, port);
916 }
917
918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
925 }
926
927 /* Assign Ram Buffer allocation to queue */
928 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
929 {
930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
936
937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
944 u32 tp = space - space/4;
945
946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
952
953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
965 }
966
967 /* Setup Bus Memory Interface */
968 static void sky2_qset(struct sky2_hw *hw, u16 q)
969 {
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
974 }
975
976 /* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
979 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
980 u64 addr, u32 last)
981 {
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
990 }
991
992 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993 {
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
997 le->ctrl = 0;
998 return le;
999 }
1000
1001 static void tx_init(struct sky2_port *sky2)
1002 {
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
1012 }
1013
1014 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016 {
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018 }
1019
1020 /* Update chip's next pointer */
1021 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1022 {
1023 /* Make sure write' to descriptors are complete before we tell hardware */
1024 wmb();
1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
1029 }
1030
1031
1032 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033 {
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1036 le->ctrl = 0;
1037 return le;
1038 }
1039
1040 /* Build description to hardware for one receive segment */
1041 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
1043 {
1044 struct sky2_rx_le *le;
1045
1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
1047 le = sky2_next_rx(sky2);
1048 le->addr = cpu_to_le32(upper_32_bits(map));
1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
1051
1052 le = sky2_next_rx(sky2);
1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
1055 le->opcode = op | HW_OWNER;
1056 }
1057
1058 /* Build description to hardware for one possibly fragmented skb */
1059 static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061 {
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068 }
1069
1070
1071 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1072 unsigned size)
1073 {
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
1089 return 0;
1090 }
1091
1092 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093 {
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104 }
1105
1106 /* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
1110 static void rx_set_checksum(struct sky2_port *sky2)
1111 {
1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
1113
1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
1117
1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1121 }
1122
1123 /*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133 static void sky2_rx_stop(struct sky2_port *sky2)
1134 {
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149 stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1154 mmiowb();
1155 }
1156
1157 /* Clean out receive buffer area, assumes receiver hardware stopped */
1158 static void sky2_rx_clean(struct sky2_port *sky2)
1159 {
1160 unsigned i;
1161
1162 memset(sky2->rx_le, 0, RX_LE_BYTES);
1163 for (i = 0; i < sky2->rx_pending; i++) {
1164 struct rx_ring_info *re = sky2->rx_ring + i;
1165
1166 if (re->skb) {
1167 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1168 kfree_skb(re->skb);
1169 re->skb = NULL;
1170 }
1171 }
1172 }
1173
1174 /* Basic MII support */
1175 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1176 {
1177 struct mii_ioctl_data *data = if_mii(ifr);
1178 struct sky2_port *sky2 = netdev_priv(dev);
1179 struct sky2_hw *hw = sky2->hw;
1180 int err = -EOPNOTSUPP;
1181
1182 if (!netif_running(dev))
1183 return -ENODEV; /* Phy still in reset */
1184
1185 switch (cmd) {
1186 case SIOCGMIIPHY:
1187 data->phy_id = PHY_ADDR_MARV;
1188
1189 /* fallthru */
1190 case SIOCGMIIREG: {
1191 u16 val = 0;
1192
1193 spin_lock_bh(&sky2->phy_lock);
1194 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1195 spin_unlock_bh(&sky2->phy_lock);
1196
1197 data->val_out = val;
1198 break;
1199 }
1200
1201 case SIOCSMIIREG:
1202 if (!capable(CAP_NET_ADMIN))
1203 return -EPERM;
1204
1205 spin_lock_bh(&sky2->phy_lock);
1206 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1207 data->val_in);
1208 spin_unlock_bh(&sky2->phy_lock);
1209 break;
1210 }
1211 return err;
1212 }
1213
1214 #ifdef SKY2_VLAN_TAG_USED
1215 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1216 {
1217 if (onoff) {
1218 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1219 RX_VLAN_STRIP_ON);
1220 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1221 TX_VLAN_TAG_ON);
1222 } else {
1223 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1224 RX_VLAN_STRIP_OFF);
1225 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1226 TX_VLAN_TAG_OFF);
1227 }
1228 }
1229
1230 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1231 {
1232 struct sky2_port *sky2 = netdev_priv(dev);
1233 struct sky2_hw *hw = sky2->hw;
1234 u16 port = sky2->port;
1235
1236 netif_tx_lock_bh(dev);
1237 napi_disable(&hw->napi);
1238
1239 sky2->vlgrp = grp;
1240 sky2_set_vlan_mode(hw, port, grp != NULL);
1241
1242 sky2_read32(hw, B0_Y2_SP_LISR);
1243 napi_enable(&hw->napi);
1244 netif_tx_unlock_bh(dev);
1245 }
1246 #endif
1247
1248 /*
1249 * Allocate an skb for receiving. If the MTU is large enough
1250 * make the skb non-linear with a fragment list of pages.
1251 */
1252 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1253 {
1254 struct sk_buff *skb;
1255 int i;
1256
1257 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1258 unsigned char *start;
1259 /*
1260 * Workaround for a bug in FIFO that cause hang
1261 * if the FIFO if the receive buffer is not 64 byte aligned.
1262 * The buffer returned from netdev_alloc_skb is
1263 * aligned except if slab debugging is enabled.
1264 */
1265 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1266 if (!skb)
1267 goto nomem;
1268 start = PTR_ALIGN(skb->data, 8);
1269 skb_reserve(skb, start - skb->data);
1270 } else {
1271 skb = netdev_alloc_skb(sky2->netdev,
1272 sky2->rx_data_size + NET_IP_ALIGN);
1273 if (!skb)
1274 goto nomem;
1275 skb_reserve(skb, NET_IP_ALIGN);
1276 }
1277
1278 for (i = 0; i < sky2->rx_nfrags; i++) {
1279 struct page *page = alloc_page(GFP_ATOMIC);
1280
1281 if (!page)
1282 goto free_partial;
1283 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1284 }
1285
1286 return skb;
1287 free_partial:
1288 kfree_skb(skb);
1289 nomem:
1290 return NULL;
1291 }
1292
1293 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1294 {
1295 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1296 }
1297
1298 /*
1299 * Allocate and setup receiver buffer pool.
1300 * Normal case this ends up creating one list element for skb
1301 * in the receive ring. Worst case if using large MTU and each
1302 * allocation falls on a different 64 bit region, that results
1303 * in 6 list elements per ring entry.
1304 * One element is used for checksum enable/disable, and one
1305 * extra to avoid wrap.
1306 */
1307 static int sky2_rx_start(struct sky2_port *sky2)
1308 {
1309 struct sky2_hw *hw = sky2->hw;
1310 struct rx_ring_info *re;
1311 unsigned rxq = rxqaddr[sky2->port];
1312 unsigned i, size, thresh;
1313
1314 sky2->rx_put = sky2->rx_next = 0;
1315 sky2_qset(hw, rxq);
1316
1317 /* On PCI express lowering the watermark gives better performance */
1318 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1319 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1320
1321 /* These chips have no ram buffer?
1322 * MAC Rx RAM Read is controlled by hardware */
1323 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1324 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1325 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1326 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1327
1328 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1329
1330 if (!(hw->flags & SKY2_HW_NEW_LE))
1331 rx_set_checksum(sky2);
1332
1333 /* Space needed for frame data + headers rounded up */
1334 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1335
1336 /* Stopping point for hardware truncation */
1337 thresh = (size - 8) / sizeof(u32);
1338
1339 sky2->rx_nfrags = size >> PAGE_SHIFT;
1340 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1341
1342 /* Compute residue after pages */
1343 size -= sky2->rx_nfrags << PAGE_SHIFT;
1344
1345 /* Optimize to handle small packets and headers */
1346 if (size < copybreak)
1347 size = copybreak;
1348 if (size < ETH_HLEN)
1349 size = ETH_HLEN;
1350
1351 sky2->rx_data_size = size;
1352
1353 /* Fill Rx ring */
1354 for (i = 0; i < sky2->rx_pending; i++) {
1355 re = sky2->rx_ring + i;
1356
1357 re->skb = sky2_rx_alloc(sky2);
1358 if (!re->skb)
1359 goto nomem;
1360
1361 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1362 dev_kfree_skb(re->skb);
1363 re->skb = NULL;
1364 goto nomem;
1365 }
1366
1367 sky2_rx_submit(sky2, re);
1368 }
1369
1370 /*
1371 * The receiver hangs if it receives frames larger than the
1372 * packet buffer. As a workaround, truncate oversize frames, but
1373 * the register is limited to 9 bits, so if you do frames > 2052
1374 * you better get the MTU right!
1375 */
1376 if (thresh > 0x1ff)
1377 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1378 else {
1379 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1380 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1381 }
1382
1383 /* Tell chip about available buffers */
1384 sky2_rx_update(sky2, rxq);
1385 return 0;
1386 nomem:
1387 sky2_rx_clean(sky2);
1388 return -ENOMEM;
1389 }
1390
1391 /* Bring up network interface. */
1392 static int sky2_up(struct net_device *dev)
1393 {
1394 struct sky2_port *sky2 = netdev_priv(dev);
1395 struct sky2_hw *hw = sky2->hw;
1396 unsigned port = sky2->port;
1397 u32 imask, ramsize;
1398 int cap, err = -ENOMEM;
1399 struct net_device *otherdev = hw->dev[sky2->port^1];
1400
1401 /*
1402 * On dual port PCI-X card, there is an problem where status
1403 * can be received out of order due to split transactions
1404 */
1405 if (otherdev && netif_running(otherdev) &&
1406 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1407 u16 cmd;
1408
1409 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1410 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1411 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1412
1413 }
1414
1415 netif_carrier_off(dev);
1416
1417 /* must be power of 2 */
1418 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1419 TX_RING_SIZE *
1420 sizeof(struct sky2_tx_le),
1421 &sky2->tx_le_map);
1422 if (!sky2->tx_le)
1423 goto err_out;
1424
1425 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1426 GFP_KERNEL);
1427 if (!sky2->tx_ring)
1428 goto err_out;
1429
1430 tx_init(sky2);
1431
1432 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1433 &sky2->rx_le_map);
1434 if (!sky2->rx_le)
1435 goto err_out;
1436 memset(sky2->rx_le, 0, RX_LE_BYTES);
1437
1438 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1439 GFP_KERNEL);
1440 if (!sky2->rx_ring)
1441 goto err_out;
1442
1443 sky2_mac_init(hw, port);
1444
1445 /* Register is number of 4K blocks on internal RAM buffer. */
1446 ramsize = sky2_read8(hw, B2_E_0) * 4;
1447 if (ramsize > 0) {
1448 u32 rxspace;
1449
1450 hw->flags |= SKY2_HW_RAM_BUFFER;
1451 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1452 if (ramsize < 16)
1453 rxspace = ramsize / 2;
1454 else
1455 rxspace = 8 + (2*(ramsize - 16))/3;
1456
1457 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1458 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1459
1460 /* Make sure SyncQ is disabled */
1461 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1462 RB_RST_SET);
1463 }
1464
1465 sky2_qset(hw, txqaddr[port]);
1466
1467 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1468 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1469 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1470
1471 /* Set almost empty threshold */
1472 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1473 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1474 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1475
1476 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1477 TX_RING_SIZE - 1);
1478
1479 #ifdef SKY2_VLAN_TAG_USED
1480 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1481 #endif
1482
1483 err = sky2_rx_start(sky2);
1484 if (err)
1485 goto err_out;
1486
1487 /* Enable interrupts from phy/mac for port */
1488 imask = sky2_read32(hw, B0_IMSK);
1489 imask |= portirq_msk[port];
1490 sky2_write32(hw, B0_IMSK, imask);
1491
1492 sky2_set_multicast(dev);
1493
1494 if (netif_msg_ifup(sky2))
1495 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1496 return 0;
1497
1498 err_out:
1499 if (sky2->rx_le) {
1500 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1501 sky2->rx_le, sky2->rx_le_map);
1502 sky2->rx_le = NULL;
1503 }
1504 if (sky2->tx_le) {
1505 pci_free_consistent(hw->pdev,
1506 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1507 sky2->tx_le, sky2->tx_le_map);
1508 sky2->tx_le = NULL;
1509 }
1510 kfree(sky2->tx_ring);
1511 kfree(sky2->rx_ring);
1512
1513 sky2->tx_ring = NULL;
1514 sky2->rx_ring = NULL;
1515 return err;
1516 }
1517
1518 /* Modular subtraction in ring */
1519 static inline int tx_dist(unsigned tail, unsigned head)
1520 {
1521 return (head - tail) & (TX_RING_SIZE - 1);
1522 }
1523
1524 /* Number of list elements available for next tx */
1525 static inline int tx_avail(const struct sky2_port *sky2)
1526 {
1527 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1528 }
1529
1530 /* Estimate of number of transmit list elements required */
1531 static unsigned tx_le_req(const struct sk_buff *skb)
1532 {
1533 unsigned count;
1534
1535 count = sizeof(dma_addr_t) / sizeof(u32);
1536 count += skb_shinfo(skb)->nr_frags * count;
1537
1538 if (skb_is_gso(skb))
1539 ++count;
1540
1541 if (skb->ip_summed == CHECKSUM_PARTIAL)
1542 ++count;
1543
1544 return count;
1545 }
1546
1547 /*
1548 * Put one packet in ring for transmit.
1549 * A single packet can generate multiple list elements, and
1550 * the number of ring elements will probably be less than the number
1551 * of list elements used.
1552 */
1553 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1554 {
1555 struct sky2_port *sky2 = netdev_priv(dev);
1556 struct sky2_hw *hw = sky2->hw;
1557 struct sky2_tx_le *le = NULL;
1558 struct tx_ring_info *re;
1559 unsigned i, len, first_slot;
1560 dma_addr_t mapping;
1561 u16 mss;
1562 u8 ctrl;
1563
1564 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1565 return NETDEV_TX_BUSY;
1566
1567 len = skb_headlen(skb);
1568 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1569
1570 if (pci_dma_mapping_error(hw->pdev, mapping))
1571 goto mapping_error;
1572
1573 first_slot = sky2->tx_prod;
1574 if (unlikely(netif_msg_tx_queued(sky2)))
1575 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1576 dev->name, first_slot, skb->len);
1577
1578 /* Send high bits if needed */
1579 if (sizeof(dma_addr_t) > sizeof(u32)) {
1580 le = get_tx_le(sky2);
1581 le->addr = cpu_to_le32(upper_32_bits(mapping));
1582 le->opcode = OP_ADDR64 | HW_OWNER;
1583 }
1584
1585 /* Check for TCP Segmentation Offload */
1586 mss = skb_shinfo(skb)->gso_size;
1587 if (mss != 0) {
1588
1589 if (!(hw->flags & SKY2_HW_NEW_LE))
1590 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1591
1592 if (mss != sky2->tx_last_mss) {
1593 le = get_tx_le(sky2);
1594 le->addr = cpu_to_le32(mss);
1595
1596 if (hw->flags & SKY2_HW_NEW_LE)
1597 le->opcode = OP_MSS | HW_OWNER;
1598 else
1599 le->opcode = OP_LRGLEN | HW_OWNER;
1600 sky2->tx_last_mss = mss;
1601 }
1602 }
1603
1604 ctrl = 0;
1605 #ifdef SKY2_VLAN_TAG_USED
1606 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1607 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1608 if (!le) {
1609 le = get_tx_le(sky2);
1610 le->addr = 0;
1611 le->opcode = OP_VLAN|HW_OWNER;
1612 } else
1613 le->opcode |= OP_VLAN;
1614 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1615 ctrl |= INS_VLAN;
1616 }
1617 #endif
1618
1619 /* Handle TCP checksum offload */
1620 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1621 /* On Yukon EX (some versions) encoding change. */
1622 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1623 ctrl |= CALSUM; /* auto checksum */
1624 else {
1625 const unsigned offset = skb_transport_offset(skb);
1626 u32 tcpsum;
1627
1628 tcpsum = offset << 16; /* sum start */
1629 tcpsum |= offset + skb->csum_offset; /* sum write */
1630
1631 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1632 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1633 ctrl |= UDPTCP;
1634
1635 if (tcpsum != sky2->tx_tcpsum) {
1636 sky2->tx_tcpsum = tcpsum;
1637
1638 le = get_tx_le(sky2);
1639 le->addr = cpu_to_le32(tcpsum);
1640 le->length = 0; /* initial checksum value */
1641 le->ctrl = 1; /* one packet */
1642 le->opcode = OP_TCPLISW | HW_OWNER;
1643 }
1644 }
1645 }
1646
1647 le = get_tx_le(sky2);
1648 le->addr = cpu_to_le32((u32) mapping);
1649 le->length = cpu_to_le16(len);
1650 le->ctrl = ctrl;
1651 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1652
1653 re = tx_le_re(sky2, le);
1654 re->skb = skb;
1655 pci_unmap_addr_set(re, mapaddr, mapping);
1656 pci_unmap_len_set(re, maplen, len);
1657
1658 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1659 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1660
1661 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1662 frag->size, PCI_DMA_TODEVICE);
1663
1664 if (pci_dma_mapping_error(hw->pdev, mapping))
1665 goto mapping_unwind;
1666
1667 if (sizeof(dma_addr_t) > sizeof(u32)) {
1668 le = get_tx_le(sky2);
1669 le->addr = cpu_to_le32(upper_32_bits(mapping));
1670 le->ctrl = 0;
1671 le->opcode = OP_ADDR64 | HW_OWNER;
1672 }
1673
1674 le = get_tx_le(sky2);
1675 le->addr = cpu_to_le32((u32) mapping);
1676 le->length = cpu_to_le16(frag->size);
1677 le->ctrl = ctrl;
1678 le->opcode = OP_BUFFER | HW_OWNER;
1679
1680 re = tx_le_re(sky2, le);
1681 re->skb = skb;
1682 pci_unmap_addr_set(re, mapaddr, mapping);
1683 pci_unmap_len_set(re, maplen, frag->size);
1684 }
1685
1686 le->ctrl |= EOP;
1687
1688 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1689 netif_stop_queue(dev);
1690
1691 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1692
1693 return NETDEV_TX_OK;
1694
1695 mapping_unwind:
1696 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1697 le = sky2->tx_le + i;
1698 re = sky2->tx_ring + i;
1699
1700 switch(le->opcode & ~HW_OWNER) {
1701 case OP_LARGESEND:
1702 case OP_PACKET:
1703 pci_unmap_single(hw->pdev,
1704 pci_unmap_addr(re, mapaddr),
1705 pci_unmap_len(re, maplen),
1706 PCI_DMA_TODEVICE);
1707 break;
1708 case OP_BUFFER:
1709 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1710 pci_unmap_len(re, maplen),
1711 PCI_DMA_TODEVICE);
1712 break;
1713 }
1714 }
1715
1716 sky2->tx_prod = first_slot;
1717 mapping_error:
1718 if (net_ratelimit())
1719 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1720 dev_kfree_skb(skb);
1721 return NETDEV_TX_OK;
1722 }
1723
1724 /*
1725 * Free ring elements from starting at tx_cons until "done"
1726 *
1727 * NB: the hardware will tell us about partial completion of multi-part
1728 * buffers so make sure not to free skb to early.
1729 */
1730 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1731 {
1732 struct net_device *dev = sky2->netdev;
1733 struct pci_dev *pdev = sky2->hw->pdev;
1734 unsigned idx;
1735
1736 BUG_ON(done >= TX_RING_SIZE);
1737
1738 for (idx = sky2->tx_cons; idx != done;
1739 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1740 struct sky2_tx_le *le = sky2->tx_le + idx;
1741 struct tx_ring_info *re = sky2->tx_ring + idx;
1742
1743 switch(le->opcode & ~HW_OWNER) {
1744 case OP_LARGESEND:
1745 case OP_PACKET:
1746 pci_unmap_single(pdev,
1747 pci_unmap_addr(re, mapaddr),
1748 pci_unmap_len(re, maplen),
1749 PCI_DMA_TODEVICE);
1750 break;
1751 case OP_BUFFER:
1752 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1753 pci_unmap_len(re, maplen),
1754 PCI_DMA_TODEVICE);
1755 break;
1756 }
1757
1758 if (le->ctrl & EOP) {
1759 if (unlikely(netif_msg_tx_done(sky2)))
1760 printk(KERN_DEBUG "%s: tx done %u\n",
1761 dev->name, idx);
1762
1763 dev->stats.tx_packets++;
1764 dev->stats.tx_bytes += re->skb->len;
1765
1766 dev_kfree_skb_any(re->skb);
1767 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1768 }
1769 }
1770
1771 sky2->tx_cons = idx;
1772 smp_mb();
1773
1774 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1775 netif_wake_queue(dev);
1776 }
1777
1778 /* Cleanup all untransmitted buffers, assume transmitter not running */
1779 static void sky2_tx_clean(struct net_device *dev)
1780 {
1781 struct sky2_port *sky2 = netdev_priv(dev);
1782
1783 netif_tx_lock_bh(dev);
1784 sky2_tx_complete(sky2, sky2->tx_prod);
1785 netif_tx_unlock_bh(dev);
1786 }
1787
1788 /* Network shutdown */
1789 static int sky2_down(struct net_device *dev)
1790 {
1791 struct sky2_port *sky2 = netdev_priv(dev);
1792 struct sky2_hw *hw = sky2->hw;
1793 unsigned port = sky2->port;
1794 u16 ctrl;
1795 u32 imask;
1796
1797 /* Never really got started! */
1798 if (!sky2->tx_le)
1799 return 0;
1800
1801 if (netif_msg_ifdown(sky2))
1802 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1803
1804 /* Disable port IRQ */
1805 imask = sky2_read32(hw, B0_IMSK);
1806 imask &= ~portirq_msk[port];
1807 sky2_write32(hw, B0_IMSK, imask);
1808
1809 synchronize_irq(hw->pdev->irq);
1810
1811 sky2_gmac_reset(hw, port);
1812
1813 /* Stop transmitter */
1814 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1815 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1816
1817 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1818 RB_RST_SET | RB_DIS_OP_MD);
1819
1820 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1821 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1822 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1823
1824 /* Make sure no packets are pending */
1825 napi_synchronize(&hw->napi);
1826
1827 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1828
1829 /* Workaround shared GMAC reset */
1830 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1831 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1832 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1833
1834 /* Disable Force Sync bit and Enable Alloc bit */
1835 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1836 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1837
1838 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1839 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1840 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1841
1842 /* Reset the PCI FIFO of the async Tx queue */
1843 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1844 BMU_RST_SET | BMU_FIFO_RST);
1845
1846 /* Reset the Tx prefetch units */
1847 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1848 PREF_UNIT_RST_SET);
1849
1850 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1851
1852 sky2_rx_stop(sky2);
1853
1854 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1855 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1856
1857 sky2_phy_power_down(hw, port);
1858
1859 /* turn off LED's */
1860 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1861
1862 sky2_tx_clean(dev);
1863 sky2_rx_clean(sky2);
1864
1865 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1866 sky2->rx_le, sky2->rx_le_map);
1867 kfree(sky2->rx_ring);
1868
1869 pci_free_consistent(hw->pdev,
1870 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1871 sky2->tx_le, sky2->tx_le_map);
1872 kfree(sky2->tx_ring);
1873
1874 sky2->tx_le = NULL;
1875 sky2->rx_le = NULL;
1876
1877 sky2->rx_ring = NULL;
1878 sky2->tx_ring = NULL;
1879
1880 return 0;
1881 }
1882
1883 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1884 {
1885 if (hw->flags & SKY2_HW_FIBRE_PHY)
1886 return SPEED_1000;
1887
1888 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1889 if (aux & PHY_M_PS_SPEED_100)
1890 return SPEED_100;
1891 else
1892 return SPEED_10;
1893 }
1894
1895 switch (aux & PHY_M_PS_SPEED_MSK) {
1896 case PHY_M_PS_SPEED_1000:
1897 return SPEED_1000;
1898 case PHY_M_PS_SPEED_100:
1899 return SPEED_100;
1900 default:
1901 return SPEED_10;
1902 }
1903 }
1904
1905 static void sky2_link_up(struct sky2_port *sky2)
1906 {
1907 struct sky2_hw *hw = sky2->hw;
1908 unsigned port = sky2->port;
1909 u16 reg;
1910 static const char *fc_name[] = {
1911 [FC_NONE] = "none",
1912 [FC_TX] = "tx",
1913 [FC_RX] = "rx",
1914 [FC_BOTH] = "both",
1915 };
1916
1917 /* enable Rx/Tx */
1918 reg = gma_read16(hw, port, GM_GP_CTRL);
1919 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1920 gma_write16(hw, port, GM_GP_CTRL, reg);
1921
1922 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1923
1924 netif_carrier_on(sky2->netdev);
1925
1926 mod_timer(&hw->watchdog_timer, jiffies + 1);
1927
1928 /* Turn on link LED */
1929 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1930 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1931
1932 if (netif_msg_link(sky2))
1933 printk(KERN_INFO PFX
1934 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1935 sky2->netdev->name, sky2->speed,
1936 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1937 fc_name[sky2->flow_status]);
1938 }
1939
1940 static void sky2_link_down(struct sky2_port *sky2)
1941 {
1942 struct sky2_hw *hw = sky2->hw;
1943 unsigned port = sky2->port;
1944 u16 reg;
1945
1946 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1947
1948 reg = gma_read16(hw, port, GM_GP_CTRL);
1949 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1950 gma_write16(hw, port, GM_GP_CTRL, reg);
1951
1952 netif_carrier_off(sky2->netdev);
1953
1954 /* Turn on link LED */
1955 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1956
1957 if (netif_msg_link(sky2))
1958 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1959
1960 sky2_phy_init(hw, port);
1961 }
1962
1963 static enum flow_control sky2_flow(int rx, int tx)
1964 {
1965 if (rx)
1966 return tx ? FC_BOTH : FC_RX;
1967 else
1968 return tx ? FC_TX : FC_NONE;
1969 }
1970
1971 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1972 {
1973 struct sky2_hw *hw = sky2->hw;
1974 unsigned port = sky2->port;
1975 u16 advert, lpa;
1976
1977 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1978 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1979 if (lpa & PHY_M_AN_RF) {
1980 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1981 return -1;
1982 }
1983
1984 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1985 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1986 sky2->netdev->name);
1987 return -1;
1988 }
1989
1990 sky2->speed = sky2_phy_speed(hw, aux);
1991 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1992
1993 /* Since the pause result bits seem to in different positions on
1994 * different chips. look at registers.
1995 */
1996 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1997 /* Shift for bits in fiber PHY */
1998 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1999 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2000
2001 if (advert & ADVERTISE_1000XPAUSE)
2002 advert |= ADVERTISE_PAUSE_CAP;
2003 if (advert & ADVERTISE_1000XPSE_ASYM)
2004 advert |= ADVERTISE_PAUSE_ASYM;
2005 if (lpa & LPA_1000XPAUSE)
2006 lpa |= LPA_PAUSE_CAP;
2007 if (lpa & LPA_1000XPAUSE_ASYM)
2008 lpa |= LPA_PAUSE_ASYM;
2009 }
2010
2011 sky2->flow_status = FC_NONE;
2012 if (advert & ADVERTISE_PAUSE_CAP) {
2013 if (lpa & LPA_PAUSE_CAP)
2014 sky2->flow_status = FC_BOTH;
2015 else if (advert & ADVERTISE_PAUSE_ASYM)
2016 sky2->flow_status = FC_RX;
2017 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2018 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2019 sky2->flow_status = FC_TX;
2020 }
2021
2022 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2023 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2024 sky2->flow_status = FC_NONE;
2025
2026 if (sky2->flow_status & FC_TX)
2027 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2028 else
2029 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2030
2031 return 0;
2032 }
2033
2034 /* Interrupt from PHY */
2035 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2036 {
2037 struct net_device *dev = hw->dev[port];
2038 struct sky2_port *sky2 = netdev_priv(dev);
2039 u16 istatus, phystat;
2040
2041 if (!netif_running(dev))
2042 return;
2043
2044 spin_lock(&sky2->phy_lock);
2045 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2046 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2047
2048 if (netif_msg_intr(sky2))
2049 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2050 sky2->netdev->name, istatus, phystat);
2051
2052 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2053 if (sky2_autoneg_done(sky2, phystat) == 0)
2054 sky2_link_up(sky2);
2055 goto out;
2056 }
2057
2058 if (istatus & PHY_M_IS_LSP_CHANGE)
2059 sky2->speed = sky2_phy_speed(hw, phystat);
2060
2061 if (istatus & PHY_M_IS_DUP_CHANGE)
2062 sky2->duplex =
2063 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2064
2065 if (istatus & PHY_M_IS_LST_CHANGE) {
2066 if (phystat & PHY_M_PS_LINK_UP)
2067 sky2_link_up(sky2);
2068 else
2069 sky2_link_down(sky2);
2070 }
2071 out:
2072 spin_unlock(&sky2->phy_lock);
2073 }
2074
2075 /* Transmit timeout is only called if we are running, carrier is up
2076 * and tx queue is full (stopped).
2077 */
2078 static void sky2_tx_timeout(struct net_device *dev)
2079 {
2080 struct sky2_port *sky2 = netdev_priv(dev);
2081 struct sky2_hw *hw = sky2->hw;
2082
2083 if (netif_msg_timer(sky2))
2084 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2085
2086 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2087 dev->name, sky2->tx_cons, sky2->tx_prod,
2088 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2089 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2090
2091 /* can't restart safely under softirq */
2092 schedule_work(&hw->restart_work);
2093 }
2094
2095 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2096 {
2097 struct sky2_port *sky2 = netdev_priv(dev);
2098 struct sky2_hw *hw = sky2->hw;
2099 unsigned port = sky2->port;
2100 int err;
2101 u16 ctl, mode;
2102 u32 imask;
2103
2104 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2105 return -EINVAL;
2106
2107 if (new_mtu > ETH_DATA_LEN &&
2108 (hw->chip_id == CHIP_ID_YUKON_FE ||
2109 hw->chip_id == CHIP_ID_YUKON_FE_P))
2110 return -EINVAL;
2111
2112 if (!netif_running(dev)) {
2113 dev->mtu = new_mtu;
2114 return 0;
2115 }
2116
2117 imask = sky2_read32(hw, B0_IMSK);
2118 sky2_write32(hw, B0_IMSK, 0);
2119
2120 dev->trans_start = jiffies; /* prevent tx timeout */
2121 netif_stop_queue(dev);
2122 napi_disable(&hw->napi);
2123
2124 synchronize_irq(hw->pdev->irq);
2125
2126 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2127 sky2_set_tx_stfwd(hw, port);
2128
2129 ctl = gma_read16(hw, port, GM_GP_CTRL);
2130 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2131 sky2_rx_stop(sky2);
2132 sky2_rx_clean(sky2);
2133
2134 dev->mtu = new_mtu;
2135
2136 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2137 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2138
2139 if (dev->mtu > ETH_DATA_LEN)
2140 mode |= GM_SMOD_JUMBO_ENA;
2141
2142 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2143
2144 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2145
2146 err = sky2_rx_start(sky2);
2147 sky2_write32(hw, B0_IMSK, imask);
2148
2149 sky2_read32(hw, B0_Y2_SP_LISR);
2150 napi_enable(&hw->napi);
2151
2152 if (err)
2153 dev_close(dev);
2154 else {
2155 gma_write16(hw, port, GM_GP_CTRL, ctl);
2156
2157 netif_wake_queue(dev);
2158 }
2159
2160 return err;
2161 }
2162
2163 /* For small just reuse existing skb for next receive */
2164 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2165 const struct rx_ring_info *re,
2166 unsigned length)
2167 {
2168 struct sk_buff *skb;
2169
2170 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2171 if (likely(skb)) {
2172 skb_reserve(skb, 2);
2173 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2174 length, PCI_DMA_FROMDEVICE);
2175 skb_copy_from_linear_data(re->skb, skb->data, length);
2176 skb->ip_summed = re->skb->ip_summed;
2177 skb->csum = re->skb->csum;
2178 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2179 length, PCI_DMA_FROMDEVICE);
2180 re->skb->ip_summed = CHECKSUM_NONE;
2181 skb_put(skb, length);
2182 }
2183 return skb;
2184 }
2185
2186 /* Adjust length of skb with fragments to match received data */
2187 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2188 unsigned int length)
2189 {
2190 int i, num_frags;
2191 unsigned int size;
2192
2193 /* put header into skb */
2194 size = min(length, hdr_space);
2195 skb->tail += size;
2196 skb->len += size;
2197 length -= size;
2198
2199 num_frags = skb_shinfo(skb)->nr_frags;
2200 for (i = 0; i < num_frags; i++) {
2201 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2202
2203 if (length == 0) {
2204 /* don't need this page */
2205 __free_page(frag->page);
2206 --skb_shinfo(skb)->nr_frags;
2207 } else {
2208 size = min(length, (unsigned) PAGE_SIZE);
2209
2210 frag->size = size;
2211 skb->data_len += size;
2212 skb->truesize += size;
2213 skb->len += size;
2214 length -= size;
2215 }
2216 }
2217 }
2218
2219 /* Normal packet - take skb from ring element and put in a new one */
2220 static struct sk_buff *receive_new(struct sky2_port *sky2,
2221 struct rx_ring_info *re,
2222 unsigned int length)
2223 {
2224 struct sk_buff *skb, *nskb;
2225 unsigned hdr_space = sky2->rx_data_size;
2226
2227 /* Don't be tricky about reusing pages (yet) */
2228 nskb = sky2_rx_alloc(sky2);
2229 if (unlikely(!nskb))
2230 return NULL;
2231
2232 skb = re->skb;
2233 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2234
2235 prefetch(skb->data);
2236 re->skb = nskb;
2237 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2238 dev_kfree_skb(nskb);
2239 re->skb = skb;
2240 return NULL;
2241 }
2242
2243 if (skb_shinfo(skb)->nr_frags)
2244 skb_put_frags(skb, hdr_space, length);
2245 else
2246 skb_put(skb, length);
2247 return skb;
2248 }
2249
2250 /*
2251 * Receive one packet.
2252 * For larger packets, get new buffer.
2253 */
2254 static struct sk_buff *sky2_receive(struct net_device *dev,
2255 u16 length, u32 status)
2256 {
2257 struct sky2_port *sky2 = netdev_priv(dev);
2258 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2259 struct sk_buff *skb = NULL;
2260 u16 count = (status & GMR_FS_LEN) >> 16;
2261
2262 #ifdef SKY2_VLAN_TAG_USED
2263 /* Account for vlan tag */
2264 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2265 count -= VLAN_HLEN;
2266 #endif
2267
2268 if (unlikely(netif_msg_rx_status(sky2)))
2269 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2270 dev->name, sky2->rx_next, status, length);
2271
2272 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2273 prefetch(sky2->rx_ring + sky2->rx_next);
2274
2275 /* This chip has hardware problems that generates bogus status.
2276 * So do only marginal checking and expect higher level protocols
2277 * to handle crap frames.
2278 */
2279 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2280 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2281 length != count)
2282 goto okay;
2283
2284 if (status & GMR_FS_ANY_ERR)
2285 goto error;
2286
2287 if (!(status & GMR_FS_RX_OK))
2288 goto resubmit;
2289
2290 /* if length reported by DMA does not match PHY, packet was truncated */
2291 if (length != count)
2292 goto len_error;
2293
2294 okay:
2295 if (length < copybreak)
2296 skb = receive_copy(sky2, re, length);
2297 else
2298 skb = receive_new(sky2, re, length);
2299 resubmit:
2300 sky2_rx_submit(sky2, re);
2301
2302 return skb;
2303
2304 len_error:
2305 /* Truncation of overlength packets
2306 causes PHY length to not match MAC length */
2307 ++dev->stats.rx_length_errors;
2308 if (netif_msg_rx_err(sky2) && net_ratelimit())
2309 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2310 dev->name, status, length);
2311 goto resubmit;
2312
2313 error:
2314 ++dev->stats.rx_errors;
2315 if (status & GMR_FS_RX_FF_OV) {
2316 dev->stats.rx_over_errors++;
2317 goto resubmit;
2318 }
2319
2320 if (netif_msg_rx_err(sky2) && net_ratelimit())
2321 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2322 dev->name, status, length);
2323
2324 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2325 dev->stats.rx_length_errors++;
2326 if (status & GMR_FS_FRAGMENT)
2327 dev->stats.rx_frame_errors++;
2328 if (status & GMR_FS_CRC_ERR)
2329 dev->stats.rx_crc_errors++;
2330
2331 goto resubmit;
2332 }
2333
2334 /* Transmit complete */
2335 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2336 {
2337 struct sky2_port *sky2 = netdev_priv(dev);
2338
2339 if (netif_running(dev)) {
2340 netif_tx_lock(dev);
2341 sky2_tx_complete(sky2, last);
2342 netif_tx_unlock(dev);
2343 }
2344 }
2345
2346 /* Process status response ring */
2347 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2348 {
2349 int work_done = 0;
2350 unsigned rx[2] = { 0, 0 };
2351
2352 rmb();
2353 do {
2354 struct sky2_port *sky2;
2355 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2356 unsigned port;
2357 struct net_device *dev;
2358 struct sk_buff *skb;
2359 u32 status;
2360 u16 length;
2361 u8 opcode = le->opcode;
2362
2363 if (!(opcode & HW_OWNER))
2364 break;
2365
2366 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2367
2368 port = le->css & CSS_LINK_BIT;
2369 dev = hw->dev[port];
2370 sky2 = netdev_priv(dev);
2371 length = le16_to_cpu(le->length);
2372 status = le32_to_cpu(le->status);
2373
2374 le->opcode = 0;
2375 switch (opcode & ~HW_OWNER) {
2376 case OP_RXSTAT:
2377 ++rx[port];
2378 skb = sky2_receive(dev, length, status);
2379 if (unlikely(!skb)) {
2380 dev->stats.rx_dropped++;
2381 break;
2382 }
2383
2384 /* This chip reports checksum status differently */
2385 if (hw->flags & SKY2_HW_NEW_LE) {
2386 if (sky2->rx_csum &&
2387 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2388 (le->css & CSS_TCPUDPCSOK))
2389 skb->ip_summed = CHECKSUM_UNNECESSARY;
2390 else
2391 skb->ip_summed = CHECKSUM_NONE;
2392 }
2393
2394 skb->protocol = eth_type_trans(skb, dev);
2395 dev->stats.rx_packets++;
2396 dev->stats.rx_bytes += skb->len;
2397 dev->last_rx = jiffies;
2398
2399 #ifdef SKY2_VLAN_TAG_USED
2400 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2401 vlan_hwaccel_receive_skb(skb,
2402 sky2->vlgrp,
2403 be16_to_cpu(sky2->rx_tag));
2404 } else
2405 #endif
2406 netif_receive_skb(skb);
2407
2408 /* Stop after net poll weight */
2409 if (++work_done >= to_do)
2410 goto exit_loop;
2411 break;
2412
2413 #ifdef SKY2_VLAN_TAG_USED
2414 case OP_RXVLAN:
2415 sky2->rx_tag = length;
2416 break;
2417
2418 case OP_RXCHKSVLAN:
2419 sky2->rx_tag = length;
2420 /* fall through */
2421 #endif
2422 case OP_RXCHKS:
2423 if (!sky2->rx_csum)
2424 break;
2425
2426 /* If this happens then driver assuming wrong format */
2427 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2428 if (net_ratelimit())
2429 printk(KERN_NOTICE "%s: unexpected"
2430 " checksum status\n",
2431 dev->name);
2432 break;
2433 }
2434
2435 /* Both checksum counters are programmed to start at
2436 * the same offset, so unless there is a problem they
2437 * should match. This failure is an early indication that
2438 * hardware receive checksumming won't work.
2439 */
2440 if (likely(status >> 16 == (status & 0xffff))) {
2441 skb = sky2->rx_ring[sky2->rx_next].skb;
2442 skb->ip_summed = CHECKSUM_COMPLETE;
2443 skb->csum = status & 0xffff;
2444 } else {
2445 printk(KERN_NOTICE PFX "%s: hardware receive "
2446 "checksum problem (status = %#x)\n",
2447 dev->name, status);
2448 sky2->rx_csum = 0;
2449 sky2_write32(sky2->hw,
2450 Q_ADDR(rxqaddr[port], Q_CSR),
2451 BMU_DIS_RX_CHKSUM);
2452 }
2453 break;
2454
2455 case OP_TXINDEXLE:
2456 /* TX index reports status for both ports */
2457 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2458 sky2_tx_done(hw->dev[0], status & 0xfff);
2459 if (hw->dev[1])
2460 sky2_tx_done(hw->dev[1],
2461 ((status >> 24) & 0xff)
2462 | (u16)(length & 0xf) << 8);
2463 break;
2464
2465 default:
2466 if (net_ratelimit())
2467 printk(KERN_WARNING PFX
2468 "unknown status opcode 0x%x\n", opcode);
2469 }
2470 } while (hw->st_idx != idx);
2471
2472 /* Fully processed status ring so clear irq */
2473 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2474
2475 exit_loop:
2476 if (rx[0])
2477 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2478
2479 if (rx[1])
2480 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2481
2482 return work_done;
2483 }
2484
2485 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2486 {
2487 struct net_device *dev = hw->dev[port];
2488
2489 if (net_ratelimit())
2490 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2491 dev->name, status);
2492
2493 if (status & Y2_IS_PAR_RD1) {
2494 if (net_ratelimit())
2495 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2496 dev->name);
2497 /* Clear IRQ */
2498 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2499 }
2500
2501 if (status & Y2_IS_PAR_WR1) {
2502 if (net_ratelimit())
2503 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2504 dev->name);
2505
2506 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2507 }
2508
2509 if (status & Y2_IS_PAR_MAC1) {
2510 if (net_ratelimit())
2511 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2512 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2513 }
2514
2515 if (status & Y2_IS_PAR_RX1) {
2516 if (net_ratelimit())
2517 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2518 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2519 }
2520
2521 if (status & Y2_IS_TCP_TXA1) {
2522 if (net_ratelimit())
2523 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2524 dev->name);
2525 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2526 }
2527 }
2528
2529 static void sky2_hw_intr(struct sky2_hw *hw)
2530 {
2531 struct pci_dev *pdev = hw->pdev;
2532 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2533 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2534
2535 status &= hwmsk;
2536
2537 if (status & Y2_IS_TIST_OV)
2538 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2539
2540 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2541 u16 pci_err;
2542
2543 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2544 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2545 if (net_ratelimit())
2546 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2547 pci_err);
2548
2549 sky2_pci_write16(hw, PCI_STATUS,
2550 pci_err | PCI_STATUS_ERROR_BITS);
2551 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2552 }
2553
2554 if (status & Y2_IS_PCI_EXP) {
2555 /* PCI-Express uncorrectable Error occurred */
2556 u32 err;
2557
2558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2559 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2560 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2561 0xfffffffful);
2562 if (net_ratelimit())
2563 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2564
2565 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2566 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2567 }
2568
2569 if (status & Y2_HWE_L1_MASK)
2570 sky2_hw_error(hw, 0, status);
2571 status >>= 8;
2572 if (status & Y2_HWE_L1_MASK)
2573 sky2_hw_error(hw, 1, status);
2574 }
2575
2576 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2577 {
2578 struct net_device *dev = hw->dev[port];
2579 struct sky2_port *sky2 = netdev_priv(dev);
2580 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2581
2582 if (netif_msg_intr(sky2))
2583 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2584 dev->name, status);
2585
2586 if (status & GM_IS_RX_CO_OV)
2587 gma_read16(hw, port, GM_RX_IRQ_SRC);
2588
2589 if (status & GM_IS_TX_CO_OV)
2590 gma_read16(hw, port, GM_TX_IRQ_SRC);
2591
2592 if (status & GM_IS_RX_FF_OR) {
2593 ++dev->stats.rx_fifo_errors;
2594 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2595 }
2596
2597 if (status & GM_IS_TX_FF_UR) {
2598 ++dev->stats.tx_fifo_errors;
2599 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2600 }
2601 }
2602
2603 /* This should never happen it is a bug. */
2604 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2605 u16 q, unsigned ring_size)
2606 {
2607 struct net_device *dev = hw->dev[port];
2608 struct sky2_port *sky2 = netdev_priv(dev);
2609 unsigned idx;
2610 const u64 *le = (q == Q_R1 || q == Q_R2)
2611 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2612
2613 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2614 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2615 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2616 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2617
2618 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2619 }
2620
2621 static int sky2_rx_hung(struct net_device *dev)
2622 {
2623 struct sky2_port *sky2 = netdev_priv(dev);
2624 struct sky2_hw *hw = sky2->hw;
2625 unsigned port = sky2->port;
2626 unsigned rxq = rxqaddr[port];
2627 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2628 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2629 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2630 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2631
2632 /* If idle and MAC or PCI is stuck */
2633 if (sky2->check.last == dev->last_rx &&
2634 ((mac_rp == sky2->check.mac_rp &&
2635 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2636 /* Check if the PCI RX hang */
2637 (fifo_rp == sky2->check.fifo_rp &&
2638 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2639 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2640 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2641 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2642 return 1;
2643 } else {
2644 sky2->check.last = dev->last_rx;
2645 sky2->check.mac_rp = mac_rp;
2646 sky2->check.mac_lev = mac_lev;
2647 sky2->check.fifo_rp = fifo_rp;
2648 sky2->check.fifo_lev = fifo_lev;
2649 return 0;
2650 }
2651 }
2652
2653 static void sky2_watchdog(unsigned long arg)
2654 {
2655 struct sky2_hw *hw = (struct sky2_hw *) arg;
2656
2657 /* Check for lost IRQ once a second */
2658 if (sky2_read32(hw, B0_ISRC)) {
2659 napi_schedule(&hw->napi);
2660 } else {
2661 int i, active = 0;
2662
2663 for (i = 0; i < hw->ports; i++) {
2664 struct net_device *dev = hw->dev[i];
2665 if (!netif_running(dev))
2666 continue;
2667 ++active;
2668
2669 /* For chips with Rx FIFO, check if stuck */
2670 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2671 sky2_rx_hung(dev)) {
2672 pr_info(PFX "%s: receiver hang detected\n",
2673 dev->name);
2674 schedule_work(&hw->restart_work);
2675 return;
2676 }
2677 }
2678
2679 if (active == 0)
2680 return;
2681 }
2682
2683 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2684 }
2685
2686 /* Hardware/software error handling */
2687 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2688 {
2689 if (net_ratelimit())
2690 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2691
2692 if (status & Y2_IS_HW_ERR)
2693 sky2_hw_intr(hw);
2694
2695 if (status & Y2_IS_IRQ_MAC1)
2696 sky2_mac_intr(hw, 0);
2697
2698 if (status & Y2_IS_IRQ_MAC2)
2699 sky2_mac_intr(hw, 1);
2700
2701 if (status & Y2_IS_CHK_RX1)
2702 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2703
2704 if (status & Y2_IS_CHK_RX2)
2705 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2706
2707 if (status & Y2_IS_CHK_TXA1)
2708 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2709
2710 if (status & Y2_IS_CHK_TXA2)
2711 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2712 }
2713
2714 static int sky2_poll(struct napi_struct *napi, int work_limit)
2715 {
2716 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2717 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2718 int work_done = 0;
2719 u16 idx;
2720
2721 if (unlikely(status & Y2_IS_ERROR))
2722 sky2_err_intr(hw, status);
2723
2724 if (status & Y2_IS_IRQ_PHY1)
2725 sky2_phy_intr(hw, 0);
2726
2727 if (status & Y2_IS_IRQ_PHY2)
2728 sky2_phy_intr(hw, 1);
2729
2730 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2731 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2732
2733 if (work_done >= work_limit)
2734 goto done;
2735 }
2736
2737 napi_complete(napi);
2738 sky2_read32(hw, B0_Y2_SP_LISR);
2739 done:
2740
2741 return work_done;
2742 }
2743
2744 static irqreturn_t sky2_intr(int irq, void *dev_id)
2745 {
2746 struct sky2_hw *hw = dev_id;
2747 u32 status;
2748
2749 /* Reading this mask interrupts as side effect */
2750 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2751 if (status == 0 || status == ~0)
2752 return IRQ_NONE;
2753
2754 prefetch(&hw->st_le[hw->st_idx]);
2755
2756 napi_schedule(&hw->napi);
2757
2758 return IRQ_HANDLED;
2759 }
2760
2761 #ifdef CONFIG_NET_POLL_CONTROLLER
2762 static void sky2_netpoll(struct net_device *dev)
2763 {
2764 struct sky2_port *sky2 = netdev_priv(dev);
2765
2766 napi_schedule(&sky2->hw->napi);
2767 }
2768 #endif
2769
2770 /* Chip internal frequency for clock calculations */
2771 static u32 sky2_mhz(const struct sky2_hw *hw)
2772 {
2773 switch (hw->chip_id) {
2774 case CHIP_ID_YUKON_EC:
2775 case CHIP_ID_YUKON_EC_U:
2776 case CHIP_ID_YUKON_EX:
2777 case CHIP_ID_YUKON_SUPR:
2778 case CHIP_ID_YUKON_UL_2:
2779 return 125;
2780
2781 case CHIP_ID_YUKON_FE:
2782 return 100;
2783
2784 case CHIP_ID_YUKON_FE_P:
2785 return 50;
2786
2787 case CHIP_ID_YUKON_XL:
2788 return 156;
2789
2790 default:
2791 BUG();
2792 }
2793 }
2794
2795 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2796 {
2797 return sky2_mhz(hw) * us;
2798 }
2799
2800 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2801 {
2802 return clk / sky2_mhz(hw);
2803 }
2804
2805
2806 static int __devinit sky2_init(struct sky2_hw *hw)
2807 {
2808 u8 t8;
2809
2810 /* Enable all clocks and check for bad PCI access */
2811 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2812
2813 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2814
2815 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2816 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2817
2818 switch(hw->chip_id) {
2819 case CHIP_ID_YUKON_XL:
2820 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2821 break;
2822
2823 case CHIP_ID_YUKON_EC_U:
2824 hw->flags = SKY2_HW_GIGABIT
2825 | SKY2_HW_NEWER_PHY
2826 | SKY2_HW_ADV_POWER_CTL;
2827 break;
2828
2829 case CHIP_ID_YUKON_EX:
2830 hw->flags = SKY2_HW_GIGABIT
2831 | SKY2_HW_NEWER_PHY
2832 | SKY2_HW_NEW_LE
2833 | SKY2_HW_ADV_POWER_CTL;
2834
2835 /* New transmit checksum */
2836 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2837 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2838 break;
2839
2840 case CHIP_ID_YUKON_EC:
2841 /* This rev is really old, and requires untested workarounds */
2842 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2843 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2844 return -EOPNOTSUPP;
2845 }
2846 hw->flags = SKY2_HW_GIGABIT;
2847 break;
2848
2849 case CHIP_ID_YUKON_FE:
2850 break;
2851
2852 case CHIP_ID_YUKON_FE_P:
2853 hw->flags = SKY2_HW_NEWER_PHY
2854 | SKY2_HW_NEW_LE
2855 | SKY2_HW_AUTO_TX_SUM
2856 | SKY2_HW_ADV_POWER_CTL;
2857 break;
2858
2859 case CHIP_ID_YUKON_SUPR:
2860 hw->flags = SKY2_HW_GIGABIT
2861 | SKY2_HW_NEWER_PHY
2862 | SKY2_HW_NEW_LE
2863 | SKY2_HW_AUTO_TX_SUM
2864 | SKY2_HW_ADV_POWER_CTL;
2865 break;
2866
2867 case CHIP_ID_YUKON_UL_2:
2868 hw->flags = SKY2_HW_GIGABIT
2869 | SKY2_HW_ADV_POWER_CTL;
2870 break;
2871
2872 default:
2873 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2874 hw->chip_id);
2875 return -EOPNOTSUPP;
2876 }
2877
2878 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2879 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2880 hw->flags |= SKY2_HW_FIBRE_PHY;
2881
2882 hw->ports = 1;
2883 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2884 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2885 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2886 ++hw->ports;
2887 }
2888
2889 return 0;
2890 }
2891
2892 static void sky2_reset(struct sky2_hw *hw)
2893 {
2894 struct pci_dev *pdev = hw->pdev;
2895 u16 status;
2896 int i, cap;
2897 u32 hwe_mask = Y2_HWE_ALL_MASK;
2898
2899 /* disable ASF */
2900 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2901 status = sky2_read16(hw, HCU_CCSR);
2902 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2903 HCU_CCSR_UC_STATE_MSK);
2904 sky2_write16(hw, HCU_CCSR, status);
2905 } else
2906 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2907 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2908
2909 /* do a SW reset */
2910 sky2_write8(hw, B0_CTST, CS_RST_SET);
2911 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2912
2913 /* allow writes to PCI config */
2914 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2915
2916 /* clear PCI errors, if any */
2917 status = sky2_pci_read16(hw, PCI_STATUS);
2918 status |= PCI_STATUS_ERROR_BITS;
2919 sky2_pci_write16(hw, PCI_STATUS, status);
2920
2921 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2922
2923 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2924 if (cap) {
2925 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2926 0xfffffffful);
2927
2928 /* If error bit is stuck on ignore it */
2929 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2930 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2931 else
2932 hwe_mask |= Y2_IS_PCI_EXP;
2933 }
2934
2935 sky2_power_on(hw);
2936 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2937
2938 for (i = 0; i < hw->ports; i++) {
2939 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2940 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2941
2942 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2943 hw->chip_id == CHIP_ID_YUKON_SUPR)
2944 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2945 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2946 | GMC_BYP_RETR_ON);
2947 }
2948
2949 /* Clear I2C IRQ noise */
2950 sky2_write32(hw, B2_I2C_IRQ, 1);
2951
2952 /* turn off hardware timer (unused) */
2953 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2954 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2955
2956 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2957
2958 /* Turn off descriptor polling */
2959 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2960
2961 /* Turn off receive timestamp */
2962 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2963 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2964
2965 /* enable the Tx Arbiters */
2966 for (i = 0; i < hw->ports; i++)
2967 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2968
2969 /* Initialize ram interface */
2970 for (i = 0; i < hw->ports; i++) {
2971 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2972
2973 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2974 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2975 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2976 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2977 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2978 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2979 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2980 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2981 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2982 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2983 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2984 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2985 }
2986
2987 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2988
2989 for (i = 0; i < hw->ports; i++)
2990 sky2_gmac_reset(hw, i);
2991
2992 memset(hw->st_le, 0, STATUS_LE_BYTES);
2993 hw->st_idx = 0;
2994
2995 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2996 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2997
2998 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2999 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3000
3001 /* Set the list last index */
3002 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3003
3004 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3005 sky2_write8(hw, STAT_FIFO_WM, 16);
3006
3007 /* set Status-FIFO ISR watermark */
3008 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3009 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3010 else
3011 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3012
3013 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3014 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3015 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3016
3017 /* enable status unit */
3018 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3019
3020 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3021 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3022 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3023 }
3024
3025 static void sky2_restart(struct work_struct *work)
3026 {
3027 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3028 struct net_device *dev;
3029 int i, err;
3030
3031 rtnl_lock();
3032 for (i = 0; i < hw->ports; i++) {
3033 dev = hw->dev[i];
3034 if (netif_running(dev))
3035 sky2_down(dev);
3036 }
3037
3038 napi_disable(&hw->napi);
3039 sky2_write32(hw, B0_IMSK, 0);
3040 sky2_reset(hw);
3041 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3042 napi_enable(&hw->napi);
3043
3044 for (i = 0; i < hw->ports; i++) {
3045 dev = hw->dev[i];
3046 if (netif_running(dev)) {
3047 err = sky2_up(dev);
3048 if (err) {
3049 printk(KERN_INFO PFX "%s: could not restart %d\n",
3050 dev->name, err);
3051 dev_close(dev);
3052 }
3053 }
3054 }
3055
3056 rtnl_unlock();
3057 }
3058
3059 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3060 {
3061 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3062 }
3063
3064 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3065 {
3066 const struct sky2_port *sky2 = netdev_priv(dev);
3067
3068 wol->supported = sky2_wol_supported(sky2->hw);
3069 wol->wolopts = sky2->wol;
3070 }
3071
3072 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3073 {
3074 struct sky2_port *sky2 = netdev_priv(dev);
3075 struct sky2_hw *hw = sky2->hw;
3076
3077 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3078 || !device_can_wakeup(&hw->pdev->dev))
3079 return -EOPNOTSUPP;
3080
3081 sky2->wol = wol->wolopts;
3082
3083 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3084 hw->chip_id == CHIP_ID_YUKON_EX ||
3085 hw->chip_id == CHIP_ID_YUKON_FE_P)
3086 sky2_write32(hw, B0_CTST, sky2->wol
3087 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3088
3089 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3090
3091 if (!netif_running(dev))
3092 sky2_wol_init(sky2);
3093 return 0;
3094 }
3095
3096 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3097 {
3098 if (sky2_is_copper(hw)) {
3099 u32 modes = SUPPORTED_10baseT_Half
3100 | SUPPORTED_10baseT_Full
3101 | SUPPORTED_100baseT_Half
3102 | SUPPORTED_100baseT_Full
3103 | SUPPORTED_Autoneg | SUPPORTED_TP;
3104
3105 if (hw->flags & SKY2_HW_GIGABIT)
3106 modes |= SUPPORTED_1000baseT_Half
3107 | SUPPORTED_1000baseT_Full;
3108 return modes;
3109 } else
3110 return SUPPORTED_1000baseT_Half
3111 | SUPPORTED_1000baseT_Full
3112 | SUPPORTED_Autoneg
3113 | SUPPORTED_FIBRE;
3114 }
3115
3116 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3117 {
3118 struct sky2_port *sky2 = netdev_priv(dev);
3119 struct sky2_hw *hw = sky2->hw;
3120
3121 ecmd->transceiver = XCVR_INTERNAL;
3122 ecmd->supported = sky2_supported_modes(hw);
3123 ecmd->phy_address = PHY_ADDR_MARV;
3124 if (sky2_is_copper(hw)) {
3125 ecmd->port = PORT_TP;
3126 ecmd->speed = sky2->speed;
3127 } else {
3128 ecmd->speed = SPEED_1000;
3129 ecmd->port = PORT_FIBRE;
3130 }
3131
3132 ecmd->advertising = sky2->advertising;
3133 ecmd->autoneg = sky2->autoneg;
3134 ecmd->duplex = sky2->duplex;
3135 return 0;
3136 }
3137
3138 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3139 {
3140 struct sky2_port *sky2 = netdev_priv(dev);
3141 const struct sky2_hw *hw = sky2->hw;
3142 u32 supported = sky2_supported_modes(hw);
3143
3144 if (ecmd->autoneg == AUTONEG_ENABLE) {
3145 ecmd->advertising = supported;
3146 sky2->duplex = -1;
3147 sky2->speed = -1;
3148 } else {
3149 u32 setting;
3150
3151 switch (ecmd->speed) {
3152 case SPEED_1000:
3153 if (ecmd->duplex == DUPLEX_FULL)
3154 setting = SUPPORTED_1000baseT_Full;
3155 else if (ecmd->duplex == DUPLEX_HALF)
3156 setting = SUPPORTED_1000baseT_Half;
3157 else
3158 return -EINVAL;
3159 break;
3160 case SPEED_100:
3161 if (ecmd->duplex == DUPLEX_FULL)
3162 setting = SUPPORTED_100baseT_Full;
3163 else if (ecmd->duplex == DUPLEX_HALF)
3164 setting = SUPPORTED_100baseT_Half;
3165 else
3166 return -EINVAL;
3167 break;
3168
3169 case SPEED_10:
3170 if (ecmd->duplex == DUPLEX_FULL)
3171 setting = SUPPORTED_10baseT_Full;
3172 else if (ecmd->duplex == DUPLEX_HALF)
3173 setting = SUPPORTED_10baseT_Half;
3174 else
3175 return -EINVAL;
3176 break;
3177 default:
3178 return -EINVAL;
3179 }
3180
3181 if ((setting & supported) == 0)
3182 return -EINVAL;
3183
3184 sky2->speed = ecmd->speed;
3185 sky2->duplex = ecmd->duplex;
3186 }
3187
3188 sky2->autoneg = ecmd->autoneg;
3189 sky2->advertising = ecmd->advertising;
3190
3191 if (netif_running(dev)) {
3192 sky2_phy_reinit(sky2);
3193 sky2_set_multicast(dev);
3194 }
3195
3196 return 0;
3197 }
3198
3199 static void sky2_get_drvinfo(struct net_device *dev,
3200 struct ethtool_drvinfo *info)
3201 {
3202 struct sky2_port *sky2 = netdev_priv(dev);
3203
3204 strcpy(info->driver, DRV_NAME);
3205 strcpy(info->version, DRV_VERSION);
3206 strcpy(info->fw_version, "N/A");
3207 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3208 }
3209
3210 static const struct sky2_stat {
3211 char name[ETH_GSTRING_LEN];
3212 u16 offset;
3213 } sky2_stats[] = {
3214 { "tx_bytes", GM_TXO_OK_HI },
3215 { "rx_bytes", GM_RXO_OK_HI },
3216 { "tx_broadcast", GM_TXF_BC_OK },
3217 { "rx_broadcast", GM_RXF_BC_OK },
3218 { "tx_multicast", GM_TXF_MC_OK },
3219 { "rx_multicast", GM_RXF_MC_OK },
3220 { "tx_unicast", GM_TXF_UC_OK },
3221 { "rx_unicast", GM_RXF_UC_OK },
3222 { "tx_mac_pause", GM_TXF_MPAUSE },
3223 { "rx_mac_pause", GM_RXF_MPAUSE },
3224 { "collisions", GM_TXF_COL },
3225 { "late_collision",GM_TXF_LAT_COL },
3226 { "aborted", GM_TXF_ABO_COL },
3227 { "single_collisions", GM_TXF_SNG_COL },
3228 { "multi_collisions", GM_TXF_MUL_COL },
3229
3230 { "rx_short", GM_RXF_SHT },
3231 { "rx_runt", GM_RXE_FRAG },
3232 { "rx_64_byte_packets", GM_RXF_64B },
3233 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3234 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3235 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3236 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3237 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3238 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3239 { "rx_too_long", GM_RXF_LNG_ERR },
3240 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3241 { "rx_jabber", GM_RXF_JAB_PKT },
3242 { "rx_fcs_error", GM_RXF_FCS_ERR },
3243
3244 { "tx_64_byte_packets", GM_TXF_64B },
3245 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3246 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3247 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3248 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3249 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3250 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3251 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3252 };
3253
3254 static u32 sky2_get_rx_csum(struct net_device *dev)
3255 {
3256 struct sky2_port *sky2 = netdev_priv(dev);
3257
3258 return sky2->rx_csum;
3259 }
3260
3261 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3262 {
3263 struct sky2_port *sky2 = netdev_priv(dev);
3264
3265 sky2->rx_csum = data;
3266
3267 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3268 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3269
3270 return 0;
3271 }
3272
3273 static u32 sky2_get_msglevel(struct net_device *netdev)
3274 {
3275 struct sky2_port *sky2 = netdev_priv(netdev);
3276 return sky2->msg_enable;
3277 }
3278
3279 static int sky2_nway_reset(struct net_device *dev)
3280 {
3281 struct sky2_port *sky2 = netdev_priv(dev);
3282
3283 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3284 return -EINVAL;
3285
3286 sky2_phy_reinit(sky2);
3287 sky2_set_multicast(dev);
3288
3289 return 0;
3290 }
3291
3292 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3293 {
3294 struct sky2_hw *hw = sky2->hw;
3295 unsigned port = sky2->port;
3296 int i;
3297
3298 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3299 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3300 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3301 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3302
3303 for (i = 2; i < count; i++)
3304 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3305 }
3306
3307 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3308 {
3309 struct sky2_port *sky2 = netdev_priv(netdev);
3310 sky2->msg_enable = value;
3311 }
3312
3313 static int sky2_get_sset_count(struct net_device *dev, int sset)
3314 {
3315 switch (sset) {
3316 case ETH_SS_STATS:
3317 return ARRAY_SIZE(sky2_stats);
3318 default:
3319 return -EOPNOTSUPP;
3320 }
3321 }
3322
3323 static void sky2_get_ethtool_stats(struct net_device *dev,
3324 struct ethtool_stats *stats, u64 * data)
3325 {
3326 struct sky2_port *sky2 = netdev_priv(dev);
3327
3328 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3329 }
3330
3331 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3332 {
3333 int i;
3334
3335 switch (stringset) {
3336 case ETH_SS_STATS:
3337 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3338 memcpy(data + i * ETH_GSTRING_LEN,
3339 sky2_stats[i].name, ETH_GSTRING_LEN);
3340 break;
3341 }
3342 }
3343
3344 static int sky2_set_mac_address(struct net_device *dev, void *p)
3345 {
3346 struct sky2_port *sky2 = netdev_priv(dev);
3347 struct sky2_hw *hw = sky2->hw;
3348 unsigned port = sky2->port;
3349 const struct sockaddr *addr = p;
3350
3351 if (!is_valid_ether_addr(addr->sa_data))
3352 return -EADDRNOTAVAIL;
3353
3354 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3355 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3356 dev->dev_addr, ETH_ALEN);
3357 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3358 dev->dev_addr, ETH_ALEN);
3359
3360 /* virtual address for data */
3361 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3362
3363 /* physical address: used for pause frames */
3364 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3365
3366 return 0;
3367 }
3368
3369 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3370 {
3371 u32 bit;
3372
3373 bit = ether_crc(ETH_ALEN, addr) & 63;
3374 filter[bit >> 3] |= 1 << (bit & 7);
3375 }
3376
3377 static void sky2_set_multicast(struct net_device *dev)
3378 {
3379 struct sky2_port *sky2 = netdev_priv(dev);
3380 struct sky2_hw *hw = sky2->hw;
3381 unsigned port = sky2->port;
3382 struct dev_mc_list *list = dev->mc_list;
3383 u16 reg;
3384 u8 filter[8];
3385 int rx_pause;
3386 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3387
3388 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3389 memset(filter, 0, sizeof(filter));
3390
3391 reg = gma_read16(hw, port, GM_RX_CTRL);
3392 reg |= GM_RXCR_UCF_ENA;
3393
3394 if (dev->flags & IFF_PROMISC) /* promiscuous */
3395 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3396 else if (dev->flags & IFF_ALLMULTI)
3397 memset(filter, 0xff, sizeof(filter));
3398 else if (dev->mc_count == 0 && !rx_pause)
3399 reg &= ~GM_RXCR_MCF_ENA;
3400 else {
3401 int i;
3402 reg |= GM_RXCR_MCF_ENA;
3403
3404 if (rx_pause)
3405 sky2_add_filter(filter, pause_mc_addr);
3406
3407 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3408 sky2_add_filter(filter, list->dmi_addr);
3409 }
3410
3411 gma_write16(hw, port, GM_MC_ADDR_H1,
3412 (u16) filter[0] | ((u16) filter[1] << 8));
3413 gma_write16(hw, port, GM_MC_ADDR_H2,
3414 (u16) filter[2] | ((u16) filter[3] << 8));
3415 gma_write16(hw, port, GM_MC_ADDR_H3,
3416 (u16) filter[4] | ((u16) filter[5] << 8));
3417 gma_write16(hw, port, GM_MC_ADDR_H4,
3418 (u16) filter[6] | ((u16) filter[7] << 8));
3419
3420 gma_write16(hw, port, GM_RX_CTRL, reg);
3421 }
3422
3423 /* Can have one global because blinking is controlled by
3424 * ethtool and that is always under RTNL mutex
3425 */
3426 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3427 {
3428 struct sky2_hw *hw = sky2->hw;
3429 unsigned port = sky2->port;
3430
3431 spin_lock_bh(&sky2->phy_lock);
3432 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3433 hw->chip_id == CHIP_ID_YUKON_EX ||
3434 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3435 u16 pg;
3436 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3437 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3438
3439 switch (mode) {
3440 case MO_LED_OFF:
3441 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3442 PHY_M_LEDC_LOS_CTRL(8) |
3443 PHY_M_LEDC_INIT_CTRL(8) |
3444 PHY_M_LEDC_STA1_CTRL(8) |
3445 PHY_M_LEDC_STA0_CTRL(8));
3446 break;
3447 case MO_LED_ON:
3448 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3449 PHY_M_LEDC_LOS_CTRL(9) |
3450 PHY_M_LEDC_INIT_CTRL(9) |
3451 PHY_M_LEDC_STA1_CTRL(9) |
3452 PHY_M_LEDC_STA0_CTRL(9));
3453 break;
3454 case MO_LED_BLINK:
3455 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3456 PHY_M_LEDC_LOS_CTRL(0xa) |
3457 PHY_M_LEDC_INIT_CTRL(0xa) |
3458 PHY_M_LEDC_STA1_CTRL(0xa) |
3459 PHY_M_LEDC_STA0_CTRL(0xa));
3460 break;
3461 case MO_LED_NORM:
3462 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3463 PHY_M_LEDC_LOS_CTRL(1) |
3464 PHY_M_LEDC_INIT_CTRL(8) |
3465 PHY_M_LEDC_STA1_CTRL(7) |
3466 PHY_M_LEDC_STA0_CTRL(7));
3467 }
3468
3469 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3470 } else
3471 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3472 PHY_M_LED_MO_DUP(mode) |
3473 PHY_M_LED_MO_10(mode) |
3474 PHY_M_LED_MO_100(mode) |
3475 PHY_M_LED_MO_1000(mode) |
3476 PHY_M_LED_MO_RX(mode) |
3477 PHY_M_LED_MO_TX(mode));
3478
3479 spin_unlock_bh(&sky2->phy_lock);
3480 }
3481
3482 /* blink LED's for finding board */
3483 static int sky2_phys_id(struct net_device *dev, u32 data)
3484 {
3485 struct sky2_port *sky2 = netdev_priv(dev);
3486 unsigned int i;
3487
3488 if (data == 0)
3489 data = UINT_MAX;
3490
3491 for (i = 0; i < data; i++) {
3492 sky2_led(sky2, MO_LED_ON);
3493 if (msleep_interruptible(500))
3494 break;
3495 sky2_led(sky2, MO_LED_OFF);
3496 if (msleep_interruptible(500))
3497 break;
3498 }
3499 sky2_led(sky2, MO_LED_NORM);
3500
3501 return 0;
3502 }
3503
3504 static void sky2_get_pauseparam(struct net_device *dev,
3505 struct ethtool_pauseparam *ecmd)
3506 {
3507 struct sky2_port *sky2 = netdev_priv(dev);
3508
3509 switch (sky2->flow_mode) {
3510 case FC_NONE:
3511 ecmd->tx_pause = ecmd->rx_pause = 0;
3512 break;
3513 case FC_TX:
3514 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3515 break;
3516 case FC_RX:
3517 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3518 break;
3519 case FC_BOTH:
3520 ecmd->tx_pause = ecmd->rx_pause = 1;
3521 }
3522
3523 ecmd->autoneg = sky2->autoneg;
3524 }
3525
3526 static int sky2_set_pauseparam(struct net_device *dev,
3527 struct ethtool_pauseparam *ecmd)
3528 {
3529 struct sky2_port *sky2 = netdev_priv(dev);
3530
3531 sky2->autoneg = ecmd->autoneg;
3532 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3533
3534 if (netif_running(dev))
3535 sky2_phy_reinit(sky2);
3536
3537 return 0;
3538 }
3539
3540 static int sky2_get_coalesce(struct net_device *dev,
3541 struct ethtool_coalesce *ecmd)
3542 {
3543 struct sky2_port *sky2 = netdev_priv(dev);
3544 struct sky2_hw *hw = sky2->hw;
3545
3546 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3547 ecmd->tx_coalesce_usecs = 0;
3548 else {
3549 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3550 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3551 }
3552 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3553
3554 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3555 ecmd->rx_coalesce_usecs = 0;
3556 else {
3557 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3558 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3559 }
3560 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3561
3562 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3563 ecmd->rx_coalesce_usecs_irq = 0;
3564 else {
3565 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3566 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3567 }
3568
3569 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3570
3571 return 0;
3572 }
3573
3574 /* Note: this affect both ports */
3575 static int sky2_set_coalesce(struct net_device *dev,
3576 struct ethtool_coalesce *ecmd)
3577 {
3578 struct sky2_port *sky2 = netdev_priv(dev);
3579 struct sky2_hw *hw = sky2->hw;
3580 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3581
3582 if (ecmd->tx_coalesce_usecs > tmax ||
3583 ecmd->rx_coalesce_usecs > tmax ||
3584 ecmd->rx_coalesce_usecs_irq > tmax)
3585 return -EINVAL;
3586
3587 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3588 return -EINVAL;
3589 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3590 return -EINVAL;
3591 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3592 return -EINVAL;
3593
3594 if (ecmd->tx_coalesce_usecs == 0)
3595 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3596 else {
3597 sky2_write32(hw, STAT_TX_TIMER_INI,
3598 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3599 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3600 }
3601 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3602
3603 if (ecmd->rx_coalesce_usecs == 0)
3604 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3605 else {
3606 sky2_write32(hw, STAT_LEV_TIMER_INI,
3607 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3608 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3609 }
3610 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3611
3612 if (ecmd->rx_coalesce_usecs_irq == 0)
3613 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3614 else {
3615 sky2_write32(hw, STAT_ISR_TIMER_INI,
3616 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3617 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3618 }
3619 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3620 return 0;
3621 }
3622
3623 static void sky2_get_ringparam(struct net_device *dev,
3624 struct ethtool_ringparam *ering)
3625 {
3626 struct sky2_port *sky2 = netdev_priv(dev);
3627
3628 ering->rx_max_pending = RX_MAX_PENDING;
3629 ering->rx_mini_max_pending = 0;
3630 ering->rx_jumbo_max_pending = 0;
3631 ering->tx_max_pending = TX_RING_SIZE - 1;
3632
3633 ering->rx_pending = sky2->rx_pending;
3634 ering->rx_mini_pending = 0;
3635 ering->rx_jumbo_pending = 0;
3636 ering->tx_pending = sky2->tx_pending;
3637 }
3638
3639 static int sky2_set_ringparam(struct net_device *dev,
3640 struct ethtool_ringparam *ering)
3641 {
3642 struct sky2_port *sky2 = netdev_priv(dev);
3643 int err = 0;
3644
3645 if (ering->rx_pending > RX_MAX_PENDING ||
3646 ering->rx_pending < 8 ||
3647 ering->tx_pending < MAX_SKB_TX_LE ||
3648 ering->tx_pending > TX_RING_SIZE - 1)
3649 return -EINVAL;
3650
3651 if (netif_running(dev))
3652 sky2_down(dev);
3653
3654 sky2->rx_pending = ering->rx_pending;
3655 sky2->tx_pending = ering->tx_pending;
3656
3657 if (netif_running(dev)) {
3658 err = sky2_up(dev);
3659 if (err)
3660 dev_close(dev);
3661 }
3662
3663 return err;
3664 }
3665
3666 static int sky2_get_regs_len(struct net_device *dev)
3667 {
3668 return 0x4000;
3669 }
3670
3671 /*
3672 * Returns copy of control register region
3673 * Note: ethtool_get_regs always provides full size (16k) buffer
3674 */
3675 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3676 void *p)
3677 {
3678 const struct sky2_port *sky2 = netdev_priv(dev);
3679 const void __iomem *io = sky2->hw->regs;
3680 unsigned int b;
3681
3682 regs->version = 1;
3683
3684 for (b = 0; b < 128; b++) {
3685 /* This complicated switch statement is to make sure and
3686 * only access regions that are unreserved.
3687 * Some blocks are only valid on dual port cards.
3688 * and block 3 has some special diagnostic registers that
3689 * are poison.
3690 */
3691 switch (b) {
3692 case 3:
3693 /* skip diagnostic ram region */
3694 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3695 break;
3696
3697 /* dual port cards only */
3698 case 5: /* Tx Arbiter 2 */
3699 case 9: /* RX2 */
3700 case 14 ... 15: /* TX2 */
3701 case 17: case 19: /* Ram Buffer 2 */
3702 case 22 ... 23: /* Tx Ram Buffer 2 */
3703 case 25: /* Rx MAC Fifo 1 */
3704 case 27: /* Tx MAC Fifo 2 */
3705 case 31: /* GPHY 2 */
3706 case 40 ... 47: /* Pattern Ram 2 */
3707 case 52: case 54: /* TCP Segmentation 2 */
3708 case 112 ... 116: /* GMAC 2 */
3709 if (sky2->hw->ports == 1)
3710 goto reserved;
3711 /* fall through */
3712 case 0: /* Control */
3713 case 2: /* Mac address */
3714 case 4: /* Tx Arbiter 1 */
3715 case 7: /* PCI express reg */
3716 case 8: /* RX1 */
3717 case 12 ... 13: /* TX1 */
3718 case 16: case 18:/* Rx Ram Buffer 1 */
3719 case 20 ... 21: /* Tx Ram Buffer 1 */
3720 case 24: /* Rx MAC Fifo 1 */
3721 case 26: /* Tx MAC Fifo 1 */
3722 case 28 ... 29: /* Descriptor and status unit */
3723 case 30: /* GPHY 1*/
3724 case 32 ... 39: /* Pattern Ram 1 */
3725 case 48: case 50: /* TCP Segmentation 1 */
3726 case 56 ... 60: /* PCI space */
3727 case 80 ... 84: /* GMAC 1 */
3728 memcpy_fromio(p, io, 128);
3729 break;
3730 default:
3731 reserved:
3732 memset(p, 0, 128);
3733 }
3734
3735 p += 128;
3736 io += 128;
3737 }
3738 }
3739
3740 /* In order to do Jumbo packets on these chips, need to turn off the
3741 * transmit store/forward. Therefore checksum offload won't work.
3742 */
3743 static int no_tx_offload(struct net_device *dev)
3744 {
3745 const struct sky2_port *sky2 = netdev_priv(dev);
3746 const struct sky2_hw *hw = sky2->hw;
3747
3748 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3749 }
3750
3751 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3752 {
3753 if (data && no_tx_offload(dev))
3754 return -EINVAL;
3755
3756 return ethtool_op_set_tx_csum(dev, data);
3757 }
3758
3759
3760 static int sky2_set_tso(struct net_device *dev, u32 data)
3761 {
3762 if (data && no_tx_offload(dev))
3763 return -EINVAL;
3764
3765 return ethtool_op_set_tso(dev, data);
3766 }
3767
3768 static int sky2_get_eeprom_len(struct net_device *dev)
3769 {
3770 struct sky2_port *sky2 = netdev_priv(dev);
3771 struct sky2_hw *hw = sky2->hw;
3772 u16 reg2;
3773
3774 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3775 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3776 }
3777
3778 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3779 {
3780 unsigned long start = jiffies;
3781
3782 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3783 /* Can take up to 10.6 ms for write */
3784 if (time_after(jiffies, start + HZ/4)) {
3785 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3786 return -ETIMEDOUT;
3787 }
3788 mdelay(1);
3789 }
3790
3791 return 0;
3792 }
3793
3794 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3795 u16 offset, size_t length)
3796 {
3797 int rc = 0;
3798
3799 while (length > 0) {
3800 u32 val;
3801
3802 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3803 rc = sky2_vpd_wait(hw, cap, 0);
3804 if (rc)
3805 break;
3806
3807 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3808
3809 memcpy(data, &val, min(sizeof(val), length));
3810 offset += sizeof(u32);
3811 data += sizeof(u32);
3812 length -= sizeof(u32);
3813 }
3814
3815 return rc;
3816 }
3817
3818 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3819 u16 offset, unsigned int length)
3820 {
3821 unsigned int i;
3822 int rc = 0;
3823
3824 for (i = 0; i < length; i += sizeof(u32)) {
3825 u32 val = *(u32 *)(data + i);
3826
3827 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3828 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3829
3830 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3831 if (rc)
3832 break;
3833 }
3834 return rc;
3835 }
3836
3837 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3838 u8 *data)
3839 {
3840 struct sky2_port *sky2 = netdev_priv(dev);
3841 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3842
3843 if (!cap)
3844 return -EINVAL;
3845
3846 eeprom->magic = SKY2_EEPROM_MAGIC;
3847
3848 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3849 }
3850
3851 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3852 u8 *data)
3853 {
3854 struct sky2_port *sky2 = netdev_priv(dev);
3855 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3856
3857 if (!cap)
3858 return -EINVAL;
3859
3860 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3861 return -EINVAL;
3862
3863 /* Partial writes not supported */
3864 if ((eeprom->offset & 3) || (eeprom->len & 3))
3865 return -EINVAL;
3866
3867 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3868 }
3869
3870
3871 static const struct ethtool_ops sky2_ethtool_ops = {
3872 .get_settings = sky2_get_settings,
3873 .set_settings = sky2_set_settings,
3874 .get_drvinfo = sky2_get_drvinfo,
3875 .get_wol = sky2_get_wol,
3876 .set_wol = sky2_set_wol,
3877 .get_msglevel = sky2_get_msglevel,
3878 .set_msglevel = sky2_set_msglevel,
3879 .nway_reset = sky2_nway_reset,
3880 .get_regs_len = sky2_get_regs_len,
3881 .get_regs = sky2_get_regs,
3882 .get_link = ethtool_op_get_link,
3883 .get_eeprom_len = sky2_get_eeprom_len,
3884 .get_eeprom = sky2_get_eeprom,
3885 .set_eeprom = sky2_set_eeprom,
3886 .set_sg = ethtool_op_set_sg,
3887 .set_tx_csum = sky2_set_tx_csum,
3888 .set_tso = sky2_set_tso,
3889 .get_rx_csum = sky2_get_rx_csum,
3890 .set_rx_csum = sky2_set_rx_csum,
3891 .get_strings = sky2_get_strings,
3892 .get_coalesce = sky2_get_coalesce,
3893 .set_coalesce = sky2_set_coalesce,
3894 .get_ringparam = sky2_get_ringparam,
3895 .set_ringparam = sky2_set_ringparam,
3896 .get_pauseparam = sky2_get_pauseparam,
3897 .set_pauseparam = sky2_set_pauseparam,
3898 .phys_id = sky2_phys_id,
3899 .get_sset_count = sky2_get_sset_count,
3900 .get_ethtool_stats = sky2_get_ethtool_stats,
3901 };
3902
3903 #ifdef CONFIG_SKY2_DEBUG
3904
3905 static struct dentry *sky2_debug;
3906
3907
3908 /*
3909 * Read and parse the first part of Vital Product Data
3910 */
3911 #define VPD_SIZE 128
3912 #define VPD_MAGIC 0x82
3913
3914 static const struct vpd_tag {
3915 char tag[2];
3916 char *label;
3917 } vpd_tags[] = {
3918 { "PN", "Part Number" },
3919 { "EC", "Engineering Level" },
3920 { "MN", "Manufacturer" },
3921 { "SN", "Serial Number" },
3922 { "YA", "Asset Tag" },
3923 { "VL", "First Error Log Message" },
3924 { "VF", "Second Error Log Message" },
3925 { "VB", "Boot Agent ROM Configuration" },
3926 { "VE", "EFI UNDI Configuration" },
3927 };
3928
3929 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3930 {
3931 size_t vpd_size;
3932 loff_t offs;
3933 u8 len;
3934 unsigned char *buf;
3935 u16 reg2;
3936
3937 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3938 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3939
3940 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3941 buf = kmalloc(vpd_size, GFP_KERNEL);
3942 if (!buf) {
3943 seq_puts(seq, "no memory!\n");
3944 return;
3945 }
3946
3947 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
3948 seq_puts(seq, "VPD read failed\n");
3949 goto out;
3950 }
3951
3952 if (buf[0] != VPD_MAGIC) {
3953 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
3954 goto out;
3955 }
3956 len = buf[1];
3957 if (len == 0 || len > vpd_size - 4) {
3958 seq_printf(seq, "Invalid id length: %d\n", len);
3959 goto out;
3960 }
3961
3962 seq_printf(seq, "%.*s\n", len, buf + 3);
3963 offs = len + 3;
3964
3965 while (offs < vpd_size - 4) {
3966 int i;
3967
3968 if (!memcmp("RW", buf + offs, 2)) /* end marker */
3969 break;
3970 len = buf[offs + 2];
3971 if (offs + len + 3 >= vpd_size)
3972 break;
3973
3974 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
3975 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
3976 seq_printf(seq, " %s: %.*s\n",
3977 vpd_tags[i].label, len, buf + offs + 3);
3978 break;
3979 }
3980 }
3981 offs += len + 3;
3982 }
3983 out:
3984 kfree(buf);
3985 }
3986
3987 static int sky2_debug_show(struct seq_file *seq, void *v)
3988 {
3989 struct net_device *dev = seq->private;
3990 const struct sky2_port *sky2 = netdev_priv(dev);
3991 struct sky2_hw *hw = sky2->hw;
3992 unsigned port = sky2->port;
3993 unsigned idx, last;
3994 int sop;
3995
3996 sky2_show_vpd(seq, hw);
3997
3998 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3999 sky2_read32(hw, B0_ISRC),
4000 sky2_read32(hw, B0_IMSK),
4001 sky2_read32(hw, B0_Y2_SP_ICR));
4002
4003 if (!netif_running(dev)) {
4004 seq_printf(seq, "network not running\n");
4005 return 0;
4006 }
4007
4008 napi_disable(&hw->napi);
4009 last = sky2_read16(hw, STAT_PUT_IDX);
4010
4011 if (hw->st_idx == last)
4012 seq_puts(seq, "Status ring (empty)\n");
4013 else {
4014 seq_puts(seq, "Status ring\n");
4015 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4016 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4017 const struct sky2_status_le *le = hw->st_le + idx;
4018 seq_printf(seq, "[%d] %#x %d %#x\n",
4019 idx, le->opcode, le->length, le->status);
4020 }
4021 seq_puts(seq, "\n");
4022 }
4023
4024 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4025 sky2->tx_cons, sky2->tx_prod,
4026 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4027 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4028
4029 /* Dump contents of tx ring */
4030 sop = 1;
4031 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4032 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4033 const struct sky2_tx_le *le = sky2->tx_le + idx;
4034 u32 a = le32_to_cpu(le->addr);
4035
4036 if (sop)
4037 seq_printf(seq, "%u:", idx);
4038 sop = 0;
4039
4040 switch(le->opcode & ~HW_OWNER) {
4041 case OP_ADDR64:
4042 seq_printf(seq, " %#x:", a);
4043 break;
4044 case OP_LRGLEN:
4045 seq_printf(seq, " mtu=%d", a);
4046 break;
4047 case OP_VLAN:
4048 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4049 break;
4050 case OP_TCPLISW:
4051 seq_printf(seq, " csum=%#x", a);
4052 break;
4053 case OP_LARGESEND:
4054 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4055 break;
4056 case OP_PACKET:
4057 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4058 break;
4059 case OP_BUFFER:
4060 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4061 break;
4062 default:
4063 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4064 a, le16_to_cpu(le->length));
4065 }
4066
4067 if (le->ctrl & EOP) {
4068 seq_putc(seq, '\n');
4069 sop = 1;
4070 }
4071 }
4072
4073 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4074 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4075 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4076 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4077
4078 sky2_read32(hw, B0_Y2_SP_LISR);
4079 napi_enable(&hw->napi);
4080 return 0;
4081 }
4082
4083 static int sky2_debug_open(struct inode *inode, struct file *file)
4084 {
4085 return single_open(file, sky2_debug_show, inode->i_private);
4086 }
4087
4088 static const struct file_operations sky2_debug_fops = {
4089 .owner = THIS_MODULE,
4090 .open = sky2_debug_open,
4091 .read = seq_read,
4092 .llseek = seq_lseek,
4093 .release = single_release,
4094 };
4095
4096 /*
4097 * Use network device events to create/remove/rename
4098 * debugfs file entries
4099 */
4100 static int sky2_device_event(struct notifier_block *unused,
4101 unsigned long event, void *ptr)
4102 {
4103 struct net_device *dev = ptr;
4104 struct sky2_port *sky2 = netdev_priv(dev);
4105
4106 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4107 return NOTIFY_DONE;
4108
4109 switch(event) {
4110 case NETDEV_CHANGENAME:
4111 if (sky2->debugfs) {
4112 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4113 sky2_debug, dev->name);
4114 }
4115 break;
4116
4117 case NETDEV_GOING_DOWN:
4118 if (sky2->debugfs) {
4119 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4120 dev->name);
4121 debugfs_remove(sky2->debugfs);
4122 sky2->debugfs = NULL;
4123 }
4124 break;
4125
4126 case NETDEV_UP:
4127 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4128 sky2_debug, dev,
4129 &sky2_debug_fops);
4130 if (IS_ERR(sky2->debugfs))
4131 sky2->debugfs = NULL;
4132 }
4133
4134 return NOTIFY_DONE;
4135 }
4136
4137 static struct notifier_block sky2_notifier = {
4138 .notifier_call = sky2_device_event,
4139 };
4140
4141
4142 static __init void sky2_debug_init(void)
4143 {
4144 struct dentry *ent;
4145
4146 ent = debugfs_create_dir("sky2", NULL);
4147 if (!ent || IS_ERR(ent))
4148 return;
4149
4150 sky2_debug = ent;
4151 register_netdevice_notifier(&sky2_notifier);
4152 }
4153
4154 static __exit void sky2_debug_cleanup(void)
4155 {
4156 if (sky2_debug) {
4157 unregister_netdevice_notifier(&sky2_notifier);
4158 debugfs_remove(sky2_debug);
4159 sky2_debug = NULL;
4160 }
4161 }
4162
4163 #else
4164 #define sky2_debug_init()
4165 #define sky2_debug_cleanup()
4166 #endif
4167
4168 /* Two copies of network device operations to handle special case of
4169 not allowing netpoll on second port */
4170 static const struct net_device_ops sky2_netdev_ops[2] = {
4171 {
4172 .ndo_open = sky2_up,
4173 .ndo_stop = sky2_down,
4174 .ndo_start_xmit = sky2_xmit_frame,
4175 .ndo_do_ioctl = sky2_ioctl,
4176 .ndo_validate_addr = eth_validate_addr,
4177 .ndo_set_mac_address = sky2_set_mac_address,
4178 .ndo_set_multicast_list = sky2_set_multicast,
4179 .ndo_change_mtu = sky2_change_mtu,
4180 .ndo_tx_timeout = sky2_tx_timeout,
4181 #ifdef SKY2_VLAN_TAG_USED
4182 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4183 #endif
4184 #ifdef CONFIG_NET_POLL_CONTROLLER
4185 .ndo_poll_controller = sky2_netpoll,
4186 #endif
4187 },
4188 {
4189 .ndo_open = sky2_up,
4190 .ndo_stop = sky2_down,
4191 .ndo_start_xmit = sky2_xmit_frame,
4192 .ndo_do_ioctl = sky2_ioctl,
4193 .ndo_validate_addr = eth_validate_addr,
4194 .ndo_set_mac_address = sky2_set_mac_address,
4195 .ndo_set_multicast_list = sky2_set_multicast,
4196 .ndo_change_mtu = sky2_change_mtu,
4197 .ndo_tx_timeout = sky2_tx_timeout,
4198 #ifdef SKY2_VLAN_TAG_USED
4199 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4200 #endif
4201 },
4202 };
4203
4204 /* Initialize network device */
4205 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4206 unsigned port,
4207 int highmem, int wol)
4208 {
4209 struct sky2_port *sky2;
4210 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4211
4212 if (!dev) {
4213 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4214 return NULL;
4215 }
4216
4217 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4218 dev->irq = hw->pdev->irq;
4219 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4220 dev->watchdog_timeo = TX_WATCHDOG;
4221 dev->netdev_ops = &sky2_netdev_ops[port];
4222
4223 sky2 = netdev_priv(dev);
4224 sky2->netdev = dev;
4225 sky2->hw = hw;
4226 sky2->msg_enable = netif_msg_init(debug, default_msg);
4227
4228 /* Auto speed and flow control */
4229 sky2->autoneg = AUTONEG_ENABLE;
4230 sky2->flow_mode = FC_BOTH;
4231
4232 sky2->duplex = -1;
4233 sky2->speed = -1;
4234 sky2->advertising = sky2_supported_modes(hw);
4235 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4236 sky2->wol = wol;
4237
4238 spin_lock_init(&sky2->phy_lock);
4239 sky2->tx_pending = TX_DEF_PENDING;
4240 sky2->rx_pending = RX_DEF_PENDING;
4241
4242 hw->dev[port] = dev;
4243
4244 sky2->port = port;
4245
4246 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4247 if (highmem)
4248 dev->features |= NETIF_F_HIGHDMA;
4249
4250 #ifdef SKY2_VLAN_TAG_USED
4251 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4252 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4253 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4254 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4255 }
4256 #endif
4257
4258 /* read the mac address */
4259 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4260 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4261
4262 return dev;
4263 }
4264
4265 static void __devinit sky2_show_addr(struct net_device *dev)
4266 {
4267 const struct sky2_port *sky2 = netdev_priv(dev);
4268
4269 if (netif_msg_probe(sky2))
4270 printk(KERN_INFO PFX "%s: addr %pM\n",
4271 dev->name, dev->dev_addr);
4272 }
4273
4274 /* Handle software interrupt used during MSI test */
4275 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4276 {
4277 struct sky2_hw *hw = dev_id;
4278 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4279
4280 if (status == 0)
4281 return IRQ_NONE;
4282
4283 if (status & Y2_IS_IRQ_SW) {
4284 hw->flags |= SKY2_HW_USE_MSI;
4285 wake_up(&hw->msi_wait);
4286 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4287 }
4288 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4289
4290 return IRQ_HANDLED;
4291 }
4292
4293 /* Test interrupt path by forcing a a software IRQ */
4294 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4295 {
4296 struct pci_dev *pdev = hw->pdev;
4297 int err;
4298
4299 init_waitqueue_head (&hw->msi_wait);
4300
4301 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4302
4303 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4304 if (err) {
4305 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4306 return err;
4307 }
4308
4309 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4310 sky2_read8(hw, B0_CTST);
4311
4312 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4313
4314 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4315 /* MSI test failed, go back to INTx mode */
4316 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4317 "switching to INTx mode.\n");
4318
4319 err = -EOPNOTSUPP;
4320 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4321 }
4322
4323 sky2_write32(hw, B0_IMSK, 0);
4324 sky2_read32(hw, B0_IMSK);
4325
4326 free_irq(pdev->irq, hw);
4327
4328 return err;
4329 }
4330
4331 /* This driver supports yukon2 chipset only */
4332 static const char *sky2_name(u8 chipid, char *buf, int sz)
4333 {
4334 const char *name[] = {
4335 "XL", /* 0xb3 */
4336 "EC Ultra", /* 0xb4 */
4337 "Extreme", /* 0xb5 */
4338 "EC", /* 0xb6 */
4339 "FE", /* 0xb7 */
4340 "FE+", /* 0xb8 */
4341 "Supreme", /* 0xb9 */
4342 "UL 2", /* 0xba */
4343 };
4344
4345 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4346 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4347 else
4348 snprintf(buf, sz, "(chip %#x)", chipid);
4349 return buf;
4350 }
4351
4352 static int __devinit sky2_probe(struct pci_dev *pdev,
4353 const struct pci_device_id *ent)
4354 {
4355 struct net_device *dev;
4356 struct sky2_hw *hw;
4357 int err, using_dac = 0, wol_default;
4358 u32 reg;
4359 char buf1[16];
4360
4361 err = pci_enable_device(pdev);
4362 if (err) {
4363 dev_err(&pdev->dev, "cannot enable PCI device\n");
4364 goto err_out;
4365 }
4366
4367 err = pci_request_regions(pdev, DRV_NAME);
4368 if (err) {
4369 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4370 goto err_out_disable;
4371 }
4372
4373 pci_set_master(pdev);
4374
4375 if (sizeof(dma_addr_t) > sizeof(u32) &&
4376 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4377 using_dac = 1;
4378 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4379 if (err < 0) {
4380 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4381 "for consistent allocations\n");
4382 goto err_out_free_regions;
4383 }
4384 } else {
4385 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4386 if (err) {
4387 dev_err(&pdev->dev, "no usable DMA configuration\n");
4388 goto err_out_free_regions;
4389 }
4390 }
4391
4392 /* Get configuration information
4393 * Note: only regular PCI config access once to test for HW issues
4394 * other PCI access through shared memory for speed and to
4395 * avoid MMCONFIG problems.
4396 */
4397 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4398 if (err) {
4399 dev_err(&pdev->dev, "PCI read config failed\n");
4400 goto err_out_free_regions;
4401 }
4402
4403 /* size of available VPD, only impact sysfs */
4404 err = pci_vpd_truncate(pdev, 1ul << (((reg & PCI_VPD_ROM_SZ) >> 14) + 8));
4405 if (err)
4406 dev_warn(&pdev->dev, "Can't set VPD size\n");
4407
4408 #ifdef __BIG_ENDIAN
4409 /* The sk98lin vendor driver uses hardware byte swapping but
4410 * this driver uses software swapping.
4411 */
4412 reg &= ~PCI_REV_DESC;
4413 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4414 if (err) {
4415 dev_err(&pdev->dev, "PCI write config failed\n");
4416 goto err_out_free_regions;
4417 }
4418 #endif
4419
4420 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4421
4422 err = -ENOMEM;
4423 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4424 if (!hw) {
4425 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4426 goto err_out_free_regions;
4427 }
4428
4429 hw->pdev = pdev;
4430
4431 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4432 if (!hw->regs) {
4433 dev_err(&pdev->dev, "cannot map device registers\n");
4434 goto err_out_free_hw;
4435 }
4436
4437 /* ring for status responses */
4438 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4439 if (!hw->st_le)
4440 goto err_out_iounmap;
4441
4442 err = sky2_init(hw);
4443 if (err)
4444 goto err_out_iounmap;
4445
4446 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4447 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4448
4449 sky2_reset(hw);
4450
4451 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4452 if (!dev) {
4453 err = -ENOMEM;
4454 goto err_out_free_pci;
4455 }
4456
4457 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4458 err = sky2_test_msi(hw);
4459 if (err == -EOPNOTSUPP)
4460 pci_disable_msi(pdev);
4461 else if (err)
4462 goto err_out_free_netdev;
4463 }
4464
4465 err = register_netdev(dev);
4466 if (err) {
4467 dev_err(&pdev->dev, "cannot register net device\n");
4468 goto err_out_free_netdev;
4469 }
4470
4471 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4472
4473 err = request_irq(pdev->irq, sky2_intr,
4474 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4475 dev->name, hw);
4476 if (err) {
4477 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4478 goto err_out_unregister;
4479 }
4480 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4481 napi_enable(&hw->napi);
4482
4483 sky2_show_addr(dev);
4484
4485 if (hw->ports > 1) {
4486 struct net_device *dev1;
4487
4488 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4489 if (!dev1)
4490 dev_warn(&pdev->dev, "allocation for second device failed\n");
4491 else if ((err = register_netdev(dev1))) {
4492 dev_warn(&pdev->dev,
4493 "register of second port failed (%d)\n", err);
4494 hw->dev[1] = NULL;
4495 free_netdev(dev1);
4496 } else
4497 sky2_show_addr(dev1);
4498 }
4499
4500 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4501 INIT_WORK(&hw->restart_work, sky2_restart);
4502
4503 pci_set_drvdata(pdev, hw);
4504
4505 return 0;
4506
4507 err_out_unregister:
4508 if (hw->flags & SKY2_HW_USE_MSI)
4509 pci_disable_msi(pdev);
4510 unregister_netdev(dev);
4511 err_out_free_netdev:
4512 free_netdev(dev);
4513 err_out_free_pci:
4514 sky2_write8(hw, B0_CTST, CS_RST_SET);
4515 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4516 err_out_iounmap:
4517 iounmap(hw->regs);
4518 err_out_free_hw:
4519 kfree(hw);
4520 err_out_free_regions:
4521 pci_release_regions(pdev);
4522 err_out_disable:
4523 pci_disable_device(pdev);
4524 err_out:
4525 pci_set_drvdata(pdev, NULL);
4526 return err;
4527 }
4528
4529 static void __devexit sky2_remove(struct pci_dev *pdev)
4530 {
4531 struct sky2_hw *hw = pci_get_drvdata(pdev);
4532 int i;
4533
4534 if (!hw)
4535 return;
4536
4537 del_timer_sync(&hw->watchdog_timer);
4538 cancel_work_sync(&hw->restart_work);
4539
4540 for (i = hw->ports-1; i >= 0; --i)
4541 unregister_netdev(hw->dev[i]);
4542
4543 sky2_write32(hw, B0_IMSK, 0);
4544
4545 sky2_power_aux(hw);
4546
4547 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4548 sky2_write8(hw, B0_CTST, CS_RST_SET);
4549 sky2_read8(hw, B0_CTST);
4550
4551 free_irq(pdev->irq, hw);
4552 if (hw->flags & SKY2_HW_USE_MSI)
4553 pci_disable_msi(pdev);
4554 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4555 pci_release_regions(pdev);
4556 pci_disable_device(pdev);
4557
4558 for (i = hw->ports-1; i >= 0; --i)
4559 free_netdev(hw->dev[i]);
4560
4561 iounmap(hw->regs);
4562 kfree(hw);
4563
4564 pci_set_drvdata(pdev, NULL);
4565 }
4566
4567 #ifdef CONFIG_PM
4568 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4569 {
4570 struct sky2_hw *hw = pci_get_drvdata(pdev);
4571 int i, wol = 0;
4572
4573 if (!hw)
4574 return 0;
4575
4576 del_timer_sync(&hw->watchdog_timer);
4577 cancel_work_sync(&hw->restart_work);
4578
4579 for (i = 0; i < hw->ports; i++) {
4580 struct net_device *dev = hw->dev[i];
4581 struct sky2_port *sky2 = netdev_priv(dev);
4582
4583 netif_device_detach(dev);
4584 if (netif_running(dev))
4585 sky2_down(dev);
4586
4587 if (sky2->wol)
4588 sky2_wol_init(sky2);
4589
4590 wol |= sky2->wol;
4591 }
4592
4593 sky2_write32(hw, B0_IMSK, 0);
4594 napi_disable(&hw->napi);
4595 sky2_power_aux(hw);
4596
4597 pci_save_state(pdev);
4598 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4599 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4600
4601 return 0;
4602 }
4603
4604 static int sky2_resume(struct pci_dev *pdev)
4605 {
4606 struct sky2_hw *hw = pci_get_drvdata(pdev);
4607 int i, err;
4608
4609 if (!hw)
4610 return 0;
4611
4612 err = pci_set_power_state(pdev, PCI_D0);
4613 if (err)
4614 goto out;
4615
4616 err = pci_restore_state(pdev);
4617 if (err)
4618 goto out;
4619
4620 pci_enable_wake(pdev, PCI_D0, 0);
4621
4622 /* Re-enable all clocks */
4623 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4624 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4625 hw->chip_id == CHIP_ID_YUKON_FE_P)
4626 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4627
4628 sky2_reset(hw);
4629 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4630 napi_enable(&hw->napi);
4631
4632 for (i = 0; i < hw->ports; i++) {
4633 struct net_device *dev = hw->dev[i];
4634
4635 netif_device_attach(dev);
4636 if (netif_running(dev)) {
4637 err = sky2_up(dev);
4638 if (err) {
4639 printk(KERN_ERR PFX "%s: could not up: %d\n",
4640 dev->name, err);
4641 rtnl_lock();
4642 dev_close(dev);
4643 rtnl_unlock();
4644 goto out;
4645 }
4646 }
4647 }
4648
4649 return 0;
4650 out:
4651 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4652 pci_disable_device(pdev);
4653 return err;
4654 }
4655 #endif
4656
4657 static void sky2_shutdown(struct pci_dev *pdev)
4658 {
4659 struct sky2_hw *hw = pci_get_drvdata(pdev);
4660 int i, wol = 0;
4661
4662 if (!hw)
4663 return;
4664
4665 del_timer_sync(&hw->watchdog_timer);
4666
4667 for (i = 0; i < hw->ports; i++) {
4668 struct net_device *dev = hw->dev[i];
4669 struct sky2_port *sky2 = netdev_priv(dev);
4670
4671 if (sky2->wol) {
4672 wol = 1;
4673 sky2_wol_init(sky2);
4674 }
4675 }
4676
4677 if (wol)
4678 sky2_power_aux(hw);
4679
4680 pci_enable_wake(pdev, PCI_D3hot, wol);
4681 pci_enable_wake(pdev, PCI_D3cold, wol);
4682
4683 pci_disable_device(pdev);
4684 pci_set_power_state(pdev, PCI_D3hot);
4685 }
4686
4687 static struct pci_driver sky2_driver = {
4688 .name = DRV_NAME,
4689 .id_table = sky2_id_table,
4690 .probe = sky2_probe,
4691 .remove = __devexit_p(sky2_remove),
4692 #ifdef CONFIG_PM
4693 .suspend = sky2_suspend,
4694 .resume = sky2_resume,
4695 #endif
4696 .shutdown = sky2_shutdown,
4697 };
4698
4699 static int __init sky2_init_module(void)
4700 {
4701 pr_info(PFX "driver version " DRV_VERSION "\n");
4702
4703 sky2_debug_init();
4704 return pci_register_driver(&sky2_driver);
4705 }
4706
4707 static void __exit sky2_cleanup_module(void)
4708 {
4709 pci_unregister_driver(&sky2_driver);
4710 sky2_debug_cleanup();
4711 }
4712
4713 module_init(sky2_init_module);
4714 module_exit(sky2_cleanup_module);
4715
4716 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4717 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4718 MODULE_LICENSE("GPL");
4719 MODULE_VERSION(DRV_VERSION);
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