2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.14"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66 #define RX_SKB_ALIGN 8
67 #define RX_BUF_WRITE 16
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82 static const u32 default_msg
=
83 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
84 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
87 static int debug
= -1; /* defaults above */
88 module_param(debug
, int, 0);
89 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
91 static int copybreak __read_mostly
= 128;
92 module_param(copybreak
, int, 0);
93 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
95 static int disable_msi
= 0;
96 module_param(disable_msi
, int, 0);
97 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
99 static int idle_timeout
= 0;
100 module_param(idle_timeout
, int, 0);
101 MODULE_PARM_DESC(idle_timeout
, "Watchdog timer for lost interrupts (ms)");
103 static const struct pci_device_id sky2_id_table
[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
133 // { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
139 /* Avoid conditionals by using array */
140 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
141 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
142 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
144 /* This driver supports yukon2 chipset only */
145 static const char *yukon2_name
[] = {
147 "EC Ultra", /* 0xb4 */
148 "Extreme", /* 0xb5 */
153 /* Access to external PHY */
154 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
158 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
159 gma_write16(hw
, port
, GM_SMI_CTRL
,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
162 for (i
= 0; i
< PHY_RETRIES
; i
++) {
163 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
168 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
172 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
176 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
177 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
179 for (i
= 0; i
< PHY_RETRIES
; i
++) {
180 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
181 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
191 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
195 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
196 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
201 static void sky2_power_on(struct sky2_hw
*hw
)
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw
, B0_POWER_CTRL
,
205 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
207 /* disable Core Clock Division, */
208 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
210 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
211 /* enable bits are inverted */
212 sky2_write8(hw
, B2_Y2_CLK_GATE
,
213 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
214 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
215 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
217 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
219 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
222 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
223 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
224 reg1
&= P_ASPM_CONTROL_MSK
;
225 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
226 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
230 static void sky2_power_aux(struct sky2_hw
*hw
)
232 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
233 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
235 /* enable bits are inverted */
236 sky2_write8(hw
, B2_Y2_CLK_GATE
,
237 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
238 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
239 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
241 /* switch power to VAUX */
242 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
243 sky2_write8(hw
, B0_POWER_CTRL
,
244 (PC_VAUX_ENA
| PC_VCC_ENA
|
245 PC_VAUX_ON
| PC_VCC_OFF
));
248 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
252 /* disable all GMAC IRQ's */
253 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
254 /* disable PHY IRQs */
255 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
257 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
258 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
259 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
260 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
262 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
263 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
264 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
267 /* flow control to advertise bits */
268 static const u16 copper_fc_adv
[] = {
270 [FC_TX
] = PHY_M_AN_ASP
,
271 [FC_RX
] = PHY_M_AN_PC
,
272 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
275 /* flow control to advertise bits when using 1000BaseX */
276 static const u16 fiber_fc_adv
[] = {
277 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
278 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
279 [FC_RX
] = PHY_M_P_SYM_MD_X
,
280 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
283 /* flow control to GMA disable bits */
284 static const u16 gm_fc_disable
[] = {
285 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
286 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
287 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
292 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
294 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
295 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
297 if (sky2
->autoneg
== AUTONEG_ENABLE
298 && !(hw
->chip_id
== CHIP_ID_YUKON_XL
299 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
300 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
301 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
303 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
305 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
307 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
308 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
310 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
312 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
315 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
316 if (sky2_is_copper(hw
)) {
317 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
318 /* enable automatic crossover */
319 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
321 /* disable energy detect */
322 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
324 /* enable automatic crossover */
325 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
327 if (sky2
->autoneg
== AUTONEG_ENABLE
328 && (hw
->chip_id
== CHIP_ID_YUKON_XL
329 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
330 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
331 ctrl
&= ~PHY_M_PC_DSC_MSK
;
332 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
336 /* workaround for deviation #4.88 (CRC errors) */
337 /* disable Automatic Crossover */
339 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
342 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
344 /* special setup for PHY 88E1112 Fiber */
345 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
346 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
348 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
349 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
350 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
351 ctrl
&= ~PHY_M_MAC_MD_MSK
;
352 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
353 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
355 if (hw
->pmd_type
== 'P') {
356 /* select page 1 to access Fiber registers */
357 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
359 /* for SFP-module set SIGDET polarity to low */
360 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
361 ctrl
|= PHY_M_FIB_SIGD_POL
;
362 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
365 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
373 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
374 if (sky2_is_copper(hw
)) {
375 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
376 ct1000
|= PHY_M_1000C_AFD
;
377 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
378 ct1000
|= PHY_M_1000C_AHD
;
379 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
380 adv
|= PHY_M_AN_100_FD
;
381 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
382 adv
|= PHY_M_AN_100_HD
;
383 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
384 adv
|= PHY_M_AN_10_FD
;
385 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
386 adv
|= PHY_M_AN_10_HD
;
388 adv
|= copper_fc_adv
[sky2
->flow_mode
];
389 } else { /* special defines for FIBER (88E1040S only) */
390 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
391 adv
|= PHY_M_AN_1000X_AFD
;
392 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
393 adv
|= PHY_M_AN_1000X_AHD
;
395 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
398 /* Restart Auto-negotiation */
399 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
401 /* forced speed/duplex settings */
402 ct1000
= PHY_M_1000C_MSE
;
404 /* Disable auto update for duplex flow control and speed */
405 reg
|= GM_GPCR_AU_ALL_DIS
;
407 switch (sky2
->speed
) {
409 ctrl
|= PHY_CT_SP1000
;
410 reg
|= GM_GPCR_SPEED_1000
;
413 ctrl
|= PHY_CT_SP100
;
414 reg
|= GM_GPCR_SPEED_100
;
418 if (sky2
->duplex
== DUPLEX_FULL
) {
419 reg
|= GM_GPCR_DUP_FULL
;
420 ctrl
|= PHY_CT_DUP_MD
;
421 } else if (sky2
->speed
< SPEED_1000
)
422 sky2
->flow_mode
= FC_NONE
;
425 reg
|= gm_fc_disable
[sky2
->flow_mode
];
427 /* Forward pause packets to GMAC? */
428 if (sky2
->flow_mode
& FC_RX
)
429 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
431 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
434 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
436 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
437 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
439 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
440 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
442 /* Setup Phy LED's */
443 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
446 switch (hw
->chip_id
) {
447 case CHIP_ID_YUKON_FE
:
448 /* on 88E3082 these bits are at 11..9 (shifted left) */
449 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
451 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
453 /* delete ACT LED control bits */
454 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
455 /* change ACT LED control to blink mode */
456 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
457 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
460 case CHIP_ID_YUKON_XL
:
461 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
463 /* select page 3 to access LED control register */
464 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
466 /* set LED Function Control register */
467 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
468 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
469 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
470 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
471 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
473 /* set Polarity Control register */
474 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
475 (PHY_M_POLC_LS1_P_MIX(4) |
476 PHY_M_POLC_IS0_P_MIX(4) |
477 PHY_M_POLC_LOS_CTRL(2) |
478 PHY_M_POLC_INIT_CTRL(2) |
479 PHY_M_POLC_STA1_CTRL(2) |
480 PHY_M_POLC_STA0_CTRL(2)));
482 /* restore page register */
483 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
486 case CHIP_ID_YUKON_EC_U
:
487 case CHIP_ID_YUKON_EX
:
488 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
490 /* select page 3 to access LED control register */
491 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
493 /* set LED Function Control register */
494 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
495 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
496 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
497 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
498 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
500 /* set Blink Rate in LED Timer Control Register */
501 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
502 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
503 /* restore page register */
504 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
508 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
509 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
510 /* turn off the Rx LED (LED_RX) */
511 ledover
&= ~PHY_M_LED_MO_RX
;
514 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
515 hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
) {
516 /* apply fixes in PHY AFE */
517 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
519 /* increase differential signal amplitude in 10BASE-T */
520 gm_phy_write(hw
, port
, 0x18, 0xaa99);
521 gm_phy_write(hw
, port
, 0x17, 0x2011);
523 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
524 gm_phy_write(hw
, port
, 0x18, 0xa204);
525 gm_phy_write(hw
, port
, 0x17, 0x2002);
527 /* set page register to 0 */
528 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
529 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
530 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
532 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
533 /* turn on 100 Mbps LED (LED_LINK100) */
534 ledover
|= PHY_M_LED_MO_100
;
538 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
542 /* Enable phy interrupt on auto-negotiation complete (or link up) */
543 if (sky2
->autoneg
== AUTONEG_ENABLE
)
544 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
546 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
549 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
552 static const u32 phy_power
[]
553 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
555 /* looks like this XL is back asswards .. */
556 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
559 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
560 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
562 /* Turn off phy power saving */
563 reg1
&= ~phy_power
[port
];
565 reg1
|= phy_power
[port
];
567 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
568 sky2_pci_read32(hw
, PCI_DEV_REG1
);
569 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
573 /* Force a renegotiation */
574 static void sky2_phy_reinit(struct sky2_port
*sky2
)
576 spin_lock_bh(&sky2
->phy_lock
);
577 sky2_phy_init(sky2
->hw
, sky2
->port
);
578 spin_unlock_bh(&sky2
->phy_lock
);
581 /* Put device in state to listen for Wake On Lan */
582 static void sky2_wol_init(struct sky2_port
*sky2
)
584 struct sky2_hw
*hw
= sky2
->hw
;
585 unsigned port
= sky2
->port
;
586 enum flow_control save_mode
;
590 /* Bring hardware out of reset */
591 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
592 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
594 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
595 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
598 * sky2_reset will re-enable on resume
600 save_mode
= sky2
->flow_mode
;
601 ctrl
= sky2
->advertising
;
603 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
604 sky2
->flow_mode
= FC_NONE
;
605 sky2_phy_power(hw
, port
, 1);
606 sky2_phy_reinit(sky2
);
608 sky2
->flow_mode
= save_mode
;
609 sky2
->advertising
= ctrl
;
611 /* Set GMAC to no flow control and auto update for speed/duplex */
612 gma_write16(hw
, port
, GM_GP_CTRL
,
613 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
614 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
616 /* Set WOL address */
617 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
618 sky2
->netdev
->dev_addr
, ETH_ALEN
);
620 /* Turn on appropriate WOL control bits */
621 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
623 if (sky2
->wol
& WAKE_PHY
)
624 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
626 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
628 if (sky2
->wol
& WAKE_MAGIC
)
629 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
631 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
633 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
634 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
636 /* Turn on legacy PCI-Express PME mode */
637 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
638 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
639 reg1
|= PCI_Y2_PME_LEGACY
;
640 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
641 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
644 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
648 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
650 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
653 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
655 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
656 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
658 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
660 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
661 /* WA DEV_472 -- looks like crossed wires on port 2 */
662 /* clear GMAC 1 Control reset */
663 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
665 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
666 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
667 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
668 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
669 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
672 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
674 /* Enable Transmit FIFO Underrun */
675 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
677 spin_lock_bh(&sky2
->phy_lock
);
678 sky2_phy_init(hw
, port
);
679 spin_unlock_bh(&sky2
->phy_lock
);
682 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
683 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
685 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
686 gma_read16(hw
, port
, i
);
687 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
689 /* transmit control */
690 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
692 /* receive control reg: unicast + multicast + no FCS */
693 gma_write16(hw
, port
, GM_RX_CTRL
,
694 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
696 /* transmit flow control */
697 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
699 /* transmit parameter */
700 gma_write16(hw
, port
, GM_TX_PARAM
,
701 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
702 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
703 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
704 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
706 /* serial mode register */
707 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
708 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
710 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
711 reg
|= GM_SMOD_JUMBO_ENA
;
713 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
715 /* virtual address for data */
716 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
718 /* physical address: used for pause frames */
719 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
721 /* ignore counter overflows */
722 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
723 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
724 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
726 /* Configure Rx MAC FIFO */
727 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
728 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
729 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
731 /* Flush Rx MAC FIFO on any flow control or error */
732 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
734 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
735 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
737 /* Configure Tx MAC FIFO */
738 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
739 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
741 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
742 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
743 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
745 /* set Tx GMAC FIFO Almost Empty Threshold */
746 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
747 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
749 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
750 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
751 TX_JUMBO_ENA
| TX_STFW_DIS
);
753 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
754 TX_JUMBO_DIS
| TX_STFW_ENA
);
759 /* Assign Ram Buffer allocation to queue */
760 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
764 /* convert from K bytes to qwords used for hw register */
767 end
= start
+ space
- 1;
769 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
770 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
771 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
772 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
773 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
775 if (q
== Q_R1
|| q
== Q_R2
) {
776 u32 tp
= space
- space
/4;
778 /* On receive queue's set the thresholds
779 * give receiver priority when > 3/4 full
780 * send pause when down to 2K
782 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
783 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
786 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
787 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
789 /* Enable store & forward on Tx queue's because
790 * Tx FIFO is only 1K on Yukon
792 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
795 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
796 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
799 /* Setup Bus Memory Interface */
800 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
802 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
803 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
804 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
805 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
808 /* Setup prefetch unit registers. This is the interface between
809 * hardware and driver list elements
811 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
814 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
815 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
816 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
817 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
818 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
819 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
821 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
824 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
826 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
828 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
833 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
834 struct sky2_tx_le
*le
)
836 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
839 /* Update chip's next pointer */
840 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
842 q
= Y2_QADDR(q
, PREF_UNIT_PUT_IDX
);
844 sky2_write16(hw
, q
, idx
);
849 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
851 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
852 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
857 /* Return high part of DMA address (could be 32 or 64 bit) */
858 static inline u32
high32(dma_addr_t a
)
860 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
863 /* Build description to hardware for one receive segment */
864 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
865 dma_addr_t map
, unsigned len
)
867 struct sky2_rx_le
*le
;
868 u32 hi
= high32(map
);
870 if (sky2
->rx_addr64
!= hi
) {
871 le
= sky2_next_rx(sky2
);
872 le
->addr
= cpu_to_le32(hi
);
873 le
->opcode
= OP_ADDR64
| HW_OWNER
;
874 sky2
->rx_addr64
= high32(map
+ len
);
877 le
= sky2_next_rx(sky2
);
878 le
->addr
= cpu_to_le32((u32
) map
);
879 le
->length
= cpu_to_le16(len
);
880 le
->opcode
= op
| HW_OWNER
;
883 /* Build description to hardware for one possibly fragmented skb */
884 static void sky2_rx_submit(struct sky2_port
*sky2
,
885 const struct rx_ring_info
*re
)
889 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
891 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
892 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
896 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
899 struct sk_buff
*skb
= re
->skb
;
902 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
903 pci_unmap_len_set(re
, data_size
, size
);
905 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
906 re
->frag_addr
[i
] = pci_map_page(pdev
,
907 skb_shinfo(skb
)->frags
[i
].page
,
908 skb_shinfo(skb
)->frags
[i
].page_offset
,
909 skb_shinfo(skb
)->frags
[i
].size
,
913 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
915 struct sk_buff
*skb
= re
->skb
;
918 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
921 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
922 pci_unmap_page(pdev
, re
->frag_addr
[i
],
923 skb_shinfo(skb
)->frags
[i
].size
,
927 /* Tell chip where to start receive checksum.
928 * Actually has two checksums, but set both same to avoid possible byte
931 static void rx_set_checksum(struct sky2_port
*sky2
)
933 struct sky2_rx_le
*le
;
935 le
= sky2_next_rx(sky2
);
936 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
938 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
940 sky2_write32(sky2
->hw
,
941 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
942 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
947 * The RX Stop command will not work for Yukon-2 if the BMU does not
948 * reach the end of packet and since we can't make sure that we have
949 * incoming data, we must reset the BMU while it is not doing a DMA
950 * transfer. Since it is possible that the RX path is still active,
951 * the RX RAM buffer will be stopped first, so any possible incoming
952 * data will not trigger a DMA. After the RAM buffer is stopped, the
953 * BMU is polled until any DMA in progress is ended and only then it
956 static void sky2_rx_stop(struct sky2_port
*sky2
)
958 struct sky2_hw
*hw
= sky2
->hw
;
959 unsigned rxq
= rxqaddr
[sky2
->port
];
962 /* disable the RAM Buffer receive queue */
963 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
965 for (i
= 0; i
< 0xffff; i
++)
966 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
967 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
970 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
973 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
975 /* reset the Rx prefetch unit */
976 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
979 /* Clean out receive buffer area, assumes receiver hardware stopped */
980 static void sky2_rx_clean(struct sky2_port
*sky2
)
984 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
985 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
986 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
989 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
996 /* Basic MII support */
997 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
999 struct mii_ioctl_data
*data
= if_mii(ifr
);
1000 struct sky2_port
*sky2
= netdev_priv(dev
);
1001 struct sky2_hw
*hw
= sky2
->hw
;
1002 int err
= -EOPNOTSUPP
;
1004 if (!netif_running(dev
))
1005 return -ENODEV
; /* Phy still in reset */
1009 data
->phy_id
= PHY_ADDR_MARV
;
1015 spin_lock_bh(&sky2
->phy_lock
);
1016 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1017 spin_unlock_bh(&sky2
->phy_lock
);
1019 data
->val_out
= val
;
1024 if (!capable(CAP_NET_ADMIN
))
1027 spin_lock_bh(&sky2
->phy_lock
);
1028 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1030 spin_unlock_bh(&sky2
->phy_lock
);
1036 #ifdef SKY2_VLAN_TAG_USED
1037 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1039 struct sky2_port
*sky2
= netdev_priv(dev
);
1040 struct sky2_hw
*hw
= sky2
->hw
;
1041 u16 port
= sky2
->port
;
1043 netif_tx_lock_bh(dev
);
1045 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
1046 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
1049 netif_tx_unlock_bh(dev
);
1052 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
1054 struct sky2_port
*sky2
= netdev_priv(dev
);
1055 struct sky2_hw
*hw
= sky2
->hw
;
1056 u16 port
= sky2
->port
;
1058 netif_tx_lock_bh(dev
);
1060 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
1061 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
1062 vlan_group_set_device(sky2
->vlgrp
, vid
, NULL
);
1064 netif_tx_unlock_bh(dev
);
1069 * Allocate an skb for receiving. If the MTU is large enough
1070 * make the skb non-linear with a fragment list of pages.
1072 * It appears the hardware has a bug in the FIFO logic that
1073 * cause it to hang if the FIFO gets overrun and the receive buffer
1074 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1075 * aligned except if slab debugging is enabled.
1077 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1079 struct sk_buff
*skb
;
1083 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1087 p
= (unsigned long) skb
->data
;
1088 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1090 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1091 struct page
*page
= alloc_page(GFP_ATOMIC
);
1095 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1106 * Allocate and setup receiver buffer pool.
1107 * Normal case this ends up creating one list element for skb
1108 * in the receive ring. Worst case if using large MTU and each
1109 * allocation falls on a different 64 bit region, that results
1110 * in 6 list elements per ring entry.
1111 * One element is used for checksum enable/disable, and one
1112 * extra to avoid wrap.
1114 static int sky2_rx_start(struct sky2_port
*sky2
)
1116 struct sky2_hw
*hw
= sky2
->hw
;
1117 struct rx_ring_info
*re
;
1118 unsigned rxq
= rxqaddr
[sky2
->port
];
1119 unsigned i
, size
, space
, thresh
;
1121 sky2
->rx_put
= sky2
->rx_next
= 0;
1124 /* On PCI express lowering the watermark gives better performance */
1125 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1126 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1128 /* These chips have no ram buffer?
1129 * MAC Rx RAM Read is controlled by hardware */
1130 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1131 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1132 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1133 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
1135 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1137 rx_set_checksum(sky2
);
1139 /* Space needed for frame data + headers rounded up */
1140 size
= ALIGN(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8)
1143 /* Stopping point for hardware truncation */
1144 thresh
= (size
- 8) / sizeof(u32
);
1146 /* Account for overhead of skb - to avoid order > 0 allocation */
1147 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1148 + sizeof(struct skb_shared_info
);
1150 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1151 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1153 if (sky2
->rx_nfrags
!= 0) {
1154 /* Compute residue after pages */
1155 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1162 /* Optimize to handle small packets and headers */
1163 if (size
< copybreak
)
1165 if (size
< ETH_HLEN
)
1168 sky2
->rx_data_size
= size
;
1171 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1172 re
= sky2
->rx_ring
+ i
;
1174 re
->skb
= sky2_rx_alloc(sky2
);
1178 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1179 sky2_rx_submit(sky2
, re
);
1183 * The receiver hangs if it receives frames larger than the
1184 * packet buffer. As a workaround, truncate oversize frames, but
1185 * the register is limited to 9 bits, so if you do frames > 2052
1186 * you better get the MTU right!
1189 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1191 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1192 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1195 /* Tell chip about available buffers */
1196 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1199 sky2_rx_clean(sky2
);
1203 /* Bring up network interface. */
1204 static int sky2_up(struct net_device
*dev
)
1206 struct sky2_port
*sky2
= netdev_priv(dev
);
1207 struct sky2_hw
*hw
= sky2
->hw
;
1208 unsigned port
= sky2
->port
;
1210 int cap
, err
= -ENOMEM
;
1211 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1214 * On dual port PCI-X card, there is an problem where status
1215 * can be received out of order due to split transactions
1217 if (otherdev
&& netif_running(otherdev
) &&
1218 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1219 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1222 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1223 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1224 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1230 if (netif_msg_ifup(sky2
))
1231 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1233 /* must be power of 2 */
1234 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1236 sizeof(struct sky2_tx_le
),
1241 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1245 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1247 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1251 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1253 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1258 sky2_phy_power(hw
, port
, 1);
1260 sky2_mac_init(hw
, port
);
1262 /* Register is number of 4K blocks on internal RAM buffer. */
1263 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1264 printk(KERN_INFO PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1270 rxspace
= ramsize
/ 2;
1272 rxspace
= 8 + (2*(ramsize
- 16))/3;
1274 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1275 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1277 /* Make sure SyncQ is disabled */
1278 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1282 sky2_qset(hw
, txqaddr
[port
]);
1284 /* Set almost empty threshold */
1285 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1286 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1287 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1289 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1292 err
= sky2_rx_start(sky2
);
1296 /* Enable interrupts from phy/mac for port */
1297 imask
= sky2_read32(hw
, B0_IMSK
);
1298 imask
|= portirq_msk
[port
];
1299 sky2_write32(hw
, B0_IMSK
, imask
);
1305 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1306 sky2
->rx_le
, sky2
->rx_le_map
);
1310 pci_free_consistent(hw
->pdev
,
1311 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1312 sky2
->tx_le
, sky2
->tx_le_map
);
1315 kfree(sky2
->tx_ring
);
1316 kfree(sky2
->rx_ring
);
1318 sky2
->tx_ring
= NULL
;
1319 sky2
->rx_ring
= NULL
;
1323 /* Modular subtraction in ring */
1324 static inline int tx_dist(unsigned tail
, unsigned head
)
1326 return (head
- tail
) & (TX_RING_SIZE
- 1);
1329 /* Number of list elements available for next tx */
1330 static inline int tx_avail(const struct sky2_port
*sky2
)
1332 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1335 /* Estimate of number of transmit list elements required */
1336 static unsigned tx_le_req(const struct sk_buff
*skb
)
1340 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1341 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1343 if (skb_is_gso(skb
))
1346 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1353 * Put one packet in ring for transmit.
1354 * A single packet can generate multiple list elements, and
1355 * the number of ring elements will probably be less than the number
1356 * of list elements used.
1358 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1360 struct sky2_port
*sky2
= netdev_priv(dev
);
1361 struct sky2_hw
*hw
= sky2
->hw
;
1362 struct sky2_tx_le
*le
= NULL
;
1363 struct tx_ring_info
*re
;
1370 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1371 return NETDEV_TX_BUSY
;
1373 if (unlikely(netif_msg_tx_queued(sky2
)))
1374 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1375 dev
->name
, sky2
->tx_prod
, skb
->len
);
1377 len
= skb_headlen(skb
);
1378 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1379 addr64
= high32(mapping
);
1381 /* Send high bits if changed or crosses boundary */
1382 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1383 le
= get_tx_le(sky2
);
1384 le
->addr
= cpu_to_le32(addr64
);
1385 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1386 sky2
->tx_addr64
= high32(mapping
+ len
);
1389 /* Check for TCP Segmentation Offload */
1390 mss
= skb_shinfo(skb
)->gso_size
;
1392 mss
+= tcp_optlen(skb
); /* TCP options */
1393 mss
+= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
1396 if (mss
!= sky2
->tx_last_mss
) {
1397 le
= get_tx_le(sky2
);
1398 le
->addr
= cpu_to_le32(mss
);
1399 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1400 sky2
->tx_last_mss
= mss
;
1405 #ifdef SKY2_VLAN_TAG_USED
1406 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1407 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1409 le
= get_tx_le(sky2
);
1411 le
->opcode
= OP_VLAN
|HW_OWNER
;
1413 le
->opcode
|= OP_VLAN
;
1414 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1419 /* Handle TCP checksum offload */
1420 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1421 const unsigned offset
= skb_transport_offset(skb
);
1424 tcpsum
= offset
<< 16; /* sum start */
1425 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1427 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1428 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1431 if (tcpsum
!= sky2
->tx_tcpsum
) {
1432 sky2
->tx_tcpsum
= tcpsum
;
1434 le
= get_tx_le(sky2
);
1435 le
->addr
= cpu_to_le32(tcpsum
);
1436 le
->length
= 0; /* initial checksum value */
1437 le
->ctrl
= 1; /* one packet */
1438 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1442 le
= get_tx_le(sky2
);
1443 le
->addr
= cpu_to_le32((u32
) mapping
);
1444 le
->length
= cpu_to_le16(len
);
1446 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1448 re
= tx_le_re(sky2
, le
);
1450 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1451 pci_unmap_len_set(re
, maplen
, len
);
1453 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1454 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1456 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1457 frag
->size
, PCI_DMA_TODEVICE
);
1458 addr64
= high32(mapping
);
1459 if (addr64
!= sky2
->tx_addr64
) {
1460 le
= get_tx_le(sky2
);
1461 le
->addr
= cpu_to_le32(addr64
);
1463 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1464 sky2
->tx_addr64
= addr64
;
1467 le
= get_tx_le(sky2
);
1468 le
->addr
= cpu_to_le32((u32
) mapping
);
1469 le
->length
= cpu_to_le16(frag
->size
);
1471 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1473 re
= tx_le_re(sky2
, le
);
1475 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1476 pci_unmap_len_set(re
, maplen
, frag
->size
);
1481 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1482 netif_stop_queue(dev
);
1484 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1486 dev
->trans_start
= jiffies
;
1487 return NETDEV_TX_OK
;
1491 * Free ring elements from starting at tx_cons until "done"
1493 * NB: the hardware will tell us about partial completion of multi-part
1494 * buffers so make sure not to free skb to early.
1496 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1498 struct net_device
*dev
= sky2
->netdev
;
1499 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1502 BUG_ON(done
>= TX_RING_SIZE
);
1504 for (idx
= sky2
->tx_cons
; idx
!= done
;
1505 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1506 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1507 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1509 switch(le
->opcode
& ~HW_OWNER
) {
1512 pci_unmap_single(pdev
,
1513 pci_unmap_addr(re
, mapaddr
),
1514 pci_unmap_len(re
, maplen
),
1518 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1519 pci_unmap_len(re
, maplen
),
1524 if (le
->ctrl
& EOP
) {
1525 if (unlikely(netif_msg_tx_done(sky2
)))
1526 printk(KERN_DEBUG
"%s: tx done %u\n",
1528 sky2
->net_stats
.tx_packets
++;
1529 sky2
->net_stats
.tx_bytes
+= re
->skb
->len
;
1531 dev_kfree_skb_any(re
->skb
);
1534 le
->opcode
= 0; /* paranoia */
1537 sky2
->tx_cons
= idx
;
1538 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1539 netif_wake_queue(dev
);
1542 /* Cleanup all untransmitted buffers, assume transmitter not running */
1543 static void sky2_tx_clean(struct net_device
*dev
)
1545 struct sky2_port
*sky2
= netdev_priv(dev
);
1547 netif_tx_lock_bh(dev
);
1548 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1549 netif_tx_unlock_bh(dev
);
1552 /* Network shutdown */
1553 static int sky2_down(struct net_device
*dev
)
1555 struct sky2_port
*sky2
= netdev_priv(dev
);
1556 struct sky2_hw
*hw
= sky2
->hw
;
1557 unsigned port
= sky2
->port
;
1561 /* Never really got started! */
1565 if (netif_msg_ifdown(sky2
))
1566 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1568 /* Stop more packets from being queued */
1569 netif_stop_queue(dev
);
1570 netif_carrier_off(dev
);
1572 /* Disable port IRQ */
1573 imask
= sky2_read32(hw
, B0_IMSK
);
1574 imask
&= ~portirq_msk
[port
];
1575 sky2_write32(hw
, B0_IMSK
, imask
);
1578 * Both ports share the NAPI poll on port 0, so if necessary undo the
1579 * the disable that is done in dev_close.
1581 if (sky2
->port
== 0 && hw
->ports
> 1)
1582 netif_poll_enable(dev
);
1584 sky2_gmac_reset(hw
, port
);
1586 /* Stop transmitter */
1587 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1588 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1590 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1591 RB_RST_SET
| RB_DIS_OP_MD
);
1593 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1594 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1595 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1597 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1599 /* Workaround shared GMAC reset */
1600 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1601 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1602 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1604 /* Disable Force Sync bit and Enable Alloc bit */
1605 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1606 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1608 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1609 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1610 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1612 /* Reset the PCI FIFO of the async Tx queue */
1613 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1614 BMU_RST_SET
| BMU_FIFO_RST
);
1616 /* Reset the Tx prefetch units */
1617 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1620 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1624 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1625 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1627 sky2_phy_power(hw
, port
, 0);
1629 /* turn off LED's */
1630 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1632 synchronize_irq(hw
->pdev
->irq
);
1635 sky2_rx_clean(sky2
);
1637 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1638 sky2
->rx_le
, sky2
->rx_le_map
);
1639 kfree(sky2
->rx_ring
);
1641 pci_free_consistent(hw
->pdev
,
1642 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1643 sky2
->tx_le
, sky2
->tx_le_map
);
1644 kfree(sky2
->tx_ring
);
1649 sky2
->rx_ring
= NULL
;
1650 sky2
->tx_ring
= NULL
;
1655 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1657 if (!sky2_is_copper(hw
))
1660 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1661 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1663 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1664 case PHY_M_PS_SPEED_1000
:
1666 case PHY_M_PS_SPEED_100
:
1673 static void sky2_link_up(struct sky2_port
*sky2
)
1675 struct sky2_hw
*hw
= sky2
->hw
;
1676 unsigned port
= sky2
->port
;
1678 static const char *fc_name
[] = {
1686 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1687 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1688 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1690 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1692 netif_carrier_on(sky2
->netdev
);
1693 netif_wake_queue(sky2
->netdev
);
1695 /* Turn on link LED */
1696 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1697 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1699 if (hw
->chip_id
== CHIP_ID_YUKON_XL
1700 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
1701 || hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1702 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1703 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1705 switch(sky2
->speed
) {
1707 led
|= PHY_M_LEDC_INIT_CTRL(7);
1711 led
|= PHY_M_LEDC_STA1_CTRL(7);
1715 led
|= PHY_M_LEDC_STA0_CTRL(7);
1719 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1720 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1721 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1724 if (netif_msg_link(sky2
))
1725 printk(KERN_INFO PFX
1726 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1727 sky2
->netdev
->name
, sky2
->speed
,
1728 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1729 fc_name
[sky2
->flow_status
]);
1732 static void sky2_link_down(struct sky2_port
*sky2
)
1734 struct sky2_hw
*hw
= sky2
->hw
;
1735 unsigned port
= sky2
->port
;
1738 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1740 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1741 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1742 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1744 netif_carrier_off(sky2
->netdev
);
1745 netif_stop_queue(sky2
->netdev
);
1747 /* Turn on link LED */
1748 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1750 if (netif_msg_link(sky2
))
1751 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1753 sky2_phy_init(hw
, port
);
1756 static enum flow_control
sky2_flow(int rx
, int tx
)
1759 return tx
? FC_BOTH
: FC_RX
;
1761 return tx
? FC_TX
: FC_NONE
;
1764 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1766 struct sky2_hw
*hw
= sky2
->hw
;
1767 unsigned port
= sky2
->port
;
1770 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1771 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1772 if (lpa
& PHY_M_AN_RF
) {
1773 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1777 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1778 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1779 sky2
->netdev
->name
);
1783 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1784 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1786 /* Since the pause result bits seem to in different positions on
1787 * different chips. look at registers.
1789 if (!sky2_is_copper(hw
)) {
1790 /* Shift for bits in fiber PHY */
1791 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1792 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1794 if (advert
& ADVERTISE_1000XPAUSE
)
1795 advert
|= ADVERTISE_PAUSE_CAP
;
1796 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1797 advert
|= ADVERTISE_PAUSE_ASYM
;
1798 if (lpa
& LPA_1000XPAUSE
)
1799 lpa
|= LPA_PAUSE_CAP
;
1800 if (lpa
& LPA_1000XPAUSE_ASYM
)
1801 lpa
|= LPA_PAUSE_ASYM
;
1804 sky2
->flow_status
= FC_NONE
;
1805 if (advert
& ADVERTISE_PAUSE_CAP
) {
1806 if (lpa
& LPA_PAUSE_CAP
)
1807 sky2
->flow_status
= FC_BOTH
;
1808 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1809 sky2
->flow_status
= FC_RX
;
1810 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1811 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1812 sky2
->flow_status
= FC_TX
;
1815 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1816 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1817 sky2
->flow_status
= FC_NONE
;
1819 if (sky2
->flow_status
& FC_TX
)
1820 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1822 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1827 /* Interrupt from PHY */
1828 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1830 struct net_device
*dev
= hw
->dev
[port
];
1831 struct sky2_port
*sky2
= netdev_priv(dev
);
1832 u16 istatus
, phystat
;
1834 if (!netif_running(dev
))
1837 spin_lock(&sky2
->phy_lock
);
1838 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1839 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1841 if (netif_msg_intr(sky2
))
1842 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1843 sky2
->netdev
->name
, istatus
, phystat
);
1845 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1846 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1851 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1852 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1854 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1856 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1858 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1859 if (phystat
& PHY_M_PS_LINK_UP
)
1862 sky2_link_down(sky2
);
1865 spin_unlock(&sky2
->phy_lock
);
1868 /* Transmit timeout is only called if we are running, carrier is up
1869 * and tx queue is full (stopped).
1871 static void sky2_tx_timeout(struct net_device
*dev
)
1873 struct sky2_port
*sky2
= netdev_priv(dev
);
1874 struct sky2_hw
*hw
= sky2
->hw
;
1876 if (netif_msg_timer(sky2
))
1877 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1879 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1880 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
1881 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
1882 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
1884 /* can't restart safely under softirq */
1885 schedule_work(&hw
->restart_work
);
1888 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1890 struct sky2_port
*sky2
= netdev_priv(dev
);
1891 struct sky2_hw
*hw
= sky2
->hw
;
1892 unsigned port
= sky2
->port
;
1897 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1900 if (new_mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_FE
)
1903 if (!netif_running(dev
)) {
1908 imask
= sky2_read32(hw
, B0_IMSK
);
1909 sky2_write32(hw
, B0_IMSK
, 0);
1911 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1912 netif_stop_queue(dev
);
1913 netif_poll_disable(hw
->dev
[0]);
1915 synchronize_irq(hw
->pdev
->irq
);
1917 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1918 if (new_mtu
> ETH_DATA_LEN
) {
1919 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1920 TX_JUMBO_ENA
| TX_STFW_DIS
);
1921 dev
->features
&= NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_IP_CSUM
;
1923 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1924 TX_JUMBO_DIS
| TX_STFW_ENA
);
1927 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1928 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1930 sky2_rx_clean(sky2
);
1934 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1935 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1937 if (dev
->mtu
> ETH_DATA_LEN
)
1938 mode
|= GM_SMOD_JUMBO_ENA
;
1940 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
1942 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
1944 err
= sky2_rx_start(sky2
);
1945 sky2_write32(hw
, B0_IMSK
, imask
);
1950 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
1952 netif_poll_enable(hw
->dev
[0]);
1953 netif_wake_queue(dev
);
1959 /* For small just reuse existing skb for next receive */
1960 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
1961 const struct rx_ring_info
*re
,
1964 struct sk_buff
*skb
;
1966 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
1968 skb_reserve(skb
, 2);
1969 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
1970 length
, PCI_DMA_FROMDEVICE
);
1971 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
1972 skb
->ip_summed
= re
->skb
->ip_summed
;
1973 skb
->csum
= re
->skb
->csum
;
1974 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
1975 length
, PCI_DMA_FROMDEVICE
);
1976 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1977 skb_put(skb
, length
);
1982 /* Adjust length of skb with fragments to match received data */
1983 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
1984 unsigned int length
)
1989 /* put header into skb */
1990 size
= min(length
, hdr_space
);
1995 num_frags
= skb_shinfo(skb
)->nr_frags
;
1996 for (i
= 0; i
< num_frags
; i
++) {
1997 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2000 /* don't need this page */
2001 __free_page(frag
->page
);
2002 --skb_shinfo(skb
)->nr_frags
;
2004 size
= min(length
, (unsigned) PAGE_SIZE
);
2007 skb
->data_len
+= size
;
2008 skb
->truesize
+= size
;
2015 /* Normal packet - take skb from ring element and put in a new one */
2016 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2017 struct rx_ring_info
*re
,
2018 unsigned int length
)
2020 struct sk_buff
*skb
, *nskb
;
2021 unsigned hdr_space
= sky2
->rx_data_size
;
2023 pr_debug(PFX
"receive new length=%d\n", length
);
2025 /* Don't be tricky about reusing pages (yet) */
2026 nskb
= sky2_rx_alloc(sky2
);
2027 if (unlikely(!nskb
))
2031 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2033 prefetch(skb
->data
);
2035 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2037 if (skb_shinfo(skb
)->nr_frags
)
2038 skb_put_frags(skb
, hdr_space
, length
);
2040 skb_put(skb
, length
);
2045 * Receive one packet.
2046 * For larger packets, get new buffer.
2048 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2049 u16 length
, u32 status
)
2051 struct sky2_port
*sky2
= netdev_priv(dev
);
2052 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2053 struct sk_buff
*skb
= NULL
;
2055 if (unlikely(netif_msg_rx_status(sky2
)))
2056 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2057 dev
->name
, sky2
->rx_next
, status
, length
);
2059 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2060 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2062 if (status
& GMR_FS_ANY_ERR
)
2065 if (!(status
& GMR_FS_RX_OK
))
2068 if (length
< copybreak
)
2069 skb
= receive_copy(sky2
, re
, length
);
2071 skb
= receive_new(sky2
, re
, length
);
2073 sky2_rx_submit(sky2
, re
);
2078 ++sky2
->net_stats
.rx_errors
;
2079 if (status
& GMR_FS_RX_FF_OV
) {
2080 sky2
->net_stats
.rx_over_errors
++;
2084 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2085 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2086 dev
->name
, status
, length
);
2088 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2089 sky2
->net_stats
.rx_length_errors
++;
2090 if (status
& GMR_FS_FRAGMENT
)
2091 sky2
->net_stats
.rx_frame_errors
++;
2092 if (status
& GMR_FS_CRC_ERR
)
2093 sky2
->net_stats
.rx_crc_errors
++;
2098 /* Transmit complete */
2099 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2101 struct sky2_port
*sky2
= netdev_priv(dev
);
2103 if (netif_running(dev
)) {
2105 sky2_tx_complete(sky2
, last
);
2106 netif_tx_unlock(dev
);
2110 /* Process status response ring */
2111 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2113 struct sky2_port
*sky2
;
2115 unsigned buf_write
[2] = { 0, 0 };
2116 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2120 while (hw
->st_idx
!= hwidx
) {
2121 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2122 struct net_device
*dev
;
2123 struct sk_buff
*skb
;
2127 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2129 BUG_ON(le
->link
>= 2);
2130 dev
= hw
->dev
[le
->link
];
2132 sky2
= netdev_priv(dev
);
2133 length
= le16_to_cpu(le
->length
);
2134 status
= le32_to_cpu(le
->status
);
2136 switch (le
->opcode
& ~HW_OWNER
) {
2138 skb
= sky2_receive(dev
, length
, status
);
2142 skb
->protocol
= eth_type_trans(skb
, dev
);
2143 sky2
->net_stats
.rx_packets
++;
2144 sky2
->net_stats
.rx_bytes
+= skb
->len
;
2145 dev
->last_rx
= jiffies
;
2147 #ifdef SKY2_VLAN_TAG_USED
2148 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2149 vlan_hwaccel_receive_skb(skb
,
2151 be16_to_cpu(sky2
->rx_tag
));
2154 netif_receive_skb(skb
);
2156 /* Update receiver after 16 frames */
2157 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
2159 sky2_put_idx(hw
, rxqaddr
[le
->link
], sky2
->rx_put
);
2160 buf_write
[le
->link
] = 0;
2163 /* Stop after net poll weight */
2164 if (++work_done
>= to_do
)
2168 #ifdef SKY2_VLAN_TAG_USED
2170 sky2
->rx_tag
= length
;
2174 sky2
->rx_tag
= length
;
2181 /* Both checksum counters are programmed to start at
2182 * the same offset, so unless there is a problem they
2183 * should match. This failure is an early indication that
2184 * hardware receive checksumming won't work.
2186 if (likely(status
>> 16 == (status
& 0xffff))) {
2187 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2188 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2189 skb
->csum
= status
& 0xffff;
2191 printk(KERN_NOTICE PFX
"%s: hardware receive "
2192 "checksum problem (status = %#x)\n",
2195 sky2_write32(sky2
->hw
,
2196 Q_ADDR(rxqaddr
[le
->link
], Q_CSR
),
2202 /* TX index reports status for both ports */
2203 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2204 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2206 sky2_tx_done(hw
->dev
[1],
2207 ((status
>> 24) & 0xff)
2208 | (u16
)(length
& 0xf) << 8);
2212 if (net_ratelimit())
2213 printk(KERN_WARNING PFX
2214 "unknown status opcode 0x%x\n", le
->opcode
);
2219 /* Fully processed status ring so clear irq */
2220 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2224 sky2
= netdev_priv(hw
->dev
[0]);
2225 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2229 sky2
= netdev_priv(hw
->dev
[1]);
2230 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2236 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2238 struct net_device
*dev
= hw
->dev
[port
];
2240 if (net_ratelimit())
2241 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2244 if (status
& Y2_IS_PAR_RD1
) {
2245 if (net_ratelimit())
2246 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2249 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2252 if (status
& Y2_IS_PAR_WR1
) {
2253 if (net_ratelimit())
2254 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2257 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2260 if (status
& Y2_IS_PAR_MAC1
) {
2261 if (net_ratelimit())
2262 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2263 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2266 if (status
& Y2_IS_PAR_RX1
) {
2267 if (net_ratelimit())
2268 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2269 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2272 if (status
& Y2_IS_TCP_TXA1
) {
2273 if (net_ratelimit())
2274 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2276 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2280 static void sky2_hw_intr(struct sky2_hw
*hw
)
2282 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2284 if (status
& Y2_IS_TIST_OV
)
2285 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2287 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2290 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2291 if (net_ratelimit())
2292 dev_err(&hw
->pdev
->dev
, "PCI hardware error (0x%x)\n",
2295 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2296 sky2_pci_write16(hw
, PCI_STATUS
,
2297 pci_err
| PCI_STATUS_ERROR_BITS
);
2298 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2301 if (status
& Y2_IS_PCI_EXP
) {
2302 /* PCI-Express uncorrectable Error occurred */
2305 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2307 if (net_ratelimit())
2308 dev_err(&hw
->pdev
->dev
, "PCI Express error (0x%x)\n",
2311 /* clear the interrupt */
2312 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2313 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2315 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2317 if (pex_err
& PEX_FATAL_ERRORS
) {
2318 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2319 hwmsk
&= ~Y2_IS_PCI_EXP
;
2320 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2324 if (status
& Y2_HWE_L1_MASK
)
2325 sky2_hw_error(hw
, 0, status
);
2327 if (status
& Y2_HWE_L1_MASK
)
2328 sky2_hw_error(hw
, 1, status
);
2331 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2333 struct net_device
*dev
= hw
->dev
[port
];
2334 struct sky2_port
*sky2
= netdev_priv(dev
);
2335 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2337 if (netif_msg_intr(sky2
))
2338 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2341 if (status
& GM_IS_RX_FF_OR
) {
2342 ++sky2
->net_stats
.rx_fifo_errors
;
2343 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2346 if (status
& GM_IS_TX_FF_UR
) {
2347 ++sky2
->net_stats
.tx_fifo_errors
;
2348 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2352 /* This should never happen it is a bug. */
2353 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2354 u16 q
, unsigned ring_size
)
2356 struct net_device
*dev
= hw
->dev
[port
];
2357 struct sky2_port
*sky2
= netdev_priv(dev
);
2359 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2360 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2362 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2363 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2364 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2365 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2367 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2370 /* If idle then force a fake soft NAPI poll once a second
2371 * to work around cases where sharing an edge triggered interrupt.
2373 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2375 if (idle_timeout
> 0)
2376 mod_timer(&hw
->idle_timer
,
2377 jiffies
+ msecs_to_jiffies(idle_timeout
));
2380 static void sky2_idle(unsigned long arg
)
2382 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2383 struct net_device
*dev
= hw
->dev
[0];
2385 if (__netif_rx_schedule_prep(dev
))
2386 __netif_rx_schedule(dev
);
2388 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2391 /* Hardware/software error handling */
2392 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2394 if (net_ratelimit())
2395 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2397 if (status
& Y2_IS_HW_ERR
)
2400 if (status
& Y2_IS_IRQ_MAC1
)
2401 sky2_mac_intr(hw
, 0);
2403 if (status
& Y2_IS_IRQ_MAC2
)
2404 sky2_mac_intr(hw
, 1);
2406 if (status
& Y2_IS_CHK_RX1
)
2407 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2409 if (status
& Y2_IS_CHK_RX2
)
2410 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2412 if (status
& Y2_IS_CHK_TXA1
)
2413 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2415 if (status
& Y2_IS_CHK_TXA2
)
2416 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2419 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2421 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2422 int work_limit
= min(dev0
->quota
, *budget
);
2424 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2426 if (unlikely(status
& Y2_IS_ERROR
))
2427 sky2_err_intr(hw
, status
);
2429 if (status
& Y2_IS_IRQ_PHY1
)
2430 sky2_phy_intr(hw
, 0);
2432 if (status
& Y2_IS_IRQ_PHY2
)
2433 sky2_phy_intr(hw
, 1);
2435 work_done
= sky2_status_intr(hw
, work_limit
);
2436 if (work_done
< work_limit
) {
2437 netif_rx_complete(dev0
);
2439 sky2_read32(hw
, B0_Y2_SP_LISR
);
2442 *budget
-= work_done
;
2443 dev0
->quota
-= work_done
;
2448 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2450 struct sky2_hw
*hw
= dev_id
;
2451 struct net_device
*dev0
= hw
->dev
[0];
2454 /* Reading this mask interrupts as side effect */
2455 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2456 if (status
== 0 || status
== ~0)
2459 prefetch(&hw
->st_le
[hw
->st_idx
]);
2460 if (likely(__netif_rx_schedule_prep(dev0
)))
2461 __netif_rx_schedule(dev0
);
2466 #ifdef CONFIG_NET_POLL_CONTROLLER
2467 static void sky2_netpoll(struct net_device
*dev
)
2469 struct sky2_port
*sky2
= netdev_priv(dev
);
2470 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2472 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2473 __netif_rx_schedule(dev0
);
2477 /* Chip internal frequency for clock calculations */
2478 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2480 switch (hw
->chip_id
) {
2481 case CHIP_ID_YUKON_EC
:
2482 case CHIP_ID_YUKON_EC_U
:
2483 case CHIP_ID_YUKON_EX
:
2484 return 125; /* 125 Mhz */
2485 case CHIP_ID_YUKON_FE
:
2486 return 100; /* 100 Mhz */
2487 default: /* YUKON_XL */
2488 return 156; /* 156 Mhz */
2492 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2494 return sky2_mhz(hw
) * us
;
2497 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2499 return clk
/ sky2_mhz(hw
);
2503 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2507 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2509 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2510 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2511 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2516 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2517 dev_warn(&hw
->pdev
->dev
, "this driver not yet tested on this chip type\n"
2518 "Please report success or failure to <netdev@vger.kernel.org>\n");
2520 /* Make sure and enable all clocks */
2521 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
2522 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2524 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2526 /* This rev is really old, and requires untested workarounds */
2527 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2528 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2529 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2530 hw
->chip_id
, hw
->chip_rev
);
2534 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2536 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2537 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2538 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2545 static void sky2_reset(struct sky2_hw
*hw
)
2551 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2552 status
= sky2_read16(hw
, HCU_CCSR
);
2553 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2554 HCU_CCSR_UC_STATE_MSK
);
2555 sky2_write16(hw
, HCU_CCSR
, status
);
2557 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2558 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2561 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2562 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2564 /* clear PCI errors, if any */
2565 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2567 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2568 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2571 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2573 /* clear any PEX errors */
2574 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2575 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2580 for (i
= 0; i
< hw
->ports
; i
++) {
2581 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2582 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2585 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2587 /* Clear I2C IRQ noise */
2588 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2590 /* turn off hardware timer (unused) */
2591 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2592 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2594 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2596 /* Turn off descriptor polling */
2597 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2599 /* Turn off receive timestamp */
2600 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2601 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2603 /* enable the Tx Arbiters */
2604 for (i
= 0; i
< hw
->ports
; i
++)
2605 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2607 /* Initialize ram interface */
2608 for (i
= 0; i
< hw
->ports
; i
++) {
2609 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2611 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2612 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2613 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2614 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2615 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2616 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2617 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2618 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2619 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2620 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2621 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2622 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2625 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2627 for (i
= 0; i
< hw
->ports
; i
++)
2628 sky2_gmac_reset(hw
, i
);
2630 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2633 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2634 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2636 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2637 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2639 /* Set the list last index */
2640 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2642 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2643 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2645 /* set Status-FIFO ISR watermark */
2646 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2647 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2649 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2651 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2652 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2653 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2655 /* enable status unit */
2656 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2658 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2659 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2660 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2663 static void sky2_restart(struct work_struct
*work
)
2665 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2666 struct net_device
*dev
;
2669 dev_dbg(&hw
->pdev
->dev
, "restarting\n");
2671 del_timer_sync(&hw
->idle_timer
);
2674 sky2_write32(hw
, B0_IMSK
, 0);
2675 sky2_read32(hw
, B0_IMSK
);
2677 netif_poll_disable(hw
->dev
[0]);
2679 for (i
= 0; i
< hw
->ports
; i
++) {
2681 if (netif_running(dev
))
2686 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2687 netif_poll_enable(hw
->dev
[0]);
2689 for (i
= 0; i
< hw
->ports
; i
++) {
2691 if (netif_running(dev
)) {
2694 printk(KERN_INFO PFX
"%s: could not restart %d\n",
2701 sky2_idle_start(hw
);
2706 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2708 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2711 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2713 const struct sky2_port
*sky2
= netdev_priv(dev
);
2715 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2716 wol
->wolopts
= sky2
->wol
;
2719 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2721 struct sky2_port
*sky2
= netdev_priv(dev
);
2722 struct sky2_hw
*hw
= sky2
->hw
;
2724 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2727 sky2
->wol
= wol
->wolopts
;
2729 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
2730 sky2_write32(hw
, B0_CTST
, sky2
->wol
2731 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2733 if (!netif_running(dev
))
2734 sky2_wol_init(sky2
);
2738 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2740 if (sky2_is_copper(hw
)) {
2741 u32 modes
= SUPPORTED_10baseT_Half
2742 | SUPPORTED_10baseT_Full
2743 | SUPPORTED_100baseT_Half
2744 | SUPPORTED_100baseT_Full
2745 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2747 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2748 modes
|= SUPPORTED_1000baseT_Half
2749 | SUPPORTED_1000baseT_Full
;
2752 return SUPPORTED_1000baseT_Half
2753 | SUPPORTED_1000baseT_Full
2758 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2760 struct sky2_port
*sky2
= netdev_priv(dev
);
2761 struct sky2_hw
*hw
= sky2
->hw
;
2763 ecmd
->transceiver
= XCVR_INTERNAL
;
2764 ecmd
->supported
= sky2_supported_modes(hw
);
2765 ecmd
->phy_address
= PHY_ADDR_MARV
;
2766 if (sky2_is_copper(hw
)) {
2767 ecmd
->supported
= SUPPORTED_10baseT_Half
2768 | SUPPORTED_10baseT_Full
2769 | SUPPORTED_100baseT_Half
2770 | SUPPORTED_100baseT_Full
2771 | SUPPORTED_1000baseT_Half
2772 | SUPPORTED_1000baseT_Full
2773 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2774 ecmd
->port
= PORT_TP
;
2775 ecmd
->speed
= sky2
->speed
;
2777 ecmd
->speed
= SPEED_1000
;
2778 ecmd
->port
= PORT_FIBRE
;
2781 ecmd
->advertising
= sky2
->advertising
;
2782 ecmd
->autoneg
= sky2
->autoneg
;
2783 ecmd
->duplex
= sky2
->duplex
;
2787 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2789 struct sky2_port
*sky2
= netdev_priv(dev
);
2790 const struct sky2_hw
*hw
= sky2
->hw
;
2791 u32 supported
= sky2_supported_modes(hw
);
2793 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2794 ecmd
->advertising
= supported
;
2800 switch (ecmd
->speed
) {
2802 if (ecmd
->duplex
== DUPLEX_FULL
)
2803 setting
= SUPPORTED_1000baseT_Full
;
2804 else if (ecmd
->duplex
== DUPLEX_HALF
)
2805 setting
= SUPPORTED_1000baseT_Half
;
2810 if (ecmd
->duplex
== DUPLEX_FULL
)
2811 setting
= SUPPORTED_100baseT_Full
;
2812 else if (ecmd
->duplex
== DUPLEX_HALF
)
2813 setting
= SUPPORTED_100baseT_Half
;
2819 if (ecmd
->duplex
== DUPLEX_FULL
)
2820 setting
= SUPPORTED_10baseT_Full
;
2821 else if (ecmd
->duplex
== DUPLEX_HALF
)
2822 setting
= SUPPORTED_10baseT_Half
;
2830 if ((setting
& supported
) == 0)
2833 sky2
->speed
= ecmd
->speed
;
2834 sky2
->duplex
= ecmd
->duplex
;
2837 sky2
->autoneg
= ecmd
->autoneg
;
2838 sky2
->advertising
= ecmd
->advertising
;
2840 if (netif_running(dev
))
2841 sky2_phy_reinit(sky2
);
2846 static void sky2_get_drvinfo(struct net_device
*dev
,
2847 struct ethtool_drvinfo
*info
)
2849 struct sky2_port
*sky2
= netdev_priv(dev
);
2851 strcpy(info
->driver
, DRV_NAME
);
2852 strcpy(info
->version
, DRV_VERSION
);
2853 strcpy(info
->fw_version
, "N/A");
2854 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2857 static const struct sky2_stat
{
2858 char name
[ETH_GSTRING_LEN
];
2861 { "tx_bytes", GM_TXO_OK_HI
},
2862 { "rx_bytes", GM_RXO_OK_HI
},
2863 { "tx_broadcast", GM_TXF_BC_OK
},
2864 { "rx_broadcast", GM_RXF_BC_OK
},
2865 { "tx_multicast", GM_TXF_MC_OK
},
2866 { "rx_multicast", GM_RXF_MC_OK
},
2867 { "tx_unicast", GM_TXF_UC_OK
},
2868 { "rx_unicast", GM_RXF_UC_OK
},
2869 { "tx_mac_pause", GM_TXF_MPAUSE
},
2870 { "rx_mac_pause", GM_RXF_MPAUSE
},
2871 { "collisions", GM_TXF_COL
},
2872 { "late_collision",GM_TXF_LAT_COL
},
2873 { "aborted", GM_TXF_ABO_COL
},
2874 { "single_collisions", GM_TXF_SNG_COL
},
2875 { "multi_collisions", GM_TXF_MUL_COL
},
2877 { "rx_short", GM_RXF_SHT
},
2878 { "rx_runt", GM_RXE_FRAG
},
2879 { "rx_64_byte_packets", GM_RXF_64B
},
2880 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2881 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2882 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2883 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2884 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2885 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2886 { "rx_too_long", GM_RXF_LNG_ERR
},
2887 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2888 { "rx_jabber", GM_RXF_JAB_PKT
},
2889 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2891 { "tx_64_byte_packets", GM_TXF_64B
},
2892 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2893 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2894 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2895 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2896 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2897 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2898 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2901 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2903 struct sky2_port
*sky2
= netdev_priv(dev
);
2905 return sky2
->rx_csum
;
2908 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2910 struct sky2_port
*sky2
= netdev_priv(dev
);
2912 sky2
->rx_csum
= data
;
2914 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2915 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2920 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2922 struct sky2_port
*sky2
= netdev_priv(netdev
);
2923 return sky2
->msg_enable
;
2926 static int sky2_nway_reset(struct net_device
*dev
)
2928 struct sky2_port
*sky2
= netdev_priv(dev
);
2930 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
2933 sky2_phy_reinit(sky2
);
2938 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2940 struct sky2_hw
*hw
= sky2
->hw
;
2941 unsigned port
= sky2
->port
;
2944 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2945 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2946 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2947 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2949 for (i
= 2; i
< count
; i
++)
2950 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2953 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2955 struct sky2_port
*sky2
= netdev_priv(netdev
);
2956 sky2
->msg_enable
= value
;
2959 static int sky2_get_stats_count(struct net_device
*dev
)
2961 return ARRAY_SIZE(sky2_stats
);
2964 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2965 struct ethtool_stats
*stats
, u64
* data
)
2967 struct sky2_port
*sky2
= netdev_priv(dev
);
2969 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2972 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2976 switch (stringset
) {
2978 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2979 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2980 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2985 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2987 struct sky2_port
*sky2
= netdev_priv(dev
);
2988 return &sky2
->net_stats
;
2991 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2993 struct sky2_port
*sky2
= netdev_priv(dev
);
2994 struct sky2_hw
*hw
= sky2
->hw
;
2995 unsigned port
= sky2
->port
;
2996 const struct sockaddr
*addr
= p
;
2998 if (!is_valid_ether_addr(addr
->sa_data
))
2999 return -EADDRNOTAVAIL
;
3001 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3002 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3003 dev
->dev_addr
, ETH_ALEN
);
3004 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3005 dev
->dev_addr
, ETH_ALEN
);
3007 /* virtual address for data */
3008 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3010 /* physical address: used for pause frames */
3011 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3016 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3020 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3021 filter
[bit
>> 3] |= 1 << (bit
& 7);
3024 static void sky2_set_multicast(struct net_device
*dev
)
3026 struct sky2_port
*sky2
= netdev_priv(dev
);
3027 struct sky2_hw
*hw
= sky2
->hw
;
3028 unsigned port
= sky2
->port
;
3029 struct dev_mc_list
*list
= dev
->mc_list
;
3033 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3035 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3036 memset(filter
, 0, sizeof(filter
));
3038 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3039 reg
|= GM_RXCR_UCF_ENA
;
3041 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3042 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3043 else if (dev
->flags
& IFF_ALLMULTI
)
3044 memset(filter
, 0xff, sizeof(filter
));
3045 else if (dev
->mc_count
== 0 && !rx_pause
)
3046 reg
&= ~GM_RXCR_MCF_ENA
;
3049 reg
|= GM_RXCR_MCF_ENA
;
3052 sky2_add_filter(filter
, pause_mc_addr
);
3054 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3055 sky2_add_filter(filter
, list
->dmi_addr
);
3058 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3059 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3060 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3061 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3062 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3063 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3064 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3065 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3067 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3070 /* Can have one global because blinking is controlled by
3071 * ethtool and that is always under RTNL mutex
3073 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
3077 switch (hw
->chip_id
) {
3078 case CHIP_ID_YUKON_XL
:
3079 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3080 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3081 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3082 on
? (PHY_M_LEDC_LOS_CTRL(1) |
3083 PHY_M_LEDC_INIT_CTRL(7) |
3084 PHY_M_LEDC_STA1_CTRL(7) |
3085 PHY_M_LEDC_STA0_CTRL(7))
3088 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3092 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3093 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3094 on
? PHY_M_LED_ALL
: 0);
3098 /* blink LED's for finding board */
3099 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3101 struct sky2_port
*sky2
= netdev_priv(dev
);
3102 struct sky2_hw
*hw
= sky2
->hw
;
3103 unsigned port
= sky2
->port
;
3104 u16 ledctrl
, ledover
= 0;
3109 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3110 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3114 /* save initial values */
3115 spin_lock_bh(&sky2
->phy_lock
);
3116 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3117 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3118 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3119 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3120 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3122 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3123 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3127 while (!interrupted
&& ms
> 0) {
3128 sky2_led(hw
, port
, onoff
);
3131 spin_unlock_bh(&sky2
->phy_lock
);
3132 interrupted
= msleep_interruptible(250);
3133 spin_lock_bh(&sky2
->phy_lock
);
3138 /* resume regularly scheduled programming */
3139 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3140 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3141 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3142 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3143 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3145 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3146 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3148 spin_unlock_bh(&sky2
->phy_lock
);
3153 static void sky2_get_pauseparam(struct net_device
*dev
,
3154 struct ethtool_pauseparam
*ecmd
)
3156 struct sky2_port
*sky2
= netdev_priv(dev
);
3158 switch (sky2
->flow_mode
) {
3160 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3163 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3166 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3169 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3172 ecmd
->autoneg
= sky2
->autoneg
;
3175 static int sky2_set_pauseparam(struct net_device
*dev
,
3176 struct ethtool_pauseparam
*ecmd
)
3178 struct sky2_port
*sky2
= netdev_priv(dev
);
3180 sky2
->autoneg
= ecmd
->autoneg
;
3181 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3183 if (netif_running(dev
))
3184 sky2_phy_reinit(sky2
);
3189 static int sky2_get_coalesce(struct net_device
*dev
,
3190 struct ethtool_coalesce
*ecmd
)
3192 struct sky2_port
*sky2
= netdev_priv(dev
);
3193 struct sky2_hw
*hw
= sky2
->hw
;
3195 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3196 ecmd
->tx_coalesce_usecs
= 0;
3198 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3199 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3201 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3203 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3204 ecmd
->rx_coalesce_usecs
= 0;
3206 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3207 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3209 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3211 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3212 ecmd
->rx_coalesce_usecs_irq
= 0;
3214 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3215 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3218 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3223 /* Note: this affect both ports */
3224 static int sky2_set_coalesce(struct net_device
*dev
,
3225 struct ethtool_coalesce
*ecmd
)
3227 struct sky2_port
*sky2
= netdev_priv(dev
);
3228 struct sky2_hw
*hw
= sky2
->hw
;
3229 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3231 if (ecmd
->tx_coalesce_usecs
> tmax
||
3232 ecmd
->rx_coalesce_usecs
> tmax
||
3233 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3236 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3238 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3240 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3243 if (ecmd
->tx_coalesce_usecs
== 0)
3244 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3246 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3247 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3248 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3250 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3252 if (ecmd
->rx_coalesce_usecs
== 0)
3253 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3255 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3256 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3257 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3259 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3261 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3262 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3264 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3265 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3266 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3268 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3272 static void sky2_get_ringparam(struct net_device
*dev
,
3273 struct ethtool_ringparam
*ering
)
3275 struct sky2_port
*sky2
= netdev_priv(dev
);
3277 ering
->rx_max_pending
= RX_MAX_PENDING
;
3278 ering
->rx_mini_max_pending
= 0;
3279 ering
->rx_jumbo_max_pending
= 0;
3280 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3282 ering
->rx_pending
= sky2
->rx_pending
;
3283 ering
->rx_mini_pending
= 0;
3284 ering
->rx_jumbo_pending
= 0;
3285 ering
->tx_pending
= sky2
->tx_pending
;
3288 static int sky2_set_ringparam(struct net_device
*dev
,
3289 struct ethtool_ringparam
*ering
)
3291 struct sky2_port
*sky2
= netdev_priv(dev
);
3294 if (ering
->rx_pending
> RX_MAX_PENDING
||
3295 ering
->rx_pending
< 8 ||
3296 ering
->tx_pending
< MAX_SKB_TX_LE
||
3297 ering
->tx_pending
> TX_RING_SIZE
- 1)
3300 if (netif_running(dev
))
3303 sky2
->rx_pending
= ering
->rx_pending
;
3304 sky2
->tx_pending
= ering
->tx_pending
;
3306 if (netif_running(dev
)) {
3311 sky2_set_multicast(dev
);
3317 static int sky2_get_regs_len(struct net_device
*dev
)
3323 * Returns copy of control register region
3324 * Note: access to the RAM address register set will cause timeouts.
3326 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3329 const struct sky2_port
*sky2
= netdev_priv(dev
);
3330 const void __iomem
*io
= sky2
->hw
->regs
;
3332 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3334 memset(p
, 0, regs
->len
);
3336 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3338 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3340 regs
->len
- B3_RI_WTO_R1
);
3343 /* In order to do Jumbo packets on these chips, need to turn off the
3344 * transmit store/forward. Therefore checksum offload won't work.
3346 static int no_tx_offload(struct net_device
*dev
)
3348 const struct sky2_port
*sky2
= netdev_priv(dev
);
3349 const struct sky2_hw
*hw
= sky2
->hw
;
3351 return dev
->mtu
> ETH_DATA_LEN
&&
3352 (hw
->chip_id
== CHIP_ID_YUKON_EX
3353 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
);
3356 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3358 if (data
&& no_tx_offload(dev
))
3361 return ethtool_op_set_tx_csum(dev
, data
);
3365 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3367 if (data
&& no_tx_offload(dev
))
3370 return ethtool_op_set_tso(dev
, data
);
3373 static const struct ethtool_ops sky2_ethtool_ops
= {
3374 .get_settings
= sky2_get_settings
,
3375 .set_settings
= sky2_set_settings
,
3376 .get_drvinfo
= sky2_get_drvinfo
,
3377 .get_wol
= sky2_get_wol
,
3378 .set_wol
= sky2_set_wol
,
3379 .get_msglevel
= sky2_get_msglevel
,
3380 .set_msglevel
= sky2_set_msglevel
,
3381 .nway_reset
= sky2_nway_reset
,
3382 .get_regs_len
= sky2_get_regs_len
,
3383 .get_regs
= sky2_get_regs
,
3384 .get_link
= ethtool_op_get_link
,
3385 .get_sg
= ethtool_op_get_sg
,
3386 .set_sg
= ethtool_op_set_sg
,
3387 .get_tx_csum
= ethtool_op_get_tx_csum
,
3388 .set_tx_csum
= sky2_set_tx_csum
,
3389 .get_tso
= ethtool_op_get_tso
,
3390 .set_tso
= sky2_set_tso
,
3391 .get_rx_csum
= sky2_get_rx_csum
,
3392 .set_rx_csum
= sky2_set_rx_csum
,
3393 .get_strings
= sky2_get_strings
,
3394 .get_coalesce
= sky2_get_coalesce
,
3395 .set_coalesce
= sky2_set_coalesce
,
3396 .get_ringparam
= sky2_get_ringparam
,
3397 .set_ringparam
= sky2_set_ringparam
,
3398 .get_pauseparam
= sky2_get_pauseparam
,
3399 .set_pauseparam
= sky2_set_pauseparam
,
3400 .phys_id
= sky2_phys_id
,
3401 .get_stats_count
= sky2_get_stats_count
,
3402 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3403 .get_perm_addr
= ethtool_op_get_perm_addr
,
3406 /* Initialize network device */
3407 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3409 int highmem
, int wol
)
3411 struct sky2_port
*sky2
;
3412 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3415 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed");
3419 SET_MODULE_OWNER(dev
);
3420 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3421 dev
->irq
= hw
->pdev
->irq
;
3422 dev
->open
= sky2_up
;
3423 dev
->stop
= sky2_down
;
3424 dev
->do_ioctl
= sky2_ioctl
;
3425 dev
->hard_start_xmit
= sky2_xmit_frame
;
3426 dev
->get_stats
= sky2_get_stats
;
3427 dev
->set_multicast_list
= sky2_set_multicast
;
3428 dev
->set_mac_address
= sky2_set_mac_address
;
3429 dev
->change_mtu
= sky2_change_mtu
;
3430 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3431 dev
->tx_timeout
= sky2_tx_timeout
;
3432 dev
->watchdog_timeo
= TX_WATCHDOG
;
3434 dev
->poll
= sky2_poll
;
3435 dev
->weight
= NAPI_WEIGHT
;
3436 #ifdef CONFIG_NET_POLL_CONTROLLER
3437 /* Network console (only works on port 0)
3438 * because netpoll makes assumptions about NAPI
3441 dev
->poll_controller
= sky2_netpoll
;
3444 sky2
= netdev_priv(dev
);
3447 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3449 /* Auto speed and flow control */
3450 sky2
->autoneg
= AUTONEG_ENABLE
;
3451 sky2
->flow_mode
= FC_BOTH
;
3455 sky2
->advertising
= sky2_supported_modes(hw
);
3459 spin_lock_init(&sky2
->phy_lock
);
3460 sky2
->tx_pending
= TX_DEF_PENDING
;
3461 sky2
->rx_pending
= RX_DEF_PENDING
;
3463 hw
->dev
[port
] = dev
;
3467 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
3469 dev
->features
|= NETIF_F_HIGHDMA
;
3471 #ifdef SKY2_VLAN_TAG_USED
3472 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3473 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3474 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3477 /* read the mac address */
3478 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3479 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3481 /* device is off until link detection */
3482 netif_carrier_off(dev
);
3483 netif_stop_queue(dev
);
3488 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3490 const struct sky2_port
*sky2
= netdev_priv(dev
);
3492 if (netif_msg_probe(sky2
))
3493 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3495 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3496 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3499 /* Handle software interrupt used during MSI test */
3500 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3502 struct sky2_hw
*hw
= dev_id
;
3503 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3508 if (status
& Y2_IS_IRQ_SW
) {
3510 wake_up(&hw
->msi_wait
);
3511 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3513 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3518 /* Test interrupt path by forcing a a software IRQ */
3519 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3521 struct pci_dev
*pdev
= hw
->pdev
;
3524 init_waitqueue_head (&hw
->msi_wait
);
3526 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3528 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
3530 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3534 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3535 sky2_read8(hw
, B0_CTST
);
3537 wait_event_timeout(hw
->msi_wait
, hw
->msi
, HZ
/10);
3540 /* MSI test failed, go back to INTx mode */
3541 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
3542 "switching to INTx mode.\n");
3545 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3548 sky2_write32(hw
, B0_IMSK
, 0);
3549 sky2_read32(hw
, B0_IMSK
);
3551 free_irq(pdev
->irq
, hw
);
3556 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
3558 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3563 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
3565 return value
& PCI_PM_CTRL_PME_ENABLE
;
3568 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3569 const struct pci_device_id
*ent
)
3571 struct net_device
*dev
;
3573 int err
, using_dac
= 0, wol_default
;
3575 err
= pci_enable_device(pdev
);
3577 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3581 err
= pci_request_regions(pdev
, DRV_NAME
);
3583 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3584 goto err_out_disable
;
3587 pci_set_master(pdev
);
3589 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3590 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3592 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3594 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
3595 "for consistent allocations\n");
3596 goto err_out_free_regions
;
3599 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3601 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3602 goto err_out_free_regions
;
3606 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
3609 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3611 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3612 goto err_out_free_regions
;
3617 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3619 dev_err(&pdev
->dev
, "cannot map device registers\n");
3620 goto err_out_free_hw
;
3624 /* The sk98lin vendor driver uses hardware byte swapping but
3625 * this driver uses software swapping.
3629 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3630 reg
&= ~PCI_REV_DESC
;
3631 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3635 /* ring for status responses */
3636 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3639 goto err_out_iounmap
;
3641 err
= sky2_init(hw
);
3643 goto err_out_iounmap
;
3645 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3646 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3647 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3648 hw
->chip_id
, hw
->chip_rev
);
3652 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
3655 goto err_out_free_pci
;
3658 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3659 err
= sky2_test_msi(hw
);
3660 if (err
== -EOPNOTSUPP
)
3661 pci_disable_msi(pdev
);
3663 goto err_out_free_netdev
;
3666 err
= register_netdev(dev
);
3668 dev_err(&pdev
->dev
, "cannot register net device\n");
3669 goto err_out_free_netdev
;
3672 err
= request_irq(pdev
->irq
, sky2_intr
, hw
->msi
? 0 : IRQF_SHARED
,
3675 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3676 goto err_out_unregister
;
3678 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3680 sky2_show_addr(dev
);
3682 if (hw
->ports
> 1) {
3683 struct net_device
*dev1
;
3685 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
3687 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
3688 else if ((err
= register_netdev(dev1
))) {
3689 dev_warn(&pdev
->dev
,
3690 "register of second port failed (%d)\n", err
);
3694 sky2_show_addr(dev1
);
3697 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3698 INIT_WORK(&hw
->restart_work
, sky2_restart
);
3700 sky2_idle_start(hw
);
3702 pci_set_drvdata(pdev
, hw
);
3708 pci_disable_msi(pdev
);
3709 unregister_netdev(dev
);
3710 err_out_free_netdev
:
3713 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3714 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3719 err_out_free_regions
:
3720 pci_release_regions(pdev
);
3722 pci_disable_device(pdev
);
3724 pci_set_drvdata(pdev
, NULL
);
3728 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3730 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3731 struct net_device
*dev0
, *dev1
;
3736 del_timer_sync(&hw
->idle_timer
);
3738 flush_scheduled_work();
3740 sky2_write32(hw
, B0_IMSK
, 0);
3741 synchronize_irq(hw
->pdev
->irq
);
3746 unregister_netdev(dev1
);
3747 unregister_netdev(dev0
);
3751 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3752 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3753 sky2_read8(hw
, B0_CTST
);
3755 free_irq(pdev
->irq
, hw
);
3757 pci_disable_msi(pdev
);
3758 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3759 pci_release_regions(pdev
);
3760 pci_disable_device(pdev
);
3768 pci_set_drvdata(pdev
, NULL
);
3772 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3774 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3780 del_timer_sync(&hw
->idle_timer
);
3781 netif_poll_disable(hw
->dev
[0]);
3783 for (i
= 0; i
< hw
->ports
; i
++) {
3784 struct net_device
*dev
= hw
->dev
[i
];
3785 struct sky2_port
*sky2
= netdev_priv(dev
);
3787 if (netif_running(dev
))
3791 sky2_wol_init(sky2
);
3796 sky2_write32(hw
, B0_IMSK
, 0);
3799 pci_save_state(pdev
);
3800 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3801 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3806 static int sky2_resume(struct pci_dev
*pdev
)
3808 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3814 err
= pci_set_power_state(pdev
, PCI_D0
);
3818 err
= pci_restore_state(pdev
);
3822 pci_enable_wake(pdev
, PCI_D0
, 0);
3824 /* Re-enable all clocks */
3825 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
3826 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
3830 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3832 for (i
= 0; i
< hw
->ports
; i
++) {
3833 struct net_device
*dev
= hw
->dev
[i
];
3834 if (netif_running(dev
)) {
3837 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3845 netif_poll_enable(hw
->dev
[0]);
3846 sky2_idle_start(hw
);
3849 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
3850 pci_disable_device(pdev
);
3855 static void sky2_shutdown(struct pci_dev
*pdev
)
3857 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3863 del_timer_sync(&hw
->idle_timer
);
3864 netif_poll_disable(hw
->dev
[0]);
3866 for (i
= 0; i
< hw
->ports
; i
++) {
3867 struct net_device
*dev
= hw
->dev
[i
];
3868 struct sky2_port
*sky2
= netdev_priv(dev
);
3872 sky2_wol_init(sky2
);
3879 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
3880 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
3882 pci_disable_device(pdev
);
3883 pci_set_power_state(pdev
, PCI_D3hot
);
3887 static struct pci_driver sky2_driver
= {
3889 .id_table
= sky2_id_table
,
3890 .probe
= sky2_probe
,
3891 .remove
= __devexit_p(sky2_remove
),
3893 .suspend
= sky2_suspend
,
3894 .resume
= sky2_resume
,
3896 .shutdown
= sky2_shutdown
,
3899 static int __init
sky2_init_module(void)
3901 return pci_register_driver(&sky2_driver
);
3904 static void __exit
sky2_cleanup_module(void)
3906 pci_unregister_driver(&sky2_driver
);
3909 module_init(sky2_init_module
);
3910 module_exit(sky2_cleanup_module
);
3912 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3913 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3914 MODULE_LICENSE("GPL");
3915 MODULE_VERSION(DRV_VERSION
);