2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.25"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN + TSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg
=
86 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
87 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
90 static int debug
= -1; /* defaults above */
91 module_param(debug
, int, 0);
92 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly
= 128;
95 module_param(copybreak
, int, 0);
96 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
98 static int disable_msi
= 0;
99 module_param(disable_msi
, int, 0);
100 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table
) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4355) }, /* 88E8040T */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4357) }, /* 88E8042 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436C) }, /* 88E8072 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4370) }, /* 88E8075 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4380) }, /* 88E8057 */
145 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
147 /* Avoid conditionals by using array */
148 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
149 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
150 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
152 static void sky2_set_multicast(struct net_device
*dev
);
154 /* Access to PHY via serial interconnect */
155 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
159 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
160 gma_write16(hw
, port
, GM_SMI_CTRL
,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
163 for (i
= 0; i
< PHY_RETRIES
; i
++) {
164 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
168 if (!(ctrl
& GM_SMI_CT_BUSY
))
174 dev_warn(&hw
->pdev
->dev
,"%s: phy write timeout\n", hw
->dev
[port
]->name
);
178 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
182 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
186 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
187 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
189 for (i
= 0; i
< PHY_RETRIES
; i
++) {
190 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
194 if (ctrl
& GM_SMI_CT_RD_VAL
) {
195 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
202 dev_warn(&hw
->pdev
->dev
, "%s: phy read timeout\n", hw
->dev
[port
]->name
);
205 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
209 static inline u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
212 __gm_phy_read(hw
, port
, reg
, &v
);
217 static void sky2_power_on(struct sky2_hw
*hw
)
219 /* switch power to VCC (WA for VAUX problem) */
220 sky2_write8(hw
, B0_POWER_CTRL
,
221 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
223 /* disable Core Clock Division, */
224 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
226 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
227 /* enable bits are inverted */
228 sky2_write8(hw
, B2_Y2_CLK_GATE
,
229 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
230 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
231 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
233 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
235 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
238 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
240 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
241 /* set all bits to 0 except bits 15..12 and 8 */
242 reg
&= P_ASPM_CONTROL_MSK
;
243 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
245 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
246 /* set all bits to 0 except bits 28 & 27 */
247 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
248 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
250 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg
= sky2_read32(hw
, B2_GP_IO
);
254 reg
|= GLB_GPIO_STAT_RACE_DIS
;
255 sky2_write32(hw
, B2_GP_IO
, reg
);
257 sky2_read32(hw
, B2_GP_IO
);
261 static void sky2_power_aux(struct sky2_hw
*hw
)
263 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
264 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
266 /* enable bits are inverted */
267 sky2_write8(hw
, B2_Y2_CLK_GATE
,
268 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
269 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
270 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
272 /* switch power to VAUX */
273 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
274 sky2_write8(hw
, B0_POWER_CTRL
,
275 (PC_VAUX_ENA
| PC_VCC_ENA
|
276 PC_VAUX_ON
| PC_VCC_OFF
));
279 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
283 /* disable all GMAC IRQ's */
284 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
286 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
287 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
288 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
289 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
291 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
292 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
293 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
296 /* flow control to advertise bits */
297 static const u16 copper_fc_adv
[] = {
299 [FC_TX
] = PHY_M_AN_ASP
,
300 [FC_RX
] = PHY_M_AN_PC
,
301 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
304 /* flow control to advertise bits when using 1000BaseX */
305 static const u16 fiber_fc_adv
[] = {
306 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
307 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
308 [FC_RX
] = PHY_M_P_SYM_MD_X
,
309 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
312 /* flow control to GMA disable bits */
313 static const u16 gm_fc_disable
[] = {
314 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
315 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
316 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
321 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
323 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
324 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
326 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
327 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
328 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
330 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
332 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
334 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
335 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
336 /* set downshift counter to 3x and enable downshift */
337 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
339 /* set master & slave downshift counter to 1x */
340 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
342 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
345 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
346 if (sky2_is_copper(hw
)) {
347 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
348 /* enable automatic crossover */
349 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
351 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
352 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
355 /* Enable Class A driver for FE+ A0 */
356 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
357 spec
|= PHY_M_FESC_SEL_CL_A
;
358 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
361 /* disable energy detect */
362 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
364 /* enable automatic crossover */
365 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
367 /* downshift on PHY 88E1112 and 88E1149 is changed */
368 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
369 && (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
370 /* set downshift counter to 3x and enable downshift */
371 ctrl
&= ~PHY_M_PC_DSC_MSK
;
372 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
376 /* workaround for deviation #4.88 (CRC errors) */
377 /* disable Automatic Crossover */
379 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
382 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
384 /* special setup for PHY 88E1112 Fiber */
385 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
386 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
388 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
389 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
390 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
391 ctrl
&= ~PHY_M_MAC_MD_MSK
;
392 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
393 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
395 if (hw
->pmd_type
== 'P') {
396 /* select page 1 to access Fiber registers */
397 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
399 /* for SFP-module set SIGDET polarity to low */
400 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
401 ctrl
|= PHY_M_FIB_SIGD_POL
;
402 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
405 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
413 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) {
414 if (sky2_is_copper(hw
)) {
415 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
416 ct1000
|= PHY_M_1000C_AFD
;
417 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
418 ct1000
|= PHY_M_1000C_AHD
;
419 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
420 adv
|= PHY_M_AN_100_FD
;
421 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
422 adv
|= PHY_M_AN_100_HD
;
423 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
424 adv
|= PHY_M_AN_10_FD
;
425 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
426 adv
|= PHY_M_AN_10_HD
;
428 } else { /* special defines for FIBER (88E1040S only) */
429 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
430 adv
|= PHY_M_AN_1000X_AFD
;
431 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
432 adv
|= PHY_M_AN_1000X_AHD
;
435 /* Restart Auto-negotiation */
436 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
438 /* forced speed/duplex settings */
439 ct1000
= PHY_M_1000C_MSE
;
441 /* Disable auto update for duplex flow control and duplex */
442 reg
|= GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_SPD_DIS
;
444 switch (sky2
->speed
) {
446 ctrl
|= PHY_CT_SP1000
;
447 reg
|= GM_GPCR_SPEED_1000
;
450 ctrl
|= PHY_CT_SP100
;
451 reg
|= GM_GPCR_SPEED_100
;
455 if (sky2
->duplex
== DUPLEX_FULL
) {
456 reg
|= GM_GPCR_DUP_FULL
;
457 ctrl
|= PHY_CT_DUP_MD
;
458 } else if (sky2
->speed
< SPEED_1000
)
459 sky2
->flow_mode
= FC_NONE
;
462 if (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
) {
463 if (sky2_is_copper(hw
))
464 adv
|= copper_fc_adv
[sky2
->flow_mode
];
466 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
468 reg
|= GM_GPCR_AU_FCT_DIS
;
469 reg
|= gm_fc_disable
[sky2
->flow_mode
];
471 /* Forward pause packets to GMAC? */
472 if (sky2
->flow_mode
& FC_RX
)
473 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
475 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
478 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
480 if (hw
->flags
& SKY2_HW_GIGABIT
)
481 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
483 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
484 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
486 /* Setup Phy LED's */
487 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
490 switch (hw
->chip_id
) {
491 case CHIP_ID_YUKON_FE
:
492 /* on 88E3082 these bits are at 11..9 (shifted left) */
493 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
495 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
497 /* delete ACT LED control bits */
498 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
499 /* change ACT LED control to blink mode */
500 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
501 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
504 case CHIP_ID_YUKON_FE_P
:
505 /* Enable Link Partner Next Page */
506 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
507 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
509 /* disable Energy Detect and enable scrambler */
510 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
511 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
513 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
514 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
515 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
516 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
518 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
521 case CHIP_ID_YUKON_XL
:
522 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
524 /* select page 3 to access LED control register */
525 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
527 /* set LED Function Control register */
528 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
529 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
530 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
531 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
532 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
534 /* set Polarity Control register */
535 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
536 (PHY_M_POLC_LS1_P_MIX(4) |
537 PHY_M_POLC_IS0_P_MIX(4) |
538 PHY_M_POLC_LOS_CTRL(2) |
539 PHY_M_POLC_INIT_CTRL(2) |
540 PHY_M_POLC_STA1_CTRL(2) |
541 PHY_M_POLC_STA0_CTRL(2)));
543 /* restore page register */
544 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
547 case CHIP_ID_YUKON_EC_U
:
548 case CHIP_ID_YUKON_EX
:
549 case CHIP_ID_YUKON_SUPR
:
550 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
552 /* select page 3 to access LED control register */
553 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
555 /* set LED Function Control register */
556 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
557 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
558 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
559 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
560 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
562 /* set Blink Rate in LED Timer Control Register */
563 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
564 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
565 /* restore page register */
566 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
570 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
571 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
573 /* turn off the Rx LED (LED_RX) */
574 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
577 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_UL_2
) {
578 /* apply fixes in PHY AFE */
579 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
581 /* increase differential signal amplitude in 10BASE-T */
582 gm_phy_write(hw
, port
, 0x18, 0xaa99);
583 gm_phy_write(hw
, port
, 0x17, 0x2011);
585 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
586 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
587 gm_phy_write(hw
, port
, 0x18, 0xa204);
588 gm_phy_write(hw
, port
, 0x17, 0x2002);
591 /* set page register to 0 */
592 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
593 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
594 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
595 /* apply workaround for integrated resistors calibration */
596 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
597 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
598 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
&&
599 hw
->chip_id
< CHIP_ID_YUKON_SUPR
) {
600 /* no effect on Yukon-XL */
601 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
603 if ( !(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
604 || sky2
->speed
== SPEED_100
) {
605 /* turn on 100 Mbps LED (LED_LINK100) */
606 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
610 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
614 /* Enable phy interrupt on auto-negotiation complete (or link up) */
615 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
616 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
618 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
621 static const u32 phy_power
[] = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
622 static const u32 coma_mode
[] = { PCI_Y2_PHY1_COMA
, PCI_Y2_PHY2_COMA
};
624 static void sky2_phy_power_up(struct sky2_hw
*hw
, unsigned port
)
628 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
629 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
630 reg1
&= ~phy_power
[port
];
632 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
633 reg1
|= coma_mode
[port
];
635 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
636 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
637 sky2_pci_read32(hw
, PCI_DEV_REG1
);
639 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
640 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_ANE
);
641 else if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
)
642 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
645 static void sky2_phy_power_down(struct sky2_hw
*hw
, unsigned port
)
650 /* release GPHY Control reset */
651 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
653 /* release GMAC reset */
654 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
656 if (hw
->flags
& SKY2_HW_NEWER_PHY
) {
657 /* select page 2 to access MAC control register */
658 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
660 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
661 /* allow GMII Power Down */
662 ctrl
&= ~PHY_M_MAC_GMIF_PUP
;
663 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
665 /* set page register back to 0 */
666 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
669 /* setup General Purpose Control Register */
670 gma_write16(hw
, port
, GM_GP_CTRL
,
671 GM_GPCR_FL_PASS
| GM_GPCR_SPEED_100
|
672 GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_FCT_DIS
|
675 if (hw
->chip_id
!= CHIP_ID_YUKON_EC
) {
676 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
677 /* select page 2 to access MAC control register */
678 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
680 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
681 /* enable Power Down */
682 ctrl
|= PHY_M_PC_POW_D_ENA
;
683 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
685 /* set page register back to 0 */
686 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
689 /* set IEEE compatible Power Down Mode (dev. #4.99) */
690 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_PDOWN
);
693 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
694 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
695 reg1
|= phy_power
[port
]; /* set PHY to PowerDown/COMA Mode */
696 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
697 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
700 /* Force a renegotiation */
701 static void sky2_phy_reinit(struct sky2_port
*sky2
)
703 spin_lock_bh(&sky2
->phy_lock
);
704 sky2_phy_init(sky2
->hw
, sky2
->port
);
705 spin_unlock_bh(&sky2
->phy_lock
);
708 /* Put device in state to listen for Wake On Lan */
709 static void sky2_wol_init(struct sky2_port
*sky2
)
711 struct sky2_hw
*hw
= sky2
->hw
;
712 unsigned port
= sky2
->port
;
713 enum flow_control save_mode
;
717 /* Bring hardware out of reset */
718 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
719 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
721 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
722 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
725 * sky2_reset will re-enable on resume
727 save_mode
= sky2
->flow_mode
;
728 ctrl
= sky2
->advertising
;
730 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
731 sky2
->flow_mode
= FC_NONE
;
733 spin_lock_bh(&sky2
->phy_lock
);
734 sky2_phy_power_up(hw
, port
);
735 sky2_phy_init(hw
, port
);
736 spin_unlock_bh(&sky2
->phy_lock
);
738 sky2
->flow_mode
= save_mode
;
739 sky2
->advertising
= ctrl
;
741 /* Set GMAC to no flow control and auto update for speed/duplex */
742 gma_write16(hw
, port
, GM_GP_CTRL
,
743 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
744 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
746 /* Set WOL address */
747 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
748 sky2
->netdev
->dev_addr
, ETH_ALEN
);
750 /* Turn on appropriate WOL control bits */
751 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
753 if (sky2
->wol
& WAKE_PHY
)
754 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
756 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
758 if (sky2
->wol
& WAKE_MAGIC
)
759 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
761 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
763 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
764 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
766 /* Turn on legacy PCI-Express PME mode */
767 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
768 reg1
|= PCI_Y2_PME_LEGACY
;
769 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
772 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
776 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
778 struct net_device
*dev
= hw
->dev
[port
];
780 if ( (hw
->chip_id
== CHIP_ID_YUKON_EX
&&
781 hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) ||
782 hw
->chip_id
== CHIP_ID_YUKON_FE_P
||
783 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
784 /* Yukon-Extreme B0 and further Extreme devices */
785 /* enable Store & Forward mode for TX */
787 if (dev
->mtu
<= ETH_DATA_LEN
)
788 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
789 TX_JUMBO_DIS
| TX_STFW_ENA
);
792 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
793 TX_JUMBO_ENA
| TX_STFW_ENA
);
795 if (dev
->mtu
<= ETH_DATA_LEN
)
796 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
798 /* set Tx GMAC FIFO Almost Empty Threshold */
799 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
800 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
802 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
804 /* Can't do offload because of lack of store/forward */
805 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_ALL_CSUM
);
810 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
812 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
816 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
818 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
819 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
821 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
823 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
824 /* WA DEV_472 -- looks like crossed wires on port 2 */
825 /* clear GMAC 1 Control reset */
826 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
828 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
829 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
830 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
831 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
832 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
835 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
837 /* Enable Transmit FIFO Underrun */
838 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
840 spin_lock_bh(&sky2
->phy_lock
);
841 sky2_phy_power_up(hw
, port
);
842 sky2_phy_init(hw
, port
);
843 spin_unlock_bh(&sky2
->phy_lock
);
846 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
847 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
849 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
850 gma_read16(hw
, port
, i
);
851 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
853 /* transmit control */
854 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
856 /* receive control reg: unicast + multicast + no FCS */
857 gma_write16(hw
, port
, GM_RX_CTRL
,
858 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
860 /* transmit flow control */
861 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
863 /* transmit parameter */
864 gma_write16(hw
, port
, GM_TX_PARAM
,
865 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
866 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
867 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
868 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
870 /* serial mode register */
871 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
872 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
874 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
875 reg
|= GM_SMOD_JUMBO_ENA
;
877 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
879 /* virtual address for data */
880 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
882 /* physical address: used for pause frames */
883 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
885 /* ignore counter overflows */
886 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
887 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
888 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
890 /* Configure Rx MAC FIFO */
891 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
892 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
893 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
894 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
895 rx_reg
|= GMF_RX_OVER_ON
;
897 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
899 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
900 /* Hardware errata - clear flush mask */
901 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), 0);
903 /* Flush Rx MAC FIFO on any flow control or error */
904 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
907 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
908 reg
= RX_GMF_FL_THR_DEF
+ 1;
909 /* Another magic mystery workaround from sk98lin */
910 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
911 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
913 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
915 /* Configure Tx MAC FIFO */
916 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
917 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
919 /* On chips without ram buffer, pause is controled by MAC level */
920 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
)) {
921 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
922 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
924 sky2_set_tx_stfwd(hw
, port
);
927 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
928 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
929 /* disable dynamic watermark */
930 reg
= sky2_read16(hw
, SK_REG(port
, TX_GMF_EA
));
931 reg
&= ~TX_DYN_WM_ENA
;
932 sky2_write16(hw
, SK_REG(port
, TX_GMF_EA
), reg
);
936 /* Assign Ram Buffer allocation to queue */
937 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
941 /* convert from K bytes to qwords used for hw register */
944 end
= start
+ space
- 1;
946 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
947 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
948 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
949 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
950 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
952 if (q
== Q_R1
|| q
== Q_R2
) {
953 u32 tp
= space
- space
/4;
955 /* On receive queue's set the thresholds
956 * give receiver priority when > 3/4 full
957 * send pause when down to 2K
959 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
960 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
963 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
964 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
966 /* Enable store & forward on Tx queue's because
967 * Tx FIFO is only 1K on Yukon
969 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
972 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
973 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
976 /* Setup Bus Memory Interface */
977 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
979 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
980 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
981 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
982 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
985 /* Setup prefetch unit registers. This is the interface between
986 * hardware and driver list elements
988 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
989 dma_addr_t addr
, u32 last
)
991 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
992 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
993 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), upper_32_bits(addr
));
994 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), lower_32_bits(addr
));
995 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
996 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
998 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
1001 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
, u16
*slot
)
1003 struct sky2_tx_le
*le
= sky2
->tx_le
+ *slot
;
1004 struct tx_ring_info
*re
= sky2
->tx_ring
+ *slot
;
1006 *slot
= RING_NEXT(*slot
, sky2
->tx_ring_size
);
1013 static void tx_init(struct sky2_port
*sky2
)
1015 struct sky2_tx_le
*le
;
1017 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1018 sky2
->tx_tcpsum
= 0;
1019 sky2
->tx_last_mss
= 0;
1021 le
= get_tx_le(sky2
, &sky2
->tx_prod
);
1023 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1024 sky2
->tx_last_upper
= 0;
1027 /* Update chip's next pointer */
1028 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
1030 /* Make sure write' to descriptors are complete before we tell hardware */
1032 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
1034 /* Synchronize I/O on since next processor may write to tail */
1039 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
1041 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
1042 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
1047 /* Build description to hardware for one receive segment */
1048 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
1049 dma_addr_t map
, unsigned len
)
1051 struct sky2_rx_le
*le
;
1053 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1054 le
= sky2_next_rx(sky2
);
1055 le
->addr
= cpu_to_le32(upper_32_bits(map
));
1056 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1059 le
= sky2_next_rx(sky2
);
1060 le
->addr
= cpu_to_le32(lower_32_bits(map
));
1061 le
->length
= cpu_to_le16(len
);
1062 le
->opcode
= op
| HW_OWNER
;
1065 /* Build description to hardware for one possibly fragmented skb */
1066 static void sky2_rx_submit(struct sky2_port
*sky2
,
1067 const struct rx_ring_info
*re
)
1071 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
1073 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
1074 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
1078 static int sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
1081 struct sk_buff
*skb
= re
->skb
;
1084 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1085 if (unlikely(pci_dma_mapping_error(pdev
, re
->data_addr
)))
1088 pci_unmap_len_set(re
, data_size
, size
);
1090 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1091 re
->frag_addr
[i
] = pci_map_page(pdev
,
1092 skb_shinfo(skb
)->frags
[i
].page
,
1093 skb_shinfo(skb
)->frags
[i
].page_offset
,
1094 skb_shinfo(skb
)->frags
[i
].size
,
1095 PCI_DMA_FROMDEVICE
);
1099 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1101 struct sk_buff
*skb
= re
->skb
;
1104 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1105 PCI_DMA_FROMDEVICE
);
1107 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1108 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1109 skb_shinfo(skb
)->frags
[i
].size
,
1110 PCI_DMA_FROMDEVICE
);
1113 /* Tell chip where to start receive checksum.
1114 * Actually has two checksums, but set both same to avoid possible byte
1117 static void rx_set_checksum(struct sky2_port
*sky2
)
1119 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1121 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1123 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1125 sky2_write32(sky2
->hw
,
1126 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1127 (sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
)
1128 ? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1132 * The RX Stop command will not work for Yukon-2 if the BMU does not
1133 * reach the end of packet and since we can't make sure that we have
1134 * incoming data, we must reset the BMU while it is not doing a DMA
1135 * transfer. Since it is possible that the RX path is still active,
1136 * the RX RAM buffer will be stopped first, so any possible incoming
1137 * data will not trigger a DMA. After the RAM buffer is stopped, the
1138 * BMU is polled until any DMA in progress is ended and only then it
1141 static void sky2_rx_stop(struct sky2_port
*sky2
)
1143 struct sky2_hw
*hw
= sky2
->hw
;
1144 unsigned rxq
= rxqaddr
[sky2
->port
];
1147 /* disable the RAM Buffer receive queue */
1148 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1150 for (i
= 0; i
< 0xffff; i
++)
1151 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1152 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1155 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1156 sky2
->netdev
->name
);
1158 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1160 /* reset the Rx prefetch unit */
1161 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1165 /* Clean out receive buffer area, assumes receiver hardware stopped */
1166 static void sky2_rx_clean(struct sky2_port
*sky2
)
1170 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1171 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1172 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1175 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1182 /* Basic MII support */
1183 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1185 struct mii_ioctl_data
*data
= if_mii(ifr
);
1186 struct sky2_port
*sky2
= netdev_priv(dev
);
1187 struct sky2_hw
*hw
= sky2
->hw
;
1188 int err
= -EOPNOTSUPP
;
1190 if (!netif_running(dev
))
1191 return -ENODEV
; /* Phy still in reset */
1195 data
->phy_id
= PHY_ADDR_MARV
;
1201 spin_lock_bh(&sky2
->phy_lock
);
1202 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1203 spin_unlock_bh(&sky2
->phy_lock
);
1205 data
->val_out
= val
;
1210 if (!capable(CAP_NET_ADMIN
))
1213 spin_lock_bh(&sky2
->phy_lock
);
1214 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1216 spin_unlock_bh(&sky2
->phy_lock
);
1222 #ifdef SKY2_VLAN_TAG_USED
1223 static void sky2_set_vlan_mode(struct sky2_hw
*hw
, u16 port
, bool onoff
)
1226 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1228 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1231 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1233 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1238 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1240 struct sky2_port
*sky2
= netdev_priv(dev
);
1241 struct sky2_hw
*hw
= sky2
->hw
;
1242 u16 port
= sky2
->port
;
1244 netif_tx_lock_bh(dev
);
1245 napi_disable(&hw
->napi
);
1248 sky2_set_vlan_mode(hw
, port
, grp
!= NULL
);
1250 sky2_read32(hw
, B0_Y2_SP_LISR
);
1251 napi_enable(&hw
->napi
);
1252 netif_tx_unlock_bh(dev
);
1256 /* Amount of required worst case padding in rx buffer */
1257 static inline unsigned sky2_rx_pad(const struct sky2_hw
*hw
)
1259 return (hw
->flags
& SKY2_HW_RAM_BUFFER
) ? 8 : 2;
1263 * Allocate an skb for receiving. If the MTU is large enough
1264 * make the skb non-linear with a fragment list of pages.
1266 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1268 struct sk_buff
*skb
;
1271 skb
= netdev_alloc_skb(sky2
->netdev
,
1272 sky2
->rx_data_size
+ sky2_rx_pad(sky2
->hw
));
1276 if (sky2
->hw
->flags
& SKY2_HW_RAM_BUFFER
) {
1277 unsigned char *start
;
1279 * Workaround for a bug in FIFO that cause hang
1280 * if the FIFO if the receive buffer is not 64 byte aligned.
1281 * The buffer returned from netdev_alloc_skb is
1282 * aligned except if slab debugging is enabled.
1284 start
= PTR_ALIGN(skb
->data
, 8);
1285 skb_reserve(skb
, start
- skb
->data
);
1287 skb_reserve(skb
, NET_IP_ALIGN
);
1289 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1290 struct page
*page
= alloc_page(GFP_ATOMIC
);
1294 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1304 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1306 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1310 * Allocate and setup receiver buffer pool.
1311 * Normal case this ends up creating one list element for skb
1312 * in the receive ring. Worst case if using large MTU and each
1313 * allocation falls on a different 64 bit region, that results
1314 * in 6 list elements per ring entry.
1315 * One element is used for checksum enable/disable, and one
1316 * extra to avoid wrap.
1318 static int sky2_rx_start(struct sky2_port
*sky2
)
1320 struct sky2_hw
*hw
= sky2
->hw
;
1321 struct rx_ring_info
*re
;
1322 unsigned rxq
= rxqaddr
[sky2
->port
];
1323 unsigned i
, size
, thresh
;
1325 sky2
->rx_put
= sky2
->rx_next
= 0;
1328 /* On PCI express lowering the watermark gives better performance */
1329 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1330 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1332 /* These chips have no ram buffer?
1333 * MAC Rx RAM Read is controlled by hardware */
1334 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1335 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1336 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1337 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1339 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1341 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1342 rx_set_checksum(sky2
);
1344 /* Space needed for frame data + headers rounded up */
1345 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1347 /* Stopping point for hardware truncation */
1348 thresh
= (size
- 8) / sizeof(u32
);
1350 sky2
->rx_nfrags
= size
>> PAGE_SHIFT
;
1351 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1353 /* Compute residue after pages */
1354 size
-= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1356 /* Optimize to handle small packets and headers */
1357 if (size
< copybreak
)
1359 if (size
< ETH_HLEN
)
1362 sky2
->rx_data_size
= size
;
1365 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1366 re
= sky2
->rx_ring
+ i
;
1368 re
->skb
= sky2_rx_alloc(sky2
);
1372 if (sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
)) {
1373 dev_kfree_skb(re
->skb
);
1378 sky2_rx_submit(sky2
, re
);
1382 * The receiver hangs if it receives frames larger than the
1383 * packet buffer. As a workaround, truncate oversize frames, but
1384 * the register is limited to 9 bits, so if you do frames > 2052
1385 * you better get the MTU right!
1388 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1390 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1391 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1394 /* Tell chip about available buffers */
1395 sky2_rx_update(sky2
, rxq
);
1398 sky2_rx_clean(sky2
);
1402 /* Bring up network interface. */
1403 static int sky2_up(struct net_device
*dev
)
1405 struct sky2_port
*sky2
= netdev_priv(dev
);
1406 struct sky2_hw
*hw
= sky2
->hw
;
1407 unsigned port
= sky2
->port
;
1409 int cap
, err
= -ENOMEM
;
1410 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1413 * On dual port PCI-X card, there is an problem where status
1414 * can be received out of order due to split transactions
1416 if (otherdev
&& netif_running(otherdev
) &&
1417 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1420 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1421 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1422 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1426 netif_carrier_off(dev
);
1428 /* must be power of 2 */
1429 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1430 sky2
->tx_ring_size
*
1431 sizeof(struct sky2_tx_le
),
1436 sky2
->tx_ring
= kcalloc(sky2
->tx_ring_size
, sizeof(struct tx_ring_info
),
1443 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1447 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1449 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1454 sky2_mac_init(hw
, port
);
1456 /* Register is number of 4K blocks on internal RAM buffer. */
1457 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1461 hw
->flags
|= SKY2_HW_RAM_BUFFER
;
1462 pr_debug(PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1464 rxspace
= ramsize
/ 2;
1466 rxspace
= 8 + (2*(ramsize
- 16))/3;
1468 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1469 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1471 /* Make sure SyncQ is disabled */
1472 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1476 sky2_qset(hw
, txqaddr
[port
]);
1478 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1479 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1480 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1482 /* Set almost empty threshold */
1483 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1484 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1485 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1487 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1488 sky2
->tx_ring_size
- 1);
1490 #ifdef SKY2_VLAN_TAG_USED
1491 sky2_set_vlan_mode(hw
, port
, sky2
->vlgrp
!= NULL
);
1494 err
= sky2_rx_start(sky2
);
1498 /* Enable interrupts from phy/mac for port */
1499 imask
= sky2_read32(hw
, B0_IMSK
);
1500 imask
|= portirq_msk
[port
];
1501 sky2_write32(hw
, B0_IMSK
, imask
);
1502 sky2_read32(hw
, B0_IMSK
);
1504 if (netif_msg_ifup(sky2
))
1505 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1511 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1512 sky2
->rx_le
, sky2
->rx_le_map
);
1516 pci_free_consistent(hw
->pdev
,
1517 sky2
->tx_ring_size
* sizeof(struct sky2_tx_le
),
1518 sky2
->tx_le
, sky2
->tx_le_map
);
1521 kfree(sky2
->tx_ring
);
1522 kfree(sky2
->rx_ring
);
1524 sky2
->tx_ring
= NULL
;
1525 sky2
->rx_ring
= NULL
;
1529 /* Modular subtraction in ring */
1530 static inline int tx_inuse(const struct sky2_port
*sky2
)
1532 return (sky2
->tx_prod
- sky2
->tx_cons
) & (sky2
->tx_ring_size
- 1);
1535 /* Number of list elements available for next tx */
1536 static inline int tx_avail(const struct sky2_port
*sky2
)
1538 return sky2
->tx_pending
- tx_inuse(sky2
);
1541 /* Estimate of number of transmit list elements required */
1542 static unsigned tx_le_req(const struct sk_buff
*skb
)
1546 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1547 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1549 if (skb_is_gso(skb
))
1552 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1558 static void sky2_tx_unmap(struct pci_dev
*pdev
,
1559 const struct tx_ring_info
*re
)
1561 if (re
->flags
& TX_MAP_SINGLE
)
1562 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1563 pci_unmap_len(re
, maplen
),
1565 else if (re
->flags
& TX_MAP_PAGE
)
1566 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1567 pci_unmap_len(re
, maplen
),
1572 * Put one packet in ring for transmit.
1573 * A single packet can generate multiple list elements, and
1574 * the number of ring elements will probably be less than the number
1575 * of list elements used.
1577 static netdev_tx_t
sky2_xmit_frame(struct sk_buff
*skb
,
1578 struct net_device
*dev
)
1580 struct sky2_port
*sky2
= netdev_priv(dev
);
1581 struct sky2_hw
*hw
= sky2
->hw
;
1582 struct sky2_tx_le
*le
= NULL
;
1583 struct tx_ring_info
*re
;
1591 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1592 return NETDEV_TX_BUSY
;
1594 len
= skb_headlen(skb
);
1595 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1597 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1600 slot
= sky2
->tx_prod
;
1601 if (unlikely(netif_msg_tx_queued(sky2
)))
1602 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1603 dev
->name
, slot
, skb
->len
);
1605 /* Send high bits if needed */
1606 upper
= upper_32_bits(mapping
);
1607 if (upper
!= sky2
->tx_last_upper
) {
1608 le
= get_tx_le(sky2
, &slot
);
1609 le
->addr
= cpu_to_le32(upper
);
1610 sky2
->tx_last_upper
= upper
;
1611 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1614 /* Check for TCP Segmentation Offload */
1615 mss
= skb_shinfo(skb
)->gso_size
;
1618 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1619 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1621 if (mss
!= sky2
->tx_last_mss
) {
1622 le
= get_tx_le(sky2
, &slot
);
1623 le
->addr
= cpu_to_le32(mss
);
1625 if (hw
->flags
& SKY2_HW_NEW_LE
)
1626 le
->opcode
= OP_MSS
| HW_OWNER
;
1628 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1629 sky2
->tx_last_mss
= mss
;
1634 #ifdef SKY2_VLAN_TAG_USED
1635 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1636 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1638 le
= get_tx_le(sky2
, &slot
);
1640 le
->opcode
= OP_VLAN
|HW_OWNER
;
1642 le
->opcode
|= OP_VLAN
;
1643 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1648 /* Handle TCP checksum offload */
1649 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1650 /* On Yukon EX (some versions) encoding change. */
1651 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1652 ctrl
|= CALSUM
; /* auto checksum */
1654 const unsigned offset
= skb_transport_offset(skb
);
1657 tcpsum
= offset
<< 16; /* sum start */
1658 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1660 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1661 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1664 if (tcpsum
!= sky2
->tx_tcpsum
) {
1665 sky2
->tx_tcpsum
= tcpsum
;
1667 le
= get_tx_le(sky2
, &slot
);
1668 le
->addr
= cpu_to_le32(tcpsum
);
1669 le
->length
= 0; /* initial checksum value */
1670 le
->ctrl
= 1; /* one packet */
1671 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1676 re
= sky2
->tx_ring
+ slot
;
1677 re
->flags
= TX_MAP_SINGLE
;
1678 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1679 pci_unmap_len_set(re
, maplen
, len
);
1681 le
= get_tx_le(sky2
, &slot
);
1682 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1683 le
->length
= cpu_to_le16(len
);
1685 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1688 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1689 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1691 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1692 frag
->size
, PCI_DMA_TODEVICE
);
1694 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1695 goto mapping_unwind
;
1697 upper
= upper_32_bits(mapping
);
1698 if (upper
!= sky2
->tx_last_upper
) {
1699 le
= get_tx_le(sky2
, &slot
);
1700 le
->addr
= cpu_to_le32(upper
);
1701 sky2
->tx_last_upper
= upper
;
1702 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1705 re
= sky2
->tx_ring
+ slot
;
1706 re
->flags
= TX_MAP_PAGE
;
1707 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1708 pci_unmap_len_set(re
, maplen
, frag
->size
);
1710 le
= get_tx_le(sky2
, &slot
);
1711 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1712 le
->length
= cpu_to_le16(frag
->size
);
1714 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1720 sky2
->tx_prod
= slot
;
1722 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1723 netif_stop_queue(dev
);
1725 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1727 return NETDEV_TX_OK
;
1730 for (i
= sky2
->tx_prod
; i
!= slot
; i
= RING_NEXT(i
, sky2
->tx_ring_size
)) {
1731 re
= sky2
->tx_ring
+ i
;
1733 sky2_tx_unmap(hw
->pdev
, re
);
1737 if (net_ratelimit())
1738 dev_warn(&hw
->pdev
->dev
, "%s: tx mapping error\n", dev
->name
);
1740 return NETDEV_TX_OK
;
1744 * Free ring elements from starting at tx_cons until "done"
1747 * 1. The hardware will tell us about partial completion of multi-part
1748 * buffers so make sure not to free skb to early.
1749 * 2. This may run in parallel start_xmit because the it only
1750 * looks at the tail of the queue of FIFO (tx_cons), not
1751 * the head (tx_prod)
1753 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1755 struct net_device
*dev
= sky2
->netdev
;
1758 BUG_ON(done
>= sky2
->tx_ring_size
);
1760 for (idx
= sky2
->tx_cons
; idx
!= done
;
1761 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
1762 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1763 struct sk_buff
*skb
= re
->skb
;
1765 sky2_tx_unmap(sky2
->hw
->pdev
, re
);
1768 if (unlikely(netif_msg_tx_done(sky2
)))
1769 printk(KERN_DEBUG
"%s: tx done %u\n",
1772 dev
->stats
.tx_packets
++;
1773 dev
->stats
.tx_bytes
+= skb
->len
;
1775 dev_kfree_skb_any(skb
);
1777 sky2
->tx_next
= RING_NEXT(idx
, sky2
->tx_ring_size
);
1781 sky2
->tx_cons
= idx
;
1784 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1785 netif_wake_queue(dev
);
1788 static void sky2_tx_reset(struct sky2_hw
*hw
, unsigned port
)
1790 /* Disable Force Sync bit and Enable Alloc bit */
1791 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1792 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1794 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1795 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1796 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1798 /* Reset the PCI FIFO of the async Tx queue */
1799 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1800 BMU_RST_SET
| BMU_FIFO_RST
);
1802 /* Reset the Tx prefetch units */
1803 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1806 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1807 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1810 /* Network shutdown */
1811 static int sky2_down(struct net_device
*dev
)
1813 struct sky2_port
*sky2
= netdev_priv(dev
);
1814 struct sky2_hw
*hw
= sky2
->hw
;
1815 unsigned port
= sky2
->port
;
1819 /* Never really got started! */
1823 if (netif_msg_ifdown(sky2
))
1824 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1826 /* Force flow control off */
1827 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1829 /* Stop transmitter */
1830 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1831 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1833 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1834 RB_RST_SET
| RB_DIS_OP_MD
);
1836 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1837 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1838 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1840 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1842 /* Workaround shared GMAC reset */
1843 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1844 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1845 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1847 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1849 /* Force any delayed status interrrupt and NAPI */
1850 sky2_write32(hw
, STAT_LEV_TIMER_CNT
, 0);
1851 sky2_write32(hw
, STAT_TX_TIMER_CNT
, 0);
1852 sky2_write32(hw
, STAT_ISR_TIMER_CNT
, 0);
1853 sky2_read8(hw
, STAT_ISR_TIMER_CTRL
);
1857 /* Disable port IRQ */
1858 imask
= sky2_read32(hw
, B0_IMSK
);
1859 imask
&= ~portirq_msk
[port
];
1860 sky2_write32(hw
, B0_IMSK
, imask
);
1861 sky2_read32(hw
, B0_IMSK
);
1863 synchronize_irq(hw
->pdev
->irq
);
1864 napi_synchronize(&hw
->napi
);
1866 spin_lock_bh(&sky2
->phy_lock
);
1867 sky2_phy_power_down(hw
, port
);
1868 spin_unlock_bh(&sky2
->phy_lock
);
1870 /* turn off LED's */
1871 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1873 sky2_tx_reset(hw
, port
);
1875 /* Free any pending frames stuck in HW queue */
1876 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1878 sky2_rx_clean(sky2
);
1880 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1881 sky2
->rx_le
, sky2
->rx_le_map
);
1882 kfree(sky2
->rx_ring
);
1884 pci_free_consistent(hw
->pdev
,
1885 sky2
->tx_ring_size
* sizeof(struct sky2_tx_le
),
1886 sky2
->tx_le
, sky2
->tx_le_map
);
1887 kfree(sky2
->tx_ring
);
1892 sky2
->rx_ring
= NULL
;
1893 sky2
->tx_ring
= NULL
;
1898 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1900 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
1903 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
1904 if (aux
& PHY_M_PS_SPEED_100
)
1910 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1911 case PHY_M_PS_SPEED_1000
:
1913 case PHY_M_PS_SPEED_100
:
1920 static void sky2_link_up(struct sky2_port
*sky2
)
1922 struct sky2_hw
*hw
= sky2
->hw
;
1923 unsigned port
= sky2
->port
;
1925 static const char *fc_name
[] = {
1933 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1934 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1935 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1937 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1939 netif_carrier_on(sky2
->netdev
);
1941 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
1943 /* Turn on link LED */
1944 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1945 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1947 if (netif_msg_link(sky2
))
1948 printk(KERN_INFO PFX
1949 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1950 sky2
->netdev
->name
, sky2
->speed
,
1951 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1952 fc_name
[sky2
->flow_status
]);
1955 static void sky2_link_down(struct sky2_port
*sky2
)
1957 struct sky2_hw
*hw
= sky2
->hw
;
1958 unsigned port
= sky2
->port
;
1961 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1963 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1964 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1965 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1967 netif_carrier_off(sky2
->netdev
);
1969 /* Turn on link LED */
1970 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1972 if (netif_msg_link(sky2
))
1973 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1975 sky2_phy_init(hw
, port
);
1978 static enum flow_control
sky2_flow(int rx
, int tx
)
1981 return tx
? FC_BOTH
: FC_RX
;
1983 return tx
? FC_TX
: FC_NONE
;
1986 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1988 struct sky2_hw
*hw
= sky2
->hw
;
1989 unsigned port
= sky2
->port
;
1992 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1993 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1994 if (lpa
& PHY_M_AN_RF
) {
1995 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1999 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
2000 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
2001 sky2
->netdev
->name
);
2005 sky2
->speed
= sky2_phy_speed(hw
, aux
);
2006 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2008 /* Since the pause result bits seem to in different positions on
2009 * different chips. look at registers.
2011 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
2012 /* Shift for bits in fiber PHY */
2013 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
2014 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
2016 if (advert
& ADVERTISE_1000XPAUSE
)
2017 advert
|= ADVERTISE_PAUSE_CAP
;
2018 if (advert
& ADVERTISE_1000XPSE_ASYM
)
2019 advert
|= ADVERTISE_PAUSE_ASYM
;
2020 if (lpa
& LPA_1000XPAUSE
)
2021 lpa
|= LPA_PAUSE_CAP
;
2022 if (lpa
& LPA_1000XPAUSE_ASYM
)
2023 lpa
|= LPA_PAUSE_ASYM
;
2026 sky2
->flow_status
= FC_NONE
;
2027 if (advert
& ADVERTISE_PAUSE_CAP
) {
2028 if (lpa
& LPA_PAUSE_CAP
)
2029 sky2
->flow_status
= FC_BOTH
;
2030 else if (advert
& ADVERTISE_PAUSE_ASYM
)
2031 sky2
->flow_status
= FC_RX
;
2032 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
2033 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
2034 sky2
->flow_status
= FC_TX
;
2037 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
2038 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
2039 sky2
->flow_status
= FC_NONE
;
2041 if (sky2
->flow_status
& FC_TX
)
2042 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2044 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2049 /* Interrupt from PHY */
2050 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2052 struct net_device
*dev
= hw
->dev
[port
];
2053 struct sky2_port
*sky2
= netdev_priv(dev
);
2054 u16 istatus
, phystat
;
2056 if (!netif_running(dev
))
2059 spin_lock(&sky2
->phy_lock
);
2060 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2061 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2063 if (netif_msg_intr(sky2
))
2064 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
2065 sky2
->netdev
->name
, istatus
, phystat
);
2067 if (istatus
& PHY_M_IS_AN_COMPL
) {
2068 if (sky2_autoneg_done(sky2
, phystat
) == 0)
2073 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2074 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
2076 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2078 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2080 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2081 if (phystat
& PHY_M_PS_LINK_UP
)
2084 sky2_link_down(sky2
);
2087 spin_unlock(&sky2
->phy_lock
);
2090 /* Transmit timeout is only called if we are running, carrier is up
2091 * and tx queue is full (stopped).
2093 static void sky2_tx_timeout(struct net_device
*dev
)
2095 struct sky2_port
*sky2
= netdev_priv(dev
);
2096 struct sky2_hw
*hw
= sky2
->hw
;
2098 if (netif_msg_timer(sky2
))
2099 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
2101 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
2102 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
2103 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
2104 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
2106 /* can't restart safely under softirq */
2107 schedule_work(&hw
->restart_work
);
2110 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
2112 struct sky2_port
*sky2
= netdev_priv(dev
);
2113 struct sky2_hw
*hw
= sky2
->hw
;
2114 unsigned port
= sky2
->port
;
2119 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2122 if (new_mtu
> ETH_DATA_LEN
&&
2123 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2124 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2127 if (!netif_running(dev
)) {
2132 imask
= sky2_read32(hw
, B0_IMSK
);
2133 sky2_write32(hw
, B0_IMSK
, 0);
2135 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2136 netif_stop_queue(dev
);
2137 napi_disable(&hw
->napi
);
2139 synchronize_irq(hw
->pdev
->irq
);
2141 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
))
2142 sky2_set_tx_stfwd(hw
, port
);
2144 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2145 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2147 sky2_rx_clean(sky2
);
2151 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
2152 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2154 if (dev
->mtu
> ETH_DATA_LEN
)
2155 mode
|= GM_SMOD_JUMBO_ENA
;
2157 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2159 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2161 err
= sky2_rx_start(sky2
);
2162 sky2_write32(hw
, B0_IMSK
, imask
);
2164 sky2_read32(hw
, B0_Y2_SP_LISR
);
2165 napi_enable(&hw
->napi
);
2170 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2172 netif_wake_queue(dev
);
2178 /* For small just reuse existing skb for next receive */
2179 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2180 const struct rx_ring_info
*re
,
2183 struct sk_buff
*skb
;
2185 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
2187 skb_reserve(skb
, 2);
2188 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2189 length
, PCI_DMA_FROMDEVICE
);
2190 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2191 skb
->ip_summed
= re
->skb
->ip_summed
;
2192 skb
->csum
= re
->skb
->csum
;
2193 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2194 length
, PCI_DMA_FROMDEVICE
);
2195 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2196 skb_put(skb
, length
);
2201 /* Adjust length of skb with fragments to match received data */
2202 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2203 unsigned int length
)
2208 /* put header into skb */
2209 size
= min(length
, hdr_space
);
2214 num_frags
= skb_shinfo(skb
)->nr_frags
;
2215 for (i
= 0; i
< num_frags
; i
++) {
2216 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2219 /* don't need this page */
2220 __free_page(frag
->page
);
2221 --skb_shinfo(skb
)->nr_frags
;
2223 size
= min(length
, (unsigned) PAGE_SIZE
);
2226 skb
->data_len
+= size
;
2227 skb
->truesize
+= size
;
2234 /* Normal packet - take skb from ring element and put in a new one */
2235 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2236 struct rx_ring_info
*re
,
2237 unsigned int length
)
2239 struct sk_buff
*skb
, *nskb
;
2240 unsigned hdr_space
= sky2
->rx_data_size
;
2242 /* Don't be tricky about reusing pages (yet) */
2243 nskb
= sky2_rx_alloc(sky2
);
2244 if (unlikely(!nskb
))
2248 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2250 prefetch(skb
->data
);
2252 if (sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
)) {
2253 dev_kfree_skb(nskb
);
2258 if (skb_shinfo(skb
)->nr_frags
)
2259 skb_put_frags(skb
, hdr_space
, length
);
2261 skb_put(skb
, length
);
2266 * Receive one packet.
2267 * For larger packets, get new buffer.
2269 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2270 u16 length
, u32 status
)
2272 struct sky2_port
*sky2
= netdev_priv(dev
);
2273 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2274 struct sk_buff
*skb
= NULL
;
2275 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2277 #ifdef SKY2_VLAN_TAG_USED
2278 /* Account for vlan tag */
2279 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
))
2283 if (unlikely(netif_msg_rx_status(sky2
)))
2284 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2285 dev
->name
, sky2
->rx_next
, status
, length
);
2287 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2288 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2290 /* This chip has hardware problems that generates bogus status.
2291 * So do only marginal checking and expect higher level protocols
2292 * to handle crap frames.
2294 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2295 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2299 if (status
& GMR_FS_ANY_ERR
)
2302 if (!(status
& GMR_FS_RX_OK
))
2305 /* if length reported by DMA does not match PHY, packet was truncated */
2306 if (length
!= count
)
2310 if (length
< copybreak
)
2311 skb
= receive_copy(sky2
, re
, length
);
2313 skb
= receive_new(sky2
, re
, length
);
2315 sky2_rx_submit(sky2
, re
);
2320 /* Truncation of overlength packets
2321 causes PHY length to not match MAC length */
2322 ++dev
->stats
.rx_length_errors
;
2323 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2324 pr_info(PFX
"%s: rx length error: status %#x length %d\n",
2325 dev
->name
, status
, length
);
2329 ++dev
->stats
.rx_errors
;
2330 if (status
& GMR_FS_RX_FF_OV
) {
2331 dev
->stats
.rx_over_errors
++;
2335 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2336 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2337 dev
->name
, status
, length
);
2339 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2340 dev
->stats
.rx_length_errors
++;
2341 if (status
& GMR_FS_FRAGMENT
)
2342 dev
->stats
.rx_frame_errors
++;
2343 if (status
& GMR_FS_CRC_ERR
)
2344 dev
->stats
.rx_crc_errors
++;
2349 /* Transmit complete */
2350 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2352 struct sky2_port
*sky2
= netdev_priv(dev
);
2354 if (netif_running(dev
))
2355 sky2_tx_complete(sky2
, last
);
2358 static inline void sky2_skb_rx(const struct sky2_port
*sky2
,
2359 u32 status
, struct sk_buff
*skb
)
2361 #ifdef SKY2_VLAN_TAG_USED
2362 u16 vlan_tag
= be16_to_cpu(sky2
->rx_tag
);
2363 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2364 if (skb
->ip_summed
== CHECKSUM_NONE
)
2365 vlan_hwaccel_receive_skb(skb
, sky2
->vlgrp
, vlan_tag
);
2367 vlan_gro_receive(&sky2
->hw
->napi
, sky2
->vlgrp
,
2372 if (skb
->ip_summed
== CHECKSUM_NONE
)
2373 netif_receive_skb(skb
);
2375 napi_gro_receive(&sky2
->hw
->napi
, skb
);
2378 static inline void sky2_rx_done(struct sky2_hw
*hw
, unsigned port
,
2379 unsigned packets
, unsigned bytes
)
2382 struct net_device
*dev
= hw
->dev
[port
];
2384 dev
->stats
.rx_packets
+= packets
;
2385 dev
->stats
.rx_bytes
+= bytes
;
2386 dev
->last_rx
= jiffies
;
2387 sky2_rx_update(netdev_priv(dev
), rxqaddr
[port
]);
2391 /* Process status response ring */
2392 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
, u16 idx
)
2395 unsigned int total_bytes
[2] = { 0 };
2396 unsigned int total_packets
[2] = { 0 };
2400 struct sky2_port
*sky2
;
2401 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2403 struct net_device
*dev
;
2404 struct sk_buff
*skb
;
2407 u8 opcode
= le
->opcode
;
2409 if (!(opcode
& HW_OWNER
))
2412 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2414 port
= le
->css
& CSS_LINK_BIT
;
2415 dev
= hw
->dev
[port
];
2416 sky2
= netdev_priv(dev
);
2417 length
= le16_to_cpu(le
->length
);
2418 status
= le32_to_cpu(le
->status
);
2421 switch (opcode
& ~HW_OWNER
) {
2423 total_packets
[port
]++;
2424 total_bytes
[port
] += length
;
2425 skb
= sky2_receive(dev
, length
, status
);
2426 if (unlikely(!skb
)) {
2427 dev
->stats
.rx_dropped
++;
2431 /* This chip reports checksum status differently */
2432 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2433 if ((sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
) &&
2434 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2435 (le
->css
& CSS_TCPUDPCSOK
))
2436 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2438 skb
->ip_summed
= CHECKSUM_NONE
;
2441 skb
->protocol
= eth_type_trans(skb
, dev
);
2443 sky2_skb_rx(sky2
, status
, skb
);
2445 /* Stop after net poll weight */
2446 if (++work_done
>= to_do
)
2450 #ifdef SKY2_VLAN_TAG_USED
2452 sky2
->rx_tag
= length
;
2456 sky2
->rx_tag
= length
;
2460 if (!(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
))
2463 /* If this happens then driver assuming wrong format */
2464 if (unlikely(hw
->flags
& SKY2_HW_NEW_LE
)) {
2465 if (net_ratelimit())
2466 printk(KERN_NOTICE
"%s: unexpected"
2467 " checksum status\n",
2472 /* Both checksum counters are programmed to start at
2473 * the same offset, so unless there is a problem they
2474 * should match. This failure is an early indication that
2475 * hardware receive checksumming won't work.
2477 if (likely(status
>> 16 == (status
& 0xffff))) {
2478 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2479 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2480 skb
->csum
= le16_to_cpu(status
);
2482 printk(KERN_NOTICE PFX
"%s: hardware receive "
2483 "checksum problem (status = %#x)\n",
2485 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
2487 sky2_write32(sky2
->hw
,
2488 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2494 /* TX index reports status for both ports */
2495 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2497 sky2_tx_done(hw
->dev
[1],
2498 ((status
>> 24) & 0xff)
2499 | (u16
)(length
& 0xf) << 8);
2503 if (net_ratelimit())
2504 printk(KERN_WARNING PFX
2505 "unknown status opcode 0x%x\n", opcode
);
2507 } while (hw
->st_idx
!= idx
);
2509 /* Fully processed status ring so clear irq */
2510 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2513 sky2_rx_done(hw
, 0, total_packets
[0], total_bytes
[0]);
2514 sky2_rx_done(hw
, 1, total_packets
[1], total_bytes
[1]);
2519 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2521 struct net_device
*dev
= hw
->dev
[port
];
2523 if (net_ratelimit())
2524 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2527 if (status
& Y2_IS_PAR_RD1
) {
2528 if (net_ratelimit())
2529 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2532 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2535 if (status
& Y2_IS_PAR_WR1
) {
2536 if (net_ratelimit())
2537 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2540 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2543 if (status
& Y2_IS_PAR_MAC1
) {
2544 if (net_ratelimit())
2545 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2546 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2549 if (status
& Y2_IS_PAR_RX1
) {
2550 if (net_ratelimit())
2551 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2552 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2555 if (status
& Y2_IS_TCP_TXA1
) {
2556 if (net_ratelimit())
2557 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2559 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2563 static void sky2_hw_intr(struct sky2_hw
*hw
)
2565 struct pci_dev
*pdev
= hw
->pdev
;
2566 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2567 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2571 if (status
& Y2_IS_TIST_OV
)
2572 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2574 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2577 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2578 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2579 if (net_ratelimit())
2580 dev_err(&pdev
->dev
, "PCI hardware error (0x%x)\n",
2583 sky2_pci_write16(hw
, PCI_STATUS
,
2584 pci_err
| PCI_STATUS_ERROR_BITS
);
2585 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2588 if (status
& Y2_IS_PCI_EXP
) {
2589 /* PCI-Express uncorrectable Error occurred */
2592 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2593 err
= sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2594 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2596 if (net_ratelimit())
2597 dev_err(&pdev
->dev
, "PCI Express error (0x%x)\n", err
);
2599 sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2600 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2603 if (status
& Y2_HWE_L1_MASK
)
2604 sky2_hw_error(hw
, 0, status
);
2606 if (status
& Y2_HWE_L1_MASK
)
2607 sky2_hw_error(hw
, 1, status
);
2610 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2612 struct net_device
*dev
= hw
->dev
[port
];
2613 struct sky2_port
*sky2
= netdev_priv(dev
);
2614 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2616 if (netif_msg_intr(sky2
))
2617 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2620 if (status
& GM_IS_RX_CO_OV
)
2621 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2623 if (status
& GM_IS_TX_CO_OV
)
2624 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2626 if (status
& GM_IS_RX_FF_OR
) {
2627 ++dev
->stats
.rx_fifo_errors
;
2628 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2631 if (status
& GM_IS_TX_FF_UR
) {
2632 ++dev
->stats
.tx_fifo_errors
;
2633 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2637 /* This should never happen it is a bug. */
2638 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
, u16 q
)
2640 struct net_device
*dev
= hw
->dev
[port
];
2641 u16 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2643 dev_err(&hw
->pdev
->dev
, PFX
2644 "%s: descriptor error q=%#x get=%u put=%u\n",
2645 dev
->name
, (unsigned) q
, (unsigned) idx
,
2646 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2648 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2651 static int sky2_rx_hung(struct net_device
*dev
)
2653 struct sky2_port
*sky2
= netdev_priv(dev
);
2654 struct sky2_hw
*hw
= sky2
->hw
;
2655 unsigned port
= sky2
->port
;
2656 unsigned rxq
= rxqaddr
[port
];
2657 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2658 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2659 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2660 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2662 /* If idle and MAC or PCI is stuck */
2663 if (sky2
->check
.last
== dev
->last_rx
&&
2664 ((mac_rp
== sky2
->check
.mac_rp
&&
2665 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2666 /* Check if the PCI RX hang */
2667 (fifo_rp
== sky2
->check
.fifo_rp
&&
2668 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2669 printk(KERN_DEBUG PFX
"%s: hung mac %d:%d fifo %d (%d:%d)\n",
2670 dev
->name
, mac_lev
, mac_rp
, fifo_lev
, fifo_rp
,
2671 sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2674 sky2
->check
.last
= dev
->last_rx
;
2675 sky2
->check
.mac_rp
= mac_rp
;
2676 sky2
->check
.mac_lev
= mac_lev
;
2677 sky2
->check
.fifo_rp
= fifo_rp
;
2678 sky2
->check
.fifo_lev
= fifo_lev
;
2683 static void sky2_watchdog(unsigned long arg
)
2685 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2687 /* Check for lost IRQ once a second */
2688 if (sky2_read32(hw
, B0_ISRC
)) {
2689 napi_schedule(&hw
->napi
);
2693 for (i
= 0; i
< hw
->ports
; i
++) {
2694 struct net_device
*dev
= hw
->dev
[i
];
2695 if (!netif_running(dev
))
2699 /* For chips with Rx FIFO, check if stuck */
2700 if ((hw
->flags
& SKY2_HW_RAM_BUFFER
) &&
2701 sky2_rx_hung(dev
)) {
2702 pr_info(PFX
"%s: receiver hang detected\n",
2704 schedule_work(&hw
->restart_work
);
2713 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2716 /* Hardware/software error handling */
2717 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2719 if (net_ratelimit())
2720 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2722 if (status
& Y2_IS_HW_ERR
)
2725 if (status
& Y2_IS_IRQ_MAC1
)
2726 sky2_mac_intr(hw
, 0);
2728 if (status
& Y2_IS_IRQ_MAC2
)
2729 sky2_mac_intr(hw
, 1);
2731 if (status
& Y2_IS_CHK_RX1
)
2732 sky2_le_error(hw
, 0, Q_R1
);
2734 if (status
& Y2_IS_CHK_RX2
)
2735 sky2_le_error(hw
, 1, Q_R2
);
2737 if (status
& Y2_IS_CHK_TXA1
)
2738 sky2_le_error(hw
, 0, Q_XA1
);
2740 if (status
& Y2_IS_CHK_TXA2
)
2741 sky2_le_error(hw
, 1, Q_XA2
);
2744 static int sky2_poll(struct napi_struct
*napi
, int work_limit
)
2746 struct sky2_hw
*hw
= container_of(napi
, struct sky2_hw
, napi
);
2747 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2751 if (unlikely(status
& Y2_IS_ERROR
))
2752 sky2_err_intr(hw
, status
);
2754 if (status
& Y2_IS_IRQ_PHY1
)
2755 sky2_phy_intr(hw
, 0);
2757 if (status
& Y2_IS_IRQ_PHY2
)
2758 sky2_phy_intr(hw
, 1);
2760 while ((idx
= sky2_read16(hw
, STAT_PUT_IDX
)) != hw
->st_idx
) {
2761 work_done
+= sky2_status_intr(hw
, work_limit
- work_done
, idx
);
2763 if (work_done
>= work_limit
)
2767 napi_complete(napi
);
2768 sky2_read32(hw
, B0_Y2_SP_LISR
);
2774 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2776 struct sky2_hw
*hw
= dev_id
;
2779 /* Reading this mask interrupts as side effect */
2780 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2781 if (status
== 0 || status
== ~0)
2784 prefetch(&hw
->st_le
[hw
->st_idx
]);
2786 napi_schedule(&hw
->napi
);
2791 #ifdef CONFIG_NET_POLL_CONTROLLER
2792 static void sky2_netpoll(struct net_device
*dev
)
2794 struct sky2_port
*sky2
= netdev_priv(dev
);
2796 napi_schedule(&sky2
->hw
->napi
);
2800 /* Chip internal frequency for clock calculations */
2801 static u32
sky2_mhz(const struct sky2_hw
*hw
)
2803 switch (hw
->chip_id
) {
2804 case CHIP_ID_YUKON_EC
:
2805 case CHIP_ID_YUKON_EC_U
:
2806 case CHIP_ID_YUKON_EX
:
2807 case CHIP_ID_YUKON_SUPR
:
2808 case CHIP_ID_YUKON_UL_2
:
2811 case CHIP_ID_YUKON_FE
:
2814 case CHIP_ID_YUKON_FE_P
:
2817 case CHIP_ID_YUKON_XL
:
2825 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2827 return sky2_mhz(hw
) * us
;
2830 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2832 return clk
/ sky2_mhz(hw
);
2836 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2840 /* Enable all clocks and check for bad PCI access */
2841 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2843 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2845 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2846 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2848 switch(hw
->chip_id
) {
2849 case CHIP_ID_YUKON_XL
:
2850 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_NEWER_PHY
;
2853 case CHIP_ID_YUKON_EC_U
:
2854 hw
->flags
= SKY2_HW_GIGABIT
2856 | SKY2_HW_ADV_POWER_CTL
;
2859 case CHIP_ID_YUKON_EX
:
2860 hw
->flags
= SKY2_HW_GIGABIT
2863 | SKY2_HW_ADV_POWER_CTL
;
2865 /* New transmit checksum */
2866 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
2867 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
2870 case CHIP_ID_YUKON_EC
:
2871 /* This rev is really old, and requires untested workarounds */
2872 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2873 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
2876 hw
->flags
= SKY2_HW_GIGABIT
;
2879 case CHIP_ID_YUKON_FE
:
2882 case CHIP_ID_YUKON_FE_P
:
2883 hw
->flags
= SKY2_HW_NEWER_PHY
2885 | SKY2_HW_AUTO_TX_SUM
2886 | SKY2_HW_ADV_POWER_CTL
;
2889 case CHIP_ID_YUKON_SUPR
:
2890 hw
->flags
= SKY2_HW_GIGABIT
2893 | SKY2_HW_AUTO_TX_SUM
2894 | SKY2_HW_ADV_POWER_CTL
;
2897 case CHIP_ID_YUKON_UL_2
:
2898 hw
->flags
= SKY2_HW_GIGABIT
2899 | SKY2_HW_ADV_POWER_CTL
;
2903 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2908 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2909 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
2910 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
2913 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2914 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2915 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2922 static void sky2_reset(struct sky2_hw
*hw
)
2924 struct pci_dev
*pdev
= hw
->pdev
;
2927 u32 hwe_mask
= Y2_HWE_ALL_MASK
;
2930 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2931 status
= sky2_read16(hw
, HCU_CCSR
);
2932 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2933 HCU_CCSR_UC_STATE_MSK
);
2934 sky2_write16(hw
, HCU_CCSR
, status
);
2936 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2937 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2940 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2941 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2943 /* allow writes to PCI config */
2944 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2946 /* clear PCI errors, if any */
2947 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2948 status
|= PCI_STATUS_ERROR_BITS
;
2949 sky2_pci_write16(hw
, PCI_STATUS
, status
);
2951 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2953 cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
2955 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2958 /* If error bit is stuck on ignore it */
2959 if (sky2_read32(hw
, B0_HWE_ISRC
) & Y2_IS_PCI_EXP
)
2960 dev_info(&pdev
->dev
, "ignoring stuck error report bit\n");
2962 hwe_mask
|= Y2_IS_PCI_EXP
;
2966 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2968 for (i
= 0; i
< hw
->ports
; i
++) {
2969 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2970 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2972 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
2973 hw
->chip_id
== CHIP_ID_YUKON_SUPR
)
2974 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
2975 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
2979 /* Clear I2C IRQ noise */
2980 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2982 /* turn off hardware timer (unused) */
2983 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2984 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2986 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2988 /* Turn off descriptor polling */
2989 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2991 /* Turn off receive timestamp */
2992 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2993 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2995 /* enable the Tx Arbiters */
2996 for (i
= 0; i
< hw
->ports
; i
++)
2997 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2999 /* Initialize ram interface */
3000 for (i
= 0; i
< hw
->ports
; i
++) {
3001 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
3003 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
3004 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
3005 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
3006 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
3007 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
3008 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
3009 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
3010 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
3011 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
3012 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
3013 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
3014 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
3017 sky2_write32(hw
, B0_HWE_IMSK
, hwe_mask
);
3019 for (i
= 0; i
< hw
->ports
; i
++)
3020 sky2_gmac_reset(hw
, i
);
3022 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
3025 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
3026 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
3028 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
3029 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
3031 /* Set the list last index */
3032 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
3034 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
3035 sky2_write8(hw
, STAT_FIFO_WM
, 16);
3037 /* set Status-FIFO ISR watermark */
3038 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
3039 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
3041 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
3043 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
3044 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
3045 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
3047 /* enable status unit */
3048 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
3050 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3051 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3052 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3055 /* Take device down (offline).
3056 * Equivalent to doing dev_stop() but this does not
3057 * inform upper layers of the transistion.
3059 static void sky2_detach(struct net_device
*dev
)
3061 if (netif_running(dev
)) {
3062 netif_device_detach(dev
); /* stop txq */
3067 /* Bring device back after doing sky2_detach */
3068 static int sky2_reattach(struct net_device
*dev
)
3072 if (netif_running(dev
)) {
3075 printk(KERN_INFO PFX
"%s: could not restart %d\n",
3079 netif_device_attach(dev
);
3080 sky2_set_multicast(dev
);
3087 static void sky2_restart(struct work_struct
*work
)
3089 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
3093 for (i
= 0; i
< hw
->ports
; i
++)
3094 sky2_detach(hw
->dev
[i
]);
3096 napi_disable(&hw
->napi
);
3097 sky2_write32(hw
, B0_IMSK
, 0);
3099 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3100 napi_enable(&hw
->napi
);
3102 for (i
= 0; i
< hw
->ports
; i
++)
3103 sky2_reattach(hw
->dev
[i
]);
3108 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
3110 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
3113 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3115 const struct sky2_port
*sky2
= netdev_priv(dev
);
3117 wol
->supported
= sky2_wol_supported(sky2
->hw
);
3118 wol
->wolopts
= sky2
->wol
;
3121 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3123 struct sky2_port
*sky2
= netdev_priv(dev
);
3124 struct sky2_hw
*hw
= sky2
->hw
;
3126 if ((wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
3127 || !device_can_wakeup(&hw
->pdev
->dev
))
3130 sky2
->wol
= wol
->wolopts
;
3132 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3133 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3134 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
3135 sky2_write32(hw
, B0_CTST
, sky2
->wol
3136 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
3138 device_set_wakeup_enable(&hw
->pdev
->dev
, sky2
->wol
);
3140 if (!netif_running(dev
))
3141 sky2_wol_init(sky2
);
3145 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
3147 if (sky2_is_copper(hw
)) {
3148 u32 modes
= SUPPORTED_10baseT_Half
3149 | SUPPORTED_10baseT_Full
3150 | SUPPORTED_100baseT_Half
3151 | SUPPORTED_100baseT_Full
3152 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
3154 if (hw
->flags
& SKY2_HW_GIGABIT
)
3155 modes
|= SUPPORTED_1000baseT_Half
3156 | SUPPORTED_1000baseT_Full
;
3159 return SUPPORTED_1000baseT_Half
3160 | SUPPORTED_1000baseT_Full
3165 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3167 struct sky2_port
*sky2
= netdev_priv(dev
);
3168 struct sky2_hw
*hw
= sky2
->hw
;
3170 ecmd
->transceiver
= XCVR_INTERNAL
;
3171 ecmd
->supported
= sky2_supported_modes(hw
);
3172 ecmd
->phy_address
= PHY_ADDR_MARV
;
3173 if (sky2_is_copper(hw
)) {
3174 ecmd
->port
= PORT_TP
;
3175 ecmd
->speed
= sky2
->speed
;
3177 ecmd
->speed
= SPEED_1000
;
3178 ecmd
->port
= PORT_FIBRE
;
3181 ecmd
->advertising
= sky2
->advertising
;
3182 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
3183 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3184 ecmd
->duplex
= sky2
->duplex
;
3188 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3190 struct sky2_port
*sky2
= netdev_priv(dev
);
3191 const struct sky2_hw
*hw
= sky2
->hw
;
3192 u32 supported
= sky2_supported_modes(hw
);
3194 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3195 sky2
->flags
|= SKY2_FLAG_AUTO_SPEED
;
3196 ecmd
->advertising
= supported
;
3202 switch (ecmd
->speed
) {
3204 if (ecmd
->duplex
== DUPLEX_FULL
)
3205 setting
= SUPPORTED_1000baseT_Full
;
3206 else if (ecmd
->duplex
== DUPLEX_HALF
)
3207 setting
= SUPPORTED_1000baseT_Half
;
3212 if (ecmd
->duplex
== DUPLEX_FULL
)
3213 setting
= SUPPORTED_100baseT_Full
;
3214 else if (ecmd
->duplex
== DUPLEX_HALF
)
3215 setting
= SUPPORTED_100baseT_Half
;
3221 if (ecmd
->duplex
== DUPLEX_FULL
)
3222 setting
= SUPPORTED_10baseT_Full
;
3223 else if (ecmd
->duplex
== DUPLEX_HALF
)
3224 setting
= SUPPORTED_10baseT_Half
;
3232 if ((setting
& supported
) == 0)
3235 sky2
->speed
= ecmd
->speed
;
3236 sky2
->duplex
= ecmd
->duplex
;
3237 sky2
->flags
&= ~SKY2_FLAG_AUTO_SPEED
;
3240 sky2
->advertising
= ecmd
->advertising
;
3242 if (netif_running(dev
)) {
3243 sky2_phy_reinit(sky2
);
3244 sky2_set_multicast(dev
);
3250 static void sky2_get_drvinfo(struct net_device
*dev
,
3251 struct ethtool_drvinfo
*info
)
3253 struct sky2_port
*sky2
= netdev_priv(dev
);
3255 strcpy(info
->driver
, DRV_NAME
);
3256 strcpy(info
->version
, DRV_VERSION
);
3257 strcpy(info
->fw_version
, "N/A");
3258 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
3261 static const struct sky2_stat
{
3262 char name
[ETH_GSTRING_LEN
];
3265 { "tx_bytes", GM_TXO_OK_HI
},
3266 { "rx_bytes", GM_RXO_OK_HI
},
3267 { "tx_broadcast", GM_TXF_BC_OK
},
3268 { "rx_broadcast", GM_RXF_BC_OK
},
3269 { "tx_multicast", GM_TXF_MC_OK
},
3270 { "rx_multicast", GM_RXF_MC_OK
},
3271 { "tx_unicast", GM_TXF_UC_OK
},
3272 { "rx_unicast", GM_RXF_UC_OK
},
3273 { "tx_mac_pause", GM_TXF_MPAUSE
},
3274 { "rx_mac_pause", GM_RXF_MPAUSE
},
3275 { "collisions", GM_TXF_COL
},
3276 { "late_collision",GM_TXF_LAT_COL
},
3277 { "aborted", GM_TXF_ABO_COL
},
3278 { "single_collisions", GM_TXF_SNG_COL
},
3279 { "multi_collisions", GM_TXF_MUL_COL
},
3281 { "rx_short", GM_RXF_SHT
},
3282 { "rx_runt", GM_RXE_FRAG
},
3283 { "rx_64_byte_packets", GM_RXF_64B
},
3284 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3285 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3286 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3287 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3288 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3289 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3290 { "rx_too_long", GM_RXF_LNG_ERR
},
3291 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3292 { "rx_jabber", GM_RXF_JAB_PKT
},
3293 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3295 { "tx_64_byte_packets", GM_TXF_64B
},
3296 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3297 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3298 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3299 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3300 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3301 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3302 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3305 static u32
sky2_get_rx_csum(struct net_device
*dev
)
3307 struct sky2_port
*sky2
= netdev_priv(dev
);
3309 return !!(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
);
3312 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
3314 struct sky2_port
*sky2
= netdev_priv(dev
);
3317 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
3319 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
3321 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
3322 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
3327 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3329 struct sky2_port
*sky2
= netdev_priv(netdev
);
3330 return sky2
->msg_enable
;
3333 static int sky2_nway_reset(struct net_device
*dev
)
3335 struct sky2_port
*sky2
= netdev_priv(dev
);
3337 if (!netif_running(dev
) || !(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
))
3340 sky2_phy_reinit(sky2
);
3341 sky2_set_multicast(dev
);
3346 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3348 struct sky2_hw
*hw
= sky2
->hw
;
3349 unsigned port
= sky2
->port
;
3352 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3353 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3354 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3355 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3357 for (i
= 2; i
< count
; i
++)
3358 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3361 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3363 struct sky2_port
*sky2
= netdev_priv(netdev
);
3364 sky2
->msg_enable
= value
;
3367 static int sky2_get_sset_count(struct net_device
*dev
, int sset
)
3371 return ARRAY_SIZE(sky2_stats
);
3377 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3378 struct ethtool_stats
*stats
, u64
* data
)
3380 struct sky2_port
*sky2
= netdev_priv(dev
);
3382 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3385 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3389 switch (stringset
) {
3391 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3392 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3393 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3398 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3400 struct sky2_port
*sky2
= netdev_priv(dev
);
3401 struct sky2_hw
*hw
= sky2
->hw
;
3402 unsigned port
= sky2
->port
;
3403 const struct sockaddr
*addr
= p
;
3405 if (!is_valid_ether_addr(addr
->sa_data
))
3406 return -EADDRNOTAVAIL
;
3408 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3409 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3410 dev
->dev_addr
, ETH_ALEN
);
3411 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3412 dev
->dev_addr
, ETH_ALEN
);
3414 /* virtual address for data */
3415 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3417 /* physical address: used for pause frames */
3418 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3423 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3427 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3428 filter
[bit
>> 3] |= 1 << (bit
& 7);
3431 static void sky2_set_multicast(struct net_device
*dev
)
3433 struct sky2_port
*sky2
= netdev_priv(dev
);
3434 struct sky2_hw
*hw
= sky2
->hw
;
3435 unsigned port
= sky2
->port
;
3436 struct dev_mc_list
*list
= dev
->mc_list
;
3440 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3442 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3443 memset(filter
, 0, sizeof(filter
));
3445 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3446 reg
|= GM_RXCR_UCF_ENA
;
3448 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3449 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3450 else if (dev
->flags
& IFF_ALLMULTI
)
3451 memset(filter
, 0xff, sizeof(filter
));
3452 else if (dev
->mc_count
== 0 && !rx_pause
)
3453 reg
&= ~GM_RXCR_MCF_ENA
;
3456 reg
|= GM_RXCR_MCF_ENA
;
3459 sky2_add_filter(filter
, pause_mc_addr
);
3461 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3462 sky2_add_filter(filter
, list
->dmi_addr
);
3465 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3466 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3467 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3468 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3469 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3470 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3471 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3472 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3474 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3477 /* Can have one global because blinking is controlled by
3478 * ethtool and that is always under RTNL mutex
3480 static void sky2_led(struct sky2_port
*sky2
, enum led_mode mode
)
3482 struct sky2_hw
*hw
= sky2
->hw
;
3483 unsigned port
= sky2
->port
;
3485 spin_lock_bh(&sky2
->phy_lock
);
3486 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3487 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3488 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3490 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3491 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3495 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3496 PHY_M_LEDC_LOS_CTRL(8) |
3497 PHY_M_LEDC_INIT_CTRL(8) |
3498 PHY_M_LEDC_STA1_CTRL(8) |
3499 PHY_M_LEDC_STA0_CTRL(8));
3502 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3503 PHY_M_LEDC_LOS_CTRL(9) |
3504 PHY_M_LEDC_INIT_CTRL(9) |
3505 PHY_M_LEDC_STA1_CTRL(9) |
3506 PHY_M_LEDC_STA0_CTRL(9));
3509 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3510 PHY_M_LEDC_LOS_CTRL(0xa) |
3511 PHY_M_LEDC_INIT_CTRL(0xa) |
3512 PHY_M_LEDC_STA1_CTRL(0xa) |
3513 PHY_M_LEDC_STA0_CTRL(0xa));
3516 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3517 PHY_M_LEDC_LOS_CTRL(1) |
3518 PHY_M_LEDC_INIT_CTRL(8) |
3519 PHY_M_LEDC_STA1_CTRL(7) |
3520 PHY_M_LEDC_STA0_CTRL(7));
3523 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3525 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3526 PHY_M_LED_MO_DUP(mode
) |
3527 PHY_M_LED_MO_10(mode
) |
3528 PHY_M_LED_MO_100(mode
) |
3529 PHY_M_LED_MO_1000(mode
) |
3530 PHY_M_LED_MO_RX(mode
) |
3531 PHY_M_LED_MO_TX(mode
));
3533 spin_unlock_bh(&sky2
->phy_lock
);
3536 /* blink LED's for finding board */
3537 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3539 struct sky2_port
*sky2
= netdev_priv(dev
);
3545 for (i
= 0; i
< data
; i
++) {
3546 sky2_led(sky2
, MO_LED_ON
);
3547 if (msleep_interruptible(500))
3549 sky2_led(sky2
, MO_LED_OFF
);
3550 if (msleep_interruptible(500))
3553 sky2_led(sky2
, MO_LED_NORM
);
3558 static void sky2_get_pauseparam(struct net_device
*dev
,
3559 struct ethtool_pauseparam
*ecmd
)
3561 struct sky2_port
*sky2
= netdev_priv(dev
);
3563 switch (sky2
->flow_mode
) {
3565 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3568 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3571 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3574 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3577 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
)
3578 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3581 static int sky2_set_pauseparam(struct net_device
*dev
,
3582 struct ethtool_pauseparam
*ecmd
)
3584 struct sky2_port
*sky2
= netdev_priv(dev
);
3586 if (ecmd
->autoneg
== AUTONEG_ENABLE
)
3587 sky2
->flags
|= SKY2_FLAG_AUTO_PAUSE
;
3589 sky2
->flags
&= ~SKY2_FLAG_AUTO_PAUSE
;
3591 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3593 if (netif_running(dev
))
3594 sky2_phy_reinit(sky2
);
3599 static int sky2_get_coalesce(struct net_device
*dev
,
3600 struct ethtool_coalesce
*ecmd
)
3602 struct sky2_port
*sky2
= netdev_priv(dev
);
3603 struct sky2_hw
*hw
= sky2
->hw
;
3605 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3606 ecmd
->tx_coalesce_usecs
= 0;
3608 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3609 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3611 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3613 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3614 ecmd
->rx_coalesce_usecs
= 0;
3616 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3617 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3619 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3621 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3622 ecmd
->rx_coalesce_usecs_irq
= 0;
3624 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3625 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3628 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3633 /* Note: this affect both ports */
3634 static int sky2_set_coalesce(struct net_device
*dev
,
3635 struct ethtool_coalesce
*ecmd
)
3637 struct sky2_port
*sky2
= netdev_priv(dev
);
3638 struct sky2_hw
*hw
= sky2
->hw
;
3639 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3641 if (ecmd
->tx_coalesce_usecs
> tmax
||
3642 ecmd
->rx_coalesce_usecs
> tmax
||
3643 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3646 if (ecmd
->tx_max_coalesced_frames
>= sky2
->tx_ring_size
-1)
3648 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3650 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3653 if (ecmd
->tx_coalesce_usecs
== 0)
3654 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3656 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3657 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3658 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3660 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3662 if (ecmd
->rx_coalesce_usecs
== 0)
3663 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3665 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3666 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3667 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3669 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3671 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3672 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3674 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3675 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3676 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3678 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3682 static void sky2_get_ringparam(struct net_device
*dev
,
3683 struct ethtool_ringparam
*ering
)
3685 struct sky2_port
*sky2
= netdev_priv(dev
);
3687 ering
->rx_max_pending
= RX_MAX_PENDING
;
3688 ering
->rx_mini_max_pending
= 0;
3689 ering
->rx_jumbo_max_pending
= 0;
3690 ering
->tx_max_pending
= TX_MAX_PENDING
;
3692 ering
->rx_pending
= sky2
->rx_pending
;
3693 ering
->rx_mini_pending
= 0;
3694 ering
->rx_jumbo_pending
= 0;
3695 ering
->tx_pending
= sky2
->tx_pending
;
3698 static int sky2_set_ringparam(struct net_device
*dev
,
3699 struct ethtool_ringparam
*ering
)
3701 struct sky2_port
*sky2
= netdev_priv(dev
);
3703 if (ering
->rx_pending
> RX_MAX_PENDING
||
3704 ering
->rx_pending
< 8 ||
3705 ering
->tx_pending
< TX_MIN_PENDING
||
3706 ering
->tx_pending
> TX_MAX_PENDING
)
3711 sky2
->rx_pending
= ering
->rx_pending
;
3712 sky2
->tx_pending
= ering
->tx_pending
;
3713 sky2
->tx_ring_size
= roundup_pow_of_two(sky2
->tx_pending
+1);
3715 return sky2_reattach(dev
);
3718 static int sky2_get_regs_len(struct net_device
*dev
)
3724 * Returns copy of control register region
3725 * Note: ethtool_get_regs always provides full size (16k) buffer
3727 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3730 const struct sky2_port
*sky2
= netdev_priv(dev
);
3731 const void __iomem
*io
= sky2
->hw
->regs
;
3736 for (b
= 0; b
< 128; b
++) {
3737 /* This complicated switch statement is to make sure and
3738 * only access regions that are unreserved.
3739 * Some blocks are only valid on dual port cards.
3740 * and block 3 has some special diagnostic registers that
3745 /* skip diagnostic ram region */
3746 memcpy_fromio(p
+ 0x10, io
+ 0x10, 128 - 0x10);
3749 /* dual port cards only */
3750 case 5: /* Tx Arbiter 2 */
3752 case 14 ... 15: /* TX2 */
3753 case 17: case 19: /* Ram Buffer 2 */
3754 case 22 ... 23: /* Tx Ram Buffer 2 */
3755 case 25: /* Rx MAC Fifo 1 */
3756 case 27: /* Tx MAC Fifo 2 */
3757 case 31: /* GPHY 2 */
3758 case 40 ... 47: /* Pattern Ram 2 */
3759 case 52: case 54: /* TCP Segmentation 2 */
3760 case 112 ... 116: /* GMAC 2 */
3761 if (sky2
->hw
->ports
== 1)
3764 case 0: /* Control */
3765 case 2: /* Mac address */
3766 case 4: /* Tx Arbiter 1 */
3767 case 7: /* PCI express reg */
3769 case 12 ... 13: /* TX1 */
3770 case 16: case 18:/* Rx Ram Buffer 1 */
3771 case 20 ... 21: /* Tx Ram Buffer 1 */
3772 case 24: /* Rx MAC Fifo 1 */
3773 case 26: /* Tx MAC Fifo 1 */
3774 case 28 ... 29: /* Descriptor and status unit */
3775 case 30: /* GPHY 1*/
3776 case 32 ... 39: /* Pattern Ram 1 */
3777 case 48: case 50: /* TCP Segmentation 1 */
3778 case 56 ... 60: /* PCI space */
3779 case 80 ... 84: /* GMAC 1 */
3780 memcpy_fromio(p
, io
, 128);
3792 /* In order to do Jumbo packets on these chips, need to turn off the
3793 * transmit store/forward. Therefore checksum offload won't work.
3795 static int no_tx_offload(struct net_device
*dev
)
3797 const struct sky2_port
*sky2
= netdev_priv(dev
);
3798 const struct sky2_hw
*hw
= sky2
->hw
;
3800 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3803 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3805 if (data
&& no_tx_offload(dev
))
3808 return ethtool_op_set_tx_csum(dev
, data
);
3812 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3814 if (data
&& no_tx_offload(dev
))
3817 return ethtool_op_set_tso(dev
, data
);
3820 static int sky2_get_eeprom_len(struct net_device
*dev
)
3822 struct sky2_port
*sky2
= netdev_priv(dev
);
3823 struct sky2_hw
*hw
= sky2
->hw
;
3826 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
3827 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3830 static int sky2_vpd_wait(const struct sky2_hw
*hw
, int cap
, u16 busy
)
3832 unsigned long start
= jiffies
;
3834 while ( (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
) == busy
) {
3835 /* Can take up to 10.6 ms for write */
3836 if (time_after(jiffies
, start
+ HZ
/4)) {
3837 dev_err(&hw
->pdev
->dev
, PFX
"VPD cycle timed out");
3846 static int sky2_vpd_read(struct sky2_hw
*hw
, int cap
, void *data
,
3847 u16 offset
, size_t length
)
3851 while (length
> 0) {
3854 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
3855 rc
= sky2_vpd_wait(hw
, cap
, 0);
3859 val
= sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
3861 memcpy(data
, &val
, min(sizeof(val
), length
));
3862 offset
+= sizeof(u32
);
3863 data
+= sizeof(u32
);
3864 length
-= sizeof(u32
);
3870 static int sky2_vpd_write(struct sky2_hw
*hw
, int cap
, const void *data
,
3871 u16 offset
, unsigned int length
)
3876 for (i
= 0; i
< length
; i
+= sizeof(u32
)) {
3877 u32 val
= *(u32
*)(data
+ i
);
3879 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
3880 sky2_pci_write32(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
3882 rc
= sky2_vpd_wait(hw
, cap
, PCI_VPD_ADDR_F
);
3889 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3892 struct sky2_port
*sky2
= netdev_priv(dev
);
3893 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3898 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
3900 return sky2_vpd_read(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
3903 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3906 struct sky2_port
*sky2
= netdev_priv(dev
);
3907 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3912 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
3915 /* Partial writes not supported */
3916 if ((eeprom
->offset
& 3) || (eeprom
->len
& 3))
3919 return sky2_vpd_write(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
3923 static const struct ethtool_ops sky2_ethtool_ops
= {
3924 .get_settings
= sky2_get_settings
,
3925 .set_settings
= sky2_set_settings
,
3926 .get_drvinfo
= sky2_get_drvinfo
,
3927 .get_wol
= sky2_get_wol
,
3928 .set_wol
= sky2_set_wol
,
3929 .get_msglevel
= sky2_get_msglevel
,
3930 .set_msglevel
= sky2_set_msglevel
,
3931 .nway_reset
= sky2_nway_reset
,
3932 .get_regs_len
= sky2_get_regs_len
,
3933 .get_regs
= sky2_get_regs
,
3934 .get_link
= ethtool_op_get_link
,
3935 .get_eeprom_len
= sky2_get_eeprom_len
,
3936 .get_eeprom
= sky2_get_eeprom
,
3937 .set_eeprom
= sky2_set_eeprom
,
3938 .set_sg
= ethtool_op_set_sg
,
3939 .set_tx_csum
= sky2_set_tx_csum
,
3940 .set_tso
= sky2_set_tso
,
3941 .get_rx_csum
= sky2_get_rx_csum
,
3942 .set_rx_csum
= sky2_set_rx_csum
,
3943 .get_strings
= sky2_get_strings
,
3944 .get_coalesce
= sky2_get_coalesce
,
3945 .set_coalesce
= sky2_set_coalesce
,
3946 .get_ringparam
= sky2_get_ringparam
,
3947 .set_ringparam
= sky2_set_ringparam
,
3948 .get_pauseparam
= sky2_get_pauseparam
,
3949 .set_pauseparam
= sky2_set_pauseparam
,
3950 .phys_id
= sky2_phys_id
,
3951 .get_sset_count
= sky2_get_sset_count
,
3952 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3955 #ifdef CONFIG_SKY2_DEBUG
3957 static struct dentry
*sky2_debug
;
3961 * Read and parse the first part of Vital Product Data
3963 #define VPD_SIZE 128
3964 #define VPD_MAGIC 0x82
3966 static const struct vpd_tag
{
3970 { "PN", "Part Number" },
3971 { "EC", "Engineering Level" },
3972 { "MN", "Manufacturer" },
3973 { "SN", "Serial Number" },
3974 { "YA", "Asset Tag" },
3975 { "VL", "First Error Log Message" },
3976 { "VF", "Second Error Log Message" },
3977 { "VB", "Boot Agent ROM Configuration" },
3978 { "VE", "EFI UNDI Configuration" },
3981 static void sky2_show_vpd(struct seq_file
*seq
, struct sky2_hw
*hw
)
3989 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
3990 vpd_size
= 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3992 seq_printf(seq
, "%s Product Data\n", pci_name(hw
->pdev
));
3993 buf
= kmalloc(vpd_size
, GFP_KERNEL
);
3995 seq_puts(seq
, "no memory!\n");
3999 if (pci_read_vpd(hw
->pdev
, 0, vpd_size
, buf
) < 0) {
4000 seq_puts(seq
, "VPD read failed\n");
4004 if (buf
[0] != VPD_MAGIC
) {
4005 seq_printf(seq
, "VPD tag mismatch: %#x\n", buf
[0]);
4009 if (len
== 0 || len
> vpd_size
- 4) {
4010 seq_printf(seq
, "Invalid id length: %d\n", len
);
4014 seq_printf(seq
, "%.*s\n", len
, buf
+ 3);
4017 while (offs
< vpd_size
- 4) {
4020 if (!memcmp("RW", buf
+ offs
, 2)) /* end marker */
4022 len
= buf
[offs
+ 2];
4023 if (offs
+ len
+ 3 >= vpd_size
)
4026 for (i
= 0; i
< ARRAY_SIZE(vpd_tags
); i
++) {
4027 if (!memcmp(vpd_tags
[i
].tag
, buf
+ offs
, 2)) {
4028 seq_printf(seq
, " %s: %.*s\n",
4029 vpd_tags
[i
].label
, len
, buf
+ offs
+ 3);
4039 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
4041 struct net_device
*dev
= seq
->private;
4042 const struct sky2_port
*sky2
= netdev_priv(dev
);
4043 struct sky2_hw
*hw
= sky2
->hw
;
4044 unsigned port
= sky2
->port
;
4048 sky2_show_vpd(seq
, hw
);
4050 seq_printf(seq
, "\nIRQ src=%x mask=%x control=%x\n",
4051 sky2_read32(hw
, B0_ISRC
),
4052 sky2_read32(hw
, B0_IMSK
),
4053 sky2_read32(hw
, B0_Y2_SP_ICR
));
4055 if (!netif_running(dev
)) {
4056 seq_printf(seq
, "network not running\n");
4060 napi_disable(&hw
->napi
);
4061 last
= sky2_read16(hw
, STAT_PUT_IDX
);
4063 if (hw
->st_idx
== last
)
4064 seq_puts(seq
, "Status ring (empty)\n");
4066 seq_puts(seq
, "Status ring\n");
4067 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
4068 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
4069 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
4070 seq_printf(seq
, "[%d] %#x %d %#x\n",
4071 idx
, le
->opcode
, le
->length
, le
->status
);
4073 seq_puts(seq
, "\n");
4076 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
4077 sky2
->tx_cons
, sky2
->tx_prod
,
4078 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
4079 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
4081 /* Dump contents of tx ring */
4083 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< sky2
->tx_ring_size
;
4084 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
4085 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
4086 u32 a
= le32_to_cpu(le
->addr
);
4089 seq_printf(seq
, "%u:", idx
);
4092 switch(le
->opcode
& ~HW_OWNER
) {
4094 seq_printf(seq
, " %#x:", a
);
4097 seq_printf(seq
, " mtu=%d", a
);
4100 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
4103 seq_printf(seq
, " csum=%#x", a
);
4106 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
4109 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
4112 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
4115 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
4116 a
, le16_to_cpu(le
->length
));
4119 if (le
->ctrl
& EOP
) {
4120 seq_putc(seq
, '\n');
4125 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
4126 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
4127 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
4128 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
4130 sky2_read32(hw
, B0_Y2_SP_LISR
);
4131 napi_enable(&hw
->napi
);
4135 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
4137 return single_open(file
, sky2_debug_show
, inode
->i_private
);
4140 static const struct file_operations sky2_debug_fops
= {
4141 .owner
= THIS_MODULE
,
4142 .open
= sky2_debug_open
,
4144 .llseek
= seq_lseek
,
4145 .release
= single_release
,
4149 * Use network device events to create/remove/rename
4150 * debugfs file entries
4152 static int sky2_device_event(struct notifier_block
*unused
,
4153 unsigned long event
, void *ptr
)
4155 struct net_device
*dev
= ptr
;
4156 struct sky2_port
*sky2
= netdev_priv(dev
);
4158 if (dev
->netdev_ops
->ndo_open
!= sky2_up
|| !sky2_debug
)
4162 case NETDEV_CHANGENAME
:
4163 if (sky2
->debugfs
) {
4164 sky2
->debugfs
= debugfs_rename(sky2_debug
, sky2
->debugfs
,
4165 sky2_debug
, dev
->name
);
4169 case NETDEV_GOING_DOWN
:
4170 if (sky2
->debugfs
) {
4171 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
4173 debugfs_remove(sky2
->debugfs
);
4174 sky2
->debugfs
= NULL
;
4179 sky2
->debugfs
= debugfs_create_file(dev
->name
, S_IRUGO
,
4182 if (IS_ERR(sky2
->debugfs
))
4183 sky2
->debugfs
= NULL
;
4189 static struct notifier_block sky2_notifier
= {
4190 .notifier_call
= sky2_device_event
,
4194 static __init
void sky2_debug_init(void)
4198 ent
= debugfs_create_dir("sky2", NULL
);
4199 if (!ent
|| IS_ERR(ent
))
4203 register_netdevice_notifier(&sky2_notifier
);
4206 static __exit
void sky2_debug_cleanup(void)
4209 unregister_netdevice_notifier(&sky2_notifier
);
4210 debugfs_remove(sky2_debug
);
4216 #define sky2_debug_init()
4217 #define sky2_debug_cleanup()
4220 /* Two copies of network device operations to handle special case of
4221 not allowing netpoll on second port */
4222 static const struct net_device_ops sky2_netdev_ops
[2] = {
4224 .ndo_open
= sky2_up
,
4225 .ndo_stop
= sky2_down
,
4226 .ndo_start_xmit
= sky2_xmit_frame
,
4227 .ndo_do_ioctl
= sky2_ioctl
,
4228 .ndo_validate_addr
= eth_validate_addr
,
4229 .ndo_set_mac_address
= sky2_set_mac_address
,
4230 .ndo_set_multicast_list
= sky2_set_multicast
,
4231 .ndo_change_mtu
= sky2_change_mtu
,
4232 .ndo_tx_timeout
= sky2_tx_timeout
,
4233 #ifdef SKY2_VLAN_TAG_USED
4234 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4236 #ifdef CONFIG_NET_POLL_CONTROLLER
4237 .ndo_poll_controller
= sky2_netpoll
,
4241 .ndo_open
= sky2_up
,
4242 .ndo_stop
= sky2_down
,
4243 .ndo_start_xmit
= sky2_xmit_frame
,
4244 .ndo_do_ioctl
= sky2_ioctl
,
4245 .ndo_validate_addr
= eth_validate_addr
,
4246 .ndo_set_mac_address
= sky2_set_mac_address
,
4247 .ndo_set_multicast_list
= sky2_set_multicast
,
4248 .ndo_change_mtu
= sky2_change_mtu
,
4249 .ndo_tx_timeout
= sky2_tx_timeout
,
4250 #ifdef SKY2_VLAN_TAG_USED
4251 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4256 /* Initialize network device */
4257 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
4259 int highmem
, int wol
)
4261 struct sky2_port
*sky2
;
4262 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
4265 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
4269 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
4270 dev
->irq
= hw
->pdev
->irq
;
4271 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
4272 dev
->watchdog_timeo
= TX_WATCHDOG
;
4273 dev
->netdev_ops
= &sky2_netdev_ops
[port
];
4275 sky2
= netdev_priv(dev
);
4278 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
4280 /* Auto speed and flow control */
4281 sky2
->flags
= SKY2_FLAG_AUTO_SPEED
| SKY2_FLAG_AUTO_PAUSE
;
4282 if (hw
->chip_id
!= CHIP_ID_YUKON_XL
)
4283 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
4285 sky2
->flow_mode
= FC_BOTH
;
4289 sky2
->advertising
= sky2_supported_modes(hw
);
4292 spin_lock_init(&sky2
->phy_lock
);
4294 sky2
->tx_pending
= TX_DEF_PENDING
;
4295 sky2
->tx_ring_size
= roundup_pow_of_two(TX_DEF_PENDING
+1);
4296 sky2
->rx_pending
= RX_DEF_PENDING
;
4298 hw
->dev
[port
] = dev
;
4302 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
4304 dev
->features
|= NETIF_F_HIGHDMA
;
4306 #ifdef SKY2_VLAN_TAG_USED
4307 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4308 if (!(sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
4309 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)) {
4310 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4314 /* read the mac address */
4315 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
4316 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4321 static void __devinit
sky2_show_addr(struct net_device
*dev
)
4323 const struct sky2_port
*sky2
= netdev_priv(dev
);
4325 if (netif_msg_probe(sky2
))
4326 printk(KERN_INFO PFX
"%s: addr %pM\n",
4327 dev
->name
, dev
->dev_addr
);
4330 /* Handle software interrupt used during MSI test */
4331 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
4333 struct sky2_hw
*hw
= dev_id
;
4334 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4339 if (status
& Y2_IS_IRQ_SW
) {
4340 hw
->flags
|= SKY2_HW_USE_MSI
;
4341 wake_up(&hw
->msi_wait
);
4342 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4344 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4349 /* Test interrupt path by forcing a a software IRQ */
4350 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
4352 struct pci_dev
*pdev
= hw
->pdev
;
4355 init_waitqueue_head (&hw
->msi_wait
);
4357 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4359 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4361 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4365 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4366 sky2_read8(hw
, B0_CTST
);
4368 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4370 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4371 /* MSI test failed, go back to INTx mode */
4372 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4373 "switching to INTx mode.\n");
4376 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4379 sky2_write32(hw
, B0_IMSK
, 0);
4380 sky2_read32(hw
, B0_IMSK
);
4382 free_irq(pdev
->irq
, hw
);
4387 /* This driver supports yukon2 chipset only */
4388 static const char *sky2_name(u8 chipid
, char *buf
, int sz
)
4390 const char *name
[] = {
4392 "EC Ultra", /* 0xb4 */
4393 "Extreme", /* 0xb5 */
4397 "Supreme", /* 0xb9 */
4401 if (chipid
>= CHIP_ID_YUKON_XL
&& chipid
< CHIP_ID_YUKON_UL_2
)
4402 strncpy(buf
, name
[chipid
- CHIP_ID_YUKON_XL
], sz
);
4404 snprintf(buf
, sz
, "(chip %#x)", chipid
);
4408 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
4409 const struct pci_device_id
*ent
)
4411 struct net_device
*dev
;
4413 int err
, using_dac
= 0, wol_default
;
4417 err
= pci_enable_device(pdev
);
4419 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4423 /* Get configuration information
4424 * Note: only regular PCI config access once to test for HW issues
4425 * other PCI access through shared memory for speed and to
4426 * avoid MMCONFIG problems.
4428 err
= pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
4430 dev_err(&pdev
->dev
, "PCI read config failed\n");
4435 dev_err(&pdev
->dev
, "PCI configuration read error\n");
4439 err
= pci_request_regions(pdev
, DRV_NAME
);
4441 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4442 goto err_out_disable
;
4445 pci_set_master(pdev
);
4447 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4448 !(err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))) {
4450 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
4452 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4453 "for consistent allocations\n");
4454 goto err_out_free_regions
;
4457 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4459 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4460 goto err_out_free_regions
;
4466 /* The sk98lin vendor driver uses hardware byte swapping but
4467 * this driver uses software swapping.
4469 reg
&= ~PCI_REV_DESC
;
4470 err
= pci_write_config_dword(pdev
,PCI_DEV_REG2
, reg
);
4472 dev_err(&pdev
->dev
, "PCI write config failed\n");
4473 goto err_out_free_regions
;
4477 wol_default
= device_may_wakeup(&pdev
->dev
) ? WAKE_MAGIC
: 0;
4480 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
4482 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
4483 goto err_out_free_regions
;
4488 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4490 dev_err(&pdev
->dev
, "cannot map device registers\n");
4491 goto err_out_free_hw
;
4494 /* ring for status responses */
4495 hw
->st_le
= pci_alloc_consistent(pdev
, STATUS_LE_BYTES
, &hw
->st_dma
);
4497 goto err_out_iounmap
;
4499 err
= sky2_init(hw
);
4501 goto err_out_iounmap
;
4503 dev_info(&pdev
->dev
, "Yukon-2 %s chip revision %d\n",
4504 sky2_name(hw
->chip_id
, buf1
, sizeof(buf1
)), hw
->chip_rev
);
4508 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
4511 goto err_out_free_pci
;
4514 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
4515 err
= sky2_test_msi(hw
);
4516 if (err
== -EOPNOTSUPP
)
4517 pci_disable_msi(pdev
);
4519 goto err_out_free_netdev
;
4522 err
= register_netdev(dev
);
4524 dev_err(&pdev
->dev
, "cannot register net device\n");
4525 goto err_out_free_netdev
;
4528 netif_napi_add(dev
, &hw
->napi
, sky2_poll
, NAPI_WEIGHT
);
4530 err
= request_irq(pdev
->irq
, sky2_intr
,
4531 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
4534 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4535 goto err_out_unregister
;
4537 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4538 napi_enable(&hw
->napi
);
4540 sky2_show_addr(dev
);
4542 if (hw
->ports
> 1) {
4543 struct net_device
*dev1
;
4545 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4547 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
4548 else if ((err
= register_netdev(dev1
))) {
4549 dev_warn(&pdev
->dev
,
4550 "register of second port failed (%d)\n", err
);
4554 sky2_show_addr(dev1
);
4557 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
4558 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4560 pci_set_drvdata(pdev
, hw
);
4565 if (hw
->flags
& SKY2_HW_USE_MSI
)
4566 pci_disable_msi(pdev
);
4567 unregister_netdev(dev
);
4568 err_out_free_netdev
:
4571 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4572 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4577 err_out_free_regions
:
4578 pci_release_regions(pdev
);
4580 pci_disable_device(pdev
);
4582 pci_set_drvdata(pdev
, NULL
);
4586 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4588 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4594 del_timer_sync(&hw
->watchdog_timer
);
4595 cancel_work_sync(&hw
->restart_work
);
4597 for (i
= hw
->ports
-1; i
>= 0; --i
)
4598 unregister_netdev(hw
->dev
[i
]);
4600 sky2_write32(hw
, B0_IMSK
, 0);
4604 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
4605 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4606 sky2_read8(hw
, B0_CTST
);
4608 free_irq(pdev
->irq
, hw
);
4609 if (hw
->flags
& SKY2_HW_USE_MSI
)
4610 pci_disable_msi(pdev
);
4611 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4612 pci_release_regions(pdev
);
4613 pci_disable_device(pdev
);
4615 for (i
= hw
->ports
-1; i
>= 0; --i
)
4616 free_netdev(hw
->dev
[i
]);
4621 pci_set_drvdata(pdev
, NULL
);
4625 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4627 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4633 del_timer_sync(&hw
->watchdog_timer
);
4634 cancel_work_sync(&hw
->restart_work
);
4637 for (i
= 0; i
< hw
->ports
; i
++) {
4638 struct net_device
*dev
= hw
->dev
[i
];
4639 struct sky2_port
*sky2
= netdev_priv(dev
);
4644 sky2_wol_init(sky2
);
4649 sky2_write32(hw
, B0_IMSK
, 0);
4650 napi_disable(&hw
->napi
);
4654 pci_save_state(pdev
);
4655 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4656 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4661 static int sky2_resume(struct pci_dev
*pdev
)
4663 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4669 err
= pci_set_power_state(pdev
, PCI_D0
);
4673 err
= pci_restore_state(pdev
);
4677 pci_enable_wake(pdev
, PCI_D0
, 0);
4679 /* Re-enable all clocks */
4680 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
4681 hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
4682 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
4683 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4686 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4687 napi_enable(&hw
->napi
);
4690 for (i
= 0; i
< hw
->ports
; i
++) {
4691 err
= sky2_reattach(hw
->dev
[i
]);
4701 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4702 pci_disable_device(pdev
);
4707 static void sky2_shutdown(struct pci_dev
*pdev
)
4709 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4716 del_timer_sync(&hw
->watchdog_timer
);
4718 for (i
= 0; i
< hw
->ports
; i
++) {
4719 struct net_device
*dev
= hw
->dev
[i
];
4720 struct sky2_port
*sky2
= netdev_priv(dev
);
4724 sky2_wol_init(sky2
);
4732 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4733 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4735 pci_disable_device(pdev
);
4736 pci_set_power_state(pdev
, PCI_D3hot
);
4739 static struct pci_driver sky2_driver
= {
4741 .id_table
= sky2_id_table
,
4742 .probe
= sky2_probe
,
4743 .remove
= __devexit_p(sky2_remove
),
4745 .suspend
= sky2_suspend
,
4746 .resume
= sky2_resume
,
4748 .shutdown
= sky2_shutdown
,
4751 static int __init
sky2_init_module(void)
4753 pr_info(PFX
"driver version " DRV_VERSION
"\n");
4756 return pci_register_driver(&sky2_driver
);
4759 static void __exit
sky2_cleanup_module(void)
4761 pci_unregister_driver(&sky2_driver
);
4762 sky2_debug_cleanup();
4765 module_init(sky2_init_module
);
4766 module_exit(sky2_cleanup_module
);
4768 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4769 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4770 MODULE_LICENSE("GPL");
4771 MODULE_VERSION(DRV_VERSION
);