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[PATCH] sky2: more pci device ids
[mirror_ubuntu-eoan-kernel.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.5"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
63 #define RX_LE_SIZE 512
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 256;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static int idle_timeout = 100;
102 module_param(idle_timeout, int, 0);
103 MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
105 static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
129 { 0 }
130 };
131
132 MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134 /* Avoid conditionals by using array */
135 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
137 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
138
139 /* This driver supports yukon2 chipset only */
140 static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
146 };
147
148 /* Access to external PHY */
149 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
150 {
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
159 return 0;
160 udelay(1);
161 }
162
163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
164 return -ETIMEDOUT;
165 }
166
167 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
168 {
169 int i;
170
171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
180 udelay(1);
181 }
182
183 return -ETIMEDOUT;
184 }
185
186 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187 {
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
193 }
194
195 static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
196 {
197 u16 power_control;
198 u32 reg1;
199 int vaux;
200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
206 (power_control & PCI_PM_CAP_PME_D3cold);
207
208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
231 /* Turn off phy power saving */
232 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
233 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
234
235 /* looks like this XL is back asswards .. */
236 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
237 reg1 |= PCI_Y2_PHY1_COMA;
238 if (hw->ports > 1)
239 reg1 |= PCI_Y2_PHY2_COMA;
240 }
241
242 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
243 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
244 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
245 reg1 &= P_ASPM_CONTROL_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
247 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
248 }
249
250 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
251 udelay(100);
252
253 break;
254
255 case PCI_D3hot:
256 case PCI_D3cold:
257 /* Turn on phy power saving */
258 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
259 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
260 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
261 else
262 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
263 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
264 udelay(100);
265
266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
268 else
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
274
275 /* switch power to VAUX */
276 if (vaux && state != PCI_D3cold)
277 sky2_write8(hw, B0_POWER_CTRL,
278 (PC_VAUX_ENA | PC_VCC_ENA |
279 PC_VAUX_ON | PC_VCC_OFF));
280 break;
281 default:
282 printk(KERN_ERR PFX "Unknown power state %d\n", state);
283 }
284
285 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
286 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
287 }
288
289 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
290 {
291 u16 reg;
292
293 /* disable all GMAC IRQ's */
294 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
295 /* disable PHY IRQs */
296 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
297
298 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
299 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
301 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302
303 reg = gma_read16(hw, port, GM_RX_CTRL);
304 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
305 gma_write16(hw, port, GM_RX_CTRL, reg);
306 }
307
308 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
309 {
310 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
311 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
312
313 if (sky2->autoneg == AUTONEG_ENABLE &&
314 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
315 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
316
317 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
318 PHY_M_EC_MAC_S_MSK);
319 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
320
321 if (hw->chip_id == CHIP_ID_YUKON_EC)
322 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
323 else
324 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
325
326 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
327 }
328
329 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
330 if (hw->copper) {
331 if (hw->chip_id == CHIP_ID_YUKON_FE) {
332 /* enable automatic crossover */
333 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
334 } else {
335 /* disable energy detect */
336 ctrl &= ~PHY_M_PC_EN_DET_MSK;
337
338 /* enable automatic crossover */
339 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
340
341 if (sky2->autoneg == AUTONEG_ENABLE &&
342 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
343 ctrl &= ~PHY_M_PC_DSC_MSK;
344 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
345 }
346 }
347 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348 } else {
349 /* workaround for deviation #4.88 (CRC errors) */
350 /* disable Automatic Crossover */
351
352 ctrl &= ~PHY_M_PC_MDIX_MSK;
353 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
354
355 if (hw->chip_id == CHIP_ID_YUKON_XL) {
356 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
358 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
359 ctrl &= ~PHY_M_MAC_MD_MSK;
360 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
361 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
362
363 /* select page 1 to access Fiber registers */
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
365 }
366 }
367
368 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
369 if (sky2->autoneg == AUTONEG_DISABLE)
370 ctrl &= ~PHY_CT_ANE;
371 else
372 ctrl |= PHY_CT_ANE;
373
374 ctrl |= PHY_CT_RESET;
375 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
376
377 ctrl = 0;
378 ct1000 = 0;
379 adv = PHY_AN_CSMA;
380
381 if (sky2->autoneg == AUTONEG_ENABLE) {
382 if (hw->copper) {
383 if (sky2->advertising & ADVERTISED_1000baseT_Full)
384 ct1000 |= PHY_M_1000C_AFD;
385 if (sky2->advertising & ADVERTISED_1000baseT_Half)
386 ct1000 |= PHY_M_1000C_AHD;
387 if (sky2->advertising & ADVERTISED_100baseT_Full)
388 adv |= PHY_M_AN_100_FD;
389 if (sky2->advertising & ADVERTISED_100baseT_Half)
390 adv |= PHY_M_AN_100_HD;
391 if (sky2->advertising & ADVERTISED_10baseT_Full)
392 adv |= PHY_M_AN_10_FD;
393 if (sky2->advertising & ADVERTISED_10baseT_Half)
394 adv |= PHY_M_AN_10_HD;
395 } else /* special defines for FIBER (88E1011S only) */
396 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
397
398 /* Set Flow-control capabilities */
399 if (sky2->tx_pause && sky2->rx_pause)
400 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
401 else if (sky2->rx_pause && !sky2->tx_pause)
402 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
403 else if (!sky2->rx_pause && sky2->tx_pause)
404 adv |= PHY_AN_PAUSE_ASYM; /* local */
405
406 /* Restart Auto-negotiation */
407 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
408 } else {
409 /* forced speed/duplex settings */
410 ct1000 = PHY_M_1000C_MSE;
411
412 if (sky2->duplex == DUPLEX_FULL)
413 ctrl |= PHY_CT_DUP_MD;
414
415 switch (sky2->speed) {
416 case SPEED_1000:
417 ctrl |= PHY_CT_SP1000;
418 break;
419 case SPEED_100:
420 ctrl |= PHY_CT_SP100;
421 break;
422 }
423
424 ctrl |= PHY_CT_RESET;
425 }
426
427 if (hw->chip_id != CHIP_ID_YUKON_FE)
428 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
429
430 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
431 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
432
433 /* Setup Phy LED's */
434 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
435 ledover = 0;
436
437 switch (hw->chip_id) {
438 case CHIP_ID_YUKON_FE:
439 /* on 88E3082 these bits are at 11..9 (shifted left) */
440 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
441
442 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
443
444 /* delete ACT LED control bits */
445 ctrl &= ~PHY_M_FELP_LED1_MSK;
446 /* change ACT LED control to blink mode */
447 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
448 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
449 break;
450
451 case CHIP_ID_YUKON_XL:
452 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
453
454 /* select page 3 to access LED control register */
455 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
456
457 /* set LED Function Control register */
458 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
459 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
460 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
461 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
462 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
463
464 /* set Polarity Control register */
465 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
466 (PHY_M_POLC_LS1_P_MIX(4) |
467 PHY_M_POLC_IS0_P_MIX(4) |
468 PHY_M_POLC_LOS_CTRL(2) |
469 PHY_M_POLC_INIT_CTRL(2) |
470 PHY_M_POLC_STA1_CTRL(2) |
471 PHY_M_POLC_STA0_CTRL(2)));
472
473 /* restore page register */
474 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
475 break;
476 case CHIP_ID_YUKON_EC_U:
477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
488
489 /* set Blink Rate in LED Timer Control Register */
490 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
491 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
492 /* restore page register */
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
494 break;
495
496 default:
497 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
498 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
499 /* turn off the Rx LED (LED_RX) */
500 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
501 }
502
503 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
504 /* apply fixes in PHY AFE */
505 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
507
508 /* increase differential signal amplitude in 10BASE-T */
509 gm_phy_write(hw, port, 0x18, 0xaa99);
510 gm_phy_write(hw, port, 0x17, 0x2011);
511
512 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
513 gm_phy_write(hw, port, 0x18, 0xa204);
514 gm_phy_write(hw, port, 0x17, 0x2002);
515
516 /* set page register to 0 */
517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
518 } else {
519 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
520
521 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
522 /* turn on 100 Mbps LED (LED_LINK100) */
523 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
524 }
525
526 if (ledover)
527 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
528
529 }
530 /* Enable phy interrupt on auto-negotiation complete (or link up) */
531 if (sky2->autoneg == AUTONEG_ENABLE)
532 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
533 else
534 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
535 }
536
537 /* Force a renegotiation */
538 static void sky2_phy_reinit(struct sky2_port *sky2)
539 {
540 spin_lock_bh(&sky2->phy_lock);
541 sky2_phy_init(sky2->hw, sky2->port);
542 spin_unlock_bh(&sky2->phy_lock);
543 }
544
545 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
546 {
547 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
548 u16 reg;
549 int i;
550 const u8 *addr = hw->dev[port]->dev_addr;
551
552 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
553 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
554
555 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
556
557 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
558 /* WA DEV_472 -- looks like crossed wires on port 2 */
559 /* clear GMAC 1 Control reset */
560 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
561 do {
562 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
563 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
564 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
565 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
566 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
567 }
568
569 if (sky2->autoneg == AUTONEG_DISABLE) {
570 reg = gma_read16(hw, port, GM_GP_CTRL);
571 reg |= GM_GPCR_AU_ALL_DIS;
572 gma_write16(hw, port, GM_GP_CTRL, reg);
573 gma_read16(hw, port, GM_GP_CTRL);
574
575 switch (sky2->speed) {
576 case SPEED_1000:
577 reg &= ~GM_GPCR_SPEED_100;
578 reg |= GM_GPCR_SPEED_1000;
579 break;
580 case SPEED_100:
581 reg &= ~GM_GPCR_SPEED_1000;
582 reg |= GM_GPCR_SPEED_100;
583 break;
584 case SPEED_10:
585 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
586 break;
587 }
588
589 if (sky2->duplex == DUPLEX_FULL)
590 reg |= GM_GPCR_DUP_FULL;
591
592 /* turn off pause in 10/100mbps half duplex */
593 else if (sky2->speed != SPEED_1000 &&
594 hw->chip_id != CHIP_ID_YUKON_EC_U)
595 sky2->tx_pause = sky2->rx_pause = 0;
596 } else
597 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
598
599 if (!sky2->tx_pause && !sky2->rx_pause) {
600 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
601 reg |=
602 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
603 } else if (sky2->tx_pause && !sky2->rx_pause) {
604 /* disable Rx flow-control */
605 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
606 }
607
608 gma_write16(hw, port, GM_GP_CTRL, reg);
609
610 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
611
612 spin_lock_bh(&sky2->phy_lock);
613 sky2_phy_init(hw, port);
614 spin_unlock_bh(&sky2->phy_lock);
615
616 /* MIB clear */
617 reg = gma_read16(hw, port, GM_PHY_ADDR);
618 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
619
620 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
621 gma_read16(hw, port, i);
622 gma_write16(hw, port, GM_PHY_ADDR, reg);
623
624 /* transmit control */
625 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
626
627 /* receive control reg: unicast + multicast + no FCS */
628 gma_write16(hw, port, GM_RX_CTRL,
629 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
630
631 /* transmit flow control */
632 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
633
634 /* transmit parameter */
635 gma_write16(hw, port, GM_TX_PARAM,
636 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
637 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
638 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
639 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
640
641 /* serial mode register */
642 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
643 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
644
645 if (hw->dev[port]->mtu > ETH_DATA_LEN)
646 reg |= GM_SMOD_JUMBO_ENA;
647
648 gma_write16(hw, port, GM_SERIAL_MODE, reg);
649
650 /* virtual address for data */
651 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
652
653 /* physical address: used for pause frames */
654 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
655
656 /* ignore counter overflows */
657 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
658 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
659 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
660
661 /* Configure Rx MAC FIFO */
662 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
663 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
664 GMF_OPER_ON | GMF_RX_F_FL_ON);
665
666 /* Flush Rx MAC FIFO on any flow control or error */
667 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
668
669 /* Set threshold to 0xa (64 bytes)
670 * ASF disabled so no need to do WA dev #4.30
671 */
672 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
673
674 /* Configure Tx MAC FIFO */
675 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
676 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
677
678 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
679 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
680 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
681 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
682 /* set Tx GMAC FIFO Almost Empty Threshold */
683 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
684 /* Disable Store & Forward mode for TX */
685 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
686 }
687 }
688
689 }
690
691 /* Assign Ram Buffer allocation.
692 * start and end are in units of 4k bytes
693 * ram registers are in units of 64bit words
694 */
695 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
696 {
697 u32 start, end;
698
699 start = startk * 4096/8;
700 end = (endk * 4096/8) - 1;
701
702 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
703 sky2_write32(hw, RB_ADDR(q, RB_START), start);
704 sky2_write32(hw, RB_ADDR(q, RB_END), end);
705 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
706 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
707
708 if (q == Q_R1 || q == Q_R2) {
709 u32 space = (endk - startk) * 4096/8;
710 u32 tp = space - space/4;
711
712 /* On receive queue's set the thresholds
713 * give receiver priority when > 3/4 full
714 * send pause when down to 2K
715 */
716 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
717 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
718
719 tp = space - 2048/8;
720 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
721 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
722 } else {
723 /* Enable store & forward on Tx queue's because
724 * Tx FIFO is only 1K on Yukon
725 */
726 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
727 }
728
729 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
730 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
731 }
732
733 /* Setup Bus Memory Interface */
734 static void sky2_qset(struct sky2_hw *hw, u16 q)
735 {
736 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
737 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
738 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
739 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
740 }
741
742 /* Setup prefetch unit registers. This is the interface between
743 * hardware and driver list elements
744 */
745 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
746 u64 addr, u32 last)
747 {
748 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
749 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
750 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
751 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
752 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
753 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
754
755 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
756 }
757
758 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
759 {
760 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
761
762 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
763 return le;
764 }
765
766 /* Update chip's next pointer */
767 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
768 {
769 wmb();
770 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
771 mmiowb();
772 }
773
774
775 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
776 {
777 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
778 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
779 return le;
780 }
781
782 /* Return high part of DMA address (could be 32 or 64 bit) */
783 static inline u32 high32(dma_addr_t a)
784 {
785 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
786 }
787
788 /* Build description to hardware about buffer */
789 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
790 {
791 struct sky2_rx_le *le;
792 u32 hi = high32(map);
793 u16 len = sky2->rx_bufsize;
794
795 if (sky2->rx_addr64 != hi) {
796 le = sky2_next_rx(sky2);
797 le->addr = cpu_to_le32(hi);
798 le->ctrl = 0;
799 le->opcode = OP_ADDR64 | HW_OWNER;
800 sky2->rx_addr64 = high32(map + len);
801 }
802
803 le = sky2_next_rx(sky2);
804 le->addr = cpu_to_le32((u32) map);
805 le->length = cpu_to_le16(len);
806 le->ctrl = 0;
807 le->opcode = OP_PACKET | HW_OWNER;
808 }
809
810
811 /* Tell chip where to start receive checksum.
812 * Actually has two checksums, but set both same to avoid possible byte
813 * order problems.
814 */
815 static void rx_set_checksum(struct sky2_port *sky2)
816 {
817 struct sky2_rx_le *le;
818
819 le = sky2_next_rx(sky2);
820 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
821 le->ctrl = 0;
822 le->opcode = OP_TCPSTART | HW_OWNER;
823
824 sky2_write32(sky2->hw,
825 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
826 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
827
828 }
829
830 /*
831 * The RX Stop command will not work for Yukon-2 if the BMU does not
832 * reach the end of packet and since we can't make sure that we have
833 * incoming data, we must reset the BMU while it is not doing a DMA
834 * transfer. Since it is possible that the RX path is still active,
835 * the RX RAM buffer will be stopped first, so any possible incoming
836 * data will not trigger a DMA. After the RAM buffer is stopped, the
837 * BMU is polled until any DMA in progress is ended and only then it
838 * will be reset.
839 */
840 static void sky2_rx_stop(struct sky2_port *sky2)
841 {
842 struct sky2_hw *hw = sky2->hw;
843 unsigned rxq = rxqaddr[sky2->port];
844 int i;
845
846 /* disable the RAM Buffer receive queue */
847 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
848
849 for (i = 0; i < 0xffff; i++)
850 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
851 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
852 goto stopped;
853
854 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
855 sky2->netdev->name);
856 stopped:
857 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
858
859 /* reset the Rx prefetch unit */
860 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
861 }
862
863 /* Clean out receive buffer area, assumes receiver hardware stopped */
864 static void sky2_rx_clean(struct sky2_port *sky2)
865 {
866 unsigned i;
867
868 memset(sky2->rx_le, 0, RX_LE_BYTES);
869 for (i = 0; i < sky2->rx_pending; i++) {
870 struct ring_info *re = sky2->rx_ring + i;
871
872 if (re->skb) {
873 pci_unmap_single(sky2->hw->pdev,
874 re->mapaddr, sky2->rx_bufsize,
875 PCI_DMA_FROMDEVICE);
876 kfree_skb(re->skb);
877 re->skb = NULL;
878 }
879 }
880 }
881
882 /* Basic MII support */
883 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
884 {
885 struct mii_ioctl_data *data = if_mii(ifr);
886 struct sky2_port *sky2 = netdev_priv(dev);
887 struct sky2_hw *hw = sky2->hw;
888 int err = -EOPNOTSUPP;
889
890 if (!netif_running(dev))
891 return -ENODEV; /* Phy still in reset */
892
893 switch (cmd) {
894 case SIOCGMIIPHY:
895 data->phy_id = PHY_ADDR_MARV;
896
897 /* fallthru */
898 case SIOCGMIIREG: {
899 u16 val = 0;
900
901 spin_lock_bh(&sky2->phy_lock);
902 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
903 spin_unlock_bh(&sky2->phy_lock);
904
905 data->val_out = val;
906 break;
907 }
908
909 case SIOCSMIIREG:
910 if (!capable(CAP_NET_ADMIN))
911 return -EPERM;
912
913 spin_lock_bh(&sky2->phy_lock);
914 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
915 data->val_in);
916 spin_unlock_bh(&sky2->phy_lock);
917 break;
918 }
919 return err;
920 }
921
922 #ifdef SKY2_VLAN_TAG_USED
923 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
924 {
925 struct sky2_port *sky2 = netdev_priv(dev);
926 struct sky2_hw *hw = sky2->hw;
927 u16 port = sky2->port;
928
929 spin_lock_bh(&sky2->tx_lock);
930
931 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
932 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
933 sky2->vlgrp = grp;
934
935 spin_unlock_bh(&sky2->tx_lock);
936 }
937
938 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
939 {
940 struct sky2_port *sky2 = netdev_priv(dev);
941 struct sky2_hw *hw = sky2->hw;
942 u16 port = sky2->port;
943
944 spin_lock_bh(&sky2->tx_lock);
945
946 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
947 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
948 if (sky2->vlgrp)
949 sky2->vlgrp->vlan_devices[vid] = NULL;
950
951 spin_unlock_bh(&sky2->tx_lock);
952 }
953 #endif
954
955 /*
956 * It appears the hardware has a bug in the FIFO logic that
957 * cause it to hang if the FIFO gets overrun and the receive buffer
958 * is not aligned. ALso alloc_skb() won't align properly if slab
959 * debugging is enabled.
960 */
961 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
962 {
963 struct sk_buff *skb;
964
965 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
966 if (likely(skb)) {
967 unsigned long p = (unsigned long) skb->data;
968 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
969 }
970
971 return skb;
972 }
973
974 /*
975 * Allocate and setup receiver buffer pool.
976 * In case of 64 bit dma, there are 2X as many list elements
977 * available as ring entries
978 * and need to reserve one list element so we don't wrap around.
979 */
980 static int sky2_rx_start(struct sky2_port *sky2)
981 {
982 struct sky2_hw *hw = sky2->hw;
983 unsigned rxq = rxqaddr[sky2->port];
984 int i;
985 unsigned thresh;
986
987 sky2->rx_put = sky2->rx_next = 0;
988 sky2_qset(hw, rxq);
989
990 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
991 /* MAC Rx RAM Read is controlled by hardware */
992 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
993 }
994
995 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
996
997 rx_set_checksum(sky2);
998 for (i = 0; i < sky2->rx_pending; i++) {
999 struct ring_info *re = sky2->rx_ring + i;
1000
1001 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
1002 if (!re->skb)
1003 goto nomem;
1004
1005 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
1006 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1007 sky2_rx_add(sky2, re->mapaddr);
1008 }
1009
1010
1011 /*
1012 * The receiver hangs if it receives frames larger than the
1013 * packet buffer. As a workaround, truncate oversize frames, but
1014 * the register is limited to 9 bits, so if you do frames > 2052
1015 * you better get the MTU right!
1016 */
1017 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1018 if (thresh > 0x1ff)
1019 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1020 else {
1021 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1022 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1023 }
1024
1025
1026 /* Tell chip about available buffers */
1027 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1028 return 0;
1029 nomem:
1030 sky2_rx_clean(sky2);
1031 return -ENOMEM;
1032 }
1033
1034 /* Bring up network interface. */
1035 static int sky2_up(struct net_device *dev)
1036 {
1037 struct sky2_port *sky2 = netdev_priv(dev);
1038 struct sky2_hw *hw = sky2->hw;
1039 unsigned port = sky2->port;
1040 u32 ramsize, rxspace, imask;
1041 int cap, err = -ENOMEM;
1042 struct net_device *otherdev = hw->dev[sky2->port^1];
1043
1044 /*
1045 * On dual port PCI-X card, there is an problem where status
1046 * can be received out of order due to split transactions
1047 */
1048 if (otherdev && netif_running(otherdev) &&
1049 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1050 struct sky2_port *osky2 = netdev_priv(otherdev);
1051 u16 cmd;
1052
1053 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1054 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1055 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1056
1057 sky2->rx_csum = 0;
1058 osky2->rx_csum = 0;
1059 }
1060
1061 if (netif_msg_ifup(sky2))
1062 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1063
1064 /* must be power of 2 */
1065 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1066 TX_RING_SIZE *
1067 sizeof(struct sky2_tx_le),
1068 &sky2->tx_le_map);
1069 if (!sky2->tx_le)
1070 goto err_out;
1071
1072 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1073 GFP_KERNEL);
1074 if (!sky2->tx_ring)
1075 goto err_out;
1076 sky2->tx_prod = sky2->tx_cons = 0;
1077
1078 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1079 &sky2->rx_le_map);
1080 if (!sky2->rx_le)
1081 goto err_out;
1082 memset(sky2->rx_le, 0, RX_LE_BYTES);
1083
1084 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1085 GFP_KERNEL);
1086 if (!sky2->rx_ring)
1087 goto err_out;
1088
1089 sky2_mac_init(hw, port);
1090
1091 /* Determine available ram buffer space (in 4K blocks).
1092 * Note: not sure about the FE setting below yet
1093 */
1094 if (hw->chip_id == CHIP_ID_YUKON_FE)
1095 ramsize = 4;
1096 else
1097 ramsize = sky2_read8(hw, B2_E_0);
1098
1099 /* Give transmitter one third (rounded up) */
1100 rxspace = ramsize - (ramsize + 2) / 3;
1101
1102 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1103 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1104
1105 /* Make sure SyncQ is disabled */
1106 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1107 RB_RST_SET);
1108
1109 sky2_qset(hw, txqaddr[port]);
1110
1111 /* Set almost empty threshold */
1112 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1113 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1114
1115 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1116 TX_RING_SIZE - 1);
1117
1118 err = sky2_rx_start(sky2);
1119 if (err)
1120 goto err_out;
1121
1122 /* Enable interrupts from phy/mac for port */
1123 imask = sky2_read32(hw, B0_IMSK);
1124 imask |= portirq_msk[port];
1125 sky2_write32(hw, B0_IMSK, imask);
1126
1127 return 0;
1128
1129 err_out:
1130 if (sky2->rx_le) {
1131 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1132 sky2->rx_le, sky2->rx_le_map);
1133 sky2->rx_le = NULL;
1134 }
1135 if (sky2->tx_le) {
1136 pci_free_consistent(hw->pdev,
1137 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1138 sky2->tx_le, sky2->tx_le_map);
1139 sky2->tx_le = NULL;
1140 }
1141 kfree(sky2->tx_ring);
1142 kfree(sky2->rx_ring);
1143
1144 sky2->tx_ring = NULL;
1145 sky2->rx_ring = NULL;
1146 return err;
1147 }
1148
1149 /* Modular subtraction in ring */
1150 static inline int tx_dist(unsigned tail, unsigned head)
1151 {
1152 return (head - tail) & (TX_RING_SIZE - 1);
1153 }
1154
1155 /* Number of list elements available for next tx */
1156 static inline int tx_avail(const struct sky2_port *sky2)
1157 {
1158 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1159 }
1160
1161 /* Estimate of number of transmit list elements required */
1162 static unsigned tx_le_req(const struct sk_buff *skb)
1163 {
1164 unsigned count;
1165
1166 count = sizeof(dma_addr_t) / sizeof(u32);
1167 count += skb_shinfo(skb)->nr_frags * count;
1168
1169 if (skb_is_gso(skb))
1170 ++count;
1171
1172 if (skb->ip_summed == CHECKSUM_HW)
1173 ++count;
1174
1175 return count;
1176 }
1177
1178 /*
1179 * Put one packet in ring for transmit.
1180 * A single packet can generate multiple list elements, and
1181 * the number of ring elements will probably be less than the number
1182 * of list elements used.
1183 *
1184 * No BH disabling for tx_lock here (like tg3)
1185 */
1186 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1187 {
1188 struct sky2_port *sky2 = netdev_priv(dev);
1189 struct sky2_hw *hw = sky2->hw;
1190 struct sky2_tx_le *le = NULL;
1191 struct tx_ring_info *re;
1192 unsigned i, len;
1193 int avail;
1194 dma_addr_t mapping;
1195 u32 addr64;
1196 u16 mss;
1197 u8 ctrl;
1198
1199 /* No BH disabling for tx_lock here. We are running in BH disabled
1200 * context and TX reclaim runs via poll inside of a software
1201 * interrupt, and no related locks in IRQ processing.
1202 */
1203 if (!spin_trylock(&sky2->tx_lock))
1204 return NETDEV_TX_LOCKED;
1205
1206 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1207 /* There is a known but harmless race with lockless tx
1208 * and netif_stop_queue.
1209 */
1210 if (!netif_queue_stopped(dev)) {
1211 netif_stop_queue(dev);
1212 if (net_ratelimit())
1213 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1214 dev->name);
1215 }
1216 spin_unlock(&sky2->tx_lock);
1217
1218 return NETDEV_TX_BUSY;
1219 }
1220
1221 if (unlikely(netif_msg_tx_queued(sky2)))
1222 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1223 dev->name, sky2->tx_prod, skb->len);
1224
1225 len = skb_headlen(skb);
1226 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1227 addr64 = high32(mapping);
1228
1229 re = sky2->tx_ring + sky2->tx_prod;
1230
1231 /* Send high bits if changed or crosses boundary */
1232 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1233 le = get_tx_le(sky2);
1234 le->tx.addr = cpu_to_le32(addr64);
1235 le->ctrl = 0;
1236 le->opcode = OP_ADDR64 | HW_OWNER;
1237 sky2->tx_addr64 = high32(mapping + len);
1238 }
1239
1240 /* Check for TCP Segmentation Offload */
1241 mss = skb_shinfo(skb)->gso_size;
1242 if (mss != 0) {
1243 /* just drop the packet if non-linear expansion fails */
1244 if (skb_header_cloned(skb) &&
1245 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1246 dev_kfree_skb(skb);
1247 goto out_unlock;
1248 }
1249
1250 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1251 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1252 mss += ETH_HLEN;
1253 }
1254
1255 if (mss != sky2->tx_last_mss) {
1256 le = get_tx_le(sky2);
1257 le->tx.tso.size = cpu_to_le16(mss);
1258 le->tx.tso.rsvd = 0;
1259 le->opcode = OP_LRGLEN | HW_OWNER;
1260 le->ctrl = 0;
1261 sky2->tx_last_mss = mss;
1262 }
1263
1264 ctrl = 0;
1265 #ifdef SKY2_VLAN_TAG_USED
1266 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1267 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1268 if (!le) {
1269 le = get_tx_le(sky2);
1270 le->tx.addr = 0;
1271 le->opcode = OP_VLAN|HW_OWNER;
1272 le->ctrl = 0;
1273 } else
1274 le->opcode |= OP_VLAN;
1275 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1276 ctrl |= INS_VLAN;
1277 }
1278 #endif
1279
1280 /* Handle TCP checksum offload */
1281 if (skb->ip_summed == CHECKSUM_HW) {
1282 u16 hdr = skb->h.raw - skb->data;
1283 u16 offset = hdr + skb->csum;
1284
1285 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1286 if (skb->nh.iph->protocol == IPPROTO_UDP)
1287 ctrl |= UDPTCP;
1288
1289 le = get_tx_le(sky2);
1290 le->tx.csum.start = cpu_to_le16(hdr);
1291 le->tx.csum.offset = cpu_to_le16(offset);
1292 le->length = 0; /* initial checksum value */
1293 le->ctrl = 1; /* one packet */
1294 le->opcode = OP_TCPLISW | HW_OWNER;
1295 }
1296
1297 le = get_tx_le(sky2);
1298 le->tx.addr = cpu_to_le32((u32) mapping);
1299 le->length = cpu_to_le16(len);
1300 le->ctrl = ctrl;
1301 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1302
1303 /* Record the transmit mapping info */
1304 re->skb = skb;
1305 pci_unmap_addr_set(re, mapaddr, mapping);
1306
1307 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1308 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1309 struct tx_ring_info *fre;
1310
1311 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1312 frag->size, PCI_DMA_TODEVICE);
1313 addr64 = high32(mapping);
1314 if (addr64 != sky2->tx_addr64) {
1315 le = get_tx_le(sky2);
1316 le->tx.addr = cpu_to_le32(addr64);
1317 le->ctrl = 0;
1318 le->opcode = OP_ADDR64 | HW_OWNER;
1319 sky2->tx_addr64 = addr64;
1320 }
1321
1322 le = get_tx_le(sky2);
1323 le->tx.addr = cpu_to_le32((u32) mapping);
1324 le->length = cpu_to_le16(frag->size);
1325 le->ctrl = ctrl;
1326 le->opcode = OP_BUFFER | HW_OWNER;
1327
1328 fre = sky2->tx_ring
1329 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
1330 pci_unmap_addr_set(fre, mapaddr, mapping);
1331 }
1332
1333 re->idx = sky2->tx_prod;
1334 le->ctrl |= EOP;
1335
1336 avail = tx_avail(sky2);
1337 if (mss != 0 || avail < TX_MIN_PENDING) {
1338 le->ctrl |= FRC_STAT;
1339 if (avail <= MAX_SKB_TX_LE)
1340 netif_stop_queue(dev);
1341 }
1342
1343 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1344
1345 out_unlock:
1346 spin_unlock(&sky2->tx_lock);
1347
1348 dev->trans_start = jiffies;
1349 return NETDEV_TX_OK;
1350 }
1351
1352 /*
1353 * Free ring elements from starting at tx_cons until "done"
1354 *
1355 * NB: the hardware will tell us about partial completion of multi-part
1356 * buffers; these are deferred until completion.
1357 */
1358 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1359 {
1360 struct net_device *dev = sky2->netdev;
1361 struct pci_dev *pdev = sky2->hw->pdev;
1362 u16 nxt, put;
1363 unsigned i;
1364
1365 BUG_ON(done >= TX_RING_SIZE);
1366
1367 if (unlikely(netif_msg_tx_done(sky2)))
1368 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1369 dev->name, done);
1370
1371 for (put = sky2->tx_cons; put != done; put = nxt) {
1372 struct tx_ring_info *re = sky2->tx_ring + put;
1373 struct sk_buff *skb = re->skb;
1374
1375 nxt = re->idx;
1376 BUG_ON(nxt >= TX_RING_SIZE);
1377 prefetch(sky2->tx_ring + nxt);
1378
1379 /* Check for partial status */
1380 if (tx_dist(put, done) < tx_dist(put, nxt))
1381 break;
1382
1383 skb = re->skb;
1384 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1385 skb_headlen(skb), PCI_DMA_TODEVICE);
1386
1387 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1388 struct tx_ring_info *fre;
1389 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
1390 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1391 skb_shinfo(skb)->frags[i].size,
1392 PCI_DMA_TODEVICE);
1393 }
1394
1395 dev_kfree_skb(skb);
1396 }
1397
1398 sky2->tx_cons = put;
1399 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1400 netif_wake_queue(dev);
1401 }
1402
1403 /* Cleanup all untransmitted buffers, assume transmitter not running */
1404 static void sky2_tx_clean(struct sky2_port *sky2)
1405 {
1406 spin_lock_bh(&sky2->tx_lock);
1407 sky2_tx_complete(sky2, sky2->tx_prod);
1408 spin_unlock_bh(&sky2->tx_lock);
1409 }
1410
1411 /* Network shutdown */
1412 static int sky2_down(struct net_device *dev)
1413 {
1414 struct sky2_port *sky2 = netdev_priv(dev);
1415 struct sky2_hw *hw = sky2->hw;
1416 unsigned port = sky2->port;
1417 u16 ctrl;
1418 u32 imask;
1419
1420 /* Never really got started! */
1421 if (!sky2->tx_le)
1422 return 0;
1423
1424 if (netif_msg_ifdown(sky2))
1425 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1426
1427 /* Stop more packets from being queued */
1428 netif_stop_queue(dev);
1429
1430 sky2_phy_reset(hw, port);
1431
1432 /* Stop transmitter */
1433 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1434 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1435
1436 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1437 RB_RST_SET | RB_DIS_OP_MD);
1438
1439 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1440 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1441 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1442
1443 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1444
1445 /* Workaround shared GMAC reset */
1446 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1447 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1449
1450 /* Disable Force Sync bit and Enable Alloc bit */
1451 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1452 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1453
1454 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1455 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1456 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1457
1458 /* Reset the PCI FIFO of the async Tx queue */
1459 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1460 BMU_RST_SET | BMU_FIFO_RST);
1461
1462 /* Reset the Tx prefetch units */
1463 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1464 PREF_UNIT_RST_SET);
1465
1466 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1467
1468 sky2_rx_stop(sky2);
1469
1470 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1471 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1472
1473 /* Disable port IRQ */
1474 imask = sky2_read32(hw, B0_IMSK);
1475 imask &= ~portirq_msk[port];
1476 sky2_write32(hw, B0_IMSK, imask);
1477
1478 /* turn off LED's */
1479 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1480
1481 synchronize_irq(hw->pdev->irq);
1482
1483 sky2_tx_clean(sky2);
1484 sky2_rx_clean(sky2);
1485
1486 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1487 sky2->rx_le, sky2->rx_le_map);
1488 kfree(sky2->rx_ring);
1489
1490 pci_free_consistent(hw->pdev,
1491 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1492 sky2->tx_le, sky2->tx_le_map);
1493 kfree(sky2->tx_ring);
1494
1495 sky2->tx_le = NULL;
1496 sky2->rx_le = NULL;
1497
1498 sky2->rx_ring = NULL;
1499 sky2->tx_ring = NULL;
1500
1501 return 0;
1502 }
1503
1504 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1505 {
1506 if (!hw->copper)
1507 return SPEED_1000;
1508
1509 if (hw->chip_id == CHIP_ID_YUKON_FE)
1510 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1511
1512 switch (aux & PHY_M_PS_SPEED_MSK) {
1513 case PHY_M_PS_SPEED_1000:
1514 return SPEED_1000;
1515 case PHY_M_PS_SPEED_100:
1516 return SPEED_100;
1517 default:
1518 return SPEED_10;
1519 }
1520 }
1521
1522 static void sky2_link_up(struct sky2_port *sky2)
1523 {
1524 struct sky2_hw *hw = sky2->hw;
1525 unsigned port = sky2->port;
1526 u16 reg;
1527
1528 /* Enable Transmit FIFO Underrun */
1529 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1530
1531 reg = gma_read16(hw, port, GM_GP_CTRL);
1532 if (sky2->autoneg == AUTONEG_DISABLE) {
1533 reg |= GM_GPCR_AU_ALL_DIS;
1534
1535 /* Is write/read necessary? Copied from sky2_mac_init */
1536 gma_write16(hw, port, GM_GP_CTRL, reg);
1537 gma_read16(hw, port, GM_GP_CTRL);
1538
1539 switch (sky2->speed) {
1540 case SPEED_1000:
1541 reg &= ~GM_GPCR_SPEED_100;
1542 reg |= GM_GPCR_SPEED_1000;
1543 break;
1544 case SPEED_100:
1545 reg &= ~GM_GPCR_SPEED_1000;
1546 reg |= GM_GPCR_SPEED_100;
1547 break;
1548 case SPEED_10:
1549 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1550 break;
1551 }
1552 } else
1553 reg &= ~GM_GPCR_AU_ALL_DIS;
1554
1555 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1556 reg |= GM_GPCR_DUP_FULL;
1557
1558 /* enable Rx/Tx */
1559 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1560 gma_write16(hw, port, GM_GP_CTRL, reg);
1561 gma_read16(hw, port, GM_GP_CTRL);
1562
1563 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1564
1565 netif_carrier_on(sky2->netdev);
1566 netif_wake_queue(sky2->netdev);
1567
1568 /* Turn on link LED */
1569 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1570 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1571
1572 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1573 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1574 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1575
1576 switch(sky2->speed) {
1577 case SPEED_10:
1578 led |= PHY_M_LEDC_INIT_CTRL(7);
1579 break;
1580
1581 case SPEED_100:
1582 led |= PHY_M_LEDC_STA1_CTRL(7);
1583 break;
1584
1585 case SPEED_1000:
1586 led |= PHY_M_LEDC_STA0_CTRL(7);
1587 break;
1588 }
1589
1590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1591 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1592 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1593 }
1594
1595 if (netif_msg_link(sky2))
1596 printk(KERN_INFO PFX
1597 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1598 sky2->netdev->name, sky2->speed,
1599 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1600 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1601 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1602 }
1603
1604 static void sky2_link_down(struct sky2_port *sky2)
1605 {
1606 struct sky2_hw *hw = sky2->hw;
1607 unsigned port = sky2->port;
1608 u16 reg;
1609
1610 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1611
1612 reg = gma_read16(hw, port, GM_GP_CTRL);
1613 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1614 gma_write16(hw, port, GM_GP_CTRL, reg);
1615 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1616
1617 if (sky2->rx_pause && !sky2->tx_pause) {
1618 /* restore Asymmetric Pause bit */
1619 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1620 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1621 | PHY_M_AN_ASP);
1622 }
1623
1624 netif_carrier_off(sky2->netdev);
1625 netif_stop_queue(sky2->netdev);
1626
1627 /* Turn on link LED */
1628 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1629
1630 if (netif_msg_link(sky2))
1631 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1632 sky2_phy_init(hw, port);
1633 }
1634
1635 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1636 {
1637 struct sky2_hw *hw = sky2->hw;
1638 unsigned port = sky2->port;
1639 u16 lpa;
1640
1641 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1642
1643 if (lpa & PHY_M_AN_RF) {
1644 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1645 return -1;
1646 }
1647
1648 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1649 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1650 printk(KERN_ERR PFX "%s: master/slave fault",
1651 sky2->netdev->name);
1652 return -1;
1653 }
1654
1655 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1656 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1657 sky2->netdev->name);
1658 return -1;
1659 }
1660
1661 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1662
1663 sky2->speed = sky2_phy_speed(hw, aux);
1664
1665 /* Pause bits are offset (9..8) */
1666 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1667 aux >>= 6;
1668
1669 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1670 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1671
1672 if ((sky2->tx_pause || sky2->rx_pause)
1673 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1674 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1675 else
1676 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1677
1678 return 0;
1679 }
1680
1681 /* Interrupt from PHY */
1682 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1683 {
1684 struct net_device *dev = hw->dev[port];
1685 struct sky2_port *sky2 = netdev_priv(dev);
1686 u16 istatus, phystat;
1687
1688 spin_lock(&sky2->phy_lock);
1689 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1690 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1691
1692 if (!netif_running(dev))
1693 goto out;
1694
1695 if (netif_msg_intr(sky2))
1696 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1697 sky2->netdev->name, istatus, phystat);
1698
1699 if (istatus & PHY_M_IS_AN_COMPL) {
1700 if (sky2_autoneg_done(sky2, phystat) == 0)
1701 sky2_link_up(sky2);
1702 goto out;
1703 }
1704
1705 if (istatus & PHY_M_IS_LSP_CHANGE)
1706 sky2->speed = sky2_phy_speed(hw, phystat);
1707
1708 if (istatus & PHY_M_IS_DUP_CHANGE)
1709 sky2->duplex =
1710 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1711
1712 if (istatus & PHY_M_IS_LST_CHANGE) {
1713 if (phystat & PHY_M_PS_LINK_UP)
1714 sky2_link_up(sky2);
1715 else
1716 sky2_link_down(sky2);
1717 }
1718 out:
1719 spin_unlock(&sky2->phy_lock);
1720 }
1721
1722
1723 /* Transmit timeout is only called if we are running, carries is up
1724 * and tx queue is full (stopped).
1725 */
1726 static void sky2_tx_timeout(struct net_device *dev)
1727 {
1728 struct sky2_port *sky2 = netdev_priv(dev);
1729 struct sky2_hw *hw = sky2->hw;
1730 unsigned txq = txqaddr[sky2->port];
1731 u16 report, done;
1732
1733 if (netif_msg_timer(sky2))
1734 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1735
1736 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1737 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1738
1739 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1740 dev->name,
1741 sky2->tx_cons, sky2->tx_prod, report, done);
1742
1743 if (report != done) {
1744 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1745
1746 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1747 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1748 } else if (report != sky2->tx_cons) {
1749 printk(KERN_INFO PFX "status report lost?\n");
1750
1751 spin_lock_bh(&sky2->tx_lock);
1752 sky2_tx_complete(sky2, report);
1753 spin_unlock_bh(&sky2->tx_lock);
1754 } else {
1755 printk(KERN_INFO PFX "hardware hung? flushing\n");
1756
1757 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1758 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1759
1760 sky2_tx_clean(sky2);
1761
1762 sky2_qset(hw, txq);
1763 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1764 }
1765 }
1766
1767
1768 /* Want receive buffer size to be multiple of 64 bits
1769 * and incl room for vlan and truncation
1770 */
1771 static inline unsigned sky2_buf_size(int mtu)
1772 {
1773 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1774 }
1775
1776 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1777 {
1778 struct sky2_port *sky2 = netdev_priv(dev);
1779 struct sky2_hw *hw = sky2->hw;
1780 int err;
1781 u16 ctl, mode;
1782 u32 imask;
1783
1784 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1785 return -EINVAL;
1786
1787 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1788 return -EINVAL;
1789
1790 if (!netif_running(dev)) {
1791 dev->mtu = new_mtu;
1792 return 0;
1793 }
1794
1795 imask = sky2_read32(hw, B0_IMSK);
1796 sky2_write32(hw, B0_IMSK, 0);
1797
1798 dev->trans_start = jiffies; /* prevent tx timeout */
1799 netif_stop_queue(dev);
1800 netif_poll_disable(hw->dev[0]);
1801
1802 synchronize_irq(hw->pdev->irq);
1803
1804 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1805 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1806 sky2_rx_stop(sky2);
1807 sky2_rx_clean(sky2);
1808
1809 dev->mtu = new_mtu;
1810 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1811 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1812 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1813
1814 if (dev->mtu > ETH_DATA_LEN)
1815 mode |= GM_SMOD_JUMBO_ENA;
1816
1817 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1818
1819 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1820
1821 err = sky2_rx_start(sky2);
1822 sky2_write32(hw, B0_IMSK, imask);
1823
1824 if (err)
1825 dev_close(dev);
1826 else {
1827 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1828
1829 netif_poll_enable(hw->dev[0]);
1830 netif_wake_queue(dev);
1831 }
1832
1833 return err;
1834 }
1835
1836 /*
1837 * Receive one packet.
1838 * For small packets or errors, just reuse existing skb.
1839 * For larger packets, get new buffer.
1840 */
1841 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1842 u16 length, u32 status)
1843 {
1844 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1845 struct sk_buff *skb = NULL;
1846
1847 if (unlikely(netif_msg_rx_status(sky2)))
1848 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1849 sky2->netdev->name, sky2->rx_next, status, length);
1850
1851 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1852 prefetch(sky2->rx_ring + sky2->rx_next);
1853
1854 if (status & GMR_FS_ANY_ERR)
1855 goto error;
1856
1857 if (!(status & GMR_FS_RX_OK))
1858 goto resubmit;
1859
1860 if (length > sky2->netdev->mtu + ETH_HLEN)
1861 goto oversize;
1862
1863 if (length < copybreak) {
1864 skb = alloc_skb(length + 2, GFP_ATOMIC);
1865 if (!skb)
1866 goto resubmit;
1867
1868 skb_reserve(skb, 2);
1869 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1870 length, PCI_DMA_FROMDEVICE);
1871 memcpy(skb->data, re->skb->data, length);
1872 skb->ip_summed = re->skb->ip_summed;
1873 skb->csum = re->skb->csum;
1874 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1875 length, PCI_DMA_FROMDEVICE);
1876 } else {
1877 struct sk_buff *nskb;
1878
1879 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1880 if (!nskb)
1881 goto resubmit;
1882
1883 skb = re->skb;
1884 re->skb = nskb;
1885 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1886 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1887 prefetch(skb->data);
1888
1889 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1890 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1891 }
1892
1893 skb_put(skb, length);
1894 resubmit:
1895 re->skb->ip_summed = CHECKSUM_NONE;
1896 sky2_rx_add(sky2, re->mapaddr);
1897
1898 return skb;
1899
1900 oversize:
1901 ++sky2->net_stats.rx_over_errors;
1902 goto resubmit;
1903
1904 error:
1905 ++sky2->net_stats.rx_errors;
1906
1907 if (netif_msg_rx_err(sky2) && net_ratelimit())
1908 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1909 sky2->netdev->name, status, length);
1910
1911 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1912 sky2->net_stats.rx_length_errors++;
1913 if (status & GMR_FS_FRAGMENT)
1914 sky2->net_stats.rx_frame_errors++;
1915 if (status & GMR_FS_CRC_ERR)
1916 sky2->net_stats.rx_crc_errors++;
1917 if (status & GMR_FS_RX_FF_OV)
1918 sky2->net_stats.rx_fifo_errors++;
1919
1920 goto resubmit;
1921 }
1922
1923 /* Transmit complete */
1924 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1925 {
1926 struct sky2_port *sky2 = netdev_priv(dev);
1927
1928 if (netif_running(dev)) {
1929 spin_lock(&sky2->tx_lock);
1930 sky2_tx_complete(sky2, last);
1931 spin_unlock(&sky2->tx_lock);
1932 }
1933 }
1934
1935 /* Is status ring empty or is there more to do? */
1936 static inline int sky2_more_work(const struct sky2_hw *hw)
1937 {
1938 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1939 }
1940
1941 /* Process status response ring */
1942 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1943 {
1944 struct sky2_port *sky2;
1945 int work_done = 0;
1946 unsigned buf_write[2] = { 0, 0 };
1947 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1948
1949 rmb();
1950
1951 while (hw->st_idx != hwidx) {
1952 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1953 struct net_device *dev;
1954 struct sk_buff *skb;
1955 u32 status;
1956 u16 length;
1957
1958 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1959
1960 BUG_ON(le->link >= 2);
1961 dev = hw->dev[le->link];
1962
1963 sky2 = netdev_priv(dev);
1964 length = le->length;
1965 status = le->status;
1966
1967 switch (le->opcode & ~HW_OWNER) {
1968 case OP_RXSTAT:
1969 skb = sky2_receive(sky2, length, status);
1970 if (!skb)
1971 break;
1972
1973 skb->dev = dev;
1974 skb->protocol = eth_type_trans(skb, dev);
1975 dev->last_rx = jiffies;
1976
1977 #ifdef SKY2_VLAN_TAG_USED
1978 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1979 vlan_hwaccel_receive_skb(skb,
1980 sky2->vlgrp,
1981 be16_to_cpu(sky2->rx_tag));
1982 } else
1983 #endif
1984 netif_receive_skb(skb);
1985
1986 /* Update receiver after 16 frames */
1987 if (++buf_write[le->link] == RX_BUF_WRITE) {
1988 sky2_put_idx(hw, rxqaddr[le->link],
1989 sky2->rx_put);
1990 buf_write[le->link] = 0;
1991 }
1992
1993 /* Stop after net poll weight */
1994 if (++work_done >= to_do)
1995 goto exit_loop;
1996 break;
1997
1998 #ifdef SKY2_VLAN_TAG_USED
1999 case OP_RXVLAN:
2000 sky2->rx_tag = length;
2001 break;
2002
2003 case OP_RXCHKSVLAN:
2004 sky2->rx_tag = length;
2005 /* fall through */
2006 #endif
2007 case OP_RXCHKS:
2008 skb = sky2->rx_ring[sky2->rx_next].skb;
2009 skb->ip_summed = CHECKSUM_HW;
2010 skb->csum = le16_to_cpu(status);
2011 break;
2012
2013 case OP_TXINDEXLE:
2014 /* TX index reports status for both ports */
2015 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2016 sky2_tx_done(hw->dev[0], status & 0xfff);
2017 if (hw->dev[1])
2018 sky2_tx_done(hw->dev[1],
2019 ((status >> 24) & 0xff)
2020 | (u16)(length & 0xf) << 8);
2021 break;
2022
2023 default:
2024 if (net_ratelimit())
2025 printk(KERN_WARNING PFX
2026 "unknown status opcode 0x%x\n", le->opcode);
2027 goto exit_loop;
2028 }
2029 }
2030
2031 exit_loop:
2032 if (buf_write[0]) {
2033 sky2 = netdev_priv(hw->dev[0]);
2034 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2035 }
2036
2037 if (buf_write[1]) {
2038 sky2 = netdev_priv(hw->dev[1]);
2039 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2040 }
2041
2042 return work_done;
2043 }
2044
2045 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2046 {
2047 struct net_device *dev = hw->dev[port];
2048
2049 if (net_ratelimit())
2050 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2051 dev->name, status);
2052
2053 if (status & Y2_IS_PAR_RD1) {
2054 if (net_ratelimit())
2055 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2056 dev->name);
2057 /* Clear IRQ */
2058 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2059 }
2060
2061 if (status & Y2_IS_PAR_WR1) {
2062 if (net_ratelimit())
2063 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2064 dev->name);
2065
2066 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2067 }
2068
2069 if (status & Y2_IS_PAR_MAC1) {
2070 if (net_ratelimit())
2071 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2072 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2073 }
2074
2075 if (status & Y2_IS_PAR_RX1) {
2076 if (net_ratelimit())
2077 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2078 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2079 }
2080
2081 if (status & Y2_IS_TCP_TXA1) {
2082 if (net_ratelimit())
2083 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2084 dev->name);
2085 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2086 }
2087 }
2088
2089 static void sky2_hw_intr(struct sky2_hw *hw)
2090 {
2091 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2092
2093 if (status & Y2_IS_TIST_OV)
2094 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2095
2096 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2097 u16 pci_err;
2098
2099 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2100 if (net_ratelimit())
2101 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2102 pci_name(hw->pdev), pci_err);
2103
2104 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2105 sky2_pci_write16(hw, PCI_STATUS,
2106 pci_err | PCI_STATUS_ERROR_BITS);
2107 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2108 }
2109
2110 if (status & Y2_IS_PCI_EXP) {
2111 /* PCI-Express uncorrectable Error occurred */
2112 u32 pex_err;
2113
2114 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2115
2116 if (net_ratelimit())
2117 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2118 pci_name(hw->pdev), pex_err);
2119
2120 /* clear the interrupt */
2121 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2122 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2123 0xffffffffUL);
2124 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2125
2126 if (pex_err & PEX_FATAL_ERRORS) {
2127 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2128 hwmsk &= ~Y2_IS_PCI_EXP;
2129 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2130 }
2131 }
2132
2133 if (status & Y2_HWE_L1_MASK)
2134 sky2_hw_error(hw, 0, status);
2135 status >>= 8;
2136 if (status & Y2_HWE_L1_MASK)
2137 sky2_hw_error(hw, 1, status);
2138 }
2139
2140 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2141 {
2142 struct net_device *dev = hw->dev[port];
2143 struct sky2_port *sky2 = netdev_priv(dev);
2144 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2145
2146 if (netif_msg_intr(sky2))
2147 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2148 dev->name, status);
2149
2150 if (status & GM_IS_RX_FF_OR) {
2151 ++sky2->net_stats.rx_fifo_errors;
2152 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2153 }
2154
2155 if (status & GM_IS_TX_FF_UR) {
2156 ++sky2->net_stats.tx_fifo_errors;
2157 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2158 }
2159 }
2160
2161 /* This should never happen it is a fatal situation */
2162 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2163 const char *rxtx, u32 mask)
2164 {
2165 struct net_device *dev = hw->dev[port];
2166 struct sky2_port *sky2 = netdev_priv(dev);
2167 u32 imask;
2168
2169 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2170 dev ? dev->name : "<not registered>", rxtx);
2171
2172 imask = sky2_read32(hw, B0_IMSK);
2173 imask &= ~mask;
2174 sky2_write32(hw, B0_IMSK, imask);
2175
2176 if (dev) {
2177 spin_lock(&sky2->phy_lock);
2178 sky2_link_down(sky2);
2179 spin_unlock(&sky2->phy_lock);
2180 }
2181 }
2182
2183 /* If idle then force a fake soft NAPI poll once a second
2184 * to work around cases where sharing an edge triggered interrupt.
2185 */
2186 static inline void sky2_idle_start(struct sky2_hw *hw)
2187 {
2188 if (idle_timeout > 0)
2189 mod_timer(&hw->idle_timer,
2190 jiffies + msecs_to_jiffies(idle_timeout));
2191 }
2192
2193 static void sky2_idle(unsigned long arg)
2194 {
2195 struct sky2_hw *hw = (struct sky2_hw *) arg;
2196 struct net_device *dev = hw->dev[0];
2197
2198 if (__netif_rx_schedule_prep(dev))
2199 __netif_rx_schedule(dev);
2200
2201 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2202 }
2203
2204
2205 static int sky2_poll(struct net_device *dev0, int *budget)
2206 {
2207 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2208 int work_limit = min(dev0->quota, *budget);
2209 int work_done = 0;
2210 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2211
2212 if (status & Y2_IS_HW_ERR)
2213 sky2_hw_intr(hw);
2214
2215 if (status & Y2_IS_IRQ_PHY1)
2216 sky2_phy_intr(hw, 0);
2217
2218 if (status & Y2_IS_IRQ_PHY2)
2219 sky2_phy_intr(hw, 1);
2220
2221 if (status & Y2_IS_IRQ_MAC1)
2222 sky2_mac_intr(hw, 0);
2223
2224 if (status & Y2_IS_IRQ_MAC2)
2225 sky2_mac_intr(hw, 1);
2226
2227 if (status & Y2_IS_CHK_RX1)
2228 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2229
2230 if (status & Y2_IS_CHK_RX2)
2231 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2232
2233 if (status & Y2_IS_CHK_TXA1)
2234 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2235
2236 if (status & Y2_IS_CHK_TXA2)
2237 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2238
2239 work_done = sky2_status_intr(hw, work_limit);
2240 *budget -= work_done;
2241 dev0->quota -= work_done;
2242
2243 if (status & Y2_IS_STAT_BMU)
2244 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2245
2246 if (sky2_more_work(hw))
2247 return 1;
2248
2249 netif_rx_complete(dev0);
2250
2251 sky2_read32(hw, B0_Y2_SP_LISR);
2252 return 0;
2253 }
2254
2255 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2256 {
2257 struct sky2_hw *hw = dev_id;
2258 struct net_device *dev0 = hw->dev[0];
2259 u32 status;
2260
2261 /* Reading this mask interrupts as side effect */
2262 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2263 if (status == 0 || status == ~0)
2264 return IRQ_NONE;
2265
2266 prefetch(&hw->st_le[hw->st_idx]);
2267 if (likely(__netif_rx_schedule_prep(dev0)))
2268 __netif_rx_schedule(dev0);
2269
2270 return IRQ_HANDLED;
2271 }
2272
2273 #ifdef CONFIG_NET_POLL_CONTROLLER
2274 static void sky2_netpoll(struct net_device *dev)
2275 {
2276 struct sky2_port *sky2 = netdev_priv(dev);
2277 struct net_device *dev0 = sky2->hw->dev[0];
2278
2279 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2280 __netif_rx_schedule(dev0);
2281 }
2282 #endif
2283
2284 /* Chip internal frequency for clock calculations */
2285 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2286 {
2287 switch (hw->chip_id) {
2288 case CHIP_ID_YUKON_EC:
2289 case CHIP_ID_YUKON_EC_U:
2290 return 125; /* 125 Mhz */
2291 case CHIP_ID_YUKON_FE:
2292 return 100; /* 100 Mhz */
2293 default: /* YUKON_XL */
2294 return 156; /* 156 Mhz */
2295 }
2296 }
2297
2298 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2299 {
2300 return sky2_mhz(hw) * us;
2301 }
2302
2303 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2304 {
2305 return clk / sky2_mhz(hw);
2306 }
2307
2308
2309 static int sky2_reset(struct sky2_hw *hw)
2310 {
2311 u16 status;
2312 u8 t8, pmd_type;
2313 int i;
2314
2315 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2316
2317 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2318 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2319 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2320 pci_name(hw->pdev), hw->chip_id);
2321 return -EOPNOTSUPP;
2322 }
2323
2324 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2325
2326 /* This rev is really old, and requires untested workarounds */
2327 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2328 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2329 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2330 hw->chip_id, hw->chip_rev);
2331 return -EOPNOTSUPP;
2332 }
2333
2334 /* disable ASF */
2335 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2336 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2337 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2338 }
2339
2340 /* do a SW reset */
2341 sky2_write8(hw, B0_CTST, CS_RST_SET);
2342 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2343
2344 /* clear PCI errors, if any */
2345 status = sky2_pci_read16(hw, PCI_STATUS);
2346
2347 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2348 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2349
2350
2351 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2352
2353 /* clear any PEX errors */
2354 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2355 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2356
2357
2358 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2359 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2360
2361 hw->ports = 1;
2362 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2363 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2364 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2365 ++hw->ports;
2366 }
2367
2368 sky2_set_power_state(hw, PCI_D0);
2369
2370 for (i = 0; i < hw->ports; i++) {
2371 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2372 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2373 }
2374
2375 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2376
2377 /* Clear I2C IRQ noise */
2378 sky2_write32(hw, B2_I2C_IRQ, 1);
2379
2380 /* turn off hardware timer (unused) */
2381 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2382 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2383
2384 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2385
2386 /* Turn off descriptor polling */
2387 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2388
2389 /* Turn off receive timestamp */
2390 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2391 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2392
2393 /* enable the Tx Arbiters */
2394 for (i = 0; i < hw->ports; i++)
2395 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2396
2397 /* Initialize ram interface */
2398 for (i = 0; i < hw->ports; i++) {
2399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2400
2401 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2402 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2404 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2407 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2408 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2409 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2410 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2411 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2412 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2413 }
2414
2415 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2416
2417 for (i = 0; i < hw->ports; i++)
2418 sky2_phy_reset(hw, i);
2419
2420 memset(hw->st_le, 0, STATUS_LE_BYTES);
2421 hw->st_idx = 0;
2422
2423 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2424 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2425
2426 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2427 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2428
2429 /* Set the list last index */
2430 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2431
2432 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2433 sky2_write8(hw, STAT_FIFO_WM, 16);
2434
2435 /* set Status-FIFO ISR watermark */
2436 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2437 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2438 else
2439 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2440
2441 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2442 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2443 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2444
2445 /* enable status unit */
2446 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2447
2448 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2449 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2450 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2451
2452 return 0;
2453 }
2454
2455 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2456 {
2457 u32 modes;
2458 if (hw->copper) {
2459 modes = SUPPORTED_10baseT_Half
2460 | SUPPORTED_10baseT_Full
2461 | SUPPORTED_100baseT_Half
2462 | SUPPORTED_100baseT_Full
2463 | SUPPORTED_Autoneg | SUPPORTED_TP;
2464
2465 if (hw->chip_id != CHIP_ID_YUKON_FE)
2466 modes |= SUPPORTED_1000baseT_Half
2467 | SUPPORTED_1000baseT_Full;
2468 } else
2469 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2470 | SUPPORTED_Autoneg;
2471 return modes;
2472 }
2473
2474 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2475 {
2476 struct sky2_port *sky2 = netdev_priv(dev);
2477 struct sky2_hw *hw = sky2->hw;
2478
2479 ecmd->transceiver = XCVR_INTERNAL;
2480 ecmd->supported = sky2_supported_modes(hw);
2481 ecmd->phy_address = PHY_ADDR_MARV;
2482 if (hw->copper) {
2483 ecmd->supported = SUPPORTED_10baseT_Half
2484 | SUPPORTED_10baseT_Full
2485 | SUPPORTED_100baseT_Half
2486 | SUPPORTED_100baseT_Full
2487 | SUPPORTED_1000baseT_Half
2488 | SUPPORTED_1000baseT_Full
2489 | SUPPORTED_Autoneg | SUPPORTED_TP;
2490 ecmd->port = PORT_TP;
2491 } else
2492 ecmd->port = PORT_FIBRE;
2493
2494 ecmd->advertising = sky2->advertising;
2495 ecmd->autoneg = sky2->autoneg;
2496 ecmd->speed = sky2->speed;
2497 ecmd->duplex = sky2->duplex;
2498 return 0;
2499 }
2500
2501 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2502 {
2503 struct sky2_port *sky2 = netdev_priv(dev);
2504 const struct sky2_hw *hw = sky2->hw;
2505 u32 supported = sky2_supported_modes(hw);
2506
2507 if (ecmd->autoneg == AUTONEG_ENABLE) {
2508 ecmd->advertising = supported;
2509 sky2->duplex = -1;
2510 sky2->speed = -1;
2511 } else {
2512 u32 setting;
2513
2514 switch (ecmd->speed) {
2515 case SPEED_1000:
2516 if (ecmd->duplex == DUPLEX_FULL)
2517 setting = SUPPORTED_1000baseT_Full;
2518 else if (ecmd->duplex == DUPLEX_HALF)
2519 setting = SUPPORTED_1000baseT_Half;
2520 else
2521 return -EINVAL;
2522 break;
2523 case SPEED_100:
2524 if (ecmd->duplex == DUPLEX_FULL)
2525 setting = SUPPORTED_100baseT_Full;
2526 else if (ecmd->duplex == DUPLEX_HALF)
2527 setting = SUPPORTED_100baseT_Half;
2528 else
2529 return -EINVAL;
2530 break;
2531
2532 case SPEED_10:
2533 if (ecmd->duplex == DUPLEX_FULL)
2534 setting = SUPPORTED_10baseT_Full;
2535 else if (ecmd->duplex == DUPLEX_HALF)
2536 setting = SUPPORTED_10baseT_Half;
2537 else
2538 return -EINVAL;
2539 break;
2540 default:
2541 return -EINVAL;
2542 }
2543
2544 if ((setting & supported) == 0)
2545 return -EINVAL;
2546
2547 sky2->speed = ecmd->speed;
2548 sky2->duplex = ecmd->duplex;
2549 }
2550
2551 sky2->autoneg = ecmd->autoneg;
2552 sky2->advertising = ecmd->advertising;
2553
2554 if (netif_running(dev))
2555 sky2_phy_reinit(sky2);
2556
2557 return 0;
2558 }
2559
2560 static void sky2_get_drvinfo(struct net_device *dev,
2561 struct ethtool_drvinfo *info)
2562 {
2563 struct sky2_port *sky2 = netdev_priv(dev);
2564
2565 strcpy(info->driver, DRV_NAME);
2566 strcpy(info->version, DRV_VERSION);
2567 strcpy(info->fw_version, "N/A");
2568 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2569 }
2570
2571 static const struct sky2_stat {
2572 char name[ETH_GSTRING_LEN];
2573 u16 offset;
2574 } sky2_stats[] = {
2575 { "tx_bytes", GM_TXO_OK_HI },
2576 { "rx_bytes", GM_RXO_OK_HI },
2577 { "tx_broadcast", GM_TXF_BC_OK },
2578 { "rx_broadcast", GM_RXF_BC_OK },
2579 { "tx_multicast", GM_TXF_MC_OK },
2580 { "rx_multicast", GM_RXF_MC_OK },
2581 { "tx_unicast", GM_TXF_UC_OK },
2582 { "rx_unicast", GM_RXF_UC_OK },
2583 { "tx_mac_pause", GM_TXF_MPAUSE },
2584 { "rx_mac_pause", GM_RXF_MPAUSE },
2585 { "collisions", GM_TXF_COL },
2586 { "late_collision",GM_TXF_LAT_COL },
2587 { "aborted", GM_TXF_ABO_COL },
2588 { "single_collisions", GM_TXF_SNG_COL },
2589 { "multi_collisions", GM_TXF_MUL_COL },
2590
2591 { "rx_short", GM_RXF_SHT },
2592 { "rx_runt", GM_RXE_FRAG },
2593 { "rx_64_byte_packets", GM_RXF_64B },
2594 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2595 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2596 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2597 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2598 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2599 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2600 { "rx_too_long", GM_RXF_LNG_ERR },
2601 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2602 { "rx_jabber", GM_RXF_JAB_PKT },
2603 { "rx_fcs_error", GM_RXF_FCS_ERR },
2604
2605 { "tx_64_byte_packets", GM_TXF_64B },
2606 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2607 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2608 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2609 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2610 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2611 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2612 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2613 };
2614
2615 static u32 sky2_get_rx_csum(struct net_device *dev)
2616 {
2617 struct sky2_port *sky2 = netdev_priv(dev);
2618
2619 return sky2->rx_csum;
2620 }
2621
2622 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2623 {
2624 struct sky2_port *sky2 = netdev_priv(dev);
2625
2626 sky2->rx_csum = data;
2627
2628 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2629 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2630
2631 return 0;
2632 }
2633
2634 static u32 sky2_get_msglevel(struct net_device *netdev)
2635 {
2636 struct sky2_port *sky2 = netdev_priv(netdev);
2637 return sky2->msg_enable;
2638 }
2639
2640 static int sky2_nway_reset(struct net_device *dev)
2641 {
2642 struct sky2_port *sky2 = netdev_priv(dev);
2643
2644 if (sky2->autoneg != AUTONEG_ENABLE)
2645 return -EINVAL;
2646
2647 sky2_phy_reinit(sky2);
2648
2649 return 0;
2650 }
2651
2652 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2653 {
2654 struct sky2_hw *hw = sky2->hw;
2655 unsigned port = sky2->port;
2656 int i;
2657
2658 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2659 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2660 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2661 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2662
2663 for (i = 2; i < count; i++)
2664 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2665 }
2666
2667 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2668 {
2669 struct sky2_port *sky2 = netdev_priv(netdev);
2670 sky2->msg_enable = value;
2671 }
2672
2673 static int sky2_get_stats_count(struct net_device *dev)
2674 {
2675 return ARRAY_SIZE(sky2_stats);
2676 }
2677
2678 static void sky2_get_ethtool_stats(struct net_device *dev,
2679 struct ethtool_stats *stats, u64 * data)
2680 {
2681 struct sky2_port *sky2 = netdev_priv(dev);
2682
2683 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2684 }
2685
2686 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2687 {
2688 int i;
2689
2690 switch (stringset) {
2691 case ETH_SS_STATS:
2692 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2693 memcpy(data + i * ETH_GSTRING_LEN,
2694 sky2_stats[i].name, ETH_GSTRING_LEN);
2695 break;
2696 }
2697 }
2698
2699 /* Use hardware MIB variables for critical path statistics and
2700 * transmit feedback not reported at interrupt.
2701 * Other errors are accounted for in interrupt handler.
2702 */
2703 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2704 {
2705 struct sky2_port *sky2 = netdev_priv(dev);
2706 u64 data[13];
2707
2708 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2709
2710 sky2->net_stats.tx_bytes = data[0];
2711 sky2->net_stats.rx_bytes = data[1];
2712 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2713 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2714 sky2->net_stats.multicast = data[3] + data[5];
2715 sky2->net_stats.collisions = data[10];
2716 sky2->net_stats.tx_aborted_errors = data[12];
2717
2718 return &sky2->net_stats;
2719 }
2720
2721 static int sky2_set_mac_address(struct net_device *dev, void *p)
2722 {
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724 struct sky2_hw *hw = sky2->hw;
2725 unsigned port = sky2->port;
2726 const struct sockaddr *addr = p;
2727
2728 if (!is_valid_ether_addr(addr->sa_data))
2729 return -EADDRNOTAVAIL;
2730
2731 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2732 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2733 dev->dev_addr, ETH_ALEN);
2734 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2735 dev->dev_addr, ETH_ALEN);
2736
2737 /* virtual address for data */
2738 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2739
2740 /* physical address: used for pause frames */
2741 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2742
2743 return 0;
2744 }
2745
2746 static void sky2_set_multicast(struct net_device *dev)
2747 {
2748 struct sky2_port *sky2 = netdev_priv(dev);
2749 struct sky2_hw *hw = sky2->hw;
2750 unsigned port = sky2->port;
2751 struct dev_mc_list *list = dev->mc_list;
2752 u16 reg;
2753 u8 filter[8];
2754
2755 memset(filter, 0, sizeof(filter));
2756
2757 reg = gma_read16(hw, port, GM_RX_CTRL);
2758 reg |= GM_RXCR_UCF_ENA;
2759
2760 if (dev->flags & IFF_PROMISC) /* promiscuous */
2761 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2762 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2763 memset(filter, 0xff, sizeof(filter));
2764 else if (dev->mc_count == 0) /* no multicast */
2765 reg &= ~GM_RXCR_MCF_ENA;
2766 else {
2767 int i;
2768 reg |= GM_RXCR_MCF_ENA;
2769
2770 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2771 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2772 filter[bit / 8] |= 1 << (bit % 8);
2773 }
2774 }
2775
2776 gma_write16(hw, port, GM_MC_ADDR_H1,
2777 (u16) filter[0] | ((u16) filter[1] << 8));
2778 gma_write16(hw, port, GM_MC_ADDR_H2,
2779 (u16) filter[2] | ((u16) filter[3] << 8));
2780 gma_write16(hw, port, GM_MC_ADDR_H3,
2781 (u16) filter[4] | ((u16) filter[5] << 8));
2782 gma_write16(hw, port, GM_MC_ADDR_H4,
2783 (u16) filter[6] | ((u16) filter[7] << 8));
2784
2785 gma_write16(hw, port, GM_RX_CTRL, reg);
2786 }
2787
2788 /* Can have one global because blinking is controlled by
2789 * ethtool and that is always under RTNL mutex
2790 */
2791 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2792 {
2793 u16 pg;
2794
2795 switch (hw->chip_id) {
2796 case CHIP_ID_YUKON_XL:
2797 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2798 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2799 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2800 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2801 PHY_M_LEDC_INIT_CTRL(7) |
2802 PHY_M_LEDC_STA1_CTRL(7) |
2803 PHY_M_LEDC_STA0_CTRL(7))
2804 : 0);
2805
2806 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2807 break;
2808
2809 default:
2810 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2811 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2812 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2813 PHY_M_LED_MO_10(MO_LED_ON) |
2814 PHY_M_LED_MO_100(MO_LED_ON) |
2815 PHY_M_LED_MO_1000(MO_LED_ON) |
2816 PHY_M_LED_MO_RX(MO_LED_ON)
2817 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2818 PHY_M_LED_MO_10(MO_LED_OFF) |
2819 PHY_M_LED_MO_100(MO_LED_OFF) |
2820 PHY_M_LED_MO_1000(MO_LED_OFF) |
2821 PHY_M_LED_MO_RX(MO_LED_OFF));
2822
2823 }
2824 }
2825
2826 /* blink LED's for finding board */
2827 static int sky2_phys_id(struct net_device *dev, u32 data)
2828 {
2829 struct sky2_port *sky2 = netdev_priv(dev);
2830 struct sky2_hw *hw = sky2->hw;
2831 unsigned port = sky2->port;
2832 u16 ledctrl, ledover = 0;
2833 long ms;
2834 int interrupted;
2835 int onoff = 1;
2836
2837 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2838 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2839 else
2840 ms = data * 1000;
2841
2842 /* save initial values */
2843 spin_lock_bh(&sky2->phy_lock);
2844 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2845 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2846 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2847 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2848 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2849 } else {
2850 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2851 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2852 }
2853
2854 interrupted = 0;
2855 while (!interrupted && ms > 0) {
2856 sky2_led(hw, port, onoff);
2857 onoff = !onoff;
2858
2859 spin_unlock_bh(&sky2->phy_lock);
2860 interrupted = msleep_interruptible(250);
2861 spin_lock_bh(&sky2->phy_lock);
2862
2863 ms -= 250;
2864 }
2865
2866 /* resume regularly scheduled programming */
2867 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2868 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2869 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2870 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2871 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2872 } else {
2873 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2874 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2875 }
2876 spin_unlock_bh(&sky2->phy_lock);
2877
2878 return 0;
2879 }
2880
2881 static void sky2_get_pauseparam(struct net_device *dev,
2882 struct ethtool_pauseparam *ecmd)
2883 {
2884 struct sky2_port *sky2 = netdev_priv(dev);
2885
2886 ecmd->tx_pause = sky2->tx_pause;
2887 ecmd->rx_pause = sky2->rx_pause;
2888 ecmd->autoneg = sky2->autoneg;
2889 }
2890
2891 static int sky2_set_pauseparam(struct net_device *dev,
2892 struct ethtool_pauseparam *ecmd)
2893 {
2894 struct sky2_port *sky2 = netdev_priv(dev);
2895 int err = 0;
2896
2897 sky2->autoneg = ecmd->autoneg;
2898 sky2->tx_pause = ecmd->tx_pause != 0;
2899 sky2->rx_pause = ecmd->rx_pause != 0;
2900
2901 sky2_phy_reinit(sky2);
2902
2903 return err;
2904 }
2905
2906 static int sky2_get_coalesce(struct net_device *dev,
2907 struct ethtool_coalesce *ecmd)
2908 {
2909 struct sky2_port *sky2 = netdev_priv(dev);
2910 struct sky2_hw *hw = sky2->hw;
2911
2912 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2913 ecmd->tx_coalesce_usecs = 0;
2914 else {
2915 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2916 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2917 }
2918 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2919
2920 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2921 ecmd->rx_coalesce_usecs = 0;
2922 else {
2923 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2924 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2925 }
2926 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2927
2928 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2929 ecmd->rx_coalesce_usecs_irq = 0;
2930 else {
2931 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2932 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2933 }
2934
2935 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2936
2937 return 0;
2938 }
2939
2940 /* Note: this affect both ports */
2941 static int sky2_set_coalesce(struct net_device *dev,
2942 struct ethtool_coalesce *ecmd)
2943 {
2944 struct sky2_port *sky2 = netdev_priv(dev);
2945 struct sky2_hw *hw = sky2->hw;
2946 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2947
2948 if (ecmd->tx_coalesce_usecs > tmax ||
2949 ecmd->rx_coalesce_usecs > tmax ||
2950 ecmd->rx_coalesce_usecs_irq > tmax)
2951 return -EINVAL;
2952
2953 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2954 return -EINVAL;
2955 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2956 return -EINVAL;
2957 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2958 return -EINVAL;
2959
2960 if (ecmd->tx_coalesce_usecs == 0)
2961 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2962 else {
2963 sky2_write32(hw, STAT_TX_TIMER_INI,
2964 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2965 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2966 }
2967 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2968
2969 if (ecmd->rx_coalesce_usecs == 0)
2970 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2971 else {
2972 sky2_write32(hw, STAT_LEV_TIMER_INI,
2973 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2974 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2975 }
2976 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2977
2978 if (ecmd->rx_coalesce_usecs_irq == 0)
2979 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2980 else {
2981 sky2_write32(hw, STAT_ISR_TIMER_INI,
2982 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2983 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2984 }
2985 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2986 return 0;
2987 }
2988
2989 static void sky2_get_ringparam(struct net_device *dev,
2990 struct ethtool_ringparam *ering)
2991 {
2992 struct sky2_port *sky2 = netdev_priv(dev);
2993
2994 ering->rx_max_pending = RX_MAX_PENDING;
2995 ering->rx_mini_max_pending = 0;
2996 ering->rx_jumbo_max_pending = 0;
2997 ering->tx_max_pending = TX_RING_SIZE - 1;
2998
2999 ering->rx_pending = sky2->rx_pending;
3000 ering->rx_mini_pending = 0;
3001 ering->rx_jumbo_pending = 0;
3002 ering->tx_pending = sky2->tx_pending;
3003 }
3004
3005 static int sky2_set_ringparam(struct net_device *dev,
3006 struct ethtool_ringparam *ering)
3007 {
3008 struct sky2_port *sky2 = netdev_priv(dev);
3009 int err = 0;
3010
3011 if (ering->rx_pending > RX_MAX_PENDING ||
3012 ering->rx_pending < 8 ||
3013 ering->tx_pending < MAX_SKB_TX_LE ||
3014 ering->tx_pending > TX_RING_SIZE - 1)
3015 return -EINVAL;
3016
3017 if (netif_running(dev))
3018 sky2_down(dev);
3019
3020 sky2->rx_pending = ering->rx_pending;
3021 sky2->tx_pending = ering->tx_pending;
3022
3023 if (netif_running(dev)) {
3024 err = sky2_up(dev);
3025 if (err)
3026 dev_close(dev);
3027 else
3028 sky2_set_multicast(dev);
3029 }
3030
3031 return err;
3032 }
3033
3034 static int sky2_get_regs_len(struct net_device *dev)
3035 {
3036 return 0x4000;
3037 }
3038
3039 /*
3040 * Returns copy of control register region
3041 * Note: access to the RAM address register set will cause timeouts.
3042 */
3043 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3044 void *p)
3045 {
3046 const struct sky2_port *sky2 = netdev_priv(dev);
3047 const void __iomem *io = sky2->hw->regs;
3048
3049 BUG_ON(regs->len < B3_RI_WTO_R1);
3050 regs->version = 1;
3051 memset(p, 0, regs->len);
3052
3053 memcpy_fromio(p, io, B3_RAM_ADDR);
3054
3055 memcpy_fromio(p + B3_RI_WTO_R1,
3056 io + B3_RI_WTO_R1,
3057 regs->len - B3_RI_WTO_R1);
3058 }
3059
3060 static struct ethtool_ops sky2_ethtool_ops = {
3061 .get_settings = sky2_get_settings,
3062 .set_settings = sky2_set_settings,
3063 .get_drvinfo = sky2_get_drvinfo,
3064 .get_msglevel = sky2_get_msglevel,
3065 .set_msglevel = sky2_set_msglevel,
3066 .nway_reset = sky2_nway_reset,
3067 .get_regs_len = sky2_get_regs_len,
3068 .get_regs = sky2_get_regs,
3069 .get_link = ethtool_op_get_link,
3070 .get_sg = ethtool_op_get_sg,
3071 .set_sg = ethtool_op_set_sg,
3072 .get_tx_csum = ethtool_op_get_tx_csum,
3073 .set_tx_csum = ethtool_op_set_tx_csum,
3074 .get_tso = ethtool_op_get_tso,
3075 .set_tso = ethtool_op_set_tso,
3076 .get_rx_csum = sky2_get_rx_csum,
3077 .set_rx_csum = sky2_set_rx_csum,
3078 .get_strings = sky2_get_strings,
3079 .get_coalesce = sky2_get_coalesce,
3080 .set_coalesce = sky2_set_coalesce,
3081 .get_ringparam = sky2_get_ringparam,
3082 .set_ringparam = sky2_set_ringparam,
3083 .get_pauseparam = sky2_get_pauseparam,
3084 .set_pauseparam = sky2_set_pauseparam,
3085 .phys_id = sky2_phys_id,
3086 .get_stats_count = sky2_get_stats_count,
3087 .get_ethtool_stats = sky2_get_ethtool_stats,
3088 .get_perm_addr = ethtool_op_get_perm_addr,
3089 };
3090
3091 /* Initialize network device */
3092 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3093 unsigned port, int highmem)
3094 {
3095 struct sky2_port *sky2;
3096 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3097
3098 if (!dev) {
3099 printk(KERN_ERR "sky2 etherdev alloc failed");
3100 return NULL;
3101 }
3102
3103 SET_MODULE_OWNER(dev);
3104 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3105 dev->irq = hw->pdev->irq;
3106 dev->open = sky2_up;
3107 dev->stop = sky2_down;
3108 dev->do_ioctl = sky2_ioctl;
3109 dev->hard_start_xmit = sky2_xmit_frame;
3110 dev->get_stats = sky2_get_stats;
3111 dev->set_multicast_list = sky2_set_multicast;
3112 dev->set_mac_address = sky2_set_mac_address;
3113 dev->change_mtu = sky2_change_mtu;
3114 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3115 dev->tx_timeout = sky2_tx_timeout;
3116 dev->watchdog_timeo = TX_WATCHDOG;
3117 if (port == 0)
3118 dev->poll = sky2_poll;
3119 dev->weight = NAPI_WEIGHT;
3120 #ifdef CONFIG_NET_POLL_CONTROLLER
3121 dev->poll_controller = sky2_netpoll;
3122 #endif
3123
3124 sky2 = netdev_priv(dev);
3125 sky2->netdev = dev;
3126 sky2->hw = hw;
3127 sky2->msg_enable = netif_msg_init(debug, default_msg);
3128
3129 spin_lock_init(&sky2->tx_lock);
3130 /* Auto speed and flow control */
3131 sky2->autoneg = AUTONEG_ENABLE;
3132 sky2->tx_pause = 1;
3133 sky2->rx_pause = 1;
3134 sky2->duplex = -1;
3135 sky2->speed = -1;
3136 sky2->advertising = sky2_supported_modes(hw);
3137 sky2->rx_csum = 1;
3138
3139 spin_lock_init(&sky2->phy_lock);
3140 sky2->tx_pending = TX_DEF_PENDING;
3141 sky2->rx_pending = RX_DEF_PENDING;
3142 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3143
3144 hw->dev[port] = dev;
3145
3146 sky2->port = port;
3147
3148 dev->features |= NETIF_F_LLTX;
3149 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3150 dev->features |= NETIF_F_TSO;
3151 if (highmem)
3152 dev->features |= NETIF_F_HIGHDMA;
3153 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3154
3155 #ifdef SKY2_VLAN_TAG_USED
3156 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3157 dev->vlan_rx_register = sky2_vlan_rx_register;
3158 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3159 #endif
3160
3161 /* read the mac address */
3162 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3163 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3164
3165 /* device is off until link detection */
3166 netif_carrier_off(dev);
3167 netif_stop_queue(dev);
3168
3169 return dev;
3170 }
3171
3172 static void __devinit sky2_show_addr(struct net_device *dev)
3173 {
3174 const struct sky2_port *sky2 = netdev_priv(dev);
3175
3176 if (netif_msg_probe(sky2))
3177 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3178 dev->name,
3179 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3180 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3181 }
3182
3183 /* Handle software interrupt used during MSI test */
3184 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3185 struct pt_regs *regs)
3186 {
3187 struct sky2_hw *hw = dev_id;
3188 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3189
3190 if (status == 0)
3191 return IRQ_NONE;
3192
3193 if (status & Y2_IS_IRQ_SW) {
3194 hw->msi_detected = 1;
3195 wake_up(&hw->msi_wait);
3196 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3197 }
3198 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3199
3200 return IRQ_HANDLED;
3201 }
3202
3203 /* Test interrupt path by forcing a a software IRQ */
3204 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3205 {
3206 struct pci_dev *pdev = hw->pdev;
3207 int err;
3208
3209 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3210
3211 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
3212 if (err) {
3213 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3214 pci_name(pdev), pdev->irq);
3215 return err;
3216 }
3217
3218 init_waitqueue_head (&hw->msi_wait);
3219
3220 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3221 wmb();
3222
3223 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3224
3225 if (!hw->msi_detected) {
3226 /* MSI test failed, go back to INTx mode */
3227 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3228 "switching to INTx mode. Please report this failure to "
3229 "the PCI maintainer and include system chipset information.\n",
3230 pci_name(pdev));
3231
3232 err = -EOPNOTSUPP;
3233 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3234 }
3235
3236 sky2_write32(hw, B0_IMSK, 0);
3237
3238 free_irq(pdev->irq, hw);
3239
3240 return err;
3241 }
3242
3243 static int __devinit sky2_probe(struct pci_dev *pdev,
3244 const struct pci_device_id *ent)
3245 {
3246 struct net_device *dev, *dev1 = NULL;
3247 struct sky2_hw *hw;
3248 int err, pm_cap, using_dac = 0;
3249
3250 err = pci_enable_device(pdev);
3251 if (err) {
3252 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3253 pci_name(pdev));
3254 goto err_out;
3255 }
3256
3257 err = pci_request_regions(pdev, DRV_NAME);
3258 if (err) {
3259 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3260 pci_name(pdev));
3261 goto err_out;
3262 }
3263
3264 pci_set_master(pdev);
3265
3266 /* Find power-management capability. */
3267 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3268 if (pm_cap == 0) {
3269 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3270 "aborting.\n");
3271 err = -EIO;
3272 goto err_out_free_regions;
3273 }
3274
3275 if (sizeof(dma_addr_t) > sizeof(u32) &&
3276 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3277 using_dac = 1;
3278 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3279 if (err < 0) {
3280 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3281 "for consistent allocations\n", pci_name(pdev));
3282 goto err_out_free_regions;
3283 }
3284
3285 } else {
3286 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3287 if (err) {
3288 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3289 pci_name(pdev));
3290 goto err_out_free_regions;
3291 }
3292 }
3293
3294 err = -ENOMEM;
3295 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3296 if (!hw) {
3297 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3298 pci_name(pdev));
3299 goto err_out_free_regions;
3300 }
3301
3302 hw->pdev = pdev;
3303
3304 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3305 if (!hw->regs) {
3306 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3307 pci_name(pdev));
3308 goto err_out_free_hw;
3309 }
3310 hw->pm_cap = pm_cap;
3311
3312 #ifdef __BIG_ENDIAN
3313 /* byte swap descriptors in hardware */
3314 {
3315 u32 reg;
3316
3317 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3318 reg |= PCI_REV_DESC;
3319 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3320 }
3321 #endif
3322
3323 /* ring for status responses */
3324 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3325 &hw->st_dma);
3326 if (!hw->st_le)
3327 goto err_out_iounmap;
3328
3329 err = sky2_reset(hw);
3330 if (err)
3331 goto err_out_iounmap;
3332
3333 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3334 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3335 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3336 hw->chip_id, hw->chip_rev);
3337
3338 dev = sky2_init_netdev(hw, 0, using_dac);
3339 if (!dev)
3340 goto err_out_free_pci;
3341
3342 err = register_netdev(dev);
3343 if (err) {
3344 printk(KERN_ERR PFX "%s: cannot register net device\n",
3345 pci_name(pdev));
3346 goto err_out_free_netdev;
3347 }
3348
3349 sky2_show_addr(dev);
3350
3351 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3352 if (register_netdev(dev1) == 0)
3353 sky2_show_addr(dev1);
3354 else {
3355 /* Failure to register second port need not be fatal */
3356 printk(KERN_WARNING PFX
3357 "register of second port failed\n");
3358 hw->dev[1] = NULL;
3359 free_netdev(dev1);
3360 }
3361 }
3362
3363 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3364 err = sky2_test_msi(hw);
3365 if (err == -EOPNOTSUPP)
3366 pci_disable_msi(pdev);
3367 else if (err)
3368 goto err_out_unregister;
3369 }
3370
3371 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
3372 if (err) {
3373 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3374 pci_name(pdev), pdev->irq);
3375 goto err_out_unregister;
3376 }
3377
3378 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3379
3380 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3381 sky2_idle_start(hw);
3382
3383 pci_set_drvdata(pdev, hw);
3384
3385 return 0;
3386
3387 err_out_unregister:
3388 pci_disable_msi(pdev);
3389 if (dev1) {
3390 unregister_netdev(dev1);
3391 free_netdev(dev1);
3392 }
3393 unregister_netdev(dev);
3394 err_out_free_netdev:
3395 free_netdev(dev);
3396 err_out_free_pci:
3397 sky2_write8(hw, B0_CTST, CS_RST_SET);
3398 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3399 err_out_iounmap:
3400 iounmap(hw->regs);
3401 err_out_free_hw:
3402 kfree(hw);
3403 err_out_free_regions:
3404 pci_release_regions(pdev);
3405 pci_disable_device(pdev);
3406 err_out:
3407 return err;
3408 }
3409
3410 static void __devexit sky2_remove(struct pci_dev *pdev)
3411 {
3412 struct sky2_hw *hw = pci_get_drvdata(pdev);
3413 struct net_device *dev0, *dev1;
3414
3415 if (!hw)
3416 return;
3417
3418 del_timer_sync(&hw->idle_timer);
3419
3420 sky2_write32(hw, B0_IMSK, 0);
3421 synchronize_irq(hw->pdev->irq);
3422
3423 dev0 = hw->dev[0];
3424 dev1 = hw->dev[1];
3425 if (dev1)
3426 unregister_netdev(dev1);
3427 unregister_netdev(dev0);
3428
3429 sky2_set_power_state(hw, PCI_D3hot);
3430 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3431 sky2_write8(hw, B0_CTST, CS_RST_SET);
3432 sky2_read8(hw, B0_CTST);
3433
3434 free_irq(pdev->irq, hw);
3435 pci_disable_msi(pdev);
3436 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3437 pci_release_regions(pdev);
3438 pci_disable_device(pdev);
3439
3440 if (dev1)
3441 free_netdev(dev1);
3442 free_netdev(dev0);
3443 iounmap(hw->regs);
3444 kfree(hw);
3445
3446 pci_set_drvdata(pdev, NULL);
3447 }
3448
3449 #ifdef CONFIG_PM
3450 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3451 {
3452 struct sky2_hw *hw = pci_get_drvdata(pdev);
3453 int i;
3454 pci_power_t pstate = pci_choose_state(pdev, state);
3455
3456 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3457 return -EINVAL;
3458
3459 del_timer_sync(&hw->idle_timer);
3460 netif_poll_disable(hw->dev[0]);
3461
3462 for (i = 0; i < hw->ports; i++) {
3463 struct net_device *dev = hw->dev[i];
3464
3465 if (netif_running(dev)) {
3466 sky2_down(dev);
3467 netif_device_detach(dev);
3468 }
3469 }
3470
3471 sky2_write32(hw, B0_IMSK, 0);
3472 pci_save_state(pdev);
3473 sky2_set_power_state(hw, pstate);
3474 return 0;
3475 }
3476
3477 static int sky2_resume(struct pci_dev *pdev)
3478 {
3479 struct sky2_hw *hw = pci_get_drvdata(pdev);
3480 int i, err;
3481
3482 pci_restore_state(pdev);
3483 pci_enable_wake(pdev, PCI_D0, 0);
3484 sky2_set_power_state(hw, PCI_D0);
3485
3486 err = sky2_reset(hw);
3487 if (err)
3488 goto out;
3489
3490 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3491
3492 for (i = 0; i < hw->ports; i++) {
3493 struct net_device *dev = hw->dev[i];
3494 if (netif_running(dev)) {
3495 netif_device_attach(dev);
3496
3497 err = sky2_up(dev);
3498 if (err) {
3499 printk(KERN_ERR PFX "%s: could not up: %d\n",
3500 dev->name, err);
3501 dev_close(dev);
3502 goto out;
3503 }
3504 }
3505 }
3506
3507 netif_poll_enable(hw->dev[0]);
3508 sky2_idle_start(hw);
3509 out:
3510 return err;
3511 }
3512 #endif
3513
3514 static struct pci_driver sky2_driver = {
3515 .name = DRV_NAME,
3516 .id_table = sky2_id_table,
3517 .probe = sky2_probe,
3518 .remove = __devexit_p(sky2_remove),
3519 #ifdef CONFIG_PM
3520 .suspend = sky2_suspend,
3521 .resume = sky2_resume,
3522 #endif
3523 };
3524
3525 static int __init sky2_init_module(void)
3526 {
3527 return pci_register_driver(&sky2_driver);
3528 }
3529
3530 static void __exit sky2_cleanup_module(void)
3531 {
3532 pci_unregister_driver(&sky2_driver);
3533 }
3534
3535 module_init(sky2_init_module);
3536 module_exit(sky2_cleanup_module);
3537
3538 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3539 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3540 MODULE_LICENSE("GPL");
3541 MODULE_VERSION(DRV_VERSION);
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