2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.6"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
63 #define RX_LE_SIZE 512
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg
=
85 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
86 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
89 static int debug
= -1; /* defaults above */
90 module_param(debug
, int, 0);
91 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly
= 256;
94 module_param(copybreak
, int, 0);
95 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
97 static int disable_msi
= 0;
98 module_param(disable_msi
, int, 0);
99 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
101 static int idle_timeout
= 100;
102 module_param(idle_timeout
, int, 0);
103 MODULE_PARM_DESC(idle_timeout
, "Idle timeout workaround for lost interrupts (ms)");
105 static const struct pci_device_id sky2_id_table
[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) },
132 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
134 /* Avoid conditionals by using array */
135 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
136 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
137 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
139 /* This driver supports yukon2 chipset only */
140 static const char *yukon2_name
[] = {
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
148 /* Access to external PHY */
149 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
153 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
154 gma_write16(hw
, port
, GM_SMI_CTRL
,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
157 for (i
= 0; i
< PHY_RETRIES
; i
++) {
158 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
163 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
167 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
171 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
172 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
174 for (i
= 0; i
< PHY_RETRIES
; i
++) {
175 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
176 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
186 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
190 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
191 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
195 static void sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
201 pr_debug("sky2_set_power_state %d\n", state
);
202 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
204 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
205 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
206 (power_control
& PCI_PM_CAP_PME_D3cold
);
208 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
210 power_control
|= PCI_PM_CTRL_PME_STATUS
;
211 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw
, B0_POWER_CTRL
,
217 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
219 /* disable Core Clock Division, */
220 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
222 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
223 /* enable bits are inverted */
224 sky2_write8(hw
, B2_Y2_CLK_GATE
,
225 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
226 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
227 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
229 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
231 /* Turn off phy power saving */
232 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
233 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
235 /* looks like this XL is back asswards .. */
236 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
237 reg1
|= PCI_Y2_PHY1_COMA
;
239 reg1
|= PCI_Y2_PHY2_COMA
;
241 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
244 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
245 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
246 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
247 reg1
&= P_ASPM_CONTROL_MSK
;
248 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
249 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
256 /* Turn on phy power saving */
257 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
258 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
259 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
261 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
262 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
265 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
266 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
268 /* enable bits are inverted */
269 sky2_write8(hw
, B2_Y2_CLK_GATE
,
270 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
271 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
272 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
274 /* switch power to VAUX */
275 if (vaux
&& state
!= PCI_D3cold
)
276 sky2_write8(hw
, B0_POWER_CTRL
,
277 (PC_VAUX_ENA
| PC_VCC_ENA
|
278 PC_VAUX_ON
| PC_VCC_OFF
));
281 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
284 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
285 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
288 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
294 /* disable PHY IRQs */
295 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
297 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
298 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
299 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
300 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
302 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
303 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
304 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
307 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
309 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
310 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
312 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
313 !(hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
314 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
316 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
318 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
320 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
321 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
323 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
325 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
328 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
330 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
331 /* enable automatic crossover */
332 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
334 /* disable energy detect */
335 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
337 /* enable automatic crossover */
338 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
340 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
341 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
342 ctrl
&= ~PHY_M_PC_DSC_MSK
;
343 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
346 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
348 /* workaround for deviation #4.88 (CRC errors) */
349 /* disable Automatic Crossover */
351 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
352 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
354 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
355 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
356 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
357 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
358 ctrl
&= ~PHY_M_MAC_MD_MSK
;
359 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
360 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
362 /* select page 1 to access Fiber registers */
363 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
367 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
368 if (sky2
->autoneg
== AUTONEG_DISABLE
)
373 ctrl
|= PHY_CT_RESET
;
374 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
380 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
382 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
383 ct1000
|= PHY_M_1000C_AFD
;
384 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
385 ct1000
|= PHY_M_1000C_AHD
;
386 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
387 adv
|= PHY_M_AN_100_FD
;
388 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
389 adv
|= PHY_M_AN_100_HD
;
390 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
391 adv
|= PHY_M_AN_10_FD
;
392 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
393 adv
|= PHY_M_AN_10_HD
;
394 } else /* special defines for FIBER (88E1011S only) */
395 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
397 /* Set Flow-control capabilities */
398 if (sky2
->tx_pause
&& sky2
->rx_pause
)
399 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
400 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
401 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
402 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
403 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
405 /* Restart Auto-negotiation */
406 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
408 /* forced speed/duplex settings */
409 ct1000
= PHY_M_1000C_MSE
;
411 if (sky2
->duplex
== DUPLEX_FULL
)
412 ctrl
|= PHY_CT_DUP_MD
;
414 switch (sky2
->speed
) {
416 ctrl
|= PHY_CT_SP1000
;
419 ctrl
|= PHY_CT_SP100
;
423 ctrl
|= PHY_CT_RESET
;
426 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
427 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
429 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
430 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
432 /* Setup Phy LED's */
433 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
436 switch (hw
->chip_id
) {
437 case CHIP_ID_YUKON_FE
:
438 /* on 88E3082 these bits are at 11..9 (shifted left) */
439 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
441 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
443 /* delete ACT LED control bits */
444 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
445 /* change ACT LED control to blink mode */
446 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
447 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
450 case CHIP_ID_YUKON_XL
:
451 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
453 /* select page 3 to access LED control register */
454 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
456 /* set LED Function Control register */
457 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
458 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
459 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
460 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
461 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
463 /* set Polarity Control register */
464 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
465 (PHY_M_POLC_LS1_P_MIX(4) |
466 PHY_M_POLC_IS0_P_MIX(4) |
467 PHY_M_POLC_LOS_CTRL(2) |
468 PHY_M_POLC_INIT_CTRL(2) |
469 PHY_M_POLC_STA1_CTRL(2) |
470 PHY_M_POLC_STA0_CTRL(2)));
472 /* restore page register */
473 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
475 case CHIP_ID_YUKON_EC_U
:
476 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
478 /* select page 3 to access LED control register */
479 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
481 /* set LED Function Control register */
482 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
483 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
484 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
485 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
486 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
488 /* set Blink Rate in LED Timer Control Register */
489 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
490 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
491 /* restore page register */
492 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
496 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
497 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
498 /* turn off the Rx LED (LED_RX) */
499 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
502 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
503 /* apply fixes in PHY AFE */
504 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
505 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
507 /* increase differential signal amplitude in 10BASE-T */
508 gm_phy_write(hw
, port
, 0x18, 0xaa99);
509 gm_phy_write(hw
, port
, 0x17, 0x2011);
511 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
512 gm_phy_write(hw
, port
, 0x18, 0xa204);
513 gm_phy_write(hw
, port
, 0x17, 0x2002);
515 /* set page register to 0 */
516 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
518 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
520 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
521 /* turn on 100 Mbps LED (LED_LINK100) */
522 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
526 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
529 /* Enable phy interrupt on auto-negotiation complete (or link up) */
530 if (sky2
->autoneg
== AUTONEG_ENABLE
)
531 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
533 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
536 /* Force a renegotiation */
537 static void sky2_phy_reinit(struct sky2_port
*sky2
)
539 spin_lock_bh(&sky2
->phy_lock
);
540 sky2_phy_init(sky2
->hw
, sky2
->port
);
541 spin_unlock_bh(&sky2
->phy_lock
);
544 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
546 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
549 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
551 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
552 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
554 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
556 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
557 /* WA DEV_472 -- looks like crossed wires on port 2 */
558 /* clear GMAC 1 Control reset */
559 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
561 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
562 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
563 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
564 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
565 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
568 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
569 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
570 reg
|= GM_GPCR_AU_ALL_DIS
;
571 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
572 gma_read16(hw
, port
, GM_GP_CTRL
);
574 switch (sky2
->speed
) {
576 reg
&= ~GM_GPCR_SPEED_100
;
577 reg
|= GM_GPCR_SPEED_1000
;
580 reg
&= ~GM_GPCR_SPEED_1000
;
581 reg
|= GM_GPCR_SPEED_100
;
584 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
588 if (sky2
->duplex
== DUPLEX_FULL
)
589 reg
|= GM_GPCR_DUP_FULL
;
591 /* turn off pause in 10/100mbps half duplex */
592 else if (sky2
->speed
!= SPEED_1000
&&
593 hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
594 sky2
->tx_pause
= sky2
->rx_pause
= 0;
596 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
598 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
599 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
601 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
602 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
603 /* disable Rx flow-control */
604 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
607 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
609 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
611 spin_lock_bh(&sky2
->phy_lock
);
612 sky2_phy_init(hw
, port
);
613 spin_unlock_bh(&sky2
->phy_lock
);
616 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
617 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
619 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
620 gma_read16(hw
, port
, i
);
621 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
623 /* transmit control */
624 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
626 /* receive control reg: unicast + multicast + no FCS */
627 gma_write16(hw
, port
, GM_RX_CTRL
,
628 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
630 /* transmit flow control */
631 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
633 /* transmit parameter */
634 gma_write16(hw
, port
, GM_TX_PARAM
,
635 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
636 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
637 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
638 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
640 /* serial mode register */
641 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
642 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
644 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
645 reg
|= GM_SMOD_JUMBO_ENA
;
647 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
649 /* virtual address for data */
650 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
652 /* physical address: used for pause frames */
653 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
655 /* ignore counter overflows */
656 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
657 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
658 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
660 /* Configure Rx MAC FIFO */
661 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
662 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
663 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
665 /* Flush Rx MAC FIFO on any flow control or error */
666 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
668 /* Set threshold to 0xa (64 bytes)
669 * ASF disabled so no need to do WA dev #4.30
671 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
673 /* Configure Tx MAC FIFO */
674 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
675 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
677 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
678 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
679 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
680 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
681 /* set Tx GMAC FIFO Almost Empty Threshold */
682 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
683 /* Disable Store & Forward mode for TX */
684 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
690 /* Assign Ram Buffer allocation.
691 * start and end are in units of 4k bytes
692 * ram registers are in units of 64bit words
694 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
698 start
= startk
* 4096/8;
699 end
= (endk
* 4096/8) - 1;
701 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
702 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
703 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
704 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
705 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
707 if (q
== Q_R1
|| q
== Q_R2
) {
708 u32 space
= (endk
- startk
) * 4096/8;
709 u32 tp
= space
- space
/4;
711 /* On receive queue's set the thresholds
712 * give receiver priority when > 3/4 full
713 * send pause when down to 2K
715 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
716 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
719 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
720 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
722 /* Enable store & forward on Tx queue's because
723 * Tx FIFO is only 1K on Yukon
725 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
728 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
729 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
732 /* Setup Bus Memory Interface */
733 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
735 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
736 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
737 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
738 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
741 /* Setup prefetch unit registers. This is the interface between
742 * hardware and driver list elements
744 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
747 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
748 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
749 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
750 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
751 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
752 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
754 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
757 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
759 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
761 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
765 /* Update chip's next pointer */
766 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
769 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
774 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
776 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
777 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
781 /* Return high part of DMA address (could be 32 or 64 bit) */
782 static inline u32
high32(dma_addr_t a
)
784 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
787 /* Build description to hardware about buffer */
788 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
790 struct sky2_rx_le
*le
;
791 u32 hi
= high32(map
);
792 u16 len
= sky2
->rx_bufsize
;
794 if (sky2
->rx_addr64
!= hi
) {
795 le
= sky2_next_rx(sky2
);
796 le
->addr
= cpu_to_le32(hi
);
798 le
->opcode
= OP_ADDR64
| HW_OWNER
;
799 sky2
->rx_addr64
= high32(map
+ len
);
802 le
= sky2_next_rx(sky2
);
803 le
->addr
= cpu_to_le32((u32
) map
);
804 le
->length
= cpu_to_le16(len
);
806 le
->opcode
= OP_PACKET
| HW_OWNER
;
810 /* Tell chip where to start receive checksum.
811 * Actually has two checksums, but set both same to avoid possible byte
814 static void rx_set_checksum(struct sky2_port
*sky2
)
816 struct sky2_rx_le
*le
;
818 le
= sky2_next_rx(sky2
);
819 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
821 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
823 sky2_write32(sky2
->hw
,
824 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
825 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
830 * The RX Stop command will not work for Yukon-2 if the BMU does not
831 * reach the end of packet and since we can't make sure that we have
832 * incoming data, we must reset the BMU while it is not doing a DMA
833 * transfer. Since it is possible that the RX path is still active,
834 * the RX RAM buffer will be stopped first, so any possible incoming
835 * data will not trigger a DMA. After the RAM buffer is stopped, the
836 * BMU is polled until any DMA in progress is ended and only then it
839 static void sky2_rx_stop(struct sky2_port
*sky2
)
841 struct sky2_hw
*hw
= sky2
->hw
;
842 unsigned rxq
= rxqaddr
[sky2
->port
];
845 /* disable the RAM Buffer receive queue */
846 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
848 for (i
= 0; i
< 0xffff; i
++)
849 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
850 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
853 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
856 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
858 /* reset the Rx prefetch unit */
859 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
862 /* Clean out receive buffer area, assumes receiver hardware stopped */
863 static void sky2_rx_clean(struct sky2_port
*sky2
)
867 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
868 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
869 struct ring_info
*re
= sky2
->rx_ring
+ i
;
872 pci_unmap_single(sky2
->hw
->pdev
,
873 re
->mapaddr
, sky2
->rx_bufsize
,
881 /* Basic MII support */
882 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
884 struct mii_ioctl_data
*data
= if_mii(ifr
);
885 struct sky2_port
*sky2
= netdev_priv(dev
);
886 struct sky2_hw
*hw
= sky2
->hw
;
887 int err
= -EOPNOTSUPP
;
889 if (!netif_running(dev
))
890 return -ENODEV
; /* Phy still in reset */
894 data
->phy_id
= PHY_ADDR_MARV
;
900 spin_lock_bh(&sky2
->phy_lock
);
901 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
902 spin_unlock_bh(&sky2
->phy_lock
);
909 if (!capable(CAP_NET_ADMIN
))
912 spin_lock_bh(&sky2
->phy_lock
);
913 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
915 spin_unlock_bh(&sky2
->phy_lock
);
921 #ifdef SKY2_VLAN_TAG_USED
922 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
924 struct sky2_port
*sky2
= netdev_priv(dev
);
925 struct sky2_hw
*hw
= sky2
->hw
;
926 u16 port
= sky2
->port
;
928 spin_lock_bh(&sky2
->tx_lock
);
930 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
931 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
934 spin_unlock_bh(&sky2
->tx_lock
);
937 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
939 struct sky2_port
*sky2
= netdev_priv(dev
);
940 struct sky2_hw
*hw
= sky2
->hw
;
941 u16 port
= sky2
->port
;
943 spin_lock_bh(&sky2
->tx_lock
);
945 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
946 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
948 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
950 spin_unlock_bh(&sky2
->tx_lock
);
955 * It appears the hardware has a bug in the FIFO logic that
956 * cause it to hang if the FIFO gets overrun and the receive buffer
957 * is not aligned. ALso alloc_skb() won't align properly if slab
958 * debugging is enabled.
960 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
964 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
966 unsigned long p
= (unsigned long) skb
->data
;
967 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
974 * Allocate and setup receiver buffer pool.
975 * In case of 64 bit dma, there are 2X as many list elements
976 * available as ring entries
977 * and need to reserve one list element so we don't wrap around.
979 static int sky2_rx_start(struct sky2_port
*sky2
)
981 struct sky2_hw
*hw
= sky2
->hw
;
982 unsigned rxq
= rxqaddr
[sky2
->port
];
986 sky2
->rx_put
= sky2
->rx_next
= 0;
989 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
990 /* MAC Rx RAM Read is controlled by hardware */
991 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
994 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
996 rx_set_checksum(sky2
);
997 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
998 struct ring_info
*re
= sky2
->rx_ring
+ i
;
1000 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
1004 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
1005 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1006 sky2_rx_add(sky2
, re
->mapaddr
);
1011 * The receiver hangs if it receives frames larger than the
1012 * packet buffer. As a workaround, truncate oversize frames, but
1013 * the register is limited to 9 bits, so if you do frames > 2052
1014 * you better get the MTU right!
1016 thresh
= (sky2
->rx_bufsize
- 8) / sizeof(u32
);
1018 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1020 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1021 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1025 /* Tell chip about available buffers */
1026 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1029 sky2_rx_clean(sky2
);
1033 /* Bring up network interface. */
1034 static int sky2_up(struct net_device
*dev
)
1036 struct sky2_port
*sky2
= netdev_priv(dev
);
1037 struct sky2_hw
*hw
= sky2
->hw
;
1038 unsigned port
= sky2
->port
;
1039 u32 ramsize
, rxspace
, imask
;
1040 int cap
, err
= -ENOMEM
;
1041 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1044 * On dual port PCI-X card, there is an problem where status
1045 * can be received out of order due to split transactions
1047 if (otherdev
&& netif_running(otherdev
) &&
1048 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1049 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1052 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1053 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1054 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1060 if (netif_msg_ifup(sky2
))
1061 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1063 /* must be power of 2 */
1064 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1066 sizeof(struct sky2_tx_le
),
1071 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1075 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1077 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1081 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1083 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1088 sky2_mac_init(hw
, port
);
1090 /* Determine available ram buffer space (in 4K blocks).
1091 * Note: not sure about the FE setting below yet
1093 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1096 ramsize
= sky2_read8(hw
, B2_E_0
);
1098 /* Give transmitter one third (rounded up) */
1099 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1101 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1102 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1104 /* Make sure SyncQ is disabled */
1105 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1108 sky2_qset(hw
, txqaddr
[port
]);
1110 /* Set almost empty threshold */
1111 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== 1)
1112 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1114 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1117 err
= sky2_rx_start(sky2
);
1121 /* Enable interrupts from phy/mac for port */
1122 imask
= sky2_read32(hw
, B0_IMSK
);
1123 imask
|= portirq_msk
[port
];
1124 sky2_write32(hw
, B0_IMSK
, imask
);
1130 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1131 sky2
->rx_le
, sky2
->rx_le_map
);
1135 pci_free_consistent(hw
->pdev
,
1136 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1137 sky2
->tx_le
, sky2
->tx_le_map
);
1140 kfree(sky2
->tx_ring
);
1141 kfree(sky2
->rx_ring
);
1143 sky2
->tx_ring
= NULL
;
1144 sky2
->rx_ring
= NULL
;
1148 /* Modular subtraction in ring */
1149 static inline int tx_dist(unsigned tail
, unsigned head
)
1151 return (head
- tail
) & (TX_RING_SIZE
- 1);
1154 /* Number of list elements available for next tx */
1155 static inline int tx_avail(const struct sky2_port
*sky2
)
1157 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1160 /* Estimate of number of transmit list elements required */
1161 static unsigned tx_le_req(const struct sk_buff
*skb
)
1165 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1166 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1168 if (skb_is_gso(skb
))
1171 if (skb
->ip_summed
== CHECKSUM_HW
)
1178 * Put one packet in ring for transmit.
1179 * A single packet can generate multiple list elements, and
1180 * the number of ring elements will probably be less than the number
1181 * of list elements used.
1183 * No BH disabling for tx_lock here (like tg3)
1185 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1187 struct sky2_port
*sky2
= netdev_priv(dev
);
1188 struct sky2_hw
*hw
= sky2
->hw
;
1189 struct sky2_tx_le
*le
= NULL
;
1190 struct tx_ring_info
*re
;
1198 /* No BH disabling for tx_lock here. We are running in BH disabled
1199 * context and TX reclaim runs via poll inside of a software
1200 * interrupt, and no related locks in IRQ processing.
1202 if (!spin_trylock(&sky2
->tx_lock
))
1203 return NETDEV_TX_LOCKED
;
1205 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1206 /* There is a known but harmless race with lockless tx
1207 * and netif_stop_queue.
1209 if (!netif_queue_stopped(dev
)) {
1210 netif_stop_queue(dev
);
1211 if (net_ratelimit())
1212 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1215 spin_unlock(&sky2
->tx_lock
);
1217 return NETDEV_TX_BUSY
;
1220 if (unlikely(netif_msg_tx_queued(sky2
)))
1221 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1222 dev
->name
, sky2
->tx_prod
, skb
->len
);
1224 len
= skb_headlen(skb
);
1225 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1226 addr64
= high32(mapping
);
1228 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1230 /* Send high bits if changed or crosses boundary */
1231 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1232 le
= get_tx_le(sky2
);
1233 le
->tx
.addr
= cpu_to_le32(addr64
);
1235 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1236 sky2
->tx_addr64
= high32(mapping
+ len
);
1239 /* Check for TCP Segmentation Offload */
1240 mss
= skb_shinfo(skb
)->gso_size
;
1242 /* just drop the packet if non-linear expansion fails */
1243 if (skb_header_cloned(skb
) &&
1244 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1249 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1250 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1254 if (mss
!= sky2
->tx_last_mss
) {
1255 le
= get_tx_le(sky2
);
1256 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1257 le
->tx
.tso
.rsvd
= 0;
1258 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1260 sky2
->tx_last_mss
= mss
;
1264 #ifdef SKY2_VLAN_TAG_USED
1265 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1266 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1268 le
= get_tx_le(sky2
);
1270 le
->opcode
= OP_VLAN
|HW_OWNER
;
1273 le
->opcode
|= OP_VLAN
;
1274 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1279 /* Handle TCP checksum offload */
1280 if (skb
->ip_summed
== CHECKSUM_HW
) {
1281 u16 hdr
= skb
->h
.raw
- skb
->data
;
1282 u16 offset
= hdr
+ skb
->csum
;
1284 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1285 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1288 le
= get_tx_le(sky2
);
1289 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1290 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1291 le
->length
= 0; /* initial checksum value */
1292 le
->ctrl
= 1; /* one packet */
1293 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1296 le
= get_tx_le(sky2
);
1297 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1298 le
->length
= cpu_to_le16(len
);
1300 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1302 /* Record the transmit mapping info */
1304 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1306 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1307 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1308 struct tx_ring_info
*fre
;
1310 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1311 frag
->size
, PCI_DMA_TODEVICE
);
1312 addr64
= high32(mapping
);
1313 if (addr64
!= sky2
->tx_addr64
) {
1314 le
= get_tx_le(sky2
);
1315 le
->tx
.addr
= cpu_to_le32(addr64
);
1317 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1318 sky2
->tx_addr64
= addr64
;
1321 le
= get_tx_le(sky2
);
1322 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1323 le
->length
= cpu_to_le16(frag
->size
);
1325 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1328 + RING_NEXT((re
- sky2
->tx_ring
) + i
, TX_RING_SIZE
);
1329 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1332 re
->idx
= sky2
->tx_prod
;
1335 avail
= tx_avail(sky2
);
1336 if (mss
!= 0 || avail
< TX_MIN_PENDING
) {
1337 le
->ctrl
|= FRC_STAT
;
1338 if (avail
<= MAX_SKB_TX_LE
)
1339 netif_stop_queue(dev
);
1342 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1345 spin_unlock(&sky2
->tx_lock
);
1347 dev
->trans_start
= jiffies
;
1348 return NETDEV_TX_OK
;
1352 * Free ring elements from starting at tx_cons until "done"
1354 * NB: the hardware will tell us about partial completion of multi-part
1355 * buffers; these are deferred until completion.
1357 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1359 struct net_device
*dev
= sky2
->netdev
;
1360 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1364 BUG_ON(done
>= TX_RING_SIZE
);
1366 if (unlikely(netif_msg_tx_done(sky2
)))
1367 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1370 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1371 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1372 struct sk_buff
*skb
= re
->skb
;
1375 BUG_ON(nxt
>= TX_RING_SIZE
);
1376 prefetch(sky2
->tx_ring
+ nxt
);
1378 /* Check for partial status */
1379 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1383 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1384 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1386 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1387 struct tx_ring_info
*fre
;
1388 fre
= sky2
->tx_ring
+ RING_NEXT(put
+ i
, TX_RING_SIZE
);
1389 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1390 skb_shinfo(skb
)->frags
[i
].size
,
1397 sky2
->tx_cons
= put
;
1398 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1399 netif_wake_queue(dev
);
1402 /* Cleanup all untransmitted buffers, assume transmitter not running */
1403 static void sky2_tx_clean(struct sky2_port
*sky2
)
1405 spin_lock_bh(&sky2
->tx_lock
);
1406 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1407 spin_unlock_bh(&sky2
->tx_lock
);
1410 /* Network shutdown */
1411 static int sky2_down(struct net_device
*dev
)
1413 struct sky2_port
*sky2
= netdev_priv(dev
);
1414 struct sky2_hw
*hw
= sky2
->hw
;
1415 unsigned port
= sky2
->port
;
1419 /* Never really got started! */
1423 if (netif_msg_ifdown(sky2
))
1424 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1426 /* Stop more packets from being queued */
1427 netif_stop_queue(dev
);
1429 sky2_phy_reset(hw
, port
);
1431 /* Stop transmitter */
1432 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1433 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1435 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1436 RB_RST_SET
| RB_DIS_OP_MD
);
1438 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1439 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1440 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1442 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1444 /* Workaround shared GMAC reset */
1445 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1446 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1447 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1449 /* Disable Force Sync bit and Enable Alloc bit */
1450 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1451 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1453 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1454 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1455 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1457 /* Reset the PCI FIFO of the async Tx queue */
1458 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1459 BMU_RST_SET
| BMU_FIFO_RST
);
1461 /* Reset the Tx prefetch units */
1462 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1465 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1469 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1470 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1472 /* Disable port IRQ */
1473 imask
= sky2_read32(hw
, B0_IMSK
);
1474 imask
&= ~portirq_msk
[port
];
1475 sky2_write32(hw
, B0_IMSK
, imask
);
1477 /* turn off LED's */
1478 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1480 synchronize_irq(hw
->pdev
->irq
);
1482 sky2_tx_clean(sky2
);
1483 sky2_rx_clean(sky2
);
1485 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1486 sky2
->rx_le
, sky2
->rx_le_map
);
1487 kfree(sky2
->rx_ring
);
1489 pci_free_consistent(hw
->pdev
,
1490 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1491 sky2
->tx_le
, sky2
->tx_le_map
);
1492 kfree(sky2
->tx_ring
);
1497 sky2
->rx_ring
= NULL
;
1498 sky2
->tx_ring
= NULL
;
1503 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1508 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1509 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1511 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1512 case PHY_M_PS_SPEED_1000
:
1514 case PHY_M_PS_SPEED_100
:
1521 static void sky2_link_up(struct sky2_port
*sky2
)
1523 struct sky2_hw
*hw
= sky2
->hw
;
1524 unsigned port
= sky2
->port
;
1527 /* Enable Transmit FIFO Underrun */
1528 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1530 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1531 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1532 reg
|= GM_GPCR_AU_ALL_DIS
;
1534 /* Is write/read necessary? Copied from sky2_mac_init */
1535 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1536 gma_read16(hw
, port
, GM_GP_CTRL
);
1538 switch (sky2
->speed
) {
1540 reg
&= ~GM_GPCR_SPEED_100
;
1541 reg
|= GM_GPCR_SPEED_1000
;
1544 reg
&= ~GM_GPCR_SPEED_1000
;
1545 reg
|= GM_GPCR_SPEED_100
;
1548 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1552 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1554 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1555 reg
|= GM_GPCR_DUP_FULL
;
1558 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1559 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1560 gma_read16(hw
, port
, GM_GP_CTRL
);
1562 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1564 netif_carrier_on(sky2
->netdev
);
1565 netif_wake_queue(sky2
->netdev
);
1567 /* Turn on link LED */
1568 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1569 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1571 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1572 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1573 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1575 switch(sky2
->speed
) {
1577 led
|= PHY_M_LEDC_INIT_CTRL(7);
1581 led
|= PHY_M_LEDC_STA1_CTRL(7);
1585 led
|= PHY_M_LEDC_STA0_CTRL(7);
1589 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1590 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1591 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1594 if (netif_msg_link(sky2
))
1595 printk(KERN_INFO PFX
1596 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1597 sky2
->netdev
->name
, sky2
->speed
,
1598 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1599 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1600 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1603 static void sky2_link_down(struct sky2_port
*sky2
)
1605 struct sky2_hw
*hw
= sky2
->hw
;
1606 unsigned port
= sky2
->port
;
1609 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1611 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1612 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1613 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1614 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1616 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1617 /* restore Asymmetric Pause bit */
1618 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1619 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1623 netif_carrier_off(sky2
->netdev
);
1624 netif_stop_queue(sky2
->netdev
);
1626 /* Turn on link LED */
1627 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1629 if (netif_msg_link(sky2
))
1630 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1631 sky2_phy_init(hw
, port
);
1634 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1636 struct sky2_hw
*hw
= sky2
->hw
;
1637 unsigned port
= sky2
->port
;
1640 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1642 if (lpa
& PHY_M_AN_RF
) {
1643 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1647 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1648 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1649 printk(KERN_ERR PFX
"%s: master/slave fault",
1650 sky2
->netdev
->name
);
1654 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1655 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1656 sky2
->netdev
->name
);
1660 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1662 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1664 /* Pause bits are offset (9..8) */
1665 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1668 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1669 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1671 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1672 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1673 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1675 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1680 /* Interrupt from PHY */
1681 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1683 struct net_device
*dev
= hw
->dev
[port
];
1684 struct sky2_port
*sky2
= netdev_priv(dev
);
1685 u16 istatus
, phystat
;
1687 spin_lock(&sky2
->phy_lock
);
1688 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1689 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1691 if (!netif_running(dev
))
1694 if (netif_msg_intr(sky2
))
1695 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1696 sky2
->netdev
->name
, istatus
, phystat
);
1698 if (istatus
& PHY_M_IS_AN_COMPL
) {
1699 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1704 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1705 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1707 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1709 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1711 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1712 if (phystat
& PHY_M_PS_LINK_UP
)
1715 sky2_link_down(sky2
);
1718 spin_unlock(&sky2
->phy_lock
);
1722 /* Transmit timeout is only called if we are running, carries is up
1723 * and tx queue is full (stopped).
1725 static void sky2_tx_timeout(struct net_device
*dev
)
1727 struct sky2_port
*sky2
= netdev_priv(dev
);
1728 struct sky2_hw
*hw
= sky2
->hw
;
1729 unsigned txq
= txqaddr
[sky2
->port
];
1732 if (netif_msg_timer(sky2
))
1733 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1735 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1736 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1738 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1740 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1742 if (report
!= done
) {
1743 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1745 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1746 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1747 } else if (report
!= sky2
->tx_cons
) {
1748 printk(KERN_INFO PFX
"status report lost?\n");
1750 spin_lock_bh(&sky2
->tx_lock
);
1751 sky2_tx_complete(sky2
, report
);
1752 spin_unlock_bh(&sky2
->tx_lock
);
1754 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1756 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1757 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1759 sky2_tx_clean(sky2
);
1762 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1767 /* Want receive buffer size to be multiple of 64 bits
1768 * and incl room for vlan and truncation
1770 static inline unsigned sky2_buf_size(int mtu
)
1772 return ALIGN(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1775 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1777 struct sky2_port
*sky2
= netdev_priv(dev
);
1778 struct sky2_hw
*hw
= sky2
->hw
;
1783 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1786 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1789 if (!netif_running(dev
)) {
1794 imask
= sky2_read32(hw
, B0_IMSK
);
1795 sky2_write32(hw
, B0_IMSK
, 0);
1797 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1798 netif_stop_queue(dev
);
1799 netif_poll_disable(hw
->dev
[0]);
1801 synchronize_irq(hw
->pdev
->irq
);
1803 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1804 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1806 sky2_rx_clean(sky2
);
1809 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1810 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1811 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1813 if (dev
->mtu
> ETH_DATA_LEN
)
1814 mode
|= GM_SMOD_JUMBO_ENA
;
1816 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1818 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1820 err
= sky2_rx_start(sky2
);
1821 sky2_write32(hw
, B0_IMSK
, imask
);
1826 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1828 netif_poll_enable(hw
->dev
[0]);
1829 netif_wake_queue(dev
);
1836 * Receive one packet.
1837 * For small packets or errors, just reuse existing skb.
1838 * For larger packets, get new buffer.
1840 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1841 u16 length
, u32 status
)
1843 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1844 struct sk_buff
*skb
= NULL
;
1846 if (unlikely(netif_msg_rx_status(sky2
)))
1847 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1848 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1850 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1851 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1853 if (status
& GMR_FS_ANY_ERR
)
1856 if (!(status
& GMR_FS_RX_OK
))
1859 if (length
> sky2
->netdev
->mtu
+ ETH_HLEN
)
1862 if (length
< copybreak
) {
1863 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1867 skb_reserve(skb
, 2);
1868 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1869 length
, PCI_DMA_FROMDEVICE
);
1870 memcpy(skb
->data
, re
->skb
->data
, length
);
1871 skb
->ip_summed
= re
->skb
->ip_summed
;
1872 skb
->csum
= re
->skb
->csum
;
1873 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1874 length
, PCI_DMA_FROMDEVICE
);
1876 struct sk_buff
*nskb
;
1878 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1884 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1885 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1886 prefetch(skb
->data
);
1888 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1889 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1892 skb_put(skb
, length
);
1894 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1895 sky2_rx_add(sky2
, re
->mapaddr
);
1900 ++sky2
->net_stats
.rx_over_errors
;
1904 ++sky2
->net_stats
.rx_errors
;
1906 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1907 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1908 sky2
->netdev
->name
, status
, length
);
1910 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1911 sky2
->net_stats
.rx_length_errors
++;
1912 if (status
& GMR_FS_FRAGMENT
)
1913 sky2
->net_stats
.rx_frame_errors
++;
1914 if (status
& GMR_FS_CRC_ERR
)
1915 sky2
->net_stats
.rx_crc_errors
++;
1916 if (status
& GMR_FS_RX_FF_OV
)
1917 sky2
->net_stats
.rx_fifo_errors
++;
1922 /* Transmit complete */
1923 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
1925 struct sky2_port
*sky2
= netdev_priv(dev
);
1927 if (netif_running(dev
)) {
1928 spin_lock(&sky2
->tx_lock
);
1929 sky2_tx_complete(sky2
, last
);
1930 spin_unlock(&sky2
->tx_lock
);
1934 /* Process status response ring */
1935 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
1937 struct sky2_port
*sky2
;
1939 unsigned buf_write
[2] = { 0, 0 };
1940 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1944 while (hw
->st_idx
!= hwidx
) {
1945 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1946 struct net_device
*dev
;
1947 struct sk_buff
*skb
;
1951 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
1953 BUG_ON(le
->link
>= 2);
1954 dev
= hw
->dev
[le
->link
];
1956 sky2
= netdev_priv(dev
);
1957 length
= le
->length
;
1958 status
= le
->status
;
1960 switch (le
->opcode
& ~HW_OWNER
) {
1962 skb
= sky2_receive(sky2
, length
, status
);
1967 skb
->protocol
= eth_type_trans(skb
, dev
);
1968 dev
->last_rx
= jiffies
;
1970 #ifdef SKY2_VLAN_TAG_USED
1971 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1972 vlan_hwaccel_receive_skb(skb
,
1974 be16_to_cpu(sky2
->rx_tag
));
1977 netif_receive_skb(skb
);
1979 /* Update receiver after 16 frames */
1980 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
1981 sky2_put_idx(hw
, rxqaddr
[le
->link
],
1983 buf_write
[le
->link
] = 0;
1986 /* Stop after net poll weight */
1987 if (++work_done
>= to_do
)
1991 #ifdef SKY2_VLAN_TAG_USED
1993 sky2
->rx_tag
= length
;
1997 sky2
->rx_tag
= length
;
2001 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2002 skb
->ip_summed
= CHECKSUM_HW
;
2003 skb
->csum
= le16_to_cpu(status
);
2007 /* TX index reports status for both ports */
2008 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2009 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2011 sky2_tx_done(hw
->dev
[1],
2012 ((status
>> 24) & 0xff)
2013 | (u16
)(length
& 0xf) << 8);
2017 if (net_ratelimit())
2018 printk(KERN_WARNING PFX
2019 "unknown status opcode 0x%x\n", le
->opcode
);
2024 /* Fully processed status ring so clear irq */
2025 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2029 sky2
= netdev_priv(hw
->dev
[0]);
2030 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2034 sky2
= netdev_priv(hw
->dev
[1]);
2035 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2041 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2043 struct net_device
*dev
= hw
->dev
[port
];
2045 if (net_ratelimit())
2046 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2049 if (status
& Y2_IS_PAR_RD1
) {
2050 if (net_ratelimit())
2051 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2054 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2057 if (status
& Y2_IS_PAR_WR1
) {
2058 if (net_ratelimit())
2059 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2062 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2065 if (status
& Y2_IS_PAR_MAC1
) {
2066 if (net_ratelimit())
2067 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2068 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2071 if (status
& Y2_IS_PAR_RX1
) {
2072 if (net_ratelimit())
2073 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2074 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2077 if (status
& Y2_IS_TCP_TXA1
) {
2078 if (net_ratelimit())
2079 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2081 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2085 static void sky2_hw_intr(struct sky2_hw
*hw
)
2087 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2089 if (status
& Y2_IS_TIST_OV
)
2090 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2092 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2095 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2096 if (net_ratelimit())
2097 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2098 pci_name(hw
->pdev
), pci_err
);
2100 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2101 sky2_pci_write16(hw
, PCI_STATUS
,
2102 pci_err
| PCI_STATUS_ERROR_BITS
);
2103 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2106 if (status
& Y2_IS_PCI_EXP
) {
2107 /* PCI-Express uncorrectable Error occurred */
2110 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2112 if (net_ratelimit())
2113 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2114 pci_name(hw
->pdev
), pex_err
);
2116 /* clear the interrupt */
2117 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2118 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2120 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2122 if (pex_err
& PEX_FATAL_ERRORS
) {
2123 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2124 hwmsk
&= ~Y2_IS_PCI_EXP
;
2125 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2129 if (status
& Y2_HWE_L1_MASK
)
2130 sky2_hw_error(hw
, 0, status
);
2132 if (status
& Y2_HWE_L1_MASK
)
2133 sky2_hw_error(hw
, 1, status
);
2136 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2138 struct net_device
*dev
= hw
->dev
[port
];
2139 struct sky2_port
*sky2
= netdev_priv(dev
);
2140 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2142 if (netif_msg_intr(sky2
))
2143 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2146 if (status
& GM_IS_RX_FF_OR
) {
2147 ++sky2
->net_stats
.rx_fifo_errors
;
2148 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2151 if (status
& GM_IS_TX_FF_UR
) {
2152 ++sky2
->net_stats
.tx_fifo_errors
;
2153 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2157 /* This should never happen it is a fatal situation */
2158 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2159 const char *rxtx
, u32 mask
)
2161 struct net_device
*dev
= hw
->dev
[port
];
2162 struct sky2_port
*sky2
= netdev_priv(dev
);
2165 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2166 dev
? dev
->name
: "<not registered>", rxtx
);
2168 imask
= sky2_read32(hw
, B0_IMSK
);
2170 sky2_write32(hw
, B0_IMSK
, imask
);
2173 spin_lock(&sky2
->phy_lock
);
2174 sky2_link_down(sky2
);
2175 spin_unlock(&sky2
->phy_lock
);
2179 /* If idle then force a fake soft NAPI poll once a second
2180 * to work around cases where sharing an edge triggered interrupt.
2182 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2184 if (idle_timeout
> 0)
2185 mod_timer(&hw
->idle_timer
,
2186 jiffies
+ msecs_to_jiffies(idle_timeout
));
2189 static void sky2_idle(unsigned long arg
)
2191 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2192 struct net_device
*dev
= hw
->dev
[0];
2194 if (__netif_rx_schedule_prep(dev
))
2195 __netif_rx_schedule(dev
);
2197 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2201 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2203 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2204 int work_limit
= min(dev0
->quota
, *budget
);
2206 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2208 if (status
& Y2_IS_HW_ERR
)
2211 if (status
& Y2_IS_IRQ_PHY1
)
2212 sky2_phy_intr(hw
, 0);
2214 if (status
& Y2_IS_IRQ_PHY2
)
2215 sky2_phy_intr(hw
, 1);
2217 if (status
& Y2_IS_IRQ_MAC1
)
2218 sky2_mac_intr(hw
, 0);
2220 if (status
& Y2_IS_IRQ_MAC2
)
2221 sky2_mac_intr(hw
, 1);
2223 if (status
& Y2_IS_CHK_RX1
)
2224 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2226 if (status
& Y2_IS_CHK_RX2
)
2227 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2229 if (status
& Y2_IS_CHK_TXA1
)
2230 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2232 if (status
& Y2_IS_CHK_TXA2
)
2233 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2235 work_done
= sky2_status_intr(hw
, work_limit
);
2236 if (work_done
< work_limit
) {
2237 netif_rx_complete(dev0
);
2239 sky2_read32(hw
, B0_Y2_SP_LISR
);
2242 *budget
-= work_done
;
2243 dev0
->quota
-= work_done
;
2248 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2250 struct sky2_hw
*hw
= dev_id
;
2251 struct net_device
*dev0
= hw
->dev
[0];
2254 /* Reading this mask interrupts as side effect */
2255 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2256 if (status
== 0 || status
== ~0)
2259 prefetch(&hw
->st_le
[hw
->st_idx
]);
2260 if (likely(__netif_rx_schedule_prep(dev0
)))
2261 __netif_rx_schedule(dev0
);
2266 #ifdef CONFIG_NET_POLL_CONTROLLER
2267 static void sky2_netpoll(struct net_device
*dev
)
2269 struct sky2_port
*sky2
= netdev_priv(dev
);
2270 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2272 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2273 __netif_rx_schedule(dev0
);
2277 /* Chip internal frequency for clock calculations */
2278 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2280 switch (hw
->chip_id
) {
2281 case CHIP_ID_YUKON_EC
:
2282 case CHIP_ID_YUKON_EC_U
:
2283 return 125; /* 125 Mhz */
2284 case CHIP_ID_YUKON_FE
:
2285 return 100; /* 100 Mhz */
2286 default: /* YUKON_XL */
2287 return 156; /* 156 Mhz */
2291 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2293 return sky2_mhz(hw
) * us
;
2296 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2298 return clk
/ sky2_mhz(hw
);
2302 static int sky2_reset(struct sky2_hw
*hw
)
2308 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2310 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2311 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2312 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2313 pci_name(hw
->pdev
), hw
->chip_id
);
2317 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2319 /* This rev is really old, and requires untested workarounds */
2320 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2321 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2322 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2323 hw
->chip_id
, hw
->chip_rev
);
2328 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2329 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2330 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2334 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2335 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2337 /* clear PCI errors, if any */
2338 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2340 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2341 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2344 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2346 /* clear any PEX errors */
2347 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2348 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2351 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2352 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2355 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2356 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2357 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2361 sky2_set_power_state(hw
, PCI_D0
);
2363 for (i
= 0; i
< hw
->ports
; i
++) {
2364 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2365 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2368 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2370 /* Clear I2C IRQ noise */
2371 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2373 /* turn off hardware timer (unused) */
2374 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2375 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2377 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2379 /* Turn off descriptor polling */
2380 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2382 /* Turn off receive timestamp */
2383 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2384 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2386 /* enable the Tx Arbiters */
2387 for (i
= 0; i
< hw
->ports
; i
++)
2388 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2390 /* Initialize ram interface */
2391 for (i
= 0; i
< hw
->ports
; i
++) {
2392 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2394 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2395 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2396 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2397 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2398 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2399 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2400 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2401 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2402 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2403 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2404 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2405 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2408 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2410 for (i
= 0; i
< hw
->ports
; i
++)
2411 sky2_phy_reset(hw
, i
);
2413 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2416 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2417 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2419 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2420 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2422 /* Set the list last index */
2423 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2425 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2426 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2428 /* set Status-FIFO ISR watermark */
2429 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2430 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2432 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2434 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2435 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2436 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2438 /* enable status unit */
2439 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2441 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2442 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2443 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2448 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2452 modes
= SUPPORTED_10baseT_Half
2453 | SUPPORTED_10baseT_Full
2454 | SUPPORTED_100baseT_Half
2455 | SUPPORTED_100baseT_Full
2456 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2458 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2459 modes
|= SUPPORTED_1000baseT_Half
2460 | SUPPORTED_1000baseT_Full
;
2462 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2463 | SUPPORTED_Autoneg
;
2467 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2469 struct sky2_port
*sky2
= netdev_priv(dev
);
2470 struct sky2_hw
*hw
= sky2
->hw
;
2472 ecmd
->transceiver
= XCVR_INTERNAL
;
2473 ecmd
->supported
= sky2_supported_modes(hw
);
2474 ecmd
->phy_address
= PHY_ADDR_MARV
;
2476 ecmd
->supported
= SUPPORTED_10baseT_Half
2477 | SUPPORTED_10baseT_Full
2478 | SUPPORTED_100baseT_Half
2479 | SUPPORTED_100baseT_Full
2480 | SUPPORTED_1000baseT_Half
2481 | SUPPORTED_1000baseT_Full
2482 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2483 ecmd
->port
= PORT_TP
;
2485 ecmd
->port
= PORT_FIBRE
;
2487 ecmd
->advertising
= sky2
->advertising
;
2488 ecmd
->autoneg
= sky2
->autoneg
;
2489 ecmd
->speed
= sky2
->speed
;
2490 ecmd
->duplex
= sky2
->duplex
;
2494 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2496 struct sky2_port
*sky2
= netdev_priv(dev
);
2497 const struct sky2_hw
*hw
= sky2
->hw
;
2498 u32 supported
= sky2_supported_modes(hw
);
2500 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2501 ecmd
->advertising
= supported
;
2507 switch (ecmd
->speed
) {
2509 if (ecmd
->duplex
== DUPLEX_FULL
)
2510 setting
= SUPPORTED_1000baseT_Full
;
2511 else if (ecmd
->duplex
== DUPLEX_HALF
)
2512 setting
= SUPPORTED_1000baseT_Half
;
2517 if (ecmd
->duplex
== DUPLEX_FULL
)
2518 setting
= SUPPORTED_100baseT_Full
;
2519 else if (ecmd
->duplex
== DUPLEX_HALF
)
2520 setting
= SUPPORTED_100baseT_Half
;
2526 if (ecmd
->duplex
== DUPLEX_FULL
)
2527 setting
= SUPPORTED_10baseT_Full
;
2528 else if (ecmd
->duplex
== DUPLEX_HALF
)
2529 setting
= SUPPORTED_10baseT_Half
;
2537 if ((setting
& supported
) == 0)
2540 sky2
->speed
= ecmd
->speed
;
2541 sky2
->duplex
= ecmd
->duplex
;
2544 sky2
->autoneg
= ecmd
->autoneg
;
2545 sky2
->advertising
= ecmd
->advertising
;
2547 if (netif_running(dev
))
2548 sky2_phy_reinit(sky2
);
2553 static void sky2_get_drvinfo(struct net_device
*dev
,
2554 struct ethtool_drvinfo
*info
)
2556 struct sky2_port
*sky2
= netdev_priv(dev
);
2558 strcpy(info
->driver
, DRV_NAME
);
2559 strcpy(info
->version
, DRV_VERSION
);
2560 strcpy(info
->fw_version
, "N/A");
2561 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2564 static const struct sky2_stat
{
2565 char name
[ETH_GSTRING_LEN
];
2568 { "tx_bytes", GM_TXO_OK_HI
},
2569 { "rx_bytes", GM_RXO_OK_HI
},
2570 { "tx_broadcast", GM_TXF_BC_OK
},
2571 { "rx_broadcast", GM_RXF_BC_OK
},
2572 { "tx_multicast", GM_TXF_MC_OK
},
2573 { "rx_multicast", GM_RXF_MC_OK
},
2574 { "tx_unicast", GM_TXF_UC_OK
},
2575 { "rx_unicast", GM_RXF_UC_OK
},
2576 { "tx_mac_pause", GM_TXF_MPAUSE
},
2577 { "rx_mac_pause", GM_RXF_MPAUSE
},
2578 { "collisions", GM_TXF_COL
},
2579 { "late_collision",GM_TXF_LAT_COL
},
2580 { "aborted", GM_TXF_ABO_COL
},
2581 { "single_collisions", GM_TXF_SNG_COL
},
2582 { "multi_collisions", GM_TXF_MUL_COL
},
2584 { "rx_short", GM_RXF_SHT
},
2585 { "rx_runt", GM_RXE_FRAG
},
2586 { "rx_64_byte_packets", GM_RXF_64B
},
2587 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2588 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2589 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2590 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2591 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2592 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2593 { "rx_too_long", GM_RXF_LNG_ERR
},
2594 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2595 { "rx_jabber", GM_RXF_JAB_PKT
},
2596 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2598 { "tx_64_byte_packets", GM_TXF_64B
},
2599 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2600 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2601 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2602 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2603 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2604 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2605 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2608 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2610 struct sky2_port
*sky2
= netdev_priv(dev
);
2612 return sky2
->rx_csum
;
2615 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2617 struct sky2_port
*sky2
= netdev_priv(dev
);
2619 sky2
->rx_csum
= data
;
2621 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2622 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2627 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2629 struct sky2_port
*sky2
= netdev_priv(netdev
);
2630 return sky2
->msg_enable
;
2633 static int sky2_nway_reset(struct net_device
*dev
)
2635 struct sky2_port
*sky2
= netdev_priv(dev
);
2637 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2640 sky2_phy_reinit(sky2
);
2645 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2647 struct sky2_hw
*hw
= sky2
->hw
;
2648 unsigned port
= sky2
->port
;
2651 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2652 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2653 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2654 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2656 for (i
= 2; i
< count
; i
++)
2657 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2660 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2662 struct sky2_port
*sky2
= netdev_priv(netdev
);
2663 sky2
->msg_enable
= value
;
2666 static int sky2_get_stats_count(struct net_device
*dev
)
2668 return ARRAY_SIZE(sky2_stats
);
2671 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2672 struct ethtool_stats
*stats
, u64
* data
)
2674 struct sky2_port
*sky2
= netdev_priv(dev
);
2676 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2679 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2683 switch (stringset
) {
2685 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2686 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2687 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2692 /* Use hardware MIB variables for critical path statistics and
2693 * transmit feedback not reported at interrupt.
2694 * Other errors are accounted for in interrupt handler.
2696 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2698 struct sky2_port
*sky2
= netdev_priv(dev
);
2701 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2703 sky2
->net_stats
.tx_bytes
= data
[0];
2704 sky2
->net_stats
.rx_bytes
= data
[1];
2705 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2706 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2707 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2708 sky2
->net_stats
.collisions
= data
[10];
2709 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2711 return &sky2
->net_stats
;
2714 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2716 struct sky2_port
*sky2
= netdev_priv(dev
);
2717 struct sky2_hw
*hw
= sky2
->hw
;
2718 unsigned port
= sky2
->port
;
2719 const struct sockaddr
*addr
= p
;
2721 if (!is_valid_ether_addr(addr
->sa_data
))
2722 return -EADDRNOTAVAIL
;
2724 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2725 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2726 dev
->dev_addr
, ETH_ALEN
);
2727 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2728 dev
->dev_addr
, ETH_ALEN
);
2730 /* virtual address for data */
2731 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2733 /* physical address: used for pause frames */
2734 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2739 static void sky2_set_multicast(struct net_device
*dev
)
2741 struct sky2_port
*sky2
= netdev_priv(dev
);
2742 struct sky2_hw
*hw
= sky2
->hw
;
2743 unsigned port
= sky2
->port
;
2744 struct dev_mc_list
*list
= dev
->mc_list
;
2748 memset(filter
, 0, sizeof(filter
));
2750 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2751 reg
|= GM_RXCR_UCF_ENA
;
2753 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2754 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2755 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2756 memset(filter
, 0xff, sizeof(filter
));
2757 else if (dev
->mc_count
== 0) /* no multicast */
2758 reg
&= ~GM_RXCR_MCF_ENA
;
2761 reg
|= GM_RXCR_MCF_ENA
;
2763 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2764 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2765 filter
[bit
/ 8] |= 1 << (bit
% 8);
2769 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2770 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2771 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2772 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2773 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2774 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2775 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2776 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2778 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2781 /* Can have one global because blinking is controlled by
2782 * ethtool and that is always under RTNL mutex
2784 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2788 switch (hw
->chip_id
) {
2789 case CHIP_ID_YUKON_XL
:
2790 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2791 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2792 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2793 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2794 PHY_M_LEDC_INIT_CTRL(7) |
2795 PHY_M_LEDC_STA1_CTRL(7) |
2796 PHY_M_LEDC_STA0_CTRL(7))
2799 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2803 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2804 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2805 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2806 PHY_M_LED_MO_10(MO_LED_ON
) |
2807 PHY_M_LED_MO_100(MO_LED_ON
) |
2808 PHY_M_LED_MO_1000(MO_LED_ON
) |
2809 PHY_M_LED_MO_RX(MO_LED_ON
)
2810 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2811 PHY_M_LED_MO_10(MO_LED_OFF
) |
2812 PHY_M_LED_MO_100(MO_LED_OFF
) |
2813 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2814 PHY_M_LED_MO_RX(MO_LED_OFF
));
2819 /* blink LED's for finding board */
2820 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2822 struct sky2_port
*sky2
= netdev_priv(dev
);
2823 struct sky2_hw
*hw
= sky2
->hw
;
2824 unsigned port
= sky2
->port
;
2825 u16 ledctrl
, ledover
= 0;
2830 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2831 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2835 /* save initial values */
2836 spin_lock_bh(&sky2
->phy_lock
);
2837 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2838 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2839 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2840 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2841 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2843 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2844 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2848 while (!interrupted
&& ms
> 0) {
2849 sky2_led(hw
, port
, onoff
);
2852 spin_unlock_bh(&sky2
->phy_lock
);
2853 interrupted
= msleep_interruptible(250);
2854 spin_lock_bh(&sky2
->phy_lock
);
2859 /* resume regularly scheduled programming */
2860 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2861 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2862 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2863 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2864 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2866 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2867 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2869 spin_unlock_bh(&sky2
->phy_lock
);
2874 static void sky2_get_pauseparam(struct net_device
*dev
,
2875 struct ethtool_pauseparam
*ecmd
)
2877 struct sky2_port
*sky2
= netdev_priv(dev
);
2879 ecmd
->tx_pause
= sky2
->tx_pause
;
2880 ecmd
->rx_pause
= sky2
->rx_pause
;
2881 ecmd
->autoneg
= sky2
->autoneg
;
2884 static int sky2_set_pauseparam(struct net_device
*dev
,
2885 struct ethtool_pauseparam
*ecmd
)
2887 struct sky2_port
*sky2
= netdev_priv(dev
);
2890 sky2
->autoneg
= ecmd
->autoneg
;
2891 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2892 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2894 sky2_phy_reinit(sky2
);
2899 static int sky2_get_coalesce(struct net_device
*dev
,
2900 struct ethtool_coalesce
*ecmd
)
2902 struct sky2_port
*sky2
= netdev_priv(dev
);
2903 struct sky2_hw
*hw
= sky2
->hw
;
2905 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2906 ecmd
->tx_coalesce_usecs
= 0;
2908 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2909 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2911 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2913 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2914 ecmd
->rx_coalesce_usecs
= 0;
2916 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2917 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2919 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2921 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2922 ecmd
->rx_coalesce_usecs_irq
= 0;
2924 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2925 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2928 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2933 /* Note: this affect both ports */
2934 static int sky2_set_coalesce(struct net_device
*dev
,
2935 struct ethtool_coalesce
*ecmd
)
2937 struct sky2_port
*sky2
= netdev_priv(dev
);
2938 struct sky2_hw
*hw
= sky2
->hw
;
2939 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
2941 if (ecmd
->tx_coalesce_usecs
> tmax
||
2942 ecmd
->rx_coalesce_usecs
> tmax
||
2943 ecmd
->rx_coalesce_usecs_irq
> tmax
)
2946 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2948 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2950 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2953 if (ecmd
->tx_coalesce_usecs
== 0)
2954 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2956 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2957 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2958 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2960 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2962 if (ecmd
->rx_coalesce_usecs
== 0)
2963 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2965 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2966 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2967 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2969 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2971 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2972 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2974 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2975 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2976 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2978 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2982 static void sky2_get_ringparam(struct net_device
*dev
,
2983 struct ethtool_ringparam
*ering
)
2985 struct sky2_port
*sky2
= netdev_priv(dev
);
2987 ering
->rx_max_pending
= RX_MAX_PENDING
;
2988 ering
->rx_mini_max_pending
= 0;
2989 ering
->rx_jumbo_max_pending
= 0;
2990 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2992 ering
->rx_pending
= sky2
->rx_pending
;
2993 ering
->rx_mini_pending
= 0;
2994 ering
->rx_jumbo_pending
= 0;
2995 ering
->tx_pending
= sky2
->tx_pending
;
2998 static int sky2_set_ringparam(struct net_device
*dev
,
2999 struct ethtool_ringparam
*ering
)
3001 struct sky2_port
*sky2
= netdev_priv(dev
);
3004 if (ering
->rx_pending
> RX_MAX_PENDING
||
3005 ering
->rx_pending
< 8 ||
3006 ering
->tx_pending
< MAX_SKB_TX_LE
||
3007 ering
->tx_pending
> TX_RING_SIZE
- 1)
3010 if (netif_running(dev
))
3013 sky2
->rx_pending
= ering
->rx_pending
;
3014 sky2
->tx_pending
= ering
->tx_pending
;
3016 if (netif_running(dev
)) {
3021 sky2_set_multicast(dev
);
3027 static int sky2_get_regs_len(struct net_device
*dev
)
3033 * Returns copy of control register region
3034 * Note: access to the RAM address register set will cause timeouts.
3036 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3039 const struct sky2_port
*sky2
= netdev_priv(dev
);
3040 const void __iomem
*io
= sky2
->hw
->regs
;
3042 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3044 memset(p
, 0, regs
->len
);
3046 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3048 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3050 regs
->len
- B3_RI_WTO_R1
);
3053 static struct ethtool_ops sky2_ethtool_ops
= {
3054 .get_settings
= sky2_get_settings
,
3055 .set_settings
= sky2_set_settings
,
3056 .get_drvinfo
= sky2_get_drvinfo
,
3057 .get_msglevel
= sky2_get_msglevel
,
3058 .set_msglevel
= sky2_set_msglevel
,
3059 .nway_reset
= sky2_nway_reset
,
3060 .get_regs_len
= sky2_get_regs_len
,
3061 .get_regs
= sky2_get_regs
,
3062 .get_link
= ethtool_op_get_link
,
3063 .get_sg
= ethtool_op_get_sg
,
3064 .set_sg
= ethtool_op_set_sg
,
3065 .get_tx_csum
= ethtool_op_get_tx_csum
,
3066 .set_tx_csum
= ethtool_op_set_tx_csum
,
3067 .get_tso
= ethtool_op_get_tso
,
3068 .set_tso
= ethtool_op_set_tso
,
3069 .get_rx_csum
= sky2_get_rx_csum
,
3070 .set_rx_csum
= sky2_set_rx_csum
,
3071 .get_strings
= sky2_get_strings
,
3072 .get_coalesce
= sky2_get_coalesce
,
3073 .set_coalesce
= sky2_set_coalesce
,
3074 .get_ringparam
= sky2_get_ringparam
,
3075 .set_ringparam
= sky2_set_ringparam
,
3076 .get_pauseparam
= sky2_get_pauseparam
,
3077 .set_pauseparam
= sky2_set_pauseparam
,
3078 .phys_id
= sky2_phys_id
,
3079 .get_stats_count
= sky2_get_stats_count
,
3080 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3081 .get_perm_addr
= ethtool_op_get_perm_addr
,
3084 /* Initialize network device */
3085 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3086 unsigned port
, int highmem
)
3088 struct sky2_port
*sky2
;
3089 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3092 printk(KERN_ERR
"sky2 etherdev alloc failed");
3096 SET_MODULE_OWNER(dev
);
3097 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3098 dev
->irq
= hw
->pdev
->irq
;
3099 dev
->open
= sky2_up
;
3100 dev
->stop
= sky2_down
;
3101 dev
->do_ioctl
= sky2_ioctl
;
3102 dev
->hard_start_xmit
= sky2_xmit_frame
;
3103 dev
->get_stats
= sky2_get_stats
;
3104 dev
->set_multicast_list
= sky2_set_multicast
;
3105 dev
->set_mac_address
= sky2_set_mac_address
;
3106 dev
->change_mtu
= sky2_change_mtu
;
3107 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3108 dev
->tx_timeout
= sky2_tx_timeout
;
3109 dev
->watchdog_timeo
= TX_WATCHDOG
;
3111 dev
->poll
= sky2_poll
;
3112 dev
->weight
= NAPI_WEIGHT
;
3113 #ifdef CONFIG_NET_POLL_CONTROLLER
3114 dev
->poll_controller
= sky2_netpoll
;
3117 sky2
= netdev_priv(dev
);
3120 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3122 spin_lock_init(&sky2
->tx_lock
);
3123 /* Auto speed and flow control */
3124 sky2
->autoneg
= AUTONEG_ENABLE
;
3129 sky2
->advertising
= sky2_supported_modes(hw
);
3132 spin_lock_init(&sky2
->phy_lock
);
3133 sky2
->tx_pending
= TX_DEF_PENDING
;
3134 sky2
->rx_pending
= RX_DEF_PENDING
;
3135 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3137 hw
->dev
[port
] = dev
;
3141 dev
->features
|= NETIF_F_LLTX
;
3142 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3143 dev
->features
|= NETIF_F_TSO
;
3145 dev
->features
|= NETIF_F_HIGHDMA
;
3146 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3148 #ifdef SKY2_VLAN_TAG_USED
3149 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3150 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3151 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3154 /* read the mac address */
3155 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3156 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3158 /* device is off until link detection */
3159 netif_carrier_off(dev
);
3160 netif_stop_queue(dev
);
3165 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3167 const struct sky2_port
*sky2
= netdev_priv(dev
);
3169 if (netif_msg_probe(sky2
))
3170 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3172 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3173 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3176 /* Handle software interrupt used during MSI test */
3177 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3178 struct pt_regs
*regs
)
3180 struct sky2_hw
*hw
= dev_id
;
3181 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3186 if (status
& Y2_IS_IRQ_SW
) {
3187 hw
->msi_detected
= 1;
3188 wake_up(&hw
->msi_wait
);
3189 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3191 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3196 /* Test interrupt path by forcing a a software IRQ */
3197 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3199 struct pci_dev
*pdev
= hw
->pdev
;
3202 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3204 err
= request_irq(pdev
->irq
, sky2_test_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3206 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3207 pci_name(pdev
), pdev
->irq
);
3211 init_waitqueue_head (&hw
->msi_wait
);
3213 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3216 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3218 if (!hw
->msi_detected
) {
3219 /* MSI test failed, go back to INTx mode */
3220 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3221 "switching to INTx mode. Please report this failure to "
3222 "the PCI maintainer and include system chipset information.\n",
3226 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3229 sky2_write32(hw
, B0_IMSK
, 0);
3231 free_irq(pdev
->irq
, hw
);
3236 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3237 const struct pci_device_id
*ent
)
3239 struct net_device
*dev
, *dev1
= NULL
;
3241 int err
, pm_cap
, using_dac
= 0;
3243 err
= pci_enable_device(pdev
);
3245 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3250 err
= pci_request_regions(pdev
, DRV_NAME
);
3252 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3257 pci_set_master(pdev
);
3259 /* Find power-management capability. */
3260 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3262 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3265 goto err_out_free_regions
;
3268 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3269 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3271 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3273 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3274 "for consistent allocations\n", pci_name(pdev
));
3275 goto err_out_free_regions
;
3279 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3281 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3283 goto err_out_free_regions
;
3288 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3290 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3292 goto err_out_free_regions
;
3297 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3299 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3301 goto err_out_free_hw
;
3303 hw
->pm_cap
= pm_cap
;
3306 /* byte swap descriptors in hardware */
3310 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3311 reg
|= PCI_REV_DESC
;
3312 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3316 /* ring for status responses */
3317 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3320 goto err_out_iounmap
;
3322 err
= sky2_reset(hw
);
3324 goto err_out_iounmap
;
3326 printk(KERN_INFO PFX
"v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3327 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3328 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3329 hw
->chip_id
, hw
->chip_rev
);
3331 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3333 goto err_out_free_pci
;
3335 err
= register_netdev(dev
);
3337 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3339 goto err_out_free_netdev
;
3342 sky2_show_addr(dev
);
3344 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3345 if (register_netdev(dev1
) == 0)
3346 sky2_show_addr(dev1
);
3348 /* Failure to register second port need not be fatal */
3349 printk(KERN_WARNING PFX
3350 "register of second port failed\n");
3356 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3357 err
= sky2_test_msi(hw
);
3358 if (err
== -EOPNOTSUPP
)
3359 pci_disable_msi(pdev
);
3361 goto err_out_unregister
;
3364 err
= request_irq(pdev
->irq
, sky2_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3366 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3367 pci_name(pdev
), pdev
->irq
);
3368 goto err_out_unregister
;
3371 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3373 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3374 sky2_idle_start(hw
);
3376 pci_set_drvdata(pdev
, hw
);
3381 pci_disable_msi(pdev
);
3383 unregister_netdev(dev1
);
3386 unregister_netdev(dev
);
3387 err_out_free_netdev
:
3390 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3391 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3396 err_out_free_regions
:
3397 pci_release_regions(pdev
);
3398 pci_disable_device(pdev
);
3403 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3405 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3406 struct net_device
*dev0
, *dev1
;
3411 del_timer_sync(&hw
->idle_timer
);
3413 sky2_write32(hw
, B0_IMSK
, 0);
3414 synchronize_irq(hw
->pdev
->irq
);
3419 unregister_netdev(dev1
);
3420 unregister_netdev(dev0
);
3422 sky2_set_power_state(hw
, PCI_D3hot
);
3423 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3424 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3425 sky2_read8(hw
, B0_CTST
);
3427 free_irq(pdev
->irq
, hw
);
3428 pci_disable_msi(pdev
);
3429 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3430 pci_release_regions(pdev
);
3431 pci_disable_device(pdev
);
3439 pci_set_drvdata(pdev
, NULL
);
3443 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3445 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3447 pci_power_t pstate
= pci_choose_state(pdev
, state
);
3449 if (!(pstate
== PCI_D3hot
|| pstate
== PCI_D3cold
))
3452 del_timer_sync(&hw
->idle_timer
);
3453 netif_poll_disable(hw
->dev
[0]);
3455 for (i
= 0; i
< hw
->ports
; i
++) {
3456 struct net_device
*dev
= hw
->dev
[i
];
3458 if (netif_running(dev
)) {
3460 netif_device_detach(dev
);
3464 sky2_write32(hw
, B0_IMSK
, 0);
3465 pci_save_state(pdev
);
3466 sky2_set_power_state(hw
, pstate
);
3470 static int sky2_resume(struct pci_dev
*pdev
)
3472 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3475 pci_restore_state(pdev
);
3476 pci_enable_wake(pdev
, PCI_D0
, 0);
3477 sky2_set_power_state(hw
, PCI_D0
);
3479 err
= sky2_reset(hw
);
3483 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3485 for (i
= 0; i
< hw
->ports
; i
++) {
3486 struct net_device
*dev
= hw
->dev
[i
];
3487 if (netif_running(dev
)) {
3488 netif_device_attach(dev
);
3492 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3500 netif_poll_enable(hw
->dev
[0]);
3501 sky2_idle_start(hw
);
3507 static struct pci_driver sky2_driver
= {
3509 .id_table
= sky2_id_table
,
3510 .probe
= sky2_probe
,
3511 .remove
= __devexit_p(sky2_remove
),
3513 .suspend
= sky2_suspend
,
3514 .resume
= sky2_resume
,
3518 static int __init
sky2_init_module(void)
3520 return pci_register_driver(&sky2_driver
);
3523 static void __exit
sky2_cleanup_module(void)
3525 pci_unregister_driver(&sky2_driver
);
3528 module_init(sky2_init_module
);
3529 module_exit(sky2_cleanup_module
);
3531 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3532 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3533 MODULE_LICENSE("GPL");
3534 MODULE_VERSION(DRV_VERSION
);