2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.4"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
63 #define RX_LE_SIZE 512
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define ETH_JUMBO_MTU 9000
77 #define TX_WATCHDOG (5 * HZ)
78 #define NAPI_WEIGHT 64
79 #define PHY_RETRIES 1000
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83 static const u32 default_msg
=
84 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
85 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
88 static int debug
= -1; /* defaults above */
89 module_param(debug
, int, 0);
90 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
92 static int copybreak __read_mostly
= 256;
93 module_param(copybreak
, int, 0);
94 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
96 static int disable_msi
= 0;
97 module_param(disable_msi
, int, 0);
98 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
100 static int idle_timeout
= 100;
101 module_param(idle_timeout
, int, 0);
102 MODULE_PARM_DESC(idle_timeout
, "Idle timeout workaround for lost interrupts (ms)");
104 static const struct pci_device_id sky2_id_table
[] = {
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
126 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
130 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
131 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
133 /* This driver supports yukon2 chipset only */
134 static const char *yukon2_name
[] = {
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
142 /* Access to external PHY */
143 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
147 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
148 gma_write16(hw
, port
, GM_SMI_CTRL
,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
151 for (i
= 0; i
< PHY_RETRIES
; i
++) {
152 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
157 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
161 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
165 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
166 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
168 for (i
= 0; i
< PHY_RETRIES
; i
++) {
169 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
170 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
180 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
184 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
185 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
189 static void sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
195 pr_debug("sky2_set_power_state %d\n", state
);
196 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
198 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
199 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
200 (power_control
& PCI_PM_CAP_PME_D3cold
);
202 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
204 power_control
|= PCI_PM_CTRL_PME_STATUS
;
205 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw
, B0_POWER_CTRL
,
211 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
213 /* disable Core Clock Division, */
214 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
216 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
217 /* enable bits are inverted */
218 sky2_write8(hw
, B2_Y2_CLK_GATE
,
219 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
220 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
221 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
223 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
225 /* Turn off phy power saving */
226 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
227 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
229 /* looks like this XL is back asswards .. */
230 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
231 reg1
|= PCI_Y2_PHY1_COMA
;
233 reg1
|= PCI_Y2_PHY2_COMA
;
236 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
237 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
238 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
239 reg1
&= P_ASPM_CONTROL_MSK
;
240 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
241 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
244 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
251 /* Turn on phy power saving */
252 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
253 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
254 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
256 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
257 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
260 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
261 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
263 /* enable bits are inverted */
264 sky2_write8(hw
, B2_Y2_CLK_GATE
,
265 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
266 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
267 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
269 /* switch power to VAUX */
270 if (vaux
&& state
!= PCI_D3cold
)
271 sky2_write8(hw
, B0_POWER_CTRL
,
272 (PC_VAUX_ENA
| PC_VCC_ENA
|
273 PC_VAUX_ON
| PC_VCC_OFF
));
276 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
279 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
280 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
283 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
287 /* disable all GMAC IRQ's */
288 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
289 /* disable PHY IRQs */
290 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
292 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
293 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
294 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
295 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
297 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
298 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
299 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
302 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
304 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
305 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
307 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
308 !(hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
309 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
311 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
313 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
315 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
316 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
318 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
320 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
323 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
325 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
326 /* enable automatic crossover */
327 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
329 /* disable energy detect */
330 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
332 /* enable automatic crossover */
333 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
335 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
336 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
337 ctrl
&= ~PHY_M_PC_DSC_MSK
;
338 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
341 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
343 /* workaround for deviation #4.88 (CRC errors) */
344 /* disable Automatic Crossover */
346 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
347 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
349 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
350 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
351 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
352 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
353 ctrl
&= ~PHY_M_MAC_MD_MSK
;
354 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
355 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
357 /* select page 1 to access Fiber registers */
358 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
362 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
363 if (sky2
->autoneg
== AUTONEG_DISABLE
)
368 ctrl
|= PHY_CT_RESET
;
369 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
375 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
377 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
378 ct1000
|= PHY_M_1000C_AFD
;
379 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
380 ct1000
|= PHY_M_1000C_AHD
;
381 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
382 adv
|= PHY_M_AN_100_FD
;
383 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
384 adv
|= PHY_M_AN_100_HD
;
385 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
386 adv
|= PHY_M_AN_10_FD
;
387 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
388 adv
|= PHY_M_AN_10_HD
;
389 } else /* special defines for FIBER (88E1011S only) */
390 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
392 /* Set Flow-control capabilities */
393 if (sky2
->tx_pause
&& sky2
->rx_pause
)
394 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
395 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
396 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
397 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
398 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
400 /* Restart Auto-negotiation */
401 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
403 /* forced speed/duplex settings */
404 ct1000
= PHY_M_1000C_MSE
;
406 if (sky2
->duplex
== DUPLEX_FULL
)
407 ctrl
|= PHY_CT_DUP_MD
;
409 switch (sky2
->speed
) {
411 ctrl
|= PHY_CT_SP1000
;
414 ctrl
|= PHY_CT_SP100
;
418 ctrl
|= PHY_CT_RESET
;
421 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
422 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
424 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
425 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
427 /* Setup Phy LED's */
428 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
431 switch (hw
->chip_id
) {
432 case CHIP_ID_YUKON_FE
:
433 /* on 88E3082 these bits are at 11..9 (shifted left) */
434 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
436 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
438 /* delete ACT LED control bits */
439 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
440 /* change ACT LED control to blink mode */
441 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
442 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
445 case CHIP_ID_YUKON_XL
:
446 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
448 /* select page 3 to access LED control register */
449 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
451 /* set LED Function Control register */
452 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
453 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
454 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
455 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
456 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
458 /* set Polarity Control register */
459 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
460 (PHY_M_POLC_LS1_P_MIX(4) |
461 PHY_M_POLC_IS0_P_MIX(4) |
462 PHY_M_POLC_LOS_CTRL(2) |
463 PHY_M_POLC_INIT_CTRL(2) |
464 PHY_M_POLC_STA1_CTRL(2) |
465 PHY_M_POLC_STA0_CTRL(2)));
467 /* restore page register */
468 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
470 case CHIP_ID_YUKON_EC_U
:
471 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
473 /* select page 3 to access LED control register */
474 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
476 /* set LED Function Control register */
477 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
478 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
479 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
480 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
481 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
483 /* set Blink Rate in LED Timer Control Register */
484 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
485 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
486 /* restore page register */
487 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
491 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
492 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
493 /* turn off the Rx LED (LED_RX) */
494 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
497 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
498 /* apply fixes in PHY AFE */
499 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
500 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
502 /* increase differential signal amplitude in 10BASE-T */
503 gm_phy_write(hw
, port
, 0x18, 0xaa99);
504 gm_phy_write(hw
, port
, 0x17, 0x2011);
506 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
507 gm_phy_write(hw
, port
, 0x18, 0xa204);
508 gm_phy_write(hw
, port
, 0x17, 0x2002);
510 /* set page register to 0 */
511 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
513 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
515 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
516 /* turn on 100 Mbps LED (LED_LINK100) */
517 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
521 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
524 /* Enable phy interrupt on auto-negotiation complete (or link up) */
525 if (sky2
->autoneg
== AUTONEG_ENABLE
)
526 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
528 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
531 /* Force a renegotiation */
532 static void sky2_phy_reinit(struct sky2_port
*sky2
)
534 spin_lock_bh(&sky2
->phy_lock
);
535 sky2_phy_init(sky2
->hw
, sky2
->port
);
536 spin_unlock_bh(&sky2
->phy_lock
);
539 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
541 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
544 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
546 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
547 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
549 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
551 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
552 /* WA DEV_472 -- looks like crossed wires on port 2 */
553 /* clear GMAC 1 Control reset */
554 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
556 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
557 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
558 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
559 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
560 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
563 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
564 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
565 reg
|= GM_GPCR_AU_ALL_DIS
;
566 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
567 gma_read16(hw
, port
, GM_GP_CTRL
);
569 switch (sky2
->speed
) {
571 reg
&= ~GM_GPCR_SPEED_100
;
572 reg
|= GM_GPCR_SPEED_1000
;
575 reg
&= ~GM_GPCR_SPEED_1000
;
576 reg
|= GM_GPCR_SPEED_100
;
579 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
583 if (sky2
->duplex
== DUPLEX_FULL
)
584 reg
|= GM_GPCR_DUP_FULL
;
586 /* turn off pause in 10/100mbps half duplex */
587 else if (sky2
->speed
!= SPEED_1000
&&
588 hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
589 sky2
->tx_pause
= sky2
->rx_pause
= 0;
591 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
593 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
594 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
596 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
597 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
598 /* disable Rx flow-control */
599 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
602 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
604 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
606 spin_lock_bh(&sky2
->phy_lock
);
607 sky2_phy_init(hw
, port
);
608 spin_unlock_bh(&sky2
->phy_lock
);
611 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
612 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
614 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
615 gma_read16(hw
, port
, i
);
616 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
618 /* transmit control */
619 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
621 /* receive control reg: unicast + multicast + no FCS */
622 gma_write16(hw
, port
, GM_RX_CTRL
,
623 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
625 /* transmit flow control */
626 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
628 /* transmit parameter */
629 gma_write16(hw
, port
, GM_TX_PARAM
,
630 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
631 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
632 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
633 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
635 /* serial mode register */
636 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
637 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
639 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
640 reg
|= GM_SMOD_JUMBO_ENA
;
642 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
644 /* virtual address for data */
645 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
647 /* physical address: used for pause frames */
648 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
650 /* ignore counter overflows */
651 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
652 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
653 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
655 /* Configure Rx MAC FIFO */
656 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
657 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
658 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
660 /* Flush Rx MAC FIFO on any flow control or error */
661 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
663 /* Set threshold to 0xa (64 bytes)
664 * ASF disabled so no need to do WA dev #4.30
666 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
668 /* Configure Tx MAC FIFO */
669 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
670 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
672 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
673 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
674 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
675 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
676 /* set Tx GMAC FIFO Almost Empty Threshold */
677 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
678 /* Disable Store & Forward mode for TX */
679 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
685 /* Assign Ram Buffer allocation.
686 * start and end are in units of 4k bytes
687 * ram registers are in units of 64bit words
689 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
693 start
= startk
* 4096/8;
694 end
= (endk
* 4096/8) - 1;
696 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
697 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
698 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
699 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
700 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
702 if (q
== Q_R1
|| q
== Q_R2
) {
703 u32 space
= (endk
- startk
) * 4096/8;
704 u32 tp
= space
- space
/4;
706 /* On receive queue's set the thresholds
707 * give receiver priority when > 3/4 full
708 * send pause when down to 2K
710 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
711 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
714 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
715 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
717 /* Enable store & forward on Tx queue's because
718 * Tx FIFO is only 1K on Yukon
720 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
723 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
724 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
727 /* Setup Bus Memory Interface */
728 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
730 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
731 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
732 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
733 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
736 /* Setup prefetch unit registers. This is the interface between
737 * hardware and driver list elements
739 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
742 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
743 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
744 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
745 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
746 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
747 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
749 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
752 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
754 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
756 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
760 /* Update chip's next pointer */
761 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
764 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
769 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
771 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
772 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
776 /* Return high part of DMA address (could be 32 or 64 bit) */
777 static inline u32
high32(dma_addr_t a
)
779 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
782 /* Build description to hardware about buffer */
783 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
785 struct sky2_rx_le
*le
;
786 u32 hi
= high32(map
);
787 u16 len
= sky2
->rx_bufsize
;
789 if (sky2
->rx_addr64
!= hi
) {
790 le
= sky2_next_rx(sky2
);
791 le
->addr
= cpu_to_le32(hi
);
793 le
->opcode
= OP_ADDR64
| HW_OWNER
;
794 sky2
->rx_addr64
= high32(map
+ len
);
797 le
= sky2_next_rx(sky2
);
798 le
->addr
= cpu_to_le32((u32
) map
);
799 le
->length
= cpu_to_le16(len
);
801 le
->opcode
= OP_PACKET
| HW_OWNER
;
805 /* Tell chip where to start receive checksum.
806 * Actually has two checksums, but set both same to avoid possible byte
809 static void rx_set_checksum(struct sky2_port
*sky2
)
811 struct sky2_rx_le
*le
;
813 le
= sky2_next_rx(sky2
);
814 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
816 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
818 sky2_write32(sky2
->hw
,
819 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
820 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
825 * The RX Stop command will not work for Yukon-2 if the BMU does not
826 * reach the end of packet and since we can't make sure that we have
827 * incoming data, we must reset the BMU while it is not doing a DMA
828 * transfer. Since it is possible that the RX path is still active,
829 * the RX RAM buffer will be stopped first, so any possible incoming
830 * data will not trigger a DMA. After the RAM buffer is stopped, the
831 * BMU is polled until any DMA in progress is ended and only then it
834 static void sky2_rx_stop(struct sky2_port
*sky2
)
836 struct sky2_hw
*hw
= sky2
->hw
;
837 unsigned rxq
= rxqaddr
[sky2
->port
];
840 /* disable the RAM Buffer receive queue */
841 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
843 for (i
= 0; i
< 0xffff; i
++)
844 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
845 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
848 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
851 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
853 /* reset the Rx prefetch unit */
854 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
857 /* Clean out receive buffer area, assumes receiver hardware stopped */
858 static void sky2_rx_clean(struct sky2_port
*sky2
)
862 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
863 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
864 struct ring_info
*re
= sky2
->rx_ring
+ i
;
867 pci_unmap_single(sky2
->hw
->pdev
,
868 re
->mapaddr
, sky2
->rx_bufsize
,
876 /* Basic MII support */
877 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
879 struct mii_ioctl_data
*data
= if_mii(ifr
);
880 struct sky2_port
*sky2
= netdev_priv(dev
);
881 struct sky2_hw
*hw
= sky2
->hw
;
882 int err
= -EOPNOTSUPP
;
884 if (!netif_running(dev
))
885 return -ENODEV
; /* Phy still in reset */
889 data
->phy_id
= PHY_ADDR_MARV
;
895 spin_lock_bh(&sky2
->phy_lock
);
896 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
897 spin_unlock_bh(&sky2
->phy_lock
);
904 if (!capable(CAP_NET_ADMIN
))
907 spin_lock_bh(&sky2
->phy_lock
);
908 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
910 spin_unlock_bh(&sky2
->phy_lock
);
916 #ifdef SKY2_VLAN_TAG_USED
917 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
919 struct sky2_port
*sky2
= netdev_priv(dev
);
920 struct sky2_hw
*hw
= sky2
->hw
;
921 u16 port
= sky2
->port
;
923 spin_lock_bh(&sky2
->tx_lock
);
925 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
926 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
929 spin_unlock_bh(&sky2
->tx_lock
);
932 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
934 struct sky2_port
*sky2
= netdev_priv(dev
);
935 struct sky2_hw
*hw
= sky2
->hw
;
936 u16 port
= sky2
->port
;
938 spin_lock_bh(&sky2
->tx_lock
);
940 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
941 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
943 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
945 spin_unlock_bh(&sky2
->tx_lock
);
950 * It appears the hardware has a bug in the FIFO logic that
951 * cause it to hang if the FIFO gets overrun and the receive buffer
952 * is not aligned. ALso alloc_skb() won't align properly if slab
953 * debugging is enabled.
955 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
959 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
961 unsigned long p
= (unsigned long) skb
->data
;
962 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
969 * Allocate and setup receiver buffer pool.
970 * In case of 64 bit dma, there are 2X as many list elements
971 * available as ring entries
972 * and need to reserve one list element so we don't wrap around.
974 static int sky2_rx_start(struct sky2_port
*sky2
)
976 struct sky2_hw
*hw
= sky2
->hw
;
977 unsigned rxq
= rxqaddr
[sky2
->port
];
981 sky2
->rx_put
= sky2
->rx_next
= 0;
984 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
985 /* MAC Rx RAM Read is controlled by hardware */
986 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
989 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
991 rx_set_checksum(sky2
);
992 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
993 struct ring_info
*re
= sky2
->rx_ring
+ i
;
995 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
999 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
1000 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1001 sky2_rx_add(sky2
, re
->mapaddr
);
1006 * The receiver hangs if it receives frames larger than the
1007 * packet buffer. As a workaround, truncate oversize frames, but
1008 * the register is limited to 9 bits, so if you do frames > 2052
1009 * you better get the MTU right!
1011 thresh
= (sky2
->rx_bufsize
- 8) / sizeof(u32
);
1013 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1015 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1016 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1020 /* Tell chip about available buffers */
1021 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1024 sky2_rx_clean(sky2
);
1028 /* Bring up network interface. */
1029 static int sky2_up(struct net_device
*dev
)
1031 struct sky2_port
*sky2
= netdev_priv(dev
);
1032 struct sky2_hw
*hw
= sky2
->hw
;
1033 unsigned port
= sky2
->port
;
1034 u32 ramsize
, rxspace
, imask
;
1035 int cap
, err
= -ENOMEM
;
1036 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1039 * On dual port PCI-X card, there is an problem where status
1040 * can be received out of order due to split transactions
1042 if (otherdev
&& netif_running(otherdev
) &&
1043 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1044 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1047 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1048 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1049 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1055 if (netif_msg_ifup(sky2
))
1056 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1058 /* must be power of 2 */
1059 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1061 sizeof(struct sky2_tx_le
),
1066 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1070 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1072 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1076 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1078 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1083 sky2_mac_init(hw
, port
);
1085 /* Determine available ram buffer space (in 4K blocks).
1086 * Note: not sure about the FE setting below yet
1088 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1091 ramsize
= sky2_read8(hw
, B2_E_0
);
1093 /* Give transmitter one third (rounded up) */
1094 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1096 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1097 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1099 /* Make sure SyncQ is disabled */
1100 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1103 sky2_qset(hw
, txqaddr
[port
]);
1105 /* Set almost empty threshold */
1106 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== 1)
1107 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1109 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1112 err
= sky2_rx_start(sky2
);
1116 /* Enable interrupts from phy/mac for port */
1117 imask
= sky2_read32(hw
, B0_IMSK
);
1118 imask
|= portirq_msk
[port
];
1119 sky2_write32(hw
, B0_IMSK
, imask
);
1125 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1126 sky2
->rx_le
, sky2
->rx_le_map
);
1130 pci_free_consistent(hw
->pdev
,
1131 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1132 sky2
->tx_le
, sky2
->tx_le_map
);
1135 kfree(sky2
->tx_ring
);
1136 kfree(sky2
->rx_ring
);
1138 sky2
->tx_ring
= NULL
;
1139 sky2
->rx_ring
= NULL
;
1143 /* Modular subtraction in ring */
1144 static inline int tx_dist(unsigned tail
, unsigned head
)
1146 return (head
- tail
) & (TX_RING_SIZE
- 1);
1149 /* Number of list elements available for next tx */
1150 static inline int tx_avail(const struct sky2_port
*sky2
)
1152 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1155 /* Estimate of number of transmit list elements required */
1156 static unsigned tx_le_req(const struct sk_buff
*skb
)
1160 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1161 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1163 if (skb_is_gso(skb
))
1166 if (skb
->ip_summed
== CHECKSUM_HW
)
1173 * Put one packet in ring for transmit.
1174 * A single packet can generate multiple list elements, and
1175 * the number of ring elements will probably be less than the number
1176 * of list elements used.
1178 * No BH disabling for tx_lock here (like tg3)
1180 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1182 struct sky2_port
*sky2
= netdev_priv(dev
);
1183 struct sky2_hw
*hw
= sky2
->hw
;
1184 struct sky2_tx_le
*le
= NULL
;
1185 struct tx_ring_info
*re
;
1193 /* No BH disabling for tx_lock here. We are running in BH disabled
1194 * context and TX reclaim runs via poll inside of a software
1195 * interrupt, and no related locks in IRQ processing.
1197 if (!spin_trylock(&sky2
->tx_lock
))
1198 return NETDEV_TX_LOCKED
;
1200 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1201 /* There is a known but harmless race with lockless tx
1202 * and netif_stop_queue.
1204 if (!netif_queue_stopped(dev
)) {
1205 netif_stop_queue(dev
);
1206 if (net_ratelimit())
1207 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1210 spin_unlock(&sky2
->tx_lock
);
1212 return NETDEV_TX_BUSY
;
1215 if (unlikely(netif_msg_tx_queued(sky2
)))
1216 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1217 dev
->name
, sky2
->tx_prod
, skb
->len
);
1219 len
= skb_headlen(skb
);
1220 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1221 addr64
= high32(mapping
);
1223 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1225 /* Send high bits if changed or crosses boundary */
1226 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1227 le
= get_tx_le(sky2
);
1228 le
->tx
.addr
= cpu_to_le32(addr64
);
1230 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1231 sky2
->tx_addr64
= high32(mapping
+ len
);
1234 /* Check for TCP Segmentation Offload */
1235 mss
= skb_shinfo(skb
)->gso_size
;
1237 /* just drop the packet if non-linear expansion fails */
1238 if (skb_header_cloned(skb
) &&
1239 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1244 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1245 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1249 if (mss
!= sky2
->tx_last_mss
) {
1250 le
= get_tx_le(sky2
);
1251 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1252 le
->tx
.tso
.rsvd
= 0;
1253 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1255 sky2
->tx_last_mss
= mss
;
1259 #ifdef SKY2_VLAN_TAG_USED
1260 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1261 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1263 le
= get_tx_le(sky2
);
1265 le
->opcode
= OP_VLAN
|HW_OWNER
;
1268 le
->opcode
|= OP_VLAN
;
1269 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1274 /* Handle TCP checksum offload */
1275 if (skb
->ip_summed
== CHECKSUM_HW
) {
1276 u16 hdr
= skb
->h
.raw
- skb
->data
;
1277 u16 offset
= hdr
+ skb
->csum
;
1279 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1280 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1283 le
= get_tx_le(sky2
);
1284 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1285 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1286 le
->length
= 0; /* initial checksum value */
1287 le
->ctrl
= 1; /* one packet */
1288 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1291 le
= get_tx_le(sky2
);
1292 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1293 le
->length
= cpu_to_le16(len
);
1295 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1297 /* Record the transmit mapping info */
1299 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1301 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1302 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1303 struct tx_ring_info
*fre
;
1305 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1306 frag
->size
, PCI_DMA_TODEVICE
);
1307 addr64
= high32(mapping
);
1308 if (addr64
!= sky2
->tx_addr64
) {
1309 le
= get_tx_le(sky2
);
1310 le
->tx
.addr
= cpu_to_le32(addr64
);
1312 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1313 sky2
->tx_addr64
= addr64
;
1316 le
= get_tx_le(sky2
);
1317 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1318 le
->length
= cpu_to_le16(frag
->size
);
1320 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1323 + RING_NEXT((re
- sky2
->tx_ring
) + i
, TX_RING_SIZE
);
1324 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1327 re
->idx
= sky2
->tx_prod
;
1330 avail
= tx_avail(sky2
);
1331 if (mss
!= 0 || avail
< TX_MIN_PENDING
) {
1332 le
->ctrl
|= FRC_STAT
;
1333 if (avail
<= MAX_SKB_TX_LE
)
1334 netif_stop_queue(dev
);
1337 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1340 spin_unlock(&sky2
->tx_lock
);
1342 dev
->trans_start
= jiffies
;
1343 return NETDEV_TX_OK
;
1347 * Free ring elements from starting at tx_cons until "done"
1349 * NB: the hardware will tell us about partial completion of multi-part
1350 * buffers; these are deferred until completion.
1352 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1354 struct net_device
*dev
= sky2
->netdev
;
1355 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1359 BUG_ON(done
>= TX_RING_SIZE
);
1361 if (unlikely(netif_msg_tx_done(sky2
)))
1362 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1365 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1366 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1367 struct sk_buff
*skb
= re
->skb
;
1370 BUG_ON(nxt
>= TX_RING_SIZE
);
1371 prefetch(sky2
->tx_ring
+ nxt
);
1373 /* Check for partial status */
1374 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1378 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1379 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1381 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1382 struct tx_ring_info
*fre
;
1383 fre
= sky2
->tx_ring
+ RING_NEXT(put
+ i
, TX_RING_SIZE
);
1384 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1385 skb_shinfo(skb
)->frags
[i
].size
,
1392 sky2
->tx_cons
= put
;
1393 if (tx_avail(sky2
) > MAX_SKB_TX_LE
)
1394 netif_wake_queue(dev
);
1397 /* Cleanup all untransmitted buffers, assume transmitter not running */
1398 static void sky2_tx_clean(struct sky2_port
*sky2
)
1400 spin_lock_bh(&sky2
->tx_lock
);
1401 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1402 spin_unlock_bh(&sky2
->tx_lock
);
1405 /* Network shutdown */
1406 static int sky2_down(struct net_device
*dev
)
1408 struct sky2_port
*sky2
= netdev_priv(dev
);
1409 struct sky2_hw
*hw
= sky2
->hw
;
1410 unsigned port
= sky2
->port
;
1414 /* Never really got started! */
1418 if (netif_msg_ifdown(sky2
))
1419 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1421 /* Stop more packets from being queued */
1422 netif_stop_queue(dev
);
1424 sky2_phy_reset(hw
, port
);
1426 /* Stop transmitter */
1427 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1428 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1430 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1431 RB_RST_SET
| RB_DIS_OP_MD
);
1433 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1434 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1435 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1437 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1439 /* Workaround shared GMAC reset */
1440 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1441 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1442 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1444 /* Disable Force Sync bit and Enable Alloc bit */
1445 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1446 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1448 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1449 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1450 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1452 /* Reset the PCI FIFO of the async Tx queue */
1453 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1454 BMU_RST_SET
| BMU_FIFO_RST
);
1456 /* Reset the Tx prefetch units */
1457 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1460 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1464 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1465 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1467 /* Disable port IRQ */
1468 imask
= sky2_read32(hw
, B0_IMSK
);
1469 imask
&= ~portirq_msk
[port
];
1470 sky2_write32(hw
, B0_IMSK
, imask
);
1472 /* turn off LED's */
1473 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1475 synchronize_irq(hw
->pdev
->irq
);
1477 sky2_tx_clean(sky2
);
1478 sky2_rx_clean(sky2
);
1480 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1481 sky2
->rx_le
, sky2
->rx_le_map
);
1482 kfree(sky2
->rx_ring
);
1484 pci_free_consistent(hw
->pdev
,
1485 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1486 sky2
->tx_le
, sky2
->tx_le_map
);
1487 kfree(sky2
->tx_ring
);
1492 sky2
->rx_ring
= NULL
;
1493 sky2
->tx_ring
= NULL
;
1498 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1503 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1504 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1506 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1507 case PHY_M_PS_SPEED_1000
:
1509 case PHY_M_PS_SPEED_100
:
1516 static void sky2_link_up(struct sky2_port
*sky2
)
1518 struct sky2_hw
*hw
= sky2
->hw
;
1519 unsigned port
= sky2
->port
;
1522 /* Enable Transmit FIFO Underrun */
1523 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1525 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1526 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1527 reg
|= GM_GPCR_AU_ALL_DIS
;
1529 /* Is write/read necessary? Copied from sky2_mac_init */
1530 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1531 gma_read16(hw
, port
, GM_GP_CTRL
);
1533 switch (sky2
->speed
) {
1535 reg
&= ~GM_GPCR_SPEED_100
;
1536 reg
|= GM_GPCR_SPEED_1000
;
1539 reg
&= ~GM_GPCR_SPEED_1000
;
1540 reg
|= GM_GPCR_SPEED_100
;
1543 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1547 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1549 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1550 reg
|= GM_GPCR_DUP_FULL
;
1553 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1554 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1555 gma_read16(hw
, port
, GM_GP_CTRL
);
1557 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1559 netif_carrier_on(sky2
->netdev
);
1560 netif_wake_queue(sky2
->netdev
);
1562 /* Turn on link LED */
1563 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1564 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1566 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1567 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1568 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1570 switch(sky2
->speed
) {
1572 led
|= PHY_M_LEDC_INIT_CTRL(7);
1576 led
|= PHY_M_LEDC_STA1_CTRL(7);
1580 led
|= PHY_M_LEDC_STA0_CTRL(7);
1584 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1585 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1586 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1589 if (netif_msg_link(sky2
))
1590 printk(KERN_INFO PFX
1591 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1592 sky2
->netdev
->name
, sky2
->speed
,
1593 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1594 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1595 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1598 static void sky2_link_down(struct sky2_port
*sky2
)
1600 struct sky2_hw
*hw
= sky2
->hw
;
1601 unsigned port
= sky2
->port
;
1604 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1606 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1607 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1608 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1609 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1611 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1612 /* restore Asymmetric Pause bit */
1613 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1614 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1618 netif_carrier_off(sky2
->netdev
);
1619 netif_stop_queue(sky2
->netdev
);
1621 /* Turn on link LED */
1622 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1624 if (netif_msg_link(sky2
))
1625 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1626 sky2_phy_init(hw
, port
);
1629 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1631 struct sky2_hw
*hw
= sky2
->hw
;
1632 unsigned port
= sky2
->port
;
1635 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1637 if (lpa
& PHY_M_AN_RF
) {
1638 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1642 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1643 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1644 printk(KERN_ERR PFX
"%s: master/slave fault",
1645 sky2
->netdev
->name
);
1649 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1650 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1651 sky2
->netdev
->name
);
1655 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1657 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1659 /* Pause bits are offset (9..8) */
1660 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1663 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1664 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1666 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1667 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1668 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1670 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1675 /* Interrupt from PHY */
1676 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1678 struct net_device
*dev
= hw
->dev
[port
];
1679 struct sky2_port
*sky2
= netdev_priv(dev
);
1680 u16 istatus
, phystat
;
1682 spin_lock(&sky2
->phy_lock
);
1683 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1684 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1686 if (!netif_running(dev
))
1689 if (netif_msg_intr(sky2
))
1690 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1691 sky2
->netdev
->name
, istatus
, phystat
);
1693 if (istatus
& PHY_M_IS_AN_COMPL
) {
1694 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1699 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1700 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1702 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1704 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1706 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1707 if (phystat
& PHY_M_PS_LINK_UP
)
1710 sky2_link_down(sky2
);
1713 spin_unlock(&sky2
->phy_lock
);
1717 /* Transmit timeout is only called if we are running, carries is up
1718 * and tx queue is full (stopped).
1720 static void sky2_tx_timeout(struct net_device
*dev
)
1722 struct sky2_port
*sky2
= netdev_priv(dev
);
1723 struct sky2_hw
*hw
= sky2
->hw
;
1724 unsigned txq
= txqaddr
[sky2
->port
];
1727 if (netif_msg_timer(sky2
))
1728 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1730 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1731 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1733 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1735 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1737 if (report
!= done
) {
1738 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1740 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1741 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1742 } else if (report
!= sky2
->tx_cons
) {
1743 printk(KERN_INFO PFX
"status report lost?\n");
1745 spin_lock_bh(&sky2
->tx_lock
);
1746 sky2_tx_complete(sky2
, report
);
1747 spin_unlock_bh(&sky2
->tx_lock
);
1749 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1751 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1752 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1754 sky2_tx_clean(sky2
);
1757 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1762 /* Want receive buffer size to be multiple of 64 bits
1763 * and incl room for vlan and truncation
1765 static inline unsigned sky2_buf_size(int mtu
)
1767 return ALIGN(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1770 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1772 struct sky2_port
*sky2
= netdev_priv(dev
);
1773 struct sky2_hw
*hw
= sky2
->hw
;
1778 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1781 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1784 if (!netif_running(dev
)) {
1789 imask
= sky2_read32(hw
, B0_IMSK
);
1790 sky2_write32(hw
, B0_IMSK
, 0);
1792 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1793 netif_stop_queue(dev
);
1794 netif_poll_disable(hw
->dev
[0]);
1796 synchronize_irq(hw
->pdev
->irq
);
1798 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1799 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1801 sky2_rx_clean(sky2
);
1804 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1805 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1806 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1808 if (dev
->mtu
> ETH_DATA_LEN
)
1809 mode
|= GM_SMOD_JUMBO_ENA
;
1811 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1813 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1815 err
= sky2_rx_start(sky2
);
1816 sky2_write32(hw
, B0_IMSK
, imask
);
1821 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1823 netif_poll_enable(hw
->dev
[0]);
1824 netif_wake_queue(dev
);
1831 * Receive one packet.
1832 * For small packets or errors, just reuse existing skb.
1833 * For larger packets, get new buffer.
1835 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1836 u16 length
, u32 status
)
1838 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1839 struct sk_buff
*skb
= NULL
;
1841 if (unlikely(netif_msg_rx_status(sky2
)))
1842 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1843 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1845 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1846 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1848 if (status
& GMR_FS_ANY_ERR
)
1851 if (!(status
& GMR_FS_RX_OK
))
1854 if (length
> sky2
->netdev
->mtu
+ ETH_HLEN
)
1857 if (length
< copybreak
) {
1858 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1862 skb_reserve(skb
, 2);
1863 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1864 length
, PCI_DMA_FROMDEVICE
);
1865 memcpy(skb
->data
, re
->skb
->data
, length
);
1866 skb
->ip_summed
= re
->skb
->ip_summed
;
1867 skb
->csum
= re
->skb
->csum
;
1868 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1869 length
, PCI_DMA_FROMDEVICE
);
1871 struct sk_buff
*nskb
;
1873 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1879 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1880 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1881 prefetch(skb
->data
);
1883 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1884 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1887 skb_put(skb
, length
);
1889 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1890 sky2_rx_add(sky2
, re
->mapaddr
);
1892 /* Tell receiver about new buffers. */
1893 sky2_put_idx(sky2
->hw
, rxqaddr
[sky2
->port
], sky2
->rx_put
);
1898 ++sky2
->net_stats
.rx_over_errors
;
1902 ++sky2
->net_stats
.rx_errors
;
1904 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1905 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1906 sky2
->netdev
->name
, status
, length
);
1908 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1909 sky2
->net_stats
.rx_length_errors
++;
1910 if (status
& GMR_FS_FRAGMENT
)
1911 sky2
->net_stats
.rx_frame_errors
++;
1912 if (status
& GMR_FS_CRC_ERR
)
1913 sky2
->net_stats
.rx_crc_errors
++;
1914 if (status
& GMR_FS_RX_FF_OV
)
1915 sky2
->net_stats
.rx_fifo_errors
++;
1920 /* Transmit complete */
1921 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
1923 struct sky2_port
*sky2
= netdev_priv(dev
);
1925 if (netif_running(dev
)) {
1926 spin_lock(&sky2
->tx_lock
);
1927 sky2_tx_complete(sky2
, last
);
1928 spin_unlock(&sky2
->tx_lock
);
1932 /* Is status ring empty or is there more to do? */
1933 static inline int sky2_more_work(const struct sky2_hw
*hw
)
1935 return (hw
->st_idx
!= sky2_read16(hw
, STAT_PUT_IDX
));
1938 /* Process status response ring */
1939 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
1942 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1946 while (hw
->st_idx
!= hwidx
) {
1947 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1948 struct net_device
*dev
;
1949 struct sky2_port
*sky2
;
1950 struct sk_buff
*skb
;
1954 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
1956 BUG_ON(le
->link
>= 2);
1957 dev
= hw
->dev
[le
->link
];
1959 sky2
= netdev_priv(dev
);
1960 length
= le
->length
;
1961 status
= le
->status
;
1963 switch (le
->opcode
& ~HW_OWNER
) {
1965 skb
= sky2_receive(sky2
, length
, status
);
1970 skb
->protocol
= eth_type_trans(skb
, dev
);
1971 dev
->last_rx
= jiffies
;
1973 #ifdef SKY2_VLAN_TAG_USED
1974 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1975 vlan_hwaccel_receive_skb(skb
,
1977 be16_to_cpu(sky2
->rx_tag
));
1980 netif_receive_skb(skb
);
1982 if (++work_done
>= to_do
)
1986 #ifdef SKY2_VLAN_TAG_USED
1988 sky2
->rx_tag
= length
;
1992 sky2
->rx_tag
= length
;
1996 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
1997 skb
->ip_summed
= CHECKSUM_HW
;
1998 skb
->csum
= le16_to_cpu(status
);
2002 /* TX index reports status for both ports */
2003 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2004 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2006 sky2_tx_done(hw
->dev
[1],
2007 ((status
>> 24) & 0xff)
2008 | (u16
)(length
& 0xf) << 8);
2012 if (net_ratelimit())
2013 printk(KERN_WARNING PFX
2014 "unknown status opcode 0x%x\n", le
->opcode
);
2023 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2025 struct net_device
*dev
= hw
->dev
[port
];
2027 if (net_ratelimit())
2028 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2031 if (status
& Y2_IS_PAR_RD1
) {
2032 if (net_ratelimit())
2033 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2036 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2039 if (status
& Y2_IS_PAR_WR1
) {
2040 if (net_ratelimit())
2041 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2044 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2047 if (status
& Y2_IS_PAR_MAC1
) {
2048 if (net_ratelimit())
2049 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2050 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2053 if (status
& Y2_IS_PAR_RX1
) {
2054 if (net_ratelimit())
2055 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2056 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2059 if (status
& Y2_IS_TCP_TXA1
) {
2060 if (net_ratelimit())
2061 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2063 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2067 static void sky2_hw_intr(struct sky2_hw
*hw
)
2069 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2071 if (status
& Y2_IS_TIST_OV
)
2072 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2074 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2077 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2078 if (net_ratelimit())
2079 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2080 pci_name(hw
->pdev
), pci_err
);
2082 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2083 sky2_pci_write16(hw
, PCI_STATUS
,
2084 pci_err
| PCI_STATUS_ERROR_BITS
);
2085 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2088 if (status
& Y2_IS_PCI_EXP
) {
2089 /* PCI-Express uncorrectable Error occurred */
2092 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2094 if (net_ratelimit())
2095 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2096 pci_name(hw
->pdev
), pex_err
);
2098 /* clear the interrupt */
2099 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2100 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2102 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2104 if (pex_err
& PEX_FATAL_ERRORS
) {
2105 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2106 hwmsk
&= ~Y2_IS_PCI_EXP
;
2107 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2111 if (status
& Y2_HWE_L1_MASK
)
2112 sky2_hw_error(hw
, 0, status
);
2114 if (status
& Y2_HWE_L1_MASK
)
2115 sky2_hw_error(hw
, 1, status
);
2118 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2120 struct net_device
*dev
= hw
->dev
[port
];
2121 struct sky2_port
*sky2
= netdev_priv(dev
);
2122 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2124 if (netif_msg_intr(sky2
))
2125 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2128 if (status
& GM_IS_RX_FF_OR
) {
2129 ++sky2
->net_stats
.rx_fifo_errors
;
2130 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2133 if (status
& GM_IS_TX_FF_UR
) {
2134 ++sky2
->net_stats
.tx_fifo_errors
;
2135 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2139 /* This should never happen it is a fatal situation */
2140 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2141 const char *rxtx
, u32 mask
)
2143 struct net_device
*dev
= hw
->dev
[port
];
2144 struct sky2_port
*sky2
= netdev_priv(dev
);
2147 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2148 dev
? dev
->name
: "<not registered>", rxtx
);
2150 imask
= sky2_read32(hw
, B0_IMSK
);
2152 sky2_write32(hw
, B0_IMSK
, imask
);
2155 spin_lock(&sky2
->phy_lock
);
2156 sky2_link_down(sky2
);
2157 spin_unlock(&sky2
->phy_lock
);
2161 /* If idle then force a fake soft NAPI poll once a second
2162 * to work around cases where sharing an edge triggered interrupt.
2164 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2166 if (idle_timeout
> 0)
2167 mod_timer(&hw
->idle_timer
,
2168 jiffies
+ msecs_to_jiffies(idle_timeout
));
2171 static void sky2_idle(unsigned long arg
)
2173 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2174 struct net_device
*dev
= hw
->dev
[0];
2176 if (__netif_rx_schedule_prep(dev
))
2177 __netif_rx_schedule(dev
);
2179 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2183 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2185 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2186 int work_limit
= min(dev0
->quota
, *budget
);
2188 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2193 if (status
& Y2_IS_HW_ERR
)
2196 if (status
& Y2_IS_IRQ_PHY1
)
2197 sky2_phy_intr(hw
, 0);
2199 if (status
& Y2_IS_IRQ_PHY2
)
2200 sky2_phy_intr(hw
, 1);
2202 if (status
& Y2_IS_IRQ_MAC1
)
2203 sky2_mac_intr(hw
, 0);
2205 if (status
& Y2_IS_IRQ_MAC2
)
2206 sky2_mac_intr(hw
, 1);
2208 if (status
& Y2_IS_CHK_RX1
)
2209 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2211 if (status
& Y2_IS_CHK_RX2
)
2212 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2214 if (status
& Y2_IS_CHK_TXA1
)
2215 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2217 if (status
& Y2_IS_CHK_TXA2
)
2218 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2220 work_done
= sky2_status_intr(hw
, work_limit
);
2221 *budget
-= work_done
;
2222 dev0
->quota
-= work_done
;
2224 if (status
& Y2_IS_STAT_BMU
)
2225 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2227 if (sky2_more_work(hw
))
2230 netif_rx_complete(dev0
);
2232 sky2_read32(hw
, B0_Y2_SP_LISR
);
2236 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2238 struct sky2_hw
*hw
= dev_id
;
2239 struct net_device
*dev0
= hw
->dev
[0];
2242 /* Reading this mask interrupts as side effect */
2243 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2244 if (status
== 0 || status
== ~0)
2247 prefetch(&hw
->st_le
[hw
->st_idx
]);
2248 if (likely(__netif_rx_schedule_prep(dev0
)))
2249 __netif_rx_schedule(dev0
);
2254 #ifdef CONFIG_NET_POLL_CONTROLLER
2255 static void sky2_netpoll(struct net_device
*dev
)
2257 struct sky2_port
*sky2
= netdev_priv(dev
);
2258 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2260 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2261 __netif_rx_schedule(dev0
);
2265 /* Chip internal frequency for clock calculations */
2266 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2268 switch (hw
->chip_id
) {
2269 case CHIP_ID_YUKON_EC
:
2270 case CHIP_ID_YUKON_EC_U
:
2271 return 125; /* 125 Mhz */
2272 case CHIP_ID_YUKON_FE
:
2273 return 100; /* 100 Mhz */
2274 default: /* YUKON_XL */
2275 return 156; /* 156 Mhz */
2279 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2281 return sky2_mhz(hw
) * us
;
2284 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2286 return clk
/ sky2_mhz(hw
);
2290 static int sky2_reset(struct sky2_hw
*hw
)
2296 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2298 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2299 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2300 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2301 pci_name(hw
->pdev
), hw
->chip_id
);
2305 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2307 /* This rev is really old, and requires untested workarounds */
2308 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2309 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2310 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2311 hw
->chip_id
, hw
->chip_rev
);
2316 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2317 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2318 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2322 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2323 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2325 /* clear PCI errors, if any */
2326 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2328 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2329 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2332 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2334 /* clear any PEX errors */
2335 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2336 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2339 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2340 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2343 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2344 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2345 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2349 sky2_set_power_state(hw
, PCI_D0
);
2351 for (i
= 0; i
< hw
->ports
; i
++) {
2352 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2353 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2356 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2358 /* Clear I2C IRQ noise */
2359 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2361 /* turn off hardware timer (unused) */
2362 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2363 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2365 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2367 /* Turn off descriptor polling */
2368 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2370 /* Turn off receive timestamp */
2371 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2372 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2374 /* enable the Tx Arbiters */
2375 for (i
= 0; i
< hw
->ports
; i
++)
2376 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2378 /* Initialize ram interface */
2379 for (i
= 0; i
< hw
->ports
; i
++) {
2380 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2382 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2383 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2384 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2385 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2386 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2387 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2388 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2389 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2390 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2391 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2392 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2393 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2396 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2398 for (i
= 0; i
< hw
->ports
; i
++)
2399 sky2_phy_reset(hw
, i
);
2401 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2404 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2405 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2407 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2408 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2410 /* Set the list last index */
2411 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2413 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2414 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2416 /* set Status-FIFO ISR watermark */
2417 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2418 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2420 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2422 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2423 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2424 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2426 /* enable status unit */
2427 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2429 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2430 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2431 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2436 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2440 modes
= SUPPORTED_10baseT_Half
2441 | SUPPORTED_10baseT_Full
2442 | SUPPORTED_100baseT_Half
2443 | SUPPORTED_100baseT_Full
2444 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2446 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2447 modes
|= SUPPORTED_1000baseT_Half
2448 | SUPPORTED_1000baseT_Full
;
2450 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2451 | SUPPORTED_Autoneg
;
2455 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2457 struct sky2_port
*sky2
= netdev_priv(dev
);
2458 struct sky2_hw
*hw
= sky2
->hw
;
2460 ecmd
->transceiver
= XCVR_INTERNAL
;
2461 ecmd
->supported
= sky2_supported_modes(hw
);
2462 ecmd
->phy_address
= PHY_ADDR_MARV
;
2464 ecmd
->supported
= SUPPORTED_10baseT_Half
2465 | SUPPORTED_10baseT_Full
2466 | SUPPORTED_100baseT_Half
2467 | SUPPORTED_100baseT_Full
2468 | SUPPORTED_1000baseT_Half
2469 | SUPPORTED_1000baseT_Full
2470 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2471 ecmd
->port
= PORT_TP
;
2473 ecmd
->port
= PORT_FIBRE
;
2475 ecmd
->advertising
= sky2
->advertising
;
2476 ecmd
->autoneg
= sky2
->autoneg
;
2477 ecmd
->speed
= sky2
->speed
;
2478 ecmd
->duplex
= sky2
->duplex
;
2482 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2484 struct sky2_port
*sky2
= netdev_priv(dev
);
2485 const struct sky2_hw
*hw
= sky2
->hw
;
2486 u32 supported
= sky2_supported_modes(hw
);
2488 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2489 ecmd
->advertising
= supported
;
2495 switch (ecmd
->speed
) {
2497 if (ecmd
->duplex
== DUPLEX_FULL
)
2498 setting
= SUPPORTED_1000baseT_Full
;
2499 else if (ecmd
->duplex
== DUPLEX_HALF
)
2500 setting
= SUPPORTED_1000baseT_Half
;
2505 if (ecmd
->duplex
== DUPLEX_FULL
)
2506 setting
= SUPPORTED_100baseT_Full
;
2507 else if (ecmd
->duplex
== DUPLEX_HALF
)
2508 setting
= SUPPORTED_100baseT_Half
;
2514 if (ecmd
->duplex
== DUPLEX_FULL
)
2515 setting
= SUPPORTED_10baseT_Full
;
2516 else if (ecmd
->duplex
== DUPLEX_HALF
)
2517 setting
= SUPPORTED_10baseT_Half
;
2525 if ((setting
& supported
) == 0)
2528 sky2
->speed
= ecmd
->speed
;
2529 sky2
->duplex
= ecmd
->duplex
;
2532 sky2
->autoneg
= ecmd
->autoneg
;
2533 sky2
->advertising
= ecmd
->advertising
;
2535 if (netif_running(dev
))
2536 sky2_phy_reinit(sky2
);
2541 static void sky2_get_drvinfo(struct net_device
*dev
,
2542 struct ethtool_drvinfo
*info
)
2544 struct sky2_port
*sky2
= netdev_priv(dev
);
2546 strcpy(info
->driver
, DRV_NAME
);
2547 strcpy(info
->version
, DRV_VERSION
);
2548 strcpy(info
->fw_version
, "N/A");
2549 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2552 static const struct sky2_stat
{
2553 char name
[ETH_GSTRING_LEN
];
2556 { "tx_bytes", GM_TXO_OK_HI
},
2557 { "rx_bytes", GM_RXO_OK_HI
},
2558 { "tx_broadcast", GM_TXF_BC_OK
},
2559 { "rx_broadcast", GM_RXF_BC_OK
},
2560 { "tx_multicast", GM_TXF_MC_OK
},
2561 { "rx_multicast", GM_RXF_MC_OK
},
2562 { "tx_unicast", GM_TXF_UC_OK
},
2563 { "rx_unicast", GM_RXF_UC_OK
},
2564 { "tx_mac_pause", GM_TXF_MPAUSE
},
2565 { "rx_mac_pause", GM_RXF_MPAUSE
},
2566 { "collisions", GM_TXF_COL
},
2567 { "late_collision",GM_TXF_LAT_COL
},
2568 { "aborted", GM_TXF_ABO_COL
},
2569 { "single_collisions", GM_TXF_SNG_COL
},
2570 { "multi_collisions", GM_TXF_MUL_COL
},
2572 { "rx_short", GM_RXF_SHT
},
2573 { "rx_runt", GM_RXE_FRAG
},
2574 { "rx_64_byte_packets", GM_RXF_64B
},
2575 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2576 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2577 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2578 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2579 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2580 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2581 { "rx_too_long", GM_RXF_LNG_ERR
},
2582 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2583 { "rx_jabber", GM_RXF_JAB_PKT
},
2584 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2586 { "tx_64_byte_packets", GM_TXF_64B
},
2587 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2588 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2589 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2590 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2591 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2592 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2593 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2596 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2598 struct sky2_port
*sky2
= netdev_priv(dev
);
2600 return sky2
->rx_csum
;
2603 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2605 struct sky2_port
*sky2
= netdev_priv(dev
);
2607 sky2
->rx_csum
= data
;
2609 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2610 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2615 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2617 struct sky2_port
*sky2
= netdev_priv(netdev
);
2618 return sky2
->msg_enable
;
2621 static int sky2_nway_reset(struct net_device
*dev
)
2623 struct sky2_port
*sky2
= netdev_priv(dev
);
2625 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2628 sky2_phy_reinit(sky2
);
2633 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2635 struct sky2_hw
*hw
= sky2
->hw
;
2636 unsigned port
= sky2
->port
;
2639 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2640 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2641 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2642 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2644 for (i
= 2; i
< count
; i
++)
2645 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2648 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2650 struct sky2_port
*sky2
= netdev_priv(netdev
);
2651 sky2
->msg_enable
= value
;
2654 static int sky2_get_stats_count(struct net_device
*dev
)
2656 return ARRAY_SIZE(sky2_stats
);
2659 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2660 struct ethtool_stats
*stats
, u64
* data
)
2662 struct sky2_port
*sky2
= netdev_priv(dev
);
2664 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2667 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2671 switch (stringset
) {
2673 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2674 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2675 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2680 /* Use hardware MIB variables for critical path statistics and
2681 * transmit feedback not reported at interrupt.
2682 * Other errors are accounted for in interrupt handler.
2684 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2686 struct sky2_port
*sky2
= netdev_priv(dev
);
2689 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2691 sky2
->net_stats
.tx_bytes
= data
[0];
2692 sky2
->net_stats
.rx_bytes
= data
[1];
2693 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2694 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2695 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2696 sky2
->net_stats
.collisions
= data
[10];
2697 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2699 return &sky2
->net_stats
;
2702 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2704 struct sky2_port
*sky2
= netdev_priv(dev
);
2705 struct sky2_hw
*hw
= sky2
->hw
;
2706 unsigned port
= sky2
->port
;
2707 const struct sockaddr
*addr
= p
;
2709 if (!is_valid_ether_addr(addr
->sa_data
))
2710 return -EADDRNOTAVAIL
;
2712 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2713 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2714 dev
->dev_addr
, ETH_ALEN
);
2715 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2716 dev
->dev_addr
, ETH_ALEN
);
2718 /* virtual address for data */
2719 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2721 /* physical address: used for pause frames */
2722 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2727 static void sky2_set_multicast(struct net_device
*dev
)
2729 struct sky2_port
*sky2
= netdev_priv(dev
);
2730 struct sky2_hw
*hw
= sky2
->hw
;
2731 unsigned port
= sky2
->port
;
2732 struct dev_mc_list
*list
= dev
->mc_list
;
2736 memset(filter
, 0, sizeof(filter
));
2738 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2739 reg
|= GM_RXCR_UCF_ENA
;
2741 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2742 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2743 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2744 memset(filter
, 0xff, sizeof(filter
));
2745 else if (dev
->mc_count
== 0) /* no multicast */
2746 reg
&= ~GM_RXCR_MCF_ENA
;
2749 reg
|= GM_RXCR_MCF_ENA
;
2751 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2752 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2753 filter
[bit
/ 8] |= 1 << (bit
% 8);
2757 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2758 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2759 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2760 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2761 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2762 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2763 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2764 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2766 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2769 /* Can have one global because blinking is controlled by
2770 * ethtool and that is always under RTNL mutex
2772 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2776 switch (hw
->chip_id
) {
2777 case CHIP_ID_YUKON_XL
:
2778 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2779 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2780 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2781 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2782 PHY_M_LEDC_INIT_CTRL(7) |
2783 PHY_M_LEDC_STA1_CTRL(7) |
2784 PHY_M_LEDC_STA0_CTRL(7))
2787 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2791 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2792 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2793 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2794 PHY_M_LED_MO_10(MO_LED_ON
) |
2795 PHY_M_LED_MO_100(MO_LED_ON
) |
2796 PHY_M_LED_MO_1000(MO_LED_ON
) |
2797 PHY_M_LED_MO_RX(MO_LED_ON
)
2798 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2799 PHY_M_LED_MO_10(MO_LED_OFF
) |
2800 PHY_M_LED_MO_100(MO_LED_OFF
) |
2801 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2802 PHY_M_LED_MO_RX(MO_LED_OFF
));
2807 /* blink LED's for finding board */
2808 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2810 struct sky2_port
*sky2
= netdev_priv(dev
);
2811 struct sky2_hw
*hw
= sky2
->hw
;
2812 unsigned port
= sky2
->port
;
2813 u16 ledctrl
, ledover
= 0;
2818 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2819 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2823 /* save initial values */
2824 spin_lock_bh(&sky2
->phy_lock
);
2825 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2826 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2827 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2828 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2829 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2831 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2832 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2836 while (!interrupted
&& ms
> 0) {
2837 sky2_led(hw
, port
, onoff
);
2840 spin_unlock_bh(&sky2
->phy_lock
);
2841 interrupted
= msleep_interruptible(250);
2842 spin_lock_bh(&sky2
->phy_lock
);
2847 /* resume regularly scheduled programming */
2848 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2849 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2850 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2851 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2852 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2854 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2855 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2857 spin_unlock_bh(&sky2
->phy_lock
);
2862 static void sky2_get_pauseparam(struct net_device
*dev
,
2863 struct ethtool_pauseparam
*ecmd
)
2865 struct sky2_port
*sky2
= netdev_priv(dev
);
2867 ecmd
->tx_pause
= sky2
->tx_pause
;
2868 ecmd
->rx_pause
= sky2
->rx_pause
;
2869 ecmd
->autoneg
= sky2
->autoneg
;
2872 static int sky2_set_pauseparam(struct net_device
*dev
,
2873 struct ethtool_pauseparam
*ecmd
)
2875 struct sky2_port
*sky2
= netdev_priv(dev
);
2878 sky2
->autoneg
= ecmd
->autoneg
;
2879 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2880 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2882 sky2_phy_reinit(sky2
);
2887 static int sky2_get_coalesce(struct net_device
*dev
,
2888 struct ethtool_coalesce
*ecmd
)
2890 struct sky2_port
*sky2
= netdev_priv(dev
);
2891 struct sky2_hw
*hw
= sky2
->hw
;
2893 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2894 ecmd
->tx_coalesce_usecs
= 0;
2896 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2897 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2899 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2901 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2902 ecmd
->rx_coalesce_usecs
= 0;
2904 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2905 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2907 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2909 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2910 ecmd
->rx_coalesce_usecs_irq
= 0;
2912 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2913 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2916 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2921 /* Note: this affect both ports */
2922 static int sky2_set_coalesce(struct net_device
*dev
,
2923 struct ethtool_coalesce
*ecmd
)
2925 struct sky2_port
*sky2
= netdev_priv(dev
);
2926 struct sky2_hw
*hw
= sky2
->hw
;
2927 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
2929 if (ecmd
->tx_coalesce_usecs
> tmax
||
2930 ecmd
->rx_coalesce_usecs
> tmax
||
2931 ecmd
->rx_coalesce_usecs_irq
> tmax
)
2934 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2936 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2938 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2941 if (ecmd
->tx_coalesce_usecs
== 0)
2942 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2944 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2945 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2946 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2948 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2950 if (ecmd
->rx_coalesce_usecs
== 0)
2951 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2953 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2954 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2955 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2957 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2959 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2960 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2962 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2963 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2964 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2966 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2970 static void sky2_get_ringparam(struct net_device
*dev
,
2971 struct ethtool_ringparam
*ering
)
2973 struct sky2_port
*sky2
= netdev_priv(dev
);
2975 ering
->rx_max_pending
= RX_MAX_PENDING
;
2976 ering
->rx_mini_max_pending
= 0;
2977 ering
->rx_jumbo_max_pending
= 0;
2978 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2980 ering
->rx_pending
= sky2
->rx_pending
;
2981 ering
->rx_mini_pending
= 0;
2982 ering
->rx_jumbo_pending
= 0;
2983 ering
->tx_pending
= sky2
->tx_pending
;
2986 static int sky2_set_ringparam(struct net_device
*dev
,
2987 struct ethtool_ringparam
*ering
)
2989 struct sky2_port
*sky2
= netdev_priv(dev
);
2992 if (ering
->rx_pending
> RX_MAX_PENDING
||
2993 ering
->rx_pending
< 8 ||
2994 ering
->tx_pending
< MAX_SKB_TX_LE
||
2995 ering
->tx_pending
> TX_RING_SIZE
- 1)
2998 if (netif_running(dev
))
3001 sky2
->rx_pending
= ering
->rx_pending
;
3002 sky2
->tx_pending
= ering
->tx_pending
;
3004 if (netif_running(dev
)) {
3009 sky2_set_multicast(dev
);
3015 static int sky2_get_regs_len(struct net_device
*dev
)
3021 * Returns copy of control register region
3022 * Note: access to the RAM address register set will cause timeouts.
3024 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3027 const struct sky2_port
*sky2
= netdev_priv(dev
);
3028 const void __iomem
*io
= sky2
->hw
->regs
;
3030 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3032 memset(p
, 0, regs
->len
);
3034 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3036 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3038 regs
->len
- B3_RI_WTO_R1
);
3041 static struct ethtool_ops sky2_ethtool_ops
= {
3042 .get_settings
= sky2_get_settings
,
3043 .set_settings
= sky2_set_settings
,
3044 .get_drvinfo
= sky2_get_drvinfo
,
3045 .get_msglevel
= sky2_get_msglevel
,
3046 .set_msglevel
= sky2_set_msglevel
,
3047 .nway_reset
= sky2_nway_reset
,
3048 .get_regs_len
= sky2_get_regs_len
,
3049 .get_regs
= sky2_get_regs
,
3050 .get_link
= ethtool_op_get_link
,
3051 .get_sg
= ethtool_op_get_sg
,
3052 .set_sg
= ethtool_op_set_sg
,
3053 .get_tx_csum
= ethtool_op_get_tx_csum
,
3054 .set_tx_csum
= ethtool_op_set_tx_csum
,
3055 .get_tso
= ethtool_op_get_tso
,
3056 .set_tso
= ethtool_op_set_tso
,
3057 .get_rx_csum
= sky2_get_rx_csum
,
3058 .set_rx_csum
= sky2_set_rx_csum
,
3059 .get_strings
= sky2_get_strings
,
3060 .get_coalesce
= sky2_get_coalesce
,
3061 .set_coalesce
= sky2_set_coalesce
,
3062 .get_ringparam
= sky2_get_ringparam
,
3063 .set_ringparam
= sky2_set_ringparam
,
3064 .get_pauseparam
= sky2_get_pauseparam
,
3065 .set_pauseparam
= sky2_set_pauseparam
,
3066 .phys_id
= sky2_phys_id
,
3067 .get_stats_count
= sky2_get_stats_count
,
3068 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3069 .get_perm_addr
= ethtool_op_get_perm_addr
,
3072 /* Initialize network device */
3073 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3074 unsigned port
, int highmem
)
3076 struct sky2_port
*sky2
;
3077 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3080 printk(KERN_ERR
"sky2 etherdev alloc failed");
3084 SET_MODULE_OWNER(dev
);
3085 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3086 dev
->irq
= hw
->pdev
->irq
;
3087 dev
->open
= sky2_up
;
3088 dev
->stop
= sky2_down
;
3089 dev
->do_ioctl
= sky2_ioctl
;
3090 dev
->hard_start_xmit
= sky2_xmit_frame
;
3091 dev
->get_stats
= sky2_get_stats
;
3092 dev
->set_multicast_list
= sky2_set_multicast
;
3093 dev
->set_mac_address
= sky2_set_mac_address
;
3094 dev
->change_mtu
= sky2_change_mtu
;
3095 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3096 dev
->tx_timeout
= sky2_tx_timeout
;
3097 dev
->watchdog_timeo
= TX_WATCHDOG
;
3099 dev
->poll
= sky2_poll
;
3100 dev
->weight
= NAPI_WEIGHT
;
3101 #ifdef CONFIG_NET_POLL_CONTROLLER
3102 dev
->poll_controller
= sky2_netpoll
;
3105 sky2
= netdev_priv(dev
);
3108 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3110 spin_lock_init(&sky2
->tx_lock
);
3111 /* Auto speed and flow control */
3112 sky2
->autoneg
= AUTONEG_ENABLE
;
3117 sky2
->advertising
= sky2_supported_modes(hw
);
3120 spin_lock_init(&sky2
->phy_lock
);
3121 sky2
->tx_pending
= TX_DEF_PENDING
;
3122 sky2
->rx_pending
= RX_DEF_PENDING
;
3123 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3125 hw
->dev
[port
] = dev
;
3129 dev
->features
|= NETIF_F_LLTX
;
3130 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3131 dev
->features
|= NETIF_F_TSO
;
3133 dev
->features
|= NETIF_F_HIGHDMA
;
3134 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3136 #ifdef SKY2_VLAN_TAG_USED
3137 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3138 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3139 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3142 /* read the mac address */
3143 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3144 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3146 /* device is off until link detection */
3147 netif_carrier_off(dev
);
3148 netif_stop_queue(dev
);
3153 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3155 const struct sky2_port
*sky2
= netdev_priv(dev
);
3157 if (netif_msg_probe(sky2
))
3158 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3160 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3161 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3164 /* Handle software interrupt used during MSI test */
3165 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3166 struct pt_regs
*regs
)
3168 struct sky2_hw
*hw
= dev_id
;
3169 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3174 if (status
& Y2_IS_IRQ_SW
) {
3175 hw
->msi_detected
= 1;
3176 wake_up(&hw
->msi_wait
);
3177 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3179 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3184 /* Test interrupt path by forcing a a software IRQ */
3185 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3187 struct pci_dev
*pdev
= hw
->pdev
;
3190 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3192 err
= request_irq(pdev
->irq
, sky2_test_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3194 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3195 pci_name(pdev
), pdev
->irq
);
3199 init_waitqueue_head (&hw
->msi_wait
);
3201 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3204 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3206 if (!hw
->msi_detected
) {
3207 /* MSI test failed, go back to INTx mode */
3208 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3209 "switching to INTx mode. Please report this failure to "
3210 "the PCI maintainer and include system chipset information.\n",
3214 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3217 sky2_write32(hw
, B0_IMSK
, 0);
3219 free_irq(pdev
->irq
, hw
);
3224 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3225 const struct pci_device_id
*ent
)
3227 struct net_device
*dev
, *dev1
= NULL
;
3229 int err
, pm_cap
, using_dac
= 0;
3231 err
= pci_enable_device(pdev
);
3233 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3238 err
= pci_request_regions(pdev
, DRV_NAME
);
3240 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3245 pci_set_master(pdev
);
3247 /* Find power-management capability. */
3248 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3250 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3253 goto err_out_free_regions
;
3256 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3257 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3259 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3261 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3262 "for consistent allocations\n", pci_name(pdev
));
3263 goto err_out_free_regions
;
3267 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3269 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3271 goto err_out_free_regions
;
3276 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3278 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3280 goto err_out_free_regions
;
3285 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3287 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3289 goto err_out_free_hw
;
3291 hw
->pm_cap
= pm_cap
;
3294 /* byte swap descriptors in hardware */
3298 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3299 reg
|= PCI_REV_DESC
;
3300 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3304 /* ring for status responses */
3305 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3308 goto err_out_iounmap
;
3310 err
= sky2_reset(hw
);
3312 goto err_out_iounmap
;
3314 printk(KERN_INFO PFX
"v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3315 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3316 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3317 hw
->chip_id
, hw
->chip_rev
);
3319 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3321 goto err_out_free_pci
;
3323 err
= register_netdev(dev
);
3325 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3327 goto err_out_free_netdev
;
3330 sky2_show_addr(dev
);
3332 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3333 if (register_netdev(dev1
) == 0)
3334 sky2_show_addr(dev1
);
3336 /* Failure to register second port need not be fatal */
3337 printk(KERN_WARNING PFX
3338 "register of second port failed\n");
3344 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3345 err
= sky2_test_msi(hw
);
3346 if (err
== -EOPNOTSUPP
)
3347 pci_disable_msi(pdev
);
3349 goto err_out_unregister
;
3352 err
= request_irq(pdev
->irq
, sky2_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3354 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3355 pci_name(pdev
), pdev
->irq
);
3356 goto err_out_unregister
;
3359 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3361 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3362 sky2_idle_start(hw
);
3364 pci_set_drvdata(pdev
, hw
);
3369 pci_disable_msi(pdev
);
3371 unregister_netdev(dev1
);
3374 unregister_netdev(dev
);
3375 err_out_free_netdev
:
3378 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3379 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3384 err_out_free_regions
:
3385 pci_release_regions(pdev
);
3386 pci_disable_device(pdev
);
3391 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3393 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3394 struct net_device
*dev0
, *dev1
;
3399 del_timer_sync(&hw
->idle_timer
);
3401 sky2_write32(hw
, B0_IMSK
, 0);
3402 synchronize_irq(hw
->pdev
->irq
);
3407 unregister_netdev(dev1
);
3408 unregister_netdev(dev0
);
3410 sky2_set_power_state(hw
, PCI_D3hot
);
3411 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3412 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3413 sky2_read8(hw
, B0_CTST
);
3415 free_irq(pdev
->irq
, hw
);
3416 pci_disable_msi(pdev
);
3417 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3418 pci_release_regions(pdev
);
3419 pci_disable_device(pdev
);
3427 pci_set_drvdata(pdev
, NULL
);
3431 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3433 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3435 pci_power_t pstate
= pci_choose_state(pdev
, state
);
3437 if (!(pstate
== PCI_D3hot
|| pstate
== PCI_D3cold
))
3440 del_timer_sync(&hw
->idle_timer
);
3441 netif_poll_disable(hw
->dev
[0]);
3443 for (i
= 0; i
< hw
->ports
; i
++) {
3444 struct net_device
*dev
= hw
->dev
[i
];
3446 if (netif_running(dev
)) {
3448 netif_device_detach(dev
);
3452 sky2_write32(hw
, B0_IMSK
, 0);
3453 pci_save_state(pdev
);
3454 sky2_set_power_state(hw
, pstate
);
3458 static int sky2_resume(struct pci_dev
*pdev
)
3460 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3463 pci_restore_state(pdev
);
3464 pci_enable_wake(pdev
, PCI_D0
, 0);
3465 sky2_set_power_state(hw
, PCI_D0
);
3467 err
= sky2_reset(hw
);
3471 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3473 for (i
= 0; i
< hw
->ports
; i
++) {
3474 struct net_device
*dev
= hw
->dev
[i
];
3475 if (netif_running(dev
)) {
3476 netif_device_attach(dev
);
3480 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3488 netif_poll_enable(hw
->dev
[0]);
3489 sky2_idle_start(hw
);
3495 static struct pci_driver sky2_driver
= {
3497 .id_table
= sky2_id_table
,
3498 .probe
= sky2_probe
,
3499 .remove
= __devexit_p(sky2_remove
),
3501 .suspend
= sky2_suspend
,
3502 .resume
= sky2_resume
,
3506 static int __init
sky2_init_module(void)
3508 return pci_register_driver(&sky2_driver
);
3511 static void __exit
sky2_cleanup_module(void)
3513 pci_unregister_driver(&sky2_driver
);
3516 module_init(sky2_init_module
);
3517 module_exit(sky2_cleanup_module
);
3519 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3520 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3521 MODULE_LICENSE("GPL");
3522 MODULE_VERSION(DRV_VERSION
);