2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.5"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
63 #define RX_LE_SIZE 512
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg
=
85 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
86 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
89 static int debug
= -1; /* defaults above */
90 module_param(debug
, int, 0);
91 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly
= 256;
94 module_param(copybreak
, int, 0);
95 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
97 static int disable_msi
= 0;
98 module_param(disable_msi
, int, 0);
99 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
101 static int idle_timeout
= 100;
102 module_param(idle_timeout
, int, 0);
103 MODULE_PARM_DESC(idle_timeout
, "Idle timeout workaround for lost interrupts (ms)");
105 static const struct pci_device_id sky2_id_table
[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) },
128 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
130 /* Avoid conditionals by using array */
131 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
132 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
133 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
135 /* This driver supports yukon2 chipset only */
136 static const char *yukon2_name
[] = {
138 "EC Ultra", /* 0xb4 */
139 "UNKNOWN", /* 0xb5 */
144 /* Access to external PHY */
145 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
149 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
150 gma_write16(hw
, port
, GM_SMI_CTRL
,
151 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
153 for (i
= 0; i
< PHY_RETRIES
; i
++) {
154 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
159 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
163 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
167 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
168 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
170 for (i
= 0; i
< PHY_RETRIES
; i
++) {
171 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
172 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
182 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
186 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
187 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
191 static void sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
197 pr_debug("sky2_set_power_state %d\n", state
);
198 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
200 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
201 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
202 (power_control
& PCI_PM_CAP_PME_D3cold
);
204 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
206 power_control
|= PCI_PM_CTRL_PME_STATUS
;
207 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
211 /* switch power to VCC (WA for VAUX problem) */
212 sky2_write8(hw
, B0_POWER_CTRL
,
213 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
215 /* disable Core Clock Division, */
216 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
218 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
219 /* enable bits are inverted */
220 sky2_write8(hw
, B2_Y2_CLK_GATE
,
221 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
222 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
223 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
225 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
227 /* Turn off phy power saving */
228 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
229 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
231 /* looks like this XL is back asswards .. */
232 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
233 reg1
|= PCI_Y2_PHY1_COMA
;
235 reg1
|= PCI_Y2_PHY2_COMA
;
238 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
239 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
240 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
241 reg1
&= P_ASPM_CONTROL_MSK
;
242 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
243 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
246 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
253 /* Turn on phy power saving */
254 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
255 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
256 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
258 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
259 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
262 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
263 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
265 /* enable bits are inverted */
266 sky2_write8(hw
, B2_Y2_CLK_GATE
,
267 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
268 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
269 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
271 /* switch power to VAUX */
272 if (vaux
&& state
!= PCI_D3cold
)
273 sky2_write8(hw
, B0_POWER_CTRL
,
274 (PC_VAUX_ENA
| PC_VCC_ENA
|
275 PC_VAUX_ON
| PC_VCC_OFF
));
278 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
281 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
282 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
285 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
291 /* disable PHY IRQs */
292 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
294 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
295 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
296 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
297 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
299 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
300 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
301 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
304 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
306 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
307 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
309 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
310 !(hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
311 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
313 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
315 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
317 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
318 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
320 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
322 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
325 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
327 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
328 /* enable automatic crossover */
329 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
331 /* disable energy detect */
332 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
334 /* enable automatic crossover */
335 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
337 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
338 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
339 ctrl
&= ~PHY_M_PC_DSC_MSK
;
340 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
343 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
345 /* workaround for deviation #4.88 (CRC errors) */
346 /* disable Automatic Crossover */
348 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
349 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
351 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
352 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
353 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
354 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
355 ctrl
&= ~PHY_M_MAC_MD_MSK
;
356 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
357 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
359 /* select page 1 to access Fiber registers */
360 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
364 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
365 if (sky2
->autoneg
== AUTONEG_DISABLE
)
370 ctrl
|= PHY_CT_RESET
;
371 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
377 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
379 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
380 ct1000
|= PHY_M_1000C_AFD
;
381 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
382 ct1000
|= PHY_M_1000C_AHD
;
383 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
384 adv
|= PHY_M_AN_100_FD
;
385 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
386 adv
|= PHY_M_AN_100_HD
;
387 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
388 adv
|= PHY_M_AN_10_FD
;
389 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
390 adv
|= PHY_M_AN_10_HD
;
391 } else /* special defines for FIBER (88E1011S only) */
392 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
394 /* Set Flow-control capabilities */
395 if (sky2
->tx_pause
&& sky2
->rx_pause
)
396 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
397 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
398 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
399 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
400 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
402 /* Restart Auto-negotiation */
403 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
405 /* forced speed/duplex settings */
406 ct1000
= PHY_M_1000C_MSE
;
408 if (sky2
->duplex
== DUPLEX_FULL
)
409 ctrl
|= PHY_CT_DUP_MD
;
411 switch (sky2
->speed
) {
413 ctrl
|= PHY_CT_SP1000
;
416 ctrl
|= PHY_CT_SP100
;
420 ctrl
|= PHY_CT_RESET
;
423 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
424 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
426 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
427 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
429 /* Setup Phy LED's */
430 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
433 switch (hw
->chip_id
) {
434 case CHIP_ID_YUKON_FE
:
435 /* on 88E3082 these bits are at 11..9 (shifted left) */
436 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
438 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
440 /* delete ACT LED control bits */
441 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
442 /* change ACT LED control to blink mode */
443 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
444 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
447 case CHIP_ID_YUKON_XL
:
448 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
450 /* select page 3 to access LED control register */
451 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
453 /* set LED Function Control register */
454 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
455 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
456 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
457 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
458 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
460 /* set Polarity Control register */
461 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
462 (PHY_M_POLC_LS1_P_MIX(4) |
463 PHY_M_POLC_IS0_P_MIX(4) |
464 PHY_M_POLC_LOS_CTRL(2) |
465 PHY_M_POLC_INIT_CTRL(2) |
466 PHY_M_POLC_STA1_CTRL(2) |
467 PHY_M_POLC_STA0_CTRL(2)));
469 /* restore page register */
470 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
472 case CHIP_ID_YUKON_EC_U
:
473 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
475 /* select page 3 to access LED control register */
476 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
478 /* set LED Function Control register */
479 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
480 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
481 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
482 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
483 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
485 /* set Blink Rate in LED Timer Control Register */
486 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
487 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
488 /* restore page register */
489 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
493 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
494 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
495 /* turn off the Rx LED (LED_RX) */
496 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
499 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
500 /* apply fixes in PHY AFE */
501 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
502 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
504 /* increase differential signal amplitude in 10BASE-T */
505 gm_phy_write(hw
, port
, 0x18, 0xaa99);
506 gm_phy_write(hw
, port
, 0x17, 0x2011);
508 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
509 gm_phy_write(hw
, port
, 0x18, 0xa204);
510 gm_phy_write(hw
, port
, 0x17, 0x2002);
512 /* set page register to 0 */
513 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
515 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
517 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
518 /* turn on 100 Mbps LED (LED_LINK100) */
519 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
523 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
526 /* Enable phy interrupt on auto-negotiation complete (or link up) */
527 if (sky2
->autoneg
== AUTONEG_ENABLE
)
528 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
530 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
533 /* Force a renegotiation */
534 static void sky2_phy_reinit(struct sky2_port
*sky2
)
536 spin_lock_bh(&sky2
->phy_lock
);
537 sky2_phy_init(sky2
->hw
, sky2
->port
);
538 spin_unlock_bh(&sky2
->phy_lock
);
541 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
543 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
546 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
548 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
549 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
551 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
553 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
554 /* WA DEV_472 -- looks like crossed wires on port 2 */
555 /* clear GMAC 1 Control reset */
556 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
558 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
559 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
560 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
561 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
562 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
565 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
566 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
567 reg
|= GM_GPCR_AU_ALL_DIS
;
568 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
569 gma_read16(hw
, port
, GM_GP_CTRL
);
571 switch (sky2
->speed
) {
573 reg
&= ~GM_GPCR_SPEED_100
;
574 reg
|= GM_GPCR_SPEED_1000
;
577 reg
&= ~GM_GPCR_SPEED_1000
;
578 reg
|= GM_GPCR_SPEED_100
;
581 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
585 if (sky2
->duplex
== DUPLEX_FULL
)
586 reg
|= GM_GPCR_DUP_FULL
;
588 /* turn off pause in 10/100mbps half duplex */
589 else if (sky2
->speed
!= SPEED_1000
&&
590 hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
591 sky2
->tx_pause
= sky2
->rx_pause
= 0;
593 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
595 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
596 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
598 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
599 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
600 /* disable Rx flow-control */
601 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
604 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
606 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
608 spin_lock_bh(&sky2
->phy_lock
);
609 sky2_phy_init(hw
, port
);
610 spin_unlock_bh(&sky2
->phy_lock
);
613 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
614 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
616 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
617 gma_read16(hw
, port
, i
);
618 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
620 /* transmit control */
621 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
623 /* receive control reg: unicast + multicast + no FCS */
624 gma_write16(hw
, port
, GM_RX_CTRL
,
625 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
627 /* transmit flow control */
628 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
630 /* transmit parameter */
631 gma_write16(hw
, port
, GM_TX_PARAM
,
632 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
633 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
634 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
635 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
637 /* serial mode register */
638 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
639 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
641 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
642 reg
|= GM_SMOD_JUMBO_ENA
;
644 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
646 /* virtual address for data */
647 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
649 /* physical address: used for pause frames */
650 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
652 /* ignore counter overflows */
653 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
654 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
655 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
657 /* Configure Rx MAC FIFO */
658 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
659 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
660 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
662 /* Flush Rx MAC FIFO on any flow control or error */
663 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
665 /* Set threshold to 0xa (64 bytes)
666 * ASF disabled so no need to do WA dev #4.30
668 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
670 /* Configure Tx MAC FIFO */
671 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
672 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
674 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
675 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
676 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
677 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
678 /* set Tx GMAC FIFO Almost Empty Threshold */
679 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
680 /* Disable Store & Forward mode for TX */
681 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
687 /* Assign Ram Buffer allocation.
688 * start and end are in units of 4k bytes
689 * ram registers are in units of 64bit words
691 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
695 start
= startk
* 4096/8;
696 end
= (endk
* 4096/8) - 1;
698 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
699 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
700 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
701 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
702 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
704 if (q
== Q_R1
|| q
== Q_R2
) {
705 u32 space
= (endk
- startk
) * 4096/8;
706 u32 tp
= space
- space
/4;
708 /* On receive queue's set the thresholds
709 * give receiver priority when > 3/4 full
710 * send pause when down to 2K
712 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
713 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
716 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
717 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
719 /* Enable store & forward on Tx queue's because
720 * Tx FIFO is only 1K on Yukon
722 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
725 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
726 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
729 /* Setup Bus Memory Interface */
730 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
732 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
733 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
734 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
735 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
738 /* Setup prefetch unit registers. This is the interface between
739 * hardware and driver list elements
741 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
744 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
745 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
746 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
747 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
748 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
749 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
751 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
754 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
756 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
758 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
762 /* Update chip's next pointer */
763 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
766 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
771 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
773 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
774 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
778 /* Return high part of DMA address (could be 32 or 64 bit) */
779 static inline u32
high32(dma_addr_t a
)
781 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
784 /* Build description to hardware about buffer */
785 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
787 struct sky2_rx_le
*le
;
788 u32 hi
= high32(map
);
789 u16 len
= sky2
->rx_bufsize
;
791 if (sky2
->rx_addr64
!= hi
) {
792 le
= sky2_next_rx(sky2
);
793 le
->addr
= cpu_to_le32(hi
);
795 le
->opcode
= OP_ADDR64
| HW_OWNER
;
796 sky2
->rx_addr64
= high32(map
+ len
);
799 le
= sky2_next_rx(sky2
);
800 le
->addr
= cpu_to_le32((u32
) map
);
801 le
->length
= cpu_to_le16(len
);
803 le
->opcode
= OP_PACKET
| HW_OWNER
;
807 /* Tell chip where to start receive checksum.
808 * Actually has two checksums, but set both same to avoid possible byte
811 static void rx_set_checksum(struct sky2_port
*sky2
)
813 struct sky2_rx_le
*le
;
815 le
= sky2_next_rx(sky2
);
816 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
818 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
820 sky2_write32(sky2
->hw
,
821 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
822 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
827 * The RX Stop command will not work for Yukon-2 if the BMU does not
828 * reach the end of packet and since we can't make sure that we have
829 * incoming data, we must reset the BMU while it is not doing a DMA
830 * transfer. Since it is possible that the RX path is still active,
831 * the RX RAM buffer will be stopped first, so any possible incoming
832 * data will not trigger a DMA. After the RAM buffer is stopped, the
833 * BMU is polled until any DMA in progress is ended and only then it
836 static void sky2_rx_stop(struct sky2_port
*sky2
)
838 struct sky2_hw
*hw
= sky2
->hw
;
839 unsigned rxq
= rxqaddr
[sky2
->port
];
842 /* disable the RAM Buffer receive queue */
843 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
845 for (i
= 0; i
< 0xffff; i
++)
846 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
847 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
850 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
853 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
855 /* reset the Rx prefetch unit */
856 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
859 /* Clean out receive buffer area, assumes receiver hardware stopped */
860 static void sky2_rx_clean(struct sky2_port
*sky2
)
864 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
865 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
866 struct ring_info
*re
= sky2
->rx_ring
+ i
;
869 pci_unmap_single(sky2
->hw
->pdev
,
870 re
->mapaddr
, sky2
->rx_bufsize
,
878 /* Basic MII support */
879 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
881 struct mii_ioctl_data
*data
= if_mii(ifr
);
882 struct sky2_port
*sky2
= netdev_priv(dev
);
883 struct sky2_hw
*hw
= sky2
->hw
;
884 int err
= -EOPNOTSUPP
;
886 if (!netif_running(dev
))
887 return -ENODEV
; /* Phy still in reset */
891 data
->phy_id
= PHY_ADDR_MARV
;
897 spin_lock_bh(&sky2
->phy_lock
);
898 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
899 spin_unlock_bh(&sky2
->phy_lock
);
906 if (!capable(CAP_NET_ADMIN
))
909 spin_lock_bh(&sky2
->phy_lock
);
910 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
912 spin_unlock_bh(&sky2
->phy_lock
);
918 #ifdef SKY2_VLAN_TAG_USED
919 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
921 struct sky2_port
*sky2
= netdev_priv(dev
);
922 struct sky2_hw
*hw
= sky2
->hw
;
923 u16 port
= sky2
->port
;
925 spin_lock_bh(&sky2
->tx_lock
);
927 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
928 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
931 spin_unlock_bh(&sky2
->tx_lock
);
934 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
936 struct sky2_port
*sky2
= netdev_priv(dev
);
937 struct sky2_hw
*hw
= sky2
->hw
;
938 u16 port
= sky2
->port
;
940 spin_lock_bh(&sky2
->tx_lock
);
942 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
943 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
945 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
947 spin_unlock_bh(&sky2
->tx_lock
);
952 * It appears the hardware has a bug in the FIFO logic that
953 * cause it to hang if the FIFO gets overrun and the receive buffer
954 * is not aligned. ALso alloc_skb() won't align properly if slab
955 * debugging is enabled.
957 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
961 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
963 unsigned long p
= (unsigned long) skb
->data
;
964 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
971 * Allocate and setup receiver buffer pool.
972 * In case of 64 bit dma, there are 2X as many list elements
973 * available as ring entries
974 * and need to reserve one list element so we don't wrap around.
976 static int sky2_rx_start(struct sky2_port
*sky2
)
978 struct sky2_hw
*hw
= sky2
->hw
;
979 unsigned rxq
= rxqaddr
[sky2
->port
];
983 sky2
->rx_put
= sky2
->rx_next
= 0;
986 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
987 /* MAC Rx RAM Read is controlled by hardware */
988 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
991 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
993 rx_set_checksum(sky2
);
994 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
995 struct ring_info
*re
= sky2
->rx_ring
+ i
;
997 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
1001 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
1002 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1003 sky2_rx_add(sky2
, re
->mapaddr
);
1008 * The receiver hangs if it receives frames larger than the
1009 * packet buffer. As a workaround, truncate oversize frames, but
1010 * the register is limited to 9 bits, so if you do frames > 2052
1011 * you better get the MTU right!
1013 thresh
= (sky2
->rx_bufsize
- 8) / sizeof(u32
);
1015 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1017 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1018 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1022 /* Tell chip about available buffers */
1023 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1026 sky2_rx_clean(sky2
);
1030 /* Bring up network interface. */
1031 static int sky2_up(struct net_device
*dev
)
1033 struct sky2_port
*sky2
= netdev_priv(dev
);
1034 struct sky2_hw
*hw
= sky2
->hw
;
1035 unsigned port
= sky2
->port
;
1036 u32 ramsize
, rxspace
, imask
;
1037 int cap
, err
= -ENOMEM
;
1038 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1041 * On dual port PCI-X card, there is an problem where status
1042 * can be received out of order due to split transactions
1044 if (otherdev
&& netif_running(otherdev
) &&
1045 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1046 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1049 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1050 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1051 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1057 if (netif_msg_ifup(sky2
))
1058 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1060 /* must be power of 2 */
1061 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1063 sizeof(struct sky2_tx_le
),
1068 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1072 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1074 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1078 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1080 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1085 sky2_mac_init(hw
, port
);
1087 /* Determine available ram buffer space (in 4K blocks).
1088 * Note: not sure about the FE setting below yet
1090 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1093 ramsize
= sky2_read8(hw
, B2_E_0
);
1095 /* Give transmitter one third (rounded up) */
1096 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1098 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1099 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1101 /* Make sure SyncQ is disabled */
1102 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1105 sky2_qset(hw
, txqaddr
[port
]);
1107 /* Set almost empty threshold */
1108 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== 1)
1109 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1111 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1114 err
= sky2_rx_start(sky2
);
1118 /* Enable interrupts from phy/mac for port */
1119 imask
= sky2_read32(hw
, B0_IMSK
);
1120 imask
|= portirq_msk
[port
];
1121 sky2_write32(hw
, B0_IMSK
, imask
);
1127 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1128 sky2
->rx_le
, sky2
->rx_le_map
);
1132 pci_free_consistent(hw
->pdev
,
1133 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1134 sky2
->tx_le
, sky2
->tx_le_map
);
1137 kfree(sky2
->tx_ring
);
1138 kfree(sky2
->rx_ring
);
1140 sky2
->tx_ring
= NULL
;
1141 sky2
->rx_ring
= NULL
;
1145 /* Modular subtraction in ring */
1146 static inline int tx_dist(unsigned tail
, unsigned head
)
1148 return (head
- tail
) & (TX_RING_SIZE
- 1);
1151 /* Number of list elements available for next tx */
1152 static inline int tx_avail(const struct sky2_port
*sky2
)
1154 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1157 /* Estimate of number of transmit list elements required */
1158 static unsigned tx_le_req(const struct sk_buff
*skb
)
1162 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1163 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1165 if (skb_is_gso(skb
))
1168 if (skb
->ip_summed
== CHECKSUM_HW
)
1175 * Put one packet in ring for transmit.
1176 * A single packet can generate multiple list elements, and
1177 * the number of ring elements will probably be less than the number
1178 * of list elements used.
1180 * No BH disabling for tx_lock here (like tg3)
1182 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1184 struct sky2_port
*sky2
= netdev_priv(dev
);
1185 struct sky2_hw
*hw
= sky2
->hw
;
1186 struct sky2_tx_le
*le
= NULL
;
1187 struct tx_ring_info
*re
;
1195 /* No BH disabling for tx_lock here. We are running in BH disabled
1196 * context and TX reclaim runs via poll inside of a software
1197 * interrupt, and no related locks in IRQ processing.
1199 if (!spin_trylock(&sky2
->tx_lock
))
1200 return NETDEV_TX_LOCKED
;
1202 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1203 /* There is a known but harmless race with lockless tx
1204 * and netif_stop_queue.
1206 if (!netif_queue_stopped(dev
)) {
1207 netif_stop_queue(dev
);
1208 if (net_ratelimit())
1209 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1212 spin_unlock(&sky2
->tx_lock
);
1214 return NETDEV_TX_BUSY
;
1217 if (unlikely(netif_msg_tx_queued(sky2
)))
1218 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1219 dev
->name
, sky2
->tx_prod
, skb
->len
);
1221 len
= skb_headlen(skb
);
1222 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1223 addr64
= high32(mapping
);
1225 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1227 /* Send high bits if changed or crosses boundary */
1228 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1229 le
= get_tx_le(sky2
);
1230 le
->tx
.addr
= cpu_to_le32(addr64
);
1232 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1233 sky2
->tx_addr64
= high32(mapping
+ len
);
1236 /* Check for TCP Segmentation Offload */
1237 mss
= skb_shinfo(skb
)->gso_size
;
1239 /* just drop the packet if non-linear expansion fails */
1240 if (skb_header_cloned(skb
) &&
1241 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1246 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1247 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1251 if (mss
!= sky2
->tx_last_mss
) {
1252 le
= get_tx_le(sky2
);
1253 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1254 le
->tx
.tso
.rsvd
= 0;
1255 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1257 sky2
->tx_last_mss
= mss
;
1261 #ifdef SKY2_VLAN_TAG_USED
1262 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1263 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1265 le
= get_tx_le(sky2
);
1267 le
->opcode
= OP_VLAN
|HW_OWNER
;
1270 le
->opcode
|= OP_VLAN
;
1271 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1276 /* Handle TCP checksum offload */
1277 if (skb
->ip_summed
== CHECKSUM_HW
) {
1278 u16 hdr
= skb
->h
.raw
- skb
->data
;
1279 u16 offset
= hdr
+ skb
->csum
;
1281 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1282 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1285 le
= get_tx_le(sky2
);
1286 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1287 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1288 le
->length
= 0; /* initial checksum value */
1289 le
->ctrl
= 1; /* one packet */
1290 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1293 le
= get_tx_le(sky2
);
1294 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1295 le
->length
= cpu_to_le16(len
);
1297 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1299 /* Record the transmit mapping info */
1301 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1303 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1304 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1305 struct tx_ring_info
*fre
;
1307 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1308 frag
->size
, PCI_DMA_TODEVICE
);
1309 addr64
= high32(mapping
);
1310 if (addr64
!= sky2
->tx_addr64
) {
1311 le
= get_tx_le(sky2
);
1312 le
->tx
.addr
= cpu_to_le32(addr64
);
1314 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1315 sky2
->tx_addr64
= addr64
;
1318 le
= get_tx_le(sky2
);
1319 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1320 le
->length
= cpu_to_le16(frag
->size
);
1322 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1325 + RING_NEXT((re
- sky2
->tx_ring
) + i
, TX_RING_SIZE
);
1326 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1329 re
->idx
= sky2
->tx_prod
;
1332 avail
= tx_avail(sky2
);
1333 if (mss
!= 0 || avail
< TX_MIN_PENDING
) {
1334 le
->ctrl
|= FRC_STAT
;
1335 if (avail
<= MAX_SKB_TX_LE
)
1336 netif_stop_queue(dev
);
1339 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1342 spin_unlock(&sky2
->tx_lock
);
1344 dev
->trans_start
= jiffies
;
1345 return NETDEV_TX_OK
;
1349 * Free ring elements from starting at tx_cons until "done"
1351 * NB: the hardware will tell us about partial completion of multi-part
1352 * buffers; these are deferred until completion.
1354 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1356 struct net_device
*dev
= sky2
->netdev
;
1357 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1361 BUG_ON(done
>= TX_RING_SIZE
);
1363 if (unlikely(netif_msg_tx_done(sky2
)))
1364 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1367 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1368 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1369 struct sk_buff
*skb
= re
->skb
;
1372 BUG_ON(nxt
>= TX_RING_SIZE
);
1373 prefetch(sky2
->tx_ring
+ nxt
);
1375 /* Check for partial status */
1376 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1380 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1381 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1383 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1384 struct tx_ring_info
*fre
;
1385 fre
= sky2
->tx_ring
+ RING_NEXT(put
+ i
, TX_RING_SIZE
);
1386 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1387 skb_shinfo(skb
)->frags
[i
].size
,
1394 sky2
->tx_cons
= put
;
1395 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1396 netif_wake_queue(dev
);
1399 /* Cleanup all untransmitted buffers, assume transmitter not running */
1400 static void sky2_tx_clean(struct sky2_port
*sky2
)
1402 spin_lock_bh(&sky2
->tx_lock
);
1403 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1404 spin_unlock_bh(&sky2
->tx_lock
);
1407 /* Network shutdown */
1408 static int sky2_down(struct net_device
*dev
)
1410 struct sky2_port
*sky2
= netdev_priv(dev
);
1411 struct sky2_hw
*hw
= sky2
->hw
;
1412 unsigned port
= sky2
->port
;
1416 /* Never really got started! */
1420 if (netif_msg_ifdown(sky2
))
1421 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1423 /* Stop more packets from being queued */
1424 netif_stop_queue(dev
);
1426 sky2_phy_reset(hw
, port
);
1428 /* Stop transmitter */
1429 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1430 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1432 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1433 RB_RST_SET
| RB_DIS_OP_MD
);
1435 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1436 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1437 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1439 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1441 /* Workaround shared GMAC reset */
1442 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1443 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1444 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1446 /* Disable Force Sync bit and Enable Alloc bit */
1447 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1448 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1450 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1451 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1452 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1454 /* Reset the PCI FIFO of the async Tx queue */
1455 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1456 BMU_RST_SET
| BMU_FIFO_RST
);
1458 /* Reset the Tx prefetch units */
1459 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1462 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1466 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1467 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1469 /* Disable port IRQ */
1470 imask
= sky2_read32(hw
, B0_IMSK
);
1471 imask
&= ~portirq_msk
[port
];
1472 sky2_write32(hw
, B0_IMSK
, imask
);
1474 /* turn off LED's */
1475 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1477 synchronize_irq(hw
->pdev
->irq
);
1479 sky2_tx_clean(sky2
);
1480 sky2_rx_clean(sky2
);
1482 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1483 sky2
->rx_le
, sky2
->rx_le_map
);
1484 kfree(sky2
->rx_ring
);
1486 pci_free_consistent(hw
->pdev
,
1487 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1488 sky2
->tx_le
, sky2
->tx_le_map
);
1489 kfree(sky2
->tx_ring
);
1494 sky2
->rx_ring
= NULL
;
1495 sky2
->tx_ring
= NULL
;
1500 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1505 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1506 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1508 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1509 case PHY_M_PS_SPEED_1000
:
1511 case PHY_M_PS_SPEED_100
:
1518 static void sky2_link_up(struct sky2_port
*sky2
)
1520 struct sky2_hw
*hw
= sky2
->hw
;
1521 unsigned port
= sky2
->port
;
1524 /* Enable Transmit FIFO Underrun */
1525 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1527 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1528 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1529 reg
|= GM_GPCR_AU_ALL_DIS
;
1531 /* Is write/read necessary? Copied from sky2_mac_init */
1532 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1533 gma_read16(hw
, port
, GM_GP_CTRL
);
1535 switch (sky2
->speed
) {
1537 reg
&= ~GM_GPCR_SPEED_100
;
1538 reg
|= GM_GPCR_SPEED_1000
;
1541 reg
&= ~GM_GPCR_SPEED_1000
;
1542 reg
|= GM_GPCR_SPEED_100
;
1545 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1549 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1551 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1552 reg
|= GM_GPCR_DUP_FULL
;
1555 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1556 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1557 gma_read16(hw
, port
, GM_GP_CTRL
);
1559 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1561 netif_carrier_on(sky2
->netdev
);
1562 netif_wake_queue(sky2
->netdev
);
1564 /* Turn on link LED */
1565 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1566 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1568 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1569 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1570 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1572 switch(sky2
->speed
) {
1574 led
|= PHY_M_LEDC_INIT_CTRL(7);
1578 led
|= PHY_M_LEDC_STA1_CTRL(7);
1582 led
|= PHY_M_LEDC_STA0_CTRL(7);
1586 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1587 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1588 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1591 if (netif_msg_link(sky2
))
1592 printk(KERN_INFO PFX
1593 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1594 sky2
->netdev
->name
, sky2
->speed
,
1595 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1596 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1597 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1600 static void sky2_link_down(struct sky2_port
*sky2
)
1602 struct sky2_hw
*hw
= sky2
->hw
;
1603 unsigned port
= sky2
->port
;
1606 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1608 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1609 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1610 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1611 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1613 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1614 /* restore Asymmetric Pause bit */
1615 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1616 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1620 netif_carrier_off(sky2
->netdev
);
1621 netif_stop_queue(sky2
->netdev
);
1623 /* Turn on link LED */
1624 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1626 if (netif_msg_link(sky2
))
1627 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1628 sky2_phy_init(hw
, port
);
1631 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1633 struct sky2_hw
*hw
= sky2
->hw
;
1634 unsigned port
= sky2
->port
;
1637 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1639 if (lpa
& PHY_M_AN_RF
) {
1640 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1644 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1645 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1646 printk(KERN_ERR PFX
"%s: master/slave fault",
1647 sky2
->netdev
->name
);
1651 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1652 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1653 sky2
->netdev
->name
);
1657 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1659 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1661 /* Pause bits are offset (9..8) */
1662 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1665 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1666 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1668 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1669 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1670 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1672 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1677 /* Interrupt from PHY */
1678 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1680 struct net_device
*dev
= hw
->dev
[port
];
1681 struct sky2_port
*sky2
= netdev_priv(dev
);
1682 u16 istatus
, phystat
;
1684 spin_lock(&sky2
->phy_lock
);
1685 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1686 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1688 if (!netif_running(dev
))
1691 if (netif_msg_intr(sky2
))
1692 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1693 sky2
->netdev
->name
, istatus
, phystat
);
1695 if (istatus
& PHY_M_IS_AN_COMPL
) {
1696 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1701 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1702 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1704 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1706 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1708 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1709 if (phystat
& PHY_M_PS_LINK_UP
)
1712 sky2_link_down(sky2
);
1715 spin_unlock(&sky2
->phy_lock
);
1719 /* Transmit timeout is only called if we are running, carries is up
1720 * and tx queue is full (stopped).
1722 static void sky2_tx_timeout(struct net_device
*dev
)
1724 struct sky2_port
*sky2
= netdev_priv(dev
);
1725 struct sky2_hw
*hw
= sky2
->hw
;
1726 unsigned txq
= txqaddr
[sky2
->port
];
1729 if (netif_msg_timer(sky2
))
1730 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1732 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1733 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1735 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1737 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1739 if (report
!= done
) {
1740 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1742 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1743 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1744 } else if (report
!= sky2
->tx_cons
) {
1745 printk(KERN_INFO PFX
"status report lost?\n");
1747 spin_lock_bh(&sky2
->tx_lock
);
1748 sky2_tx_complete(sky2
, report
);
1749 spin_unlock_bh(&sky2
->tx_lock
);
1751 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1753 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1754 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1756 sky2_tx_clean(sky2
);
1759 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1764 /* Want receive buffer size to be multiple of 64 bits
1765 * and incl room for vlan and truncation
1767 static inline unsigned sky2_buf_size(int mtu
)
1769 return ALIGN(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1772 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1774 struct sky2_port
*sky2
= netdev_priv(dev
);
1775 struct sky2_hw
*hw
= sky2
->hw
;
1780 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1783 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1786 if (!netif_running(dev
)) {
1791 imask
= sky2_read32(hw
, B0_IMSK
);
1792 sky2_write32(hw
, B0_IMSK
, 0);
1794 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1795 netif_stop_queue(dev
);
1796 netif_poll_disable(hw
->dev
[0]);
1798 synchronize_irq(hw
->pdev
->irq
);
1800 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1801 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1803 sky2_rx_clean(sky2
);
1806 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1807 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1808 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1810 if (dev
->mtu
> ETH_DATA_LEN
)
1811 mode
|= GM_SMOD_JUMBO_ENA
;
1813 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1815 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1817 err
= sky2_rx_start(sky2
);
1818 sky2_write32(hw
, B0_IMSK
, imask
);
1823 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1825 netif_poll_enable(hw
->dev
[0]);
1826 netif_wake_queue(dev
);
1833 * Receive one packet.
1834 * For small packets or errors, just reuse existing skb.
1835 * For larger packets, get new buffer.
1837 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1838 u16 length
, u32 status
)
1840 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1841 struct sk_buff
*skb
= NULL
;
1843 if (unlikely(netif_msg_rx_status(sky2
)))
1844 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1845 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1847 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1848 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1850 if (status
& GMR_FS_ANY_ERR
)
1853 if (!(status
& GMR_FS_RX_OK
))
1856 if (length
> sky2
->netdev
->mtu
+ ETH_HLEN
)
1859 if (length
< copybreak
) {
1860 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1864 skb_reserve(skb
, 2);
1865 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1866 length
, PCI_DMA_FROMDEVICE
);
1867 memcpy(skb
->data
, re
->skb
->data
, length
);
1868 skb
->ip_summed
= re
->skb
->ip_summed
;
1869 skb
->csum
= re
->skb
->csum
;
1870 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1871 length
, PCI_DMA_FROMDEVICE
);
1873 struct sk_buff
*nskb
;
1875 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1881 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1882 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1883 prefetch(skb
->data
);
1885 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1886 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1889 skb_put(skb
, length
);
1891 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1892 sky2_rx_add(sky2
, re
->mapaddr
);
1897 ++sky2
->net_stats
.rx_over_errors
;
1901 ++sky2
->net_stats
.rx_errors
;
1903 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1904 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1905 sky2
->netdev
->name
, status
, length
);
1907 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1908 sky2
->net_stats
.rx_length_errors
++;
1909 if (status
& GMR_FS_FRAGMENT
)
1910 sky2
->net_stats
.rx_frame_errors
++;
1911 if (status
& GMR_FS_CRC_ERR
)
1912 sky2
->net_stats
.rx_crc_errors
++;
1913 if (status
& GMR_FS_RX_FF_OV
)
1914 sky2
->net_stats
.rx_fifo_errors
++;
1919 /* Transmit complete */
1920 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
1922 struct sky2_port
*sky2
= netdev_priv(dev
);
1924 if (netif_running(dev
)) {
1925 spin_lock(&sky2
->tx_lock
);
1926 sky2_tx_complete(sky2
, last
);
1927 spin_unlock(&sky2
->tx_lock
);
1931 /* Is status ring empty or is there more to do? */
1932 static inline int sky2_more_work(const struct sky2_hw
*hw
)
1934 return (hw
->st_idx
!= sky2_read16(hw
, STAT_PUT_IDX
));
1937 /* Process status response ring */
1938 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
1940 struct sky2_port
*sky2
;
1942 unsigned buf_write
[2] = { 0, 0 };
1943 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1947 while (hw
->st_idx
!= hwidx
) {
1948 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1949 struct net_device
*dev
;
1950 struct sk_buff
*skb
;
1954 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
1956 BUG_ON(le
->link
>= 2);
1957 dev
= hw
->dev
[le
->link
];
1959 sky2
= netdev_priv(dev
);
1960 length
= le
->length
;
1961 status
= le
->status
;
1963 switch (le
->opcode
& ~HW_OWNER
) {
1965 skb
= sky2_receive(sky2
, length
, status
);
1970 skb
->protocol
= eth_type_trans(skb
, dev
);
1971 dev
->last_rx
= jiffies
;
1973 #ifdef SKY2_VLAN_TAG_USED
1974 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1975 vlan_hwaccel_receive_skb(skb
,
1977 be16_to_cpu(sky2
->rx_tag
));
1980 netif_receive_skb(skb
);
1982 /* Update receiver after 16 frames */
1983 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
1984 sky2_put_idx(hw
, rxqaddr
[le
->link
],
1986 buf_write
[le
->link
] = 0;
1989 /* Stop after net poll weight */
1990 if (++work_done
>= to_do
)
1994 #ifdef SKY2_VLAN_TAG_USED
1996 sky2
->rx_tag
= length
;
2000 sky2
->rx_tag
= length
;
2004 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2005 skb
->ip_summed
= CHECKSUM_HW
;
2006 skb
->csum
= le16_to_cpu(status
);
2010 /* TX index reports status for both ports */
2011 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2012 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2014 sky2_tx_done(hw
->dev
[1],
2015 ((status
>> 24) & 0xff)
2016 | (u16
)(length
& 0xf) << 8);
2020 if (net_ratelimit())
2021 printk(KERN_WARNING PFX
2022 "unknown status opcode 0x%x\n", le
->opcode
);
2029 sky2
= netdev_priv(hw
->dev
[0]);
2030 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2034 sky2
= netdev_priv(hw
->dev
[1]);
2035 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2041 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2043 struct net_device
*dev
= hw
->dev
[port
];
2045 if (net_ratelimit())
2046 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2049 if (status
& Y2_IS_PAR_RD1
) {
2050 if (net_ratelimit())
2051 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2054 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2057 if (status
& Y2_IS_PAR_WR1
) {
2058 if (net_ratelimit())
2059 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2062 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2065 if (status
& Y2_IS_PAR_MAC1
) {
2066 if (net_ratelimit())
2067 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2068 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2071 if (status
& Y2_IS_PAR_RX1
) {
2072 if (net_ratelimit())
2073 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2074 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2077 if (status
& Y2_IS_TCP_TXA1
) {
2078 if (net_ratelimit())
2079 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2081 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2085 static void sky2_hw_intr(struct sky2_hw
*hw
)
2087 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2089 if (status
& Y2_IS_TIST_OV
)
2090 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2092 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2095 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2096 if (net_ratelimit())
2097 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2098 pci_name(hw
->pdev
), pci_err
);
2100 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2101 sky2_pci_write16(hw
, PCI_STATUS
,
2102 pci_err
| PCI_STATUS_ERROR_BITS
);
2103 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2106 if (status
& Y2_IS_PCI_EXP
) {
2107 /* PCI-Express uncorrectable Error occurred */
2110 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2112 if (net_ratelimit())
2113 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2114 pci_name(hw
->pdev
), pex_err
);
2116 /* clear the interrupt */
2117 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2118 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2120 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2122 if (pex_err
& PEX_FATAL_ERRORS
) {
2123 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2124 hwmsk
&= ~Y2_IS_PCI_EXP
;
2125 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2129 if (status
& Y2_HWE_L1_MASK
)
2130 sky2_hw_error(hw
, 0, status
);
2132 if (status
& Y2_HWE_L1_MASK
)
2133 sky2_hw_error(hw
, 1, status
);
2136 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2138 struct net_device
*dev
= hw
->dev
[port
];
2139 struct sky2_port
*sky2
= netdev_priv(dev
);
2140 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2142 if (netif_msg_intr(sky2
))
2143 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2146 if (status
& GM_IS_RX_FF_OR
) {
2147 ++sky2
->net_stats
.rx_fifo_errors
;
2148 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2151 if (status
& GM_IS_TX_FF_UR
) {
2152 ++sky2
->net_stats
.tx_fifo_errors
;
2153 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2157 /* This should never happen it is a fatal situation */
2158 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2159 const char *rxtx
, u32 mask
)
2161 struct net_device
*dev
= hw
->dev
[port
];
2162 struct sky2_port
*sky2
= netdev_priv(dev
);
2165 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2166 dev
? dev
->name
: "<not registered>", rxtx
);
2168 imask
= sky2_read32(hw
, B0_IMSK
);
2170 sky2_write32(hw
, B0_IMSK
, imask
);
2173 spin_lock(&sky2
->phy_lock
);
2174 sky2_link_down(sky2
);
2175 spin_unlock(&sky2
->phy_lock
);
2179 /* If idle then force a fake soft NAPI poll once a second
2180 * to work around cases where sharing an edge triggered interrupt.
2182 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2184 if (idle_timeout
> 0)
2185 mod_timer(&hw
->idle_timer
,
2186 jiffies
+ msecs_to_jiffies(idle_timeout
));
2189 static void sky2_idle(unsigned long arg
)
2191 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2192 struct net_device
*dev
= hw
->dev
[0];
2194 if (__netif_rx_schedule_prep(dev
))
2195 __netif_rx_schedule(dev
);
2197 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2201 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2203 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2204 int work_limit
= min(dev0
->quota
, *budget
);
2206 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2208 if (status
& Y2_IS_HW_ERR
)
2211 if (status
& Y2_IS_IRQ_PHY1
)
2212 sky2_phy_intr(hw
, 0);
2214 if (status
& Y2_IS_IRQ_PHY2
)
2215 sky2_phy_intr(hw
, 1);
2217 if (status
& Y2_IS_IRQ_MAC1
)
2218 sky2_mac_intr(hw
, 0);
2220 if (status
& Y2_IS_IRQ_MAC2
)
2221 sky2_mac_intr(hw
, 1);
2223 if (status
& Y2_IS_CHK_RX1
)
2224 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2226 if (status
& Y2_IS_CHK_RX2
)
2227 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2229 if (status
& Y2_IS_CHK_TXA1
)
2230 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2232 if (status
& Y2_IS_CHK_TXA2
)
2233 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2235 work_done
= sky2_status_intr(hw
, work_limit
);
2236 *budget
-= work_done
;
2237 dev0
->quota
-= work_done
;
2239 if (status
& Y2_IS_STAT_BMU
)
2240 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2242 if (sky2_more_work(hw
))
2245 netif_rx_complete(dev0
);
2247 sky2_read32(hw
, B0_Y2_SP_LISR
);
2251 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2253 struct sky2_hw
*hw
= dev_id
;
2254 struct net_device
*dev0
= hw
->dev
[0];
2257 /* Reading this mask interrupts as side effect */
2258 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2259 if (status
== 0 || status
== ~0)
2262 prefetch(&hw
->st_le
[hw
->st_idx
]);
2263 if (likely(__netif_rx_schedule_prep(dev0
)))
2264 __netif_rx_schedule(dev0
);
2269 #ifdef CONFIG_NET_POLL_CONTROLLER
2270 static void sky2_netpoll(struct net_device
*dev
)
2272 struct sky2_port
*sky2
= netdev_priv(dev
);
2273 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2275 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2276 __netif_rx_schedule(dev0
);
2280 /* Chip internal frequency for clock calculations */
2281 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2283 switch (hw
->chip_id
) {
2284 case CHIP_ID_YUKON_EC
:
2285 case CHIP_ID_YUKON_EC_U
:
2286 return 125; /* 125 Mhz */
2287 case CHIP_ID_YUKON_FE
:
2288 return 100; /* 100 Mhz */
2289 default: /* YUKON_XL */
2290 return 156; /* 156 Mhz */
2294 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2296 return sky2_mhz(hw
) * us
;
2299 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2301 return clk
/ sky2_mhz(hw
);
2305 static int sky2_reset(struct sky2_hw
*hw
)
2311 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2313 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2314 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2315 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2316 pci_name(hw
->pdev
), hw
->chip_id
);
2320 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2322 /* This rev is really old, and requires untested workarounds */
2323 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2324 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2325 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2326 hw
->chip_id
, hw
->chip_rev
);
2331 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2332 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2333 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2337 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2338 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2340 /* clear PCI errors, if any */
2341 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2343 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2344 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2347 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2349 /* clear any PEX errors */
2350 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2351 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2354 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2355 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2358 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2359 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2360 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2364 sky2_set_power_state(hw
, PCI_D0
);
2366 for (i
= 0; i
< hw
->ports
; i
++) {
2367 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2368 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2371 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2373 /* Clear I2C IRQ noise */
2374 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2376 /* turn off hardware timer (unused) */
2377 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2378 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2380 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2382 /* Turn off descriptor polling */
2383 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2385 /* Turn off receive timestamp */
2386 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2387 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2389 /* enable the Tx Arbiters */
2390 for (i
= 0; i
< hw
->ports
; i
++)
2391 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2393 /* Initialize ram interface */
2394 for (i
= 0; i
< hw
->ports
; i
++) {
2395 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2397 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2398 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2399 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2400 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2401 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2402 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2403 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2404 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2405 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2406 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2407 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2408 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2411 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2413 for (i
= 0; i
< hw
->ports
; i
++)
2414 sky2_phy_reset(hw
, i
);
2416 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2419 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2420 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2422 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2423 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2425 /* Set the list last index */
2426 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2428 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2429 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2431 /* set Status-FIFO ISR watermark */
2432 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2433 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2435 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2437 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2438 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2439 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2441 /* enable status unit */
2442 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2444 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2445 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2446 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2451 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2455 modes
= SUPPORTED_10baseT_Half
2456 | SUPPORTED_10baseT_Full
2457 | SUPPORTED_100baseT_Half
2458 | SUPPORTED_100baseT_Full
2459 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2461 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2462 modes
|= SUPPORTED_1000baseT_Half
2463 | SUPPORTED_1000baseT_Full
;
2465 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2466 | SUPPORTED_Autoneg
;
2470 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2472 struct sky2_port
*sky2
= netdev_priv(dev
);
2473 struct sky2_hw
*hw
= sky2
->hw
;
2475 ecmd
->transceiver
= XCVR_INTERNAL
;
2476 ecmd
->supported
= sky2_supported_modes(hw
);
2477 ecmd
->phy_address
= PHY_ADDR_MARV
;
2479 ecmd
->supported
= SUPPORTED_10baseT_Half
2480 | SUPPORTED_10baseT_Full
2481 | SUPPORTED_100baseT_Half
2482 | SUPPORTED_100baseT_Full
2483 | SUPPORTED_1000baseT_Half
2484 | SUPPORTED_1000baseT_Full
2485 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2486 ecmd
->port
= PORT_TP
;
2488 ecmd
->port
= PORT_FIBRE
;
2490 ecmd
->advertising
= sky2
->advertising
;
2491 ecmd
->autoneg
= sky2
->autoneg
;
2492 ecmd
->speed
= sky2
->speed
;
2493 ecmd
->duplex
= sky2
->duplex
;
2497 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2499 struct sky2_port
*sky2
= netdev_priv(dev
);
2500 const struct sky2_hw
*hw
= sky2
->hw
;
2501 u32 supported
= sky2_supported_modes(hw
);
2503 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2504 ecmd
->advertising
= supported
;
2510 switch (ecmd
->speed
) {
2512 if (ecmd
->duplex
== DUPLEX_FULL
)
2513 setting
= SUPPORTED_1000baseT_Full
;
2514 else if (ecmd
->duplex
== DUPLEX_HALF
)
2515 setting
= SUPPORTED_1000baseT_Half
;
2520 if (ecmd
->duplex
== DUPLEX_FULL
)
2521 setting
= SUPPORTED_100baseT_Full
;
2522 else if (ecmd
->duplex
== DUPLEX_HALF
)
2523 setting
= SUPPORTED_100baseT_Half
;
2529 if (ecmd
->duplex
== DUPLEX_FULL
)
2530 setting
= SUPPORTED_10baseT_Full
;
2531 else if (ecmd
->duplex
== DUPLEX_HALF
)
2532 setting
= SUPPORTED_10baseT_Half
;
2540 if ((setting
& supported
) == 0)
2543 sky2
->speed
= ecmd
->speed
;
2544 sky2
->duplex
= ecmd
->duplex
;
2547 sky2
->autoneg
= ecmd
->autoneg
;
2548 sky2
->advertising
= ecmd
->advertising
;
2550 if (netif_running(dev
))
2551 sky2_phy_reinit(sky2
);
2556 static void sky2_get_drvinfo(struct net_device
*dev
,
2557 struct ethtool_drvinfo
*info
)
2559 struct sky2_port
*sky2
= netdev_priv(dev
);
2561 strcpy(info
->driver
, DRV_NAME
);
2562 strcpy(info
->version
, DRV_VERSION
);
2563 strcpy(info
->fw_version
, "N/A");
2564 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2567 static const struct sky2_stat
{
2568 char name
[ETH_GSTRING_LEN
];
2571 { "tx_bytes", GM_TXO_OK_HI
},
2572 { "rx_bytes", GM_RXO_OK_HI
},
2573 { "tx_broadcast", GM_TXF_BC_OK
},
2574 { "rx_broadcast", GM_RXF_BC_OK
},
2575 { "tx_multicast", GM_TXF_MC_OK
},
2576 { "rx_multicast", GM_RXF_MC_OK
},
2577 { "tx_unicast", GM_TXF_UC_OK
},
2578 { "rx_unicast", GM_RXF_UC_OK
},
2579 { "tx_mac_pause", GM_TXF_MPAUSE
},
2580 { "rx_mac_pause", GM_RXF_MPAUSE
},
2581 { "collisions", GM_TXF_COL
},
2582 { "late_collision",GM_TXF_LAT_COL
},
2583 { "aborted", GM_TXF_ABO_COL
},
2584 { "single_collisions", GM_TXF_SNG_COL
},
2585 { "multi_collisions", GM_TXF_MUL_COL
},
2587 { "rx_short", GM_RXF_SHT
},
2588 { "rx_runt", GM_RXE_FRAG
},
2589 { "rx_64_byte_packets", GM_RXF_64B
},
2590 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2591 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2592 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2593 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2594 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2595 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2596 { "rx_too_long", GM_RXF_LNG_ERR
},
2597 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2598 { "rx_jabber", GM_RXF_JAB_PKT
},
2599 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2601 { "tx_64_byte_packets", GM_TXF_64B
},
2602 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2603 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2604 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2605 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2606 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2607 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2608 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2611 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2613 struct sky2_port
*sky2
= netdev_priv(dev
);
2615 return sky2
->rx_csum
;
2618 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2620 struct sky2_port
*sky2
= netdev_priv(dev
);
2622 sky2
->rx_csum
= data
;
2624 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2625 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2630 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2632 struct sky2_port
*sky2
= netdev_priv(netdev
);
2633 return sky2
->msg_enable
;
2636 static int sky2_nway_reset(struct net_device
*dev
)
2638 struct sky2_port
*sky2
= netdev_priv(dev
);
2640 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2643 sky2_phy_reinit(sky2
);
2648 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2650 struct sky2_hw
*hw
= sky2
->hw
;
2651 unsigned port
= sky2
->port
;
2654 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2655 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2656 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2657 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2659 for (i
= 2; i
< count
; i
++)
2660 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2663 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2665 struct sky2_port
*sky2
= netdev_priv(netdev
);
2666 sky2
->msg_enable
= value
;
2669 static int sky2_get_stats_count(struct net_device
*dev
)
2671 return ARRAY_SIZE(sky2_stats
);
2674 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2675 struct ethtool_stats
*stats
, u64
* data
)
2677 struct sky2_port
*sky2
= netdev_priv(dev
);
2679 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2682 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2686 switch (stringset
) {
2688 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2689 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2690 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2695 /* Use hardware MIB variables for critical path statistics and
2696 * transmit feedback not reported at interrupt.
2697 * Other errors are accounted for in interrupt handler.
2699 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2701 struct sky2_port
*sky2
= netdev_priv(dev
);
2704 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2706 sky2
->net_stats
.tx_bytes
= data
[0];
2707 sky2
->net_stats
.rx_bytes
= data
[1];
2708 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2709 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2710 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2711 sky2
->net_stats
.collisions
= data
[10];
2712 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2714 return &sky2
->net_stats
;
2717 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2719 struct sky2_port
*sky2
= netdev_priv(dev
);
2720 struct sky2_hw
*hw
= sky2
->hw
;
2721 unsigned port
= sky2
->port
;
2722 const struct sockaddr
*addr
= p
;
2724 if (!is_valid_ether_addr(addr
->sa_data
))
2725 return -EADDRNOTAVAIL
;
2727 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2728 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2729 dev
->dev_addr
, ETH_ALEN
);
2730 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2731 dev
->dev_addr
, ETH_ALEN
);
2733 /* virtual address for data */
2734 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2736 /* physical address: used for pause frames */
2737 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2742 static void sky2_set_multicast(struct net_device
*dev
)
2744 struct sky2_port
*sky2
= netdev_priv(dev
);
2745 struct sky2_hw
*hw
= sky2
->hw
;
2746 unsigned port
= sky2
->port
;
2747 struct dev_mc_list
*list
= dev
->mc_list
;
2751 memset(filter
, 0, sizeof(filter
));
2753 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2754 reg
|= GM_RXCR_UCF_ENA
;
2756 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2757 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2758 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2759 memset(filter
, 0xff, sizeof(filter
));
2760 else if (dev
->mc_count
== 0) /* no multicast */
2761 reg
&= ~GM_RXCR_MCF_ENA
;
2764 reg
|= GM_RXCR_MCF_ENA
;
2766 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2767 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2768 filter
[bit
/ 8] |= 1 << (bit
% 8);
2772 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2773 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2774 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2775 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2776 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2777 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2778 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2779 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2781 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2784 /* Can have one global because blinking is controlled by
2785 * ethtool and that is always under RTNL mutex
2787 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2791 switch (hw
->chip_id
) {
2792 case CHIP_ID_YUKON_XL
:
2793 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2794 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2795 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2796 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2797 PHY_M_LEDC_INIT_CTRL(7) |
2798 PHY_M_LEDC_STA1_CTRL(7) |
2799 PHY_M_LEDC_STA0_CTRL(7))
2802 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2806 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2807 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2808 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2809 PHY_M_LED_MO_10(MO_LED_ON
) |
2810 PHY_M_LED_MO_100(MO_LED_ON
) |
2811 PHY_M_LED_MO_1000(MO_LED_ON
) |
2812 PHY_M_LED_MO_RX(MO_LED_ON
)
2813 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2814 PHY_M_LED_MO_10(MO_LED_OFF
) |
2815 PHY_M_LED_MO_100(MO_LED_OFF
) |
2816 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2817 PHY_M_LED_MO_RX(MO_LED_OFF
));
2822 /* blink LED's for finding board */
2823 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2825 struct sky2_port
*sky2
= netdev_priv(dev
);
2826 struct sky2_hw
*hw
= sky2
->hw
;
2827 unsigned port
= sky2
->port
;
2828 u16 ledctrl
, ledover
= 0;
2833 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2834 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2838 /* save initial values */
2839 spin_lock_bh(&sky2
->phy_lock
);
2840 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2841 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2842 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2843 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2844 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2846 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2847 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2851 while (!interrupted
&& ms
> 0) {
2852 sky2_led(hw
, port
, onoff
);
2855 spin_unlock_bh(&sky2
->phy_lock
);
2856 interrupted
= msleep_interruptible(250);
2857 spin_lock_bh(&sky2
->phy_lock
);
2862 /* resume regularly scheduled programming */
2863 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2864 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2865 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2866 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2867 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2869 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2870 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2872 spin_unlock_bh(&sky2
->phy_lock
);
2877 static void sky2_get_pauseparam(struct net_device
*dev
,
2878 struct ethtool_pauseparam
*ecmd
)
2880 struct sky2_port
*sky2
= netdev_priv(dev
);
2882 ecmd
->tx_pause
= sky2
->tx_pause
;
2883 ecmd
->rx_pause
= sky2
->rx_pause
;
2884 ecmd
->autoneg
= sky2
->autoneg
;
2887 static int sky2_set_pauseparam(struct net_device
*dev
,
2888 struct ethtool_pauseparam
*ecmd
)
2890 struct sky2_port
*sky2
= netdev_priv(dev
);
2893 sky2
->autoneg
= ecmd
->autoneg
;
2894 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2895 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2897 sky2_phy_reinit(sky2
);
2902 static int sky2_get_coalesce(struct net_device
*dev
,
2903 struct ethtool_coalesce
*ecmd
)
2905 struct sky2_port
*sky2
= netdev_priv(dev
);
2906 struct sky2_hw
*hw
= sky2
->hw
;
2908 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2909 ecmd
->tx_coalesce_usecs
= 0;
2911 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2912 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2914 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2916 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2917 ecmd
->rx_coalesce_usecs
= 0;
2919 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2920 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2922 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2924 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2925 ecmd
->rx_coalesce_usecs_irq
= 0;
2927 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2928 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2931 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2936 /* Note: this affect both ports */
2937 static int sky2_set_coalesce(struct net_device
*dev
,
2938 struct ethtool_coalesce
*ecmd
)
2940 struct sky2_port
*sky2
= netdev_priv(dev
);
2941 struct sky2_hw
*hw
= sky2
->hw
;
2942 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
2944 if (ecmd
->tx_coalesce_usecs
> tmax
||
2945 ecmd
->rx_coalesce_usecs
> tmax
||
2946 ecmd
->rx_coalesce_usecs_irq
> tmax
)
2949 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2951 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2953 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2956 if (ecmd
->tx_coalesce_usecs
== 0)
2957 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2959 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2960 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2961 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2963 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2965 if (ecmd
->rx_coalesce_usecs
== 0)
2966 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2968 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2969 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2970 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2972 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2974 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2975 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2977 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2978 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2979 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2981 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2985 static void sky2_get_ringparam(struct net_device
*dev
,
2986 struct ethtool_ringparam
*ering
)
2988 struct sky2_port
*sky2
= netdev_priv(dev
);
2990 ering
->rx_max_pending
= RX_MAX_PENDING
;
2991 ering
->rx_mini_max_pending
= 0;
2992 ering
->rx_jumbo_max_pending
= 0;
2993 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2995 ering
->rx_pending
= sky2
->rx_pending
;
2996 ering
->rx_mini_pending
= 0;
2997 ering
->rx_jumbo_pending
= 0;
2998 ering
->tx_pending
= sky2
->tx_pending
;
3001 static int sky2_set_ringparam(struct net_device
*dev
,
3002 struct ethtool_ringparam
*ering
)
3004 struct sky2_port
*sky2
= netdev_priv(dev
);
3007 if (ering
->rx_pending
> RX_MAX_PENDING
||
3008 ering
->rx_pending
< 8 ||
3009 ering
->tx_pending
< MAX_SKB_TX_LE
||
3010 ering
->tx_pending
> TX_RING_SIZE
- 1)
3013 if (netif_running(dev
))
3016 sky2
->rx_pending
= ering
->rx_pending
;
3017 sky2
->tx_pending
= ering
->tx_pending
;
3019 if (netif_running(dev
)) {
3024 sky2_set_multicast(dev
);
3030 static int sky2_get_regs_len(struct net_device
*dev
)
3036 * Returns copy of control register region
3037 * Note: access to the RAM address register set will cause timeouts.
3039 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3042 const struct sky2_port
*sky2
= netdev_priv(dev
);
3043 const void __iomem
*io
= sky2
->hw
->regs
;
3045 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3047 memset(p
, 0, regs
->len
);
3049 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3051 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3053 regs
->len
- B3_RI_WTO_R1
);
3056 static struct ethtool_ops sky2_ethtool_ops
= {
3057 .get_settings
= sky2_get_settings
,
3058 .set_settings
= sky2_set_settings
,
3059 .get_drvinfo
= sky2_get_drvinfo
,
3060 .get_msglevel
= sky2_get_msglevel
,
3061 .set_msglevel
= sky2_set_msglevel
,
3062 .nway_reset
= sky2_nway_reset
,
3063 .get_regs_len
= sky2_get_regs_len
,
3064 .get_regs
= sky2_get_regs
,
3065 .get_link
= ethtool_op_get_link
,
3066 .get_sg
= ethtool_op_get_sg
,
3067 .set_sg
= ethtool_op_set_sg
,
3068 .get_tx_csum
= ethtool_op_get_tx_csum
,
3069 .set_tx_csum
= ethtool_op_set_tx_csum
,
3070 .get_tso
= ethtool_op_get_tso
,
3071 .set_tso
= ethtool_op_set_tso
,
3072 .get_rx_csum
= sky2_get_rx_csum
,
3073 .set_rx_csum
= sky2_set_rx_csum
,
3074 .get_strings
= sky2_get_strings
,
3075 .get_coalesce
= sky2_get_coalesce
,
3076 .set_coalesce
= sky2_set_coalesce
,
3077 .get_ringparam
= sky2_get_ringparam
,
3078 .set_ringparam
= sky2_set_ringparam
,
3079 .get_pauseparam
= sky2_get_pauseparam
,
3080 .set_pauseparam
= sky2_set_pauseparam
,
3081 .phys_id
= sky2_phys_id
,
3082 .get_stats_count
= sky2_get_stats_count
,
3083 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3084 .get_perm_addr
= ethtool_op_get_perm_addr
,
3087 /* Initialize network device */
3088 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3089 unsigned port
, int highmem
)
3091 struct sky2_port
*sky2
;
3092 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3095 printk(KERN_ERR
"sky2 etherdev alloc failed");
3099 SET_MODULE_OWNER(dev
);
3100 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3101 dev
->irq
= hw
->pdev
->irq
;
3102 dev
->open
= sky2_up
;
3103 dev
->stop
= sky2_down
;
3104 dev
->do_ioctl
= sky2_ioctl
;
3105 dev
->hard_start_xmit
= sky2_xmit_frame
;
3106 dev
->get_stats
= sky2_get_stats
;
3107 dev
->set_multicast_list
= sky2_set_multicast
;
3108 dev
->set_mac_address
= sky2_set_mac_address
;
3109 dev
->change_mtu
= sky2_change_mtu
;
3110 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3111 dev
->tx_timeout
= sky2_tx_timeout
;
3112 dev
->watchdog_timeo
= TX_WATCHDOG
;
3114 dev
->poll
= sky2_poll
;
3115 dev
->weight
= NAPI_WEIGHT
;
3116 #ifdef CONFIG_NET_POLL_CONTROLLER
3117 dev
->poll_controller
= sky2_netpoll
;
3120 sky2
= netdev_priv(dev
);
3123 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3125 spin_lock_init(&sky2
->tx_lock
);
3126 /* Auto speed and flow control */
3127 sky2
->autoneg
= AUTONEG_ENABLE
;
3132 sky2
->advertising
= sky2_supported_modes(hw
);
3135 spin_lock_init(&sky2
->phy_lock
);
3136 sky2
->tx_pending
= TX_DEF_PENDING
;
3137 sky2
->rx_pending
= RX_DEF_PENDING
;
3138 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3140 hw
->dev
[port
] = dev
;
3144 dev
->features
|= NETIF_F_LLTX
;
3145 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3146 dev
->features
|= NETIF_F_TSO
;
3148 dev
->features
|= NETIF_F_HIGHDMA
;
3149 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3151 #ifdef SKY2_VLAN_TAG_USED
3152 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3153 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3154 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3157 /* read the mac address */
3158 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3159 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3161 /* device is off until link detection */
3162 netif_carrier_off(dev
);
3163 netif_stop_queue(dev
);
3168 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3170 const struct sky2_port
*sky2
= netdev_priv(dev
);
3172 if (netif_msg_probe(sky2
))
3173 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3175 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3176 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3179 /* Handle software interrupt used during MSI test */
3180 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3181 struct pt_regs
*regs
)
3183 struct sky2_hw
*hw
= dev_id
;
3184 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3189 if (status
& Y2_IS_IRQ_SW
) {
3190 hw
->msi_detected
= 1;
3191 wake_up(&hw
->msi_wait
);
3192 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3194 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3199 /* Test interrupt path by forcing a a software IRQ */
3200 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3202 struct pci_dev
*pdev
= hw
->pdev
;
3205 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3207 err
= request_irq(pdev
->irq
, sky2_test_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3209 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3210 pci_name(pdev
), pdev
->irq
);
3214 init_waitqueue_head (&hw
->msi_wait
);
3216 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3219 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3221 if (!hw
->msi_detected
) {
3222 /* MSI test failed, go back to INTx mode */
3223 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3224 "switching to INTx mode. Please report this failure to "
3225 "the PCI maintainer and include system chipset information.\n",
3229 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3232 sky2_write32(hw
, B0_IMSK
, 0);
3234 free_irq(pdev
->irq
, hw
);
3239 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3240 const struct pci_device_id
*ent
)
3242 struct net_device
*dev
, *dev1
= NULL
;
3244 int err
, pm_cap
, using_dac
= 0;
3246 err
= pci_enable_device(pdev
);
3248 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3253 err
= pci_request_regions(pdev
, DRV_NAME
);
3255 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3260 pci_set_master(pdev
);
3262 /* Find power-management capability. */
3263 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3265 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3268 goto err_out_free_regions
;
3271 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3272 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3274 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3276 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3277 "for consistent allocations\n", pci_name(pdev
));
3278 goto err_out_free_regions
;
3282 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3284 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3286 goto err_out_free_regions
;
3291 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3293 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3295 goto err_out_free_regions
;
3300 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3302 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3304 goto err_out_free_hw
;
3306 hw
->pm_cap
= pm_cap
;
3309 /* byte swap descriptors in hardware */
3313 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3314 reg
|= PCI_REV_DESC
;
3315 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3319 /* ring for status responses */
3320 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3323 goto err_out_iounmap
;
3325 err
= sky2_reset(hw
);
3327 goto err_out_iounmap
;
3329 printk(KERN_INFO PFX
"v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3330 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3331 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3332 hw
->chip_id
, hw
->chip_rev
);
3334 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3336 goto err_out_free_pci
;
3338 err
= register_netdev(dev
);
3340 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3342 goto err_out_free_netdev
;
3345 sky2_show_addr(dev
);
3347 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3348 if (register_netdev(dev1
) == 0)
3349 sky2_show_addr(dev1
);
3351 /* Failure to register second port need not be fatal */
3352 printk(KERN_WARNING PFX
3353 "register of second port failed\n");
3359 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3360 err
= sky2_test_msi(hw
);
3361 if (err
== -EOPNOTSUPP
)
3362 pci_disable_msi(pdev
);
3364 goto err_out_unregister
;
3367 err
= request_irq(pdev
->irq
, sky2_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3369 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3370 pci_name(pdev
), pdev
->irq
);
3371 goto err_out_unregister
;
3374 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3376 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3377 sky2_idle_start(hw
);
3379 pci_set_drvdata(pdev
, hw
);
3384 pci_disable_msi(pdev
);
3386 unregister_netdev(dev1
);
3389 unregister_netdev(dev
);
3390 err_out_free_netdev
:
3393 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3394 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3399 err_out_free_regions
:
3400 pci_release_regions(pdev
);
3401 pci_disable_device(pdev
);
3406 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3408 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3409 struct net_device
*dev0
, *dev1
;
3414 del_timer_sync(&hw
->idle_timer
);
3416 sky2_write32(hw
, B0_IMSK
, 0);
3417 synchronize_irq(hw
->pdev
->irq
);
3422 unregister_netdev(dev1
);
3423 unregister_netdev(dev0
);
3425 sky2_set_power_state(hw
, PCI_D3hot
);
3426 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3427 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3428 sky2_read8(hw
, B0_CTST
);
3430 free_irq(pdev
->irq
, hw
);
3431 pci_disable_msi(pdev
);
3432 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3433 pci_release_regions(pdev
);
3434 pci_disable_device(pdev
);
3442 pci_set_drvdata(pdev
, NULL
);
3446 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3448 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3450 pci_power_t pstate
= pci_choose_state(pdev
, state
);
3452 if (!(pstate
== PCI_D3hot
|| pstate
== PCI_D3cold
))
3455 del_timer_sync(&hw
->idle_timer
);
3456 netif_poll_disable(hw
->dev
[0]);
3458 for (i
= 0; i
< hw
->ports
; i
++) {
3459 struct net_device
*dev
= hw
->dev
[i
];
3461 if (netif_running(dev
)) {
3463 netif_device_detach(dev
);
3467 sky2_write32(hw
, B0_IMSK
, 0);
3468 pci_save_state(pdev
);
3469 sky2_set_power_state(hw
, pstate
);
3473 static int sky2_resume(struct pci_dev
*pdev
)
3475 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3478 pci_restore_state(pdev
);
3479 pci_enable_wake(pdev
, PCI_D0
, 0);
3480 sky2_set_power_state(hw
, PCI_D0
);
3482 err
= sky2_reset(hw
);
3486 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3488 for (i
= 0; i
< hw
->ports
; i
++) {
3489 struct net_device
*dev
= hw
->dev
[i
];
3490 if (netif_running(dev
)) {
3491 netif_device_attach(dev
);
3495 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3503 netif_poll_enable(hw
->dev
[0]);
3504 sky2_idle_start(hw
);
3510 static struct pci_driver sky2_driver
= {
3512 .id_table
= sky2_id_table
,
3513 .probe
= sky2_probe
,
3514 .remove
= __devexit_p(sky2_remove
),
3516 .suspend
= sky2_suspend
,
3517 .resume
= sky2_resume
,
3521 static int __init
sky2_init_module(void)
3523 return pci_register_driver(&sky2_driver
);
3526 static void __exit
sky2_cleanup_module(void)
3528 pci_unregister_driver(&sky2_driver
);
3531 module_init(sky2_init_module
);
3532 module_exit(sky2_cleanup_module
);
3534 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3535 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3536 MODULE_LICENSE("GPL");
3537 MODULE_VERSION(DRV_VERSION
);