2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.4"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
63 #define RX_LE_SIZE 512
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg
=
85 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
86 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
89 static int debug
= -1; /* defaults above */
90 module_param(debug
, int, 0);
91 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly
= 256;
94 module_param(copybreak
, int, 0);
95 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
97 static int disable_msi
= 0;
98 module_param(disable_msi
, int, 0);
99 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
101 static int idle_timeout
= 100;
102 module_param(idle_timeout
, int, 0);
103 MODULE_PARM_DESC(idle_timeout
, "Idle timeout workaround for lost interrupts (ms)");
105 static const struct pci_device_id sky2_id_table
[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
127 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
129 /* Avoid conditionals by using array */
130 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
131 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
132 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
134 /* This driver supports yukon2 chipset only */
135 static const char *yukon2_name
[] = {
137 "EC Ultra", /* 0xb4 */
138 "UNKNOWN", /* 0xb5 */
143 /* Access to external PHY */
144 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
148 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
149 gma_write16(hw
, port
, GM_SMI_CTRL
,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
152 for (i
= 0; i
< PHY_RETRIES
; i
++) {
153 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
158 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
162 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
166 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
167 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
169 for (i
= 0; i
< PHY_RETRIES
; i
++) {
170 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
171 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
181 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
185 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
186 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
190 static void sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
196 pr_debug("sky2_set_power_state %d\n", state
);
197 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
199 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
200 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
201 (power_control
& PCI_PM_CAP_PME_D3cold
);
203 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
205 power_control
|= PCI_PM_CTRL_PME_STATUS
;
206 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw
, B0_POWER_CTRL
,
212 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
214 /* disable Core Clock Division, */
215 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
217 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
218 /* enable bits are inverted */
219 sky2_write8(hw
, B2_Y2_CLK_GATE
,
220 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
221 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
222 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
224 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
226 /* Turn off phy power saving */
227 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
228 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
230 /* looks like this XL is back asswards .. */
231 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
232 reg1
|= PCI_Y2_PHY1_COMA
;
234 reg1
|= PCI_Y2_PHY2_COMA
;
237 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
238 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
239 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
240 reg1
&= P_ASPM_CONTROL_MSK
;
241 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
242 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
245 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
252 /* Turn on phy power saving */
253 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
254 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
255 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
257 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
258 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
261 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
262 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
264 /* enable bits are inverted */
265 sky2_write8(hw
, B2_Y2_CLK_GATE
,
266 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
267 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
268 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
270 /* switch power to VAUX */
271 if (vaux
&& state
!= PCI_D3cold
)
272 sky2_write8(hw
, B0_POWER_CTRL
,
273 (PC_VAUX_ENA
| PC_VCC_ENA
|
274 PC_VAUX_ON
| PC_VCC_OFF
));
277 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
280 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
281 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
284 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
288 /* disable all GMAC IRQ's */
289 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
290 /* disable PHY IRQs */
291 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
293 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
294 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
295 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
296 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
298 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
299 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
300 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
303 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
305 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
306 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
308 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
309 !(hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
310 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
312 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
314 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
316 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
317 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
319 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
321 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
324 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
326 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
327 /* enable automatic crossover */
328 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
330 /* disable energy detect */
331 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
333 /* enable automatic crossover */
334 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
336 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
337 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
338 ctrl
&= ~PHY_M_PC_DSC_MSK
;
339 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
342 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
344 /* workaround for deviation #4.88 (CRC errors) */
345 /* disable Automatic Crossover */
347 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
348 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
350 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
351 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
352 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
353 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
354 ctrl
&= ~PHY_M_MAC_MD_MSK
;
355 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
356 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
363 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
364 if (sky2
->autoneg
== AUTONEG_DISABLE
)
369 ctrl
|= PHY_CT_RESET
;
370 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
376 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
378 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
379 ct1000
|= PHY_M_1000C_AFD
;
380 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
381 ct1000
|= PHY_M_1000C_AHD
;
382 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
383 adv
|= PHY_M_AN_100_FD
;
384 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
385 adv
|= PHY_M_AN_100_HD
;
386 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
387 adv
|= PHY_M_AN_10_FD
;
388 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
389 adv
|= PHY_M_AN_10_HD
;
390 } else /* special defines for FIBER (88E1011S only) */
391 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
393 /* Set Flow-control capabilities */
394 if (sky2
->tx_pause
&& sky2
->rx_pause
)
395 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
396 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
397 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
398 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
399 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
401 /* Restart Auto-negotiation */
402 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
404 /* forced speed/duplex settings */
405 ct1000
= PHY_M_1000C_MSE
;
407 if (sky2
->duplex
== DUPLEX_FULL
)
408 ctrl
|= PHY_CT_DUP_MD
;
410 switch (sky2
->speed
) {
412 ctrl
|= PHY_CT_SP1000
;
415 ctrl
|= PHY_CT_SP100
;
419 ctrl
|= PHY_CT_RESET
;
422 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
423 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
425 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
426 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
428 /* Setup Phy LED's */
429 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
432 switch (hw
->chip_id
) {
433 case CHIP_ID_YUKON_FE
:
434 /* on 88E3082 these bits are at 11..9 (shifted left) */
435 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
437 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
439 /* delete ACT LED control bits */
440 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
441 /* change ACT LED control to blink mode */
442 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
443 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
446 case CHIP_ID_YUKON_XL
:
447 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
449 /* select page 3 to access LED control register */
450 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
452 /* set LED Function Control register */
453 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
454 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
455 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
456 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
457 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
459 /* set Polarity Control register */
460 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
461 (PHY_M_POLC_LS1_P_MIX(4) |
462 PHY_M_POLC_IS0_P_MIX(4) |
463 PHY_M_POLC_LOS_CTRL(2) |
464 PHY_M_POLC_INIT_CTRL(2) |
465 PHY_M_POLC_STA1_CTRL(2) |
466 PHY_M_POLC_STA0_CTRL(2)));
468 /* restore page register */
469 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
471 case CHIP_ID_YUKON_EC_U
:
472 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
474 /* select page 3 to access LED control register */
475 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
477 /* set LED Function Control register */
478 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
479 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
480 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
481 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
482 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
484 /* set Blink Rate in LED Timer Control Register */
485 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
486 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
487 /* restore page register */
488 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
492 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
493 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
494 /* turn off the Rx LED (LED_RX) */
495 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
498 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
499 /* apply fixes in PHY AFE */
500 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
501 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
503 /* increase differential signal amplitude in 10BASE-T */
504 gm_phy_write(hw
, port
, 0x18, 0xaa99);
505 gm_phy_write(hw
, port
, 0x17, 0x2011);
507 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
508 gm_phy_write(hw
, port
, 0x18, 0xa204);
509 gm_phy_write(hw
, port
, 0x17, 0x2002);
511 /* set page register to 0 */
512 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
514 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
516 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
517 /* turn on 100 Mbps LED (LED_LINK100) */
518 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
522 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
525 /* Enable phy interrupt on auto-negotiation complete (or link up) */
526 if (sky2
->autoneg
== AUTONEG_ENABLE
)
527 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
529 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
532 /* Force a renegotiation */
533 static void sky2_phy_reinit(struct sky2_port
*sky2
)
535 spin_lock_bh(&sky2
->phy_lock
);
536 sky2_phy_init(sky2
->hw
, sky2
->port
);
537 spin_unlock_bh(&sky2
->phy_lock
);
540 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
542 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
545 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
547 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
548 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
550 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
552 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
553 /* WA DEV_472 -- looks like crossed wires on port 2 */
554 /* clear GMAC 1 Control reset */
555 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
557 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
558 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
559 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
560 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
561 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
564 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
565 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
566 reg
|= GM_GPCR_AU_ALL_DIS
;
567 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
568 gma_read16(hw
, port
, GM_GP_CTRL
);
570 switch (sky2
->speed
) {
572 reg
&= ~GM_GPCR_SPEED_100
;
573 reg
|= GM_GPCR_SPEED_1000
;
576 reg
&= ~GM_GPCR_SPEED_1000
;
577 reg
|= GM_GPCR_SPEED_100
;
580 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
584 if (sky2
->duplex
== DUPLEX_FULL
)
585 reg
|= GM_GPCR_DUP_FULL
;
587 /* turn off pause in 10/100mbps half duplex */
588 else if (sky2
->speed
!= SPEED_1000
&&
589 hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
590 sky2
->tx_pause
= sky2
->rx_pause
= 0;
592 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
594 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
595 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
597 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
598 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
599 /* disable Rx flow-control */
600 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
603 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
605 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
607 spin_lock_bh(&sky2
->phy_lock
);
608 sky2_phy_init(hw
, port
);
609 spin_unlock_bh(&sky2
->phy_lock
);
612 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
613 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
615 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
616 gma_read16(hw
, port
, i
);
617 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
619 /* transmit control */
620 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
622 /* receive control reg: unicast + multicast + no FCS */
623 gma_write16(hw
, port
, GM_RX_CTRL
,
624 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
626 /* transmit flow control */
627 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
629 /* transmit parameter */
630 gma_write16(hw
, port
, GM_TX_PARAM
,
631 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
632 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
633 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
634 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
636 /* serial mode register */
637 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
638 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
640 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
641 reg
|= GM_SMOD_JUMBO_ENA
;
643 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
645 /* virtual address for data */
646 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
648 /* physical address: used for pause frames */
649 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
651 /* ignore counter overflows */
652 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
653 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
654 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
656 /* Configure Rx MAC FIFO */
657 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
658 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
659 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
661 /* Flush Rx MAC FIFO on any flow control or error */
662 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
664 /* Set threshold to 0xa (64 bytes)
665 * ASF disabled so no need to do WA dev #4.30
667 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
669 /* Configure Tx MAC FIFO */
670 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
671 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
673 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
674 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
675 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
676 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
677 /* set Tx GMAC FIFO Almost Empty Threshold */
678 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
679 /* Disable Store & Forward mode for TX */
680 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
686 /* Assign Ram Buffer allocation.
687 * start and end are in units of 4k bytes
688 * ram registers are in units of 64bit words
690 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
694 start
= startk
* 4096/8;
695 end
= (endk
* 4096/8) - 1;
697 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
698 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
699 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
700 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
701 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
703 if (q
== Q_R1
|| q
== Q_R2
) {
704 u32 space
= (endk
- startk
) * 4096/8;
705 u32 tp
= space
- space
/4;
707 /* On receive queue's set the thresholds
708 * give receiver priority when > 3/4 full
709 * send pause when down to 2K
711 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
712 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
715 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
716 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
718 /* Enable store & forward on Tx queue's because
719 * Tx FIFO is only 1K on Yukon
721 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
724 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
725 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
728 /* Setup Bus Memory Interface */
729 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
731 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
732 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
733 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
734 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
737 /* Setup prefetch unit registers. This is the interface between
738 * hardware and driver list elements
740 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
743 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
744 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
745 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
746 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
747 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
748 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
750 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
753 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
755 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
757 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
761 /* Update chip's next pointer */
762 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
765 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
770 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
772 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
773 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
777 /* Return high part of DMA address (could be 32 or 64 bit) */
778 static inline u32
high32(dma_addr_t a
)
780 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
783 /* Build description to hardware about buffer */
784 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
786 struct sky2_rx_le
*le
;
787 u32 hi
= high32(map
);
788 u16 len
= sky2
->rx_bufsize
;
790 if (sky2
->rx_addr64
!= hi
) {
791 le
= sky2_next_rx(sky2
);
792 le
->addr
= cpu_to_le32(hi
);
794 le
->opcode
= OP_ADDR64
| HW_OWNER
;
795 sky2
->rx_addr64
= high32(map
+ len
);
798 le
= sky2_next_rx(sky2
);
799 le
->addr
= cpu_to_le32((u32
) map
);
800 le
->length
= cpu_to_le16(len
);
802 le
->opcode
= OP_PACKET
| HW_OWNER
;
806 /* Tell chip where to start receive checksum.
807 * Actually has two checksums, but set both same to avoid possible byte
810 static void rx_set_checksum(struct sky2_port
*sky2
)
812 struct sky2_rx_le
*le
;
814 le
= sky2_next_rx(sky2
);
815 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
817 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
819 sky2_write32(sky2
->hw
,
820 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
821 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
826 * The RX Stop command will not work for Yukon-2 if the BMU does not
827 * reach the end of packet and since we can't make sure that we have
828 * incoming data, we must reset the BMU while it is not doing a DMA
829 * transfer. Since it is possible that the RX path is still active,
830 * the RX RAM buffer will be stopped first, so any possible incoming
831 * data will not trigger a DMA. After the RAM buffer is stopped, the
832 * BMU is polled until any DMA in progress is ended and only then it
835 static void sky2_rx_stop(struct sky2_port
*sky2
)
837 struct sky2_hw
*hw
= sky2
->hw
;
838 unsigned rxq
= rxqaddr
[sky2
->port
];
841 /* disable the RAM Buffer receive queue */
842 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
844 for (i
= 0; i
< 0xffff; i
++)
845 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
846 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
849 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
852 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
854 /* reset the Rx prefetch unit */
855 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
858 /* Clean out receive buffer area, assumes receiver hardware stopped */
859 static void sky2_rx_clean(struct sky2_port
*sky2
)
863 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
864 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
865 struct ring_info
*re
= sky2
->rx_ring
+ i
;
868 pci_unmap_single(sky2
->hw
->pdev
,
869 re
->mapaddr
, sky2
->rx_bufsize
,
877 /* Basic MII support */
878 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
880 struct mii_ioctl_data
*data
= if_mii(ifr
);
881 struct sky2_port
*sky2
= netdev_priv(dev
);
882 struct sky2_hw
*hw
= sky2
->hw
;
883 int err
= -EOPNOTSUPP
;
885 if (!netif_running(dev
))
886 return -ENODEV
; /* Phy still in reset */
890 data
->phy_id
= PHY_ADDR_MARV
;
896 spin_lock_bh(&sky2
->phy_lock
);
897 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
898 spin_unlock_bh(&sky2
->phy_lock
);
905 if (!capable(CAP_NET_ADMIN
))
908 spin_lock_bh(&sky2
->phy_lock
);
909 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
911 spin_unlock_bh(&sky2
->phy_lock
);
917 #ifdef SKY2_VLAN_TAG_USED
918 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
920 struct sky2_port
*sky2
= netdev_priv(dev
);
921 struct sky2_hw
*hw
= sky2
->hw
;
922 u16 port
= sky2
->port
;
924 spin_lock_bh(&sky2
->tx_lock
);
926 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
927 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
930 spin_unlock_bh(&sky2
->tx_lock
);
933 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
935 struct sky2_port
*sky2
= netdev_priv(dev
);
936 struct sky2_hw
*hw
= sky2
->hw
;
937 u16 port
= sky2
->port
;
939 spin_lock_bh(&sky2
->tx_lock
);
941 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
942 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
944 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
946 spin_unlock_bh(&sky2
->tx_lock
);
951 * It appears the hardware has a bug in the FIFO logic that
952 * cause it to hang if the FIFO gets overrun and the receive buffer
953 * is not aligned. ALso alloc_skb() won't align properly if slab
954 * debugging is enabled.
956 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
960 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
962 unsigned long p
= (unsigned long) skb
->data
;
963 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
970 * Allocate and setup receiver buffer pool.
971 * In case of 64 bit dma, there are 2X as many list elements
972 * available as ring entries
973 * and need to reserve one list element so we don't wrap around.
975 static int sky2_rx_start(struct sky2_port
*sky2
)
977 struct sky2_hw
*hw
= sky2
->hw
;
978 unsigned rxq
= rxqaddr
[sky2
->port
];
982 sky2
->rx_put
= sky2
->rx_next
= 0;
985 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
986 /* MAC Rx RAM Read is controlled by hardware */
987 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
990 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
992 rx_set_checksum(sky2
);
993 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
994 struct ring_info
*re
= sky2
->rx_ring
+ i
;
996 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
1000 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
1001 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1002 sky2_rx_add(sky2
, re
->mapaddr
);
1007 * The receiver hangs if it receives frames larger than the
1008 * packet buffer. As a workaround, truncate oversize frames, but
1009 * the register is limited to 9 bits, so if you do frames > 2052
1010 * you better get the MTU right!
1012 thresh
= (sky2
->rx_bufsize
- 8) / sizeof(u32
);
1014 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1016 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1017 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1021 /* Tell chip about available buffers */
1022 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1025 sky2_rx_clean(sky2
);
1029 /* Bring up network interface. */
1030 static int sky2_up(struct net_device
*dev
)
1032 struct sky2_port
*sky2
= netdev_priv(dev
);
1033 struct sky2_hw
*hw
= sky2
->hw
;
1034 unsigned port
= sky2
->port
;
1035 u32 ramsize
, rxspace
, imask
;
1036 int cap
, err
= -ENOMEM
;
1037 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1040 * On dual port PCI-X card, there is an problem where status
1041 * can be received out of order due to split transactions
1043 if (otherdev
&& netif_running(otherdev
) &&
1044 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1045 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1048 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1049 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1050 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1056 if (netif_msg_ifup(sky2
))
1057 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1059 /* must be power of 2 */
1060 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1062 sizeof(struct sky2_tx_le
),
1067 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1071 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1073 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1077 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1079 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1084 sky2_mac_init(hw
, port
);
1086 /* Determine available ram buffer space (in 4K blocks).
1087 * Note: not sure about the FE setting below yet
1089 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1092 ramsize
= sky2_read8(hw
, B2_E_0
);
1094 /* Give transmitter one third (rounded up) */
1095 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1097 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1098 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1100 /* Make sure SyncQ is disabled */
1101 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1104 sky2_qset(hw
, txqaddr
[port
]);
1106 /* Set almost empty threshold */
1107 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== 1)
1108 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1110 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1113 err
= sky2_rx_start(sky2
);
1117 /* Enable interrupts from phy/mac for port */
1118 imask
= sky2_read32(hw
, B0_IMSK
);
1119 imask
|= portirq_msk
[port
];
1120 sky2_write32(hw
, B0_IMSK
, imask
);
1126 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1127 sky2
->rx_le
, sky2
->rx_le_map
);
1131 pci_free_consistent(hw
->pdev
,
1132 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1133 sky2
->tx_le
, sky2
->tx_le_map
);
1136 kfree(sky2
->tx_ring
);
1137 kfree(sky2
->rx_ring
);
1139 sky2
->tx_ring
= NULL
;
1140 sky2
->rx_ring
= NULL
;
1144 /* Modular subtraction in ring */
1145 static inline int tx_dist(unsigned tail
, unsigned head
)
1147 return (head
- tail
) & (TX_RING_SIZE
- 1);
1150 /* Number of list elements available for next tx */
1151 static inline int tx_avail(const struct sky2_port
*sky2
)
1153 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1156 /* Estimate of number of transmit list elements required */
1157 static unsigned tx_le_req(const struct sk_buff
*skb
)
1161 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1162 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1164 if (skb_is_gso(skb
))
1167 if (skb
->ip_summed
== CHECKSUM_HW
)
1174 * Put one packet in ring for transmit.
1175 * A single packet can generate multiple list elements, and
1176 * the number of ring elements will probably be less than the number
1177 * of list elements used.
1179 * No BH disabling for tx_lock here (like tg3)
1181 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1183 struct sky2_port
*sky2
= netdev_priv(dev
);
1184 struct sky2_hw
*hw
= sky2
->hw
;
1185 struct sky2_tx_le
*le
= NULL
;
1186 struct tx_ring_info
*re
;
1194 /* No BH disabling for tx_lock here. We are running in BH disabled
1195 * context and TX reclaim runs via poll inside of a software
1196 * interrupt, and no related locks in IRQ processing.
1198 if (!spin_trylock(&sky2
->tx_lock
))
1199 return NETDEV_TX_LOCKED
;
1201 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1202 /* There is a known but harmless race with lockless tx
1203 * and netif_stop_queue.
1205 if (!netif_queue_stopped(dev
)) {
1206 netif_stop_queue(dev
);
1207 if (net_ratelimit())
1208 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1211 spin_unlock(&sky2
->tx_lock
);
1213 return NETDEV_TX_BUSY
;
1216 if (unlikely(netif_msg_tx_queued(sky2
)))
1217 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1218 dev
->name
, sky2
->tx_prod
, skb
->len
);
1220 len
= skb_headlen(skb
);
1221 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1222 addr64
= high32(mapping
);
1224 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1226 /* Send high bits if changed or crosses boundary */
1227 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1228 le
= get_tx_le(sky2
);
1229 le
->tx
.addr
= cpu_to_le32(addr64
);
1231 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1232 sky2
->tx_addr64
= high32(mapping
+ len
);
1235 /* Check for TCP Segmentation Offload */
1236 mss
= skb_shinfo(skb
)->gso_size
;
1238 /* just drop the packet if non-linear expansion fails */
1239 if (skb_header_cloned(skb
) &&
1240 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1245 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1246 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1250 if (mss
!= sky2
->tx_last_mss
) {
1251 le
= get_tx_le(sky2
);
1252 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1253 le
->tx
.tso
.rsvd
= 0;
1254 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1256 sky2
->tx_last_mss
= mss
;
1260 #ifdef SKY2_VLAN_TAG_USED
1261 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1262 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1264 le
= get_tx_le(sky2
);
1266 le
->opcode
= OP_VLAN
|HW_OWNER
;
1269 le
->opcode
|= OP_VLAN
;
1270 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1275 /* Handle TCP checksum offload */
1276 if (skb
->ip_summed
== CHECKSUM_HW
) {
1277 u16 hdr
= skb
->h
.raw
- skb
->data
;
1278 u16 offset
= hdr
+ skb
->csum
;
1280 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1281 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1284 le
= get_tx_le(sky2
);
1285 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1286 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1287 le
->length
= 0; /* initial checksum value */
1288 le
->ctrl
= 1; /* one packet */
1289 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1292 le
= get_tx_le(sky2
);
1293 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1294 le
->length
= cpu_to_le16(len
);
1296 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1298 /* Record the transmit mapping info */
1300 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1302 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1303 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1304 struct tx_ring_info
*fre
;
1306 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1307 frag
->size
, PCI_DMA_TODEVICE
);
1308 addr64
= high32(mapping
);
1309 if (addr64
!= sky2
->tx_addr64
) {
1310 le
= get_tx_le(sky2
);
1311 le
->tx
.addr
= cpu_to_le32(addr64
);
1313 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1314 sky2
->tx_addr64
= addr64
;
1317 le
= get_tx_le(sky2
);
1318 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1319 le
->length
= cpu_to_le16(frag
->size
);
1321 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1324 + RING_NEXT((re
- sky2
->tx_ring
) + i
, TX_RING_SIZE
);
1325 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1328 re
->idx
= sky2
->tx_prod
;
1331 avail
= tx_avail(sky2
);
1332 if (mss
!= 0 || avail
< TX_MIN_PENDING
) {
1333 le
->ctrl
|= FRC_STAT
;
1334 if (avail
<= MAX_SKB_TX_LE
)
1335 netif_stop_queue(dev
);
1338 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1341 spin_unlock(&sky2
->tx_lock
);
1343 dev
->trans_start
= jiffies
;
1344 return NETDEV_TX_OK
;
1348 * Free ring elements from starting at tx_cons until "done"
1350 * NB: the hardware will tell us about partial completion of multi-part
1351 * buffers; these are deferred until completion.
1353 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1355 struct net_device
*dev
= sky2
->netdev
;
1356 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1360 BUG_ON(done
>= TX_RING_SIZE
);
1362 if (unlikely(netif_msg_tx_done(sky2
)))
1363 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1366 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1367 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1368 struct sk_buff
*skb
= re
->skb
;
1371 BUG_ON(nxt
>= TX_RING_SIZE
);
1372 prefetch(sky2
->tx_ring
+ nxt
);
1374 /* Check for partial status */
1375 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1379 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1380 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1382 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1383 struct tx_ring_info
*fre
;
1384 fre
= sky2
->tx_ring
+ RING_NEXT(put
+ i
, TX_RING_SIZE
);
1385 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1386 skb_shinfo(skb
)->frags
[i
].size
,
1393 sky2
->tx_cons
= put
;
1394 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1395 netif_wake_queue(dev
);
1398 /* Cleanup all untransmitted buffers, assume transmitter not running */
1399 static void sky2_tx_clean(struct sky2_port
*sky2
)
1401 spin_lock_bh(&sky2
->tx_lock
);
1402 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1403 spin_unlock_bh(&sky2
->tx_lock
);
1406 /* Network shutdown */
1407 static int sky2_down(struct net_device
*dev
)
1409 struct sky2_port
*sky2
= netdev_priv(dev
);
1410 struct sky2_hw
*hw
= sky2
->hw
;
1411 unsigned port
= sky2
->port
;
1415 /* Never really got started! */
1419 if (netif_msg_ifdown(sky2
))
1420 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1422 /* Stop more packets from being queued */
1423 netif_stop_queue(dev
);
1425 sky2_phy_reset(hw
, port
);
1427 /* Stop transmitter */
1428 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1429 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1431 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1432 RB_RST_SET
| RB_DIS_OP_MD
);
1434 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1435 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1436 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1438 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1440 /* Workaround shared GMAC reset */
1441 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1442 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1443 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1445 /* Disable Force Sync bit and Enable Alloc bit */
1446 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1447 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1449 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1450 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1451 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1453 /* Reset the PCI FIFO of the async Tx queue */
1454 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1455 BMU_RST_SET
| BMU_FIFO_RST
);
1457 /* Reset the Tx prefetch units */
1458 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1461 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1465 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1466 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1468 /* Disable port IRQ */
1469 imask
= sky2_read32(hw
, B0_IMSK
);
1470 imask
&= ~portirq_msk
[port
];
1471 sky2_write32(hw
, B0_IMSK
, imask
);
1473 /* turn off LED's */
1474 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1476 synchronize_irq(hw
->pdev
->irq
);
1478 sky2_tx_clean(sky2
);
1479 sky2_rx_clean(sky2
);
1481 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1482 sky2
->rx_le
, sky2
->rx_le_map
);
1483 kfree(sky2
->rx_ring
);
1485 pci_free_consistent(hw
->pdev
,
1486 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1487 sky2
->tx_le
, sky2
->tx_le_map
);
1488 kfree(sky2
->tx_ring
);
1493 sky2
->rx_ring
= NULL
;
1494 sky2
->tx_ring
= NULL
;
1499 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1504 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1505 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1507 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1508 case PHY_M_PS_SPEED_1000
:
1510 case PHY_M_PS_SPEED_100
:
1517 static void sky2_link_up(struct sky2_port
*sky2
)
1519 struct sky2_hw
*hw
= sky2
->hw
;
1520 unsigned port
= sky2
->port
;
1523 /* Enable Transmit FIFO Underrun */
1524 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1526 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1527 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1528 reg
|= GM_GPCR_AU_ALL_DIS
;
1530 /* Is write/read necessary? Copied from sky2_mac_init */
1531 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1532 gma_read16(hw
, port
, GM_GP_CTRL
);
1534 switch (sky2
->speed
) {
1536 reg
&= ~GM_GPCR_SPEED_100
;
1537 reg
|= GM_GPCR_SPEED_1000
;
1540 reg
&= ~GM_GPCR_SPEED_1000
;
1541 reg
|= GM_GPCR_SPEED_100
;
1544 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1548 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1550 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1551 reg
|= GM_GPCR_DUP_FULL
;
1554 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1555 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1556 gma_read16(hw
, port
, GM_GP_CTRL
);
1558 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1560 netif_carrier_on(sky2
->netdev
);
1561 netif_wake_queue(sky2
->netdev
);
1563 /* Turn on link LED */
1564 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1565 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1567 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1568 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1569 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1571 switch(sky2
->speed
) {
1573 led
|= PHY_M_LEDC_INIT_CTRL(7);
1577 led
|= PHY_M_LEDC_STA1_CTRL(7);
1581 led
|= PHY_M_LEDC_STA0_CTRL(7);
1585 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1586 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1587 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1590 if (netif_msg_link(sky2
))
1591 printk(KERN_INFO PFX
1592 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1593 sky2
->netdev
->name
, sky2
->speed
,
1594 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1595 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1596 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1599 static void sky2_link_down(struct sky2_port
*sky2
)
1601 struct sky2_hw
*hw
= sky2
->hw
;
1602 unsigned port
= sky2
->port
;
1605 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1607 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1608 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1609 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1610 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1612 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1613 /* restore Asymmetric Pause bit */
1614 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1615 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1619 netif_carrier_off(sky2
->netdev
);
1620 netif_stop_queue(sky2
->netdev
);
1622 /* Turn on link LED */
1623 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1625 if (netif_msg_link(sky2
))
1626 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1627 sky2_phy_init(hw
, port
);
1630 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1632 struct sky2_hw
*hw
= sky2
->hw
;
1633 unsigned port
= sky2
->port
;
1636 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1638 if (lpa
& PHY_M_AN_RF
) {
1639 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1643 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1644 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1645 printk(KERN_ERR PFX
"%s: master/slave fault",
1646 sky2
->netdev
->name
);
1650 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1651 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1652 sky2
->netdev
->name
);
1656 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1658 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1660 /* Pause bits are offset (9..8) */
1661 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1664 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1665 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1667 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1668 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1669 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1671 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1676 /* Interrupt from PHY */
1677 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1679 struct net_device
*dev
= hw
->dev
[port
];
1680 struct sky2_port
*sky2
= netdev_priv(dev
);
1681 u16 istatus
, phystat
;
1683 spin_lock(&sky2
->phy_lock
);
1684 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1685 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1687 if (!netif_running(dev
))
1690 if (netif_msg_intr(sky2
))
1691 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1692 sky2
->netdev
->name
, istatus
, phystat
);
1694 if (istatus
& PHY_M_IS_AN_COMPL
) {
1695 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1700 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1701 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1703 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1705 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1707 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1708 if (phystat
& PHY_M_PS_LINK_UP
)
1711 sky2_link_down(sky2
);
1714 spin_unlock(&sky2
->phy_lock
);
1718 /* Transmit timeout is only called if we are running, carries is up
1719 * and tx queue is full (stopped).
1721 static void sky2_tx_timeout(struct net_device
*dev
)
1723 struct sky2_port
*sky2
= netdev_priv(dev
);
1724 struct sky2_hw
*hw
= sky2
->hw
;
1725 unsigned txq
= txqaddr
[sky2
->port
];
1728 if (netif_msg_timer(sky2
))
1729 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1731 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1732 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1734 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1736 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1738 if (report
!= done
) {
1739 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1741 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1742 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1743 } else if (report
!= sky2
->tx_cons
) {
1744 printk(KERN_INFO PFX
"status report lost?\n");
1746 spin_lock_bh(&sky2
->tx_lock
);
1747 sky2_tx_complete(sky2
, report
);
1748 spin_unlock_bh(&sky2
->tx_lock
);
1750 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1752 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1753 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1755 sky2_tx_clean(sky2
);
1758 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1763 /* Want receive buffer size to be multiple of 64 bits
1764 * and incl room for vlan and truncation
1766 static inline unsigned sky2_buf_size(int mtu
)
1768 return ALIGN(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1771 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1773 struct sky2_port
*sky2
= netdev_priv(dev
);
1774 struct sky2_hw
*hw
= sky2
->hw
;
1779 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1782 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1785 if (!netif_running(dev
)) {
1790 imask
= sky2_read32(hw
, B0_IMSK
);
1791 sky2_write32(hw
, B0_IMSK
, 0);
1793 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1794 netif_stop_queue(dev
);
1795 netif_poll_disable(hw
->dev
[0]);
1797 synchronize_irq(hw
->pdev
->irq
);
1799 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1800 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1802 sky2_rx_clean(sky2
);
1805 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1806 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1807 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1809 if (dev
->mtu
> ETH_DATA_LEN
)
1810 mode
|= GM_SMOD_JUMBO_ENA
;
1812 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1814 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1816 err
= sky2_rx_start(sky2
);
1817 sky2_write32(hw
, B0_IMSK
, imask
);
1822 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1824 netif_poll_enable(hw
->dev
[0]);
1825 netif_wake_queue(dev
);
1832 * Receive one packet.
1833 * For small packets or errors, just reuse existing skb.
1834 * For larger packets, get new buffer.
1836 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1837 u16 length
, u32 status
)
1839 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1840 struct sk_buff
*skb
= NULL
;
1842 if (unlikely(netif_msg_rx_status(sky2
)))
1843 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1844 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1846 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1847 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1849 if (status
& GMR_FS_ANY_ERR
)
1852 if (!(status
& GMR_FS_RX_OK
))
1855 if (length
> sky2
->netdev
->mtu
+ ETH_HLEN
)
1858 if (length
< copybreak
) {
1859 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1863 skb_reserve(skb
, 2);
1864 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1865 length
, PCI_DMA_FROMDEVICE
);
1866 memcpy(skb
->data
, re
->skb
->data
, length
);
1867 skb
->ip_summed
= re
->skb
->ip_summed
;
1868 skb
->csum
= re
->skb
->csum
;
1869 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1870 length
, PCI_DMA_FROMDEVICE
);
1872 struct sk_buff
*nskb
;
1874 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1880 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1881 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1882 prefetch(skb
->data
);
1884 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1885 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1888 skb_put(skb
, length
);
1890 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1891 sky2_rx_add(sky2
, re
->mapaddr
);
1896 ++sky2
->net_stats
.rx_over_errors
;
1900 ++sky2
->net_stats
.rx_errors
;
1902 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1903 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1904 sky2
->netdev
->name
, status
, length
);
1906 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1907 sky2
->net_stats
.rx_length_errors
++;
1908 if (status
& GMR_FS_FRAGMENT
)
1909 sky2
->net_stats
.rx_frame_errors
++;
1910 if (status
& GMR_FS_CRC_ERR
)
1911 sky2
->net_stats
.rx_crc_errors
++;
1912 if (status
& GMR_FS_RX_FF_OV
)
1913 sky2
->net_stats
.rx_fifo_errors
++;
1918 /* Transmit complete */
1919 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
1921 struct sky2_port
*sky2
= netdev_priv(dev
);
1923 if (netif_running(dev
)) {
1924 spin_lock(&sky2
->tx_lock
);
1925 sky2_tx_complete(sky2
, last
);
1926 spin_unlock(&sky2
->tx_lock
);
1930 /* Is status ring empty or is there more to do? */
1931 static inline int sky2_more_work(const struct sky2_hw
*hw
)
1933 return (hw
->st_idx
!= sky2_read16(hw
, STAT_PUT_IDX
));
1936 /* Process status response ring */
1937 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
1939 struct sky2_port
*sky2
;
1941 unsigned buf_write
[2] = { 0, 0 };
1942 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1946 while (hw
->st_idx
!= hwidx
) {
1947 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1948 struct net_device
*dev
;
1949 struct sk_buff
*skb
;
1953 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
1955 BUG_ON(le
->link
>= 2);
1956 dev
= hw
->dev
[le
->link
];
1958 sky2
= netdev_priv(dev
);
1959 length
= le
->length
;
1960 status
= le
->status
;
1962 switch (le
->opcode
& ~HW_OWNER
) {
1964 skb
= sky2_receive(sky2
, length
, status
);
1969 skb
->protocol
= eth_type_trans(skb
, dev
);
1970 dev
->last_rx
= jiffies
;
1972 #ifdef SKY2_VLAN_TAG_USED
1973 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1974 vlan_hwaccel_receive_skb(skb
,
1976 be16_to_cpu(sky2
->rx_tag
));
1979 netif_receive_skb(skb
);
1981 /* Update receiver after 16 frames */
1982 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
1983 sky2_put_idx(hw
, rxqaddr
[le
->link
],
1985 buf_write
[le
->link
] = 0;
1988 /* Stop after net poll weight */
1989 if (++work_done
>= to_do
)
1993 #ifdef SKY2_VLAN_TAG_USED
1995 sky2
->rx_tag
= length
;
1999 sky2
->rx_tag
= length
;
2003 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2004 skb
->ip_summed
= CHECKSUM_HW
;
2005 skb
->csum
= le16_to_cpu(status
);
2009 /* TX index reports status for both ports */
2010 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2011 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2013 sky2_tx_done(hw
->dev
[1],
2014 ((status
>> 24) & 0xff)
2015 | (u16
)(length
& 0xf) << 8);
2019 if (net_ratelimit())
2020 printk(KERN_WARNING PFX
2021 "unknown status opcode 0x%x\n", le
->opcode
);
2028 sky2
= netdev_priv(hw
->dev
[0]);
2029 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2033 sky2
= netdev_priv(hw
->dev
[1]);
2034 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2040 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2042 struct net_device
*dev
= hw
->dev
[port
];
2044 if (net_ratelimit())
2045 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2048 if (status
& Y2_IS_PAR_RD1
) {
2049 if (net_ratelimit())
2050 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2053 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2056 if (status
& Y2_IS_PAR_WR1
) {
2057 if (net_ratelimit())
2058 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2061 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2064 if (status
& Y2_IS_PAR_MAC1
) {
2065 if (net_ratelimit())
2066 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2067 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2070 if (status
& Y2_IS_PAR_RX1
) {
2071 if (net_ratelimit())
2072 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2073 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2076 if (status
& Y2_IS_TCP_TXA1
) {
2077 if (net_ratelimit())
2078 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2080 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2084 static void sky2_hw_intr(struct sky2_hw
*hw
)
2086 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2088 if (status
& Y2_IS_TIST_OV
)
2089 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2091 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2094 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2095 if (net_ratelimit())
2096 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2097 pci_name(hw
->pdev
), pci_err
);
2099 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2100 sky2_pci_write16(hw
, PCI_STATUS
,
2101 pci_err
| PCI_STATUS_ERROR_BITS
);
2102 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2105 if (status
& Y2_IS_PCI_EXP
) {
2106 /* PCI-Express uncorrectable Error occurred */
2109 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2111 if (net_ratelimit())
2112 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2113 pci_name(hw
->pdev
), pex_err
);
2115 /* clear the interrupt */
2116 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2117 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2119 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2121 if (pex_err
& PEX_FATAL_ERRORS
) {
2122 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2123 hwmsk
&= ~Y2_IS_PCI_EXP
;
2124 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2128 if (status
& Y2_HWE_L1_MASK
)
2129 sky2_hw_error(hw
, 0, status
);
2131 if (status
& Y2_HWE_L1_MASK
)
2132 sky2_hw_error(hw
, 1, status
);
2135 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2137 struct net_device
*dev
= hw
->dev
[port
];
2138 struct sky2_port
*sky2
= netdev_priv(dev
);
2139 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2141 if (netif_msg_intr(sky2
))
2142 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2145 if (status
& GM_IS_RX_FF_OR
) {
2146 ++sky2
->net_stats
.rx_fifo_errors
;
2147 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2150 if (status
& GM_IS_TX_FF_UR
) {
2151 ++sky2
->net_stats
.tx_fifo_errors
;
2152 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2156 /* This should never happen it is a fatal situation */
2157 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2158 const char *rxtx
, u32 mask
)
2160 struct net_device
*dev
= hw
->dev
[port
];
2161 struct sky2_port
*sky2
= netdev_priv(dev
);
2164 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2165 dev
? dev
->name
: "<not registered>", rxtx
);
2167 imask
= sky2_read32(hw
, B0_IMSK
);
2169 sky2_write32(hw
, B0_IMSK
, imask
);
2172 spin_lock(&sky2
->phy_lock
);
2173 sky2_link_down(sky2
);
2174 spin_unlock(&sky2
->phy_lock
);
2178 /* If idle then force a fake soft NAPI poll once a second
2179 * to work around cases where sharing an edge triggered interrupt.
2181 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2183 if (idle_timeout
> 0)
2184 mod_timer(&hw
->idle_timer
,
2185 jiffies
+ msecs_to_jiffies(idle_timeout
));
2188 static void sky2_idle(unsigned long arg
)
2190 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2191 struct net_device
*dev
= hw
->dev
[0];
2193 if (__netif_rx_schedule_prep(dev
))
2194 __netif_rx_schedule(dev
);
2196 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2200 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2202 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2203 int work_limit
= min(dev0
->quota
, *budget
);
2205 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2210 if (status
& Y2_IS_HW_ERR
)
2213 if (status
& Y2_IS_IRQ_PHY1
)
2214 sky2_phy_intr(hw
, 0);
2216 if (status
& Y2_IS_IRQ_PHY2
)
2217 sky2_phy_intr(hw
, 1);
2219 if (status
& Y2_IS_IRQ_MAC1
)
2220 sky2_mac_intr(hw
, 0);
2222 if (status
& Y2_IS_IRQ_MAC2
)
2223 sky2_mac_intr(hw
, 1);
2225 if (status
& Y2_IS_CHK_RX1
)
2226 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2228 if (status
& Y2_IS_CHK_RX2
)
2229 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2231 if (status
& Y2_IS_CHK_TXA1
)
2232 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2234 if (status
& Y2_IS_CHK_TXA2
)
2235 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2237 work_done
= sky2_status_intr(hw
, work_limit
);
2238 *budget
-= work_done
;
2239 dev0
->quota
-= work_done
;
2241 if (status
& Y2_IS_STAT_BMU
)
2242 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2244 if (sky2_more_work(hw
))
2247 netif_rx_complete(dev0
);
2249 sky2_read32(hw
, B0_Y2_SP_LISR
);
2253 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2255 struct sky2_hw
*hw
= dev_id
;
2256 struct net_device
*dev0
= hw
->dev
[0];
2259 /* Reading this mask interrupts as side effect */
2260 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2261 if (status
== 0 || status
== ~0)
2264 prefetch(&hw
->st_le
[hw
->st_idx
]);
2265 if (likely(__netif_rx_schedule_prep(dev0
)))
2266 __netif_rx_schedule(dev0
);
2271 #ifdef CONFIG_NET_POLL_CONTROLLER
2272 static void sky2_netpoll(struct net_device
*dev
)
2274 struct sky2_port
*sky2
= netdev_priv(dev
);
2275 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2277 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2278 __netif_rx_schedule(dev0
);
2282 /* Chip internal frequency for clock calculations */
2283 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2285 switch (hw
->chip_id
) {
2286 case CHIP_ID_YUKON_EC
:
2287 case CHIP_ID_YUKON_EC_U
:
2288 return 125; /* 125 Mhz */
2289 case CHIP_ID_YUKON_FE
:
2290 return 100; /* 100 Mhz */
2291 default: /* YUKON_XL */
2292 return 156; /* 156 Mhz */
2296 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2298 return sky2_mhz(hw
) * us
;
2301 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2303 return clk
/ sky2_mhz(hw
);
2307 static int sky2_reset(struct sky2_hw
*hw
)
2313 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2315 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2316 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2317 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2318 pci_name(hw
->pdev
), hw
->chip_id
);
2322 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2324 /* This rev is really old, and requires untested workarounds */
2325 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2326 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2327 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2328 hw
->chip_id
, hw
->chip_rev
);
2333 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2334 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2335 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2339 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2340 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2342 /* clear PCI errors, if any */
2343 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2345 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2346 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2349 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2351 /* clear any PEX errors */
2352 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2353 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2356 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2357 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2360 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2361 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2362 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2366 sky2_set_power_state(hw
, PCI_D0
);
2368 for (i
= 0; i
< hw
->ports
; i
++) {
2369 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2370 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2373 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2375 /* Clear I2C IRQ noise */
2376 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2378 /* turn off hardware timer (unused) */
2379 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2380 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2382 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2384 /* Turn off descriptor polling */
2385 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2387 /* Turn off receive timestamp */
2388 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2389 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2391 /* enable the Tx Arbiters */
2392 for (i
= 0; i
< hw
->ports
; i
++)
2393 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2395 /* Initialize ram interface */
2396 for (i
= 0; i
< hw
->ports
; i
++) {
2397 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2399 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2400 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2401 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2402 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2403 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2404 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2405 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2406 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2407 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2408 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2409 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2410 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2413 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2415 for (i
= 0; i
< hw
->ports
; i
++)
2416 sky2_phy_reset(hw
, i
);
2418 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2421 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2422 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2424 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2425 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2427 /* Set the list last index */
2428 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2430 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2431 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2433 /* set Status-FIFO ISR watermark */
2434 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2435 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2437 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2439 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2440 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2441 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2443 /* enable status unit */
2444 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2446 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2447 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2448 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2453 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2457 modes
= SUPPORTED_10baseT_Half
2458 | SUPPORTED_10baseT_Full
2459 | SUPPORTED_100baseT_Half
2460 | SUPPORTED_100baseT_Full
2461 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2463 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2464 modes
|= SUPPORTED_1000baseT_Half
2465 | SUPPORTED_1000baseT_Full
;
2467 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2468 | SUPPORTED_Autoneg
;
2472 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2474 struct sky2_port
*sky2
= netdev_priv(dev
);
2475 struct sky2_hw
*hw
= sky2
->hw
;
2477 ecmd
->transceiver
= XCVR_INTERNAL
;
2478 ecmd
->supported
= sky2_supported_modes(hw
);
2479 ecmd
->phy_address
= PHY_ADDR_MARV
;
2481 ecmd
->supported
= SUPPORTED_10baseT_Half
2482 | SUPPORTED_10baseT_Full
2483 | SUPPORTED_100baseT_Half
2484 | SUPPORTED_100baseT_Full
2485 | SUPPORTED_1000baseT_Half
2486 | SUPPORTED_1000baseT_Full
2487 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2488 ecmd
->port
= PORT_TP
;
2490 ecmd
->port
= PORT_FIBRE
;
2492 ecmd
->advertising
= sky2
->advertising
;
2493 ecmd
->autoneg
= sky2
->autoneg
;
2494 ecmd
->speed
= sky2
->speed
;
2495 ecmd
->duplex
= sky2
->duplex
;
2499 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2501 struct sky2_port
*sky2
= netdev_priv(dev
);
2502 const struct sky2_hw
*hw
= sky2
->hw
;
2503 u32 supported
= sky2_supported_modes(hw
);
2505 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2506 ecmd
->advertising
= supported
;
2512 switch (ecmd
->speed
) {
2514 if (ecmd
->duplex
== DUPLEX_FULL
)
2515 setting
= SUPPORTED_1000baseT_Full
;
2516 else if (ecmd
->duplex
== DUPLEX_HALF
)
2517 setting
= SUPPORTED_1000baseT_Half
;
2522 if (ecmd
->duplex
== DUPLEX_FULL
)
2523 setting
= SUPPORTED_100baseT_Full
;
2524 else if (ecmd
->duplex
== DUPLEX_HALF
)
2525 setting
= SUPPORTED_100baseT_Half
;
2531 if (ecmd
->duplex
== DUPLEX_FULL
)
2532 setting
= SUPPORTED_10baseT_Full
;
2533 else if (ecmd
->duplex
== DUPLEX_HALF
)
2534 setting
= SUPPORTED_10baseT_Half
;
2542 if ((setting
& supported
) == 0)
2545 sky2
->speed
= ecmd
->speed
;
2546 sky2
->duplex
= ecmd
->duplex
;
2549 sky2
->autoneg
= ecmd
->autoneg
;
2550 sky2
->advertising
= ecmd
->advertising
;
2552 if (netif_running(dev
))
2553 sky2_phy_reinit(sky2
);
2558 static void sky2_get_drvinfo(struct net_device
*dev
,
2559 struct ethtool_drvinfo
*info
)
2561 struct sky2_port
*sky2
= netdev_priv(dev
);
2563 strcpy(info
->driver
, DRV_NAME
);
2564 strcpy(info
->version
, DRV_VERSION
);
2565 strcpy(info
->fw_version
, "N/A");
2566 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2569 static const struct sky2_stat
{
2570 char name
[ETH_GSTRING_LEN
];
2573 { "tx_bytes", GM_TXO_OK_HI
},
2574 { "rx_bytes", GM_RXO_OK_HI
},
2575 { "tx_broadcast", GM_TXF_BC_OK
},
2576 { "rx_broadcast", GM_RXF_BC_OK
},
2577 { "tx_multicast", GM_TXF_MC_OK
},
2578 { "rx_multicast", GM_RXF_MC_OK
},
2579 { "tx_unicast", GM_TXF_UC_OK
},
2580 { "rx_unicast", GM_RXF_UC_OK
},
2581 { "tx_mac_pause", GM_TXF_MPAUSE
},
2582 { "rx_mac_pause", GM_RXF_MPAUSE
},
2583 { "collisions", GM_TXF_COL
},
2584 { "late_collision",GM_TXF_LAT_COL
},
2585 { "aborted", GM_TXF_ABO_COL
},
2586 { "single_collisions", GM_TXF_SNG_COL
},
2587 { "multi_collisions", GM_TXF_MUL_COL
},
2589 { "rx_short", GM_RXF_SHT
},
2590 { "rx_runt", GM_RXE_FRAG
},
2591 { "rx_64_byte_packets", GM_RXF_64B
},
2592 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2593 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2594 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2595 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2596 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2597 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2598 { "rx_too_long", GM_RXF_LNG_ERR
},
2599 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2600 { "rx_jabber", GM_RXF_JAB_PKT
},
2601 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2603 { "tx_64_byte_packets", GM_TXF_64B
},
2604 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2605 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2606 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2607 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2608 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2609 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2610 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2613 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2615 struct sky2_port
*sky2
= netdev_priv(dev
);
2617 return sky2
->rx_csum
;
2620 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2622 struct sky2_port
*sky2
= netdev_priv(dev
);
2624 sky2
->rx_csum
= data
;
2626 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2627 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2632 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2634 struct sky2_port
*sky2
= netdev_priv(netdev
);
2635 return sky2
->msg_enable
;
2638 static int sky2_nway_reset(struct net_device
*dev
)
2640 struct sky2_port
*sky2
= netdev_priv(dev
);
2642 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2645 sky2_phy_reinit(sky2
);
2650 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2652 struct sky2_hw
*hw
= sky2
->hw
;
2653 unsigned port
= sky2
->port
;
2656 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2657 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2658 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2659 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2661 for (i
= 2; i
< count
; i
++)
2662 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2665 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2667 struct sky2_port
*sky2
= netdev_priv(netdev
);
2668 sky2
->msg_enable
= value
;
2671 static int sky2_get_stats_count(struct net_device
*dev
)
2673 return ARRAY_SIZE(sky2_stats
);
2676 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2677 struct ethtool_stats
*stats
, u64
* data
)
2679 struct sky2_port
*sky2
= netdev_priv(dev
);
2681 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2684 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2688 switch (stringset
) {
2690 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2691 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2692 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2697 /* Use hardware MIB variables for critical path statistics and
2698 * transmit feedback not reported at interrupt.
2699 * Other errors are accounted for in interrupt handler.
2701 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2703 struct sky2_port
*sky2
= netdev_priv(dev
);
2706 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2708 sky2
->net_stats
.tx_bytes
= data
[0];
2709 sky2
->net_stats
.rx_bytes
= data
[1];
2710 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2711 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2712 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2713 sky2
->net_stats
.collisions
= data
[10];
2714 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2716 return &sky2
->net_stats
;
2719 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2721 struct sky2_port
*sky2
= netdev_priv(dev
);
2722 struct sky2_hw
*hw
= sky2
->hw
;
2723 unsigned port
= sky2
->port
;
2724 const struct sockaddr
*addr
= p
;
2726 if (!is_valid_ether_addr(addr
->sa_data
))
2727 return -EADDRNOTAVAIL
;
2729 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2730 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2731 dev
->dev_addr
, ETH_ALEN
);
2732 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2733 dev
->dev_addr
, ETH_ALEN
);
2735 /* virtual address for data */
2736 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2738 /* physical address: used for pause frames */
2739 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2744 static void sky2_set_multicast(struct net_device
*dev
)
2746 struct sky2_port
*sky2
= netdev_priv(dev
);
2747 struct sky2_hw
*hw
= sky2
->hw
;
2748 unsigned port
= sky2
->port
;
2749 struct dev_mc_list
*list
= dev
->mc_list
;
2753 memset(filter
, 0, sizeof(filter
));
2755 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2756 reg
|= GM_RXCR_UCF_ENA
;
2758 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2759 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2760 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2761 memset(filter
, 0xff, sizeof(filter
));
2762 else if (dev
->mc_count
== 0) /* no multicast */
2763 reg
&= ~GM_RXCR_MCF_ENA
;
2766 reg
|= GM_RXCR_MCF_ENA
;
2768 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2769 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2770 filter
[bit
/ 8] |= 1 << (bit
% 8);
2774 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2775 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2776 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2777 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2778 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2779 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2780 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2781 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2783 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2786 /* Can have one global because blinking is controlled by
2787 * ethtool and that is always under RTNL mutex
2789 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2793 switch (hw
->chip_id
) {
2794 case CHIP_ID_YUKON_XL
:
2795 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2796 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2797 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2798 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2799 PHY_M_LEDC_INIT_CTRL(7) |
2800 PHY_M_LEDC_STA1_CTRL(7) |
2801 PHY_M_LEDC_STA0_CTRL(7))
2804 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2808 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2809 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2810 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2811 PHY_M_LED_MO_10(MO_LED_ON
) |
2812 PHY_M_LED_MO_100(MO_LED_ON
) |
2813 PHY_M_LED_MO_1000(MO_LED_ON
) |
2814 PHY_M_LED_MO_RX(MO_LED_ON
)
2815 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2816 PHY_M_LED_MO_10(MO_LED_OFF
) |
2817 PHY_M_LED_MO_100(MO_LED_OFF
) |
2818 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2819 PHY_M_LED_MO_RX(MO_LED_OFF
));
2824 /* blink LED's for finding board */
2825 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2827 struct sky2_port
*sky2
= netdev_priv(dev
);
2828 struct sky2_hw
*hw
= sky2
->hw
;
2829 unsigned port
= sky2
->port
;
2830 u16 ledctrl
, ledover
= 0;
2835 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2836 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2840 /* save initial values */
2841 spin_lock_bh(&sky2
->phy_lock
);
2842 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2843 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2844 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2845 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2846 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2848 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2849 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2853 while (!interrupted
&& ms
> 0) {
2854 sky2_led(hw
, port
, onoff
);
2857 spin_unlock_bh(&sky2
->phy_lock
);
2858 interrupted
= msleep_interruptible(250);
2859 spin_lock_bh(&sky2
->phy_lock
);
2864 /* resume regularly scheduled programming */
2865 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2866 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2867 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2868 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2869 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2871 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2872 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2874 spin_unlock_bh(&sky2
->phy_lock
);
2879 static void sky2_get_pauseparam(struct net_device
*dev
,
2880 struct ethtool_pauseparam
*ecmd
)
2882 struct sky2_port
*sky2
= netdev_priv(dev
);
2884 ecmd
->tx_pause
= sky2
->tx_pause
;
2885 ecmd
->rx_pause
= sky2
->rx_pause
;
2886 ecmd
->autoneg
= sky2
->autoneg
;
2889 static int sky2_set_pauseparam(struct net_device
*dev
,
2890 struct ethtool_pauseparam
*ecmd
)
2892 struct sky2_port
*sky2
= netdev_priv(dev
);
2895 sky2
->autoneg
= ecmd
->autoneg
;
2896 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2897 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2899 sky2_phy_reinit(sky2
);
2904 static int sky2_get_coalesce(struct net_device
*dev
,
2905 struct ethtool_coalesce
*ecmd
)
2907 struct sky2_port
*sky2
= netdev_priv(dev
);
2908 struct sky2_hw
*hw
= sky2
->hw
;
2910 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2911 ecmd
->tx_coalesce_usecs
= 0;
2913 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2914 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2916 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2918 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2919 ecmd
->rx_coalesce_usecs
= 0;
2921 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2922 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2924 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2926 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2927 ecmd
->rx_coalesce_usecs_irq
= 0;
2929 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2930 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2933 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2938 /* Note: this affect both ports */
2939 static int sky2_set_coalesce(struct net_device
*dev
,
2940 struct ethtool_coalesce
*ecmd
)
2942 struct sky2_port
*sky2
= netdev_priv(dev
);
2943 struct sky2_hw
*hw
= sky2
->hw
;
2944 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
2946 if (ecmd
->tx_coalesce_usecs
> tmax
||
2947 ecmd
->rx_coalesce_usecs
> tmax
||
2948 ecmd
->rx_coalesce_usecs_irq
> tmax
)
2951 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2953 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2955 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2958 if (ecmd
->tx_coalesce_usecs
== 0)
2959 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2961 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2962 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2963 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2965 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2967 if (ecmd
->rx_coalesce_usecs
== 0)
2968 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2970 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2971 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2972 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2974 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2976 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2977 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2979 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2980 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2981 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2983 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2987 static void sky2_get_ringparam(struct net_device
*dev
,
2988 struct ethtool_ringparam
*ering
)
2990 struct sky2_port
*sky2
= netdev_priv(dev
);
2992 ering
->rx_max_pending
= RX_MAX_PENDING
;
2993 ering
->rx_mini_max_pending
= 0;
2994 ering
->rx_jumbo_max_pending
= 0;
2995 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2997 ering
->rx_pending
= sky2
->rx_pending
;
2998 ering
->rx_mini_pending
= 0;
2999 ering
->rx_jumbo_pending
= 0;
3000 ering
->tx_pending
= sky2
->tx_pending
;
3003 static int sky2_set_ringparam(struct net_device
*dev
,
3004 struct ethtool_ringparam
*ering
)
3006 struct sky2_port
*sky2
= netdev_priv(dev
);
3009 if (ering
->rx_pending
> RX_MAX_PENDING
||
3010 ering
->rx_pending
< 8 ||
3011 ering
->tx_pending
< MAX_SKB_TX_LE
||
3012 ering
->tx_pending
> TX_RING_SIZE
- 1)
3015 if (netif_running(dev
))
3018 sky2
->rx_pending
= ering
->rx_pending
;
3019 sky2
->tx_pending
= ering
->tx_pending
;
3021 if (netif_running(dev
)) {
3026 sky2_set_multicast(dev
);
3032 static int sky2_get_regs_len(struct net_device
*dev
)
3038 * Returns copy of control register region
3039 * Note: access to the RAM address register set will cause timeouts.
3041 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3044 const struct sky2_port
*sky2
= netdev_priv(dev
);
3045 const void __iomem
*io
= sky2
->hw
->regs
;
3047 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3049 memset(p
, 0, regs
->len
);
3051 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3053 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3055 regs
->len
- B3_RI_WTO_R1
);
3058 static struct ethtool_ops sky2_ethtool_ops
= {
3059 .get_settings
= sky2_get_settings
,
3060 .set_settings
= sky2_set_settings
,
3061 .get_drvinfo
= sky2_get_drvinfo
,
3062 .get_msglevel
= sky2_get_msglevel
,
3063 .set_msglevel
= sky2_set_msglevel
,
3064 .nway_reset
= sky2_nway_reset
,
3065 .get_regs_len
= sky2_get_regs_len
,
3066 .get_regs
= sky2_get_regs
,
3067 .get_link
= ethtool_op_get_link
,
3068 .get_sg
= ethtool_op_get_sg
,
3069 .set_sg
= ethtool_op_set_sg
,
3070 .get_tx_csum
= ethtool_op_get_tx_csum
,
3071 .set_tx_csum
= ethtool_op_set_tx_csum
,
3072 .get_tso
= ethtool_op_get_tso
,
3073 .set_tso
= ethtool_op_set_tso
,
3074 .get_rx_csum
= sky2_get_rx_csum
,
3075 .set_rx_csum
= sky2_set_rx_csum
,
3076 .get_strings
= sky2_get_strings
,
3077 .get_coalesce
= sky2_get_coalesce
,
3078 .set_coalesce
= sky2_set_coalesce
,
3079 .get_ringparam
= sky2_get_ringparam
,
3080 .set_ringparam
= sky2_set_ringparam
,
3081 .get_pauseparam
= sky2_get_pauseparam
,
3082 .set_pauseparam
= sky2_set_pauseparam
,
3083 .phys_id
= sky2_phys_id
,
3084 .get_stats_count
= sky2_get_stats_count
,
3085 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3086 .get_perm_addr
= ethtool_op_get_perm_addr
,
3089 /* Initialize network device */
3090 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3091 unsigned port
, int highmem
)
3093 struct sky2_port
*sky2
;
3094 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3097 printk(KERN_ERR
"sky2 etherdev alloc failed");
3101 SET_MODULE_OWNER(dev
);
3102 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3103 dev
->irq
= hw
->pdev
->irq
;
3104 dev
->open
= sky2_up
;
3105 dev
->stop
= sky2_down
;
3106 dev
->do_ioctl
= sky2_ioctl
;
3107 dev
->hard_start_xmit
= sky2_xmit_frame
;
3108 dev
->get_stats
= sky2_get_stats
;
3109 dev
->set_multicast_list
= sky2_set_multicast
;
3110 dev
->set_mac_address
= sky2_set_mac_address
;
3111 dev
->change_mtu
= sky2_change_mtu
;
3112 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3113 dev
->tx_timeout
= sky2_tx_timeout
;
3114 dev
->watchdog_timeo
= TX_WATCHDOG
;
3116 dev
->poll
= sky2_poll
;
3117 dev
->weight
= NAPI_WEIGHT
;
3118 #ifdef CONFIG_NET_POLL_CONTROLLER
3119 dev
->poll_controller
= sky2_netpoll
;
3122 sky2
= netdev_priv(dev
);
3125 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3127 spin_lock_init(&sky2
->tx_lock
);
3128 /* Auto speed and flow control */
3129 sky2
->autoneg
= AUTONEG_ENABLE
;
3134 sky2
->advertising
= sky2_supported_modes(hw
);
3137 spin_lock_init(&sky2
->phy_lock
);
3138 sky2
->tx_pending
= TX_DEF_PENDING
;
3139 sky2
->rx_pending
= RX_DEF_PENDING
;
3140 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3142 hw
->dev
[port
] = dev
;
3146 dev
->features
|= NETIF_F_LLTX
;
3147 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3148 dev
->features
|= NETIF_F_TSO
;
3150 dev
->features
|= NETIF_F_HIGHDMA
;
3151 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3153 #ifdef SKY2_VLAN_TAG_USED
3154 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3155 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3156 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3159 /* read the mac address */
3160 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3161 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3163 /* device is off until link detection */
3164 netif_carrier_off(dev
);
3165 netif_stop_queue(dev
);
3170 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3172 const struct sky2_port
*sky2
= netdev_priv(dev
);
3174 if (netif_msg_probe(sky2
))
3175 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3177 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3178 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3181 /* Handle software interrupt used during MSI test */
3182 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3183 struct pt_regs
*regs
)
3185 struct sky2_hw
*hw
= dev_id
;
3186 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3191 if (status
& Y2_IS_IRQ_SW
) {
3192 hw
->msi_detected
= 1;
3193 wake_up(&hw
->msi_wait
);
3194 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3196 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3201 /* Test interrupt path by forcing a a software IRQ */
3202 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3204 struct pci_dev
*pdev
= hw
->pdev
;
3207 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3209 err
= request_irq(pdev
->irq
, sky2_test_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3211 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3212 pci_name(pdev
), pdev
->irq
);
3216 init_waitqueue_head (&hw
->msi_wait
);
3218 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3221 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3223 if (!hw
->msi_detected
) {
3224 /* MSI test failed, go back to INTx mode */
3225 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3226 "switching to INTx mode. Please report this failure to "
3227 "the PCI maintainer and include system chipset information.\n",
3231 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3234 sky2_write32(hw
, B0_IMSK
, 0);
3236 free_irq(pdev
->irq
, hw
);
3241 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3242 const struct pci_device_id
*ent
)
3244 struct net_device
*dev
, *dev1
= NULL
;
3246 int err
, pm_cap
, using_dac
= 0;
3248 err
= pci_enable_device(pdev
);
3250 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3255 err
= pci_request_regions(pdev
, DRV_NAME
);
3257 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3262 pci_set_master(pdev
);
3264 /* Find power-management capability. */
3265 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3267 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3270 goto err_out_free_regions
;
3273 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3274 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3276 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3278 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3279 "for consistent allocations\n", pci_name(pdev
));
3280 goto err_out_free_regions
;
3284 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3286 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3288 goto err_out_free_regions
;
3293 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3295 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3297 goto err_out_free_regions
;
3302 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3304 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3306 goto err_out_free_hw
;
3308 hw
->pm_cap
= pm_cap
;
3311 /* byte swap descriptors in hardware */
3315 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3316 reg
|= PCI_REV_DESC
;
3317 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3321 /* ring for status responses */
3322 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3325 goto err_out_iounmap
;
3327 err
= sky2_reset(hw
);
3329 goto err_out_iounmap
;
3331 printk(KERN_INFO PFX
"v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3332 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3333 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3334 hw
->chip_id
, hw
->chip_rev
);
3336 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3338 goto err_out_free_pci
;
3340 err
= register_netdev(dev
);
3342 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3344 goto err_out_free_netdev
;
3347 sky2_show_addr(dev
);
3349 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3350 if (register_netdev(dev1
) == 0)
3351 sky2_show_addr(dev1
);
3353 /* Failure to register second port need not be fatal */
3354 printk(KERN_WARNING PFX
3355 "register of second port failed\n");
3361 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3362 err
= sky2_test_msi(hw
);
3363 if (err
== -EOPNOTSUPP
)
3364 pci_disable_msi(pdev
);
3366 goto err_out_unregister
;
3369 err
= request_irq(pdev
->irq
, sky2_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3371 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3372 pci_name(pdev
), pdev
->irq
);
3373 goto err_out_unregister
;
3376 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3378 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3379 sky2_idle_start(hw
);
3381 pci_set_drvdata(pdev
, hw
);
3386 pci_disable_msi(pdev
);
3388 unregister_netdev(dev1
);
3391 unregister_netdev(dev
);
3392 err_out_free_netdev
:
3395 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3396 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3401 err_out_free_regions
:
3402 pci_release_regions(pdev
);
3403 pci_disable_device(pdev
);
3408 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3410 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3411 struct net_device
*dev0
, *dev1
;
3416 del_timer_sync(&hw
->idle_timer
);
3418 sky2_write32(hw
, B0_IMSK
, 0);
3419 synchronize_irq(hw
->pdev
->irq
);
3424 unregister_netdev(dev1
);
3425 unregister_netdev(dev0
);
3427 sky2_set_power_state(hw
, PCI_D3hot
);
3428 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3429 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3430 sky2_read8(hw
, B0_CTST
);
3432 free_irq(pdev
->irq
, hw
);
3433 pci_disable_msi(pdev
);
3434 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3435 pci_release_regions(pdev
);
3436 pci_disable_device(pdev
);
3444 pci_set_drvdata(pdev
, NULL
);
3448 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3450 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3452 pci_power_t pstate
= pci_choose_state(pdev
, state
);
3454 if (!(pstate
== PCI_D3hot
|| pstate
== PCI_D3cold
))
3457 del_timer_sync(&hw
->idle_timer
);
3458 netif_poll_disable(hw
->dev
[0]);
3460 for (i
= 0; i
< hw
->ports
; i
++) {
3461 struct net_device
*dev
= hw
->dev
[i
];
3463 if (netif_running(dev
)) {
3465 netif_device_detach(dev
);
3469 sky2_write32(hw
, B0_IMSK
, 0);
3470 pci_save_state(pdev
);
3471 sky2_set_power_state(hw
, pstate
);
3475 static int sky2_resume(struct pci_dev
*pdev
)
3477 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3480 pci_restore_state(pdev
);
3481 pci_enable_wake(pdev
, PCI_D0
, 0);
3482 sky2_set_power_state(hw
, PCI_D0
);
3484 err
= sky2_reset(hw
);
3488 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3490 for (i
= 0; i
< hw
->ports
; i
++) {
3491 struct net_device
*dev
= hw
->dev
[i
];
3492 if (netif_running(dev
)) {
3493 netif_device_attach(dev
);
3497 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3505 netif_poll_enable(hw
->dev
[0]);
3506 sky2_idle_start(hw
);
3512 static struct pci_driver sky2_driver
= {
3514 .id_table
= sky2_id_table
,
3515 .probe
= sky2_probe
,
3516 .remove
= __devexit_p(sky2_remove
),
3518 .suspend
= sky2_suspend
,
3519 .resume
= sky2_resume
,
3523 static int __init
sky2_init_module(void)
3525 return pci_register_driver(&sky2_driver
);
3528 static void __exit
sky2_cleanup_module(void)
3530 pci_unregister_driver(&sky2_driver
);
3533 module_init(sky2_init_module
);
3534 module_exit(sky2_cleanup_module
);
3536 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3537 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3538 MODULE_LICENSE("GPL");
3539 MODULE_VERSION(DRV_VERSION
);