drivers/net/stmmac/dwmac1000_dma.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This contains the functions to handle the dma.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   You should have received a copy of the GNU General Public License along with
  20   this program; if not, write to the Free Software Foundation, Inc.,
  21   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22
  23   The full GNU General Public License is included in this distribution in
  24   the file called "COPYING".
  25
  26   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  27 *******************************************************************************/
  28
  29 #include "dwmac1000.h"
  30 #include "dwmac_dma.h"
  31
  32 static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
  33                               u32 dma_rx)
  34 {
  35         u32 value = readl(ioaddr + DMA_BUS_MODE);
  36         /* DMA SW reset */
  37         value |= DMA_BUS_MODE_SFT_RESET;
  38         writel(value, ioaddr + DMA_BUS_MODE);
  39         do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
  40
  41         value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL |
  42             ((pbl << DMA_BUS_MODE_PBL_SHIFT) |
  43              (pbl << DMA_BUS_MODE_RPBL_SHIFT));
  44
  45 #ifdef CONFIG_STMMAC_DA
  46         value |= DMA_BUS_MODE_DA;       /* Rx has priority over tx */
  47 #endif
  48         writel(value, ioaddr + DMA_BUS_MODE);
  49
  50         /* Mask interrupts by writing to CSR7 */
  51         writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
  52
  53         /* The base address of the RX/TX descriptor lists must be written into
  54          * DMA CSR3 and CSR4, respectively. */
  55         writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
  56         writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
  57
  58         return 0;
  59 }
  60
  61 static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode,
  62                                     int rxmode)
  63 {
  64         u32 csr6 = readl(ioaddr + DMA_CONTROL);
  65
  66         if (txmode == SF_DMA_MODE) {
  67                 CHIP_DBG(KERN_DEBUG "GMAC: enable TX store and forward mode\n");
  68                 /* Transmit COE type 2 cannot be done in cut-through mode. */
  69                 csr6 |= DMA_CONTROL_TSF;
  70                 /* Operating on second frame increase the performance
  71                  * especially when transmit store-and-forward is used.*/
  72                 csr6 |= DMA_CONTROL_OSF;
  73         } else {
  74                 CHIP_DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode"
  75                               " (threshold = %d)\n", txmode);
  76                 csr6 &= ~DMA_CONTROL_TSF;
  77                 csr6 &= DMA_CONTROL_TC_TX_MASK;
  78                 /* Set the transmit threshold */
  79                 if (txmode <= 32)
  80                         csr6 |= DMA_CONTROL_TTC_32;
  81                 else if (txmode <= 64)
  82                         csr6 |= DMA_CONTROL_TTC_64;
  83                 else if (txmode <= 128)
  84                         csr6 |= DMA_CONTROL_TTC_128;
  85                 else if (txmode <= 192)
  86                         csr6 |= DMA_CONTROL_TTC_192;
  87                 else
  88                         csr6 |= DMA_CONTROL_TTC_256;
  89         }
  90
  91         if (rxmode == SF_DMA_MODE) {
  92                 CHIP_DBG(KERN_DEBUG "GMAC: enable RX store and forward mode\n");
  93                 csr6 |= DMA_CONTROL_RSF;
  94         } else {
  95                 CHIP_DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode"
  96                               " (threshold = %d)\n", rxmode);
  97                 csr6 &= ~DMA_CONTROL_RSF;
  98                 csr6 &= DMA_CONTROL_TC_RX_MASK;
  99                 if (rxmode <= 32)
 100                         csr6 |= DMA_CONTROL_RTC_32;
 101                 else if (rxmode <= 64)
 102                         csr6 |= DMA_CONTROL_RTC_64;
 103                 else if (rxmode <= 96)
 104                         csr6 |= DMA_CONTROL_RTC_96;
 105                 else
 106                         csr6 |= DMA_CONTROL_RTC_128;
 107         }
 108
 109         writel(csr6, ioaddr + DMA_CONTROL);
 110 }
 111
 112 /* Not yet implemented --- no RMON module */
 113 static void dwmac1000_dma_diagnostic_fr(void *data,
 114                   struct stmmac_extra_stats *x, unsigned long ioaddr)
 115 {
 116         return;
 117 }
 118
 119 static void dwmac1000_dump_dma_regs(unsigned long ioaddr)
 120 {
 121         int i;
 122         pr_info(" DMA registers\n");
 123         for (i = 0; i < 22; i++) {
 124                 if ((i < 9) || (i > 17)) {
 125                         int offset = i * 4;
 126                         pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
 127                                (DMA_BUS_MODE + offset),
 128                                readl(ioaddr + DMA_BUS_MODE + offset));
 129                 }
 130         }
 131 }
 132
 133 struct stmmac_dma_ops dwmac1000_dma_ops = {
 134         .init = dwmac1000_dma_init,
 135         .dump_regs = dwmac1000_dump_dma_regs,
 136         .dma_mode = dwmac1000_dma_operation_mode,
 137         .dma_diagnostic_fr = dwmac1000_dma_diagnostic_fr,
 138         .enable_dma_transmission = dwmac_enable_dma_transmission,
 139         .enable_dma_irq = dwmac_enable_dma_irq,
 140         .disable_dma_irq = dwmac_disable_dma_irq,
 141         .start_tx = dwmac_dma_start_tx,
 142         .stop_tx = dwmac_dma_stop_tx,
 143         .start_rx = dwmac_dma_start_rx,
 144         .stop_rx = dwmac_dma_stop_rx,
 145         .dma_interrupt = dwmac_dma_interrupt,
 146 };