1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
22 * call netif_poll_disable() neither, thus force gem_poll() to keep a spinlock
23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/fcntl.h>
38 #include <linux/interrupt.h>
39 #include <linux/ioport.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <linux/errno.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/mii.h>
52 #include <linux/ethtool.h>
53 #include <linux/crc32.h>
54 #include <linux/random.h>
55 #include <linux/workqueue.h>
56 #include <linux/if_vlan.h>
57 #include <linux/bitops.h>
58 #include <linux/mutex.h>
61 #include <asm/system.h>
63 #include <asm/byteorder.h>
64 #include <asm/uaccess.h>
68 #include <asm/idprom.h>
69 #include <asm/openprom.h>
70 #include <asm/oplib.h>
74 #ifdef CONFIG_PPC_PMAC
75 #include <asm/pci-bridge.h>
77 #include <asm/machdep.h>
78 #include <asm/pmac_feature.h>
81 #include "sungem_phy.h"
84 /* Stripping FCS is causing problems, disabled for now */
87 #define DEFAULT_MSG (NETIF_MSG_DRV | \
91 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
92 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
93 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
95 #define DRV_NAME "sungem"
96 #define DRV_VERSION "0.98"
97 #define DRV_RELDATE "8/24/03"
98 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
100 static char version
[] __devinitdata
=
101 DRV_NAME
".c:v" DRV_VERSION
" " DRV_RELDATE
" " DRV_AUTHOR
"\n";
103 MODULE_AUTHOR(DRV_AUTHOR
);
104 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
105 MODULE_LICENSE("GPL");
107 #define GEM_MODULE_NAME "gem"
108 #define PFX GEM_MODULE_NAME ": "
110 static struct pci_device_id gem_pci_tbl
[] = {
111 { PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_GEM
,
112 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
114 /* These models only differ from the original GEM in
115 * that their tx/rx fifos are of a different size and
116 * they only support 10/100 speeds. -DaveM
118 * Apple's GMAC does support gigabit on machines with
119 * the BCM54xx PHYs. -BenH
121 { PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_RIO_GEM
,
122 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
123 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMAC
,
124 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
125 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMACP
,
126 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
127 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2
,
128 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
129 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_K2_GMAC
,
130 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
131 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_SH_SUNGEM
,
132 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
133 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID2_GMAC
,
134 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
138 MODULE_DEVICE_TABLE(pci
, gem_pci_tbl
);
140 static u16
__phy_read(struct gem
*gp
, int phy_addr
, int reg
)
147 cmd
|= (phy_addr
<< 23) & MIF_FRAME_PHYAD
;
148 cmd
|= (reg
<< 18) & MIF_FRAME_REGAD
;
149 cmd
|= (MIF_FRAME_TAMSB
);
150 writel(cmd
, gp
->regs
+ MIF_FRAME
);
153 cmd
= readl(gp
->regs
+ MIF_FRAME
);
154 if (cmd
& MIF_FRAME_TALSB
)
163 return cmd
& MIF_FRAME_DATA
;
166 static inline int _phy_read(struct net_device
*dev
, int mii_id
, int reg
)
168 struct gem
*gp
= dev
->priv
;
169 return __phy_read(gp
, mii_id
, reg
);
172 static inline u16
phy_read(struct gem
*gp
, int reg
)
174 return __phy_read(gp
, gp
->mii_phy_addr
, reg
);
177 static void __phy_write(struct gem
*gp
, int phy_addr
, int reg
, u16 val
)
184 cmd
|= (phy_addr
<< 23) & MIF_FRAME_PHYAD
;
185 cmd
|= (reg
<< 18) & MIF_FRAME_REGAD
;
186 cmd
|= (MIF_FRAME_TAMSB
);
187 cmd
|= (val
& MIF_FRAME_DATA
);
188 writel(cmd
, gp
->regs
+ MIF_FRAME
);
191 cmd
= readl(gp
->regs
+ MIF_FRAME
);
192 if (cmd
& MIF_FRAME_TALSB
)
199 static inline void _phy_write(struct net_device
*dev
, int mii_id
, int reg
, int val
)
201 struct gem
*gp
= dev
->priv
;
202 __phy_write(gp
, mii_id
, reg
, val
& 0xffff);
205 static inline void phy_write(struct gem
*gp
, int reg
, u16 val
)
207 __phy_write(gp
, gp
->mii_phy_addr
, reg
, val
);
210 static inline void gem_enable_ints(struct gem
*gp
)
212 /* Enable all interrupts but TXDONE */
213 writel(GREG_STAT_TXDONE
, gp
->regs
+ GREG_IMASK
);
216 static inline void gem_disable_ints(struct gem
*gp
)
218 /* Disable all interrupts, including TXDONE */
219 writel(GREG_STAT_NAPI
| GREG_STAT_TXDONE
, gp
->regs
+ GREG_IMASK
);
222 static void gem_get_cell(struct gem
*gp
)
224 BUG_ON(gp
->cell_enabled
< 0);
226 #ifdef CONFIG_PPC_PMAC
227 if (gp
->cell_enabled
== 1) {
229 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, gp
->of_node
, 0, 1);
232 #endif /* CONFIG_PPC_PMAC */
235 /* Turn off the chip's clock */
236 static void gem_put_cell(struct gem
*gp
)
238 BUG_ON(gp
->cell_enabled
<= 0);
240 #ifdef CONFIG_PPC_PMAC
241 if (gp
->cell_enabled
== 0) {
243 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, gp
->of_node
, 0, 0);
246 #endif /* CONFIG_PPC_PMAC */
249 static void gem_handle_mif_event(struct gem
*gp
, u32 reg_val
, u32 changed_bits
)
251 if (netif_msg_intr(gp
))
252 printk(KERN_DEBUG
"%s: mif interrupt\n", gp
->dev
->name
);
255 static int gem_pcs_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
257 u32 pcs_istat
= readl(gp
->regs
+ PCS_ISTAT
);
260 if (netif_msg_intr(gp
))
261 printk(KERN_DEBUG
"%s: pcs interrupt, pcs_istat: 0x%x\n",
262 gp
->dev
->name
, pcs_istat
);
264 if (!(pcs_istat
& PCS_ISTAT_LSC
)) {
265 printk(KERN_ERR
"%s: PCS irq but no link status change???\n",
270 /* The link status bit latches on zero, so you must
271 * read it twice in such a case to see a transition
272 * to the link being up.
274 pcs_miistat
= readl(gp
->regs
+ PCS_MIISTAT
);
275 if (!(pcs_miistat
& PCS_MIISTAT_LS
))
277 (readl(gp
->regs
+ PCS_MIISTAT
) &
280 if (pcs_miistat
& PCS_MIISTAT_ANC
) {
281 /* The remote-fault indication is only valid
282 * when autoneg has completed.
284 if (pcs_miistat
& PCS_MIISTAT_RF
)
285 printk(KERN_INFO
"%s: PCS AutoNEG complete, "
286 "RemoteFault\n", dev
->name
);
288 printk(KERN_INFO
"%s: PCS AutoNEG complete.\n",
292 if (pcs_miistat
& PCS_MIISTAT_LS
) {
293 printk(KERN_INFO
"%s: PCS link is now up.\n",
295 netif_carrier_on(gp
->dev
);
297 printk(KERN_INFO
"%s: PCS link is now down.\n",
299 netif_carrier_off(gp
->dev
);
300 /* If this happens and the link timer is not running,
301 * reset so we re-negotiate.
303 if (!timer_pending(&gp
->link_timer
))
310 static int gem_txmac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
312 u32 txmac_stat
= readl(gp
->regs
+ MAC_TXSTAT
);
314 if (netif_msg_intr(gp
))
315 printk(KERN_DEBUG
"%s: txmac interrupt, txmac_stat: 0x%x\n",
316 gp
->dev
->name
, txmac_stat
);
318 /* Defer timer expiration is quite normal,
319 * don't even log the event.
321 if ((txmac_stat
& MAC_TXSTAT_DTE
) &&
322 !(txmac_stat
& ~MAC_TXSTAT_DTE
))
325 if (txmac_stat
& MAC_TXSTAT_URUN
) {
326 printk(KERN_ERR
"%s: TX MAC xmit underrun.\n",
328 gp
->net_stats
.tx_fifo_errors
++;
331 if (txmac_stat
& MAC_TXSTAT_MPE
) {
332 printk(KERN_ERR
"%s: TX MAC max packet size error.\n",
334 gp
->net_stats
.tx_errors
++;
337 /* The rest are all cases of one of the 16-bit TX
340 if (txmac_stat
& MAC_TXSTAT_NCE
)
341 gp
->net_stats
.collisions
+= 0x10000;
343 if (txmac_stat
& MAC_TXSTAT_ECE
) {
344 gp
->net_stats
.tx_aborted_errors
+= 0x10000;
345 gp
->net_stats
.collisions
+= 0x10000;
348 if (txmac_stat
& MAC_TXSTAT_LCE
) {
349 gp
->net_stats
.tx_aborted_errors
+= 0x10000;
350 gp
->net_stats
.collisions
+= 0x10000;
353 /* We do not keep track of MAC_TXSTAT_FCE and
354 * MAC_TXSTAT_PCE events.
359 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
360 * so we do the following.
362 * If any part of the reset goes wrong, we return 1 and that causes the
363 * whole chip to be reset.
365 static int gem_rxmac_reset(struct gem
*gp
)
367 struct net_device
*dev
= gp
->dev
;
372 /* First, reset & disable MAC RX. */
373 writel(MAC_RXRST_CMD
, gp
->regs
+ MAC_RXRST
);
374 for (limit
= 0; limit
< 5000; limit
++) {
375 if (!(readl(gp
->regs
+ MAC_RXRST
) & MAC_RXRST_CMD
))
380 printk(KERN_ERR
"%s: RX MAC will not reset, resetting whole "
381 "chip.\n", dev
->name
);
385 writel(gp
->mac_rx_cfg
& ~MAC_RXCFG_ENAB
,
386 gp
->regs
+ MAC_RXCFG
);
387 for (limit
= 0; limit
< 5000; limit
++) {
388 if (!(readl(gp
->regs
+ MAC_RXCFG
) & MAC_RXCFG_ENAB
))
393 printk(KERN_ERR
"%s: RX MAC will not disable, resetting whole "
394 "chip.\n", dev
->name
);
398 /* Second, disable RX DMA. */
399 writel(0, gp
->regs
+ RXDMA_CFG
);
400 for (limit
= 0; limit
< 5000; limit
++) {
401 if (!(readl(gp
->regs
+ RXDMA_CFG
) & RXDMA_CFG_ENABLE
))
406 printk(KERN_ERR
"%s: RX DMA will not disable, resetting whole "
407 "chip.\n", dev
->name
);
413 /* Execute RX reset command. */
414 writel(gp
->swrst_base
| GREG_SWRST_RXRST
,
415 gp
->regs
+ GREG_SWRST
);
416 for (limit
= 0; limit
< 5000; limit
++) {
417 if (!(readl(gp
->regs
+ GREG_SWRST
) & GREG_SWRST_RXRST
))
422 printk(KERN_ERR
"%s: RX reset command will not execute, resetting "
423 "whole chip.\n", dev
->name
);
427 /* Refresh the RX ring. */
428 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
429 struct gem_rxd
*rxd
= &gp
->init_block
->rxd
[i
];
431 if (gp
->rx_skbs
[i
] == NULL
) {
432 printk(KERN_ERR
"%s: Parts of RX ring empty, resetting "
433 "whole chip.\n", dev
->name
);
437 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
439 gp
->rx_new
= gp
->rx_old
= 0;
441 /* Now we must reprogram the rest of RX unit. */
442 desc_dma
= (u64
) gp
->gblock_dvma
;
443 desc_dma
+= (INIT_BLOCK_TX_RING_SIZE
* sizeof(struct gem_txd
));
444 writel(desc_dma
>> 32, gp
->regs
+ RXDMA_DBHI
);
445 writel(desc_dma
& 0xffffffff, gp
->regs
+ RXDMA_DBLOW
);
446 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
447 val
= (RXDMA_CFG_BASE
| (RX_OFFSET
<< 10) |
448 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128
);
449 writel(val
, gp
->regs
+ RXDMA_CFG
);
450 if (readl(gp
->regs
+ GREG_BIFCFG
) & GREG_BIFCFG_M66EN
)
451 writel(((5 & RXDMA_BLANK_IPKTS
) |
452 ((8 << 12) & RXDMA_BLANK_ITIME
)),
453 gp
->regs
+ RXDMA_BLANK
);
455 writel(((5 & RXDMA_BLANK_IPKTS
) |
456 ((4 << 12) & RXDMA_BLANK_ITIME
)),
457 gp
->regs
+ RXDMA_BLANK
);
458 val
= (((gp
->rx_pause_off
/ 64) << 0) & RXDMA_PTHRESH_OFF
);
459 val
|= (((gp
->rx_pause_on
/ 64) << 12) & RXDMA_PTHRESH_ON
);
460 writel(val
, gp
->regs
+ RXDMA_PTHRESH
);
461 val
= readl(gp
->regs
+ RXDMA_CFG
);
462 writel(val
| RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
463 writel(MAC_RXSTAT_RCV
, gp
->regs
+ MAC_RXMASK
);
464 val
= readl(gp
->regs
+ MAC_RXCFG
);
465 writel(val
| MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
470 static int gem_rxmac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
472 u32 rxmac_stat
= readl(gp
->regs
+ MAC_RXSTAT
);
475 if (netif_msg_intr(gp
))
476 printk(KERN_DEBUG
"%s: rxmac interrupt, rxmac_stat: 0x%x\n",
477 gp
->dev
->name
, rxmac_stat
);
479 if (rxmac_stat
& MAC_RXSTAT_OFLW
) {
480 u32 smac
= readl(gp
->regs
+ MAC_SMACHINE
);
482 printk(KERN_ERR
"%s: RX MAC fifo overflow smac[%08x].\n",
484 gp
->net_stats
.rx_over_errors
++;
485 gp
->net_stats
.rx_fifo_errors
++;
487 ret
= gem_rxmac_reset(gp
);
490 if (rxmac_stat
& MAC_RXSTAT_ACE
)
491 gp
->net_stats
.rx_frame_errors
+= 0x10000;
493 if (rxmac_stat
& MAC_RXSTAT_CCE
)
494 gp
->net_stats
.rx_crc_errors
+= 0x10000;
496 if (rxmac_stat
& MAC_RXSTAT_LCE
)
497 gp
->net_stats
.rx_length_errors
+= 0x10000;
499 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
505 static int gem_mac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
507 u32 mac_cstat
= readl(gp
->regs
+ MAC_CSTAT
);
509 if (netif_msg_intr(gp
))
510 printk(KERN_DEBUG
"%s: mac interrupt, mac_cstat: 0x%x\n",
511 gp
->dev
->name
, mac_cstat
);
513 /* This interrupt is just for pause frame and pause
514 * tracking. It is useful for diagnostics and debug
515 * but probably by default we will mask these events.
517 if (mac_cstat
& MAC_CSTAT_PS
)
520 if (mac_cstat
& MAC_CSTAT_PRCV
)
521 gp
->pause_last_time_recvd
= (mac_cstat
>> 16);
526 static int gem_mif_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
528 u32 mif_status
= readl(gp
->regs
+ MIF_STATUS
);
529 u32 reg_val
, changed_bits
;
531 reg_val
= (mif_status
& MIF_STATUS_DATA
) >> 16;
532 changed_bits
= (mif_status
& MIF_STATUS_STAT
);
534 gem_handle_mif_event(gp
, reg_val
, changed_bits
);
539 static int gem_pci_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
541 u32 pci_estat
= readl(gp
->regs
+ GREG_PCIESTAT
);
543 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
544 gp
->pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
545 printk(KERN_ERR
"%s: PCI error [%04x] ",
546 dev
->name
, pci_estat
);
548 if (pci_estat
& GREG_PCIESTAT_BADACK
)
549 printk("<No ACK64# during ABS64 cycle> ");
550 if (pci_estat
& GREG_PCIESTAT_DTRTO
)
551 printk("<Delayed transaction timeout> ");
552 if (pci_estat
& GREG_PCIESTAT_OTHER
)
556 pci_estat
|= GREG_PCIESTAT_OTHER
;
557 printk(KERN_ERR
"%s: PCI error\n", dev
->name
);
560 if (pci_estat
& GREG_PCIESTAT_OTHER
) {
563 /* Interrogate PCI config space for the
566 pci_read_config_word(gp
->pdev
, PCI_STATUS
,
568 printk(KERN_ERR
"%s: Read PCI cfg space status [%04x]\n",
569 dev
->name
, pci_cfg_stat
);
570 if (pci_cfg_stat
& PCI_STATUS_PARITY
)
571 printk(KERN_ERR
"%s: PCI parity error detected.\n",
573 if (pci_cfg_stat
& PCI_STATUS_SIG_TARGET_ABORT
)
574 printk(KERN_ERR
"%s: PCI target abort.\n",
576 if (pci_cfg_stat
& PCI_STATUS_REC_TARGET_ABORT
)
577 printk(KERN_ERR
"%s: PCI master acks target abort.\n",
579 if (pci_cfg_stat
& PCI_STATUS_REC_MASTER_ABORT
)
580 printk(KERN_ERR
"%s: PCI master abort.\n",
582 if (pci_cfg_stat
& PCI_STATUS_SIG_SYSTEM_ERROR
)
583 printk(KERN_ERR
"%s: PCI system error SERR#.\n",
585 if (pci_cfg_stat
& PCI_STATUS_DETECTED_PARITY
)
586 printk(KERN_ERR
"%s: PCI parity error.\n",
589 /* Write the error bits back to clear them. */
590 pci_cfg_stat
&= (PCI_STATUS_PARITY
|
591 PCI_STATUS_SIG_TARGET_ABORT
|
592 PCI_STATUS_REC_TARGET_ABORT
|
593 PCI_STATUS_REC_MASTER_ABORT
|
594 PCI_STATUS_SIG_SYSTEM_ERROR
|
595 PCI_STATUS_DETECTED_PARITY
);
596 pci_write_config_word(gp
->pdev
,
597 PCI_STATUS
, pci_cfg_stat
);
600 /* For all PCI errors, we should reset the chip. */
604 /* All non-normal interrupt conditions get serviced here.
605 * Returns non-zero if we should just exit the interrupt
606 * handler right now (ie. if we reset the card which invalidates
607 * all of the other original irq status bits).
609 static int gem_abnormal_irq(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
611 if (gem_status
& GREG_STAT_RXNOBUF
) {
612 /* Frame arrived, no free RX buffers available. */
613 if (netif_msg_rx_err(gp
))
614 printk(KERN_DEBUG
"%s: no buffer for rx frame\n",
616 gp
->net_stats
.rx_dropped
++;
619 if (gem_status
& GREG_STAT_RXTAGERR
) {
620 /* corrupt RX tag framing */
621 if (netif_msg_rx_err(gp
))
622 printk(KERN_DEBUG
"%s: corrupt rx tag framing\n",
624 gp
->net_stats
.rx_errors
++;
629 if (gem_status
& GREG_STAT_PCS
) {
630 if (gem_pcs_interrupt(dev
, gp
, gem_status
))
634 if (gem_status
& GREG_STAT_TXMAC
) {
635 if (gem_txmac_interrupt(dev
, gp
, gem_status
))
639 if (gem_status
& GREG_STAT_RXMAC
) {
640 if (gem_rxmac_interrupt(dev
, gp
, gem_status
))
644 if (gem_status
& GREG_STAT_MAC
) {
645 if (gem_mac_interrupt(dev
, gp
, gem_status
))
649 if (gem_status
& GREG_STAT_MIF
) {
650 if (gem_mif_interrupt(dev
, gp
, gem_status
))
654 if (gem_status
& GREG_STAT_PCIERR
) {
655 if (gem_pci_interrupt(dev
, gp
, gem_status
))
662 gp
->reset_task_pending
= 1;
663 schedule_work(&gp
->reset_task
);
668 static __inline__
void gem_tx(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
672 if (netif_msg_intr(gp
))
673 printk(KERN_DEBUG
"%s: tx interrupt, gem_status: 0x%x\n",
674 gp
->dev
->name
, gem_status
);
677 limit
= ((gem_status
& GREG_STAT_TXNR
) >> GREG_STAT_TXNR_SHIFT
);
678 while (entry
!= limit
) {
685 if (netif_msg_tx_done(gp
))
686 printk(KERN_DEBUG
"%s: tx done, slot %d\n",
687 gp
->dev
->name
, entry
);
688 skb
= gp
->tx_skbs
[entry
];
689 if (skb_shinfo(skb
)->nr_frags
) {
690 int last
= entry
+ skb_shinfo(skb
)->nr_frags
;
694 last
&= (TX_RING_SIZE
- 1);
696 walk
= NEXT_TX(walk
);
705 gp
->tx_skbs
[entry
] = NULL
;
706 gp
->net_stats
.tx_bytes
+= skb
->len
;
708 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
709 txd
= &gp
->init_block
->txd
[entry
];
711 dma_addr
= le64_to_cpu(txd
->buffer
);
712 dma_len
= le64_to_cpu(txd
->control_word
) & TXDCTRL_BUFSZ
;
714 pci_unmap_page(gp
->pdev
, dma_addr
, dma_len
, PCI_DMA_TODEVICE
);
715 entry
= NEXT_TX(entry
);
718 gp
->net_stats
.tx_packets
++;
719 dev_kfree_skb_irq(skb
);
723 if (netif_queue_stopped(dev
) &&
724 TX_BUFFS_AVAIL(gp
) > (MAX_SKB_FRAGS
+ 1))
725 netif_wake_queue(dev
);
728 static __inline__
void gem_post_rxds(struct gem
*gp
, int limit
)
730 int cluster_start
, curr
, count
, kick
;
732 cluster_start
= curr
= (gp
->rx_new
& ~(4 - 1));
736 while (curr
!= limit
) {
737 curr
= NEXT_RX(curr
);
739 struct gem_rxd
*rxd
=
740 &gp
->init_block
->rxd
[cluster_start
];
742 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
744 cluster_start
= NEXT_RX(cluster_start
);
745 if (cluster_start
== curr
)
754 writel(kick
, gp
->regs
+ RXDMA_KICK
);
758 static int gem_rx(struct gem
*gp
, int work_to_do
)
760 int entry
, drops
, work_done
= 0;
763 if (netif_msg_rx_status(gp
))
764 printk(KERN_DEBUG
"%s: rx interrupt, done: %d, rx_new: %d\n",
765 gp
->dev
->name
, readl(gp
->regs
+ RXDMA_DONE
), gp
->rx_new
);
769 done
= readl(gp
->regs
+ RXDMA_DONE
);
771 struct gem_rxd
*rxd
= &gp
->init_block
->rxd
[entry
];
773 u64 status
= cpu_to_le64(rxd
->status_word
);
777 if ((status
& RXDCTRL_OWN
) != 0)
780 if (work_done
>= RX_RING_SIZE
|| work_done
>= work_to_do
)
783 /* When writing back RX descriptor, GEM writes status
784 * then buffer address, possibly in seperate transactions.
785 * If we don't wait for the chip to write both, we could
786 * post a new buffer to this descriptor then have GEM spam
787 * on the buffer address. We sync on the RX completion
788 * register to prevent this from happening.
791 done
= readl(gp
->regs
+ RXDMA_DONE
);
796 /* We can now account for the work we're about to do */
799 skb
= gp
->rx_skbs
[entry
];
801 len
= (status
& RXDCTRL_BUFSZ
) >> 16;
802 if ((len
< ETH_ZLEN
) || (status
& RXDCTRL_BAD
)) {
803 gp
->net_stats
.rx_errors
++;
805 gp
->net_stats
.rx_length_errors
++;
806 if (len
& RXDCTRL_BAD
)
807 gp
->net_stats
.rx_crc_errors
++;
809 /* We'll just return it to GEM. */
811 gp
->net_stats
.rx_dropped
++;
815 dma_addr
= cpu_to_le64(rxd
->buffer
);
816 if (len
> RX_COPY_THRESHOLD
) {
817 struct sk_buff
*new_skb
;
819 new_skb
= gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp
), GFP_ATOMIC
);
820 if (new_skb
== NULL
) {
824 pci_unmap_page(gp
->pdev
, dma_addr
,
825 RX_BUF_ALLOC_SIZE(gp
),
827 gp
->rx_skbs
[entry
] = new_skb
;
828 new_skb
->dev
= gp
->dev
;
829 skb_put(new_skb
, (gp
->rx_buf_sz
+ RX_OFFSET
));
830 rxd
->buffer
= cpu_to_le64(pci_map_page(gp
->pdev
,
831 virt_to_page(new_skb
->data
),
832 offset_in_page(new_skb
->data
),
833 RX_BUF_ALLOC_SIZE(gp
),
834 PCI_DMA_FROMDEVICE
));
835 skb_reserve(new_skb
, RX_OFFSET
);
837 /* Trim the original skb for the netif. */
840 struct sk_buff
*copy_skb
= dev_alloc_skb(len
+ 2);
842 if (copy_skb
== NULL
) {
847 copy_skb
->dev
= gp
->dev
;
848 skb_reserve(copy_skb
, 2);
849 skb_put(copy_skb
, len
);
850 pci_dma_sync_single_for_cpu(gp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
851 memcpy(copy_skb
->data
, skb
->data
, len
);
852 pci_dma_sync_single_for_device(gp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
854 /* We'll reuse the original ring buffer. */
858 skb
->csum
= ntohs((status
& RXDCTRL_TCPCSUM
) ^ 0xffff);
859 skb
->ip_summed
= CHECKSUM_COMPLETE
;
860 skb
->protocol
= eth_type_trans(skb
, gp
->dev
);
862 netif_receive_skb(skb
);
864 gp
->net_stats
.rx_packets
++;
865 gp
->net_stats
.rx_bytes
+= len
;
866 gp
->dev
->last_rx
= jiffies
;
869 entry
= NEXT_RX(entry
);
872 gem_post_rxds(gp
, entry
);
877 printk(KERN_INFO
"%s: Memory squeeze, deferring packet.\n",
883 static int gem_poll(struct net_device
*dev
, int *budget
)
885 struct gem
*gp
= dev
->priv
;
889 * NAPI locking nightmare: See comment at head of driver
891 spin_lock_irqsave(&gp
->lock
, flags
);
894 int work_to_do
, work_done
;
896 /* Handle anomalies */
897 if (gp
->status
& GREG_STAT_ABNORMAL
) {
898 if (gem_abnormal_irq(dev
, gp
, gp
->status
))
902 /* Run TX completion thread */
903 spin_lock(&gp
->tx_lock
);
904 gem_tx(dev
, gp
, gp
->status
);
905 spin_unlock(&gp
->tx_lock
);
907 spin_unlock_irqrestore(&gp
->lock
, flags
);
909 /* Run RX thread. We don't use any locking here,
910 * code willing to do bad things - like cleaning the
911 * rx ring - must call netif_poll_disable(), which
912 * schedule_timeout()'s if polling is already disabled.
914 work_to_do
= min(*budget
, dev
->quota
);
916 work_done
= gem_rx(gp
, work_to_do
);
918 *budget
-= work_done
;
919 dev
->quota
-= work_done
;
921 if (work_done
>= work_to_do
)
924 spin_lock_irqsave(&gp
->lock
, flags
);
926 gp
->status
= readl(gp
->regs
+ GREG_STAT
);
927 } while (gp
->status
& GREG_STAT_NAPI
);
929 __netif_rx_complete(dev
);
932 spin_unlock_irqrestore(&gp
->lock
, flags
);
936 static irqreturn_t
gem_interrupt(int irq
, void *dev_id
)
938 struct net_device
*dev
= dev_id
;
939 struct gem
*gp
= dev
->priv
;
942 /* Swallow interrupts when shutting the chip down, though
943 * that shouldn't happen, we should have done free_irq() at
949 spin_lock_irqsave(&gp
->lock
, flags
);
951 if (netif_rx_schedule_prep(dev
)) {
952 u32 gem_status
= readl(gp
->regs
+ GREG_STAT
);
954 if (gem_status
== 0) {
955 netif_poll_enable(dev
);
956 spin_unlock_irqrestore(&gp
->lock
, flags
);
959 gp
->status
= gem_status
;
960 gem_disable_ints(gp
);
961 __netif_rx_schedule(dev
);
964 spin_unlock_irqrestore(&gp
->lock
, flags
);
966 /* If polling was disabled at the time we received that
967 * interrupt, we may return IRQ_HANDLED here while we
968 * should return IRQ_NONE. No big deal...
973 #ifdef CONFIG_NET_POLL_CONTROLLER
974 static void gem_poll_controller(struct net_device
*dev
)
976 /* gem_interrupt is safe to reentrance so no need
977 * to disable_irq here.
979 gem_interrupt(dev
->irq
, dev
);
983 static void gem_tx_timeout(struct net_device
*dev
)
985 struct gem
*gp
= dev
->priv
;
987 printk(KERN_ERR
"%s: transmit timed out, resetting\n", dev
->name
);
989 printk("%s: hrm.. hw not running !\n", dev
->name
);
992 printk(KERN_ERR
"%s: TX_STATE[%08x:%08x:%08x]\n",
994 readl(gp
->regs
+ TXDMA_CFG
),
995 readl(gp
->regs
+ MAC_TXSTAT
),
996 readl(gp
->regs
+ MAC_TXCFG
));
997 printk(KERN_ERR
"%s: RX_STATE[%08x:%08x:%08x]\n",
999 readl(gp
->regs
+ RXDMA_CFG
),
1000 readl(gp
->regs
+ MAC_RXSTAT
),
1001 readl(gp
->regs
+ MAC_RXCFG
));
1003 spin_lock_irq(&gp
->lock
);
1004 spin_lock(&gp
->tx_lock
);
1006 gp
->reset_task_pending
= 1;
1007 schedule_work(&gp
->reset_task
);
1009 spin_unlock(&gp
->tx_lock
);
1010 spin_unlock_irq(&gp
->lock
);
1013 static __inline__
int gem_intme(int entry
)
1015 /* Algorithm: IRQ every 1/2 of descriptors. */
1016 if (!(entry
& ((TX_RING_SIZE
>>1)-1)))
1022 static int gem_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1024 struct gem
*gp
= dev
->priv
;
1027 unsigned long flags
;
1030 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1031 u64 csum_start_off
, csum_stuff_off
;
1033 csum_start_off
= (u64
) (skb
->h
.raw
- skb
->data
);
1034 csum_stuff_off
= csum_start_off
+ skb
->csum_offset
;
1036 ctrl
= (TXDCTRL_CENAB
|
1037 (csum_start_off
<< 15) |
1038 (csum_stuff_off
<< 21));
1041 local_irq_save(flags
);
1042 if (!spin_trylock(&gp
->tx_lock
)) {
1043 /* Tell upper layer to requeue */
1044 local_irq_restore(flags
);
1045 return NETDEV_TX_LOCKED
;
1047 /* We raced with gem_do_stop() */
1049 spin_unlock_irqrestore(&gp
->tx_lock
, flags
);
1050 return NETDEV_TX_BUSY
;
1053 /* This is a hard error, log it. */
1054 if (TX_BUFFS_AVAIL(gp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
1055 netif_stop_queue(dev
);
1056 spin_unlock_irqrestore(&gp
->tx_lock
, flags
);
1057 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when queue awake!\n",
1059 return NETDEV_TX_BUSY
;
1063 gp
->tx_skbs
[entry
] = skb
;
1065 if (skb_shinfo(skb
)->nr_frags
== 0) {
1066 struct gem_txd
*txd
= &gp
->init_block
->txd
[entry
];
1071 mapping
= pci_map_page(gp
->pdev
,
1072 virt_to_page(skb
->data
),
1073 offset_in_page(skb
->data
),
1074 len
, PCI_DMA_TODEVICE
);
1075 ctrl
|= TXDCTRL_SOF
| TXDCTRL_EOF
| len
;
1076 if (gem_intme(entry
))
1077 ctrl
|= TXDCTRL_INTME
;
1078 txd
->buffer
= cpu_to_le64(mapping
);
1080 txd
->control_word
= cpu_to_le64(ctrl
);
1081 entry
= NEXT_TX(entry
);
1083 struct gem_txd
*txd
;
1086 dma_addr_t first_mapping
;
1087 int frag
, first_entry
= entry
;
1090 if (gem_intme(entry
))
1091 intme
|= TXDCTRL_INTME
;
1093 /* We must give this initial chunk to the device last.
1094 * Otherwise we could race with the device.
1096 first_len
= skb_headlen(skb
);
1097 first_mapping
= pci_map_page(gp
->pdev
, virt_to_page(skb
->data
),
1098 offset_in_page(skb
->data
),
1099 first_len
, PCI_DMA_TODEVICE
);
1100 entry
= NEXT_TX(entry
);
1102 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1103 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1108 len
= this_frag
->size
;
1109 mapping
= pci_map_page(gp
->pdev
,
1111 this_frag
->page_offset
,
1112 len
, PCI_DMA_TODEVICE
);
1114 if (frag
== skb_shinfo(skb
)->nr_frags
- 1)
1115 this_ctrl
|= TXDCTRL_EOF
;
1117 txd
= &gp
->init_block
->txd
[entry
];
1118 txd
->buffer
= cpu_to_le64(mapping
);
1120 txd
->control_word
= cpu_to_le64(this_ctrl
| len
);
1122 if (gem_intme(entry
))
1123 intme
|= TXDCTRL_INTME
;
1125 entry
= NEXT_TX(entry
);
1127 txd
= &gp
->init_block
->txd
[first_entry
];
1128 txd
->buffer
= cpu_to_le64(first_mapping
);
1131 cpu_to_le64(ctrl
| TXDCTRL_SOF
| intme
| first_len
);
1135 if (TX_BUFFS_AVAIL(gp
) <= (MAX_SKB_FRAGS
+ 1))
1136 netif_stop_queue(dev
);
1138 if (netif_msg_tx_queued(gp
))
1139 printk(KERN_DEBUG
"%s: tx queued, slot %d, skblen %d\n",
1140 dev
->name
, entry
, skb
->len
);
1142 writel(gp
->tx_new
, gp
->regs
+ TXDMA_KICK
);
1143 spin_unlock_irqrestore(&gp
->tx_lock
, flags
);
1145 dev
->trans_start
= jiffies
;
1147 return NETDEV_TX_OK
;
1150 #define STOP_TRIES 32
1152 /* Must be invoked under gp->lock and gp->tx_lock. */
1153 static void gem_reset(struct gem
*gp
)
1158 /* Make sure we won't get any more interrupts */
1159 writel(0xffffffff, gp
->regs
+ GREG_IMASK
);
1161 /* Reset the chip */
1162 writel(gp
->swrst_base
| GREG_SWRST_TXRST
| GREG_SWRST_RXRST
,
1163 gp
->regs
+ GREG_SWRST
);
1169 val
= readl(gp
->regs
+ GREG_SWRST
);
1172 } while (val
& (GREG_SWRST_TXRST
| GREG_SWRST_RXRST
));
1175 printk(KERN_ERR
"%s: SW reset is ghetto.\n", gp
->dev
->name
);
1178 /* Must be invoked under gp->lock and gp->tx_lock. */
1179 static void gem_start_dma(struct gem
*gp
)
1183 /* We are ready to rock, turn everything on. */
1184 val
= readl(gp
->regs
+ TXDMA_CFG
);
1185 writel(val
| TXDMA_CFG_ENABLE
, gp
->regs
+ TXDMA_CFG
);
1186 val
= readl(gp
->regs
+ RXDMA_CFG
);
1187 writel(val
| RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
1188 val
= readl(gp
->regs
+ MAC_TXCFG
);
1189 writel(val
| MAC_TXCFG_ENAB
, gp
->regs
+ MAC_TXCFG
);
1190 val
= readl(gp
->regs
+ MAC_RXCFG
);
1191 writel(val
| MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
1193 (void) readl(gp
->regs
+ MAC_RXCFG
);
1196 gem_enable_ints(gp
);
1198 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
1201 /* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1202 * actually stopped before about 4ms tho ...
1204 static void gem_stop_dma(struct gem
*gp
)
1208 /* We are done rocking, turn everything off. */
1209 val
= readl(gp
->regs
+ TXDMA_CFG
);
1210 writel(val
& ~TXDMA_CFG_ENABLE
, gp
->regs
+ TXDMA_CFG
);
1211 val
= readl(gp
->regs
+ RXDMA_CFG
);
1212 writel(val
& ~RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
1213 val
= readl(gp
->regs
+ MAC_TXCFG
);
1214 writel(val
& ~MAC_TXCFG_ENAB
, gp
->regs
+ MAC_TXCFG
);
1215 val
= readl(gp
->regs
+ MAC_RXCFG
);
1216 writel(val
& ~MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
1218 (void) readl(gp
->regs
+ MAC_RXCFG
);
1220 /* Need to wait a bit ... done by the caller */
1224 /* Must be invoked under gp->lock and gp->tx_lock. */
1225 // XXX dbl check what that function should do when called on PCS PHY
1226 static void gem_begin_auto_negotiation(struct gem
*gp
, struct ethtool_cmd
*ep
)
1228 u32 advertise
, features
;
1233 if (gp
->phy_type
!= phy_mii_mdio0
&&
1234 gp
->phy_type
!= phy_mii_mdio1
)
1237 /* Setup advertise */
1238 if (found_mii_phy(gp
))
1239 features
= gp
->phy_mii
.def
->features
;
1243 advertise
= features
& ADVERTISE_MASK
;
1244 if (gp
->phy_mii
.advertising
!= 0)
1245 advertise
&= gp
->phy_mii
.advertising
;
1247 autoneg
= gp
->want_autoneg
;
1248 speed
= gp
->phy_mii
.speed
;
1249 duplex
= gp
->phy_mii
.duplex
;
1251 /* Setup link parameters */
1254 if (ep
->autoneg
== AUTONEG_ENABLE
) {
1255 advertise
= ep
->advertising
;
1260 duplex
= ep
->duplex
;
1264 /* Sanitize settings based on PHY capabilities */
1265 if ((features
& SUPPORTED_Autoneg
) == 0)
1267 if (speed
== SPEED_1000
&&
1268 !(features
& (SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full
)))
1270 if (speed
== SPEED_100
&&
1271 !(features
& (SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
)))
1273 if (duplex
== DUPLEX_FULL
&&
1274 !(features
& (SUPPORTED_1000baseT_Full
|
1275 SUPPORTED_100baseT_Full
|
1276 SUPPORTED_10baseT_Full
)))
1277 duplex
= DUPLEX_HALF
;
1281 /* If we are asleep, we don't try to actually setup the PHY, we
1282 * just store the settings
1285 gp
->phy_mii
.autoneg
= gp
->want_autoneg
= autoneg
;
1286 gp
->phy_mii
.speed
= speed
;
1287 gp
->phy_mii
.duplex
= duplex
;
1291 /* Configure PHY & start aneg */
1292 gp
->want_autoneg
= autoneg
;
1294 if (found_mii_phy(gp
))
1295 gp
->phy_mii
.def
->ops
->setup_aneg(&gp
->phy_mii
, advertise
);
1296 gp
->lstate
= link_aneg
;
1298 if (found_mii_phy(gp
))
1299 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, speed
, duplex
);
1300 gp
->lstate
= link_force_ok
;
1304 gp
->timer_ticks
= 0;
1305 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
1308 /* A link-up condition has occurred, initialize and enable the
1311 * Must be invoked under gp->lock and gp->tx_lock.
1313 static int gem_set_link_modes(struct gem
*gp
)
1316 int full_duplex
, speed
, pause
;
1322 if (found_mii_phy(gp
)) {
1323 if (gp
->phy_mii
.def
->ops
->read_link(&gp
->phy_mii
))
1325 full_duplex
= (gp
->phy_mii
.duplex
== DUPLEX_FULL
);
1326 speed
= gp
->phy_mii
.speed
;
1327 pause
= gp
->phy_mii
.pause
;
1328 } else if (gp
->phy_type
== phy_serialink
||
1329 gp
->phy_type
== phy_serdes
) {
1330 u32 pcs_lpa
= readl(gp
->regs
+ PCS_MIILP
);
1332 if (pcs_lpa
& PCS_MIIADV_FD
)
1337 if (netif_msg_link(gp
))
1338 printk(KERN_INFO
"%s: Link is up at %d Mbps, %s-duplex.\n",
1339 gp
->dev
->name
, speed
, (full_duplex
? "full" : "half"));
1344 val
= (MAC_TXCFG_EIPG0
| MAC_TXCFG_NGU
);
1346 val
|= (MAC_TXCFG_ICS
| MAC_TXCFG_ICOLL
);
1348 /* MAC_TXCFG_NBO must be zero. */
1350 writel(val
, gp
->regs
+ MAC_TXCFG
);
1352 val
= (MAC_XIFCFG_OE
| MAC_XIFCFG_LLED
);
1354 (gp
->phy_type
== phy_mii_mdio0
||
1355 gp
->phy_type
== phy_mii_mdio1
)) {
1356 val
|= MAC_XIFCFG_DISE
;
1357 } else if (full_duplex
) {
1358 val
|= MAC_XIFCFG_FLED
;
1361 if (speed
== SPEED_1000
)
1362 val
|= (MAC_XIFCFG_GMII
);
1364 writel(val
, gp
->regs
+ MAC_XIFCFG
);
1366 /* If gigabit and half-duplex, enable carrier extension
1367 * mode. Else, disable it.
1369 if (speed
== SPEED_1000
&& !full_duplex
) {
1370 val
= readl(gp
->regs
+ MAC_TXCFG
);
1371 writel(val
| MAC_TXCFG_TCE
, gp
->regs
+ MAC_TXCFG
);
1373 val
= readl(gp
->regs
+ MAC_RXCFG
);
1374 writel(val
| MAC_RXCFG_RCE
, gp
->regs
+ MAC_RXCFG
);
1376 val
= readl(gp
->regs
+ MAC_TXCFG
);
1377 writel(val
& ~MAC_TXCFG_TCE
, gp
->regs
+ MAC_TXCFG
);
1379 val
= readl(gp
->regs
+ MAC_RXCFG
);
1380 writel(val
& ~MAC_RXCFG_RCE
, gp
->regs
+ MAC_RXCFG
);
1383 if (gp
->phy_type
== phy_serialink
||
1384 gp
->phy_type
== phy_serdes
) {
1385 u32 pcs_lpa
= readl(gp
->regs
+ PCS_MIILP
);
1387 if (pcs_lpa
& (PCS_MIIADV_SP
| PCS_MIIADV_AP
))
1391 if (netif_msg_link(gp
)) {
1393 printk(KERN_INFO
"%s: Pause is enabled "
1394 "(rxfifo: %d off: %d on: %d)\n",
1400 printk(KERN_INFO
"%s: Pause is disabled\n",
1406 writel(512, gp
->regs
+ MAC_STIME
);
1408 writel(64, gp
->regs
+ MAC_STIME
);
1409 val
= readl(gp
->regs
+ MAC_MCCFG
);
1411 val
|= (MAC_MCCFG_SPE
| MAC_MCCFG_RPE
);
1413 val
&= ~(MAC_MCCFG_SPE
| MAC_MCCFG_RPE
);
1414 writel(val
, gp
->regs
+ MAC_MCCFG
);
1421 /* Must be invoked under gp->lock and gp->tx_lock. */
1422 static int gem_mdio_link_not_up(struct gem
*gp
)
1424 switch (gp
->lstate
) {
1425 case link_force_ret
:
1426 if (netif_msg_link(gp
))
1427 printk(KERN_INFO
"%s: Autoneg failed again, keeping"
1428 " forced mode\n", gp
->dev
->name
);
1429 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
,
1430 gp
->last_forced_speed
, DUPLEX_HALF
);
1431 gp
->timer_ticks
= 5;
1432 gp
->lstate
= link_force_ok
;
1435 /* We try forced modes after a failed aneg only on PHYs that don't
1436 * have "magic_aneg" bit set, which means they internally do the
1437 * while forced-mode thingy. On these, we just restart aneg
1439 if (gp
->phy_mii
.def
->magic_aneg
)
1441 if (netif_msg_link(gp
))
1442 printk(KERN_INFO
"%s: switching to forced 100bt\n",
1444 /* Try forced modes. */
1445 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, SPEED_100
,
1447 gp
->timer_ticks
= 5;
1448 gp
->lstate
= link_force_try
;
1450 case link_force_try
:
1451 /* Downgrade from 100 to 10 Mbps if necessary.
1452 * If already at 10Mbps, warn user about the
1453 * situation every 10 ticks.
1455 if (gp
->phy_mii
.speed
== SPEED_100
) {
1456 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, SPEED_10
,
1458 gp
->timer_ticks
= 5;
1459 if (netif_msg_link(gp
))
1460 printk(KERN_INFO
"%s: switching to forced 10bt\n",
1470 static void gem_link_timer(unsigned long data
)
1472 struct gem
*gp
= (struct gem
*) data
;
1473 int restart_aneg
= 0;
1478 spin_lock_irq(&gp
->lock
);
1479 spin_lock(&gp
->tx_lock
);
1482 /* If the reset task is still pending, we just
1483 * reschedule the link timer
1485 if (gp
->reset_task_pending
)
1488 if (gp
->phy_type
== phy_serialink
||
1489 gp
->phy_type
== phy_serdes
) {
1490 u32 val
= readl(gp
->regs
+ PCS_MIISTAT
);
1492 if (!(val
& PCS_MIISTAT_LS
))
1493 val
= readl(gp
->regs
+ PCS_MIISTAT
);
1495 if ((val
& PCS_MIISTAT_LS
) != 0) {
1496 gp
->lstate
= link_up
;
1497 netif_carrier_on(gp
->dev
);
1498 (void)gem_set_link_modes(gp
);
1502 if (found_mii_phy(gp
) && gp
->phy_mii
.def
->ops
->poll_link(&gp
->phy_mii
)) {
1503 /* Ok, here we got a link. If we had it due to a forced
1504 * fallback, and we were configured for autoneg, we do
1505 * retry a short autoneg pass. If you know your hub is
1506 * broken, use ethtool ;)
1508 if (gp
->lstate
== link_force_try
&& gp
->want_autoneg
) {
1509 gp
->lstate
= link_force_ret
;
1510 gp
->last_forced_speed
= gp
->phy_mii
.speed
;
1511 gp
->timer_ticks
= 5;
1512 if (netif_msg_link(gp
))
1513 printk(KERN_INFO
"%s: Got link after fallback, retrying"
1514 " autoneg once...\n", gp
->dev
->name
);
1515 gp
->phy_mii
.def
->ops
->setup_aneg(&gp
->phy_mii
, gp
->phy_mii
.advertising
);
1516 } else if (gp
->lstate
!= link_up
) {
1517 gp
->lstate
= link_up
;
1518 netif_carrier_on(gp
->dev
);
1519 if (gem_set_link_modes(gp
))
1523 /* If the link was previously up, we restart the
1526 if (gp
->lstate
== link_up
) {
1527 gp
->lstate
= link_down
;
1528 if (netif_msg_link(gp
))
1529 printk(KERN_INFO
"%s: Link down\n",
1531 netif_carrier_off(gp
->dev
);
1532 gp
->reset_task_pending
= 1;
1533 schedule_work(&gp
->reset_task
);
1535 } else if (++gp
->timer_ticks
> 10) {
1536 if (found_mii_phy(gp
))
1537 restart_aneg
= gem_mdio_link_not_up(gp
);
1543 gem_begin_auto_negotiation(gp
, NULL
);
1547 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
1550 spin_unlock(&gp
->tx_lock
);
1551 spin_unlock_irq(&gp
->lock
);
1554 /* Must be invoked under gp->lock and gp->tx_lock. */
1555 static void gem_clean_rings(struct gem
*gp
)
1557 struct gem_init_block
*gb
= gp
->init_block
;
1558 struct sk_buff
*skb
;
1560 dma_addr_t dma_addr
;
1562 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1563 struct gem_rxd
*rxd
;
1566 if (gp
->rx_skbs
[i
] != NULL
) {
1567 skb
= gp
->rx_skbs
[i
];
1568 dma_addr
= le64_to_cpu(rxd
->buffer
);
1569 pci_unmap_page(gp
->pdev
, dma_addr
,
1570 RX_BUF_ALLOC_SIZE(gp
),
1571 PCI_DMA_FROMDEVICE
);
1572 dev_kfree_skb_any(skb
);
1573 gp
->rx_skbs
[i
] = NULL
;
1575 rxd
->status_word
= 0;
1580 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1581 if (gp
->tx_skbs
[i
] != NULL
) {
1582 struct gem_txd
*txd
;
1585 skb
= gp
->tx_skbs
[i
];
1586 gp
->tx_skbs
[i
] = NULL
;
1588 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
1589 int ent
= i
& (TX_RING_SIZE
- 1);
1591 txd
= &gb
->txd
[ent
];
1592 dma_addr
= le64_to_cpu(txd
->buffer
);
1593 pci_unmap_page(gp
->pdev
, dma_addr
,
1594 le64_to_cpu(txd
->control_word
) &
1595 TXDCTRL_BUFSZ
, PCI_DMA_TODEVICE
);
1597 if (frag
!= skb_shinfo(skb
)->nr_frags
)
1600 dev_kfree_skb_any(skb
);
1605 /* Must be invoked under gp->lock and gp->tx_lock. */
1606 static void gem_init_rings(struct gem
*gp
)
1608 struct gem_init_block
*gb
= gp
->init_block
;
1609 struct net_device
*dev
= gp
->dev
;
1611 dma_addr_t dma_addr
;
1613 gp
->rx_new
= gp
->rx_old
= gp
->tx_new
= gp
->tx_old
= 0;
1615 gem_clean_rings(gp
);
1617 gp
->rx_buf_sz
= max(dev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
,
1618 (unsigned)VLAN_ETH_FRAME_LEN
);
1620 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1621 struct sk_buff
*skb
;
1622 struct gem_rxd
*rxd
= &gb
->rxd
[i
];
1624 skb
= gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp
), GFP_ATOMIC
);
1627 rxd
->status_word
= 0;
1631 gp
->rx_skbs
[i
] = skb
;
1633 skb_put(skb
, (gp
->rx_buf_sz
+ RX_OFFSET
));
1634 dma_addr
= pci_map_page(gp
->pdev
,
1635 virt_to_page(skb
->data
),
1636 offset_in_page(skb
->data
),
1637 RX_BUF_ALLOC_SIZE(gp
),
1638 PCI_DMA_FROMDEVICE
);
1639 rxd
->buffer
= cpu_to_le64(dma_addr
);
1641 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
1642 skb_reserve(skb
, RX_OFFSET
);
1645 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1646 struct gem_txd
*txd
= &gb
->txd
[i
];
1648 txd
->control_word
= 0;
1655 /* Init PHY interface and start link poll state machine */
1656 static void gem_init_phy(struct gem
*gp
)
1660 /* Revert MIF CFG setting done on stop_phy */
1661 mifcfg
= readl(gp
->regs
+ MIF_CFG
);
1662 mifcfg
&= ~MIF_CFG_BBMODE
;
1663 writel(mifcfg
, gp
->regs
+ MIF_CFG
);
1665 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_APPLE
) {
1668 /* Those delay sucks, the HW seem to love them though, I'll
1669 * serisouly consider breaking some locks here to be able
1670 * to schedule instead
1672 for (i
= 0; i
< 3; i
++) {
1673 #ifdef CONFIG_PPC_PMAC
1674 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET
, gp
->of_node
, 0, 0);
1677 /* Some PHYs used by apple have problem getting back to us,
1678 * we do an additional reset here
1680 phy_write(gp
, MII_BMCR
, BMCR_RESET
);
1682 if (phy_read(gp
, MII_BMCR
) != 0xffff)
1685 printk(KERN_WARNING
"%s: GMAC PHY not responding !\n",
1690 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
1691 gp
->pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
1694 /* Init datapath mode register. */
1695 if (gp
->phy_type
== phy_mii_mdio0
||
1696 gp
->phy_type
== phy_mii_mdio1
) {
1697 val
= PCS_DMODE_MGM
;
1698 } else if (gp
->phy_type
== phy_serialink
) {
1699 val
= PCS_DMODE_SM
| PCS_DMODE_GMOE
;
1701 val
= PCS_DMODE_ESM
;
1704 writel(val
, gp
->regs
+ PCS_DMODE
);
1707 if (gp
->phy_type
== phy_mii_mdio0
||
1708 gp
->phy_type
== phy_mii_mdio1
) {
1709 // XXX check for errors
1710 mii_phy_probe(&gp
->phy_mii
, gp
->mii_phy_addr
);
1713 if (gp
->phy_mii
.def
&& gp
->phy_mii
.def
->ops
->init
)
1714 gp
->phy_mii
.def
->ops
->init(&gp
->phy_mii
);
1719 /* Reset PCS unit. */
1720 val
= readl(gp
->regs
+ PCS_MIICTRL
);
1721 val
|= PCS_MIICTRL_RST
;
1722 writeb(val
, gp
->regs
+ PCS_MIICTRL
);
1725 while (readl(gp
->regs
+ PCS_MIICTRL
) & PCS_MIICTRL_RST
) {
1731 printk(KERN_WARNING
"%s: PCS reset bit would not clear.\n",
1734 /* Make sure PCS is disabled while changing advertisement
1737 val
= readl(gp
->regs
+ PCS_CFG
);
1738 val
&= ~(PCS_CFG_ENABLE
| PCS_CFG_TO
);
1739 writel(val
, gp
->regs
+ PCS_CFG
);
1741 /* Advertise all capabilities except assymetric
1744 val
= readl(gp
->regs
+ PCS_MIIADV
);
1745 val
|= (PCS_MIIADV_FD
| PCS_MIIADV_HD
|
1746 PCS_MIIADV_SP
| PCS_MIIADV_AP
);
1747 writel(val
, gp
->regs
+ PCS_MIIADV
);
1749 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1750 * and re-enable PCS.
1752 val
= readl(gp
->regs
+ PCS_MIICTRL
);
1753 val
|= (PCS_MIICTRL_RAN
| PCS_MIICTRL_ANE
);
1754 val
&= ~PCS_MIICTRL_WB
;
1755 writel(val
, gp
->regs
+ PCS_MIICTRL
);
1757 val
= readl(gp
->regs
+ PCS_CFG
);
1758 val
|= PCS_CFG_ENABLE
;
1759 writel(val
, gp
->regs
+ PCS_CFG
);
1761 /* Make sure serialink loopback is off. The meaning
1762 * of this bit is logically inverted based upon whether
1763 * you are in Serialink or SERDES mode.
1765 val
= readl(gp
->regs
+ PCS_SCTRL
);
1766 if (gp
->phy_type
== phy_serialink
)
1767 val
&= ~PCS_SCTRL_LOOP
;
1769 val
|= PCS_SCTRL_LOOP
;
1770 writel(val
, gp
->regs
+ PCS_SCTRL
);
1773 /* Default aneg parameters */
1774 gp
->timer_ticks
= 0;
1775 gp
->lstate
= link_down
;
1776 netif_carrier_off(gp
->dev
);
1778 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1779 spin_lock_irq(&gp
->lock
);
1780 gem_begin_auto_negotiation(gp
, NULL
);
1781 spin_unlock_irq(&gp
->lock
);
1784 /* Must be invoked under gp->lock and gp->tx_lock. */
1785 static void gem_init_dma(struct gem
*gp
)
1787 u64 desc_dma
= (u64
) gp
->gblock_dvma
;
1790 val
= (TXDMA_CFG_BASE
| (0x7ff << 10) | TXDMA_CFG_PMODE
);
1791 writel(val
, gp
->regs
+ TXDMA_CFG
);
1793 writel(desc_dma
>> 32, gp
->regs
+ TXDMA_DBHI
);
1794 writel(desc_dma
& 0xffffffff, gp
->regs
+ TXDMA_DBLOW
);
1795 desc_dma
+= (INIT_BLOCK_TX_RING_SIZE
* sizeof(struct gem_txd
));
1797 writel(0, gp
->regs
+ TXDMA_KICK
);
1799 val
= (RXDMA_CFG_BASE
| (RX_OFFSET
<< 10) |
1800 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128
);
1801 writel(val
, gp
->regs
+ RXDMA_CFG
);
1803 writel(desc_dma
>> 32, gp
->regs
+ RXDMA_DBHI
);
1804 writel(desc_dma
& 0xffffffff, gp
->regs
+ RXDMA_DBLOW
);
1806 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
1808 val
= (((gp
->rx_pause_off
/ 64) << 0) & RXDMA_PTHRESH_OFF
);
1809 val
|= (((gp
->rx_pause_on
/ 64) << 12) & RXDMA_PTHRESH_ON
);
1810 writel(val
, gp
->regs
+ RXDMA_PTHRESH
);
1812 if (readl(gp
->regs
+ GREG_BIFCFG
) & GREG_BIFCFG_M66EN
)
1813 writel(((5 & RXDMA_BLANK_IPKTS
) |
1814 ((8 << 12) & RXDMA_BLANK_ITIME
)),
1815 gp
->regs
+ RXDMA_BLANK
);
1817 writel(((5 & RXDMA_BLANK_IPKTS
) |
1818 ((4 << 12) & RXDMA_BLANK_ITIME
)),
1819 gp
->regs
+ RXDMA_BLANK
);
1822 /* Must be invoked under gp->lock and gp->tx_lock. */
1823 static u32
gem_setup_multicast(struct gem
*gp
)
1828 if ((gp
->dev
->flags
& IFF_ALLMULTI
) ||
1829 (gp
->dev
->mc_count
> 256)) {
1830 for (i
=0; i
<16; i
++)
1831 writel(0xffff, gp
->regs
+ MAC_HASH0
+ (i
<< 2));
1832 rxcfg
|= MAC_RXCFG_HFE
;
1833 } else if (gp
->dev
->flags
& IFF_PROMISC
) {
1834 rxcfg
|= MAC_RXCFG_PROM
;
1838 struct dev_mc_list
*dmi
= gp
->dev
->mc_list
;
1841 for (i
= 0; i
< 16; i
++)
1844 for (i
= 0; i
< gp
->dev
->mc_count
; i
++) {
1845 char *addrs
= dmi
->dmi_addr
;
1852 crc
= ether_crc_le(6, addrs
);
1854 hash_table
[crc
>> 4] |= 1 << (15 - (crc
& 0xf));
1856 for (i
=0; i
<16; i
++)
1857 writel(hash_table
[i
], gp
->regs
+ MAC_HASH0
+ (i
<< 2));
1858 rxcfg
|= MAC_RXCFG_HFE
;
1864 /* Must be invoked under gp->lock and gp->tx_lock. */
1865 static void gem_init_mac(struct gem
*gp
)
1867 unsigned char *e
= &gp
->dev
->dev_addr
[0];
1869 writel(0x1bf0, gp
->regs
+ MAC_SNDPAUSE
);
1871 writel(0x00, gp
->regs
+ MAC_IPG0
);
1872 writel(0x08, gp
->regs
+ MAC_IPG1
);
1873 writel(0x04, gp
->regs
+ MAC_IPG2
);
1874 writel(0x40, gp
->regs
+ MAC_STIME
);
1875 writel(0x40, gp
->regs
+ MAC_MINFSZ
);
1877 /* Ethernet payload + header + FCS + optional VLAN tag. */
1878 writel(0x20000000 | (gp
->rx_buf_sz
+ 4), gp
->regs
+ MAC_MAXFSZ
);
1880 writel(0x07, gp
->regs
+ MAC_PASIZE
);
1881 writel(0x04, gp
->regs
+ MAC_JAMSIZE
);
1882 writel(0x10, gp
->regs
+ MAC_ATTLIM
);
1883 writel(0x8808, gp
->regs
+ MAC_MCTYPE
);
1885 writel((e
[5] | (e
[4] << 8)) & 0x3ff, gp
->regs
+ MAC_RANDSEED
);
1887 writel((e
[4] << 8) | e
[5], gp
->regs
+ MAC_ADDR0
);
1888 writel((e
[2] << 8) | e
[3], gp
->regs
+ MAC_ADDR1
);
1889 writel((e
[0] << 8) | e
[1], gp
->regs
+ MAC_ADDR2
);
1891 writel(0, gp
->regs
+ MAC_ADDR3
);
1892 writel(0, gp
->regs
+ MAC_ADDR4
);
1893 writel(0, gp
->regs
+ MAC_ADDR5
);
1895 writel(0x0001, gp
->regs
+ MAC_ADDR6
);
1896 writel(0xc200, gp
->regs
+ MAC_ADDR7
);
1897 writel(0x0180, gp
->regs
+ MAC_ADDR8
);
1899 writel(0, gp
->regs
+ MAC_AFILT0
);
1900 writel(0, gp
->regs
+ MAC_AFILT1
);
1901 writel(0, gp
->regs
+ MAC_AFILT2
);
1902 writel(0, gp
->regs
+ MAC_AF21MSK
);
1903 writel(0, gp
->regs
+ MAC_AF0MSK
);
1905 gp
->mac_rx_cfg
= gem_setup_multicast(gp
);
1907 gp
->mac_rx_cfg
|= MAC_RXCFG_SFCS
;
1909 writel(0, gp
->regs
+ MAC_NCOLL
);
1910 writel(0, gp
->regs
+ MAC_FASUCC
);
1911 writel(0, gp
->regs
+ MAC_ECOLL
);
1912 writel(0, gp
->regs
+ MAC_LCOLL
);
1913 writel(0, gp
->regs
+ MAC_DTIMER
);
1914 writel(0, gp
->regs
+ MAC_PATMPS
);
1915 writel(0, gp
->regs
+ MAC_RFCTR
);
1916 writel(0, gp
->regs
+ MAC_LERR
);
1917 writel(0, gp
->regs
+ MAC_AERR
);
1918 writel(0, gp
->regs
+ MAC_FCSERR
);
1919 writel(0, gp
->regs
+ MAC_RXCVERR
);
1921 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1922 * them once a link is established.
1924 writel(0, gp
->regs
+ MAC_TXCFG
);
1925 writel(gp
->mac_rx_cfg
, gp
->regs
+ MAC_RXCFG
);
1926 writel(0, gp
->regs
+ MAC_MCCFG
);
1927 writel(0, gp
->regs
+ MAC_XIFCFG
);
1929 /* Setup MAC interrupts. We want to get all of the interesting
1930 * counter expiration events, but we do not want to hear about
1931 * normal rx/tx as the DMA engine tells us that.
1933 writel(MAC_TXSTAT_XMIT
, gp
->regs
+ MAC_TXMASK
);
1934 writel(MAC_RXSTAT_RCV
, gp
->regs
+ MAC_RXMASK
);
1936 /* Don't enable even the PAUSE interrupts for now, we
1937 * make no use of those events other than to record them.
1939 writel(0xffffffff, gp
->regs
+ MAC_MCMASK
);
1941 /* Don't enable GEM's WOL in normal operations
1944 writel(0, gp
->regs
+ WOL_WAKECSR
);
1947 /* Must be invoked under gp->lock and gp->tx_lock. */
1948 static void gem_init_pause_thresholds(struct gem
*gp
)
1952 /* Calculate pause thresholds. Setting the OFF threshold to the
1953 * full RX fifo size effectively disables PAUSE generation which
1954 * is what we do for 10/100 only GEMs which have FIFOs too small
1955 * to make real gains from PAUSE.
1957 if (gp
->rx_fifo_sz
<= (2 * 1024)) {
1958 gp
->rx_pause_off
= gp
->rx_pause_on
= gp
->rx_fifo_sz
;
1960 int max_frame
= (gp
->rx_buf_sz
+ 4 + 64) & ~63;
1961 int off
= (gp
->rx_fifo_sz
- (max_frame
* 2));
1962 int on
= off
- max_frame
;
1964 gp
->rx_pause_off
= off
;
1965 gp
->rx_pause_on
= on
;
1969 /* Configure the chip "burst" DMA mode & enable some
1970 * HW bug fixes on Apple version
1973 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_APPLE
)
1974 cfg
|= GREG_CFG_RONPAULBIT
| GREG_CFG_ENBUG2FIX
;
1975 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1976 cfg
|= GREG_CFG_IBURST
;
1978 cfg
|= ((31 << 1) & GREG_CFG_TXDMALIM
);
1979 cfg
|= ((31 << 6) & GREG_CFG_RXDMALIM
);
1980 writel(cfg
, gp
->regs
+ GREG_CFG
);
1982 /* If Infinite Burst didn't stick, then use different
1983 * thresholds (and Apple bug fixes don't exist)
1985 if (!(readl(gp
->regs
+ GREG_CFG
) & GREG_CFG_IBURST
)) {
1986 cfg
= ((2 << 1) & GREG_CFG_TXDMALIM
);
1987 cfg
|= ((8 << 6) & GREG_CFG_RXDMALIM
);
1988 writel(cfg
, gp
->regs
+ GREG_CFG
);
1992 static int gem_check_invariants(struct gem
*gp
)
1994 struct pci_dev
*pdev
= gp
->pdev
;
1997 /* On Apple's sungem, we can't rely on registers as the chip
1998 * was been powered down by the firmware. The PHY is looked
2001 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
) {
2002 gp
->phy_type
= phy_mii_mdio0
;
2003 gp
->tx_fifo_sz
= readl(gp
->regs
+ TXDMA_FSZ
) * 64;
2004 gp
->rx_fifo_sz
= readl(gp
->regs
+ RXDMA_FSZ
) * 64;
2007 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
2008 mif_cfg
&= ~(MIF_CFG_PSELECT
|MIF_CFG_POLL
|MIF_CFG_BBMODE
|MIF_CFG_MDI1
);
2009 mif_cfg
|= MIF_CFG_MDI0
;
2010 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2011 writel(PCS_DMODE_MGM
, gp
->regs
+ PCS_DMODE
);
2012 writel(MAC_XIFCFG_OE
, gp
->regs
+ MAC_XIFCFG
);
2014 /* We hard-code the PHY address so we can properly bring it out of
2015 * reset later on, we can't really probe it at this point, though
2016 * that isn't an issue.
2018 if (gp
->pdev
->device
== PCI_DEVICE_ID_APPLE_K2_GMAC
)
2019 gp
->mii_phy_addr
= 1;
2021 gp
->mii_phy_addr
= 0;
2026 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
2028 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
2029 pdev
->device
== PCI_DEVICE_ID_SUN_RIO_GEM
) {
2030 /* One of the MII PHYs _must_ be present
2031 * as this chip has no gigabit PHY.
2033 if ((mif_cfg
& (MIF_CFG_MDI0
| MIF_CFG_MDI1
)) == 0) {
2034 printk(KERN_ERR PFX
"RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2040 /* Determine initial PHY interface type guess. MDIO1 is the
2041 * external PHY and thus takes precedence over MDIO0.
2044 if (mif_cfg
& MIF_CFG_MDI1
) {
2045 gp
->phy_type
= phy_mii_mdio1
;
2046 mif_cfg
|= MIF_CFG_PSELECT
;
2047 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2048 } else if (mif_cfg
& MIF_CFG_MDI0
) {
2049 gp
->phy_type
= phy_mii_mdio0
;
2050 mif_cfg
&= ~MIF_CFG_PSELECT
;
2051 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2053 gp
->phy_type
= phy_serialink
;
2055 if (gp
->phy_type
== phy_mii_mdio1
||
2056 gp
->phy_type
== phy_mii_mdio0
) {
2059 for (i
= 0; i
< 32; i
++) {
2060 gp
->mii_phy_addr
= i
;
2061 if (phy_read(gp
, MII_BMCR
) != 0xffff)
2065 if (pdev
->device
!= PCI_DEVICE_ID_SUN_GEM
) {
2066 printk(KERN_ERR PFX
"RIO MII phy will not respond.\n");
2069 gp
->phy_type
= phy_serdes
;
2073 /* Fetch the FIFO configurations now too. */
2074 gp
->tx_fifo_sz
= readl(gp
->regs
+ TXDMA_FSZ
) * 64;
2075 gp
->rx_fifo_sz
= readl(gp
->regs
+ RXDMA_FSZ
) * 64;
2077 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
) {
2078 if (pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
2079 if (gp
->tx_fifo_sz
!= (9 * 1024) ||
2080 gp
->rx_fifo_sz
!= (20 * 1024)) {
2081 printk(KERN_ERR PFX
"GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2082 gp
->tx_fifo_sz
, gp
->rx_fifo_sz
);
2087 if (gp
->tx_fifo_sz
!= (2 * 1024) ||
2088 gp
->rx_fifo_sz
!= (2 * 1024)) {
2089 printk(KERN_ERR PFX
"RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2090 gp
->tx_fifo_sz
, gp
->rx_fifo_sz
);
2093 gp
->swrst_base
= (64 / 4) << GREG_SWRST_CACHE_SHIFT
;
2100 /* Must be invoked under gp->lock and gp->tx_lock. */
2101 static void gem_reinit_chip(struct gem
*gp
)
2103 /* Reset the chip */
2106 /* Make sure ints are disabled */
2107 gem_disable_ints(gp
);
2109 /* Allocate & setup ring buffers */
2112 /* Configure pause thresholds */
2113 gem_init_pause_thresholds(gp
);
2115 /* Init DMA & MAC engines */
2121 /* Must be invoked with no lock held. */
2122 static void gem_stop_phy(struct gem
*gp
, int wol
)
2125 unsigned long flags
;
2127 /* Let the chip settle down a bit, it seems that helps
2128 * for sleep mode on some models
2132 /* Make sure we aren't polling PHY status change. We
2133 * don't currently use that feature though
2135 mifcfg
= readl(gp
->regs
+ MIF_CFG
);
2136 mifcfg
&= ~MIF_CFG_POLL
;
2137 writel(mifcfg
, gp
->regs
+ MIF_CFG
);
2139 if (wol
&& gp
->has_wol
) {
2140 unsigned char *e
= &gp
->dev
->dev_addr
[0];
2143 /* Setup wake-on-lan for MAGIC packet */
2144 writel(MAC_RXCFG_HFE
| MAC_RXCFG_SFCS
| MAC_RXCFG_ENAB
,
2145 gp
->regs
+ MAC_RXCFG
);
2146 writel((e
[4] << 8) | e
[5], gp
->regs
+ WOL_MATCH0
);
2147 writel((e
[2] << 8) | e
[3], gp
->regs
+ WOL_MATCH1
);
2148 writel((e
[0] << 8) | e
[1], gp
->regs
+ WOL_MATCH2
);
2150 writel(WOL_MCOUNT_N
| WOL_MCOUNT_M
, gp
->regs
+ WOL_MCOUNT
);
2151 csr
= WOL_WAKECSR_ENABLE
;
2152 if ((readl(gp
->regs
+ MAC_XIFCFG
) & MAC_XIFCFG_GMII
) == 0)
2153 csr
|= WOL_WAKECSR_MII
;
2154 writel(csr
, gp
->regs
+ WOL_WAKECSR
);
2156 writel(0, gp
->regs
+ MAC_RXCFG
);
2157 (void)readl(gp
->regs
+ MAC_RXCFG
);
2158 /* Machine sleep will die in strange ways if we
2159 * dont wait a bit here, looks like the chip takes
2160 * some time to really shut down
2165 writel(0, gp
->regs
+ MAC_TXCFG
);
2166 writel(0, gp
->regs
+ MAC_XIFCFG
);
2167 writel(0, gp
->regs
+ TXDMA_CFG
);
2168 writel(0, gp
->regs
+ RXDMA_CFG
);
2171 spin_lock_irqsave(&gp
->lock
, flags
);
2172 spin_lock(&gp
->tx_lock
);
2174 writel(MAC_TXRST_CMD
, gp
->regs
+ MAC_TXRST
);
2175 writel(MAC_RXRST_CMD
, gp
->regs
+ MAC_RXRST
);
2176 spin_unlock(&gp
->tx_lock
);
2177 spin_unlock_irqrestore(&gp
->lock
, flags
);
2179 /* No need to take the lock here */
2181 if (found_mii_phy(gp
) && gp
->phy_mii
.def
->ops
->suspend
)
2182 gp
->phy_mii
.def
->ops
->suspend(&gp
->phy_mii
);
2184 /* According to Apple, we must set the MDIO pins to this begnign
2185 * state or we may 1) eat more current, 2) damage some PHYs
2187 writel(mifcfg
| MIF_CFG_BBMODE
, gp
->regs
+ MIF_CFG
);
2188 writel(0, gp
->regs
+ MIF_BBCLK
);
2189 writel(0, gp
->regs
+ MIF_BBDATA
);
2190 writel(0, gp
->regs
+ MIF_BBOENAB
);
2191 writel(MAC_XIFCFG_GMII
| MAC_XIFCFG_LBCK
, gp
->regs
+ MAC_XIFCFG
);
2192 (void) readl(gp
->regs
+ MAC_XIFCFG
);
2197 static int gem_do_start(struct net_device
*dev
)
2199 struct gem
*gp
= dev
->priv
;
2200 unsigned long flags
;
2202 spin_lock_irqsave(&gp
->lock
, flags
);
2203 spin_lock(&gp
->tx_lock
);
2205 /* Enable the cell */
2208 /* Init & setup chip hardware */
2209 gem_reinit_chip(gp
);
2213 if (gp
->lstate
== link_up
) {
2214 netif_carrier_on(gp
->dev
);
2215 gem_set_link_modes(gp
);
2218 netif_wake_queue(gp
->dev
);
2220 spin_unlock(&gp
->tx_lock
);
2221 spin_unlock_irqrestore(&gp
->lock
, flags
);
2223 if (request_irq(gp
->pdev
->irq
, gem_interrupt
,
2224 IRQF_SHARED
, dev
->name
, (void *)dev
)) {
2225 printk(KERN_ERR
"%s: failed to request irq !\n", gp
->dev
->name
);
2227 spin_lock_irqsave(&gp
->lock
, flags
);
2228 spin_lock(&gp
->tx_lock
);
2232 gem_clean_rings(gp
);
2235 spin_unlock(&gp
->tx_lock
);
2236 spin_unlock_irqrestore(&gp
->lock
, flags
);
2244 static void gem_do_stop(struct net_device
*dev
, int wol
)
2246 struct gem
*gp
= dev
->priv
;
2247 unsigned long flags
;
2249 spin_lock_irqsave(&gp
->lock
, flags
);
2250 spin_lock(&gp
->tx_lock
);
2254 /* Stop netif queue */
2255 netif_stop_queue(dev
);
2257 /* Make sure ints are disabled */
2258 gem_disable_ints(gp
);
2260 /* We can drop the lock now */
2261 spin_unlock(&gp
->tx_lock
);
2262 spin_unlock_irqrestore(&gp
->lock
, flags
);
2264 /* If we are going to sleep with WOL */
2271 /* Get rid of rings */
2272 gem_clean_rings(gp
);
2274 /* No irq needed anymore */
2275 free_irq(gp
->pdev
->irq
, (void *) dev
);
2277 /* Cell not needed neither if no WOL */
2279 spin_lock_irqsave(&gp
->lock
, flags
);
2281 spin_unlock_irqrestore(&gp
->lock
, flags
);
2285 static void gem_reset_task(void *data
)
2287 struct gem
*gp
= (struct gem
*) data
;
2289 mutex_lock(&gp
->pm_mutex
);
2291 netif_poll_disable(gp
->dev
);
2293 spin_lock_irq(&gp
->lock
);
2294 spin_lock(&gp
->tx_lock
);
2296 if (gp
->running
== 0)
2300 netif_stop_queue(gp
->dev
);
2302 /* Reset the chip & rings */
2303 gem_reinit_chip(gp
);
2304 if (gp
->lstate
== link_up
)
2305 gem_set_link_modes(gp
);
2306 netif_wake_queue(gp
->dev
);
2309 gp
->reset_task_pending
= 0;
2311 spin_unlock(&gp
->tx_lock
);
2312 spin_unlock_irq(&gp
->lock
);
2314 netif_poll_enable(gp
->dev
);
2316 mutex_unlock(&gp
->pm_mutex
);
2320 static int gem_open(struct net_device
*dev
)
2322 struct gem
*gp
= dev
->priv
;
2325 mutex_lock(&gp
->pm_mutex
);
2327 /* We need the cell enabled */
2329 rc
= gem_do_start(dev
);
2330 gp
->opened
= (rc
== 0);
2332 mutex_unlock(&gp
->pm_mutex
);
2337 static int gem_close(struct net_device
*dev
)
2339 struct gem
*gp
= dev
->priv
;
2341 /* Note: we don't need to call netif_poll_disable() here because
2342 * our caller (dev_close) already did it for us
2345 mutex_lock(&gp
->pm_mutex
);
2349 gem_do_stop(dev
, 0);
2351 mutex_unlock(&gp
->pm_mutex
);
2357 static int gem_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2359 struct net_device
*dev
= pci_get_drvdata(pdev
);
2360 struct gem
*gp
= dev
->priv
;
2361 unsigned long flags
;
2363 mutex_lock(&gp
->pm_mutex
);
2365 netif_poll_disable(dev
);
2367 printk(KERN_INFO
"%s: suspending, WakeOnLan %s\n",
2369 (gp
->wake_on_lan
&& gp
->opened
) ? "enabled" : "disabled");
2371 /* Keep the cell enabled during the entire operation */
2372 spin_lock_irqsave(&gp
->lock
, flags
);
2373 spin_lock(&gp
->tx_lock
);
2375 spin_unlock(&gp
->tx_lock
);
2376 spin_unlock_irqrestore(&gp
->lock
, flags
);
2378 /* If the driver is opened, we stop the MAC */
2380 /* Stop traffic, mark us closed */
2381 netif_device_detach(dev
);
2383 /* Switch off MAC, remember WOL setting */
2384 gp
->asleep_wol
= gp
->wake_on_lan
;
2385 gem_do_stop(dev
, gp
->asleep_wol
);
2389 /* Mark us asleep */
2393 /* Stop the link timer */
2394 del_timer_sync(&gp
->link_timer
);
2396 /* Now we release the mutex to not block the reset task who
2397 * can take it too. We are marked asleep, so there will be no
2400 mutex_unlock(&gp
->pm_mutex
);
2402 /* Wait for a pending reset task to complete */
2403 while (gp
->reset_task_pending
)
2405 flush_scheduled_work();
2407 /* Shut the PHY down eventually and setup WOL */
2408 gem_stop_phy(gp
, gp
->asleep_wol
);
2410 /* Make sure bus master is disabled */
2411 pci_disable_device(gp
->pdev
);
2413 /* Release the cell, no need to take a lock at this point since
2414 * nothing else can happen now
2421 static int gem_resume(struct pci_dev
*pdev
)
2423 struct net_device
*dev
= pci_get_drvdata(pdev
);
2424 struct gem
*gp
= dev
->priv
;
2425 unsigned long flags
;
2427 printk(KERN_INFO
"%s: resuming\n", dev
->name
);
2429 mutex_lock(&gp
->pm_mutex
);
2431 /* Keep the cell enabled during the entire operation, no need to
2432 * take a lock here tho since nothing else can happen while we are
2437 /* Make sure PCI access and bus master are enabled */
2438 if (pci_enable_device(gp
->pdev
)) {
2439 printk(KERN_ERR
"%s: Can't re-enable chip !\n",
2441 /* Put cell and forget it for now, it will be considered as
2442 * still asleep, a new sleep cycle may bring it back
2445 mutex_unlock(&gp
->pm_mutex
);
2448 pci_set_master(gp
->pdev
);
2450 /* Reset everything */
2453 /* Mark us woken up */
2457 /* Bring the PHY back. Again, lock is useless at this point as
2458 * nothing can be happening until we restart the whole thing
2462 /* If we were opened, bring everything back */
2467 /* Re-attach net device */
2468 netif_device_attach(dev
);
2472 spin_lock_irqsave(&gp
->lock
, flags
);
2473 spin_lock(&gp
->tx_lock
);
2475 /* If we had WOL enabled, the cell clock was never turned off during
2476 * sleep, so we end up beeing unbalanced. Fix that here
2481 /* This function doesn't need to hold the cell, it will be held if the
2482 * driver is open by gem_do_start().
2486 spin_unlock(&gp
->tx_lock
);
2487 spin_unlock_irqrestore(&gp
->lock
, flags
);
2489 netif_poll_enable(dev
);
2491 mutex_unlock(&gp
->pm_mutex
);
2495 #endif /* CONFIG_PM */
2497 static struct net_device_stats
*gem_get_stats(struct net_device
*dev
)
2499 struct gem
*gp
= dev
->priv
;
2500 struct net_device_stats
*stats
= &gp
->net_stats
;
2502 spin_lock_irq(&gp
->lock
);
2503 spin_lock(&gp
->tx_lock
);
2505 /* I have seen this being called while the PM was in progress,
2506 * so we shield against this
2509 stats
->rx_crc_errors
+= readl(gp
->regs
+ MAC_FCSERR
);
2510 writel(0, gp
->regs
+ MAC_FCSERR
);
2512 stats
->rx_frame_errors
+= readl(gp
->regs
+ MAC_AERR
);
2513 writel(0, gp
->regs
+ MAC_AERR
);
2515 stats
->rx_length_errors
+= readl(gp
->regs
+ MAC_LERR
);
2516 writel(0, gp
->regs
+ MAC_LERR
);
2518 stats
->tx_aborted_errors
+= readl(gp
->regs
+ MAC_ECOLL
);
2519 stats
->collisions
+=
2520 (readl(gp
->regs
+ MAC_ECOLL
) +
2521 readl(gp
->regs
+ MAC_LCOLL
));
2522 writel(0, gp
->regs
+ MAC_ECOLL
);
2523 writel(0, gp
->regs
+ MAC_LCOLL
);
2526 spin_unlock(&gp
->tx_lock
);
2527 spin_unlock_irq(&gp
->lock
);
2529 return &gp
->net_stats
;
2532 static void gem_set_multicast(struct net_device
*dev
)
2534 struct gem
*gp
= dev
->priv
;
2535 u32 rxcfg
, rxcfg_new
;
2539 spin_lock_irq(&gp
->lock
);
2540 spin_lock(&gp
->tx_lock
);
2545 netif_stop_queue(dev
);
2547 rxcfg
= readl(gp
->regs
+ MAC_RXCFG
);
2548 rxcfg_new
= gem_setup_multicast(gp
);
2550 rxcfg_new
|= MAC_RXCFG_SFCS
;
2552 gp
->mac_rx_cfg
= rxcfg_new
;
2554 writel(rxcfg
& ~MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
2555 while (readl(gp
->regs
+ MAC_RXCFG
) & MAC_RXCFG_ENAB
) {
2561 rxcfg
&= ~(MAC_RXCFG_PROM
| MAC_RXCFG_HFE
);
2564 writel(rxcfg
, gp
->regs
+ MAC_RXCFG
);
2566 netif_wake_queue(dev
);
2569 spin_unlock(&gp
->tx_lock
);
2570 spin_unlock_irq(&gp
->lock
);
2573 /* Jumbo-grams don't seem to work :-( */
2574 #define GEM_MIN_MTU 68
2576 #define GEM_MAX_MTU 1500
2578 #define GEM_MAX_MTU 9000
2581 static int gem_change_mtu(struct net_device
*dev
, int new_mtu
)
2583 struct gem
*gp
= dev
->priv
;
2585 if (new_mtu
< GEM_MIN_MTU
|| new_mtu
> GEM_MAX_MTU
)
2588 if (!netif_running(dev
) || !netif_device_present(dev
)) {
2589 /* We'll just catch it later when the
2590 * device is up'd or resumed.
2596 mutex_lock(&gp
->pm_mutex
);
2597 spin_lock_irq(&gp
->lock
);
2598 spin_lock(&gp
->tx_lock
);
2601 gem_reinit_chip(gp
);
2602 if (gp
->lstate
== link_up
)
2603 gem_set_link_modes(gp
);
2605 spin_unlock(&gp
->tx_lock
);
2606 spin_unlock_irq(&gp
->lock
);
2607 mutex_unlock(&gp
->pm_mutex
);
2612 static void gem_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
2614 struct gem
*gp
= dev
->priv
;
2616 strcpy(info
->driver
, DRV_NAME
);
2617 strcpy(info
->version
, DRV_VERSION
);
2618 strcpy(info
->bus_info
, pci_name(gp
->pdev
));
2621 static int gem_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2623 struct gem
*gp
= dev
->priv
;
2625 if (gp
->phy_type
== phy_mii_mdio0
||
2626 gp
->phy_type
== phy_mii_mdio1
) {
2627 if (gp
->phy_mii
.def
)
2628 cmd
->supported
= gp
->phy_mii
.def
->features
;
2630 cmd
->supported
= (SUPPORTED_10baseT_Half
|
2631 SUPPORTED_10baseT_Full
);
2633 /* XXX hardcoded stuff for now */
2634 cmd
->port
= PORT_MII
;
2635 cmd
->transceiver
= XCVR_EXTERNAL
;
2636 cmd
->phy_address
= 0; /* XXX fixed PHYAD */
2638 /* Return current PHY settings */
2639 spin_lock_irq(&gp
->lock
);
2640 cmd
->autoneg
= gp
->want_autoneg
;
2641 cmd
->speed
= gp
->phy_mii
.speed
;
2642 cmd
->duplex
= gp
->phy_mii
.duplex
;
2643 cmd
->advertising
= gp
->phy_mii
.advertising
;
2645 /* If we started with a forced mode, we don't have a default
2646 * advertise set, we need to return something sensible so
2647 * userland can re-enable autoneg properly.
2649 if (cmd
->advertising
== 0)
2650 cmd
->advertising
= cmd
->supported
;
2651 spin_unlock_irq(&gp
->lock
);
2652 } else { // XXX PCS ?
2654 (SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
2655 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
2657 cmd
->advertising
= cmd
->supported
;
2659 cmd
->duplex
= cmd
->port
= cmd
->phy_address
=
2660 cmd
->transceiver
= cmd
->autoneg
= 0;
2662 cmd
->maxtxpkt
= cmd
->maxrxpkt
= 0;
2667 static int gem_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2669 struct gem
*gp
= dev
->priv
;
2671 /* Verify the settings we care about. */
2672 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
2673 cmd
->autoneg
!= AUTONEG_DISABLE
)
2676 if (cmd
->autoneg
== AUTONEG_ENABLE
&&
2677 cmd
->advertising
== 0)
2680 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
2681 ((cmd
->speed
!= SPEED_1000
&&
2682 cmd
->speed
!= SPEED_100
&&
2683 cmd
->speed
!= SPEED_10
) ||
2684 (cmd
->duplex
!= DUPLEX_HALF
&&
2685 cmd
->duplex
!= DUPLEX_FULL
)))
2688 /* Apply settings and restart link process. */
2689 spin_lock_irq(&gp
->lock
);
2691 gem_begin_auto_negotiation(gp
, cmd
);
2693 spin_unlock_irq(&gp
->lock
);
2698 static int gem_nway_reset(struct net_device
*dev
)
2700 struct gem
*gp
= dev
->priv
;
2702 if (!gp
->want_autoneg
)
2705 /* Restart link process. */
2706 spin_lock_irq(&gp
->lock
);
2708 gem_begin_auto_negotiation(gp
, NULL
);
2710 spin_unlock_irq(&gp
->lock
);
2715 static u32
gem_get_msglevel(struct net_device
*dev
)
2717 struct gem
*gp
= dev
->priv
;
2718 return gp
->msg_enable
;
2721 static void gem_set_msglevel(struct net_device
*dev
, u32 value
)
2723 struct gem
*gp
= dev
->priv
;
2724 gp
->msg_enable
= value
;
2728 /* Add more when I understand how to program the chip */
2729 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2731 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2733 static void gem_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2735 struct gem
*gp
= dev
->priv
;
2737 /* Add more when I understand how to program the chip */
2739 wol
->supported
= WOL_SUPPORTED_MASK
;
2740 wol
->wolopts
= gp
->wake_on_lan
;
2747 static int gem_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2749 struct gem
*gp
= dev
->priv
;
2753 gp
->wake_on_lan
= wol
->wolopts
& WOL_SUPPORTED_MASK
;
2757 static const struct ethtool_ops gem_ethtool_ops
= {
2758 .get_drvinfo
= gem_get_drvinfo
,
2759 .get_link
= ethtool_op_get_link
,
2760 .get_settings
= gem_get_settings
,
2761 .set_settings
= gem_set_settings
,
2762 .nway_reset
= gem_nway_reset
,
2763 .get_msglevel
= gem_get_msglevel
,
2764 .set_msglevel
= gem_set_msglevel
,
2765 .get_wol
= gem_get_wol
,
2766 .set_wol
= gem_set_wol
,
2769 static int gem_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2771 struct gem
*gp
= dev
->priv
;
2772 struct mii_ioctl_data
*data
= if_mii(ifr
);
2773 int rc
= -EOPNOTSUPP
;
2774 unsigned long flags
;
2776 /* Hold the PM mutex while doing ioctl's or we may collide
2777 * with power management.
2779 mutex_lock(&gp
->pm_mutex
);
2781 spin_lock_irqsave(&gp
->lock
, flags
);
2783 spin_unlock_irqrestore(&gp
->lock
, flags
);
2786 case SIOCGMIIPHY
: /* Get address of MII PHY in use. */
2787 data
->phy_id
= gp
->mii_phy_addr
;
2788 /* Fallthrough... */
2790 case SIOCGMIIREG
: /* Read MII PHY register. */
2794 data
->val_out
= __phy_read(gp
, data
->phy_id
& 0x1f,
2795 data
->reg_num
& 0x1f);
2800 case SIOCSMIIREG
: /* Write MII PHY register. */
2801 if (!capable(CAP_NET_ADMIN
))
2803 else if (!gp
->running
)
2806 __phy_write(gp
, data
->phy_id
& 0x1f, data
->reg_num
& 0x1f,
2813 spin_lock_irqsave(&gp
->lock
, flags
);
2815 spin_unlock_irqrestore(&gp
->lock
, flags
);
2817 mutex_unlock(&gp
->pm_mutex
);
2822 #if (!defined(__sparc__) && !defined(CONFIG_PPC_PMAC))
2823 /* Fetch MAC address from vital product data of PCI ROM. */
2824 static int find_eth_addr_in_vpd(void __iomem
*rom_base
, int len
, unsigned char *dev_addr
)
2828 for (this_offset
= 0x20; this_offset
< len
; this_offset
++) {
2829 void __iomem
*p
= rom_base
+ this_offset
;
2832 if (readb(p
+ 0) != 0x90 ||
2833 readb(p
+ 1) != 0x00 ||
2834 readb(p
+ 2) != 0x09 ||
2835 readb(p
+ 3) != 0x4e ||
2836 readb(p
+ 4) != 0x41 ||
2837 readb(p
+ 5) != 0x06)
2843 for (i
= 0; i
< 6; i
++)
2844 dev_addr
[i
] = readb(p
+ i
);
2850 static void get_gem_mac_nonobp(struct pci_dev
*pdev
, unsigned char *dev_addr
)
2853 void __iomem
*p
= pci_map_rom(pdev
, &size
);
2858 found
= readb(p
) == 0x55 &&
2859 readb(p
+ 1) == 0xaa &&
2860 find_eth_addr_in_vpd(p
, (64 * 1024), dev_addr
);
2861 pci_unmap_rom(pdev
, p
);
2866 /* Sun MAC prefix then 3 random bytes. */
2870 get_random_bytes(dev_addr
+ 3, 3);
2873 #endif /* not Sparc and not PPC */
2875 static int __devinit
gem_get_device_address(struct gem
*gp
)
2877 #if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
2878 struct net_device
*dev
= gp
->dev
;
2881 #if defined(__sparc__)
2882 struct pci_dev
*pdev
= gp
->pdev
;
2883 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
2887 unsigned char *addr
;
2890 addr
= of_get_property(pcp
->prom_node
, "local-mac-address",
2892 if (addr
&& len
== 6) {
2894 memcpy(dev
->dev_addr
, addr
, 6);
2898 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
2899 #elif defined(CONFIG_PPC_PMAC)
2900 const unsigned char *addr
;
2902 addr
= get_property(gp
->of_node
, "local-mac-address", NULL
);
2905 printk(KERN_ERR
"%s: can't get mac-address\n", dev
->name
);
2908 memcpy(dev
->dev_addr
, addr
, 6);
2910 get_gem_mac_nonobp(gp
->pdev
, gp
->dev
->dev_addr
);
2915 static void gem_remove_one(struct pci_dev
*pdev
)
2917 struct net_device
*dev
= pci_get_drvdata(pdev
);
2920 struct gem
*gp
= dev
->priv
;
2922 unregister_netdev(dev
);
2924 /* Stop the link timer */
2925 del_timer_sync(&gp
->link_timer
);
2927 /* We shouldn't need any locking here */
2930 /* Wait for a pending reset task to complete */
2931 while (gp
->reset_task_pending
)
2933 flush_scheduled_work();
2935 /* Shut the PHY down */
2936 gem_stop_phy(gp
, 0);
2940 /* Make sure bus master is disabled */
2941 pci_disable_device(gp
->pdev
);
2943 /* Free resources */
2944 pci_free_consistent(pdev
,
2945 sizeof(struct gem_init_block
),
2949 pci_release_regions(pdev
);
2952 pci_set_drvdata(pdev
, NULL
);
2956 static int __devinit
gem_init_one(struct pci_dev
*pdev
,
2957 const struct pci_device_id
*ent
)
2959 static int gem_version_printed
= 0;
2960 unsigned long gemreg_base
, gemreg_len
;
2961 struct net_device
*dev
;
2963 int i
, err
, pci_using_dac
;
2965 if (gem_version_printed
++ == 0)
2966 printk(KERN_INFO
"%s", version
);
2968 /* Apple gmac note: during probe, the chip is powered up by
2969 * the arch code to allow the code below to work (and to let
2970 * the chip be probed on the config space. It won't stay powered
2971 * up until the interface is brought up however, so we can't rely
2972 * on register configuration done at this point.
2974 err
= pci_enable_device(pdev
);
2976 printk(KERN_ERR PFX
"Cannot enable MMIO operation, "
2980 pci_set_master(pdev
);
2982 /* Configure DMA attributes. */
2984 /* All of the GEM documentation states that 64-bit DMA addressing
2985 * is fully supported and should work just fine. However the
2986 * front end for RIO based GEMs is different and only supports
2987 * 32-bit addressing.
2989 * For now we assume the various PPC GEMs are 32-bit only as well.
2991 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
2992 pdev
->device
== PCI_DEVICE_ID_SUN_GEM
&&
2993 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
2996 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
2998 printk(KERN_ERR PFX
"No usable DMA configuration, "
3000 goto err_disable_device
;
3005 gemreg_base
= pci_resource_start(pdev
, 0);
3006 gemreg_len
= pci_resource_len(pdev
, 0);
3008 if ((pci_resource_flags(pdev
, 0) & IORESOURCE_IO
) != 0) {
3009 printk(KERN_ERR PFX
"Cannot find proper PCI device "
3010 "base address, aborting.\n");
3012 goto err_disable_device
;
3015 dev
= alloc_etherdev(sizeof(*gp
));
3017 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
3019 goto err_disable_device
;
3021 SET_MODULE_OWNER(dev
);
3022 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3026 err
= pci_request_regions(pdev
, DRV_NAME
);
3028 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
3030 goto err_out_free_netdev
;
3034 dev
->base_addr
= (long) pdev
;
3037 gp
->msg_enable
= DEFAULT_MSG
;
3039 spin_lock_init(&gp
->lock
);
3040 spin_lock_init(&gp
->tx_lock
);
3041 mutex_init(&gp
->pm_mutex
);
3043 init_timer(&gp
->link_timer
);
3044 gp
->link_timer
.function
= gem_link_timer
;
3045 gp
->link_timer
.data
= (unsigned long) gp
;
3047 INIT_WORK(&gp
->reset_task
, gem_reset_task
, gp
);
3049 gp
->lstate
= link_down
;
3050 gp
->timer_ticks
= 0;
3051 netif_carrier_off(dev
);
3053 gp
->regs
= ioremap(gemreg_base
, gemreg_len
);
3054 if (gp
->regs
== 0UL) {
3055 printk(KERN_ERR PFX
"Cannot map device registers, "
3058 goto err_out_free_res
;
3061 /* On Apple, we want a reference to the Open Firmware device-tree
3062 * node. We use it for clock control.
3064 #ifdef CONFIG_PPC_PMAC
3065 gp
->of_node
= pci_device_to_OF_node(pdev
);
3068 /* Only Apple version supports WOL afaik */
3069 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
)
3072 /* Make sure cell is enabled */
3075 /* Make sure everything is stopped and in init state */
3078 /* Fill up the mii_phy structure (even if we won't use it) */
3079 gp
->phy_mii
.dev
= dev
;
3080 gp
->phy_mii
.mdio_read
= _phy_read
;
3081 gp
->phy_mii
.mdio_write
= _phy_write
;
3082 #ifdef CONFIG_PPC_PMAC
3083 gp
->phy_mii
.platform_data
= gp
->of_node
;
3085 /* By default, we start with autoneg */
3086 gp
->want_autoneg
= 1;
3088 /* Check fifo sizes, PHY type, etc... */
3089 if (gem_check_invariants(gp
)) {
3091 goto err_out_iounmap
;
3094 /* It is guaranteed that the returned buffer will be at least
3095 * PAGE_SIZE aligned.
3097 gp
->init_block
= (struct gem_init_block
*)
3098 pci_alloc_consistent(pdev
, sizeof(struct gem_init_block
),
3100 if (!gp
->init_block
) {
3101 printk(KERN_ERR PFX
"Cannot allocate init block, "
3104 goto err_out_iounmap
;
3107 if (gem_get_device_address(gp
))
3108 goto err_out_free_consistent
;
3110 dev
->open
= gem_open
;
3111 dev
->stop
= gem_close
;
3112 dev
->hard_start_xmit
= gem_start_xmit
;
3113 dev
->get_stats
= gem_get_stats
;
3114 dev
->set_multicast_list
= gem_set_multicast
;
3115 dev
->do_ioctl
= gem_ioctl
;
3116 dev
->poll
= gem_poll
;
3118 dev
->ethtool_ops
= &gem_ethtool_ops
;
3119 dev
->tx_timeout
= gem_tx_timeout
;
3120 dev
->watchdog_timeo
= 5 * HZ
;
3121 dev
->change_mtu
= gem_change_mtu
;
3122 dev
->irq
= pdev
->irq
;
3124 #ifdef CONFIG_NET_POLL_CONTROLLER
3125 dev
->poll_controller
= gem_poll_controller
;
3128 /* Set that now, in case PM kicks in now */
3129 pci_set_drvdata(pdev
, dev
);
3131 /* Detect & init PHY, start autoneg, we release the cell now
3132 * too, it will be managed by whoever needs it
3136 spin_lock_irq(&gp
->lock
);
3138 spin_unlock_irq(&gp
->lock
);
3140 /* Register with kernel */
3141 if (register_netdev(dev
)) {
3142 printk(KERN_ERR PFX
"Cannot register net device, "
3145 goto err_out_free_consistent
;
3148 printk(KERN_INFO
"%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
3150 for (i
= 0; i
< 6; i
++)
3151 printk("%2.2x%c", dev
->dev_addr
[i
],
3152 i
== 5 ? ' ' : ':');
3155 if (gp
->phy_type
== phy_mii_mdio0
||
3156 gp
->phy_type
== phy_mii_mdio1
)
3157 printk(KERN_INFO
"%s: Found %s PHY\n", dev
->name
,
3158 gp
->phy_mii
.def
? gp
->phy_mii
.def
->name
: "no");
3160 /* GEM can do it all... */
3161 dev
->features
|= NETIF_F_SG
| NETIF_F_HW_CSUM
| NETIF_F_LLTX
;
3163 dev
->features
|= NETIF_F_HIGHDMA
;
3167 err_out_free_consistent
:
3168 gem_remove_one(pdev
);
3174 pci_release_regions(pdev
);
3176 err_out_free_netdev
:
3179 pci_disable_device(pdev
);
3185 static struct pci_driver gem_driver
= {
3186 .name
= GEM_MODULE_NAME
,
3187 .id_table
= gem_pci_tbl
,
3188 .probe
= gem_init_one
,
3189 .remove
= gem_remove_one
,
3191 .suspend
= gem_suspend
,
3192 .resume
= gem_resume
,
3193 #endif /* CONFIG_PM */
3196 static int __init
gem_init(void)
3198 return pci_register_driver(&gem_driver
);
3201 static void __exit
gem_cleanup(void)
3203 pci_unregister_driver(&gem_driver
);
3206 module_init(gem_init
);
3207 module_exit(gem_cleanup
);