2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
10 * Copyright (C) 2000-2003 Broadcom Corporation.
13 #include <linux/config.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/compiler.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/pci.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/ethtool.h>
29 #include <linux/mii.h>
30 #include <linux/if_vlan.h>
32 #include <linux/tcp.h>
33 #include <linux/workqueue.h>
35 #include <net/checksum.h>
37 #include <asm/system.h>
39 #include <asm/byteorder.h>
40 #include <asm/uaccess.h>
43 #include <asm/idprom.h>
44 #include <asm/oplib.h>
48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49 #define TG3_VLAN_TAG_USED 1
51 #define TG3_VLAN_TAG_USED 0
55 #define TG3_TSO_SUPPORT 1
57 #define TG3_TSO_SUPPORT 0
62 #define DRV_MODULE_NAME "tg3"
63 #define PFX DRV_MODULE_NAME ": "
64 #define DRV_MODULE_VERSION "3.29"
65 #define DRV_MODULE_RELDATE "May 23, 2005"
67 #define TG3_DEF_MAC_MODE 0
68 #define TG3_DEF_RX_MODE 0
69 #define TG3_DEF_TX_MODE 0
70 #define TG3_DEF_MSG_ENABLE \
80 /* length of time before we decide the hardware is borked,
81 * and dev->tx_timeout() should be called to fix the problem
83 #define TG3_TX_TIMEOUT (5 * HZ)
85 /* hardware minimum and maximum for a single frame's data payload */
86 #define TG3_MIN_MTU 60
87 #define TG3_MAX_MTU(tp) \
88 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
90 /* These numbers seem to be hard coded in the NIC firmware somehow.
91 * You can't change the ring sizes, but you can change where you place
92 * them in the NIC onboard memory.
94 #define TG3_RX_RING_SIZE 512
95 #define TG3_DEF_RX_RING_PENDING 200
96 #define TG3_RX_JUMBO_RING_SIZE 256
97 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
99 /* Do not place this n-ring entries value into the tp struct itself,
100 * we really want to expose these constants to GCC so that modulo et
101 * al. operations are done with shifts and masks instead of with
102 * hw multiply/modulo instructions. Another solution would be to
103 * replace things like '% foo' with '& (foo - 1)'.
105 #define TG3_RX_RCB_RING_SIZE(tp) \
106 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
108 #define TG3_TX_RING_SIZE 512
109 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
111 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
113 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
114 TG3_RX_JUMBO_RING_SIZE)
115 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
116 TG3_RX_RCB_RING_SIZE(tp))
117 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
119 #define TX_RING_GAP(TP) \
120 (TG3_TX_RING_SIZE - (TP)->tx_pending)
121 #define TX_BUFFS_AVAIL(TP) \
122 (((TP)->tx_cons <= (TP)->tx_prod) ? \
123 (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod : \
124 (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
125 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
128 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130 /* minimum number of free TX descriptors required to wake up TX process */
131 #define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
133 /* number of ETHTOOL_GSTATS u64's */
134 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
136 #define TG3_NUM_TEST 6
138 static char version
[] __devinitdata
=
139 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
141 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
142 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
143 MODULE_LICENSE("GPL");
144 MODULE_VERSION(DRV_MODULE_VERSION
);
146 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
147 module_param(tg3_debug
, int, 0);
148 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
150 static struct pci_device_id tg3_pci_tbl
[] = {
151 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
,
152 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
153 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
,
154 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
155 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
,
156 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
157 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
,
158 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
159 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
,
160 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
161 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
,
162 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
163 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
,
164 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
165 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
,
166 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
167 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
,
168 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
169 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
,
170 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
171 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
,
172 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
173 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
,
174 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
175 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
,
176 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
177 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
,
178 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
179 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
,
180 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
181 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
,
182 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
183 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
,
184 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
185 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
,
186 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
187 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
,
188 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
189 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
,
190 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
191 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
,
192 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
193 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
,
194 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
195 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
,
196 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
197 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
,
198 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
199 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
,
200 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
201 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
,
202 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
203 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
,
204 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
205 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
,
206 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
207 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
,
208 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
209 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
,
210 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
211 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
,
212 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
213 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
,
214 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
215 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
,
216 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
217 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
,
218 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
219 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
,
220 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
221 { PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
,
222 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
223 { PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
,
224 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
225 { PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
,
226 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
227 { PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
,
228 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
229 { PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
,
230 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
231 { PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
,
232 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
233 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
,
234 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
238 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
241 const char string
[ETH_GSTRING_LEN
];
242 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
245 { "rx_ucast_packets" },
246 { "rx_mcast_packets" },
247 { "rx_bcast_packets" },
249 { "rx_align_errors" },
250 { "rx_xon_pause_rcvd" },
251 { "rx_xoff_pause_rcvd" },
252 { "rx_mac_ctrl_rcvd" },
253 { "rx_xoff_entered" },
254 { "rx_frame_too_long_errors" },
256 { "rx_undersize_packets" },
257 { "rx_in_length_errors" },
258 { "rx_out_length_errors" },
259 { "rx_64_or_less_octet_packets" },
260 { "rx_65_to_127_octet_packets" },
261 { "rx_128_to_255_octet_packets" },
262 { "rx_256_to_511_octet_packets" },
263 { "rx_512_to_1023_octet_packets" },
264 { "rx_1024_to_1522_octet_packets" },
265 { "rx_1523_to_2047_octet_packets" },
266 { "rx_2048_to_4095_octet_packets" },
267 { "rx_4096_to_8191_octet_packets" },
268 { "rx_8192_to_9022_octet_packets" },
275 { "tx_flow_control" },
277 { "tx_single_collisions" },
278 { "tx_mult_collisions" },
280 { "tx_excessive_collisions" },
281 { "tx_late_collisions" },
282 { "tx_collide_2times" },
283 { "tx_collide_3times" },
284 { "tx_collide_4times" },
285 { "tx_collide_5times" },
286 { "tx_collide_6times" },
287 { "tx_collide_7times" },
288 { "tx_collide_8times" },
289 { "tx_collide_9times" },
290 { "tx_collide_10times" },
291 { "tx_collide_11times" },
292 { "tx_collide_12times" },
293 { "tx_collide_13times" },
294 { "tx_collide_14times" },
295 { "tx_collide_15times" },
296 { "tx_ucast_packets" },
297 { "tx_mcast_packets" },
298 { "tx_bcast_packets" },
299 { "tx_carrier_sense_errors" },
303 { "dma_writeq_full" },
304 { "dma_write_prioq_full" },
308 { "rx_threshold_hit" },
310 { "dma_readq_full" },
311 { "dma_read_prioq_full" },
312 { "tx_comp_queue_full" },
314 { "ring_set_send_prod_index" },
315 { "ring_status_update" },
317 { "nic_avoided_irqs" },
318 { "nic_tx_threshold_hit" }
322 const char string
[ETH_GSTRING_LEN
];
323 } ethtool_test_keys
[TG3_NUM_TEST
] = {
324 { "nvram test (online) " },
325 { "link test (online) " },
326 { "register test (offline)" },
327 { "memory test (offline)" },
328 { "loopback test (offline)" },
329 { "interrupt test (offline)" },
332 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
334 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) != 0) {
337 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
338 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
339 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
340 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
342 writel(val
, tp
->regs
+ off
);
343 if ((tp
->tg3_flags
& TG3_FLAG_5701_REG_WRITE_BUG
) != 0)
344 readl(tp
->regs
+ off
);
348 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
)
350 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) != 0) {
353 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
354 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
355 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
356 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
358 void __iomem
*dest
= tp
->regs
+ off
;
360 readl(dest
); /* always flush PCI write */
364 static inline void _tw32_rx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
366 void __iomem
*mbox
= tp
->regs
+ off
;
368 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
372 static inline void _tw32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
374 void __iomem
*mbox
= tp
->regs
+ off
;
376 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
378 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
382 #define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tp->regs + (reg))
383 #define tw32_rx_mbox(reg, val) _tw32_rx_mbox(tp, reg, val)
384 #define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val)
386 #define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val))
387 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
388 #define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg))
389 #define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg))
390 #define tr32(reg) readl(tp->regs + (reg))
391 #define tr16(reg) readw(tp->regs + (reg))
392 #define tr8(reg) readb(tp->regs + (reg))
394 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
398 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
399 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
400 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
402 /* Always leave this as zero. */
403 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
404 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
407 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
411 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
412 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
413 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
415 /* Always leave this as zero. */
416 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
417 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
420 static void tg3_disable_ints(struct tg3
*tp
)
422 tw32(TG3PCI_MISC_HOST_CTRL
,
423 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
424 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
425 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
428 static inline void tg3_cond_int(struct tg3
*tp
)
430 if (tp
->hw_status
->status
& SD_STATUS_UPDATED
)
431 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
434 static void tg3_enable_ints(struct tg3
*tp
)
436 tw32(TG3PCI_MISC_HOST_CTRL
,
437 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
438 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
439 (tp
->last_tag
<< 24));
440 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
445 static inline unsigned int tg3_has_work(struct tg3
*tp
)
447 struct tg3_hw_status
*sblk
= tp
->hw_status
;
448 unsigned int work_exists
= 0;
450 /* check for phy events */
451 if (!(tp
->tg3_flags
&
452 (TG3_FLAG_USE_LINKCHG_REG
|
453 TG3_FLAG_POLL_SERDES
))) {
454 if (sblk
->status
& SD_STATUS_LINK_CHG
)
457 /* check for RX/TX work to do */
458 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
||
459 sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
)
466 * similar to tg3_enable_ints, but it accurately determines whether there
467 * is new work pending and can return without flushing the PIO write
468 * which reenables interrupts
470 static void tg3_restart_ints(struct tg3
*tp
)
472 tw32(TG3PCI_MISC_HOST_CTRL
,
473 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
474 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
478 /* When doing tagged status, this work check is unnecessary.
479 * The last_tag we write above tells the chip which piece of
480 * work we've completed.
482 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
484 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
485 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
488 static inline void tg3_netif_stop(struct tg3
*tp
)
490 netif_poll_disable(tp
->dev
);
491 netif_tx_disable(tp
->dev
);
494 static inline void tg3_netif_start(struct tg3
*tp
)
496 netif_wake_queue(tp
->dev
);
497 /* NOTE: unconditional netif_wake_queue is only appropriate
498 * so long as all callers are assured to have free tx slots
499 * (such as after tg3_init_hw)
501 netif_poll_enable(tp
->dev
);
505 static void tg3_switch_clocks(struct tg3
*tp
)
507 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
510 orig_clock_ctrl
= clock_ctrl
;
511 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
512 CLOCK_CTRL_CLKRUN_OENABLE
|
514 tp
->pci_clock_ctrl
= clock_ctrl
;
516 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
517 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
518 tw32_f(TG3PCI_CLOCK_CTRL
,
519 clock_ctrl
| CLOCK_CTRL_625_CORE
);
522 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
523 tw32_f(TG3PCI_CLOCK_CTRL
,
525 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
));
527 tw32_f(TG3PCI_CLOCK_CTRL
,
528 clock_ctrl
| (CLOCK_CTRL_ALTCLK
));
531 tw32_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
);
535 #define PHY_BUSY_LOOPS 5000
537 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
543 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
545 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
551 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
552 MI_COM_PHY_ADDR_MASK
);
553 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
554 MI_COM_REG_ADDR_MASK
);
555 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
557 tw32_f(MAC_MI_COM
, frame_val
);
559 loops
= PHY_BUSY_LOOPS
;
562 frame_val
= tr32(MAC_MI_COM
);
564 if ((frame_val
& MI_COM_BUSY
) == 0) {
566 frame_val
= tr32(MAC_MI_COM
);
574 *val
= frame_val
& MI_COM_DATA_MASK
;
578 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
579 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
586 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
592 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
594 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
598 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
599 MI_COM_PHY_ADDR_MASK
);
600 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
601 MI_COM_REG_ADDR_MASK
);
602 frame_val
|= (val
& MI_COM_DATA_MASK
);
603 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
605 tw32_f(MAC_MI_COM
, frame_val
);
607 loops
= PHY_BUSY_LOOPS
;
610 frame_val
= tr32(MAC_MI_COM
);
611 if ((frame_val
& MI_COM_BUSY
) == 0) {
613 frame_val
= tr32(MAC_MI_COM
);
623 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
624 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
631 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
635 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
638 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
639 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
640 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
641 (val
| (1 << 15) | (1 << 4)));
644 static int tg3_bmcr_reset(struct tg3
*tp
)
649 /* OK, reset it, and poll the BMCR_RESET bit until it
650 * clears or we time out.
652 phy_control
= BMCR_RESET
;
653 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
659 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
663 if ((phy_control
& BMCR_RESET
) == 0) {
675 static int tg3_wait_macro_done(struct tg3
*tp
)
682 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
683 if ((tmp32
& 0x1000) == 0)
693 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
695 static const u32 test_pat
[4][6] = {
696 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
697 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
698 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
699 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
703 for (chan
= 0; chan
< 4; chan
++) {
706 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
707 (chan
* 0x2000) | 0x0200);
708 tg3_writephy(tp
, 0x16, 0x0002);
710 for (i
= 0; i
< 6; i
++)
711 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
714 tg3_writephy(tp
, 0x16, 0x0202);
715 if (tg3_wait_macro_done(tp
)) {
720 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
721 (chan
* 0x2000) | 0x0200);
722 tg3_writephy(tp
, 0x16, 0x0082);
723 if (tg3_wait_macro_done(tp
)) {
728 tg3_writephy(tp
, 0x16, 0x0802);
729 if (tg3_wait_macro_done(tp
)) {
734 for (i
= 0; i
< 6; i
+= 2) {
737 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
738 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
739 tg3_wait_macro_done(tp
)) {
745 if (low
!= test_pat
[chan
][i
] ||
746 high
!= test_pat
[chan
][i
+1]) {
747 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
748 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
749 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
759 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
763 for (chan
= 0; chan
< 4; chan
++) {
766 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
767 (chan
* 0x2000) | 0x0200);
768 tg3_writephy(tp
, 0x16, 0x0002);
769 for (i
= 0; i
< 6; i
++)
770 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
771 tg3_writephy(tp
, 0x16, 0x0202);
772 if (tg3_wait_macro_done(tp
))
779 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
781 u32 reg32
, phy9_orig
;
782 int retries
, do_phy_reset
, err
;
788 err
= tg3_bmcr_reset(tp
);
794 /* Disable transmitter and interrupt. */
795 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
799 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
801 /* Set full-duplex, 1000 mbps. */
802 tg3_writephy(tp
, MII_BMCR
,
803 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
805 /* Set to master mode. */
806 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
809 tg3_writephy(tp
, MII_TG3_CTRL
,
810 (MII_TG3_CTRL_AS_MASTER
|
811 MII_TG3_CTRL_ENABLE_AS_MASTER
));
813 /* Enable SM_DSP_CLOCK and 6dB. */
814 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
816 /* Block the PHY control access. */
817 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
818 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
820 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
825 err
= tg3_phy_reset_chanpat(tp
);
829 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
830 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
832 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
833 tg3_writephy(tp
, 0x16, 0x0000);
835 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
836 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
837 /* Set Extended packet length bit for jumbo frames */
838 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
841 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
844 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
846 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
848 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
855 /* This will reset the tigon3 PHY if there is no valid
856 * link unless the FORCE argument is non-zero.
858 static int tg3_phy_reset(struct tg3
*tp
)
863 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
864 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
868 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
869 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
870 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
871 err
= tg3_phy_reset_5703_4_5(tp
);
877 err
= tg3_bmcr_reset(tp
);
882 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
883 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
884 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
885 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
886 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
887 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
888 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
890 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
891 tg3_writephy(tp
, 0x1c, 0x8d68);
892 tg3_writephy(tp
, 0x1c, 0x8d68);
894 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
895 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
896 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
897 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
898 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
899 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
900 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
901 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
902 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
904 /* Set Extended packet length bit (bit 14) on all chips that */
905 /* support jumbo frames */
906 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
907 /* Cannot do read-modify-write on 5401 */
908 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
909 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
912 /* Set bit 14 with read-modify-write to preserve other bits */
913 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
914 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
915 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
918 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
919 * jumbo frames transmission.
921 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
924 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
925 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
926 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
929 tg3_phy_set_wirespeed(tp
);
933 static void tg3_frob_aux_power(struct tg3
*tp
)
935 struct tg3
*tp_peer
= tp
;
937 if ((tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) != 0)
940 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
941 tp_peer
= pci_get_drvdata(tp
->pdev_peer
);
947 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
948 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0) {
949 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
950 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
951 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
952 (GRC_LCLCTRL_GPIO_OE0
|
953 GRC_LCLCTRL_GPIO_OE1
|
954 GRC_LCLCTRL_GPIO_OE2
|
955 GRC_LCLCTRL_GPIO_OUTPUT0
|
956 GRC_LCLCTRL_GPIO_OUTPUT1
));
963 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
966 /* On 5753 and variants, GPIO2 cannot be used. */
967 no_gpio2
= tp
->nic_sram_data_cfg
&
968 NIC_SRAM_DATA_CFG_NO_GPIO2
;
970 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
971 GRC_LCLCTRL_GPIO_OE1
|
972 GRC_LCLCTRL_GPIO_OE2
|
973 GRC_LCLCTRL_GPIO_OUTPUT1
|
974 GRC_LCLCTRL_GPIO_OUTPUT2
;
976 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
977 GRC_LCLCTRL_GPIO_OUTPUT2
);
979 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
983 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
985 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
990 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
991 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
997 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
998 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
1000 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
1003 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1004 (GRC_LCLCTRL_GPIO_OE1
|
1005 GRC_LCLCTRL_GPIO_OUTPUT1
));
1008 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1009 (GRC_LCLCTRL_GPIO_OE1
));
1012 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1013 (GRC_LCLCTRL_GPIO_OE1
|
1014 GRC_LCLCTRL_GPIO_OUTPUT1
));
1020 static int tg3_setup_phy(struct tg3
*, int);
1022 #define RESET_KIND_SHUTDOWN 0
1023 #define RESET_KIND_INIT 1
1024 #define RESET_KIND_SUSPEND 2
1026 static void tg3_write_sig_post_reset(struct tg3
*, int);
1027 static int tg3_halt_cpu(struct tg3
*, u32
);
1029 static int tg3_set_power_state(struct tg3
*tp
, int state
)
1032 u16 power_control
, power_caps
;
1033 int pm
= tp
->pm_cap
;
1035 /* Make sure register accesses (indirect or otherwise)
1036 * will function correctly.
1038 pci_write_config_dword(tp
->pdev
,
1039 TG3PCI_MISC_HOST_CTRL
,
1040 tp
->misc_host_ctrl
);
1042 pci_read_config_word(tp
->pdev
,
1045 power_control
|= PCI_PM_CTRL_PME_STATUS
;
1046 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
1050 pci_write_config_word(tp
->pdev
,
1053 udelay(100); /* Delay after power state change */
1055 /* Switch out of Vaux if it is not a LOM */
1056 if (!(tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)) {
1057 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
1076 printk(KERN_WARNING PFX
"%s: Invalid power state (%d) "
1078 tp
->dev
->name
, state
);
1082 power_control
|= PCI_PM_CTRL_PME_ENABLE
;
1084 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
1085 tw32(TG3PCI_MISC_HOST_CTRL
,
1086 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
1088 if (tp
->link_config
.phy_is_low_power
== 0) {
1089 tp
->link_config
.phy_is_low_power
= 1;
1090 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
1091 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
1092 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
1095 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
1096 tp
->link_config
.speed
= SPEED_10
;
1097 tp
->link_config
.duplex
= DUPLEX_HALF
;
1098 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
1099 tg3_setup_phy(tp
, 0);
1102 pci_read_config_word(tp
->pdev
, pm
+ PCI_PM_PMC
, &power_caps
);
1104 if (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) {
1107 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
1108 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
1111 mac_mode
= MAC_MODE_PORT_MODE_MII
;
1113 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
||
1114 !(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
))
1115 mac_mode
|= MAC_MODE_LINK_POLARITY
;
1117 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
1120 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
1121 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
1123 if (((power_caps
& PCI_PM_CAP_PME_D3cold
) &&
1124 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
)))
1125 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
1127 tw32_f(MAC_MODE
, mac_mode
);
1130 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
1134 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
1135 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1136 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
1139 base_val
= tp
->pci_clock_ctrl
;
1140 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
1141 CLOCK_CTRL_TXCLK_DISABLE
);
1143 tw32_f(TG3PCI_CLOCK_CTRL
, base_val
|
1145 CLOCK_CTRL_PWRDOWN_PLL133
);
1147 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
1148 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
1149 u32 newbits1
, newbits2
;
1151 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1152 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1153 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
1154 CLOCK_CTRL_TXCLK_DISABLE
|
1156 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
1157 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
1158 newbits1
= CLOCK_CTRL_625_CORE
;
1159 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
1161 newbits1
= CLOCK_CTRL_ALTCLK
;
1162 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
1165 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
);
1168 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
);
1171 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
1174 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1175 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1176 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
1177 CLOCK_CTRL_TXCLK_DISABLE
|
1178 CLOCK_CTRL_44MHZ_CORE
);
1180 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
1183 tw32_f(TG3PCI_CLOCK_CTRL
,
1184 tp
->pci_clock_ctrl
| newbits3
);
1189 tg3_frob_aux_power(tp
);
1191 /* Workaround for unstable PLL clock */
1192 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
1193 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
1194 u32 val
= tr32(0x7d00);
1196 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1198 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1199 tg3_halt_cpu(tp
, RX_CPU_BASE
);
1202 /* Finally, set the new power state. */
1203 pci_write_config_word(tp
->pdev
, pm
+ PCI_PM_CTRL
, power_control
);
1204 udelay(100); /* Delay after power state change */
1206 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
1211 static void tg3_link_report(struct tg3
*tp
)
1213 if (!netif_carrier_ok(tp
->dev
)) {
1214 printk(KERN_INFO PFX
"%s: Link is down.\n", tp
->dev
->name
);
1216 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
1218 (tp
->link_config
.active_speed
== SPEED_1000
?
1220 (tp
->link_config
.active_speed
== SPEED_100
?
1222 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1225 printk(KERN_INFO PFX
"%s: Flow control is %s for TX and "
1228 (tp
->tg3_flags
& TG3_FLAG_TX_PAUSE
) ? "on" : "off",
1229 (tp
->tg3_flags
& TG3_FLAG_RX_PAUSE
) ? "on" : "off");
1233 static void tg3_setup_flow_control(struct tg3
*tp
, u32 local_adv
, u32 remote_adv
)
1235 u32 new_tg3_flags
= 0;
1236 u32 old_rx_mode
= tp
->rx_mode
;
1237 u32 old_tx_mode
= tp
->tx_mode
;
1239 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) {
1240 if (local_adv
& ADVERTISE_PAUSE_CAP
) {
1241 if (local_adv
& ADVERTISE_PAUSE_ASYM
) {
1242 if (remote_adv
& LPA_PAUSE_CAP
)
1244 (TG3_FLAG_RX_PAUSE
|
1246 else if (remote_adv
& LPA_PAUSE_ASYM
)
1248 (TG3_FLAG_RX_PAUSE
);
1250 if (remote_adv
& LPA_PAUSE_CAP
)
1252 (TG3_FLAG_RX_PAUSE
|
1255 } else if (local_adv
& ADVERTISE_PAUSE_ASYM
) {
1256 if ((remote_adv
& LPA_PAUSE_CAP
) &&
1257 (remote_adv
& LPA_PAUSE_ASYM
))
1258 new_tg3_flags
|= TG3_FLAG_TX_PAUSE
;
1261 tp
->tg3_flags
&= ~(TG3_FLAG_RX_PAUSE
| TG3_FLAG_TX_PAUSE
);
1262 tp
->tg3_flags
|= new_tg3_flags
;
1264 new_tg3_flags
= tp
->tg3_flags
;
1267 if (new_tg3_flags
& TG3_FLAG_RX_PAUSE
)
1268 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1270 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1272 if (old_rx_mode
!= tp
->rx_mode
) {
1273 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1276 if (new_tg3_flags
& TG3_FLAG_TX_PAUSE
)
1277 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1279 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1281 if (old_tx_mode
!= tp
->tx_mode
) {
1282 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1286 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
1288 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
1289 case MII_TG3_AUX_STAT_10HALF
:
1291 *duplex
= DUPLEX_HALF
;
1294 case MII_TG3_AUX_STAT_10FULL
:
1296 *duplex
= DUPLEX_FULL
;
1299 case MII_TG3_AUX_STAT_100HALF
:
1301 *duplex
= DUPLEX_HALF
;
1304 case MII_TG3_AUX_STAT_100FULL
:
1306 *duplex
= DUPLEX_FULL
;
1309 case MII_TG3_AUX_STAT_1000HALF
:
1310 *speed
= SPEED_1000
;
1311 *duplex
= DUPLEX_HALF
;
1314 case MII_TG3_AUX_STAT_1000FULL
:
1315 *speed
= SPEED_1000
;
1316 *duplex
= DUPLEX_FULL
;
1320 *speed
= SPEED_INVALID
;
1321 *duplex
= DUPLEX_INVALID
;
1326 static void tg3_phy_copper_begin(struct tg3
*tp
)
1331 if (tp
->link_config
.phy_is_low_power
) {
1332 /* Entering low power mode. Disable gigabit and
1333 * 100baseT advertisements.
1335 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
1337 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1338 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
1339 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
1340 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1342 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
1343 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
1344 tp
->link_config
.advertising
=
1345 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
1346 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
1347 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
1348 ADVERTISED_Autoneg
| ADVERTISED_MII
);
1350 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
1351 tp
->link_config
.advertising
&=
1352 ~(ADVERTISED_1000baseT_Half
|
1353 ADVERTISED_1000baseT_Full
);
1355 new_adv
= (ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
1356 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
1357 new_adv
|= ADVERTISE_10HALF
;
1358 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
1359 new_adv
|= ADVERTISE_10FULL
;
1360 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
1361 new_adv
|= ADVERTISE_100HALF
;
1362 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
1363 new_adv
|= ADVERTISE_100FULL
;
1364 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
1366 if (tp
->link_config
.advertising
&
1367 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
1369 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
1370 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
1371 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
1372 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
1373 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
1374 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
1375 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
1376 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
1377 MII_TG3_CTRL_ENABLE_AS_MASTER
);
1378 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
1380 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
1383 /* Asking for a specific link mode. */
1384 if (tp
->link_config
.speed
== SPEED_1000
) {
1385 new_adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1386 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
1388 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
1389 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
1391 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
1392 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
1393 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
1394 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
1395 MII_TG3_CTRL_ENABLE_AS_MASTER
);
1396 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
1398 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
1400 new_adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1401 if (tp
->link_config
.speed
== SPEED_100
) {
1402 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
1403 new_adv
|= ADVERTISE_100FULL
;
1405 new_adv
|= ADVERTISE_100HALF
;
1407 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
1408 new_adv
|= ADVERTISE_10FULL
;
1410 new_adv
|= ADVERTISE_10HALF
;
1412 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
1416 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
1417 tp
->link_config
.speed
!= SPEED_INVALID
) {
1418 u32 bmcr
, orig_bmcr
;
1420 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
1421 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
1424 switch (tp
->link_config
.speed
) {
1430 bmcr
|= BMCR_SPEED100
;
1434 bmcr
|= TG3_BMCR_SPEED1000
;
1438 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
1439 bmcr
|= BMCR_FULLDPLX
;
1441 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
1442 (bmcr
!= orig_bmcr
)) {
1443 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
1444 for (i
= 0; i
< 1500; i
++) {
1448 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
1449 tg3_readphy(tp
, MII_BMSR
, &tmp
))
1451 if (!(tmp
& BMSR_LSTATUS
)) {
1456 tg3_writephy(tp
, MII_BMCR
, bmcr
);
1460 tg3_writephy(tp
, MII_BMCR
,
1461 BMCR_ANENABLE
| BMCR_ANRESTART
);
1465 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
1469 /* Turn off tap power management. */
1470 /* Set Extended packet length bit */
1471 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1473 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
1474 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
1476 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
1477 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
1479 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
1480 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
1482 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
1483 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
1485 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1486 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
1493 static int tg3_copper_is_advertising_all(struct tg3
*tp
)
1495 u32 adv_reg
, all_mask
;
1497 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
1500 all_mask
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1501 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1502 if ((adv_reg
& all_mask
) != all_mask
)
1504 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1507 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
1510 all_mask
= (MII_TG3_CTRL_ADV_1000_HALF
|
1511 MII_TG3_CTRL_ADV_1000_FULL
);
1512 if ((tg3_ctrl
& all_mask
) != all_mask
)
1518 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
1520 int current_link_up
;
1529 (MAC_STATUS_SYNC_CHANGED
|
1530 MAC_STATUS_CFG_CHANGED
|
1531 MAC_STATUS_MI_COMPLETION
|
1532 MAC_STATUS_LNKSTATE_CHANGED
));
1535 tp
->mi_mode
= MAC_MI_MODE_BASE
;
1536 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1539 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
1541 /* Some third-party PHYs need to be reset on link going
1544 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1545 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1546 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
1547 netif_carrier_ok(tp
->dev
)) {
1548 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
1549 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
1550 !(bmsr
& BMSR_LSTATUS
))
1556 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
1557 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
1558 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
1559 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
1562 if (!(bmsr
& BMSR_LSTATUS
)) {
1563 err
= tg3_init_5401phy_dsp(tp
);
1567 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
1568 for (i
= 0; i
< 1000; i
++) {
1570 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
1571 (bmsr
& BMSR_LSTATUS
)) {
1577 if ((tp
->phy_id
& PHY_ID_REV_MASK
) == PHY_REV_BCM5401_B0
&&
1578 !(bmsr
& BMSR_LSTATUS
) &&
1579 tp
->link_config
.active_speed
== SPEED_1000
) {
1580 err
= tg3_phy_reset(tp
);
1582 err
= tg3_init_5401phy_dsp(tp
);
1587 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
1588 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
1589 /* 5701 {A0,B0} CRC bug workaround */
1590 tg3_writephy(tp
, 0x15, 0x0a75);
1591 tg3_writephy(tp
, 0x1c, 0x8c68);
1592 tg3_writephy(tp
, 0x1c, 0x8d68);
1593 tg3_writephy(tp
, 0x1c, 0x8c68);
1596 /* Clear pending interrupts... */
1597 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
1598 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
1600 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
1601 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
1603 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
1605 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1606 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1607 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
1608 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
1609 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
1611 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
1614 current_link_up
= 0;
1615 current_speed
= SPEED_INVALID
;
1616 current_duplex
= DUPLEX_INVALID
;
1618 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
1621 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
1622 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
1623 if (!(val
& (1 << 10))) {
1625 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
1631 for (i
= 0; i
< 100; i
++) {
1632 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
1633 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
1634 (bmsr
& BMSR_LSTATUS
))
1639 if (bmsr
& BMSR_LSTATUS
) {
1642 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
1643 for (i
= 0; i
< 2000; i
++) {
1645 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
1650 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
1655 for (i
= 0; i
< 200; i
++) {
1656 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
1657 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
1659 if (bmcr
&& bmcr
!= 0x7fff)
1664 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
1665 if (bmcr
& BMCR_ANENABLE
) {
1666 current_link_up
= 1;
1668 /* Force autoneg restart if we are exiting
1671 if (!tg3_copper_is_advertising_all(tp
))
1672 current_link_up
= 0;
1674 current_link_up
= 0;
1677 if (!(bmcr
& BMCR_ANENABLE
) &&
1678 tp
->link_config
.speed
== current_speed
&&
1679 tp
->link_config
.duplex
== current_duplex
) {
1680 current_link_up
= 1;
1682 current_link_up
= 0;
1686 tp
->link_config
.active_speed
= current_speed
;
1687 tp
->link_config
.active_duplex
= current_duplex
;
1690 if (current_link_up
== 1 &&
1691 (tp
->link_config
.active_duplex
== DUPLEX_FULL
) &&
1692 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
1693 u32 local_adv
, remote_adv
;
1695 if (tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
))
1697 local_adv
&= (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
1699 if (tg3_readphy(tp
, MII_LPA
, &remote_adv
))
1702 remote_adv
&= (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
1704 /* If we are not advertising full pause capability,
1705 * something is wrong. Bring the link down and reconfigure.
1707 if (local_adv
!= ADVERTISE_PAUSE_CAP
) {
1708 current_link_up
= 0;
1710 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
1714 if (current_link_up
== 0) {
1717 tg3_phy_copper_begin(tp
);
1719 tg3_readphy(tp
, MII_BMSR
, &tmp
);
1720 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
1721 (tmp
& BMSR_LSTATUS
))
1722 current_link_up
= 1;
1725 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
1726 if (current_link_up
== 1) {
1727 if (tp
->link_config
.active_speed
== SPEED_100
||
1728 tp
->link_config
.active_speed
== SPEED_10
)
1729 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1731 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1733 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1735 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
1736 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
1737 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1739 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
1740 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
1741 if ((tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
) ||
1742 (current_link_up
== 1 &&
1743 tp
->link_config
.active_speed
== SPEED_10
))
1744 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
1746 if (current_link_up
== 1)
1747 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
1750 /* ??? Without this setting Netgear GA302T PHY does not
1751 * ??? send/receive packets...
1753 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
&&
1754 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
1755 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
1756 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1760 tw32_f(MAC_MODE
, tp
->mac_mode
);
1763 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
1764 /* Polled via timer. */
1765 tw32_f(MAC_EVENT
, 0);
1767 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
1771 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
1772 current_link_up
== 1 &&
1773 tp
->link_config
.active_speed
== SPEED_1000
&&
1774 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
1775 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
1778 (MAC_STATUS_SYNC_CHANGED
|
1779 MAC_STATUS_CFG_CHANGED
));
1782 NIC_SRAM_FIRMWARE_MBOX
,
1783 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
1786 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
1787 if (current_link_up
)
1788 netif_carrier_on(tp
->dev
);
1790 netif_carrier_off(tp
->dev
);
1791 tg3_link_report(tp
);
1797 struct tg3_fiber_aneginfo
{
1799 #define ANEG_STATE_UNKNOWN 0
1800 #define ANEG_STATE_AN_ENABLE 1
1801 #define ANEG_STATE_RESTART_INIT 2
1802 #define ANEG_STATE_RESTART 3
1803 #define ANEG_STATE_DISABLE_LINK_OK 4
1804 #define ANEG_STATE_ABILITY_DETECT_INIT 5
1805 #define ANEG_STATE_ABILITY_DETECT 6
1806 #define ANEG_STATE_ACK_DETECT_INIT 7
1807 #define ANEG_STATE_ACK_DETECT 8
1808 #define ANEG_STATE_COMPLETE_ACK_INIT 9
1809 #define ANEG_STATE_COMPLETE_ACK 10
1810 #define ANEG_STATE_IDLE_DETECT_INIT 11
1811 #define ANEG_STATE_IDLE_DETECT 12
1812 #define ANEG_STATE_LINK_OK 13
1813 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1814 #define ANEG_STATE_NEXT_PAGE_WAIT 15
1817 #define MR_AN_ENABLE 0x00000001
1818 #define MR_RESTART_AN 0x00000002
1819 #define MR_AN_COMPLETE 0x00000004
1820 #define MR_PAGE_RX 0x00000008
1821 #define MR_NP_LOADED 0x00000010
1822 #define MR_TOGGLE_TX 0x00000020
1823 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
1824 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
1825 #define MR_LP_ADV_SYM_PAUSE 0x00000100
1826 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
1827 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1828 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1829 #define MR_LP_ADV_NEXT_PAGE 0x00001000
1830 #define MR_TOGGLE_RX 0x00002000
1831 #define MR_NP_RX 0x00004000
1833 #define MR_LINK_OK 0x80000000
1835 unsigned long link_time
, cur_time
;
1837 u32 ability_match_cfg
;
1838 int ability_match_count
;
1840 char ability_match
, idle_match
, ack_match
;
1842 u32 txconfig
, rxconfig
;
1843 #define ANEG_CFG_NP 0x00000080
1844 #define ANEG_CFG_ACK 0x00000040
1845 #define ANEG_CFG_RF2 0x00000020
1846 #define ANEG_CFG_RF1 0x00000010
1847 #define ANEG_CFG_PS2 0x00000001
1848 #define ANEG_CFG_PS1 0x00008000
1849 #define ANEG_CFG_HD 0x00004000
1850 #define ANEG_CFG_FD 0x00002000
1851 #define ANEG_CFG_INVAL 0x00001f06
1856 #define ANEG_TIMER_ENAB 2
1857 #define ANEG_FAILED -1
1859 #define ANEG_STATE_SETTLE_TIME 10000
1861 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
1862 struct tg3_fiber_aneginfo
*ap
)
1864 unsigned long delta
;
1868 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
1872 ap
->ability_match_cfg
= 0;
1873 ap
->ability_match_count
= 0;
1874 ap
->ability_match
= 0;
1880 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
1881 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
1883 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
1884 ap
->ability_match_cfg
= rx_cfg_reg
;
1885 ap
->ability_match
= 0;
1886 ap
->ability_match_count
= 0;
1888 if (++ap
->ability_match_count
> 1) {
1889 ap
->ability_match
= 1;
1890 ap
->ability_match_cfg
= rx_cfg_reg
;
1893 if (rx_cfg_reg
& ANEG_CFG_ACK
)
1901 ap
->ability_match_cfg
= 0;
1902 ap
->ability_match_count
= 0;
1903 ap
->ability_match
= 0;
1909 ap
->rxconfig
= rx_cfg_reg
;
1913 case ANEG_STATE_UNKNOWN
:
1914 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
1915 ap
->state
= ANEG_STATE_AN_ENABLE
;
1918 case ANEG_STATE_AN_ENABLE
:
1919 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
1920 if (ap
->flags
& MR_AN_ENABLE
) {
1923 ap
->ability_match_cfg
= 0;
1924 ap
->ability_match_count
= 0;
1925 ap
->ability_match
= 0;
1929 ap
->state
= ANEG_STATE_RESTART_INIT
;
1931 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
1935 case ANEG_STATE_RESTART_INIT
:
1936 ap
->link_time
= ap
->cur_time
;
1937 ap
->flags
&= ~(MR_NP_LOADED
);
1939 tw32(MAC_TX_AUTO_NEG
, 0);
1940 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
1941 tw32_f(MAC_MODE
, tp
->mac_mode
);
1944 ret
= ANEG_TIMER_ENAB
;
1945 ap
->state
= ANEG_STATE_RESTART
;
1948 case ANEG_STATE_RESTART
:
1949 delta
= ap
->cur_time
- ap
->link_time
;
1950 if (delta
> ANEG_STATE_SETTLE_TIME
) {
1951 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
1953 ret
= ANEG_TIMER_ENAB
;
1957 case ANEG_STATE_DISABLE_LINK_OK
:
1961 case ANEG_STATE_ABILITY_DETECT_INIT
:
1962 ap
->flags
&= ~(MR_TOGGLE_TX
);
1963 ap
->txconfig
= (ANEG_CFG_FD
| ANEG_CFG_PS1
);
1964 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
1965 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
1966 tw32_f(MAC_MODE
, tp
->mac_mode
);
1969 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
1972 case ANEG_STATE_ABILITY_DETECT
:
1973 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0) {
1974 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
1978 case ANEG_STATE_ACK_DETECT_INIT
:
1979 ap
->txconfig
|= ANEG_CFG_ACK
;
1980 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
1981 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
1982 tw32_f(MAC_MODE
, tp
->mac_mode
);
1985 ap
->state
= ANEG_STATE_ACK_DETECT
;
1988 case ANEG_STATE_ACK_DETECT
:
1989 if (ap
->ack_match
!= 0) {
1990 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
1991 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
1992 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
1994 ap
->state
= ANEG_STATE_AN_ENABLE
;
1996 } else if (ap
->ability_match
!= 0 &&
1997 ap
->rxconfig
== 0) {
1998 ap
->state
= ANEG_STATE_AN_ENABLE
;
2002 case ANEG_STATE_COMPLETE_ACK_INIT
:
2003 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
2007 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
2008 MR_LP_ADV_HALF_DUPLEX
|
2009 MR_LP_ADV_SYM_PAUSE
|
2010 MR_LP_ADV_ASYM_PAUSE
|
2011 MR_LP_ADV_REMOTE_FAULT1
|
2012 MR_LP_ADV_REMOTE_FAULT2
|
2013 MR_LP_ADV_NEXT_PAGE
|
2016 if (ap
->rxconfig
& ANEG_CFG_FD
)
2017 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
2018 if (ap
->rxconfig
& ANEG_CFG_HD
)
2019 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
2020 if (ap
->rxconfig
& ANEG_CFG_PS1
)
2021 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
2022 if (ap
->rxconfig
& ANEG_CFG_PS2
)
2023 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
2024 if (ap
->rxconfig
& ANEG_CFG_RF1
)
2025 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
2026 if (ap
->rxconfig
& ANEG_CFG_RF2
)
2027 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
2028 if (ap
->rxconfig
& ANEG_CFG_NP
)
2029 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
2031 ap
->link_time
= ap
->cur_time
;
2033 ap
->flags
^= (MR_TOGGLE_TX
);
2034 if (ap
->rxconfig
& 0x0008)
2035 ap
->flags
|= MR_TOGGLE_RX
;
2036 if (ap
->rxconfig
& ANEG_CFG_NP
)
2037 ap
->flags
|= MR_NP_RX
;
2038 ap
->flags
|= MR_PAGE_RX
;
2040 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
2041 ret
= ANEG_TIMER_ENAB
;
2044 case ANEG_STATE_COMPLETE_ACK
:
2045 if (ap
->ability_match
!= 0 &&
2046 ap
->rxconfig
== 0) {
2047 ap
->state
= ANEG_STATE_AN_ENABLE
;
2050 delta
= ap
->cur_time
- ap
->link_time
;
2051 if (delta
> ANEG_STATE_SETTLE_TIME
) {
2052 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
2053 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
2055 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
2056 !(ap
->flags
& MR_NP_RX
)) {
2057 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
2065 case ANEG_STATE_IDLE_DETECT_INIT
:
2066 ap
->link_time
= ap
->cur_time
;
2067 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
2068 tw32_f(MAC_MODE
, tp
->mac_mode
);
2071 ap
->state
= ANEG_STATE_IDLE_DETECT
;
2072 ret
= ANEG_TIMER_ENAB
;
2075 case ANEG_STATE_IDLE_DETECT
:
2076 if (ap
->ability_match
!= 0 &&
2077 ap
->rxconfig
== 0) {
2078 ap
->state
= ANEG_STATE_AN_ENABLE
;
2081 delta
= ap
->cur_time
- ap
->link_time
;
2082 if (delta
> ANEG_STATE_SETTLE_TIME
) {
2083 /* XXX another gem from the Broadcom driver :( */
2084 ap
->state
= ANEG_STATE_LINK_OK
;
2088 case ANEG_STATE_LINK_OK
:
2089 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
2093 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
2094 /* ??? unimplemented */
2097 case ANEG_STATE_NEXT_PAGE_WAIT
:
2098 /* ??? unimplemented */
2109 static int fiber_autoneg(struct tg3
*tp
, u32
*flags
)
2112 struct tg3_fiber_aneginfo aninfo
;
2113 int status
= ANEG_FAILED
;
2117 tw32_f(MAC_TX_AUTO_NEG
, 0);
2119 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
2120 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
2123 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
2126 memset(&aninfo
, 0, sizeof(aninfo
));
2127 aninfo
.flags
|= MR_AN_ENABLE
;
2128 aninfo
.state
= ANEG_STATE_UNKNOWN
;
2129 aninfo
.cur_time
= 0;
2131 while (++tick
< 195000) {
2132 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
2133 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
2139 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
2140 tw32_f(MAC_MODE
, tp
->mac_mode
);
2143 *flags
= aninfo
.flags
;
2145 if (status
== ANEG_DONE
&&
2146 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
2147 MR_LP_ADV_FULL_DUPLEX
)))
2153 static void tg3_init_bcm8002(struct tg3
*tp
)
2155 u32 mac_status
= tr32(MAC_STATUS
);
2158 /* Reset when initting first time or we have a link. */
2159 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
2160 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
2163 /* Set PLL lock range. */
2164 tg3_writephy(tp
, 0x16, 0x8007);
2167 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
2169 /* Wait for reset to complete. */
2170 /* XXX schedule_timeout() ... */
2171 for (i
= 0; i
< 500; i
++)
2174 /* Config mode; select PMA/Ch 1 regs. */
2175 tg3_writephy(tp
, 0x10, 0x8411);
2177 /* Enable auto-lock and comdet, select txclk for tx. */
2178 tg3_writephy(tp
, 0x11, 0x0a10);
2180 tg3_writephy(tp
, 0x18, 0x00a0);
2181 tg3_writephy(tp
, 0x16, 0x41ff);
2183 /* Assert and deassert POR. */
2184 tg3_writephy(tp
, 0x13, 0x0400);
2186 tg3_writephy(tp
, 0x13, 0x0000);
2188 tg3_writephy(tp
, 0x11, 0x0a50);
2190 tg3_writephy(tp
, 0x11, 0x0a10);
2192 /* Wait for signal to stabilize */
2193 /* XXX schedule_timeout() ... */
2194 for (i
= 0; i
< 15000; i
++)
2197 /* Deselect the channel register so we can read the PHYID
2200 tg3_writephy(tp
, 0x10, 0x8011);
2203 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
2205 u32 sg_dig_ctrl
, sg_dig_status
;
2206 u32 serdes_cfg
, expected_sg_dig_ctrl
;
2207 int workaround
, port_a
;
2208 int current_link_up
;
2211 expected_sg_dig_ctrl
= 0;
2214 current_link_up
= 0;
2216 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
2217 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
2219 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
2222 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2223 /* preserve bits 20-23 for voltage regulator */
2224 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
2227 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2229 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
2230 if (sg_dig_ctrl
& (1 << 31)) {
2232 u32 val
= serdes_cfg
;
2238 tw32_f(MAC_SERDES_CFG
, val
);
2240 tw32_f(SG_DIG_CTRL
, 0x01388400);
2242 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
2243 tg3_setup_flow_control(tp
, 0, 0);
2244 current_link_up
= 1;
2249 /* Want auto-negotiation. */
2250 expected_sg_dig_ctrl
= 0x81388400;
2252 /* Pause capability */
2253 expected_sg_dig_ctrl
|= (1 << 11);
2255 /* Asymettric pause */
2256 expected_sg_dig_ctrl
|= (1 << 12);
2258 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
2260 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
2261 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| (1 << 30));
2263 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
2265 tp
->tg3_flags2
|= TG3_FLG2_PHY_JUST_INITTED
;
2266 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
2267 MAC_STATUS_SIGNAL_DET
)) {
2270 /* Giver time to negotiate (~200ms) */
2271 for (i
= 0; i
< 40000; i
++) {
2272 sg_dig_status
= tr32(SG_DIG_STATUS
);
2273 if (sg_dig_status
& (0x3))
2277 mac_status
= tr32(MAC_STATUS
);
2279 if ((sg_dig_status
& (1 << 1)) &&
2280 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
2281 u32 local_adv
, remote_adv
;
2283 local_adv
= ADVERTISE_PAUSE_CAP
;
2285 if (sg_dig_status
& (1 << 19))
2286 remote_adv
|= LPA_PAUSE_CAP
;
2287 if (sg_dig_status
& (1 << 20))
2288 remote_adv
|= LPA_PAUSE_ASYM
;
2290 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
2291 current_link_up
= 1;
2292 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_JUST_INITTED
;
2293 } else if (!(sg_dig_status
& (1 << 1))) {
2294 if (tp
->tg3_flags2
& TG3_FLG2_PHY_JUST_INITTED
)
2295 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_JUST_INITTED
;
2298 u32 val
= serdes_cfg
;
2305 tw32_f(MAC_SERDES_CFG
, val
);
2308 tw32_f(SG_DIG_CTRL
, 0x01388400);
2311 /* Link parallel detection - link is up */
2312 /* only if we have PCS_SYNC and not */
2313 /* receiving config code words */
2314 mac_status
= tr32(MAC_STATUS
);
2315 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
2316 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
2317 tg3_setup_flow_control(tp
, 0, 0);
2318 current_link_up
= 1;
2325 return current_link_up
;
2328 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
2330 int current_link_up
= 0;
2332 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
)) {
2333 tp
->tg3_flags
&= ~TG3_FLAG_GOT_SERDES_FLOWCTL
;
2337 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
2341 if (fiber_autoneg(tp
, &flags
)) {
2342 u32 local_adv
, remote_adv
;
2344 local_adv
= ADVERTISE_PAUSE_CAP
;
2346 if (flags
& MR_LP_ADV_SYM_PAUSE
)
2347 remote_adv
|= LPA_PAUSE_CAP
;
2348 if (flags
& MR_LP_ADV_ASYM_PAUSE
)
2349 remote_adv
|= LPA_PAUSE_ASYM
;
2351 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
2353 tp
->tg3_flags
|= TG3_FLAG_GOT_SERDES_FLOWCTL
;
2354 current_link_up
= 1;
2356 for (i
= 0; i
< 30; i
++) {
2359 (MAC_STATUS_SYNC_CHANGED
|
2360 MAC_STATUS_CFG_CHANGED
));
2362 if ((tr32(MAC_STATUS
) &
2363 (MAC_STATUS_SYNC_CHANGED
|
2364 MAC_STATUS_CFG_CHANGED
)) == 0)
2368 mac_status
= tr32(MAC_STATUS
);
2369 if (current_link_up
== 0 &&
2370 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
2371 !(mac_status
& MAC_STATUS_RCVD_CFG
))
2372 current_link_up
= 1;
2374 /* Forcing 1000FD link up. */
2375 current_link_up
= 1;
2376 tp
->tg3_flags
|= TG3_FLAG_GOT_SERDES_FLOWCTL
;
2378 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
2383 return current_link_up
;
2386 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
2389 u16 orig_active_speed
;
2390 u8 orig_active_duplex
;
2392 int current_link_up
;
2396 (tp
->tg3_flags
& (TG3_FLAG_RX_PAUSE
|
2397 TG3_FLAG_TX_PAUSE
));
2398 orig_active_speed
= tp
->link_config
.active_speed
;
2399 orig_active_duplex
= tp
->link_config
.active_duplex
;
2401 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
2402 netif_carrier_ok(tp
->dev
) &&
2403 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
2404 mac_status
= tr32(MAC_STATUS
);
2405 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
2406 MAC_STATUS_SIGNAL_DET
|
2407 MAC_STATUS_CFG_CHANGED
|
2408 MAC_STATUS_RCVD_CFG
);
2409 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
2410 MAC_STATUS_SIGNAL_DET
)) {
2411 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
2412 MAC_STATUS_CFG_CHANGED
));
2417 tw32_f(MAC_TX_AUTO_NEG
, 0);
2419 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
2420 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
2421 tw32_f(MAC_MODE
, tp
->mac_mode
);
2424 if (tp
->phy_id
== PHY_ID_BCM8002
)
2425 tg3_init_bcm8002(tp
);
2427 /* Enable link change event even when serdes polling. */
2428 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
2431 current_link_up
= 0;
2432 mac_status
= tr32(MAC_STATUS
);
2434 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
2435 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
2437 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
2439 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2440 tw32_f(MAC_MODE
, tp
->mac_mode
);
2443 tp
->hw_status
->status
=
2444 (SD_STATUS_UPDATED
|
2445 (tp
->hw_status
->status
& ~SD_STATUS_LINK_CHG
));
2447 for (i
= 0; i
< 100; i
++) {
2448 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
2449 MAC_STATUS_CFG_CHANGED
));
2451 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
2452 MAC_STATUS_CFG_CHANGED
)) == 0)
2456 mac_status
= tr32(MAC_STATUS
);
2457 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
2458 current_link_up
= 0;
2459 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
2460 tw32_f(MAC_MODE
, (tp
->mac_mode
|
2461 MAC_MODE_SEND_CONFIGS
));
2463 tw32_f(MAC_MODE
, tp
->mac_mode
);
2467 if (current_link_up
== 1) {
2468 tp
->link_config
.active_speed
= SPEED_1000
;
2469 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
2470 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
2471 LED_CTRL_LNKLED_OVERRIDE
|
2472 LED_CTRL_1000MBPS_ON
));
2474 tp
->link_config
.active_speed
= SPEED_INVALID
;
2475 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
2476 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
2477 LED_CTRL_LNKLED_OVERRIDE
|
2478 LED_CTRL_TRAFFIC_OVERRIDE
));
2481 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
2482 if (current_link_up
)
2483 netif_carrier_on(tp
->dev
);
2485 netif_carrier_off(tp
->dev
);
2486 tg3_link_report(tp
);
2489 tp
->tg3_flags
& (TG3_FLAG_RX_PAUSE
|
2491 if (orig_pause_cfg
!= now_pause_cfg
||
2492 orig_active_speed
!= tp
->link_config
.active_speed
||
2493 orig_active_duplex
!= tp
->link_config
.active_duplex
)
2494 tg3_link_report(tp
);
2500 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
2504 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2505 err
= tg3_setup_fiber_phy(tp
, force_reset
);
2507 err
= tg3_setup_copper_phy(tp
, force_reset
);
2510 if (tp
->link_config
.active_speed
== SPEED_1000
&&
2511 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
2512 tw32(MAC_TX_LENGTHS
,
2513 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
2514 (6 << TX_LENGTHS_IPG_SHIFT
) |
2515 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
2517 tw32(MAC_TX_LENGTHS
,
2518 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
2519 (6 << TX_LENGTHS_IPG_SHIFT
) |
2520 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
2522 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2523 if (netif_carrier_ok(tp
->dev
)) {
2524 tw32(HOSTCC_STAT_COAL_TICKS
,
2525 tp
->coal
.stats_block_coalesce_usecs
);
2527 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
2534 /* Tigon3 never reports partial packet sends. So we do not
2535 * need special logic to handle SKBs that have not had all
2536 * of their frags sent yet, like SunGEM does.
2538 static void tg3_tx(struct tg3
*tp
)
2540 u32 hw_idx
= tp
->hw_status
->idx
[0].tx_consumer
;
2541 u32 sw_idx
= tp
->tx_cons
;
2543 while (sw_idx
!= hw_idx
) {
2544 struct tx_ring_info
*ri
= &tp
->tx_buffers
[sw_idx
];
2545 struct sk_buff
*skb
= ri
->skb
;
2548 if (unlikely(skb
== NULL
))
2551 pci_unmap_single(tp
->pdev
,
2552 pci_unmap_addr(ri
, mapping
),
2558 sw_idx
= NEXT_TX(sw_idx
);
2560 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2561 if (unlikely(sw_idx
== hw_idx
))
2564 ri
= &tp
->tx_buffers
[sw_idx
];
2565 if (unlikely(ri
->skb
!= NULL
))
2568 pci_unmap_page(tp
->pdev
,
2569 pci_unmap_addr(ri
, mapping
),
2570 skb_shinfo(skb
)->frags
[i
].size
,
2573 sw_idx
= NEXT_TX(sw_idx
);
2576 dev_kfree_skb_irq(skb
);
2579 tp
->tx_cons
= sw_idx
;
2581 if (netif_queue_stopped(tp
->dev
) &&
2582 (TX_BUFFS_AVAIL(tp
) > TG3_TX_WAKEUP_THRESH
))
2583 netif_wake_queue(tp
->dev
);
2586 /* Returns size of skb allocated or < 0 on error.
2588 * We only need to fill in the address because the other members
2589 * of the RX descriptor are invariant, see tg3_init_rings.
2591 * Note the purposeful assymetry of cpu vs. chip accesses. For
2592 * posting buffers we only dirty the first cache line of the RX
2593 * descriptor (containing the address). Whereas for the RX status
2594 * buffers the cpu only reads the last cacheline of the RX descriptor
2595 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2597 static int tg3_alloc_rx_skb(struct tg3
*tp
, u32 opaque_key
,
2598 int src_idx
, u32 dest_idx_unmasked
)
2600 struct tg3_rx_buffer_desc
*desc
;
2601 struct ring_info
*map
, *src_map
;
2602 struct sk_buff
*skb
;
2604 int skb_size
, dest_idx
;
2607 switch (opaque_key
) {
2608 case RXD_OPAQUE_RING_STD
:
2609 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
2610 desc
= &tp
->rx_std
[dest_idx
];
2611 map
= &tp
->rx_std_buffers
[dest_idx
];
2613 src_map
= &tp
->rx_std_buffers
[src_idx
];
2614 skb_size
= RX_PKT_BUF_SZ
;
2617 case RXD_OPAQUE_RING_JUMBO
:
2618 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
2619 desc
= &tp
->rx_jumbo
[dest_idx
];
2620 map
= &tp
->rx_jumbo_buffers
[dest_idx
];
2622 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
2623 skb_size
= RX_JUMBO_PKT_BUF_SZ
;
2630 /* Do not overwrite any of the map or rp information
2631 * until we are sure we can commit to a new buffer.
2633 * Callers depend upon this behavior and assume that
2634 * we leave everything unchanged if we fail.
2636 skb
= dev_alloc_skb(skb_size
);
2641 skb_reserve(skb
, tp
->rx_offset
);
2643 mapping
= pci_map_single(tp
->pdev
, skb
->data
,
2644 skb_size
- tp
->rx_offset
,
2645 PCI_DMA_FROMDEVICE
);
2648 pci_unmap_addr_set(map
, mapping
, mapping
);
2650 if (src_map
!= NULL
)
2651 src_map
->skb
= NULL
;
2653 desc
->addr_hi
= ((u64
)mapping
>> 32);
2654 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
2659 /* We only need to move over in the address because the other
2660 * members of the RX descriptor are invariant. See notes above
2661 * tg3_alloc_rx_skb for full details.
2663 static void tg3_recycle_rx(struct tg3
*tp
, u32 opaque_key
,
2664 int src_idx
, u32 dest_idx_unmasked
)
2666 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
2667 struct ring_info
*src_map
, *dest_map
;
2670 switch (opaque_key
) {
2671 case RXD_OPAQUE_RING_STD
:
2672 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
2673 dest_desc
= &tp
->rx_std
[dest_idx
];
2674 dest_map
= &tp
->rx_std_buffers
[dest_idx
];
2675 src_desc
= &tp
->rx_std
[src_idx
];
2676 src_map
= &tp
->rx_std_buffers
[src_idx
];
2679 case RXD_OPAQUE_RING_JUMBO
:
2680 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
2681 dest_desc
= &tp
->rx_jumbo
[dest_idx
];
2682 dest_map
= &tp
->rx_jumbo_buffers
[dest_idx
];
2683 src_desc
= &tp
->rx_jumbo
[src_idx
];
2684 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
2691 dest_map
->skb
= src_map
->skb
;
2692 pci_unmap_addr_set(dest_map
, mapping
,
2693 pci_unmap_addr(src_map
, mapping
));
2694 dest_desc
->addr_hi
= src_desc
->addr_hi
;
2695 dest_desc
->addr_lo
= src_desc
->addr_lo
;
2697 src_map
->skb
= NULL
;
2700 #if TG3_VLAN_TAG_USED
2701 static int tg3_vlan_rx(struct tg3
*tp
, struct sk_buff
*skb
, u16 vlan_tag
)
2703 return vlan_hwaccel_receive_skb(skb
, tp
->vlgrp
, vlan_tag
);
2707 /* The RX ring scheme is composed of multiple rings which post fresh
2708 * buffers to the chip, and one special ring the chip uses to report
2709 * status back to the host.
2711 * The special ring reports the status of received packets to the
2712 * host. The chip does not write into the original descriptor the
2713 * RX buffer was obtained from. The chip simply takes the original
2714 * descriptor as provided by the host, updates the status and length
2715 * field, then writes this into the next status ring entry.
2717 * Each ring the host uses to post buffers to the chip is described
2718 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
2719 * it is first placed into the on-chip ram. When the packet's length
2720 * is known, it walks down the TG3_BDINFO entries to select the ring.
2721 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2722 * which is within the range of the new packet's length is chosen.
2724 * The "separate ring for rx status" scheme may sound queer, but it makes
2725 * sense from a cache coherency perspective. If only the host writes
2726 * to the buffer post rings, and only the chip writes to the rx status
2727 * rings, then cache lines never move beyond shared-modified state.
2728 * If both the host and chip were to write into the same ring, cache line
2729 * eviction could occur since both entities want it in an exclusive state.
2731 static int tg3_rx(struct tg3
*tp
, int budget
)
2734 u32 sw_idx
= tp
->rx_rcb_ptr
;
2738 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
2740 * We need to order the read of hw_idx and the read of
2741 * the opaque cookie.
2746 while (sw_idx
!= hw_idx
&& budget
> 0) {
2747 struct tg3_rx_buffer_desc
*desc
= &tp
->rx_rcb
[sw_idx
];
2749 struct sk_buff
*skb
;
2750 dma_addr_t dma_addr
;
2751 u32 opaque_key
, desc_idx
, *post_ptr
;
2753 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
2754 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
2755 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
2756 dma_addr
= pci_unmap_addr(&tp
->rx_std_buffers
[desc_idx
],
2758 skb
= tp
->rx_std_buffers
[desc_idx
].skb
;
2759 post_ptr
= &tp
->rx_std_ptr
;
2760 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
2761 dma_addr
= pci_unmap_addr(&tp
->rx_jumbo_buffers
[desc_idx
],
2763 skb
= tp
->rx_jumbo_buffers
[desc_idx
].skb
;
2764 post_ptr
= &tp
->rx_jumbo_ptr
;
2767 goto next_pkt_nopost
;
2770 work_mask
|= opaque_key
;
2772 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
2773 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
2775 tg3_recycle_rx(tp
, opaque_key
,
2776 desc_idx
, *post_ptr
);
2778 /* Other statistics kept track of by card. */
2779 tp
->net_stats
.rx_dropped
++;
2783 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4; /* omit crc */
2785 if (len
> RX_COPY_THRESHOLD
2786 && tp
->rx_offset
== 2
2787 /* rx_offset != 2 iff this is a 5701 card running
2788 * in PCI-X mode [see tg3_get_invariants()] */
2792 skb_size
= tg3_alloc_rx_skb(tp
, opaque_key
,
2793 desc_idx
, *post_ptr
);
2797 pci_unmap_single(tp
->pdev
, dma_addr
,
2798 skb_size
- tp
->rx_offset
,
2799 PCI_DMA_FROMDEVICE
);
2803 struct sk_buff
*copy_skb
;
2805 tg3_recycle_rx(tp
, opaque_key
,
2806 desc_idx
, *post_ptr
);
2808 copy_skb
= dev_alloc_skb(len
+ 2);
2809 if (copy_skb
== NULL
)
2810 goto drop_it_no_recycle
;
2812 copy_skb
->dev
= tp
->dev
;
2813 skb_reserve(copy_skb
, 2);
2814 skb_put(copy_skb
, len
);
2815 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
2816 memcpy(copy_skb
->data
, skb
->data
, len
);
2817 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
2819 /* We'll reuse the original ring buffer. */
2823 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
2824 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
2825 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
2826 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
2827 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2829 skb
->ip_summed
= CHECKSUM_NONE
;
2831 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
2832 #if TG3_VLAN_TAG_USED
2833 if (tp
->vlgrp
!= NULL
&&
2834 desc
->type_flags
& RXD_FLAG_VLAN
) {
2835 tg3_vlan_rx(tp
, skb
,
2836 desc
->err_vlan
& RXD_VLAN_MASK
);
2839 netif_receive_skb(skb
);
2841 tp
->dev
->last_rx
= jiffies
;
2849 sw_idx
%= TG3_RX_RCB_RING_SIZE(tp
);
2851 /* Refresh hw_idx to see if there is new work */
2852 if (sw_idx
== hw_idx
) {
2853 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
2858 /* ACK the status ring. */
2859 tp
->rx_rcb_ptr
= sw_idx
;
2860 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, sw_idx
);
2862 /* Refill RX ring(s). */
2863 if (work_mask
& RXD_OPAQUE_RING_STD
) {
2864 sw_idx
= tp
->rx_std_ptr
% TG3_RX_RING_SIZE
;
2865 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
2868 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
2869 sw_idx
= tp
->rx_jumbo_ptr
% TG3_RX_JUMBO_RING_SIZE
;
2870 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
2878 static int tg3_poll(struct net_device
*netdev
, int *budget
)
2880 struct tg3
*tp
= netdev_priv(netdev
);
2881 struct tg3_hw_status
*sblk
= tp
->hw_status
;
2882 unsigned long flags
;
2885 spin_lock_irqsave(&tp
->lock
, flags
);
2887 /* handle link change and other phy events */
2888 if (!(tp
->tg3_flags
&
2889 (TG3_FLAG_USE_LINKCHG_REG
|
2890 TG3_FLAG_POLL_SERDES
))) {
2891 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
2892 sblk
->status
= SD_STATUS_UPDATED
|
2893 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
2894 tg3_setup_phy(tp
, 0);
2898 /* run TX completion thread */
2899 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
) {
2900 spin_lock(&tp
->tx_lock
);
2902 spin_unlock(&tp
->tx_lock
);
2905 spin_unlock_irqrestore(&tp
->lock
, flags
);
2907 /* run RX thread, within the bounds set by NAPI.
2908 * All RX "locking" is done by ensuring outside
2909 * code synchronizes with dev->poll()
2911 if (sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
) {
2912 int orig_budget
= *budget
;
2915 if (orig_budget
> netdev
->quota
)
2916 orig_budget
= netdev
->quota
;
2918 work_done
= tg3_rx(tp
, orig_budget
);
2920 *budget
-= work_done
;
2921 netdev
->quota
-= work_done
;
2924 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
2925 tp
->last_tag
= sblk
->status_tag
;
2928 /* if no more work, tell net stack and NIC we're done */
2929 done
= !tg3_has_work(tp
);
2931 spin_lock_irqsave(&tp
->lock
, flags
);
2932 __netif_rx_complete(netdev
);
2933 tg3_restart_ints(tp
);
2934 spin_unlock_irqrestore(&tp
->lock
, flags
);
2937 return (done
? 0 : 1);
2940 /* MSI ISR - No need to check for interrupt sharing and no need to
2941 * flush status block and interrupt mailbox. PCI ordering rules
2942 * guarantee that MSI will arrive after the status block.
2944 static irqreturn_t
tg3_msi(int irq
, void *dev_id
, struct pt_regs
*regs
)
2946 struct net_device
*dev
= dev_id
;
2947 struct tg3
*tp
= netdev_priv(dev
);
2948 struct tg3_hw_status
*sblk
= tp
->hw_status
;
2949 unsigned long flags
;
2951 spin_lock_irqsave(&tp
->lock
, flags
);
2954 * Writing any value to intr-mbox-0 clears PCI INTA# and
2955 * chip-internal interrupt pending events.
2956 * Writing non-zero to intr-mbox-0 additional tells the
2957 * NIC to stop sending us irqs, engaging "in-intr-handler"
2960 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
2961 tp
->last_tag
= sblk
->status_tag
;
2962 sblk
->status
&= ~SD_STATUS_UPDATED
;
2963 if (likely(tg3_has_work(tp
)))
2964 netif_rx_schedule(dev
); /* schedule NAPI poll */
2966 /* No work, re-enable interrupts. */
2967 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
2968 tp
->last_tag
<< 24);
2971 spin_unlock_irqrestore(&tp
->lock
, flags
);
2973 return IRQ_RETVAL(1);
2976 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
2978 struct net_device
*dev
= dev_id
;
2979 struct tg3
*tp
= netdev_priv(dev
);
2980 struct tg3_hw_status
*sblk
= tp
->hw_status
;
2981 unsigned long flags
;
2982 unsigned int handled
= 1;
2984 spin_lock_irqsave(&tp
->lock
, flags
);
2986 /* In INTx mode, it is possible for the interrupt to arrive at
2987 * the CPU before the status block posted prior to the interrupt.
2988 * Reading the PCI State register will confirm whether the
2989 * interrupt is ours and will flush the status block.
2991 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
2992 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
2994 * Writing any value to intr-mbox-0 clears PCI INTA# and
2995 * chip-internal interrupt pending events.
2996 * Writing non-zero to intr-mbox-0 additional tells the
2997 * NIC to stop sending us irqs, engaging "in-intr-handler"
3000 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
3002 sblk
->status
&= ~SD_STATUS_UPDATED
;
3003 if (likely(tg3_has_work(tp
)))
3004 netif_rx_schedule(dev
); /* schedule NAPI poll */
3006 /* No work, shared interrupt perhaps? re-enable
3007 * interrupts, and flush that PCI write
3009 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
3011 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
3013 } else { /* shared interrupt */
3017 spin_unlock_irqrestore(&tp
->lock
, flags
);
3019 return IRQ_RETVAL(handled
);
3022 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
, struct pt_regs
*regs
)
3024 struct net_device
*dev
= dev_id
;
3025 struct tg3
*tp
= netdev_priv(dev
);
3026 struct tg3_hw_status
*sblk
= tp
->hw_status
;
3027 unsigned long flags
;
3028 unsigned int handled
= 1;
3030 spin_lock_irqsave(&tp
->lock
, flags
);
3032 /* In INTx mode, it is possible for the interrupt to arrive at
3033 * the CPU before the status block posted prior to the interrupt.
3034 * Reading the PCI State register will confirm whether the
3035 * interrupt is ours and will flush the status block.
3037 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
3038 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
3040 * writing any value to intr-mbox-0 clears PCI INTA# and
3041 * chip-internal interrupt pending events.
3042 * writing non-zero to intr-mbox-0 additional tells the
3043 * NIC to stop sending us irqs, engaging "in-intr-handler"
3046 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
3048 tp
->last_tag
= sblk
->status_tag
;
3049 sblk
->status
&= ~SD_STATUS_UPDATED
;
3050 if (likely(tg3_has_work(tp
)))
3051 netif_rx_schedule(dev
); /* schedule NAPI poll */
3053 /* no work, shared interrupt perhaps? re-enable
3054 * interrupts, and flush that PCI write
3056 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
3057 tp
->last_tag
<< 24);
3058 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
3060 } else { /* shared interrupt */
3064 spin_unlock_irqrestore(&tp
->lock
, flags
);
3066 return IRQ_RETVAL(handled
);
3069 /* ISR for interrupt test */
3070 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
,
3071 struct pt_regs
*regs
)
3073 struct net_device
*dev
= dev_id
;
3074 struct tg3
*tp
= netdev_priv(dev
);
3075 struct tg3_hw_status
*sblk
= tp
->hw_status
;
3077 if (sblk
->status
& SD_STATUS_UPDATED
) {
3078 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
3080 return IRQ_RETVAL(1);
3082 return IRQ_RETVAL(0);
3085 static int tg3_init_hw(struct tg3
*);
3086 static int tg3_halt(struct tg3
*, int, int);
3088 #ifdef CONFIG_NET_POLL_CONTROLLER
3089 static void tg3_poll_controller(struct net_device
*dev
)
3091 struct tg3
*tp
= netdev_priv(dev
);
3093 tg3_interrupt(tp
->pdev
->irq
, dev
, NULL
);
3097 static void tg3_reset_task(void *_data
)
3099 struct tg3
*tp
= _data
;
3100 unsigned int restart_timer
;
3104 spin_lock_irq(&tp
->lock
);
3105 spin_lock(&tp
->tx_lock
);
3107 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
3108 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
3110 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
3113 tg3_netif_start(tp
);
3115 spin_unlock(&tp
->tx_lock
);
3116 spin_unlock_irq(&tp
->lock
);
3119 mod_timer(&tp
->timer
, jiffies
+ 1);
3122 static void tg3_tx_timeout(struct net_device
*dev
)
3124 struct tg3
*tp
= netdev_priv(dev
);
3126 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
3129 schedule_work(&tp
->reset_task
);
3132 static void tg3_set_txd(struct tg3
*, int, dma_addr_t
, int, u32
, u32
);
3134 static int tigon3_4gb_hwbug_workaround(struct tg3
*tp
, struct sk_buff
*skb
,
3135 u32 guilty_entry
, int guilty_len
,
3136 u32 last_plus_one
, u32
*start
, u32 mss
)
3138 struct sk_buff
*new_skb
= skb_copy(skb
, GFP_ATOMIC
);
3139 dma_addr_t new_addr
;
3148 /* New SKB is guaranteed to be linear. */
3150 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
3152 tg3_set_txd(tp
, entry
, new_addr
, new_skb
->len
,
3153 (skb
->ip_summed
== CHECKSUM_HW
) ?
3154 TXD_FLAG_TCPUDP_CSUM
: 0, 1 | (mss
<< 1));
3155 *start
= NEXT_TX(entry
);
3157 /* Now clean up the sw ring entries. */
3159 while (entry
!= last_plus_one
) {
3163 len
= skb_headlen(skb
);
3165 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
3166 pci_unmap_single(tp
->pdev
,
3167 pci_unmap_addr(&tp
->tx_buffers
[entry
], mapping
),
3168 len
, PCI_DMA_TODEVICE
);
3170 tp
->tx_buffers
[entry
].skb
= new_skb
;
3171 pci_unmap_addr_set(&tp
->tx_buffers
[entry
], mapping
, new_addr
);
3173 tp
->tx_buffers
[entry
].skb
= NULL
;
3175 entry
= NEXT_TX(entry
);
3184 static void tg3_set_txd(struct tg3
*tp
, int entry
,
3185 dma_addr_t mapping
, int len
, u32 flags
,
3188 struct tg3_tx_buffer_desc
*txd
= &tp
->tx_ring
[entry
];
3189 int is_end
= (mss_and_is_end
& 0x1);
3190 u32 mss
= (mss_and_is_end
>> 1);
3194 flags
|= TXD_FLAG_END
;
3195 if (flags
& TXD_FLAG_VLAN
) {
3196 vlan_tag
= flags
>> 16;
3199 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
3201 txd
->addr_hi
= ((u64
) mapping
>> 32);
3202 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
3203 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
3204 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
3207 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
3209 u32 base
= (u32
) mapping
& 0xffffffff;
3211 return ((base
> 0xffffdcc0) &&
3212 (base
+ len
+ 8 < base
));
3215 static int tg3_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3217 struct tg3
*tp
= netdev_priv(dev
);
3220 u32 len
, entry
, base_flags
, mss
;
3221 int would_hit_hwbug
;
3222 unsigned long flags
;
3224 len
= skb_headlen(skb
);
3226 /* No BH disabling for tx_lock here. We are running in BH disabled
3227 * context and TX reclaim runs via tp->poll inside of a software
3228 * interrupt. Rejoice!
3230 * Actually, things are not so simple. If we are to take a hw
3231 * IRQ here, we can deadlock, consider:
3240 * spin on tp->tx_lock
3242 * So we really do need to disable interrupts when taking
3245 local_irq_save(flags
);
3246 if (!spin_trylock(&tp
->tx_lock
)) {
3247 local_irq_restore(flags
);
3248 return NETDEV_TX_LOCKED
;
3251 /* This is a hard error, log it. */
3252 if (unlikely(TX_BUFFS_AVAIL(tp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
3253 netif_stop_queue(dev
);
3254 spin_unlock_irqrestore(&tp
->tx_lock
, flags
);
3255 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when queue awake!\n",
3257 return NETDEV_TX_BUSY
;
3260 entry
= tp
->tx_prod
;
3262 if (skb
->ip_summed
== CHECKSUM_HW
)
3263 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
3264 #if TG3_TSO_SUPPORT != 0
3266 if (skb
->len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
3267 (mss
= skb_shinfo(skb
)->tso_size
) != 0) {
3268 int tcp_opt_len
, ip_tcp_len
;
3270 if (skb_header_cloned(skb
) &&
3271 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
3276 tcp_opt_len
= ((skb
->h
.th
->doff
- 5) * 4);
3277 ip_tcp_len
= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
3279 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
3280 TXD_FLAG_CPU_POST_DMA
);
3282 skb
->nh
.iph
->check
= 0;
3283 skb
->nh
.iph
->tot_len
= ntohs(mss
+ ip_tcp_len
+ tcp_opt_len
);
3284 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
3285 skb
->h
.th
->check
= 0;
3286 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
3290 ~csum_tcpudp_magic(skb
->nh
.iph
->saddr
,
3295 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
3296 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)) {
3297 if (tcp_opt_len
|| skb
->nh
.iph
->ihl
> 5) {
3300 tsflags
= ((skb
->nh
.iph
->ihl
- 5) +
3301 (tcp_opt_len
>> 2));
3302 mss
|= (tsflags
<< 11);
3305 if (tcp_opt_len
|| skb
->nh
.iph
->ihl
> 5) {
3308 tsflags
= ((skb
->nh
.iph
->ihl
- 5) +
3309 (tcp_opt_len
>> 2));
3310 base_flags
|= tsflags
<< 12;
3317 #if TG3_VLAN_TAG_USED
3318 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
3319 base_flags
|= (TXD_FLAG_VLAN
|
3320 (vlan_tx_tag_get(skb
) << 16));
3323 /* Queue skb data, a.k.a. the main skb fragment. */
3324 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
3326 tp
->tx_buffers
[entry
].skb
= skb
;
3327 pci_unmap_addr_set(&tp
->tx_buffers
[entry
], mapping
, mapping
);
3329 would_hit_hwbug
= 0;
3331 if (tg3_4g_overflow_test(mapping
, len
))
3332 would_hit_hwbug
= entry
+ 1;
3334 tg3_set_txd(tp
, entry
, mapping
, len
, base_flags
,
3335 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
3337 entry
= NEXT_TX(entry
);
3339 /* Now loop through additional data fragments, and queue them. */
3340 if (skb_shinfo(skb
)->nr_frags
> 0) {
3341 unsigned int i
, last
;
3343 last
= skb_shinfo(skb
)->nr_frags
- 1;
3344 for (i
= 0; i
<= last
; i
++) {
3345 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
3348 mapping
= pci_map_page(tp
->pdev
,
3351 len
, PCI_DMA_TODEVICE
);
3353 tp
->tx_buffers
[entry
].skb
= NULL
;
3354 pci_unmap_addr_set(&tp
->tx_buffers
[entry
], mapping
, mapping
);
3356 if (tg3_4g_overflow_test(mapping
, len
)) {
3357 /* Only one should match. */
3358 if (would_hit_hwbug
)
3360 would_hit_hwbug
= entry
+ 1;
3363 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
3364 tg3_set_txd(tp
, entry
, mapping
, len
,
3365 base_flags
, (i
== last
)|(mss
<< 1));
3367 tg3_set_txd(tp
, entry
, mapping
, len
,
3368 base_flags
, (i
== last
));
3370 entry
= NEXT_TX(entry
);
3374 if (would_hit_hwbug
) {
3375 u32 last_plus_one
= entry
;
3377 unsigned int len
= 0;
3379 would_hit_hwbug
-= 1;
3380 entry
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
3381 entry
&= (TG3_TX_RING_SIZE
- 1);
3384 while (entry
!= last_plus_one
) {
3386 len
= skb_headlen(skb
);
3388 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
3390 if (entry
== would_hit_hwbug
)
3394 entry
= NEXT_TX(entry
);
3398 /* If the workaround fails due to memory/mapping
3399 * failure, silently drop this packet.
3401 if (tigon3_4gb_hwbug_workaround(tp
, skb
,
3410 /* Packets are ready, update Tx producer idx local and on card. */
3411 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
), entry
);
3413 tp
->tx_prod
= entry
;
3414 if (TX_BUFFS_AVAIL(tp
) <= (MAX_SKB_FRAGS
+ 1))
3415 netif_stop_queue(dev
);
3419 spin_unlock_irqrestore(&tp
->tx_lock
, flags
);
3421 dev
->trans_start
= jiffies
;
3423 return NETDEV_TX_OK
;
3426 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
3431 if (new_mtu
> ETH_DATA_LEN
)
3432 tp
->tg3_flags
|= TG3_FLAG_JUMBO_ENABLE
;
3434 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_ENABLE
;
3437 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
3439 struct tg3
*tp
= netdev_priv(dev
);
3441 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
3444 if (!netif_running(dev
)) {
3445 /* We'll just catch it later when the
3448 tg3_set_mtu(dev
, tp
, new_mtu
);
3453 spin_lock_irq(&tp
->lock
);
3454 spin_lock(&tp
->tx_lock
);
3456 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
3458 tg3_set_mtu(dev
, tp
, new_mtu
);
3462 tg3_netif_start(tp
);
3464 spin_unlock(&tp
->tx_lock
);
3465 spin_unlock_irq(&tp
->lock
);
3470 /* Free up pending packets in all rx/tx rings.
3472 * The chip has been shut down and the driver detached from
3473 * the networking, so no interrupts or new tx packets will
3474 * end up in the driver. tp->{tx,}lock is not held and we are not
3475 * in an interrupt context and thus may sleep.
3477 static void tg3_free_rings(struct tg3
*tp
)
3479 struct ring_info
*rxp
;
3482 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
3483 rxp
= &tp
->rx_std_buffers
[i
];
3485 if (rxp
->skb
== NULL
)
3487 pci_unmap_single(tp
->pdev
,
3488 pci_unmap_addr(rxp
, mapping
),
3489 RX_PKT_BUF_SZ
- tp
->rx_offset
,
3490 PCI_DMA_FROMDEVICE
);
3491 dev_kfree_skb_any(rxp
->skb
);
3495 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
3496 rxp
= &tp
->rx_jumbo_buffers
[i
];
3498 if (rxp
->skb
== NULL
)
3500 pci_unmap_single(tp
->pdev
,
3501 pci_unmap_addr(rxp
, mapping
),
3502 RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
,
3503 PCI_DMA_FROMDEVICE
);
3504 dev_kfree_skb_any(rxp
->skb
);
3508 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
3509 struct tx_ring_info
*txp
;
3510 struct sk_buff
*skb
;
3513 txp
= &tp
->tx_buffers
[i
];
3521 pci_unmap_single(tp
->pdev
,
3522 pci_unmap_addr(txp
, mapping
),
3529 for (j
= 0; j
< skb_shinfo(skb
)->nr_frags
; j
++) {
3530 txp
= &tp
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
3531 pci_unmap_page(tp
->pdev
,
3532 pci_unmap_addr(txp
, mapping
),
3533 skb_shinfo(skb
)->frags
[j
].size
,
3538 dev_kfree_skb_any(skb
);
3542 /* Initialize tx/rx rings for packet processing.
3544 * The chip has been shut down and the driver detached from
3545 * the networking, so no interrupts or new tx packets will
3546 * end up in the driver. tp->{tx,}lock are held and thus
3549 static void tg3_init_rings(struct tg3
*tp
)
3553 /* Free up all the SKBs. */
3556 /* Zero out all descriptors. */
3557 memset(tp
->rx_std
, 0, TG3_RX_RING_BYTES
);
3558 memset(tp
->rx_jumbo
, 0, TG3_RX_JUMBO_RING_BYTES
);
3559 memset(tp
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
3560 memset(tp
->tx_ring
, 0, TG3_TX_RING_BYTES
);
3562 /* Initialize invariants of the rings, we only set this
3563 * stuff once. This works because the card does not
3564 * write into the rx buffer posting rings.
3566 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
3567 struct tg3_rx_buffer_desc
*rxd
;
3569 rxd
= &tp
->rx_std
[i
];
3570 rxd
->idx_len
= (RX_PKT_BUF_SZ
- tp
->rx_offset
- 64)
3572 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
3573 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
3574 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
3577 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
) {
3578 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
3579 struct tg3_rx_buffer_desc
*rxd
;
3581 rxd
= &tp
->rx_jumbo
[i
];
3582 rxd
->idx_len
= (RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
- 64)
3584 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
3586 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
3587 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
3591 /* Now allocate fresh SKBs for each rx ring. */
3592 for (i
= 0; i
< tp
->rx_pending
; i
++) {
3593 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_STD
,
3598 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
) {
3599 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
3600 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_JUMBO
,
3608 * Must not be invoked with interrupt sources disabled and
3609 * the hardware shutdown down.
3611 static void tg3_free_consistent(struct tg3
*tp
)
3613 if (tp
->rx_std_buffers
) {
3614 kfree(tp
->rx_std_buffers
);
3615 tp
->rx_std_buffers
= NULL
;
3618 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
3619 tp
->rx_std
, tp
->rx_std_mapping
);
3623 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
3624 tp
->rx_jumbo
, tp
->rx_jumbo_mapping
);
3625 tp
->rx_jumbo
= NULL
;
3628 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
3629 tp
->rx_rcb
, tp
->rx_rcb_mapping
);
3633 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
3634 tp
->tx_ring
, tp
->tx_desc_mapping
);
3637 if (tp
->hw_status
) {
3638 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
3639 tp
->hw_status
, tp
->status_mapping
);
3640 tp
->hw_status
= NULL
;
3643 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
3644 tp
->hw_stats
, tp
->stats_mapping
);
3645 tp
->hw_stats
= NULL
;
3650 * Must not be invoked with interrupt sources disabled and
3651 * the hardware shutdown down. Can sleep.
3653 static int tg3_alloc_consistent(struct tg3
*tp
)
3655 tp
->rx_std_buffers
= kmalloc((sizeof(struct ring_info
) *
3657 TG3_RX_JUMBO_RING_SIZE
)) +
3658 (sizeof(struct tx_ring_info
) *
3661 if (!tp
->rx_std_buffers
)
3664 memset(tp
->rx_std_buffers
, 0,
3665 (sizeof(struct ring_info
) *
3667 TG3_RX_JUMBO_RING_SIZE
)) +
3668 (sizeof(struct tx_ring_info
) *
3671 tp
->rx_jumbo_buffers
= &tp
->rx_std_buffers
[TG3_RX_RING_SIZE
];
3672 tp
->tx_buffers
= (struct tx_ring_info
*)
3673 &tp
->rx_jumbo_buffers
[TG3_RX_JUMBO_RING_SIZE
];
3675 tp
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
3676 &tp
->rx_std_mapping
);
3680 tp
->rx_jumbo
= pci_alloc_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
3681 &tp
->rx_jumbo_mapping
);
3686 tp
->rx_rcb
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
3687 &tp
->rx_rcb_mapping
);
3691 tp
->tx_ring
= pci_alloc_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
3692 &tp
->tx_desc_mapping
);
3696 tp
->hw_status
= pci_alloc_consistent(tp
->pdev
,
3698 &tp
->status_mapping
);
3702 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
3703 sizeof(struct tg3_hw_stats
),
3704 &tp
->stats_mapping
);
3708 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
3709 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
3714 tg3_free_consistent(tp
);
3718 #define MAX_WAIT_CNT 1000
3720 /* To stop a block, clear the enable bit and poll till it
3721 * clears. tp->lock is held.
3723 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
3728 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
3735 /* We can't enable/disable these bits of the
3736 * 5705/5750, just say success.
3749 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
3752 if ((val
& enable_bit
) == 0)
3756 if (i
== MAX_WAIT_CNT
&& !silent
) {
3757 printk(KERN_ERR PFX
"tg3_stop_block timed out, "
3758 "ofs=%lx enable_bit=%x\n",
3766 /* tp->lock is held. */
3767 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
3771 tg3_disable_ints(tp
);
3773 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
3774 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
3777 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
3778 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
3779 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
3780 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
3781 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
3782 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
3784 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
3785 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
3786 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
3787 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
3788 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
3789 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
3790 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
3792 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
3793 tw32_f(MAC_MODE
, tp
->mac_mode
);
3796 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
3797 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
3799 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
3801 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
3804 if (i
>= MAX_WAIT_CNT
) {
3805 printk(KERN_ERR PFX
"tg3_abort_hw timed out for %s, "
3806 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3807 tp
->dev
->name
, tr32(MAC_TX_MODE
));
3811 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
3812 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
3813 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
3815 tw32(FTQ_RESET
, 0xffffffff);
3816 tw32(FTQ_RESET
, 0x00000000);
3818 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
3819 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
3822 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
3824 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
3829 /* tp->lock is held. */
3830 static int tg3_nvram_lock(struct tg3
*tp
)
3832 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
3835 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
3836 for (i
= 0; i
< 8000; i
++) {
3837 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
3847 /* tp->lock is held. */
3848 static void tg3_nvram_unlock(struct tg3
*tp
)
3850 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
3851 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
3854 /* tp->lock is held. */
3855 static void tg3_enable_nvram_access(struct tg3
*tp
)
3857 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
3858 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
3859 u32 nvaccess
= tr32(NVRAM_ACCESS
);
3861 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
3865 /* tp->lock is held. */
3866 static void tg3_disable_nvram_access(struct tg3
*tp
)
3868 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
3869 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
3870 u32 nvaccess
= tr32(NVRAM_ACCESS
);
3872 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
3876 /* tp->lock is held. */
3877 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
3879 if (!(tp
->tg3_flags2
& TG3_FLG2_SUN_570X
))
3880 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
3881 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
3883 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
3885 case RESET_KIND_INIT
:
3886 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3890 case RESET_KIND_SHUTDOWN
:
3891 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3895 case RESET_KIND_SUSPEND
:
3896 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3906 /* tp->lock is held. */
3907 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
3909 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
3911 case RESET_KIND_INIT
:
3912 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3913 DRV_STATE_START_DONE
);
3916 case RESET_KIND_SHUTDOWN
:
3917 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3918 DRV_STATE_UNLOAD_DONE
);
3927 /* tp->lock is held. */
3928 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
3930 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
3932 case RESET_KIND_INIT
:
3933 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3937 case RESET_KIND_SHUTDOWN
:
3938 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3942 case RESET_KIND_SUSPEND
:
3943 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3953 static void tg3_stop_fw(struct tg3
*);
3955 /* tp->lock is held. */
3956 static int tg3_chip_reset(struct tg3
*tp
)
3962 if (!(tp
->tg3_flags2
& TG3_FLG2_SUN_570X
))
3966 * We must avoid the readl() that normally takes place.
3967 * It locks machines, causes machine checks, and other
3968 * fun things. So, temporarily disable the 5701
3969 * hardware workaround, while we do the reset.
3971 flags_save
= tp
->tg3_flags
;
3972 tp
->tg3_flags
&= ~TG3_FLAG_5701_REG_WRITE_BUG
;
3975 val
= GRC_MISC_CFG_CORECLK_RESET
;
3977 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
3978 if (tr32(0x7e2c) == 0x60) {
3981 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
3982 tw32(GRC_MISC_CFG
, (1 << 29));
3987 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
3988 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
3989 tw32(GRC_MISC_CFG
, val
);
3991 /* restore 5701 hardware bug workaround flag */
3992 tp
->tg3_flags
= flags_save
;
3994 /* Unfortunately, we have to delay before the PCI read back.
3995 * Some 575X chips even will not respond to a PCI cfg access
3996 * when the reset command is given to the chip.
3998 * How do these hardware designers expect things to work
3999 * properly if the PCI write is posted for a long period
4000 * of time? It is always necessary to have some method by
4001 * which a register read back can occur to push the write
4002 * out which does the reset.
4004 * For most tg3 variants the trick below was working.
4009 /* Flush PCI posted writes. The normal MMIO registers
4010 * are inaccessible at this time so this is the only
4011 * way to make this reliably (actually, this is no longer
4012 * the case, see above). I tried to use indirect
4013 * register read/write but this upset some 5701 variants.
4015 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
4019 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
4020 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
4024 /* Wait for link training to complete. */
4025 for (i
= 0; i
< 5000; i
++)
4028 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
4029 pci_write_config_dword(tp
->pdev
, 0xc4,
4030 cfg_val
| (1 << 15));
4032 /* Set PCIE max payload size and clear error status. */
4033 pci_write_config_dword(tp
->pdev
, 0xd8, 0xf5000);
4036 /* Re-enable indirect register accesses. */
4037 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
4038 tp
->misc_host_ctrl
);
4040 /* Set MAX PCI retry to zero. */
4041 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
4042 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
4043 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
4044 val
|= PCISTATE_RETRY_SAME_DMA
;
4045 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
4047 pci_restore_state(tp
->pdev
);
4049 /* Make sure PCI-X relaxed ordering bit is clear. */
4050 pci_read_config_dword(tp
->pdev
, TG3PCI_X_CAPS
, &val
);
4051 val
&= ~PCIX_CAPS_RELAXED_ORDERING
;
4052 pci_write_config_dword(tp
->pdev
, TG3PCI_X_CAPS
, val
);
4054 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
4056 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
4058 tw32(0x5000, 0x400);
4061 tw32(GRC_MODE
, tp
->grc_mode
);
4063 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
4064 u32 val
= tr32(0xc4);
4066 tw32(0xc4, val
| (1 << 15));
4069 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
4070 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
4071 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
4072 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
4073 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
4074 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
4077 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
4078 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
4079 tw32_f(MAC_MODE
, tp
->mac_mode
);
4081 tw32_f(MAC_MODE
, 0);
4084 if (!(tp
->tg3_flags2
& TG3_FLG2_SUN_570X
)) {
4085 /* Wait for firmware initialization to complete. */
4086 for (i
= 0; i
< 100000; i
++) {
4087 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
4088 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
4093 printk(KERN_ERR PFX
"tg3_reset_hw timed out for %s, "
4094 "firmware will not restart magic=%08x\n",
4095 tp
->dev
->name
, val
);
4100 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
4101 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
4102 u32 val
= tr32(0x7c00);
4104 tw32(0x7c00, val
| (1 << 25));
4107 /* Reprobe ASF enable state. */
4108 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
4109 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
4110 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
4111 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
4114 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
4115 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
4116 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
4117 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
4118 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
4125 /* tp->lock is held. */
4126 static void tg3_stop_fw(struct tg3
*tp
)
4128 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
4132 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
4133 val
= tr32(GRC_RX_CPU_EVENT
);
4135 tw32(GRC_RX_CPU_EVENT
, val
);
4137 /* Wait for RX cpu to ACK the event. */
4138 for (i
= 0; i
< 100; i
++) {
4139 if (!(tr32(GRC_RX_CPU_EVENT
) & (1 << 14)))
4146 /* tp->lock is held. */
4147 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
4153 tg3_write_sig_pre_reset(tp
, kind
);
4155 tg3_abort_hw(tp
, silent
);
4156 err
= tg3_chip_reset(tp
);
4158 tg3_write_sig_legacy(tp
, kind
);
4159 tg3_write_sig_post_reset(tp
, kind
);
4167 #define TG3_FW_RELEASE_MAJOR 0x0
4168 #define TG3_FW_RELASE_MINOR 0x0
4169 #define TG3_FW_RELEASE_FIX 0x0
4170 #define TG3_FW_START_ADDR 0x08000000
4171 #define TG3_FW_TEXT_ADDR 0x08000000
4172 #define TG3_FW_TEXT_LEN 0x9c0
4173 #define TG3_FW_RODATA_ADDR 0x080009c0
4174 #define TG3_FW_RODATA_LEN 0x60
4175 #define TG3_FW_DATA_ADDR 0x08000a40
4176 #define TG3_FW_DATA_LEN 0x20
4177 #define TG3_FW_SBSS_ADDR 0x08000a60
4178 #define TG3_FW_SBSS_LEN 0xc
4179 #define TG3_FW_BSS_ADDR 0x08000a70
4180 #define TG3_FW_BSS_LEN 0x10
4182 static u32 tg3FwText
[(TG3_FW_TEXT_LEN
/ sizeof(u32
)) + 1] = {
4183 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4184 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4185 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4186 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4187 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4188 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4189 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4190 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4191 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4192 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4193 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4194 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4195 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4196 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4197 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4198 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4199 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4200 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4201 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4202 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4203 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4204 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4205 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4206 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4209 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4210 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4211 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4212 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4213 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4214 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4215 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4216 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4217 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4218 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4219 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4223 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4224 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4225 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4226 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4227 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4228 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4229 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4230 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4231 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4232 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4233 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4234 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4235 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4236 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4237 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4238 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4239 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4240 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4241 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4242 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4243 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4244 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4245 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4246 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4247 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4248 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4249 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4250 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4251 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4252 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4253 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4254 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4255 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4256 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4257 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4258 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4259 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4260 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4261 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4262 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4263 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4264 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4265 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4266 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4267 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4268 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4269 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4270 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4271 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4272 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4273 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4276 static u32 tg3FwRodata
[(TG3_FW_RODATA_LEN
/ sizeof(u32
)) + 1] = {
4277 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4278 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4279 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4280 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4284 #if 0 /* All zeros, don't eat up space with it. */
4285 u32 tg3FwData
[(TG3_FW_DATA_LEN
/ sizeof(u32
)) + 1] = {
4286 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4287 0x00000000, 0x00000000, 0x00000000, 0x00000000
4291 #define RX_CPU_SCRATCH_BASE 0x30000
4292 #define RX_CPU_SCRATCH_SIZE 0x04000
4293 #define TX_CPU_SCRATCH_BASE 0x34000
4294 #define TX_CPU_SCRATCH_SIZE 0x04000
4296 /* tp->lock is held. */
4297 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
4301 if (offset
== TX_CPU_BASE
&&
4302 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
4305 if (offset
== RX_CPU_BASE
) {
4306 for (i
= 0; i
< 10000; i
++) {
4307 tw32(offset
+ CPU_STATE
, 0xffffffff);
4308 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
4309 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
4313 tw32(offset
+ CPU_STATE
, 0xffffffff);
4314 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
4317 for (i
= 0; i
< 10000; i
++) {
4318 tw32(offset
+ CPU_STATE
, 0xffffffff);
4319 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
4320 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
4326 printk(KERN_ERR PFX
"tg3_reset_cpu timed out for %s, "
4329 (offset
== RX_CPU_BASE
? "RX" : "TX"));
4336 unsigned int text_base
;
4337 unsigned int text_len
;
4339 unsigned int rodata_base
;
4340 unsigned int rodata_len
;
4342 unsigned int data_base
;
4343 unsigned int data_len
;
4347 /* tp->lock is held. */
4348 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
4349 int cpu_scratch_size
, struct fw_info
*info
)
4352 u32 orig_tg3_flags
= tp
->tg3_flags
;
4353 void (*write_op
)(struct tg3
*, u32
, u32
);
4355 if (cpu_base
== TX_CPU_BASE
&&
4356 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4357 printk(KERN_ERR PFX
"tg3_load_firmware_cpu: Trying to load "
4358 "TX cpu firmware on %s which is 5705.\n",
4363 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
4364 write_op
= tg3_write_mem
;
4366 write_op
= tg3_write_indirect_reg32
;
4368 /* Force use of PCI config space for indirect register
4371 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
4373 err
= tg3_halt_cpu(tp
, cpu_base
);
4377 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
4378 write_op(tp
, cpu_scratch_base
+ i
, 0);
4379 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
4380 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
4381 for (i
= 0; i
< (info
->text_len
/ sizeof(u32
)); i
++)
4382 write_op(tp
, (cpu_scratch_base
+
4383 (info
->text_base
& 0xffff) +
4386 info
->text_data
[i
] : 0));
4387 for (i
= 0; i
< (info
->rodata_len
/ sizeof(u32
)); i
++)
4388 write_op(tp
, (cpu_scratch_base
+
4389 (info
->rodata_base
& 0xffff) +
4391 (info
->rodata_data
?
4392 info
->rodata_data
[i
] : 0));
4393 for (i
= 0; i
< (info
->data_len
/ sizeof(u32
)); i
++)
4394 write_op(tp
, (cpu_scratch_base
+
4395 (info
->data_base
& 0xffff) +
4398 info
->data_data
[i
] : 0));
4403 tp
->tg3_flags
= orig_tg3_flags
;
4407 /* tp->lock is held. */
4408 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
4410 struct fw_info info
;
4413 info
.text_base
= TG3_FW_TEXT_ADDR
;
4414 info
.text_len
= TG3_FW_TEXT_LEN
;
4415 info
.text_data
= &tg3FwText
[0];
4416 info
.rodata_base
= TG3_FW_RODATA_ADDR
;
4417 info
.rodata_len
= TG3_FW_RODATA_LEN
;
4418 info
.rodata_data
= &tg3FwRodata
[0];
4419 info
.data_base
= TG3_FW_DATA_ADDR
;
4420 info
.data_len
= TG3_FW_DATA_LEN
;
4421 info
.data_data
= NULL
;
4423 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
4424 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
4429 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
4430 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
4435 /* Now startup only the RX cpu. */
4436 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
4437 tw32_f(RX_CPU_BASE
+ CPU_PC
, TG3_FW_TEXT_ADDR
);
4439 for (i
= 0; i
< 5; i
++) {
4440 if (tr32(RX_CPU_BASE
+ CPU_PC
) == TG3_FW_TEXT_ADDR
)
4442 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
4443 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
4444 tw32_f(RX_CPU_BASE
+ CPU_PC
, TG3_FW_TEXT_ADDR
);
4448 printk(KERN_ERR PFX
"tg3_load_firmware fails for %s "
4449 "to set RX CPU PC, is %08x should be %08x\n",
4450 tp
->dev
->name
, tr32(RX_CPU_BASE
+ CPU_PC
),
4454 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
4455 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
4460 #if TG3_TSO_SUPPORT != 0
4462 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
4463 #define TG3_TSO_FW_RELASE_MINOR 0x6
4464 #define TG3_TSO_FW_RELEASE_FIX 0x0
4465 #define TG3_TSO_FW_START_ADDR 0x08000000
4466 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
4467 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
4468 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4469 #define TG3_TSO_FW_RODATA_LEN 0x60
4470 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
4471 #define TG3_TSO_FW_DATA_LEN 0x30
4472 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4473 #define TG3_TSO_FW_SBSS_LEN 0x2c
4474 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
4475 #define TG3_TSO_FW_BSS_LEN 0x894
4477 static u32 tg3TsoFwText
[(TG3_TSO_FW_TEXT_LEN
/ 4) + 1] = {
4478 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4479 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4480 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4481 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4482 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4483 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4484 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4485 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4486 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4487 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4488 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4489 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4490 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4491 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4492 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4493 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4494 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4495 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4496 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4497 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4498 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4499 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4500 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4501 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4502 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4503 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4504 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4505 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4506 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4507 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4508 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4509 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4510 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4511 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4512 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4513 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4514 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4515 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4516 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4517 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4518 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4519 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4520 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4521 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4522 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4523 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4524 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4525 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4526 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4527 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4528 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4529 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4530 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4531 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4532 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4533 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4534 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4535 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4536 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4537 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4538 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4539 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4540 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4541 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4542 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4543 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4544 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4545 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4546 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4547 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4548 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4549 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4550 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4551 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4552 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4553 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4554 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4555 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4556 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4557 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4558 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4559 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4560 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4561 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4562 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4563 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4564 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4565 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4566 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4567 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4568 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4569 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4570 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4571 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4572 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4573 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4574 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4575 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4576 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4577 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4578 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4579 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4580 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4581 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4582 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4583 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4584 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4585 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4586 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4587 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4588 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4589 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4590 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4591 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4592 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4593 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4594 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4595 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4596 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4597 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4598 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4599 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4600 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4601 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4602 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4603 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4604 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4605 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4606 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4607 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4608 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4609 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4610 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4611 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4612 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4613 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4614 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4615 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4616 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4617 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4618 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4619 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4620 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4621 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4622 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4623 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4624 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4625 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4626 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4627 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4628 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4629 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4630 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4631 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4632 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4633 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4634 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4635 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4636 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4637 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4638 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4639 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4640 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4641 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4642 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4643 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4644 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4645 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4646 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4647 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4648 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4649 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4650 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4651 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4652 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4653 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4654 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4655 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4656 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4657 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4658 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4659 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4660 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4661 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4662 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4663 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4664 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4665 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4666 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4667 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4668 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4669 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4670 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4671 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4672 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4673 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4674 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4675 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4676 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4677 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4678 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4679 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4680 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4681 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4682 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4683 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4684 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4685 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4686 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4687 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4688 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4689 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4690 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4691 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4692 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4693 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4694 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4695 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4696 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4697 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4698 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4699 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4700 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4701 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4702 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4703 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4704 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4705 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4706 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4707 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4708 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4709 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4710 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4711 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4712 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4713 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4714 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4715 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4716 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4717 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4718 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4719 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4720 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4721 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4722 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4723 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4724 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4725 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4726 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4727 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4728 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4729 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4730 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4731 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4732 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4733 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4734 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4735 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4736 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4737 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4738 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4739 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4740 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4741 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4742 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4743 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4744 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4745 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4746 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4747 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4748 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4749 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4750 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4751 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4752 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4753 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4754 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4755 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4756 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4757 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4758 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4759 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4760 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4761 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4764 static u32 tg3TsoFwRodata
[] = {
4765 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4766 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4767 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4768 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4772 static u32 tg3TsoFwData
[] = {
4773 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4774 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4778 /* 5705 needs a special version of the TSO firmware. */
4779 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
4780 #define TG3_TSO5_FW_RELASE_MINOR 0x2
4781 #define TG3_TSO5_FW_RELEASE_FIX 0x0
4782 #define TG3_TSO5_FW_START_ADDR 0x00010000
4783 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
4784 #define TG3_TSO5_FW_TEXT_LEN 0xe90
4785 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
4786 #define TG3_TSO5_FW_RODATA_LEN 0x50
4787 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
4788 #define TG3_TSO5_FW_DATA_LEN 0x20
4789 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
4790 #define TG3_TSO5_FW_SBSS_LEN 0x28
4791 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
4792 #define TG3_TSO5_FW_BSS_LEN 0x88
4794 static u32 tg3Tso5FwText
[(TG3_TSO5_FW_TEXT_LEN
/ 4) + 1] = {
4795 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4796 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4797 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4798 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4799 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4800 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4801 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4802 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4803 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4804 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4805 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4806 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4807 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4808 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4809 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4810 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4811 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4812 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4813 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4814 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4815 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4816 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4817 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4818 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4819 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4820 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4821 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4822 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4823 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4824 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4825 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4826 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4827 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4828 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4829 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4830 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4831 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4832 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4833 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4834 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4835 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4836 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4837 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4838 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4839 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4840 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4841 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4842 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4843 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4844 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4845 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4846 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4847 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4848 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4849 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4850 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4851 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4852 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4853 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4854 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4855 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4856 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4857 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4858 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4859 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4860 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4861 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4862 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4863 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4864 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4865 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4866 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4867 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4868 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4869 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4870 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4871 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4872 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4873 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4874 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4875 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4876 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4877 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4878 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4879 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4880 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4881 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4882 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4883 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4884 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4885 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4886 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4887 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4888 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4889 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4890 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4891 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4892 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4893 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4894 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4895 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4896 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4897 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4898 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4899 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4900 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4901 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4902 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4903 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4904 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4905 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4906 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4907 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4908 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4909 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4910 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4911 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4912 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4913 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4914 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4915 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4916 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4917 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4918 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4919 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4920 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4921 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4922 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4923 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4924 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4925 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4926 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4927 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4928 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4929 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4930 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4931 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4932 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4933 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4934 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4935 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4936 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4937 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4938 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4939 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4940 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4941 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4942 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4943 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4944 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4945 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4946 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4947 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4948 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4949 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4950 0x00000000, 0x00000000, 0x00000000,
4953 static u32 tg3Tso5FwRodata
[(TG3_TSO5_FW_RODATA_LEN
/ 4) + 1] = {
4954 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4955 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4956 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4957 0x00000000, 0x00000000, 0x00000000,
4960 static u32 tg3Tso5FwData
[(TG3_TSO5_FW_DATA_LEN
/ 4) + 1] = {
4961 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4962 0x00000000, 0x00000000, 0x00000000,
4965 /* tp->lock is held. */
4966 static int tg3_load_tso_firmware(struct tg3
*tp
)
4968 struct fw_info info
;
4969 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
4972 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
4975 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
4976 info
.text_base
= TG3_TSO5_FW_TEXT_ADDR
;
4977 info
.text_len
= TG3_TSO5_FW_TEXT_LEN
;
4978 info
.text_data
= &tg3Tso5FwText
[0];
4979 info
.rodata_base
= TG3_TSO5_FW_RODATA_ADDR
;
4980 info
.rodata_len
= TG3_TSO5_FW_RODATA_LEN
;
4981 info
.rodata_data
= &tg3Tso5FwRodata
[0];
4982 info
.data_base
= TG3_TSO5_FW_DATA_ADDR
;
4983 info
.data_len
= TG3_TSO5_FW_DATA_LEN
;
4984 info
.data_data
= &tg3Tso5FwData
[0];
4985 cpu_base
= RX_CPU_BASE
;
4986 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
4987 cpu_scratch_size
= (info
.text_len
+
4990 TG3_TSO5_FW_SBSS_LEN
+
4991 TG3_TSO5_FW_BSS_LEN
);
4993 info
.text_base
= TG3_TSO_FW_TEXT_ADDR
;
4994 info
.text_len
= TG3_TSO_FW_TEXT_LEN
;
4995 info
.text_data
= &tg3TsoFwText
[0];
4996 info
.rodata_base
= TG3_TSO_FW_RODATA_ADDR
;
4997 info
.rodata_len
= TG3_TSO_FW_RODATA_LEN
;
4998 info
.rodata_data
= &tg3TsoFwRodata
[0];
4999 info
.data_base
= TG3_TSO_FW_DATA_ADDR
;
5000 info
.data_len
= TG3_TSO_FW_DATA_LEN
;
5001 info
.data_data
= &tg3TsoFwData
[0];
5002 cpu_base
= TX_CPU_BASE
;
5003 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
5004 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
5007 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
5008 cpu_scratch_base
, cpu_scratch_size
,
5013 /* Now startup the cpu. */
5014 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
5015 tw32_f(cpu_base
+ CPU_PC
, info
.text_base
);
5017 for (i
= 0; i
< 5; i
++) {
5018 if (tr32(cpu_base
+ CPU_PC
) == info
.text_base
)
5020 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
5021 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
5022 tw32_f(cpu_base
+ CPU_PC
, info
.text_base
);
5026 printk(KERN_ERR PFX
"tg3_load_tso_firmware fails for %s "
5027 "to set CPU PC, is %08x should be %08x\n",
5028 tp
->dev
->name
, tr32(cpu_base
+ CPU_PC
),
5032 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
5033 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
5037 #endif /* TG3_TSO_SUPPORT != 0 */
5039 /* tp->lock is held. */
5040 static void __tg3_set_mac_addr(struct tg3
*tp
)
5042 u32 addr_high
, addr_low
;
5045 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
5046 tp
->dev
->dev_addr
[1]);
5047 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
5048 (tp
->dev
->dev_addr
[3] << 16) |
5049 (tp
->dev
->dev_addr
[4] << 8) |
5050 (tp
->dev
->dev_addr
[5] << 0));
5051 for (i
= 0; i
< 4; i
++) {
5052 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
5053 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
5056 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
5057 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
5058 for (i
= 0; i
< 12; i
++) {
5059 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
5060 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
5064 addr_high
= (tp
->dev
->dev_addr
[0] +
5065 tp
->dev
->dev_addr
[1] +
5066 tp
->dev
->dev_addr
[2] +
5067 tp
->dev
->dev_addr
[3] +
5068 tp
->dev
->dev_addr
[4] +
5069 tp
->dev
->dev_addr
[5]) &
5070 TX_BACKOFF_SEED_MASK
;
5071 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
5074 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
5076 struct tg3
*tp
= netdev_priv(dev
);
5077 struct sockaddr
*addr
= p
;
5079 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5081 spin_lock_irq(&tp
->lock
);
5082 __tg3_set_mac_addr(tp
);
5083 spin_unlock_irq(&tp
->lock
);
5088 /* tp->lock is held. */
5089 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
5090 dma_addr_t mapping
, u32 maxlen_flags
,
5094 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
5095 ((u64
) mapping
>> 32));
5097 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
5098 ((u64
) mapping
& 0xffffffff));
5100 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
5103 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
5105 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
5109 static void __tg3_set_rx_mode(struct net_device
*);
5110 static void tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
5112 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
5113 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
5114 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
5115 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
5116 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5117 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
5118 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
5120 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
5121 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
5122 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5123 u32 val
= ec
->stats_block_coalesce_usecs
;
5125 if (!netif_carrier_ok(tp
->dev
))
5128 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
5132 /* tp->lock is held. */
5133 static int tg3_reset_hw(struct tg3
*tp
)
5135 u32 val
, rdmac_mode
;
5138 tg3_disable_ints(tp
);
5142 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
5144 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) {
5145 tg3_abort_hw(tp
, 1);
5148 err
= tg3_chip_reset(tp
);
5152 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
5154 /* This works around an issue with Athlon chipsets on
5155 * B3 tigon3 silicon. This bit has no effect on any
5156 * other revision. But do not set this on PCI Express
5159 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
5160 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
5161 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
5163 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
5164 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
5165 val
= tr32(TG3PCI_PCISTATE
);
5166 val
|= PCISTATE_RETRY_SAME_DMA
;
5167 tw32(TG3PCI_PCISTATE
, val
);
5170 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
5171 /* Enable some hw fixes. */
5172 val
= tr32(TG3PCI_MSI_DATA
);
5173 val
|= (1 << 26) | (1 << 28) | (1 << 29);
5174 tw32(TG3PCI_MSI_DATA
, val
);
5177 /* Descriptor ring init may make accesses to the
5178 * NIC SRAM area to setup the TX descriptors, so we
5179 * can only do this after the hardware has been
5180 * successfully reset.
5184 /* This value is determined during the probe time DMA
5185 * engine test, tg3_test_dma.
5187 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
5189 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
5190 GRC_MODE_4X_NIC_SEND_RINGS
|
5191 GRC_MODE_NO_TX_PHDR_CSUM
|
5192 GRC_MODE_NO_RX_PHDR_CSUM
);
5193 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
5194 if (tp
->tg3_flags
& TG3_FLAG_NO_TX_PSEUDO_CSUM
)
5195 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
5196 if (tp
->tg3_flags
& TG3_FLAG_NO_RX_PSEUDO_CSUM
)
5197 tp
->grc_mode
|= GRC_MODE_NO_RX_PHDR_CSUM
;
5201 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
5203 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5204 val
= tr32(GRC_MISC_CFG
);
5206 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
5207 tw32(GRC_MISC_CFG
, val
);
5209 /* Initialize MBUF/DESC pool. */
5210 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
5212 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
5213 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
5214 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
5215 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
5217 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
5218 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
5219 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
5221 #if TG3_TSO_SUPPORT != 0
5222 else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
5225 fw_len
= (TG3_TSO5_FW_TEXT_LEN
+
5226 TG3_TSO5_FW_RODATA_LEN
+
5227 TG3_TSO5_FW_DATA_LEN
+
5228 TG3_TSO5_FW_SBSS_LEN
+
5229 TG3_TSO5_FW_BSS_LEN
);
5230 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
5231 tw32(BUFMGR_MB_POOL_ADDR
,
5232 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
5233 tw32(BUFMGR_MB_POOL_SIZE
,
5234 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
5238 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
)) {
5239 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
5240 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
5241 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
5242 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
5243 tw32(BUFMGR_MB_HIGH_WATER
,
5244 tp
->bufmgr_config
.mbuf_high_water
);
5246 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
5247 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
5248 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
5249 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
5250 tw32(BUFMGR_MB_HIGH_WATER
,
5251 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
5253 tw32(BUFMGR_DMA_LOW_WATER
,
5254 tp
->bufmgr_config
.dma_low_water
);
5255 tw32(BUFMGR_DMA_HIGH_WATER
,
5256 tp
->bufmgr_config
.dma_high_water
);
5258 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
5259 for (i
= 0; i
< 2000; i
++) {
5260 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
5265 printk(KERN_ERR PFX
"tg3_reset_hw cannot enable BUFMGR for %s.\n",
5270 /* Setup replenish threshold. */
5271 tw32(RCVBDI_STD_THRESH
, tp
->rx_pending
/ 8);
5273 /* Initialize TG3_BDINFO's at:
5274 * RCVDBDI_STD_BD: standard eth size rx ring
5275 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5276 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5279 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5280 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5281 * ring attribute flags
5282 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5284 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5285 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5287 * The size of each ring is fixed in the firmware, but the location is
5290 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
5291 ((u64
) tp
->rx_std_mapping
>> 32));
5292 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
5293 ((u64
) tp
->rx_std_mapping
& 0xffffffff));
5294 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
5295 NIC_SRAM_RX_BUFFER_DESC
);
5297 /* Don't even try to program the JUMBO/MINI buffer descriptor
5300 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
5301 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5302 RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
5304 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5305 RX_STD_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
5307 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5308 BDINFO_FLAGS_DISABLED
);
5310 /* Setup replenish threshold. */
5311 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
5313 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
) {
5314 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
5315 ((u64
) tp
->rx_jumbo_mapping
>> 32));
5316 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
5317 ((u64
) tp
->rx_jumbo_mapping
& 0xffffffff));
5318 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5319 RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
5320 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
5321 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
5323 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5324 BDINFO_FLAGS_DISABLED
);
5329 /* There is only one send ring on 5705/5750, no need to explicitly
5330 * disable the others.
5332 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5333 /* Clear out send RCB ring in SRAM. */
5334 for (i
= NIC_SRAM_SEND_RCB
; i
< NIC_SRAM_RCV_RET_RCB
; i
+= TG3_BDINFO_SIZE
)
5335 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
5336 BDINFO_FLAGS_DISABLED
);
5341 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
5342 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
5344 tg3_set_bdinfo(tp
, NIC_SRAM_SEND_RCB
,
5345 tp
->tx_desc_mapping
,
5346 (TG3_TX_RING_SIZE
<<
5347 BDINFO_FLAGS_MAXLEN_SHIFT
),
5348 NIC_SRAM_TX_BUFFER_DESC
);
5350 /* There is only one receive return ring on 5705/5750, no need
5351 * to explicitly disable the others.
5353 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5354 for (i
= NIC_SRAM_RCV_RET_RCB
; i
< NIC_SRAM_STATS_BLK
;
5355 i
+= TG3_BDINFO_SIZE
) {
5356 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
5357 BDINFO_FLAGS_DISABLED
);
5362 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
5364 tg3_set_bdinfo(tp
, NIC_SRAM_RCV_RET_RCB
,
5366 (TG3_RX_RCB_RING_SIZE(tp
) <<
5367 BDINFO_FLAGS_MAXLEN_SHIFT
),
5370 tp
->rx_std_ptr
= tp
->rx_pending
;
5371 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
5374 tp
->rx_jumbo_ptr
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
) ?
5375 tp
->rx_jumbo_pending
: 0;
5376 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
5379 /* Initialize MAC address and backoff seed. */
5380 __tg3_set_mac_addr(tp
);
5382 /* MTU + ethernet header + FCS + optional VLAN tag */
5383 tw32(MAC_RX_MTU_SIZE
, tp
->dev
->mtu
+ ETH_HLEN
+ 8);
5385 /* The slot time is changed by tg3_setup_phy if we
5386 * run at gigabit with half duplex.
5388 tw32(MAC_TX_LENGTHS
,
5389 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
5390 (6 << TX_LENGTHS_IPG_SHIFT
) |
5391 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
5393 /* Receive rules. */
5394 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
5395 tw32(RCVLPC_CONFIG
, 0x0181);
5397 /* Calculate RDMAC_MODE setting early, we need it to determine
5398 * the RCVLPC_STATE_ENABLE mask.
5400 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
5401 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
5402 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
5403 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
5404 RDMAC_MODE_LNGREAD_ENAB
);
5405 if (tp
->tg3_flags
& TG3_FLAG_SPLIT_MODE
)
5406 rdmac_mode
|= RDMAC_MODE_SPLIT_ENABLE
;
5408 /* If statement applies to 5705 and 5750 PCI devices only */
5409 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
5410 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
5411 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
5412 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
5413 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
5414 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
5415 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
5416 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
5417 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
5418 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
5422 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
5423 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
5425 #if TG3_TSO_SUPPORT != 0
5426 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5427 rdmac_mode
|= (1 << 27);
5430 /* Receive/send statistics. */
5431 if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
5432 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
5433 val
= tr32(RCVLPC_STATS_ENABLE
);
5434 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
5435 tw32(RCVLPC_STATS_ENABLE
, val
);
5437 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
5439 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
5440 tw32(SNDDATAI_STATSENAB
, 0xffffff);
5441 tw32(SNDDATAI_STATSCTRL
,
5442 (SNDDATAI_SCTRL_ENABLE
|
5443 SNDDATAI_SCTRL_FASTUPD
));
5445 /* Setup host coalescing engine. */
5446 tw32(HOSTCC_MODE
, 0);
5447 for (i
= 0; i
< 2000; i
++) {
5448 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
5453 tg3_set_coalesce(tp
, &tp
->coal
);
5455 /* set status block DMA address */
5456 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
5457 ((u64
) tp
->status_mapping
>> 32));
5458 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
5459 ((u64
) tp
->status_mapping
& 0xffffffff));
5461 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5462 /* Status/statistics block address. See tg3_timer,
5463 * the tg3_periodic_fetch_stats call there, and
5464 * tg3_get_stats to see how this works for 5705/5750 chips.
5466 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
5467 ((u64
) tp
->stats_mapping
>> 32));
5468 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
5469 ((u64
) tp
->stats_mapping
& 0xffffffff));
5470 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
5471 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
5474 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
5476 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
5477 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
5478 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
5479 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
5481 /* Clear statistics/status block in chip, and status block in ram. */
5482 for (i
= NIC_SRAM_STATS_BLK
;
5483 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
5485 tg3_write_mem(tp
, i
, 0);
5488 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5490 tp
->mac_mode
= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
5491 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
5492 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
5495 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5496 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5497 * register to preserve the GPIO settings for LOMs. The GPIOs,
5498 * whether used as inputs or outputs, are set by boot code after
5501 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
5504 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE2
|
5505 GRC_LCLCTRL_GPIO_OUTPUT0
| GRC_LCLCTRL_GPIO_OUTPUT2
;
5507 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
5508 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
5509 GRC_LCLCTRL_GPIO_OUTPUT3
;
5511 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
5513 /* GPIO1 must be driven high for eeprom write protect */
5514 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
5515 GRC_LCLCTRL_GPIO_OUTPUT1
);
5517 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
5520 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0);
5521 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
5524 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5525 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
5529 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
5530 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
5531 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
5532 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
5533 WDMAC_MODE_LNGREAD_ENAB
);
5535 /* If statement applies to 5705 and 5750 PCI devices only */
5536 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
5537 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
5538 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
5539 if ((tp
->tg3_flags
& TG3_FLG2_TSO_CAPABLE
) &&
5540 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
5541 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
5543 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
5544 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
5545 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
5546 val
|= WDMAC_MODE_RX_ACCEL
;
5550 tw32_f(WDMAC_MODE
, val
);
5553 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
5554 val
= tr32(TG3PCI_X_CAPS
);
5555 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
5556 val
&= ~PCIX_CAPS_BURST_MASK
;
5557 val
|= (PCIX_CAPS_MAX_BURST_CPIOB
<< PCIX_CAPS_BURST_SHIFT
);
5558 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
5559 val
&= ~(PCIX_CAPS_SPLIT_MASK
| PCIX_CAPS_BURST_MASK
);
5560 val
|= (PCIX_CAPS_MAX_BURST_CPIOB
<< PCIX_CAPS_BURST_SHIFT
);
5561 if (tp
->tg3_flags
& TG3_FLAG_SPLIT_MODE
)
5562 val
|= (tp
->split_mode_max_reqs
<<
5563 PCIX_CAPS_SPLIT_SHIFT
);
5565 tw32(TG3PCI_X_CAPS
, val
);
5568 tw32_f(RDMAC_MODE
, rdmac_mode
);
5571 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
5572 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
5573 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
5574 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
5575 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
5576 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
5577 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
5578 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
5579 #if TG3_TSO_SUPPORT != 0
5580 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5581 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
5583 tw32(SNDBDI_MODE
, SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
);
5584 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
5586 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
5587 err
= tg3_load_5701_a0_firmware_fix(tp
);
5592 #if TG3_TSO_SUPPORT != 0
5593 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
5594 err
= tg3_load_tso_firmware(tp
);
5600 tp
->tx_mode
= TX_MODE_ENABLE
;
5601 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
5604 tp
->rx_mode
= RX_MODE_ENABLE
;
5605 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
5608 if (tp
->link_config
.phy_is_low_power
) {
5609 tp
->link_config
.phy_is_low_power
= 0;
5610 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
5611 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
5612 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
5615 tp
->mi_mode
= MAC_MI_MODE_BASE
;
5616 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
5619 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
5621 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
5622 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
5623 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
5626 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
5629 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
5630 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
5631 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
5632 /* Set drive transmission level to 1.2V */
5633 /* only if the signal pre-emphasis bit is not set */
5634 val
= tr32(MAC_SERDES_CFG
);
5637 tw32(MAC_SERDES_CFG
, val
);
5639 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
5640 tw32(MAC_SERDES_CFG
, 0x616000);
5643 /* Prevent chip from dropping frames when flow control
5646 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, 2);
5648 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
5649 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
5650 /* Use hardware link auto-negotiation */
5651 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
5654 err
= tg3_setup_phy(tp
, 1);
5658 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
5661 /* Clear CRC stats. */
5662 if (!tg3_readphy(tp
, 0x1e, &tmp
)) {
5663 tg3_writephy(tp
, 0x1e, tmp
| 0x8000);
5664 tg3_readphy(tp
, 0x14, &tmp
);
5668 __tg3_set_rx_mode(tp
->dev
);
5670 /* Initialize receive rules. */
5671 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
5672 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
5673 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
5674 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
5676 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
5680 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
5684 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
5686 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
5688 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
5690 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
5692 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
5694 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
5696 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
5698 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
5700 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
5702 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
5704 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
5706 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
5708 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
5710 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
5718 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
5720 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
5721 tg3_enable_ints(tp
);
5726 /* Called at device open time to get the chip ready for
5727 * packet processing. Invoked with tp->lock held.
5729 static int tg3_init_hw(struct tg3
*tp
)
5733 /* Force the chip into D0. */
5734 err
= tg3_set_power_state(tp
, 0);
5738 tg3_switch_clocks(tp
);
5740 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
5742 err
= tg3_reset_hw(tp
);
5748 #define TG3_STAT_ADD32(PSTAT, REG) \
5749 do { u32 __val = tr32(REG); \
5750 (PSTAT)->low += __val; \
5751 if ((PSTAT)->low < __val) \
5752 (PSTAT)->high += 1; \
5755 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
5757 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
5759 if (!netif_carrier_ok(tp
->dev
))
5762 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
5763 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
5764 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
5765 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
5766 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
5767 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
5768 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
5769 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
5770 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
5771 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
5772 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
5773 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
5774 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
5776 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
5777 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
5778 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
5779 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
5780 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
5781 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
5782 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
5783 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
5784 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
5785 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
5786 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
5787 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
5788 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
5789 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
5792 static void tg3_timer(unsigned long __opaque
)
5794 struct tg3
*tp
= (struct tg3
*) __opaque
;
5795 unsigned long flags
;
5797 spin_lock_irqsave(&tp
->lock
, flags
);
5798 spin_lock(&tp
->tx_lock
);
5800 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
5801 /* All of this garbage is because when using non-tagged
5802 * IRQ status the mailbox/status_block protocol the chip
5803 * uses with the cpu is race prone.
5805 if (tp
->hw_status
->status
& SD_STATUS_UPDATED
) {
5806 tw32(GRC_LOCAL_CTRL
,
5807 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
5809 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
5810 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
5813 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
5814 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
5815 spin_unlock(&tp
->tx_lock
);
5816 spin_unlock_irqrestore(&tp
->lock
, flags
);
5817 schedule_work(&tp
->reset_task
);
5822 /* This part only runs once per second. */
5823 if (!--tp
->timer_counter
) {
5824 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
5825 tg3_periodic_fetch_stats(tp
);
5827 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
5831 mac_stat
= tr32(MAC_STATUS
);
5834 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
5835 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
5837 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
5841 tg3_setup_phy(tp
, 0);
5842 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
5843 u32 mac_stat
= tr32(MAC_STATUS
);
5846 if (netif_carrier_ok(tp
->dev
) &&
5847 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
5850 if (! netif_carrier_ok(tp
->dev
) &&
5851 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
5852 MAC_STATUS_SIGNAL_DET
))) {
5858 ~MAC_MODE_PORT_MODE_MASK
));
5860 tw32_f(MAC_MODE
, tp
->mac_mode
);
5862 tg3_setup_phy(tp
, 0);
5866 tp
->timer_counter
= tp
->timer_multiplier
;
5869 /* Heartbeat is only sent once every 120 seconds. */
5870 if (!--tp
->asf_counter
) {
5871 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
5874 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_ALIVE
);
5875 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
5876 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, 3);
5877 val
= tr32(GRC_RX_CPU_EVENT
);
5879 tw32(GRC_RX_CPU_EVENT
, val
);
5881 tp
->asf_counter
= tp
->asf_multiplier
;
5884 spin_unlock(&tp
->tx_lock
);
5885 spin_unlock_irqrestore(&tp
->lock
, flags
);
5887 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
5888 add_timer(&tp
->timer
);
5891 static int tg3_test_interrupt(struct tg3
*tp
)
5893 struct net_device
*dev
= tp
->dev
;
5897 if (!netif_running(dev
))
5900 tg3_disable_ints(tp
);
5902 free_irq(tp
->pdev
->irq
, dev
);
5904 err
= request_irq(tp
->pdev
->irq
, tg3_test_isr
,
5905 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
5909 tg3_enable_ints(tp
);
5911 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
5914 for (i
= 0; i
< 5; i
++) {
5915 int_mbox
= tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
5921 tg3_disable_ints(tp
);
5923 free_irq(tp
->pdev
->irq
, dev
);
5925 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
5926 err
= request_irq(tp
->pdev
->irq
, tg3_msi
,
5927 SA_SAMPLE_RANDOM
, dev
->name
, dev
);
5929 irqreturn_t (*fn
)(int, void *, struct pt_regs
*)=tg3_interrupt
;
5930 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
5931 fn
= tg3_interrupt_tagged
;
5932 err
= request_irq(tp
->pdev
->irq
, fn
,
5933 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
5945 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5946 * successfully restored
5948 static int tg3_test_msi(struct tg3
*tp
)
5950 struct net_device
*dev
= tp
->dev
;
5954 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
5957 /* Turn off SERR reporting in case MSI terminates with Master
5960 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
5961 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
5962 pci_cmd
& ~PCI_COMMAND_SERR
);
5964 err
= tg3_test_interrupt(tp
);
5966 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
5971 /* other failures */
5975 /* MSI test failed, go back to INTx mode */
5976 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
5977 "switching to INTx mode. Please report this failure to "
5978 "the PCI maintainer and include system chipset information.\n",
5981 free_irq(tp
->pdev
->irq
, dev
);
5982 pci_disable_msi(tp
->pdev
);
5984 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
5987 irqreturn_t (*fn
)(int, void *, struct pt_regs
*)=tg3_interrupt
;
5988 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
5989 fn
= tg3_interrupt_tagged
;
5991 err
= request_irq(tp
->pdev
->irq
, fn
,
5992 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
5997 /* Need to reset the chip because the MSI cycle may have terminated
5998 * with Master Abort.
6000 spin_lock_irq(&tp
->lock
);
6001 spin_lock(&tp
->tx_lock
);
6003 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6004 err
= tg3_init_hw(tp
);
6006 spin_unlock(&tp
->tx_lock
);
6007 spin_unlock_irq(&tp
->lock
);
6010 free_irq(tp
->pdev
->irq
, dev
);
6015 static int tg3_open(struct net_device
*dev
)
6017 struct tg3
*tp
= netdev_priv(dev
);
6020 spin_lock_irq(&tp
->lock
);
6021 spin_lock(&tp
->tx_lock
);
6023 tg3_disable_ints(tp
);
6024 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
6026 spin_unlock(&tp
->tx_lock
);
6027 spin_unlock_irq(&tp
->lock
);
6029 /* The placement of this call is tied
6030 * to the setup and use of Host TX descriptors.
6032 err
= tg3_alloc_consistent(tp
);
6036 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
6037 (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5750_AX
) &&
6038 (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5750_BX
)) {
6039 /* All MSI supporting chips should support tagged
6040 * status. Assert that this is the case.
6042 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
6043 printk(KERN_WARNING PFX
"%s: MSI without TAGGED? "
6044 "Not using MSI.\n", tp
->dev
->name
);
6045 } else if (pci_enable_msi(tp
->pdev
) == 0) {
6048 msi_mode
= tr32(MSGINT_MODE
);
6049 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
6050 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
6053 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
6054 err
= request_irq(tp
->pdev
->irq
, tg3_msi
,
6055 SA_SAMPLE_RANDOM
, dev
->name
, dev
);
6057 irqreturn_t (*fn
)(int, void *, struct pt_regs
*)=tg3_interrupt
;
6058 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
6059 fn
= tg3_interrupt_tagged
;
6061 err
= request_irq(tp
->pdev
->irq
, fn
,
6062 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
6066 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6067 pci_disable_msi(tp
->pdev
);
6068 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
6070 tg3_free_consistent(tp
);
6074 spin_lock_irq(&tp
->lock
);
6075 spin_lock(&tp
->tx_lock
);
6077 err
= tg3_init_hw(tp
);
6079 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6082 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
6083 tp
->timer_offset
= HZ
;
6085 tp
->timer_offset
= HZ
/ 10;
6087 BUG_ON(tp
->timer_offset
> HZ
);
6088 tp
->timer_counter
= tp
->timer_multiplier
=
6089 (HZ
/ tp
->timer_offset
);
6090 tp
->asf_counter
= tp
->asf_multiplier
=
6091 ((HZ
/ tp
->timer_offset
) * 120);
6093 init_timer(&tp
->timer
);
6094 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
6095 tp
->timer
.data
= (unsigned long) tp
;
6096 tp
->timer
.function
= tg3_timer
;
6099 spin_unlock(&tp
->tx_lock
);
6100 spin_unlock_irq(&tp
->lock
);
6103 free_irq(tp
->pdev
->irq
, dev
);
6104 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6105 pci_disable_msi(tp
->pdev
);
6106 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
6108 tg3_free_consistent(tp
);
6112 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6113 err
= tg3_test_msi(tp
);
6116 spin_lock_irq(&tp
->lock
);
6117 spin_lock(&tp
->tx_lock
);
6119 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6120 pci_disable_msi(tp
->pdev
);
6121 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
6123 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6125 tg3_free_consistent(tp
);
6127 spin_unlock(&tp
->tx_lock
);
6128 spin_unlock_irq(&tp
->lock
);
6134 spin_lock_irq(&tp
->lock
);
6135 spin_lock(&tp
->tx_lock
);
6137 add_timer(&tp
->timer
);
6138 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
6139 tg3_enable_ints(tp
);
6141 spin_unlock(&tp
->tx_lock
);
6142 spin_unlock_irq(&tp
->lock
);
6144 netif_start_queue(dev
);
6150 /*static*/ void tg3_dump_state(struct tg3
*tp
)
6152 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
6156 pci_read_config_word(tp
->pdev
, PCI_STATUS
, &val16
);
6157 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, &val32
);
6158 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6162 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6163 tr32(MAC_MODE
), tr32(MAC_STATUS
));
6164 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6165 tr32(MAC_EVENT
), tr32(MAC_LED_CTRL
));
6166 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6167 tr32(MAC_TX_MODE
), tr32(MAC_TX_STATUS
));
6168 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6169 tr32(MAC_RX_MODE
), tr32(MAC_RX_STATUS
));
6171 /* Send data initiator control block */
6172 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6173 tr32(SNDDATAI_MODE
), tr32(SNDDATAI_STATUS
));
6174 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6175 tr32(SNDDATAI_STATSCTRL
));
6177 /* Send data completion control block */
6178 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE
));
6180 /* Send BD ring selector block */
6181 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6182 tr32(SNDBDS_MODE
), tr32(SNDBDS_STATUS
));
6184 /* Send BD initiator control block */
6185 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6186 tr32(SNDBDI_MODE
), tr32(SNDBDI_STATUS
));
6188 /* Send BD completion control block */
6189 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE
));
6191 /* Receive list placement control block */
6192 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6193 tr32(RCVLPC_MODE
), tr32(RCVLPC_STATUS
));
6194 printk(" RCVLPC_STATSCTRL[%08x]\n",
6195 tr32(RCVLPC_STATSCTRL
));
6197 /* Receive data and receive BD initiator control block */
6198 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6199 tr32(RCVDBDI_MODE
), tr32(RCVDBDI_STATUS
));
6201 /* Receive data completion control block */
6202 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6205 /* Receive BD initiator control block */
6206 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6207 tr32(RCVBDI_MODE
), tr32(RCVBDI_STATUS
));
6209 /* Receive BD completion control block */
6210 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6211 tr32(RCVCC_MODE
), tr32(RCVCC_STATUS
));
6213 /* Receive list selector control block */
6214 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6215 tr32(RCVLSC_MODE
), tr32(RCVLSC_STATUS
));
6217 /* Mbuf cluster free block */
6218 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6219 tr32(MBFREE_MODE
), tr32(MBFREE_STATUS
));
6221 /* Host coalescing control block */
6222 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6223 tr32(HOSTCC_MODE
), tr32(HOSTCC_STATUS
));
6224 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6225 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6226 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
6227 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6228 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6229 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
6230 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6231 tr32(HOSTCC_STATS_BLK_NIC_ADDR
));
6232 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6233 tr32(HOSTCC_STATUS_BLK_NIC_ADDR
));
6235 /* Memory arbiter control block */
6236 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6237 tr32(MEMARB_MODE
), tr32(MEMARB_STATUS
));
6239 /* Buffer manager control block */
6240 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6241 tr32(BUFMGR_MODE
), tr32(BUFMGR_STATUS
));
6242 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6243 tr32(BUFMGR_MB_POOL_ADDR
), tr32(BUFMGR_MB_POOL_SIZE
));
6244 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6245 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6246 tr32(BUFMGR_DMA_DESC_POOL_ADDR
),
6247 tr32(BUFMGR_DMA_DESC_POOL_SIZE
));
6249 /* Read DMA control block */
6250 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6251 tr32(RDMAC_MODE
), tr32(RDMAC_STATUS
));
6253 /* Write DMA control block */
6254 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6255 tr32(WDMAC_MODE
), tr32(WDMAC_STATUS
));
6257 /* DMA completion block */
6258 printk("DEBUG: DMAC_MODE[%08x]\n",
6262 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6263 tr32(GRC_MODE
), tr32(GRC_MISC_CFG
));
6264 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6265 tr32(GRC_LOCAL_CTRL
));
6268 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6269 tr32(RCVDBDI_JUMBO_BD
+ 0x0),
6270 tr32(RCVDBDI_JUMBO_BD
+ 0x4),
6271 tr32(RCVDBDI_JUMBO_BD
+ 0x8),
6272 tr32(RCVDBDI_JUMBO_BD
+ 0xc));
6273 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6274 tr32(RCVDBDI_STD_BD
+ 0x0),
6275 tr32(RCVDBDI_STD_BD
+ 0x4),
6276 tr32(RCVDBDI_STD_BD
+ 0x8),
6277 tr32(RCVDBDI_STD_BD
+ 0xc));
6278 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6279 tr32(RCVDBDI_MINI_BD
+ 0x0),
6280 tr32(RCVDBDI_MINI_BD
+ 0x4),
6281 tr32(RCVDBDI_MINI_BD
+ 0x8),
6282 tr32(RCVDBDI_MINI_BD
+ 0xc));
6284 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x0, &val32
);
6285 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x4, &val32_2
);
6286 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x8, &val32_3
);
6287 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0xc, &val32_4
);
6288 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6289 val32
, val32_2
, val32_3
, val32_4
);
6291 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x0, &val32
);
6292 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x4, &val32_2
);
6293 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x8, &val32_3
);
6294 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0xc, &val32_4
);
6295 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6296 val32
, val32_2
, val32_3
, val32_4
);
6298 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x0, &val32
);
6299 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x4, &val32_2
);
6300 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x8, &val32_3
);
6301 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0xc, &val32_4
);
6302 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x10, &val32_5
);
6303 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6304 val32
, val32_2
, val32_3
, val32_4
, val32_5
);
6306 /* SW status block */
6307 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6308 tp
->hw_status
->status
,
6309 tp
->hw_status
->status_tag
,
6310 tp
->hw_status
->rx_jumbo_consumer
,
6311 tp
->hw_status
->rx_consumer
,
6312 tp
->hw_status
->rx_mini_consumer
,
6313 tp
->hw_status
->idx
[0].rx_producer
,
6314 tp
->hw_status
->idx
[0].tx_consumer
);
6316 /* SW statistics block */
6317 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6318 ((u32
*)tp
->hw_stats
)[0],
6319 ((u32
*)tp
->hw_stats
)[1],
6320 ((u32
*)tp
->hw_stats
)[2],
6321 ((u32
*)tp
->hw_stats
)[3]);
6324 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6325 tr32(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x0),
6326 tr32(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x4),
6327 tr32(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x0),
6328 tr32(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x4));
6330 /* NIC side send descriptors. */
6331 for (i
= 0; i
< 6; i
++) {
6334 txd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_TX_BUFFER_DESC
6335 + (i
* sizeof(struct tg3_tx_buffer_desc
));
6336 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6338 readl(txd
+ 0x0), readl(txd
+ 0x4),
6339 readl(txd
+ 0x8), readl(txd
+ 0xc));
6342 /* NIC side RX descriptors. */
6343 for (i
= 0; i
< 6; i
++) {
6346 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_BUFFER_DESC
6347 + (i
* sizeof(struct tg3_rx_buffer_desc
));
6348 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6350 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
6351 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
6352 rxd
+= (4 * sizeof(u32
));
6353 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6355 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
6356 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
6359 for (i
= 0; i
< 6; i
++) {
6362 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_JUMBO_BUFFER_DESC
6363 + (i
* sizeof(struct tg3_rx_buffer_desc
));
6364 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6366 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
6367 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
6368 rxd
+= (4 * sizeof(u32
));
6369 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6371 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
6372 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
6377 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
6378 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
6380 static int tg3_close(struct net_device
*dev
)
6382 struct tg3
*tp
= netdev_priv(dev
);
6384 netif_stop_queue(dev
);
6386 del_timer_sync(&tp
->timer
);
6388 spin_lock_irq(&tp
->lock
);
6389 spin_lock(&tp
->tx_lock
);
6394 tg3_disable_ints(tp
);
6396 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6399 ~(TG3_FLAG_INIT_COMPLETE
|
6400 TG3_FLAG_GOT_SERDES_FLOWCTL
);
6401 netif_carrier_off(tp
->dev
);
6403 spin_unlock(&tp
->tx_lock
);
6404 spin_unlock_irq(&tp
->lock
);
6406 free_irq(tp
->pdev
->irq
, dev
);
6407 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6408 pci_disable_msi(tp
->pdev
);
6409 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
6412 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
6413 sizeof(tp
->net_stats_prev
));
6414 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
6415 sizeof(tp
->estats_prev
));
6417 tg3_free_consistent(tp
);
6422 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
6426 #if (BITS_PER_LONG == 32)
6429 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
6434 static unsigned long calc_crc_errors(struct tg3
*tp
)
6436 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
6438 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
6439 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
6440 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
6441 unsigned long flags
;
6444 spin_lock_irqsave(&tp
->lock
, flags
);
6445 if (!tg3_readphy(tp
, 0x1e, &val
)) {
6446 tg3_writephy(tp
, 0x1e, val
| 0x8000);
6447 tg3_readphy(tp
, 0x14, &val
);
6450 spin_unlock_irqrestore(&tp
->lock
, flags
);
6452 tp
->phy_crc_errors
+= val
;
6454 return tp
->phy_crc_errors
;
6457 return get_stat64(&hw_stats
->rx_fcs_errors
);
6460 #define ESTAT_ADD(member) \
6461 estats->member = old_estats->member + \
6462 get_stat64(&hw_stats->member)
6464 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
6466 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
6467 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
6468 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
6473 ESTAT_ADD(rx_octets
);
6474 ESTAT_ADD(rx_fragments
);
6475 ESTAT_ADD(rx_ucast_packets
);
6476 ESTAT_ADD(rx_mcast_packets
);
6477 ESTAT_ADD(rx_bcast_packets
);
6478 ESTAT_ADD(rx_fcs_errors
);
6479 ESTAT_ADD(rx_align_errors
);
6480 ESTAT_ADD(rx_xon_pause_rcvd
);
6481 ESTAT_ADD(rx_xoff_pause_rcvd
);
6482 ESTAT_ADD(rx_mac_ctrl_rcvd
);
6483 ESTAT_ADD(rx_xoff_entered
);
6484 ESTAT_ADD(rx_frame_too_long_errors
);
6485 ESTAT_ADD(rx_jabbers
);
6486 ESTAT_ADD(rx_undersize_packets
);
6487 ESTAT_ADD(rx_in_length_errors
);
6488 ESTAT_ADD(rx_out_length_errors
);
6489 ESTAT_ADD(rx_64_or_less_octet_packets
);
6490 ESTAT_ADD(rx_65_to_127_octet_packets
);
6491 ESTAT_ADD(rx_128_to_255_octet_packets
);
6492 ESTAT_ADD(rx_256_to_511_octet_packets
);
6493 ESTAT_ADD(rx_512_to_1023_octet_packets
);
6494 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
6495 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
6496 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
6497 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
6498 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
6500 ESTAT_ADD(tx_octets
);
6501 ESTAT_ADD(tx_collisions
);
6502 ESTAT_ADD(tx_xon_sent
);
6503 ESTAT_ADD(tx_xoff_sent
);
6504 ESTAT_ADD(tx_flow_control
);
6505 ESTAT_ADD(tx_mac_errors
);
6506 ESTAT_ADD(tx_single_collisions
);
6507 ESTAT_ADD(tx_mult_collisions
);
6508 ESTAT_ADD(tx_deferred
);
6509 ESTAT_ADD(tx_excessive_collisions
);
6510 ESTAT_ADD(tx_late_collisions
);
6511 ESTAT_ADD(tx_collide_2times
);
6512 ESTAT_ADD(tx_collide_3times
);
6513 ESTAT_ADD(tx_collide_4times
);
6514 ESTAT_ADD(tx_collide_5times
);
6515 ESTAT_ADD(tx_collide_6times
);
6516 ESTAT_ADD(tx_collide_7times
);
6517 ESTAT_ADD(tx_collide_8times
);
6518 ESTAT_ADD(tx_collide_9times
);
6519 ESTAT_ADD(tx_collide_10times
);
6520 ESTAT_ADD(tx_collide_11times
);
6521 ESTAT_ADD(tx_collide_12times
);
6522 ESTAT_ADD(tx_collide_13times
);
6523 ESTAT_ADD(tx_collide_14times
);
6524 ESTAT_ADD(tx_collide_15times
);
6525 ESTAT_ADD(tx_ucast_packets
);
6526 ESTAT_ADD(tx_mcast_packets
);
6527 ESTAT_ADD(tx_bcast_packets
);
6528 ESTAT_ADD(tx_carrier_sense_errors
);
6529 ESTAT_ADD(tx_discards
);
6530 ESTAT_ADD(tx_errors
);
6532 ESTAT_ADD(dma_writeq_full
);
6533 ESTAT_ADD(dma_write_prioq_full
);
6534 ESTAT_ADD(rxbds_empty
);
6535 ESTAT_ADD(rx_discards
);
6536 ESTAT_ADD(rx_errors
);
6537 ESTAT_ADD(rx_threshold_hit
);
6539 ESTAT_ADD(dma_readq_full
);
6540 ESTAT_ADD(dma_read_prioq_full
);
6541 ESTAT_ADD(tx_comp_queue_full
);
6543 ESTAT_ADD(ring_set_send_prod_index
);
6544 ESTAT_ADD(ring_status_update
);
6545 ESTAT_ADD(nic_irqs
);
6546 ESTAT_ADD(nic_avoided_irqs
);
6547 ESTAT_ADD(nic_tx_threshold_hit
);
6552 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
6554 struct tg3
*tp
= netdev_priv(dev
);
6555 struct net_device_stats
*stats
= &tp
->net_stats
;
6556 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
6557 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
6562 stats
->rx_packets
= old_stats
->rx_packets
+
6563 get_stat64(&hw_stats
->rx_ucast_packets
) +
6564 get_stat64(&hw_stats
->rx_mcast_packets
) +
6565 get_stat64(&hw_stats
->rx_bcast_packets
);
6567 stats
->tx_packets
= old_stats
->tx_packets
+
6568 get_stat64(&hw_stats
->tx_ucast_packets
) +
6569 get_stat64(&hw_stats
->tx_mcast_packets
) +
6570 get_stat64(&hw_stats
->tx_bcast_packets
);
6572 stats
->rx_bytes
= old_stats
->rx_bytes
+
6573 get_stat64(&hw_stats
->rx_octets
);
6574 stats
->tx_bytes
= old_stats
->tx_bytes
+
6575 get_stat64(&hw_stats
->tx_octets
);
6577 stats
->rx_errors
= old_stats
->rx_errors
+
6578 get_stat64(&hw_stats
->rx_errors
) +
6579 get_stat64(&hw_stats
->rx_discards
);
6580 stats
->tx_errors
= old_stats
->tx_errors
+
6581 get_stat64(&hw_stats
->tx_errors
) +
6582 get_stat64(&hw_stats
->tx_mac_errors
) +
6583 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
6584 get_stat64(&hw_stats
->tx_discards
);
6586 stats
->multicast
= old_stats
->multicast
+
6587 get_stat64(&hw_stats
->rx_mcast_packets
);
6588 stats
->collisions
= old_stats
->collisions
+
6589 get_stat64(&hw_stats
->tx_collisions
);
6591 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
6592 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
6593 get_stat64(&hw_stats
->rx_undersize_packets
);
6595 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
6596 get_stat64(&hw_stats
->rxbds_empty
);
6597 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
6598 get_stat64(&hw_stats
->rx_align_errors
);
6599 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
6600 get_stat64(&hw_stats
->tx_discards
);
6601 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
6602 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
6604 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
6605 calc_crc_errors(tp
);
6610 static inline u32
calc_crc(unsigned char *buf
, int len
)
6618 for (j
= 0; j
< len
; j
++) {
6621 for (k
= 0; k
< 8; k
++) {
6635 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
6637 /* accept or reject all multicast frames */
6638 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
6639 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
6640 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
6641 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
6644 static void __tg3_set_rx_mode(struct net_device
*dev
)
6646 struct tg3
*tp
= netdev_priv(dev
);
6649 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
6650 RX_MODE_KEEP_VLAN_TAG
);
6652 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6655 #if TG3_VLAN_TAG_USED
6657 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
6658 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
6660 /* By definition, VLAN is disabled always in this
6663 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
6664 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
6667 if (dev
->flags
& IFF_PROMISC
) {
6668 /* Promiscuous mode. */
6669 rx_mode
|= RX_MODE_PROMISC
;
6670 } else if (dev
->flags
& IFF_ALLMULTI
) {
6671 /* Accept all multicast. */
6672 tg3_set_multi (tp
, 1);
6673 } else if (dev
->mc_count
< 1) {
6674 /* Reject all multicast. */
6675 tg3_set_multi (tp
, 0);
6677 /* Accept one or more multicast(s). */
6678 struct dev_mc_list
*mclist
;
6680 u32 mc_filter
[4] = { 0, };
6685 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
6686 i
++, mclist
= mclist
->next
) {
6688 crc
= calc_crc (mclist
->dmi_addr
, ETH_ALEN
);
6690 regidx
= (bit
& 0x60) >> 5;
6692 mc_filter
[regidx
] |= (1 << bit
);
6695 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
6696 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
6697 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
6698 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
6701 if (rx_mode
!= tp
->rx_mode
) {
6702 tp
->rx_mode
= rx_mode
;
6703 tw32_f(MAC_RX_MODE
, rx_mode
);
6708 static void tg3_set_rx_mode(struct net_device
*dev
)
6710 struct tg3
*tp
= netdev_priv(dev
);
6712 spin_lock_irq(&tp
->lock
);
6713 spin_lock(&tp
->tx_lock
);
6714 __tg3_set_rx_mode(dev
);
6715 spin_unlock(&tp
->tx_lock
);
6716 spin_unlock_irq(&tp
->lock
);
6719 #define TG3_REGDUMP_LEN (32 * 1024)
6721 static int tg3_get_regs_len(struct net_device
*dev
)
6723 return TG3_REGDUMP_LEN
;
6726 static void tg3_get_regs(struct net_device
*dev
,
6727 struct ethtool_regs
*regs
, void *_p
)
6730 struct tg3
*tp
= netdev_priv(dev
);
6736 memset(p
, 0, TG3_REGDUMP_LEN
);
6738 spin_lock_irq(&tp
->lock
);
6739 spin_lock(&tp
->tx_lock
);
6741 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
6742 #define GET_REG32_LOOP(base,len) \
6743 do { p = (u32 *)(orig_p + (base)); \
6744 for (i = 0; i < len; i += 4) \
6745 __GET_REG32((base) + i); \
6747 #define GET_REG32_1(reg) \
6748 do { p = (u32 *)(orig_p + (reg)); \
6749 __GET_REG32((reg)); \
6752 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
6753 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
6754 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
6755 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
6756 GET_REG32_1(SNDDATAC_MODE
);
6757 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
6758 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
6759 GET_REG32_1(SNDBDC_MODE
);
6760 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
6761 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
6762 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
6763 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
6764 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
6765 GET_REG32_1(RCVDCC_MODE
);
6766 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
6767 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
6768 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
6769 GET_REG32_1(MBFREE_MODE
);
6770 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
6771 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
6772 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
6773 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
6774 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
6775 GET_REG32_LOOP(RX_CPU_BASE
, 0x280);
6776 GET_REG32_LOOP(TX_CPU_BASE
, 0x280);
6777 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
6778 GET_REG32_LOOP(FTQ_RESET
, 0x120);
6779 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
6780 GET_REG32_1(DMAC_MODE
);
6781 GET_REG32_LOOP(GRC_MODE
, 0x4c);
6782 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
6783 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
6786 #undef GET_REG32_LOOP
6789 spin_unlock(&tp
->tx_lock
);
6790 spin_unlock_irq(&tp
->lock
);
6793 static int tg3_get_eeprom_len(struct net_device
*dev
)
6795 struct tg3
*tp
= netdev_priv(dev
);
6797 return tp
->nvram_size
;
6800 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
);
6802 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
6804 struct tg3
*tp
= netdev_priv(dev
);
6807 u32 i
, offset
, len
, val
, b_offset
, b_count
;
6809 offset
= eeprom
->offset
;
6813 eeprom
->magic
= TG3_EEPROM_MAGIC
;
6816 /* adjustments to start on required 4 byte boundary */
6817 b_offset
= offset
& 3;
6818 b_count
= 4 - b_offset
;
6819 if (b_count
> len
) {
6820 /* i.e. offset=1 len=2 */
6823 ret
= tg3_nvram_read(tp
, offset
-b_offset
, &val
);
6826 val
= cpu_to_le32(val
);
6827 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
6830 eeprom
->len
+= b_count
;
6833 /* read bytes upto the last 4 byte boundary */
6834 pd
= &data
[eeprom
->len
];
6835 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
6836 ret
= tg3_nvram_read(tp
, offset
+ i
, &val
);
6841 val
= cpu_to_le32(val
);
6842 memcpy(pd
+ i
, &val
, 4);
6847 /* read last bytes not ending on 4 byte boundary */
6848 pd
= &data
[eeprom
->len
];
6850 b_offset
= offset
+ len
- b_count
;
6851 ret
= tg3_nvram_read(tp
, b_offset
, &val
);
6854 val
= cpu_to_le32(val
);
6855 memcpy(pd
, ((char*)&val
), b_count
);
6856 eeprom
->len
+= b_count
;
6861 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
6863 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
6865 struct tg3
*tp
= netdev_priv(dev
);
6867 u32 offset
, len
, b_offset
, odd_len
, start
, end
;
6870 if (eeprom
->magic
!= TG3_EEPROM_MAGIC
)
6873 offset
= eeprom
->offset
;
6876 if ((b_offset
= (offset
& 3))) {
6877 /* adjustments to start on required 4 byte boundary */
6878 ret
= tg3_nvram_read(tp
, offset
-b_offset
, &start
);
6881 start
= cpu_to_le32(start
);
6890 /* adjustments to end on required 4 byte boundary */
6892 len
= (len
+ 3) & ~3;
6893 ret
= tg3_nvram_read(tp
, offset
+len
-4, &end
);
6896 end
= cpu_to_le32(end
);
6900 if (b_offset
|| odd_len
) {
6901 buf
= kmalloc(len
, GFP_KERNEL
);
6905 memcpy(buf
, &start
, 4);
6907 memcpy(buf
+len
-4, &end
, 4);
6908 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
6911 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
6919 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6921 struct tg3
*tp
= netdev_priv(dev
);
6923 cmd
->supported
= (SUPPORTED_Autoneg
);
6925 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
6926 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
6927 SUPPORTED_1000baseT_Full
);
6929 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
))
6930 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
6931 SUPPORTED_100baseT_Full
|
6932 SUPPORTED_10baseT_Half
|
6933 SUPPORTED_10baseT_Full
|
6936 cmd
->supported
|= SUPPORTED_FIBRE
;
6938 cmd
->advertising
= tp
->link_config
.advertising
;
6939 if (netif_running(dev
)) {
6940 cmd
->speed
= tp
->link_config
.active_speed
;
6941 cmd
->duplex
= tp
->link_config
.active_duplex
;
6944 cmd
->phy_address
= PHY_ADDR
;
6945 cmd
->transceiver
= 0;
6946 cmd
->autoneg
= tp
->link_config
.autoneg
;
6952 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6954 struct tg3
*tp
= netdev_priv(dev
);
6956 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
6957 /* These are the only valid advertisement bits allowed. */
6958 if (cmd
->autoneg
== AUTONEG_ENABLE
&&
6959 (cmd
->advertising
& ~(ADVERTISED_1000baseT_Half
|
6960 ADVERTISED_1000baseT_Full
|
6961 ADVERTISED_Autoneg
|
6966 spin_lock_irq(&tp
->lock
);
6967 spin_lock(&tp
->tx_lock
);
6969 tp
->link_config
.autoneg
= cmd
->autoneg
;
6970 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
6971 tp
->link_config
.advertising
= cmd
->advertising
;
6972 tp
->link_config
.speed
= SPEED_INVALID
;
6973 tp
->link_config
.duplex
= DUPLEX_INVALID
;
6975 tp
->link_config
.advertising
= 0;
6976 tp
->link_config
.speed
= cmd
->speed
;
6977 tp
->link_config
.duplex
= cmd
->duplex
;
6980 if (netif_running(dev
))
6981 tg3_setup_phy(tp
, 1);
6983 spin_unlock(&tp
->tx_lock
);
6984 spin_unlock_irq(&tp
->lock
);
6989 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
6991 struct tg3
*tp
= netdev_priv(dev
);
6993 strcpy(info
->driver
, DRV_MODULE_NAME
);
6994 strcpy(info
->version
, DRV_MODULE_VERSION
);
6995 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
6998 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
7000 struct tg3
*tp
= netdev_priv(dev
);
7002 wol
->supported
= WAKE_MAGIC
;
7004 if (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
)
7005 wol
->wolopts
= WAKE_MAGIC
;
7006 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
7009 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
7011 struct tg3
*tp
= netdev_priv(dev
);
7013 if (wol
->wolopts
& ~WAKE_MAGIC
)
7015 if ((wol
->wolopts
& WAKE_MAGIC
) &&
7016 tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
&&
7017 !(tp
->tg3_flags
& TG3_FLAG_SERDES_WOL_CAP
))
7020 spin_lock_irq(&tp
->lock
);
7021 if (wol
->wolopts
& WAKE_MAGIC
)
7022 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
7024 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
7025 spin_unlock_irq(&tp
->lock
);
7030 static u32
tg3_get_msglevel(struct net_device
*dev
)
7032 struct tg3
*tp
= netdev_priv(dev
);
7033 return tp
->msg_enable
;
7036 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
7038 struct tg3
*tp
= netdev_priv(dev
);
7039 tp
->msg_enable
= value
;
7042 #if TG3_TSO_SUPPORT != 0
7043 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
7045 struct tg3
*tp
= netdev_priv(dev
);
7047 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7052 return ethtool_op_set_tso(dev
, value
);
7056 static int tg3_nway_reset(struct net_device
*dev
)
7058 struct tg3
*tp
= netdev_priv(dev
);
7062 if (!netif_running(dev
))
7065 spin_lock_irq(&tp
->lock
);
7067 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
7068 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
7069 (bmcr
& BMCR_ANENABLE
)) {
7070 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
);
7073 spin_unlock_irq(&tp
->lock
);
7078 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
7080 struct tg3
*tp
= netdev_priv(dev
);
7082 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
7083 ering
->rx_mini_max_pending
= 0;
7084 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
7086 ering
->rx_pending
= tp
->rx_pending
;
7087 ering
->rx_mini_pending
= 0;
7088 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
7089 ering
->tx_pending
= tp
->tx_pending
;
7092 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
7094 struct tg3
*tp
= netdev_priv(dev
);
7096 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
7097 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
7098 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1))
7101 if (netif_running(dev
))
7104 spin_lock_irq(&tp
->lock
);
7105 spin_lock(&tp
->tx_lock
);
7107 tp
->rx_pending
= ering
->rx_pending
;
7109 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
7110 tp
->rx_pending
> 63)
7111 tp
->rx_pending
= 63;
7112 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
7113 tp
->tx_pending
= ering
->tx_pending
;
7115 if (netif_running(dev
)) {
7116 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7118 tg3_netif_start(tp
);
7121 spin_unlock(&tp
->tx_lock
);
7122 spin_unlock_irq(&tp
->lock
);
7127 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
7129 struct tg3
*tp
= netdev_priv(dev
);
7131 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
7132 epause
->rx_pause
= (tp
->tg3_flags
& TG3_FLAG_RX_PAUSE
) != 0;
7133 epause
->tx_pause
= (tp
->tg3_flags
& TG3_FLAG_TX_PAUSE
) != 0;
7136 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
7138 struct tg3
*tp
= netdev_priv(dev
);
7140 if (netif_running(dev
))
7143 spin_lock_irq(&tp
->lock
);
7144 spin_lock(&tp
->tx_lock
);
7145 if (epause
->autoneg
)
7146 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
7148 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
7149 if (epause
->rx_pause
)
7150 tp
->tg3_flags
|= TG3_FLAG_RX_PAUSE
;
7152 tp
->tg3_flags
&= ~TG3_FLAG_RX_PAUSE
;
7153 if (epause
->tx_pause
)
7154 tp
->tg3_flags
|= TG3_FLAG_TX_PAUSE
;
7156 tp
->tg3_flags
&= ~TG3_FLAG_TX_PAUSE
;
7158 if (netif_running(dev
)) {
7159 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7161 tg3_netif_start(tp
);
7163 spin_unlock(&tp
->tx_lock
);
7164 spin_unlock_irq(&tp
->lock
);
7169 static u32
tg3_get_rx_csum(struct net_device
*dev
)
7171 struct tg3
*tp
= netdev_priv(dev
);
7172 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
7175 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
7177 struct tg3
*tp
= netdev_priv(dev
);
7179 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
7185 spin_lock_irq(&tp
->lock
);
7187 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
7189 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
7190 spin_unlock_irq(&tp
->lock
);
7195 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
7197 struct tg3
*tp
= netdev_priv(dev
);
7199 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
7206 dev
->features
|= NETIF_F_IP_CSUM
;
7208 dev
->features
&= ~NETIF_F_IP_CSUM
;
7213 static int tg3_get_stats_count (struct net_device
*dev
)
7215 return TG3_NUM_STATS
;
7218 static int tg3_get_test_count (struct net_device
*dev
)
7220 return TG3_NUM_TEST
;
7223 static void tg3_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
7225 switch (stringset
) {
7227 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
7230 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
7233 WARN_ON(1); /* we need a WARN() */
7238 static void tg3_get_ethtool_stats (struct net_device
*dev
,
7239 struct ethtool_stats
*estats
, u64
*tmp_stats
)
7241 struct tg3
*tp
= netdev_priv(dev
);
7242 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
7245 #define NVRAM_TEST_SIZE 0x100
7247 static int tg3_test_nvram(struct tg3
*tp
)
7252 buf
= kmalloc(NVRAM_TEST_SIZE
, GFP_KERNEL
);
7256 for (i
= 0, j
= 0; i
< NVRAM_TEST_SIZE
; i
+= 4, j
++) {
7259 if ((err
= tg3_nvram_read(tp
, i
, &val
)) != 0)
7261 buf
[j
] = cpu_to_le32(val
);
7263 if (i
< NVRAM_TEST_SIZE
)
7267 if (cpu_to_be32(buf
[0]) != TG3_EEPROM_MAGIC
)
7270 /* Bootstrap checksum at offset 0x10 */
7271 csum
= calc_crc((unsigned char *) buf
, 0x10);
7272 if(csum
!= cpu_to_le32(buf
[0x10/4]))
7275 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7276 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
7277 if (csum
!= cpu_to_le32(buf
[0xfc/4]))
7287 #define TG3_SERDES_TIMEOUT_SEC 2
7288 #define TG3_COPPER_TIMEOUT_SEC 6
7290 static int tg3_test_link(struct tg3
*tp
)
7294 if (!netif_running(tp
->dev
))
7297 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
7298 max
= TG3_SERDES_TIMEOUT_SEC
;
7300 max
= TG3_COPPER_TIMEOUT_SEC
;
7302 for (i
= 0; i
< max
; i
++) {
7303 if (netif_carrier_ok(tp
->dev
))
7306 if (msleep_interruptible(1000))
7313 /* Only test the commonly used registers */
7314 static int tg3_test_registers(struct tg3
*tp
)
7317 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
7321 #define TG3_FL_5705 0x1
7322 #define TG3_FL_NOT_5705 0x2
7323 #define TG3_FL_NOT_5788 0x4
7327 /* MAC Control Registers */
7328 { MAC_MODE
, TG3_FL_NOT_5705
,
7329 0x00000000, 0x00ef6f8c },
7330 { MAC_MODE
, TG3_FL_5705
,
7331 0x00000000, 0x01ef6b8c },
7332 { MAC_STATUS
, TG3_FL_NOT_5705
,
7333 0x03800107, 0x00000000 },
7334 { MAC_STATUS
, TG3_FL_5705
,
7335 0x03800100, 0x00000000 },
7336 { MAC_ADDR_0_HIGH
, 0x0000,
7337 0x00000000, 0x0000ffff },
7338 { MAC_ADDR_0_LOW
, 0x0000,
7339 0x00000000, 0xffffffff },
7340 { MAC_RX_MTU_SIZE
, 0x0000,
7341 0x00000000, 0x0000ffff },
7342 { MAC_TX_MODE
, 0x0000,
7343 0x00000000, 0x00000070 },
7344 { MAC_TX_LENGTHS
, 0x0000,
7345 0x00000000, 0x00003fff },
7346 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
7347 0x00000000, 0x000007fc },
7348 { MAC_RX_MODE
, TG3_FL_5705
,
7349 0x00000000, 0x000007dc },
7350 { MAC_HASH_REG_0
, 0x0000,
7351 0x00000000, 0xffffffff },
7352 { MAC_HASH_REG_1
, 0x0000,
7353 0x00000000, 0xffffffff },
7354 { MAC_HASH_REG_2
, 0x0000,
7355 0x00000000, 0xffffffff },
7356 { MAC_HASH_REG_3
, 0x0000,
7357 0x00000000, 0xffffffff },
7359 /* Receive Data and Receive BD Initiator Control Registers. */
7360 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
7361 0x00000000, 0xffffffff },
7362 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
7363 0x00000000, 0xffffffff },
7364 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
7365 0x00000000, 0x00000003 },
7366 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
7367 0x00000000, 0xffffffff },
7368 { RCVDBDI_STD_BD
+0, 0x0000,
7369 0x00000000, 0xffffffff },
7370 { RCVDBDI_STD_BD
+4, 0x0000,
7371 0x00000000, 0xffffffff },
7372 { RCVDBDI_STD_BD
+8, 0x0000,
7373 0x00000000, 0xffff0002 },
7374 { RCVDBDI_STD_BD
+0xc, 0x0000,
7375 0x00000000, 0xffffffff },
7377 /* Receive BD Initiator Control Registers. */
7378 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
7379 0x00000000, 0xffffffff },
7380 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
7381 0x00000000, 0x000003ff },
7382 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
7383 0x00000000, 0xffffffff },
7385 /* Host Coalescing Control Registers. */
7386 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
7387 0x00000000, 0x00000004 },
7388 { HOSTCC_MODE
, TG3_FL_5705
,
7389 0x00000000, 0x000000f6 },
7390 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
7391 0x00000000, 0xffffffff },
7392 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
7393 0x00000000, 0x000003ff },
7394 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
7395 0x00000000, 0xffffffff },
7396 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
7397 0x00000000, 0x000003ff },
7398 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
7399 0x00000000, 0xffffffff },
7400 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
7401 0x00000000, 0x000000ff },
7402 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
7403 0x00000000, 0xffffffff },
7404 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
7405 0x00000000, 0x000000ff },
7406 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
7407 0x00000000, 0xffffffff },
7408 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
7409 0x00000000, 0xffffffff },
7410 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
7411 0x00000000, 0xffffffff },
7412 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
7413 0x00000000, 0x000000ff },
7414 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
7415 0x00000000, 0xffffffff },
7416 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
7417 0x00000000, 0x000000ff },
7418 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
7419 0x00000000, 0xffffffff },
7420 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
7421 0x00000000, 0xffffffff },
7422 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
7423 0x00000000, 0xffffffff },
7424 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
7425 0x00000000, 0xffffffff },
7426 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
7427 0x00000000, 0xffffffff },
7428 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
7429 0xffffffff, 0x00000000 },
7430 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
7431 0xffffffff, 0x00000000 },
7433 /* Buffer Manager Control Registers. */
7434 { BUFMGR_MB_POOL_ADDR
, 0x0000,
7435 0x00000000, 0x007fff80 },
7436 { BUFMGR_MB_POOL_SIZE
, 0x0000,
7437 0x00000000, 0x007fffff },
7438 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
7439 0x00000000, 0x0000003f },
7440 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
7441 0x00000000, 0x000001ff },
7442 { BUFMGR_MB_HIGH_WATER
, 0x0000,
7443 0x00000000, 0x000001ff },
7444 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
7445 0xffffffff, 0x00000000 },
7446 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
7447 0xffffffff, 0x00000000 },
7449 /* Mailbox Registers */
7450 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
7451 0x00000000, 0x000001ff },
7452 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
7453 0x00000000, 0x000001ff },
7454 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
7455 0x00000000, 0x000007ff },
7456 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
7457 0x00000000, 0x000001ff },
7459 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7462 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7467 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
7468 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
7471 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
7474 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
7475 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
7478 offset
= (u32
) reg_tbl
[i
].offset
;
7479 read_mask
= reg_tbl
[i
].read_mask
;
7480 write_mask
= reg_tbl
[i
].write_mask
;
7482 /* Save the original register content */
7483 save_val
= tr32(offset
);
7485 /* Determine the read-only value. */
7486 read_val
= save_val
& read_mask
;
7488 /* Write zero to the register, then make sure the read-only bits
7489 * are not changed and the read/write bits are all zeros.
7495 /* Test the read-only and read/write bits. */
7496 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
7499 /* Write ones to all the bits defined by RdMask and WrMask, then
7500 * make sure the read-only bits are not changed and the
7501 * read/write bits are all ones.
7503 tw32(offset
, read_mask
| write_mask
);
7507 /* Test the read-only bits. */
7508 if ((val
& read_mask
) != read_val
)
7511 /* Test the read/write bits. */
7512 if ((val
& write_mask
) != write_mask
)
7515 tw32(offset
, save_val
);
7521 printk(KERN_ERR PFX
"Register test failed at offset %x\n", offset
);
7522 tw32(offset
, save_val
);
7526 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
7528 static u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7532 for (i
= 0; i
< sizeof(test_pattern
)/sizeof(u32
); i
++) {
7533 for (j
= 0; j
< len
; j
+= 4) {
7536 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
7537 tg3_read_mem(tp
, offset
+ j
, &val
);
7538 if (val
!= test_pattern
[i
])
7545 static int tg3_test_memory(struct tg3
*tp
)
7547 static struct mem_entry
{
7550 } mem_tbl_570x
[] = {
7551 { 0x00000000, 0x01000},
7552 { 0x00002000, 0x1c000},
7553 { 0xffffffff, 0x00000}
7554 }, mem_tbl_5705
[] = {
7555 { 0x00000100, 0x0000c},
7556 { 0x00000200, 0x00008},
7557 { 0x00000b50, 0x00400},
7558 { 0x00004000, 0x00800},
7559 { 0x00006000, 0x01000},
7560 { 0x00008000, 0x02000},
7561 { 0x00010000, 0x0e000},
7562 { 0xffffffff, 0x00000}
7564 struct mem_entry
*mem_tbl
;
7568 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7569 mem_tbl
= mem_tbl_5705
;
7571 mem_tbl
= mem_tbl_570x
;
7573 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
7574 if ((err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
,
7575 mem_tbl
[i
].len
)) != 0)
7582 static int tg3_test_loopback(struct tg3
*tp
)
7584 u32 mac_mode
, send_idx
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
7586 struct sk_buff
*skb
, *rx_skb
;
7589 int num_pkts
, tx_len
, rx_len
, i
, err
;
7590 struct tg3_rx_buffer_desc
*desc
;
7592 if (!netif_running(tp
->dev
))
7597 tg3_abort_hw(tp
, 1);
7599 /* Clearing this flag to keep interrupts disabled */
7600 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
7603 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
7604 MAC_MODE_PORT_INT_LPBACK
| MAC_MODE_LINK_POLARITY
|
7605 MAC_MODE_PORT_MODE_GMII
;
7606 tw32(MAC_MODE
, mac_mode
);
7609 skb
= dev_alloc_skb(tx_len
);
7610 tx_data
= skb_put(skb
, tx_len
);
7611 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
7612 memset(tx_data
+ 6, 0x0, 8);
7614 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
7616 for (i
= 14; i
< tx_len
; i
++)
7617 tx_data
[i
] = (u8
) (i
& 0xff);
7619 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
7621 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
7626 rx_start_idx
= tp
->hw_status
->idx
[0].rx_producer
;
7631 tg3_set_txd(tp
, send_idx
, map
, tx_len
, 0, 1);
7636 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, send_idx
);
7637 tr32(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
);
7641 for (i
= 0; i
< 10; i
++) {
7642 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
7647 tx_idx
= tp
->hw_status
->idx
[0].tx_consumer
;
7648 rx_idx
= tp
->hw_status
->idx
[0].rx_producer
;
7649 if ((tx_idx
== send_idx
) &&
7650 (rx_idx
== (rx_start_idx
+ num_pkts
)))
7654 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
7657 if (tx_idx
!= send_idx
)
7660 if (rx_idx
!= rx_start_idx
+ num_pkts
)
7663 desc
= &tp
->rx_rcb
[rx_start_idx
];
7664 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
7665 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
7666 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
7669 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
7670 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
7673 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
7674 if (rx_len
!= tx_len
)
7677 rx_skb
= tp
->rx_std_buffers
[desc_idx
].skb
;
7679 map
= pci_unmap_addr(&tp
->rx_std_buffers
[desc_idx
], mapping
);
7680 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
7682 for (i
= 14; i
< tx_len
; i
++) {
7683 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
7688 /* tg3_free_rings will unmap and free the rx_skb */
7693 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
7696 struct tg3
*tp
= netdev_priv(dev
);
7698 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
7700 if (tg3_test_nvram(tp
) != 0) {
7701 etest
->flags
|= ETH_TEST_FL_FAILED
;
7704 if (tg3_test_link(tp
) != 0) {
7705 etest
->flags
|= ETH_TEST_FL_FAILED
;
7708 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
7709 if (netif_running(dev
))
7712 spin_lock_irq(&tp
->lock
);
7713 spin_lock(&tp
->tx_lock
);
7715 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
7717 tg3_halt_cpu(tp
, RX_CPU_BASE
);
7718 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7719 tg3_halt_cpu(tp
, TX_CPU_BASE
);
7720 tg3_nvram_unlock(tp
);
7722 if (tg3_test_registers(tp
) != 0) {
7723 etest
->flags
|= ETH_TEST_FL_FAILED
;
7726 if (tg3_test_memory(tp
) != 0) {
7727 etest
->flags
|= ETH_TEST_FL_FAILED
;
7730 if (tg3_test_loopback(tp
) != 0) {
7731 etest
->flags
|= ETH_TEST_FL_FAILED
;
7735 spin_unlock(&tp
->tx_lock
);
7736 spin_unlock_irq(&tp
->lock
);
7737 if (tg3_test_interrupt(tp
) != 0) {
7738 etest
->flags
|= ETH_TEST_FL_FAILED
;
7741 spin_lock_irq(&tp
->lock
);
7742 spin_lock(&tp
->tx_lock
);
7744 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7745 if (netif_running(dev
)) {
7746 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
7748 tg3_netif_start(tp
);
7750 spin_unlock(&tp
->tx_lock
);
7751 spin_unlock_irq(&tp
->lock
);
7755 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7757 struct mii_ioctl_data
*data
= if_mii(ifr
);
7758 struct tg3
*tp
= netdev_priv(dev
);
7763 data
->phy_id
= PHY_ADDR
;
7769 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
7770 break; /* We have no PHY */
7772 spin_lock_irq(&tp
->lock
);
7773 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
7774 spin_unlock_irq(&tp
->lock
);
7776 data
->val_out
= mii_regval
;
7782 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
7783 break; /* We have no PHY */
7785 if (!capable(CAP_NET_ADMIN
))
7788 spin_lock_irq(&tp
->lock
);
7789 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
7790 spin_unlock_irq(&tp
->lock
);
7801 #if TG3_VLAN_TAG_USED
7802 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
7804 struct tg3
*tp
= netdev_priv(dev
);
7806 spin_lock_irq(&tp
->lock
);
7807 spin_lock(&tp
->tx_lock
);
7811 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7812 __tg3_set_rx_mode(dev
);
7814 spin_unlock(&tp
->tx_lock
);
7815 spin_unlock_irq(&tp
->lock
);
7818 static void tg3_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
7820 struct tg3
*tp
= netdev_priv(dev
);
7822 spin_lock_irq(&tp
->lock
);
7823 spin_lock(&tp
->tx_lock
);
7825 tp
->vlgrp
->vlan_devices
[vid
] = NULL
;
7826 spin_unlock(&tp
->tx_lock
);
7827 spin_unlock_irq(&tp
->lock
);
7831 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
7833 struct tg3
*tp
= netdev_priv(dev
);
7835 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
7839 static struct ethtool_ops tg3_ethtool_ops
= {
7840 .get_settings
= tg3_get_settings
,
7841 .set_settings
= tg3_set_settings
,
7842 .get_drvinfo
= tg3_get_drvinfo
,
7843 .get_regs_len
= tg3_get_regs_len
,
7844 .get_regs
= tg3_get_regs
,
7845 .get_wol
= tg3_get_wol
,
7846 .set_wol
= tg3_set_wol
,
7847 .get_msglevel
= tg3_get_msglevel
,
7848 .set_msglevel
= tg3_set_msglevel
,
7849 .nway_reset
= tg3_nway_reset
,
7850 .get_link
= ethtool_op_get_link
,
7851 .get_eeprom_len
= tg3_get_eeprom_len
,
7852 .get_eeprom
= tg3_get_eeprom
,
7853 .set_eeprom
= tg3_set_eeprom
,
7854 .get_ringparam
= tg3_get_ringparam
,
7855 .set_ringparam
= tg3_set_ringparam
,
7856 .get_pauseparam
= tg3_get_pauseparam
,
7857 .set_pauseparam
= tg3_set_pauseparam
,
7858 .get_rx_csum
= tg3_get_rx_csum
,
7859 .set_rx_csum
= tg3_set_rx_csum
,
7860 .get_tx_csum
= ethtool_op_get_tx_csum
,
7861 .set_tx_csum
= tg3_set_tx_csum
,
7862 .get_sg
= ethtool_op_get_sg
,
7863 .set_sg
= ethtool_op_set_sg
,
7864 #if TG3_TSO_SUPPORT != 0
7865 .get_tso
= ethtool_op_get_tso
,
7866 .set_tso
= tg3_set_tso
,
7868 .self_test_count
= tg3_get_test_count
,
7869 .self_test
= tg3_self_test
,
7870 .get_strings
= tg3_get_strings
,
7871 .get_stats_count
= tg3_get_stats_count
,
7872 .get_ethtool_stats
= tg3_get_ethtool_stats
,
7873 .get_coalesce
= tg3_get_coalesce
,
7876 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
7880 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
7882 if (tg3_nvram_read(tp
, 0, &val
) != 0)
7885 if (swab32(val
) != TG3_EEPROM_MAGIC
)
7889 * Size the chip by reading offsets at increasing powers of two.
7890 * When we encounter our validation signature, we know the addressing
7891 * has wrapped around, and thus have our chip size.
7895 while (cursize
< tp
->nvram_size
) {
7896 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
7899 if (swab32(val
) == TG3_EEPROM_MAGIC
)
7905 tp
->nvram_size
= cursize
;
7908 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
7912 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
7914 tp
->nvram_size
= (val
>> 16) * 1024;
7918 tp
->nvram_size
= 0x20000;
7921 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
7925 nvcfg1
= tr32(NVRAM_CFG1
);
7926 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
7927 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
7930 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
7931 tw32(NVRAM_CFG1
, nvcfg1
);
7934 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
7935 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
7936 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
7937 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7938 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
7939 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7941 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
7942 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7943 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
7945 case FLASH_VENDOR_ATMEL_EEPROM
:
7946 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7947 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
7948 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7950 case FLASH_VENDOR_ST
:
7951 tp
->nvram_jedecnum
= JEDEC_ST
;
7952 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
7953 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7955 case FLASH_VENDOR_SAIFUN
:
7956 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
7957 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
7959 case FLASH_VENDOR_SST_SMALL
:
7960 case FLASH_VENDOR_SST_LARGE
:
7961 tp
->nvram_jedecnum
= JEDEC_SST
;
7962 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
7967 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7968 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
7969 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7973 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
7977 nvcfg1
= tr32(NVRAM_CFG1
);
7979 /* NVRAM protection for TPM */
7980 if (nvcfg1
& (1 << 27))
7981 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
7983 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
7984 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
7985 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
7986 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7987 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7989 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
7990 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7991 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7992 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
7994 case FLASH_5752VENDOR_ST_M45PE10
:
7995 case FLASH_5752VENDOR_ST_M45PE20
:
7996 case FLASH_5752VENDOR_ST_M45PE40
:
7997 tp
->nvram_jedecnum
= JEDEC_ST
;
7998 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7999 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
8003 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
8004 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
8005 case FLASH_5752PAGE_SIZE_256
:
8006 tp
->nvram_pagesize
= 256;
8008 case FLASH_5752PAGE_SIZE_512
:
8009 tp
->nvram_pagesize
= 512;
8011 case FLASH_5752PAGE_SIZE_1K
:
8012 tp
->nvram_pagesize
= 1024;
8014 case FLASH_5752PAGE_SIZE_2K
:
8015 tp
->nvram_pagesize
= 2048;
8017 case FLASH_5752PAGE_SIZE_4K
:
8018 tp
->nvram_pagesize
= 4096;
8020 case FLASH_5752PAGE_SIZE_264
:
8021 tp
->nvram_pagesize
= 264;
8026 /* For eeprom, set pagesize to maximum eeprom size */
8027 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
8029 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
8030 tw32(NVRAM_CFG1
, nvcfg1
);
8034 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
8035 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
8039 if (tp
->tg3_flags2
& TG3_FLG2_SUN_570X
)
8042 tw32_f(GRC_EEPROM_ADDR
,
8043 (EEPROM_ADDR_FSM_RESET
|
8044 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
8045 EEPROM_ADDR_CLKPERD_SHIFT
)));
8047 /* XXX schedule_timeout() ... */
8048 for (j
= 0; j
< 100; j
++)
8051 /* Enable seeprom accesses. */
8052 tw32_f(GRC_LOCAL_CTRL
,
8053 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
8056 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
8057 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
8058 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
8060 tg3_enable_nvram_access(tp
);
8062 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8063 tg3_get_5752_nvram_info(tp
);
8065 tg3_get_nvram_info(tp
);
8067 tg3_get_nvram_size(tp
);
8069 tg3_disable_nvram_access(tp
);
8072 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
8074 tg3_get_eeprom_size(tp
);
8078 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
8079 u32 offset
, u32
*val
)
8084 if (offset
> EEPROM_ADDR_ADDR_MASK
||
8088 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
8089 EEPROM_ADDR_DEVID_MASK
|
8091 tw32(GRC_EEPROM_ADDR
,
8093 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
8094 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
8095 EEPROM_ADDR_ADDR_MASK
) |
8096 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
8098 for (i
= 0; i
< 10000; i
++) {
8099 tmp
= tr32(GRC_EEPROM_ADDR
);
8101 if (tmp
& EEPROM_ADDR_COMPLETE
)
8105 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
8108 *val
= tr32(GRC_EEPROM_DATA
);
8112 #define NVRAM_CMD_TIMEOUT 10000
8114 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
8118 tw32(NVRAM_CMD
, nvram_cmd
);
8119 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
8121 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
8126 if (i
== NVRAM_CMD_TIMEOUT
) {
8132 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
8136 if (tp
->tg3_flags2
& TG3_FLG2_SUN_570X
) {
8137 printk(KERN_ERR PFX
"Attempt to do nvram_read on Sun 570X\n");
8141 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
8142 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
8144 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
8145 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
8146 (tp
->nvram_jedecnum
== JEDEC_ATMEL
)) {
8148 offset
= ((offset
/ tp
->nvram_pagesize
) <<
8149 ATMEL_AT45DB0X1B_PAGE_POS
) +
8150 (offset
% tp
->nvram_pagesize
);
8153 if (offset
> NVRAM_ADDR_MSK
)
8158 tg3_enable_nvram_access(tp
);
8160 tw32(NVRAM_ADDR
, offset
);
8161 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
8162 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
8165 *val
= swab32(tr32(NVRAM_RDDATA
));
8167 tg3_nvram_unlock(tp
);
8169 tg3_disable_nvram_access(tp
);
8174 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
8175 u32 offset
, u32 len
, u8
*buf
)
8180 for (i
= 0; i
< len
; i
+= 4) {
8185 memcpy(&data
, buf
+ i
, 4);
8187 tw32(GRC_EEPROM_DATA
, cpu_to_le32(data
));
8189 val
= tr32(GRC_EEPROM_ADDR
);
8190 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
8192 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
8194 tw32(GRC_EEPROM_ADDR
, val
|
8195 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
8196 (addr
& EEPROM_ADDR_ADDR_MASK
) |
8200 for (j
= 0; j
< 10000; j
++) {
8201 val
= tr32(GRC_EEPROM_ADDR
);
8203 if (val
& EEPROM_ADDR_COMPLETE
)
8207 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
8216 /* offset and length are dword aligned */
8217 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
8221 u32 pagesize
= tp
->nvram_pagesize
;
8222 u32 pagemask
= pagesize
- 1;
8226 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
8232 u32 phy_addr
, page_off
, size
;
8234 phy_addr
= offset
& ~pagemask
;
8236 for (j
= 0; j
< pagesize
; j
+= 4) {
8237 if ((ret
= tg3_nvram_read(tp
, phy_addr
+ j
,
8238 (u32
*) (tmp
+ j
))))
8244 page_off
= offset
& pagemask
;
8251 memcpy(tmp
+ page_off
, buf
, size
);
8253 offset
= offset
+ (pagesize
- page_off
);
8255 tg3_enable_nvram_access(tp
);
8258 * Before we can erase the flash page, we need
8259 * to issue a special "write enable" command.
8261 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
8263 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
8266 /* Erase the target page */
8267 tw32(NVRAM_ADDR
, phy_addr
);
8269 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
8270 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
8272 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
8275 /* Issue another write enable to start the write. */
8276 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
8278 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
8281 for (j
= 0; j
< pagesize
; j
+= 4) {
8284 data
= *((u32
*) (tmp
+ j
));
8285 tw32(NVRAM_WRDATA
, cpu_to_be32(data
));
8287 tw32(NVRAM_ADDR
, phy_addr
+ j
);
8289 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
8293 nvram_cmd
|= NVRAM_CMD_FIRST
;
8294 else if (j
== (pagesize
- 4))
8295 nvram_cmd
|= NVRAM_CMD_LAST
;
8297 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
8304 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
8305 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
8312 /* offset and length are dword aligned */
8313 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
8318 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
8319 u32 data
, page_off
, phy_addr
, nvram_cmd
;
8321 memcpy(&data
, buf
+ i
, 4);
8322 tw32(NVRAM_WRDATA
, cpu_to_be32(data
));
8324 page_off
= offset
% tp
->nvram_pagesize
;
8326 if ((tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
8327 (tp
->nvram_jedecnum
== JEDEC_ATMEL
)) {
8329 phy_addr
= ((offset
/ tp
->nvram_pagesize
) <<
8330 ATMEL_AT45DB0X1B_PAGE_POS
) + page_off
;
8336 tw32(NVRAM_ADDR
, phy_addr
);
8338 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
8340 if ((page_off
== 0) || (i
== 0))
8341 nvram_cmd
|= NVRAM_CMD_FIRST
;
8342 else if (page_off
== (tp
->nvram_pagesize
- 4))
8343 nvram_cmd
|= NVRAM_CMD_LAST
;
8346 nvram_cmd
|= NVRAM_CMD_LAST
;
8348 if ((tp
->nvram_jedecnum
== JEDEC_ST
) &&
8349 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
8351 if ((ret
= tg3_nvram_exec_cmd(tp
,
8352 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
8357 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
8358 /* We always do complete word writes to eeprom. */
8359 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
8362 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
8368 /* offset and length are dword aligned */
8369 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
8373 if (tp
->tg3_flags2
& TG3_FLG2_SUN_570X
) {
8374 printk(KERN_ERR PFX
"Attempt to do nvram_write on Sun 570X\n");
8378 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
8379 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
8380 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
8384 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
8385 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
8392 tg3_enable_nvram_access(tp
);
8393 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
8394 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
))
8395 tw32(NVRAM_WRITE1
, 0x406);
8397 grc_mode
= tr32(GRC_MODE
);
8398 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
8400 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
8401 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
8403 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
8407 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
8411 grc_mode
= tr32(GRC_MODE
);
8412 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
8414 tg3_disable_nvram_access(tp
);
8415 tg3_nvram_unlock(tp
);
8418 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
8419 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8426 struct subsys_tbl_ent
{
8427 u16 subsys_vendor
, subsys_devid
;
8431 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
8432 /* Broadcom boards. */
8433 { PCI_VENDOR_ID_BROADCOM
, 0x1644, PHY_ID_BCM5401
}, /* BCM95700A6 */
8434 { PCI_VENDOR_ID_BROADCOM
, 0x0001, PHY_ID_BCM5701
}, /* BCM95701A5 */
8435 { PCI_VENDOR_ID_BROADCOM
, 0x0002, PHY_ID_BCM8002
}, /* BCM95700T6 */
8436 { PCI_VENDOR_ID_BROADCOM
, 0x0003, 0 }, /* BCM95700A9 */
8437 { PCI_VENDOR_ID_BROADCOM
, 0x0005, PHY_ID_BCM5701
}, /* BCM95701T1 */
8438 { PCI_VENDOR_ID_BROADCOM
, 0x0006, PHY_ID_BCM5701
}, /* BCM95701T8 */
8439 { PCI_VENDOR_ID_BROADCOM
, 0x0007, 0 }, /* BCM95701A7 */
8440 { PCI_VENDOR_ID_BROADCOM
, 0x0008, PHY_ID_BCM5701
}, /* BCM95701A10 */
8441 { PCI_VENDOR_ID_BROADCOM
, 0x8008, PHY_ID_BCM5701
}, /* BCM95701A12 */
8442 { PCI_VENDOR_ID_BROADCOM
, 0x0009, PHY_ID_BCM5703
}, /* BCM95703Ax1 */
8443 { PCI_VENDOR_ID_BROADCOM
, 0x8009, PHY_ID_BCM5703
}, /* BCM95703Ax2 */
8446 { PCI_VENDOR_ID_3COM
, 0x1000, PHY_ID_BCM5401
}, /* 3C996T */
8447 { PCI_VENDOR_ID_3COM
, 0x1006, PHY_ID_BCM5701
}, /* 3C996BT */
8448 { PCI_VENDOR_ID_3COM
, 0x1004, 0 }, /* 3C996SX */
8449 { PCI_VENDOR_ID_3COM
, 0x1007, PHY_ID_BCM5701
}, /* 3C1000T */
8450 { PCI_VENDOR_ID_3COM
, 0x1008, PHY_ID_BCM5701
}, /* 3C940BR01 */
8453 { PCI_VENDOR_ID_DELL
, 0x00d1, PHY_ID_BCM5401
}, /* VIPER */
8454 { PCI_VENDOR_ID_DELL
, 0x0106, PHY_ID_BCM5401
}, /* JAGUAR */
8455 { PCI_VENDOR_ID_DELL
, 0x0109, PHY_ID_BCM5411
}, /* MERLOT */
8456 { PCI_VENDOR_ID_DELL
, 0x010a, PHY_ID_BCM5411
}, /* SLIM_MERLOT */
8458 /* Compaq boards. */
8459 { PCI_VENDOR_ID_COMPAQ
, 0x007c, PHY_ID_BCM5701
}, /* BANSHEE */
8460 { PCI_VENDOR_ID_COMPAQ
, 0x009a, PHY_ID_BCM5701
}, /* BANSHEE_2 */
8461 { PCI_VENDOR_ID_COMPAQ
, 0x007d, 0 }, /* CHANGELING */
8462 { PCI_VENDOR_ID_COMPAQ
, 0x0085, PHY_ID_BCM5701
}, /* NC7780 */
8463 { PCI_VENDOR_ID_COMPAQ
, 0x0099, PHY_ID_BCM5701
}, /* NC7780_2 */
8466 { PCI_VENDOR_ID_IBM
, 0x0281, 0 } /* IBM??? */
8469 static inline struct subsys_tbl_ent
*lookup_by_subsys(struct tg3
*tp
)
8473 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
8474 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
8475 tp
->pdev
->subsystem_vendor
) &&
8476 (subsys_id_to_phy_id
[i
].subsys_devid
==
8477 tp
->pdev
->subsystem_device
))
8478 return &subsys_id_to_phy_id
[i
];
8483 /* Since this function may be called in D3-hot power state during
8484 * tg3_init_one(), only config cycles are allowed.
8486 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
8490 /* Make sure register accesses (indirect or otherwise)
8491 * will function correctly.
8493 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
8494 tp
->misc_host_ctrl
);
8496 tp
->phy_id
= PHY_ID_INVALID
;
8497 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
8499 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
8500 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
8501 u32 nic_cfg
, led_cfg
;
8502 u32 nic_phy_id
, ver
, cfg2
= 0, eeprom_phy_id
;
8503 int eeprom_phy_serdes
= 0;
8505 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
8506 tp
->nic_sram_data_cfg
= nic_cfg
;
8508 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
8509 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
8510 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
8511 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
8512 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
8513 (ver
> 0) && (ver
< 0x100))
8514 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
8516 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
8517 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
8518 eeprom_phy_serdes
= 1;
8520 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
8521 if (nic_phy_id
!= 0) {
8522 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
8523 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
8525 eeprom_phy_id
= (id1
>> 16) << 10;
8526 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
8527 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
8531 tp
->phy_id
= eeprom_phy_id
;
8532 if (eeprom_phy_serdes
)
8533 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
8535 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
8536 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
8537 SHASTA_EXT_LED_MODE_MASK
);
8539 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
8543 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
8544 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
8547 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
8548 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
8551 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
8552 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
8555 case SHASTA_EXT_LED_SHARED
:
8556 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
8557 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
8558 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
8559 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
8560 LED_CTRL_MODE_PHY_2
);
8563 case SHASTA_EXT_LED_MAC
:
8564 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
8567 case SHASTA_EXT_LED_COMBO
:
8568 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
8569 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
8570 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
8571 LED_CTRL_MODE_PHY_2
);
8576 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8577 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
8578 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
8579 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
8581 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
8582 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
8583 (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
))
8584 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
8586 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
8587 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
8588 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
8589 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
8591 if (nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
)
8592 tp
->tg3_flags
|= TG3_FLAG_SERDES_WOL_CAP
;
8594 if (cfg2
& (1 << 17))
8595 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
8597 /* serdes signal pre-emphasis in register 0x590 set by */
8598 /* bootcode if bit 18 is set */
8599 if (cfg2
& (1 << 18))
8600 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
8604 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
8606 u32 hw_phy_id_1
, hw_phy_id_2
;
8607 u32 hw_phy_id
, hw_phy_id_masked
;
8610 /* Reading the PHY ID register can conflict with ASF
8611 * firwmare access to the PHY hardware.
8614 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
8615 hw_phy_id
= hw_phy_id_masked
= PHY_ID_INVALID
;
8617 /* Now read the physical PHY_ID from the chip and verify
8618 * that it is sane. If it doesn't look good, we fall back
8619 * to either the hard-coded table based PHY_ID and failing
8620 * that the value found in the eeprom area.
8622 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
8623 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
8625 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
8626 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
8627 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
8629 hw_phy_id_masked
= hw_phy_id
& PHY_ID_MASK
;
8632 if (!err
&& KNOWN_PHY_ID(hw_phy_id_masked
)) {
8633 tp
->phy_id
= hw_phy_id
;
8634 if (hw_phy_id_masked
== PHY_ID_BCM8002
)
8635 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
8637 if (tp
->phy_id
!= PHY_ID_INVALID
) {
8638 /* Do nothing, phy ID already set up in
8639 * tg3_get_eeprom_hw_cfg().
8642 struct subsys_tbl_ent
*p
;
8644 /* No eeprom signature? Try the hardcoded
8645 * subsys device table.
8647 p
= lookup_by_subsys(tp
);
8651 tp
->phy_id
= p
->phy_id
;
8653 tp
->phy_id
== PHY_ID_BCM8002
)
8654 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
8658 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8659 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
8660 u32 bmsr
, adv_reg
, tg3_ctrl
;
8662 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
8663 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
8664 (bmsr
& BMSR_LSTATUS
))
8665 goto skip_phy_reset
;
8667 err
= tg3_phy_reset(tp
);
8671 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
8672 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
8673 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
8675 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
8676 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
8677 MII_TG3_CTRL_ADV_1000_FULL
);
8678 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
8679 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
8680 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
8681 MII_TG3_CTRL_ENABLE_AS_MASTER
);
8684 if (!tg3_copper_is_advertising_all(tp
)) {
8685 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
8687 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
8688 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
8690 tg3_writephy(tp
, MII_BMCR
,
8691 BMCR_ANENABLE
| BMCR_ANRESTART
);
8693 tg3_phy_set_wirespeed(tp
);
8695 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
8696 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
8697 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
8701 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
8702 err
= tg3_init_5401phy_dsp(tp
);
8707 if (!err
&& ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)) {
8708 err
= tg3_init_5401phy_dsp(tp
);
8711 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
8712 tp
->link_config
.advertising
=
8713 (ADVERTISED_1000baseT_Half
|
8714 ADVERTISED_1000baseT_Full
|
8715 ADVERTISED_Autoneg
|
8717 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
8718 tp
->link_config
.advertising
&=
8719 ~(ADVERTISED_1000baseT_Half
|
8720 ADVERTISED_1000baseT_Full
);
8725 static void __devinit
tg3_read_partno(struct tg3
*tp
)
8727 unsigned char vpd_data
[256];
8730 if (tp
->tg3_flags2
& TG3_FLG2_SUN_570X
) {
8731 /* Sun decided not to put the necessary bits in the
8732 * NVRAM of their onboard tg3 parts :(
8734 strcpy(tp
->board_part_number
, "Sun 570X");
8738 for (i
= 0; i
< 256; i
+= 4) {
8741 if (tg3_nvram_read(tp
, 0x100 + i
, &tmp
))
8744 vpd_data
[i
+ 0] = ((tmp
>> 0) & 0xff);
8745 vpd_data
[i
+ 1] = ((tmp
>> 8) & 0xff);
8746 vpd_data
[i
+ 2] = ((tmp
>> 16) & 0xff);
8747 vpd_data
[i
+ 3] = ((tmp
>> 24) & 0xff);
8750 /* Now parse and find the part number. */
8751 for (i
= 0; i
< 256; ) {
8752 unsigned char val
= vpd_data
[i
];
8755 if (val
== 0x82 || val
== 0x91) {
8758 (vpd_data
[i
+ 2] << 8)));
8765 block_end
= (i
+ 3 +
8767 (vpd_data
[i
+ 2] << 8)));
8769 while (i
< block_end
) {
8770 if (vpd_data
[i
+ 0] == 'P' &&
8771 vpd_data
[i
+ 1] == 'N') {
8772 int partno_len
= vpd_data
[i
+ 2];
8774 if (partno_len
> 24)
8777 memcpy(tp
->board_part_number
,
8786 /* Part number not found. */
8791 strcpy(tp
->board_part_number
, "none");
8794 #ifdef CONFIG_SPARC64
8795 static int __devinit
tg3_is_sun_570X(struct tg3
*tp
)
8797 struct pci_dev
*pdev
= tp
->pdev
;
8798 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
8801 int node
= pcp
->prom_node
;
8805 err
= prom_getproperty(node
, "subsystem-vendor-id",
8806 (char *) &venid
, sizeof(venid
));
8807 if (err
== 0 || err
== -1)
8809 if (venid
== PCI_VENDOR_ID_SUN
)
8816 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
8818 static struct pci_device_id write_reorder_chipsets
[] = {
8819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
8820 PCI_DEVICE_ID_INTEL_82801AA_8
) },
8821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
8822 PCI_DEVICE_ID_INTEL_82801AB_8
) },
8823 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
8824 PCI_DEVICE_ID_INTEL_82801BA_11
) },
8825 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
8826 PCI_DEVICE_ID_INTEL_82801BA_6
) },
8827 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
8828 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
8832 u32 cacheline_sz_reg
;
8833 u32 pci_state_reg
, grc_misc_cfg
;
8838 #ifdef CONFIG_SPARC64
8839 if (tg3_is_sun_570X(tp
))
8840 tp
->tg3_flags2
|= TG3_FLG2_SUN_570X
;
8843 /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8844 * reordering to the mailbox registers done by the host
8845 * controller can cause major troubles. We read back from
8846 * every mailbox register write to force the writes to be
8847 * posted to the chip in order.
8849 if (pci_dev_present(write_reorder_chipsets
))
8850 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
8852 /* Force memory write invalidate off. If we leave it on,
8853 * then on 5700_BX chips we have to enable a workaround.
8854 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8855 * to match the cacheline size. The Broadcom driver have this
8856 * workaround but turns MWI off all the times so never uses
8857 * it. This seems to suggest that the workaround is insufficient.
8859 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8860 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
8861 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8863 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8864 * has the register indirect write enable bit set before
8865 * we try to access any of the MMIO registers. It is also
8866 * critical that the PCI-X hw workaround situation is decided
8867 * before that as well.
8869 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
8872 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
8873 MISC_HOST_CTRL_CHIPREV_SHIFT
);
8875 /* Wrong chip ID in 5752 A0. This code can be removed later
8876 * as A0 is not in production.
8878 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
8879 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
8881 /* Initialize misc host control in PCI block. */
8882 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
8883 MISC_HOST_CTRL_CHIPREV
);
8884 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
8885 tp
->misc_host_ctrl
);
8887 pci_read_config_dword(tp
->pdev
, TG3PCI_CACHELINESZ
,
8890 tp
->pci_cacheline_sz
= (cacheline_sz_reg
>> 0) & 0xff;
8891 tp
->pci_lat_timer
= (cacheline_sz_reg
>> 8) & 0xff;
8892 tp
->pci_hdr_type
= (cacheline_sz_reg
>> 16) & 0xff;
8893 tp
->pci_bist
= (cacheline_sz_reg
>> 24) & 0xff;
8895 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
8896 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8897 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
8899 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
8900 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
8901 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
8903 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
8904 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO
;
8906 if (pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
) != 0)
8907 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
8909 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
8910 tp
->pci_lat_timer
< 64) {
8911 tp
->pci_lat_timer
= 64;
8913 cacheline_sz_reg
= ((tp
->pci_cacheline_sz
& 0xff) << 0);
8914 cacheline_sz_reg
|= ((tp
->pci_lat_timer
& 0xff) << 8);
8915 cacheline_sz_reg
|= ((tp
->pci_hdr_type
& 0xff) << 16);
8916 cacheline_sz_reg
|= ((tp
->pci_bist
& 0xff) << 24);
8918 pci_write_config_dword(tp
->pdev
, TG3PCI_CACHELINESZ
,
8922 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
8925 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0) {
8926 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
8928 /* If this is a 5700 BX chipset, and we are in PCI-X
8929 * mode, enable register write workaround.
8931 * The workaround is to use indirect register accesses
8932 * for all chip writes not to mailbox registers.
8934 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
8938 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
8940 /* The chip can have it's power management PCI config
8941 * space registers clobbered due to this bug.
8942 * So explicitly force the chip into D0 here.
8944 pci_read_config_dword(tp
->pdev
, TG3PCI_PM_CTRL_STAT
,
8946 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
8947 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
8948 pci_write_config_dword(tp
->pdev
, TG3PCI_PM_CTRL_STAT
,
8951 /* Also, force SERR#/PERR# in PCI command. */
8952 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8953 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
8954 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8958 /* Back to back register writes can cause problems on this chip,
8959 * the workaround is to read back all reg writes except those to
8960 * mailbox regs. See tg3_write_indirect_reg32().
8962 * PCI Express 5750_A0 rev chips need this workaround too.
8964 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
8965 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
8966 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
))
8967 tp
->tg3_flags
|= TG3_FLAG_5701_REG_WRITE_BUG
;
8969 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
8970 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
8971 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
8972 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
8974 /* Chip-specific fixup from Broadcom driver */
8975 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
8976 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
8977 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
8978 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
8981 /* Get eeprom hw config before calling tg3_set_power_state().
8982 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8983 * determined before calling tg3_set_power_state() so that
8984 * we know whether or not to switch out of Vaux power.
8985 * When the flag is set, it means that GPIO1 is used for eeprom
8986 * write protect and also implies that it is a LOM where GPIOs
8987 * are not used to switch power.
8989 tg3_get_eeprom_hw_cfg(tp
);
8991 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8992 * GPIO1 driven high will bring 5700's external PHY out of reset.
8993 * It is also used as eeprom write protect on LOMs.
8995 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
8996 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
8997 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
8998 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8999 GRC_LCLCTRL_GPIO_OUTPUT1
);
9000 /* Unused GPIO3 must be driven as output on 5752 because there
9001 * are no pull-up resistors on unused GPIO pins.
9003 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
9004 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
9006 /* Force the chip into D0. */
9007 err
= tg3_set_power_state(tp
, 0);
9009 printk(KERN_ERR PFX
"(%s) transition to D0 failed\n",
9010 pci_name(tp
->pdev
));
9014 /* 5700 B0 chips do not support checksumming correctly due
9017 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
9018 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
9020 /* Pseudo-header checksum is done by hardware logic and not
9021 * the offload processers, so make the chip do the pseudo-
9022 * header checksums on receive. For transmit it is more
9023 * convenient to do the pseudo-header checksum in software
9024 * as Linux does that on transmit for us in all cases.
9026 tp
->tg3_flags
|= TG3_FLAG_NO_TX_PSEUDO_CSUM
;
9027 tp
->tg3_flags
&= ~TG3_FLAG_NO_RX_PSEUDO_CSUM
;
9029 /* Derive initial jumbo mode from MTU assigned in
9030 * ether_setup() via the alloc_etherdev() call
9032 if (tp
->dev
->mtu
> ETH_DATA_LEN
)
9033 tp
->tg3_flags
|= TG3_FLAG_JUMBO_ENABLE
;
9035 /* Determine WakeOnLan speed to use. */
9036 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9037 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
9038 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
9039 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
9040 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
9042 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
9045 /* A few boards don't want Ethernet@WireSpeed phy feature */
9046 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
9047 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
9048 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
9049 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)))
9050 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
9052 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
9053 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
9054 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
9055 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
9056 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
9058 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
9059 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
9061 tp
->coalesce_mode
= 0;
9062 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
9063 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
9064 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
9066 /* Initialize MAC MI mode, polling disabled. */
9067 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
9070 /* Initialize data/descriptor byte/word swapping. */
9071 val
= tr32(GRC_MODE
);
9072 val
&= GRC_MODE_HOST_STACKUP
;
9073 tw32(GRC_MODE
, val
| tp
->grc_mode
);
9075 tg3_switch_clocks(tp
);
9077 /* Clear this out for sanity. */
9078 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
9080 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
9082 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
9083 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
9084 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
9086 if (chiprevid
== CHIPREV_ID_5701_A0
||
9087 chiprevid
== CHIPREV_ID_5701_B0
||
9088 chiprevid
== CHIPREV_ID_5701_B2
||
9089 chiprevid
== CHIPREV_ID_5701_B5
) {
9090 void __iomem
*sram_base
;
9092 /* Write some dummy words into the SRAM status block
9093 * area, see if it reads back correctly. If the return
9094 * value is bad, force enable the PCIX workaround.
9096 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
9098 writel(0x00000000, sram_base
);
9099 writel(0x00000000, sram_base
+ 4);
9100 writel(0xffffffff, sram_base
+ 4);
9101 if (readl(sram_base
) != 0x00000000)
9102 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
9109 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
9110 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
9112 /* Broadcom's driver says that CIOBE multisplit has a bug */
9114 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
9115 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5704CIOBE
) {
9116 tp
->tg3_flags
|= TG3_FLAG_SPLIT_MODE
;
9117 tp
->split_mode_max_reqs
= SPLIT_MODE_5704_MAX_REQ
;
9120 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
9121 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
9122 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
9123 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
9125 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
9126 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
9127 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
9128 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
9129 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
9130 HOSTCC_MODE_CLRTICK_TXBD
);
9132 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
9133 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
9134 tp
->misc_host_ctrl
);
9137 /* these are limited to 10/100 only */
9138 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
9139 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
9140 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
9141 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
9142 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
9143 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
9144 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
9145 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
9146 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
9147 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
)))
9148 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
9150 err
= tg3_phy_probe(tp
);
9152 printk(KERN_ERR PFX
"(%s) phy probe failed, err %d\n",
9153 pci_name(tp
->pdev
), err
);
9154 /* ... but do not return immediately ... */
9157 tg3_read_partno(tp
);
9159 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
9160 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
9162 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
9163 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
9165 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
9168 /* 5700 {AX,BX} chips have a broken status block link
9169 * change bit implementation, so we must use the
9170 * status register in those cases.
9172 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
9173 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
9175 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
9177 /* The led_ctrl is set during tg3_phy_probe, here we might
9178 * have to force the link status polling mechanism based
9179 * upon subsystem IDs.
9181 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
9182 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
9183 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
9184 TG3_FLAG_USE_LINKCHG_REG
);
9187 /* For all SERDES we poll the MAC status register. */
9188 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
9189 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
9191 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
9193 /* 5700 BX chips need to have their TX producer index mailboxes
9194 * written twice to workaround a bug.
9196 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
)
9197 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
9199 tp
->tg3_flags
&= ~TG3_FLAG_TXD_MBOX_HWBUG
;
9201 /* It seems all chips can get confused if TX buffers
9202 * straddle the 4GB address boundary in some cases.
9204 tp
->dev
->hard_start_xmit
= tg3_start_xmit
;
9207 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
9208 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0)
9211 /* By default, disable wake-on-lan. User can change this
9212 * using ETHTOOL_SWOL.
9214 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9219 #ifdef CONFIG_SPARC64
9220 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
9222 struct net_device
*dev
= tp
->dev
;
9223 struct pci_dev
*pdev
= tp
->pdev
;
9224 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
9227 int node
= pcp
->prom_node
;
9229 if (prom_getproplen(node
, "local-mac-address") == 6) {
9230 prom_getproperty(node
, "local-mac-address",
9238 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
9240 struct net_device
*dev
= tp
->dev
;
9242 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
9247 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
9249 struct net_device
*dev
= tp
->dev
;
9250 u32 hi
, lo
, mac_offset
;
9252 #ifdef CONFIG_SPARC64
9253 if (!tg3_get_macaddr_sparc(tp
))
9258 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
9259 !(tp
->tg3_flags
& TG3_FLG2_SUN_570X
)) {
9260 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
9262 if (tg3_nvram_lock(tp
))
9263 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
9265 tg3_nvram_unlock(tp
);
9268 /* First try to get it from MAC address mailbox. */
9269 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
9270 if ((hi
>> 16) == 0x484b) {
9271 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
9272 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
9274 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
9275 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
9276 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
9277 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
9278 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
9280 /* Next, try NVRAM. */
9281 else if (!(tp
->tg3_flags
& TG3_FLG2_SUN_570X
) &&
9282 !tg3_nvram_read(tp
, mac_offset
+ 0, &hi
) &&
9283 !tg3_nvram_read(tp
, mac_offset
+ 4, &lo
)) {
9284 dev
->dev_addr
[0] = ((hi
>> 16) & 0xff);
9285 dev
->dev_addr
[1] = ((hi
>> 24) & 0xff);
9286 dev
->dev_addr
[2] = ((lo
>> 0) & 0xff);
9287 dev
->dev_addr
[3] = ((lo
>> 8) & 0xff);
9288 dev
->dev_addr
[4] = ((lo
>> 16) & 0xff);
9289 dev
->dev_addr
[5] = ((lo
>> 24) & 0xff);
9291 /* Finally just fetch it out of the MAC control regs. */
9293 hi
= tr32(MAC_ADDR_0_HIGH
);
9294 lo
= tr32(MAC_ADDR_0_LOW
);
9296 dev
->dev_addr
[5] = lo
& 0xff;
9297 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
9298 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
9299 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
9300 dev
->dev_addr
[1] = hi
& 0xff;
9301 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
9304 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
9305 #ifdef CONFIG_SPARC64
9306 if (!tg3_get_default_macaddr_sparc(tp
))
9314 #define BOUNDARY_SINGLE_CACHELINE 1
9315 #define BOUNDARY_MULTI_CACHELINE 2
9317 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
9323 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
9325 cacheline_size
= 1024;
9327 cacheline_size
= (int) byte
* 4;
9329 /* On 5703 and later chips, the boundary bits have no
9332 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
9333 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
9334 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
9337 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9338 goal
= BOUNDARY_MULTI_CACHELINE
;
9340 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9341 goal
= BOUNDARY_SINGLE_CACHELINE
;
9350 /* PCI controllers on most RISC systems tend to disconnect
9351 * when a device tries to burst across a cache-line boundary.
9352 * Therefore, letting tg3 do so just wastes PCI bandwidth.
9354 * Unfortunately, for PCI-E there are only limited
9355 * write-side controls for this, and thus for reads
9356 * we will still get the disconnects. We'll also waste
9357 * these PCI cycles for both read and write for chips
9358 * other than 5700 and 5701 which do not implement the
9361 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
9362 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
9363 switch (cacheline_size
) {
9368 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
9369 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
9370 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
9372 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
9373 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
9378 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
9379 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
9383 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
9384 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
9387 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
9388 switch (cacheline_size
) {
9392 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
9393 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
9394 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
9400 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
9401 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
9405 switch (cacheline_size
) {
9407 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
9408 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
9409 DMA_RWCTRL_WRITE_BNDRY_16
);
9414 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
9415 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
9416 DMA_RWCTRL_WRITE_BNDRY_32
);
9421 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
9422 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
9423 DMA_RWCTRL_WRITE_BNDRY_64
);
9428 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
9429 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
9430 DMA_RWCTRL_WRITE_BNDRY_128
);
9435 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
9436 DMA_RWCTRL_WRITE_BNDRY_256
);
9439 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
9440 DMA_RWCTRL_WRITE_BNDRY_512
);
9444 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
9445 DMA_RWCTRL_WRITE_BNDRY_1024
);
9454 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
9456 struct tg3_internal_buffer_desc test_desc
;
9460 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
9462 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
9463 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
9464 tw32(RDMAC_STATUS
, 0);
9465 tw32(WDMAC_STATUS
, 0);
9467 tw32(BUFMGR_MODE
, 0);
9470 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
9471 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
9472 test_desc
.nic_mbuf
= 0x00002100;
9473 test_desc
.len
= size
;
9476 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
9477 * the *second* time the tg3 driver was getting loaded after an
9480 * Broadcom tells me:
9481 * ...the DMA engine is connected to the GRC block and a DMA
9482 * reset may affect the GRC block in some unpredictable way...
9483 * The behavior of resets to individual blocks has not been tested.
9485 * Broadcom noted the GRC reset will also reset all sub-components.
9488 test_desc
.cqid_sqid
= (13 << 8) | 2;
9490 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
9493 test_desc
.cqid_sqid
= (16 << 8) | 7;
9495 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
9498 test_desc
.flags
= 0x00000005;
9500 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
9503 val
= *(((u32
*)&test_desc
) + i
);
9504 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
9505 sram_dma_descs
+ (i
* sizeof(u32
)));
9506 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
9508 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
9511 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
9513 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
9517 for (i
= 0; i
< 40; i
++) {
9521 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
9523 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
9524 if ((val
& 0xffff) == sram_dma_descs
) {
9535 #define TEST_BUFFER_SIZE 0x2000
9537 static int __devinit
tg3_test_dma(struct tg3
*tp
)
9540 u32
*buf
, saved_dma_rwctrl
;
9543 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
9549 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
9550 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
9552 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
9554 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
9555 /* DMA read watermark not used on PCIE */
9556 tp
->dma_rwctrl
|= 0x00180000;
9557 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
9558 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
9559 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
9560 tp
->dma_rwctrl
|= 0x003f0000;
9562 tp
->dma_rwctrl
|= 0x003f000f;
9564 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
9565 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
9566 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
9568 if (ccval
== 0x6 || ccval
== 0x7)
9569 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
9571 /* Set bit 23 to enable PCIX hw bug fix */
9572 tp
->dma_rwctrl
|= 0x009f0000;
9574 tp
->dma_rwctrl
|= 0x001b000f;
9578 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
9579 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
9580 tp
->dma_rwctrl
&= 0xfffffff0;
9582 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9583 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
9584 /* Remove this if it causes problems for some boards. */
9585 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
9587 /* On 5700/5701 chips, we need to set this bit.
9588 * Otherwise the chip will issue cacheline transactions
9589 * to streamable DMA memory with not all the byte
9590 * enables turned on. This is an error on several
9591 * RISC PCI controllers, in particular sparc64.
9593 * On 5703/5704 chips, this bit has been reassigned
9594 * a different meaning. In particular, it is used
9595 * on those chips to enable a PCI-X workaround.
9597 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
9600 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
9603 /* Unneeded, already done by tg3_get_invariants. */
9604 tg3_switch_clocks(tp
);
9608 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
9609 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
9612 /* It is best to perform DMA test with maximum write burst size
9613 * to expose the 5700/5701 write DMA bug.
9615 saved_dma_rwctrl
= tp
->dma_rwctrl
;
9616 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
9617 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
9622 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
9625 /* Send the buffer to the chip. */
9626 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
9628 printk(KERN_ERR
"tg3_test_dma() Write the buffer failed %d\n", ret
);
9633 /* validate data reached card RAM correctly. */
9634 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
9636 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
9637 if (le32_to_cpu(val
) != p
[i
]) {
9638 printk(KERN_ERR
" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val
, i
);
9639 /* ret = -ENODEV here? */
9644 /* Now read it back. */
9645 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
9647 printk(KERN_ERR
"tg3_test_dma() Read the buffer failed %d\n", ret
);
9653 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
9657 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
9658 DMA_RWCTRL_WRITE_BNDRY_16
) {
9659 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
9660 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
9661 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
9664 printk(KERN_ERR
"tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p
[i
], i
);
9670 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
9676 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
9677 DMA_RWCTRL_WRITE_BNDRY_16
) {
9678 /* DMA test passed without adjusting DMA boundary,
9679 * just restore the calculated DMA boundary
9681 tp
->dma_rwctrl
= saved_dma_rwctrl
;
9682 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
9686 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
9691 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
9693 tp
->link_config
.advertising
=
9694 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
9695 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
9696 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
9697 ADVERTISED_Autoneg
| ADVERTISED_MII
);
9698 tp
->link_config
.speed
= SPEED_INVALID
;
9699 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9700 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
9701 netif_carrier_off(tp
->dev
);
9702 tp
->link_config
.active_speed
= SPEED_INVALID
;
9703 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
9704 tp
->link_config
.phy_is_low_power
= 0;
9705 tp
->link_config
.orig_speed
= SPEED_INVALID
;
9706 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
9707 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
9710 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
9712 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
9713 DEFAULT_MB_RDMA_LOW_WATER
;
9714 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
9715 DEFAULT_MB_MACRX_LOW_WATER
;
9716 tp
->bufmgr_config
.mbuf_high_water
=
9717 DEFAULT_MB_HIGH_WATER
;
9719 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
9720 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
9721 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
9722 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
9723 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
9724 DEFAULT_MB_HIGH_WATER_JUMBO
;
9726 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
9727 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
9730 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
9732 switch (tp
->phy_id
& PHY_ID_MASK
) {
9733 case PHY_ID_BCM5400
: return "5400";
9734 case PHY_ID_BCM5401
: return "5401";
9735 case PHY_ID_BCM5411
: return "5411";
9736 case PHY_ID_BCM5701
: return "5701";
9737 case PHY_ID_BCM5703
: return "5703";
9738 case PHY_ID_BCM5704
: return "5704";
9739 case PHY_ID_BCM5705
: return "5705";
9740 case PHY_ID_BCM5750
: return "5750";
9741 case PHY_ID_BCM5752
: return "5752";
9742 case PHY_ID_BCM8002
: return "8002/serdes";
9743 case 0: return "serdes";
9744 default: return "unknown";
9748 static struct pci_dev
* __devinit
tg3_find_5704_peer(struct tg3
*tp
)
9750 struct pci_dev
*peer
;
9751 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
9753 for (func
= 0; func
< 8; func
++) {
9754 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
9755 if (peer
&& peer
!= tp
->pdev
)
9759 if (!peer
|| peer
== tp
->pdev
)
9763 * We don't need to keep the refcount elevated; there's no way
9764 * to remove one half of this device without removing the other
9771 static void __devinit
tg3_init_coal(struct tg3
*tp
)
9773 struct ethtool_coalesce
*ec
= &tp
->coal
;
9775 memset(ec
, 0, sizeof(*ec
));
9776 ec
->cmd
= ETHTOOL_GCOALESCE
;
9777 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
9778 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
9779 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
9780 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
9781 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
9782 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
9783 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
9784 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
9785 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
9787 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
9788 HOSTCC_MODE_CLRTICK_TXBD
)) {
9789 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
9790 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
9791 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
9792 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
9796 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
9797 const struct pci_device_id
*ent
)
9799 static int tg3_version_printed
= 0;
9800 unsigned long tg3reg_base
, tg3reg_len
;
9801 struct net_device
*dev
;
9803 int i
, err
, pci_using_dac
, pm_cap
;
9805 if (tg3_version_printed
++ == 0)
9806 printk(KERN_INFO
"%s", version
);
9808 err
= pci_enable_device(pdev
);
9810 printk(KERN_ERR PFX
"Cannot enable PCI device, "
9815 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
9816 printk(KERN_ERR PFX
"Cannot find proper PCI device "
9817 "base address, aborting.\n");
9819 goto err_out_disable_pdev
;
9822 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
9824 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
9826 goto err_out_disable_pdev
;
9829 pci_set_master(pdev
);
9831 /* Find power-management capability. */
9832 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
9834 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
9837 goto err_out_free_res
;
9840 /* Configure DMA attributes. */
9841 err
= pci_set_dma_mask(pdev
, 0xffffffffffffffffULL
);
9844 err
= pci_set_consistent_dma_mask(pdev
, 0xffffffffffffffffULL
);
9846 printk(KERN_ERR PFX
"Unable to obtain 64 bit DMA "
9847 "for consistent allocations\n");
9848 goto err_out_free_res
;
9851 err
= pci_set_dma_mask(pdev
, 0xffffffffULL
);
9853 printk(KERN_ERR PFX
"No usable DMA configuration, "
9855 goto err_out_free_res
;
9860 tg3reg_base
= pci_resource_start(pdev
, 0);
9861 tg3reg_len
= pci_resource_len(pdev
, 0);
9863 dev
= alloc_etherdev(sizeof(*tp
));
9865 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
9867 goto err_out_free_res
;
9870 SET_MODULE_OWNER(dev
);
9871 SET_NETDEV_DEV(dev
, &pdev
->dev
);
9874 dev
->features
|= NETIF_F_HIGHDMA
;
9875 dev
->features
|= NETIF_F_LLTX
;
9876 #if TG3_VLAN_TAG_USED
9877 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
9878 dev
->vlan_rx_register
= tg3_vlan_rx_register
;
9879 dev
->vlan_rx_kill_vid
= tg3_vlan_rx_kill_vid
;
9882 tp
= netdev_priv(dev
);
9885 tp
->pm_cap
= pm_cap
;
9886 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
9887 tp
->rx_mode
= TG3_DEF_RX_MODE
;
9888 tp
->tx_mode
= TG3_DEF_TX_MODE
;
9889 tp
->mi_mode
= MAC_MI_MODE_BASE
;
9891 tp
->msg_enable
= tg3_debug
;
9893 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
9895 /* The word/byte swap controls here control register access byte
9896 * swapping. DMA data byte swapping is controlled in the GRC_MODE
9899 tp
->misc_host_ctrl
=
9900 MISC_HOST_CTRL_MASK_PCI_INT
|
9901 MISC_HOST_CTRL_WORD_SWAP
|
9902 MISC_HOST_CTRL_INDIR_ACCESS
|
9903 MISC_HOST_CTRL_PCISTATE_RW
;
9905 /* The NONFRM (non-frame) byte/word swap controls take effect
9906 * on descriptor entries, anything which isn't packet data.
9908 * The StrongARM chips on the board (one for tx, one for rx)
9909 * are running in big-endian mode.
9911 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
9912 GRC_MODE_WSWAP_NONFRM_DATA
);
9914 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
9916 spin_lock_init(&tp
->lock
);
9917 spin_lock_init(&tp
->tx_lock
);
9918 spin_lock_init(&tp
->indirect_lock
);
9919 INIT_WORK(&tp
->reset_task
, tg3_reset_task
, tp
);
9921 tp
->regs
= ioremap_nocache(tg3reg_base
, tg3reg_len
);
9922 if (tp
->regs
== 0UL) {
9923 printk(KERN_ERR PFX
"Cannot map device registers, "
9926 goto err_out_free_dev
;
9929 tg3_init_link_config(tp
);
9931 tg3_init_bufmgr_config(tp
);
9933 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
9934 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
9935 tp
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
9937 dev
->open
= tg3_open
;
9938 dev
->stop
= tg3_close
;
9939 dev
->get_stats
= tg3_get_stats
;
9940 dev
->set_multicast_list
= tg3_set_rx_mode
;
9941 dev
->set_mac_address
= tg3_set_mac_addr
;
9942 dev
->do_ioctl
= tg3_ioctl
;
9943 dev
->tx_timeout
= tg3_tx_timeout
;
9944 dev
->poll
= tg3_poll
;
9945 dev
->ethtool_ops
= &tg3_ethtool_ops
;
9947 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
9948 dev
->change_mtu
= tg3_change_mtu
;
9949 dev
->irq
= pdev
->irq
;
9950 #ifdef CONFIG_NET_POLL_CONTROLLER
9951 dev
->poll_controller
= tg3_poll_controller
;
9954 err
= tg3_get_invariants(tp
);
9956 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
9958 goto err_out_iounmap
;
9961 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
9962 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
9963 DEFAULT_MB_RDMA_LOW_WATER_5705
;
9964 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
9965 DEFAULT_MB_MACRX_LOW_WATER_5705
;
9966 tp
->bufmgr_config
.mbuf_high_water
=
9967 DEFAULT_MB_HIGH_WATER_5705
;
9970 #if TG3_TSO_SUPPORT != 0
9971 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
9972 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
9974 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9975 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
9976 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
||
9977 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
9978 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
9980 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
9983 /* TSO is off by default, user can enable using ethtool. */
9985 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)
9986 dev
->features
|= NETIF_F_TSO
;
9991 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
9992 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
9993 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
9994 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
9995 tp
->rx_pending
= 63;
9998 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
9999 tp
->pdev_peer
= tg3_find_5704_peer(tp
);
10001 err
= tg3_get_device_address(tp
);
10003 printk(KERN_ERR PFX
"Could not obtain valid ethernet address, "
10005 goto err_out_iounmap
;
10009 * Reset chip in case UNDI or EFI driver did not shutdown
10010 * DMA self test will enable WDMAC and we'll see (spurious)
10011 * pending DMA on the PCI bus at that point.
10013 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
10014 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
10015 pci_save_state(tp
->pdev
);
10016 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
10017 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10020 err
= tg3_test_dma(tp
);
10022 printk(KERN_ERR PFX
"DMA engine test failed, aborting.\n");
10023 goto err_out_iounmap
;
10026 /* Tigon3 can do ipv4 only... and some chips have buggy
10029 if ((tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) == 0) {
10030 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
10031 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
10033 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
10035 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
10036 dev
->features
&= ~NETIF_F_HIGHDMA
;
10038 /* flow control autonegotiation is default behavior */
10039 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
10043 err
= register_netdev(dev
);
10045 printk(KERN_ERR PFX
"Cannot register net device, "
10047 goto err_out_iounmap
;
10050 pci_set_drvdata(pdev
, dev
);
10052 /* Now that we have fully setup the chip, save away a snapshot
10053 * of the PCI config space. We need to restore this after
10054 * GRC_MISC_CFG core clock resets and some resume events.
10056 pci_save_state(tp
->pdev
);
10058 printk(KERN_INFO
"%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
10060 tp
->board_part_number
,
10061 tp
->pci_chip_rev_id
,
10062 tg3_phy_string(tp
),
10063 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ? "X" : ""),
10064 ((tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
) ?
10065 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ? "133MHz" : "66MHz") :
10066 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ? "100MHz" : "33MHz")),
10067 ((tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
) ? "32-bit" : "64-bit"),
10068 (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100" : "10/100/1000");
10070 for (i
= 0; i
< 6; i
++)
10071 printk("%2.2x%c", dev
->dev_addr
[i
],
10072 i
== 5 ? '\n' : ':');
10074 printk(KERN_INFO
"%s: RXcsums[%d] LinkChgREG[%d] "
10075 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10078 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
10079 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
10080 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
10081 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
10082 (tp
->tg3_flags
& TG3_FLAG_SPLIT_MODE
) != 0,
10083 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0,
10084 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
10085 printk(KERN_INFO
"%s: dma_rwctrl[%08x]\n",
10086 dev
->name
, tp
->dma_rwctrl
);
10097 pci_release_regions(pdev
);
10099 err_out_disable_pdev
:
10100 pci_disable_device(pdev
);
10101 pci_set_drvdata(pdev
, NULL
);
10105 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
10107 struct net_device
*dev
= pci_get_drvdata(pdev
);
10110 struct tg3
*tp
= netdev_priv(dev
);
10112 unregister_netdev(dev
);
10115 pci_release_regions(pdev
);
10116 pci_disable_device(pdev
);
10117 pci_set_drvdata(pdev
, NULL
);
10121 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
10123 struct net_device
*dev
= pci_get_drvdata(pdev
);
10124 struct tg3
*tp
= netdev_priv(dev
);
10127 if (!netif_running(dev
))
10130 tg3_netif_stop(tp
);
10132 del_timer_sync(&tp
->timer
);
10134 spin_lock_irq(&tp
->lock
);
10135 spin_lock(&tp
->tx_lock
);
10136 tg3_disable_ints(tp
);
10137 spin_unlock(&tp
->tx_lock
);
10138 spin_unlock_irq(&tp
->lock
);
10140 netif_device_detach(dev
);
10142 spin_lock_irq(&tp
->lock
);
10143 spin_lock(&tp
->tx_lock
);
10144 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10145 spin_unlock(&tp
->tx_lock
);
10146 spin_unlock_irq(&tp
->lock
);
10148 err
= tg3_set_power_state(tp
, pci_choose_state(pdev
, state
));
10150 spin_lock_irq(&tp
->lock
);
10151 spin_lock(&tp
->tx_lock
);
10155 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
10156 add_timer(&tp
->timer
);
10158 netif_device_attach(dev
);
10159 tg3_netif_start(tp
);
10161 spin_unlock(&tp
->tx_lock
);
10162 spin_unlock_irq(&tp
->lock
);
10168 static int tg3_resume(struct pci_dev
*pdev
)
10170 struct net_device
*dev
= pci_get_drvdata(pdev
);
10171 struct tg3
*tp
= netdev_priv(dev
);
10174 if (!netif_running(dev
))
10177 pci_restore_state(tp
->pdev
);
10179 err
= tg3_set_power_state(tp
, 0);
10183 netif_device_attach(dev
);
10185 spin_lock_irq(&tp
->lock
);
10186 spin_lock(&tp
->tx_lock
);
10190 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
10191 add_timer(&tp
->timer
);
10193 tg3_enable_ints(tp
);
10195 tg3_netif_start(tp
);
10197 spin_unlock(&tp
->tx_lock
);
10198 spin_unlock_irq(&tp
->lock
);
10203 static struct pci_driver tg3_driver
= {
10204 .name
= DRV_MODULE_NAME
,
10205 .id_table
= tg3_pci_tbl
,
10206 .probe
= tg3_init_one
,
10207 .remove
= __devexit_p(tg3_remove_one
),
10208 .suspend
= tg3_suspend
,
10209 .resume
= tg3_resume
10212 static int __init
tg3_init(void)
10214 return pci_module_init(&tg3_driver
);
10217 static void __exit
tg3_cleanup(void)
10219 pci_unregister_driver(&tg3_driver
);
10222 module_init(tg3_init
);
10223 module_exit(tg3_cleanup
);