1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
4 Copyright 1994, 1995 Digital Equipment Corporation.
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
9 The author may be reached at davies@maniac.ultranet.com.
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
38 DE500 10/100 PCI Fasternet
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
50 So far the driver is known to work with the following cards:
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
99 To utilise this ability, you have to do 8 things:
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
108 insmod de4x5 io=0xghh where g = bus number
111 NB: autoprobing for modules is now supported by default. You may just
116 to load all available boards. For a specific board, still use
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
207 autosense to set the media/speed; with the following
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
244 Version Date Description
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
368 Fix type1_infoblock() bug introduced in 0.53, from
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/pci.h>
454 #include <linux/eisa.h>
455 #include <linux/delay.h>
456 #include <linux/init.h>
457 #include <linux/spinlock.h>
458 #include <linux/crc32.h>
459 #include <linux/netdevice.h>
460 #include <linux/etherdevice.h>
461 #include <linux/skbuff.h>
462 #include <linux/time.h>
463 #include <linux/types.h>
464 #include <linux/unistd.h>
465 #include <linux/ctype.h>
466 #include <linux/dma-mapping.h>
467 #include <linux/moduleparam.h>
468 #include <linux/bitops.h>
469 #include <linux/gfp.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <asm/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
482 static const char version
[] __devinitconst
=
483 KERN_INFO
"de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
485 #define c_char const char
491 int reset
; /* Hard reset required? */
492 int id
; /* IEEE OUI */
493 int ta
; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
502 int reset
; /* Hard reset required? */
503 int id
; /* IEEE OUI */
504 int ta
; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
510 int addr
; /* MII address for the PHY */
511 u_char
*gep
; /* Start of GEP sequence block in SROM */
512 u_char
*rst
; /* Start of reset sequence in SROM */
513 u_int mc
; /* Media Capabilities */
514 u_int ana
; /* NWay Advertisement */
515 u_int fdx
; /* Full DupleX capabilities for each media */
516 u_int ttm
; /* Transmit Threshold Mode for each media */
517 u_int mci
; /* 21142 MII Connector Interrupt info */
520 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
523 u_char mc
; /* Media Code */
524 u_char ext
; /* csr13-15 valid when set */
525 int csr13
; /* SIA Connectivity Register */
526 int csr14
; /* SIA TX/RX Register */
527 int csr15
; /* SIA General Register */
528 int gepc
; /* SIA GEP Control Information */
529 int gep
; /* SIA GEP Data */
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
536 static struct phy_table phy_info
[] = {
537 {0, NATIONAL_TX
, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4
, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4
, 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4
, 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
554 ** Define special SROM detection cases
556 static c_char enet_det
[][ETH_ALEN
] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
569 static c_char srom_repair_info
[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
578 static int de4x5_debug
= DE4X5_DEBUG
;
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug
= (DEBUG_MEDIA
| DEBUG_VERSION
);
585 ** Allow per adapter set up. For modules this is simply a command line
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
594 static char *args
= DE4X5_PARM
;
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
609 ** Ethernet PROM defines
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
633 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
638 static c_char
*de4x5_signatures
[] = DE4X5_SIGNATURE
;
641 ** Ethernet PROM defines for DC21040
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
666 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
672 #ifndef DEC_ONLY /* See README.de4x5 for using this */
675 static int dec_only
= 1;
679 ** DE4X5 IRQ ENABLE/DISABLE
681 #define ENABLE_IRQs { \
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
686 #define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
692 #define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
706 #define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
712 #define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
721 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
726 #define DE4X5_AUTOSENSE_MS 250
732 char sub_vendor_id
[2];
733 char sub_system_id
[2];
738 char num_controllers
;
743 #define SUB_VENDOR_ID 0x500a
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
753 #define NUM_RX_DESC 8 /* Number of RX descriptors */
754 #define NUM_TX_DESC 32 /* Number of TX descriptors */
755 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
759 volatile __le32 status
;
767 ** The DE4X5 private structure
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
774 u_int bins
[DE4X5_PKT_STAT_SZ
]; /* Private stats counters */
778 u_int excessive_collisions
;
780 u_int excessive_underruns
;
781 u_int rx_runt_frames
;
787 struct de4x5_private
{
788 char adapter_name
[80]; /* Adapter name */
789 u_long interrupt
; /* Aligned ISR flag */
790 struct de4x5_desc
*rx_ring
; /* RX descriptor ring */
791 struct de4x5_desc
*tx_ring
; /* TX descriptor ring */
792 struct sk_buff
*tx_skb
[NUM_TX_DESC
]; /* TX skb for freeing when sent */
793 struct sk_buff
*rx_skb
[NUM_RX_DESC
]; /* RX skb's */
794 int rx_new
, rx_old
; /* RX descriptor ring pointers */
795 int tx_new
, tx_old
; /* TX descriptor ring pointers */
796 char setup_frame
[SETUP_FRAME_LEN
]; /* Holds MCA and PA info. */
797 char frame
[64]; /* Min sized packet for loopback*/
798 spinlock_t lock
; /* Adapter specific spinlock */
799 struct net_device_stats stats
; /* Public stats */
800 struct pkt_stats pktStats
; /* Private stats counters */
803 int bus
; /* EISA or PCI */
804 int bus_num
; /* PCI Bus number */
805 int device
; /* Device number on PCI bus */
806 int state
; /* Adapter OPENED or CLOSED */
807 int chipset
; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask
; /* Interrupt Mask (Enable) bits */
809 s32 irq_en
; /* Summary interrupt bits */
810 int media
; /* Media (eg TP), mode (eg 100B)*/
811 int c_media
; /* Remember the last media conn */
812 bool fdx
; /* media full duplex flag */
813 int linkOK
; /* Link is OK */
814 int autosense
; /* Allow/disallow autosensing */
815 bool tx_enable
; /* Enable descriptor polling */
816 int setup_f
; /* Setup frame filtering type */
817 int local_state
; /* State within a 'media' state */
818 struct mii_phy phy
[DE4X5_MAX_PHY
]; /* List of attached PHY devices */
819 struct sia_phy sia
; /* SIA PHY Information */
820 int active
; /* Index to active PHY device */
821 int mii_cnt
; /* Number of attached PHY's */
822 int timeout
; /* Scheduling counter */
823 struct timer_list timer
; /* Timer info for kernel */
824 int tmp
; /* Temporary global per card */
826 u_long lock
; /* Lock the cache accesses */
827 s32 csr0
; /* Saved Bus Mode Register */
828 s32 csr6
; /* Saved Operating Mode Reg. */
829 s32 csr7
; /* Saved IRQ Mask Register */
830 s32 gep
; /* Saved General Purpose Reg. */
831 s32 gepc
; /* Control info for GEP */
832 s32 csr13
; /* Saved SIA Connectivity Reg. */
833 s32 csr14
; /* Saved SIA TX/RX Register */
834 s32 csr15
; /* Saved SIA General Register */
835 int save_cnt
; /* Flag if state already saved */
836 struct sk_buff_head queue
; /* Save the (re-ordered) skb's */
838 struct de4x5_srom srom
; /* A copy of the SROM */
839 int cfrv
; /* Card CFRV copy */
840 int rx_ovf
; /* Check for 'RX overflow' tag */
841 bool useSROM
; /* For non-DEC card use SROM */
842 bool useMII
; /* Infoblock using the MII */
843 int asBitValid
; /* Autosense bits in GEP? */
844 int asPolarity
; /* 0 => asserted high */
845 int asBit
; /* Autosense bit number in GEP */
846 int defMedium
; /* SROM default medium */
847 int tcount
; /* Last infoblock number */
848 int infoblock_init
; /* Initialised this infoblock? */
849 int infoleaf_offset
; /* SROM infoleaf for controller */
850 s32 infoblock_csr6
; /* csr6 value in SROM infoblock */
851 int infoblock_media
; /* infoblock media */
852 int (*infoleaf_fn
)(struct net_device
*); /* Pointer to infoleaf function */
853 u_char
*rst
; /* Pointer to Type 5 reset info */
854 u_char ibn
; /* Infoblock number */
855 struct parameters params
; /* Command line/ #defined params */
856 struct device
*gendev
; /* Generic device */
857 dma_addr_t dma_rings
; /* DMA handle for rings */
858 int dma_size
; /* Size of the DMA area */
859 char *rx_bufs
; /* rx bufs on alpha, sparc, ... */
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
878 u_char addr
[ETH_ALEN
];
882 ** The transmit ring full condition is described by the tx_old and tx_new
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
897 static int de4x5_open(struct net_device
*dev
);
898 static netdev_tx_t
de4x5_queue_pkt(struct sk_buff
*skb
,
899 struct net_device
*dev
);
900 static irqreturn_t
de4x5_interrupt(int irq
, void *dev_id
);
901 static int de4x5_close(struct net_device
*dev
);
902 static struct net_device_stats
*de4x5_get_stats(struct net_device
*dev
);
903 static void de4x5_local_stats(struct net_device
*dev
, char *buf
, int pkt_len
);
904 static void set_multicast_list(struct net_device
*dev
);
905 static int de4x5_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
910 static int de4x5_hw_init(struct net_device
*dev
, u_long iobase
, struct device
*gendev
);
911 static int de4x5_init(struct net_device
*dev
);
912 static int de4x5_sw_reset(struct net_device
*dev
);
913 static int de4x5_rx(struct net_device
*dev
);
914 static int de4x5_tx(struct net_device
*dev
);
915 static void de4x5_ast(struct net_device
*dev
);
916 static int de4x5_txur(struct net_device
*dev
);
917 static int de4x5_rx_ovfc(struct net_device
*dev
);
919 static int autoconf_media(struct net_device
*dev
);
920 static void create_packet(struct net_device
*dev
, char *frame
, int len
);
921 static void load_packet(struct net_device
*dev
, char *buf
, u32 flags
, struct sk_buff
*skb
);
922 static int dc21040_autoconf(struct net_device
*dev
);
923 static int dc21041_autoconf(struct net_device
*dev
);
924 static int dc21140m_autoconf(struct net_device
*dev
);
925 static int dc2114x_autoconf(struct net_device
*dev
);
926 static int srom_autoconf(struct net_device
*dev
);
927 static int de4x5_suspect_state(struct net_device
*dev
, int timeout
, int prev_state
, int (*fn
)(struct net_device
*, int), int (*asfn
)(struct net_device
*));
928 static int dc21040_state(struct net_device
*dev
, int csr13
, int csr14
, int csr15
, int timeout
, int next_state
, int suspect_state
, int (*fn
)(struct net_device
*, int));
929 static int test_media(struct net_device
*dev
, s32 irqs
, s32 irq_mask
, s32 csr13
, s32 csr14
, s32 csr15
, s32 msec
);
930 static int test_for_100Mb(struct net_device
*dev
, int msec
);
931 static int wait_for_link(struct net_device
*dev
);
932 static int test_mii_reg(struct net_device
*dev
, int reg
, int mask
, bool pol
, long msec
);
933 static int is_spd_100(struct net_device
*dev
);
934 static int is_100_up(struct net_device
*dev
);
935 static int is_10_up(struct net_device
*dev
);
936 static int is_anc_capable(struct net_device
*dev
);
937 static int ping_media(struct net_device
*dev
, int msec
);
938 static struct sk_buff
*de4x5_alloc_rx_buff(struct net_device
*dev
, int index
, int len
);
939 static void de4x5_free_rx_buffs(struct net_device
*dev
);
940 static void de4x5_free_tx_buffs(struct net_device
*dev
);
941 static void de4x5_save_skbs(struct net_device
*dev
);
942 static void de4x5_rst_desc_ring(struct net_device
*dev
);
943 static void de4x5_cache_state(struct net_device
*dev
, int flag
);
944 static void de4x5_put_cache(struct net_device
*dev
, struct sk_buff
*skb
);
945 static void de4x5_putb_cache(struct net_device
*dev
, struct sk_buff
*skb
);
946 static struct sk_buff
*de4x5_get_cache(struct net_device
*dev
);
947 static void de4x5_setup_intr(struct net_device
*dev
);
948 static void de4x5_init_connection(struct net_device
*dev
);
949 static int de4x5_reset_phy(struct net_device
*dev
);
950 static void reset_init_sia(struct net_device
*dev
, s32 sicr
, s32 strr
, s32 sigr
);
951 static int test_ans(struct net_device
*dev
, s32 irqs
, s32 irq_mask
, s32 msec
);
952 static int test_tp(struct net_device
*dev
, s32 msec
);
953 static int EISA_signature(char *name
, struct device
*device
);
954 static int PCI_signature(char *name
, struct de4x5_private
*lp
);
955 static void DevicePresent(struct net_device
*dev
, u_long iobase
);
956 static void enet_addr_rst(u_long aprom_addr
);
957 static int de4x5_bad_srom(struct de4x5_private
*lp
);
958 static short srom_rd(u_long address
, u_char offset
);
959 static void srom_latch(u_int command
, u_long address
);
960 static void srom_command(u_int command
, u_long address
);
961 static void srom_address(u_int command
, u_long address
, u_char offset
);
962 static short srom_data(u_int command
, u_long address
);
963 /*static void srom_busy(u_int command, u_long address);*/
964 static void sendto_srom(u_int command
, u_long addr
);
965 static int getfrom_srom(u_long addr
);
966 static int srom_map_media(struct net_device
*dev
);
967 static int srom_infoleaf_info(struct net_device
*dev
);
968 static void srom_init(struct net_device
*dev
);
969 static void srom_exec(struct net_device
*dev
, u_char
*p
);
970 static int mii_rd(u_char phyreg
, u_char phyaddr
, u_long ioaddr
);
971 static void mii_wr(int data
, u_char phyreg
, u_char phyaddr
, u_long ioaddr
);
972 static int mii_rdata(u_long ioaddr
);
973 static void mii_wdata(int data
, int len
, u_long ioaddr
);
974 static void mii_ta(u_long rw
, u_long ioaddr
);
975 static int mii_swap(int data
, int len
);
976 static void mii_address(u_char addr
, u_long ioaddr
);
977 static void sendto_mii(u32 command
, int data
, u_long ioaddr
);
978 static int getfrom_mii(u32 command
, u_long ioaddr
);
979 static int mii_get_oui(u_char phyaddr
, u_long ioaddr
);
980 static int mii_get_phy(struct net_device
*dev
);
981 static void SetMulticastFilter(struct net_device
*dev
);
982 static int get_hw_addr(struct net_device
*dev
);
983 static void srom_repair(struct net_device
*dev
, int card
);
984 static int test_bad_enet(struct net_device
*dev
, int status
);
985 static int an_exception(struct de4x5_private
*lp
);
986 static char *build_setup_frame(struct net_device
*dev
, int mode
);
987 static void disable_ast(struct net_device
*dev
);
988 static long de4x5_switch_mac_port(struct net_device
*dev
);
989 static int gep_rd(struct net_device
*dev
);
990 static void gep_wr(s32 data
, struct net_device
*dev
);
991 static void yawn(struct net_device
*dev
, int state
);
992 static void de4x5_parse_params(struct net_device
*dev
);
993 static void de4x5_dbg_open(struct net_device
*dev
);
994 static void de4x5_dbg_mii(struct net_device
*dev
, int k
);
995 static void de4x5_dbg_media(struct net_device
*dev
);
996 static void de4x5_dbg_srom(struct de4x5_srom
*p
);
997 static void de4x5_dbg_rx(struct sk_buff
*skb
, int len
);
998 static int de4x5_strncmp(char *a
, char *b
, int n
);
999 static int dc21041_infoleaf(struct net_device
*dev
);
1000 static int dc21140_infoleaf(struct net_device
*dev
);
1001 static int dc21142_infoleaf(struct net_device
*dev
);
1002 static int dc21143_infoleaf(struct net_device
*dev
);
1003 static int type0_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
);
1004 static int type1_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
);
1005 static int type2_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
);
1006 static int type3_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
);
1007 static int type4_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
);
1008 static int type5_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
);
1009 static int compact_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
);
1012 ** Note now that module autoprobing is allowed under EISA and PCI. The
1013 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1014 ** to "do the right thing".
1017 static int io
=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1019 module_param(io
, int, 0);
1020 module_param(de4x5_debug
, int, 0);
1021 module_param(dec_only
, int, 0);
1022 module_param(args
, charp
, 0);
1024 MODULE_PARM_DESC(io
, "de4x5 I/O base address");
1025 MODULE_PARM_DESC(de4x5_debug
, "de4x5 debug mask");
1026 MODULE_PARM_DESC(dec_only
, "de4x5 probe only for Digital boards (0-1)");
1027 MODULE_PARM_DESC(args
, "de4x5 full duplex and media type settings; see de4x5.c for details");
1028 MODULE_LICENSE("GPL");
1031 ** List the SROM infoleaf functions and chipsets
1035 int (*fn
)(struct net_device
*);
1037 static struct InfoLeaf infoleaf_array
[] = {
1038 {DC21041
, dc21041_infoleaf
},
1039 {DC21140
, dc21140_infoleaf
},
1040 {DC21142
, dc21142_infoleaf
},
1041 {DC21143
, dc21143_infoleaf
}
1043 #define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1046 ** List the SROM info block functions
1048 static int (*dc_infoblock
[])(struct net_device
*dev
, u_char
, u_char
*) = {
1058 #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1061 ** Miscellaneous defines...
1063 #define RESET_DE4X5 {\
1067 outl(i | BMR_SWR, DE4X5_BMR);\
1069 outl(i, DE4X5_BMR);\
1071 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1075 #define PHY_HARD_RESET {\
1076 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1077 mdelay(1); /* Assert for 1ms */\
1078 outl(0x00, DE4X5_GEP);\
1079 mdelay(2); /* Wait for 2ms */\
1082 static const struct net_device_ops de4x5_netdev_ops
= {
1083 .ndo_open
= de4x5_open
,
1084 .ndo_stop
= de4x5_close
,
1085 .ndo_start_xmit
= de4x5_queue_pkt
,
1086 .ndo_get_stats
= de4x5_get_stats
,
1087 .ndo_set_multicast_list
= set_multicast_list
,
1088 .ndo_do_ioctl
= de4x5_ioctl
,
1089 .ndo_change_mtu
= eth_change_mtu
,
1090 .ndo_set_mac_address
= eth_mac_addr
,
1091 .ndo_validate_addr
= eth_validate_addr
,
1095 static int __devinit
1096 de4x5_hw_init(struct net_device
*dev
, u_long iobase
, struct device
*gendev
)
1098 char name
[DE4X5_NAME_LENGTH
+ 1];
1099 struct de4x5_private
*lp
= netdev_priv(dev
);
1100 struct pci_dev
*pdev
= NULL
;
1103 dev_set_drvdata(gendev
, dev
);
1105 /* Ensure we're not sleeping */
1106 if (lp
->bus
== EISA
) {
1107 outb(WAKEUP
, PCI_CFPM
);
1109 pdev
= to_pci_dev (gendev
);
1110 pci_write_config_byte(pdev
, PCI_CFDA_PSM
, WAKEUP
);
1116 if ((inl(DE4X5_STS
) & (STS_TS
| STS_RS
)) != 0) {
1117 return -ENXIO
; /* Hardware could not reset */
1121 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1123 lp
->useSROM
= false;
1124 if (lp
->bus
== PCI
) {
1125 PCI_signature(name
, lp
);
1127 EISA_signature(name
, gendev
);
1130 if (*name
== '\0') { /* Not found a board signature */
1134 dev
->base_addr
= iobase
;
1135 printk ("%s: %s at 0x%04lx", dev_name(gendev
), name
, iobase
);
1137 status
= get_hw_addr(dev
);
1138 printk(", h/w address %pM\n", dev
->dev_addr
);
1141 printk(" which has an Ethernet PROM CRC error.\n");
1144 skb_queue_head_init(&lp
->cache
.queue
);
1145 lp
->cache
.gepc
= GEP_INIT
;
1146 lp
->asBit
= GEP_SLNK
;
1147 lp
->asPolarity
= GEP_SLNK
;
1148 lp
->asBitValid
= ~0;
1150 lp
->gendev
= gendev
;
1151 spin_lock_init(&lp
->lock
);
1152 init_timer(&lp
->timer
);
1153 lp
->timer
.function
= (void (*)(unsigned long))de4x5_ast
;
1154 lp
->timer
.data
= (unsigned long)dev
;
1155 de4x5_parse_params(dev
);
1158 ** Choose correct autosensing in case someone messed up
1160 lp
->autosense
= lp
->params
.autosense
;
1161 if (lp
->chipset
!= DC21140
) {
1162 if ((lp
->chipset
==DC21040
) && (lp
->params
.autosense
&TP_NW
)) {
1163 lp
->params
.autosense
= TP
;
1165 if ((lp
->chipset
==DC21041
) && (lp
->params
.autosense
&BNC_AUI
)) {
1166 lp
->params
.autosense
= BNC
;
1169 lp
->fdx
= lp
->params
.fdx
;
1170 sprintf(lp
->adapter_name
,"%s (%s)", name
, dev_name(gendev
));
1172 lp
->dma_size
= (NUM_RX_DESC
+ NUM_TX_DESC
) * sizeof(struct de4x5_desc
);
1173 #if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1174 lp
->dma_size
+= RX_BUFF_SZ
* NUM_RX_DESC
+ DE4X5_ALIGN
;
1176 lp
->rx_ring
= dma_alloc_coherent(gendev
, lp
->dma_size
,
1177 &lp
->dma_rings
, GFP_ATOMIC
);
1178 if (lp
->rx_ring
== NULL
) {
1182 lp
->tx_ring
= lp
->rx_ring
+ NUM_RX_DESC
;
1185 ** Set up the RX descriptor ring (Intels)
1186 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1188 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1189 for (i
=0; i
<NUM_RX_DESC
; i
++) {
1190 lp
->rx_ring
[i
].status
= 0;
1191 lp
->rx_ring
[i
].des1
= cpu_to_le32(RX_BUFF_SZ
);
1192 lp
->rx_ring
[i
].buf
= 0;
1193 lp
->rx_ring
[i
].next
= 0;
1194 lp
->rx_skb
[i
] = (struct sk_buff
*) 1; /* Dummy entry */
1199 dma_addr_t dma_rx_bufs
;
1201 dma_rx_bufs
= lp
->dma_rings
+ (NUM_RX_DESC
+ NUM_TX_DESC
)
1202 * sizeof(struct de4x5_desc
);
1203 dma_rx_bufs
= (dma_rx_bufs
+ DE4X5_ALIGN
) & ~DE4X5_ALIGN
;
1204 lp
->rx_bufs
= (char *)(((long)(lp
->rx_ring
+ NUM_RX_DESC
1205 + NUM_TX_DESC
) + DE4X5_ALIGN
) & ~DE4X5_ALIGN
);
1206 for (i
=0; i
<NUM_RX_DESC
; i
++) {
1207 lp
->rx_ring
[i
].status
= 0;
1208 lp
->rx_ring
[i
].des1
= cpu_to_le32(RX_BUFF_SZ
);
1209 lp
->rx_ring
[i
].buf
=
1210 cpu_to_le32(dma_rx_bufs
+i
*RX_BUFF_SZ
);
1211 lp
->rx_ring
[i
].next
= 0;
1212 lp
->rx_skb
[i
] = (struct sk_buff
*) 1; /* Dummy entry */
1220 lp
->rxRingSize
= NUM_RX_DESC
;
1221 lp
->txRingSize
= NUM_TX_DESC
;
1223 /* Write the end of list marker to the descriptor lists */
1224 lp
->rx_ring
[lp
->rxRingSize
- 1].des1
|= cpu_to_le32(RD_RER
);
1225 lp
->tx_ring
[lp
->txRingSize
- 1].des1
|= cpu_to_le32(TD_TER
);
1227 /* Tell the adapter where the TX/RX rings are located. */
1228 outl(lp
->dma_rings
, DE4X5_RRBA
);
1229 outl(lp
->dma_rings
+ NUM_RX_DESC
* sizeof(struct de4x5_desc
),
1232 /* Initialise the IRQ mask and Enable/Disable */
1233 lp
->irq_mask
= IMR_RIM
| IMR_TIM
| IMR_TUM
| IMR_UNM
;
1234 lp
->irq_en
= IMR_NIM
| IMR_AIM
;
1236 /* Create a loopback packet frame for later media probing */
1237 create_packet(dev
, lp
->frame
, sizeof(lp
->frame
));
1239 /* Check if the RX overflow bug needs testing for */
1240 i
= lp
->cfrv
& 0x000000fe;
1241 if ((lp
->chipset
== DC21140
) && (i
== 0x20)) {
1245 /* Initialise the SROM pointers if possible */
1247 lp
->state
= INITIALISED
;
1248 if (srom_infoleaf_info(dev
)) {
1249 dma_free_coherent (gendev
, lp
->dma_size
,
1250 lp
->rx_ring
, lp
->dma_rings
);
1259 ** Check for an MII interface
1261 if ((lp
->chipset
!= DC21040
) && (lp
->chipset
!= DC21041
)) {
1265 printk(" and requires IRQ%d (provided by %s).\n", dev
->irq
,
1266 ((lp
->bus
== PCI
) ? "PCI BIOS" : "EISA CNFG"));
1269 if (de4x5_debug
& DEBUG_VERSION
) {
1273 /* The DE4X5-specific entries in the device structure. */
1274 SET_NETDEV_DEV(dev
, gendev
);
1275 dev
->netdev_ops
= &de4x5_netdev_ops
;
1278 /* Fill in the generic fields of the device structure. */
1279 if ((status
= register_netdev (dev
))) {
1280 dma_free_coherent (gendev
, lp
->dma_size
,
1281 lp
->rx_ring
, lp
->dma_rings
);
1285 /* Let the adapter sleep to save power */
1293 de4x5_open(struct net_device
*dev
)
1295 struct de4x5_private
*lp
= netdev_priv(dev
);
1296 u_long iobase
= dev
->base_addr
;
1300 /* Allocate the RX buffers */
1301 for (i
=0; i
<lp
->rxRingSize
; i
++) {
1302 if (de4x5_alloc_rx_buff(dev
, i
, 0) == NULL
) {
1303 de4x5_free_rx_buffs(dev
);
1309 ** Wake up the adapter
1314 ** Re-initialize the DE4X5...
1316 status
= de4x5_init(dev
);
1317 spin_lock_init(&lp
->lock
);
1319 de4x5_dbg_open(dev
);
1321 if (request_irq(dev
->irq
, de4x5_interrupt
, IRQF_SHARED
,
1322 lp
->adapter_name
, dev
)) {
1323 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev
->irq
);
1324 if (request_irq(dev
->irq
, de4x5_interrupt
, IRQF_DISABLED
| IRQF_SHARED
,
1325 lp
->adapter_name
, dev
)) {
1326 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1328 de4x5_free_rx_buffs(dev
);
1329 de4x5_free_tx_buffs(dev
);
1334 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1335 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1339 lp
->interrupt
= UNMASK_INTERRUPTS
;
1340 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1344 de4x5_setup_intr(dev
);
1346 if (de4x5_debug
& DEBUG_OPEN
) {
1347 printk("\tsts: 0x%08x\n", inl(DE4X5_STS
));
1348 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR
));
1349 printk("\timr: 0x%08x\n", inl(DE4X5_IMR
));
1350 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR
));
1351 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR
));
1352 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR
));
1353 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR
));
1354 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR
));
1361 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1362 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1363 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1364 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1365 ** to be data corruption problems if it is larger (UDP errors seen from a
1369 de4x5_init(struct net_device
*dev
)
1371 /* Lock out other processes whilst setting up the hardware */
1372 netif_stop_queue(dev
);
1374 de4x5_sw_reset(dev
);
1376 /* Autoconfigure the connected port */
1377 autoconf_media(dev
);
1383 de4x5_sw_reset(struct net_device
*dev
)
1385 struct de4x5_private
*lp
= netdev_priv(dev
);
1386 u_long iobase
= dev
->base_addr
;
1387 int i
, j
, status
= 0;
1390 /* Select the MII or SRL port now and RESET the MAC */
1392 if (lp
->phy
[lp
->active
].id
!= 0) {
1393 lp
->infoblock_csr6
= OMR_SDP
| OMR_PS
| OMR_HBD
;
1395 lp
->infoblock_csr6
= OMR_SDP
| OMR_TTM
;
1397 de4x5_switch_mac_port(dev
);
1401 ** Set the programmable burst length to 8 longwords for all the DC21140
1402 ** Fasternet chips and 4 longwords for all others: DMA errors result
1403 ** without these values. Cache align 16 long.
1405 bmr
= (lp
->chipset
==DC21140
? PBL_8
: PBL_4
) | DESC_SKIP_LEN
| DE4X5_CACHE_ALIGN
;
1406 bmr
|= ((lp
->chipset
& ~0x00ff)==DC2114x
? BMR_RML
: 0);
1407 outl(bmr
, DE4X5_BMR
);
1409 omr
= inl(DE4X5_OMR
) & ~OMR_PR
; /* Turn off promiscuous mode */
1410 if (lp
->chipset
== DC21140
) {
1411 omr
|= (OMR_SDP
| OMR_SB
);
1413 lp
->setup_f
= PERFECT
;
1414 outl(lp
->dma_rings
, DE4X5_RRBA
);
1415 outl(lp
->dma_rings
+ NUM_RX_DESC
* sizeof(struct de4x5_desc
),
1418 lp
->rx_new
= lp
->rx_old
= 0;
1419 lp
->tx_new
= lp
->tx_old
= 0;
1421 for (i
= 0; i
< lp
->rxRingSize
; i
++) {
1422 lp
->rx_ring
[i
].status
= cpu_to_le32(R_OWN
);
1425 for (i
= 0; i
< lp
->txRingSize
; i
++) {
1426 lp
->tx_ring
[i
].status
= cpu_to_le32(0);
1431 /* Build the setup frame depending on filtering mode */
1432 SetMulticastFilter(dev
);
1434 load_packet(dev
, lp
->setup_frame
, PERFECT_F
|TD_SET
|SETUP_FRAME_LEN
, (struct sk_buff
*)1);
1435 outl(omr
|OMR_ST
, DE4X5_OMR
);
1437 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1439 for (j
=0, i
=0;(i
<500) && (j
==0);i
++) { /* Upto 500ms delay */
1441 if ((s32
)le32_to_cpu(lp
->tx_ring
[lp
->tx_new
].status
) >= 0) j
=1;
1443 outl(omr
, DE4X5_OMR
); /* Stop everything! */
1446 printk("%s: Setup frame timed out, status %08x\n", dev
->name
,
1451 lp
->tx_new
= (++lp
->tx_new
) % lp
->txRingSize
;
1452 lp
->tx_old
= lp
->tx_new
;
1458 ** Writes a socket buffer address to the next available transmit descriptor.
1461 de4x5_queue_pkt(struct sk_buff
*skb
, struct net_device
*dev
)
1463 struct de4x5_private
*lp
= netdev_priv(dev
);
1464 u_long iobase
= dev
->base_addr
;
1467 netif_stop_queue(dev
);
1468 if (!lp
->tx_enable
) /* Cannot send for now */
1469 return NETDEV_TX_LOCKED
;
1472 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1473 ** interrupts are lost by delayed descriptor status updates relative to
1474 ** the irq assertion, especially with a busy PCI bus.
1476 spin_lock_irqsave(&lp
->lock
, flags
);
1478 spin_unlock_irqrestore(&lp
->lock
, flags
);
1480 /* Test if cache is already locked - requeue skb if so */
1481 if (test_and_set_bit(0, (void *)&lp
->cache
.lock
) && !lp
->interrupt
)
1482 return NETDEV_TX_LOCKED
;
1484 /* Transmit descriptor ring full or stale skb */
1485 if (netif_queue_stopped(dev
) || (u_long
) lp
->tx_skb
[lp
->tx_new
] > 1) {
1486 if (lp
->interrupt
) {
1487 de4x5_putb_cache(dev
, skb
); /* Requeue the buffer */
1489 de4x5_put_cache(dev
, skb
);
1491 if (de4x5_debug
& DEBUG_TX
) {
1492 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev
->name
, inl(DE4X5_STS
), netif_queue_stopped(dev
), inl(DE4X5_IMR
), inl(DE4X5_OMR
), ((u_long
) lp
->tx_skb
[lp
->tx_new
] > 1) ? "YES" : "NO");
1494 } else if (skb
->len
> 0) {
1495 /* If we already have stuff queued locally, use that first */
1496 if (!skb_queue_empty(&lp
->cache
.queue
) && !lp
->interrupt
) {
1497 de4x5_put_cache(dev
, skb
);
1498 skb
= de4x5_get_cache(dev
);
1501 while (skb
&& !netif_queue_stopped(dev
) &&
1502 (u_long
) lp
->tx_skb
[lp
->tx_new
] <= 1) {
1503 spin_lock_irqsave(&lp
->lock
, flags
);
1504 netif_stop_queue(dev
);
1505 load_packet(dev
, skb
->data
, TD_IC
| TD_LS
| TD_FS
| skb
->len
, skb
);
1506 lp
->stats
.tx_bytes
+= skb
->len
;
1507 outl(POLL_DEMAND
, DE4X5_TPD
);/* Start the TX */
1509 lp
->tx_new
= (++lp
->tx_new
) % lp
->txRingSize
;
1511 if (TX_BUFFS_AVAIL
) {
1512 netif_start_queue(dev
); /* Another pkt may be queued */
1514 skb
= de4x5_get_cache(dev
);
1515 spin_unlock_irqrestore(&lp
->lock
, flags
);
1517 if (skb
) de4x5_putb_cache(dev
, skb
);
1522 return NETDEV_TX_OK
;
1526 ** The DE4X5 interrupt handler.
1528 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1529 ** so that the asserted interrupt always has some real data to work with -
1530 ** if these I/O accesses are ever changed to memory accesses, ensure the
1531 ** STS write is read immediately to complete the transaction if the adapter
1532 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1533 ** is high and descriptor status bits cannot be set before the associated
1534 ** interrupt is asserted and this routine entered.
1537 de4x5_interrupt(int irq
, void *dev_id
)
1539 struct net_device
*dev
= dev_id
;
1540 struct de4x5_private
*lp
;
1541 s32 imr
, omr
, sts
, limit
;
1543 unsigned int handled
= 0;
1545 lp
= netdev_priv(dev
);
1546 spin_lock(&lp
->lock
);
1547 iobase
= dev
->base_addr
;
1549 DISABLE_IRQs
; /* Ensure non re-entrancy */
1551 if (test_and_set_bit(MASK_INTERRUPTS
, (void*) &lp
->interrupt
))
1552 printk("%s: Re-entering the interrupt handler.\n", dev
->name
);
1554 synchronize_irq(dev
->irq
);
1556 for (limit
=0; limit
<8; limit
++) {
1557 sts
= inl(DE4X5_STS
); /* Read IRQ status */
1558 outl(sts
, DE4X5_STS
); /* Reset the board interrupts */
1560 if (!(sts
& lp
->irq_mask
)) break;/* All done */
1563 if (sts
& (STS_RI
| STS_RU
)) /* Rx interrupt (packet[s] arrived) */
1566 if (sts
& (STS_TI
| STS_TU
)) /* Tx interrupt (packet sent) */
1569 if (sts
& STS_LNF
) { /* TP Link has failed */
1570 lp
->irq_mask
&= ~IMR_LFM
;
1573 if (sts
& STS_UNF
) { /* Transmit underrun */
1577 if (sts
& STS_SE
) { /* Bus Error */
1579 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1581 spin_unlock(&lp
->lock
);
1586 /* Load the TX ring with any locally stored packets */
1587 if (!test_and_set_bit(0, (void *)&lp
->cache
.lock
)) {
1588 while (!skb_queue_empty(&lp
->cache
.queue
) && !netif_queue_stopped(dev
) && lp
->tx_enable
) {
1589 de4x5_queue_pkt(de4x5_get_cache(dev
), dev
);
1594 lp
->interrupt
= UNMASK_INTERRUPTS
;
1596 spin_unlock(&lp
->lock
);
1598 return IRQ_RETVAL(handled
);
1602 de4x5_rx(struct net_device
*dev
)
1604 struct de4x5_private
*lp
= netdev_priv(dev
);
1605 u_long iobase
= dev
->base_addr
;
1609 for (entry
=lp
->rx_new
; (s32
)le32_to_cpu(lp
->rx_ring
[entry
].status
)>=0;
1611 status
= (s32
)le32_to_cpu(lp
->rx_ring
[entry
].status
);
1614 if (inl(DE4X5_MFC
) & MFC_FOCM
) {
1620 if (status
& RD_FS
) { /* Remember the start of frame */
1624 if (status
& RD_LS
) { /* Valid frame status */
1625 if (lp
->tx_enable
) lp
->linkOK
++;
1626 if (status
& RD_ES
) { /* There was an error. */
1627 lp
->stats
.rx_errors
++; /* Update the error stats. */
1628 if (status
& (RD_RF
| RD_TL
)) lp
->stats
.rx_frame_errors
++;
1629 if (status
& RD_CE
) lp
->stats
.rx_crc_errors
++;
1630 if (status
& RD_OF
) lp
->stats
.rx_fifo_errors
++;
1631 if (status
& RD_TL
) lp
->stats
.rx_length_errors
++;
1632 if (status
& RD_RF
) lp
->pktStats
.rx_runt_frames
++;
1633 if (status
& RD_CS
) lp
->pktStats
.rx_collision
++;
1634 if (status
& RD_DB
) lp
->pktStats
.rx_dribble
++;
1635 if (status
& RD_OF
) lp
->pktStats
.rx_overflow
++;
1636 } else { /* A valid frame received */
1637 struct sk_buff
*skb
;
1638 short pkt_len
= (short)(le32_to_cpu(lp
->rx_ring
[entry
].status
)
1641 if ((skb
= de4x5_alloc_rx_buff(dev
, entry
, pkt_len
)) == NULL
) {
1642 printk("%s: Insufficient memory; nuking packet.\n",
1644 lp
->stats
.rx_dropped
++;
1646 de4x5_dbg_rx(skb
, pkt_len
);
1648 /* Push up the protocol stack */
1649 skb
->protocol
=eth_type_trans(skb
,dev
);
1650 de4x5_local_stats(dev
, skb
->data
, pkt_len
);
1654 lp
->stats
.rx_packets
++;
1655 lp
->stats
.rx_bytes
+= pkt_len
;
1659 /* Change buffer ownership for this frame, back to the adapter */
1660 for (;lp
->rx_old
!=entry
;lp
->rx_old
=(++lp
->rx_old
)%lp
->rxRingSize
) {
1661 lp
->rx_ring
[lp
->rx_old
].status
= cpu_to_le32(R_OWN
);
1664 lp
->rx_ring
[entry
].status
= cpu_to_le32(R_OWN
);
1669 ** Update entry information
1671 lp
->rx_new
= (++lp
->rx_new
) % lp
->rxRingSize
;
1678 de4x5_free_tx_buff(struct de4x5_private
*lp
, int entry
)
1680 dma_unmap_single(lp
->gendev
, le32_to_cpu(lp
->tx_ring
[entry
].buf
),
1681 le32_to_cpu(lp
->tx_ring
[entry
].des1
) & TD_TBS1
,
1683 if ((u_long
) lp
->tx_skb
[entry
] > 1)
1684 dev_kfree_skb_irq(lp
->tx_skb
[entry
]);
1685 lp
->tx_skb
[entry
] = NULL
;
1689 ** Buffer sent - check for TX buffer errors.
1692 de4x5_tx(struct net_device
*dev
)
1694 struct de4x5_private
*lp
= netdev_priv(dev
);
1695 u_long iobase
= dev
->base_addr
;
1699 for (entry
= lp
->tx_old
; entry
!= lp
->tx_new
; entry
= lp
->tx_old
) {
1700 status
= (s32
)le32_to_cpu(lp
->tx_ring
[entry
].status
);
1701 if (status
< 0) { /* Buffer not sent yet */
1703 } else if (status
!= 0x7fffffff) { /* Not setup frame */
1704 if (status
& TD_ES
) { /* An error happened */
1705 lp
->stats
.tx_errors
++;
1706 if (status
& TD_NC
) lp
->stats
.tx_carrier_errors
++;
1707 if (status
& TD_LC
) lp
->stats
.tx_window_errors
++;
1708 if (status
& TD_UF
) lp
->stats
.tx_fifo_errors
++;
1709 if (status
& TD_EC
) lp
->pktStats
.excessive_collisions
++;
1710 if (status
& TD_DE
) lp
->stats
.tx_aborted_errors
++;
1712 if (TX_PKT_PENDING
) {
1713 outl(POLL_DEMAND
, DE4X5_TPD
);/* Restart a stalled TX */
1715 } else { /* Packet sent */
1716 lp
->stats
.tx_packets
++;
1717 if (lp
->tx_enable
) lp
->linkOK
++;
1719 /* Update the collision counter */
1720 lp
->stats
.collisions
+= ((status
& TD_EC
) ? 16 :
1721 ((status
& TD_CC
) >> 3));
1723 /* Free the buffer. */
1724 if (lp
->tx_skb
[entry
] != NULL
)
1725 de4x5_free_tx_buff(lp
, entry
);
1728 /* Update all the pointers */
1729 lp
->tx_old
= (++lp
->tx_old
) % lp
->txRingSize
;
1732 /* Any resources available? */
1733 if (TX_BUFFS_AVAIL
&& netif_queue_stopped(dev
)) {
1735 netif_wake_queue(dev
);
1737 netif_start_queue(dev
);
1744 de4x5_ast(struct net_device
*dev
)
1746 struct de4x5_private
*lp
= netdev_priv(dev
);
1747 int next_tick
= DE4X5_AUTOSENSE_MS
;
1751 next_tick
= srom_autoconf(dev
);
1752 else if (lp
->chipset
== DC21140
)
1753 next_tick
= dc21140m_autoconf(dev
);
1754 else if (lp
->chipset
== DC21041
)
1755 next_tick
= dc21041_autoconf(dev
);
1756 else if (lp
->chipset
== DC21040
)
1757 next_tick
= dc21040_autoconf(dev
);
1760 dt
= (next_tick
* HZ
) / 1000;
1765 mod_timer(&lp
->timer
, jiffies
+ dt
);
1769 de4x5_txur(struct net_device
*dev
)
1771 struct de4x5_private
*lp
= netdev_priv(dev
);
1772 u_long iobase
= dev
->base_addr
;
1775 omr
= inl(DE4X5_OMR
);
1776 if (!(omr
& OMR_SF
) || (lp
->chipset
==DC21041
) || (lp
->chipset
==DC21040
)) {
1777 omr
&= ~(OMR_ST
|OMR_SR
);
1778 outl(omr
, DE4X5_OMR
);
1779 while (inl(DE4X5_STS
) & STS_TS
);
1780 if ((omr
& OMR_TR
) < OMR_TR
) {
1785 outl(omr
| OMR_ST
| OMR_SR
, DE4X5_OMR
);
1792 de4x5_rx_ovfc(struct net_device
*dev
)
1794 struct de4x5_private
*lp
= netdev_priv(dev
);
1795 u_long iobase
= dev
->base_addr
;
1798 omr
= inl(DE4X5_OMR
);
1799 outl(omr
& ~OMR_SR
, DE4X5_OMR
);
1800 while (inl(DE4X5_STS
) & STS_RS
);
1802 for (; (s32
)le32_to_cpu(lp
->rx_ring
[lp
->rx_new
].status
)>=0;) {
1803 lp
->rx_ring
[lp
->rx_new
].status
= cpu_to_le32(R_OWN
);
1804 lp
->rx_new
= (++lp
->rx_new
% lp
->rxRingSize
);
1807 outl(omr
, DE4X5_OMR
);
1813 de4x5_close(struct net_device
*dev
)
1815 struct de4x5_private
*lp
= netdev_priv(dev
);
1816 u_long iobase
= dev
->base_addr
;
1821 netif_stop_queue(dev
);
1823 if (de4x5_debug
& DEBUG_CLOSE
) {
1824 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1825 dev
->name
, inl(DE4X5_STS
));
1829 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1834 /* Free the associated irq */
1835 free_irq(dev
->irq
, dev
);
1838 /* Free any socket buffers */
1839 de4x5_free_rx_buffs(dev
);
1840 de4x5_free_tx_buffs(dev
);
1842 /* Put the adapter to sleep to save power */
1848 static struct net_device_stats
*
1849 de4x5_get_stats(struct net_device
*dev
)
1851 struct de4x5_private
*lp
= netdev_priv(dev
);
1852 u_long iobase
= dev
->base_addr
;
1854 lp
->stats
.rx_missed_errors
= (int)(inl(DE4X5_MFC
) & (MFC_OVFL
| MFC_CNTR
));
1860 de4x5_local_stats(struct net_device
*dev
, char *buf
, int pkt_len
)
1862 struct de4x5_private
*lp
= netdev_priv(dev
);
1865 for (i
=1; i
<DE4X5_PKT_STAT_SZ
-1; i
++) {
1866 if (pkt_len
< (i
*DE4X5_PKT_BIN_SZ
)) {
1867 lp
->pktStats
.bins
[i
]++;
1868 i
= DE4X5_PKT_STAT_SZ
;
1871 if (buf
[0] & 0x01) { /* Multicast/Broadcast */
1872 if ((*(s32
*)&buf
[0] == -1) && (*(s16
*)&buf
[4] == -1)) {
1873 lp
->pktStats
.broadcast
++;
1875 lp
->pktStats
.multicast
++;
1877 } else if ((*(s32
*)&buf
[0] == *(s32
*)&dev
->dev_addr
[0]) &&
1878 (*(s16
*)&buf
[4] == *(s16
*)&dev
->dev_addr
[4])) {
1879 lp
->pktStats
.unicast
++;
1882 lp
->pktStats
.bins
[0]++; /* Duplicates stats.rx_packets */
1883 if (lp
->pktStats
.bins
[0] == 0) { /* Reset counters */
1884 memset((char *)&lp
->pktStats
, 0, sizeof(lp
->pktStats
));
1891 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1892 ** If the flag is changed on a descriptor that is being read by the hardware,
1893 ** I assume PCI transaction ordering will mean you are either successful or
1894 ** just miss asserting the change to the hardware. Anyway you're messing with
1895 ** a descriptor you don't own, but this shouldn't kill the chip provided
1896 ** the descriptor register is read only to the hardware.
1899 load_packet(struct net_device
*dev
, char *buf
, u32 flags
, struct sk_buff
*skb
)
1901 struct de4x5_private
*lp
= netdev_priv(dev
);
1902 int entry
= (lp
->tx_new
? lp
->tx_new
-1 : lp
->txRingSize
-1);
1903 dma_addr_t buf_dma
= dma_map_single(lp
->gendev
, buf
, flags
& TD_TBS1
, DMA_TO_DEVICE
);
1905 lp
->tx_ring
[lp
->tx_new
].buf
= cpu_to_le32(buf_dma
);
1906 lp
->tx_ring
[lp
->tx_new
].des1
&= cpu_to_le32(TD_TER
);
1907 lp
->tx_ring
[lp
->tx_new
].des1
|= cpu_to_le32(flags
);
1908 lp
->tx_skb
[lp
->tx_new
] = skb
;
1909 lp
->tx_ring
[entry
].des1
&= cpu_to_le32(~TD_IC
);
1912 lp
->tx_ring
[lp
->tx_new
].status
= cpu_to_le32(T_OWN
);
1917 ** Set or clear the multicast filter for this adaptor.
1920 set_multicast_list(struct net_device
*dev
)
1922 struct de4x5_private
*lp
= netdev_priv(dev
);
1923 u_long iobase
= dev
->base_addr
;
1925 /* First, double check that the adapter is open */
1926 if (lp
->state
== OPEN
) {
1927 if (dev
->flags
& IFF_PROMISC
) { /* set promiscuous mode */
1929 omr
= inl(DE4X5_OMR
);
1931 outl(omr
, DE4X5_OMR
);
1933 SetMulticastFilter(dev
);
1934 load_packet(dev
, lp
->setup_frame
, TD_IC
| PERFECT_F
| TD_SET
|
1935 SETUP_FRAME_LEN
, (struct sk_buff
*)1);
1937 lp
->tx_new
= (++lp
->tx_new
) % lp
->txRingSize
;
1938 outl(POLL_DEMAND
, DE4X5_TPD
); /* Start the TX */
1939 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1945 ** Calculate the hash code and update the logical address filter
1946 ** from a list of ethernet multicast addresses.
1947 ** Little endian crc one liner from Matt Thomas, DEC.
1950 SetMulticastFilter(struct net_device
*dev
)
1952 struct de4x5_private
*lp
= netdev_priv(dev
);
1953 struct netdev_hw_addr
*ha
;
1954 u_long iobase
= dev
->base_addr
;
1959 unsigned char *addrs
;
1961 omr
= inl(DE4X5_OMR
);
1962 omr
&= ~(OMR_PR
| OMR_PM
);
1963 pa
= build_setup_frame(dev
, ALL
); /* Build the basic frame */
1965 if ((dev
->flags
& IFF_ALLMULTI
) || (netdev_mc_count(dev
) > 14)) {
1966 omr
|= OMR_PM
; /* Pass all multicasts */
1967 } else if (lp
->setup_f
== HASH_PERF
) { /* Hash Filtering */
1968 netdev_for_each_mc_addr(ha
, dev
) {
1970 if ((*addrs
& 0x01) == 1) { /* multicast address? */
1971 crc
= ether_crc_le(ETH_ALEN
, addrs
);
1972 hashcode
= crc
& HASH_BITS
; /* hashcode is 9 LSb of CRC */
1974 byte
= hashcode
>> 3; /* bit[3-8] -> byte in filter */
1975 bit
= 1 << (hashcode
& 0x07);/* bit[0-2] -> bit in byte */
1977 byte
<<= 1; /* calc offset into setup frame */
1981 lp
->setup_frame
[byte
] |= bit
;
1984 } else { /* Perfect filtering */
1985 netdev_for_each_mc_addr(ha
, dev
) {
1987 for (i
=0; i
<ETH_ALEN
; i
++) {
1988 *(pa
+ (i
&1)) = *addrs
++;
1989 if (i
& 0x01) pa
+= 4;
1993 outl(omr
, DE4X5_OMR
);
2000 static u_char de4x5_irq
[] = EISA_ALLOWED_IRQ_LIST
;
2002 static int __init
de4x5_eisa_probe (struct device
*gendev
)
2004 struct eisa_device
*edev
;
2010 struct net_device
*dev
;
2011 struct de4x5_private
*lp
;
2013 edev
= to_eisa_device (gendev
);
2014 iobase
= edev
->base_addr
;
2016 if (!request_region (iobase
, DE4X5_EISA_TOTAL_SIZE
, "de4x5"))
2019 if (!request_region (iobase
+ DE4X5_EISA_IO_PORTS
,
2020 DE4X5_EISA_TOTAL_SIZE
, "de4x5")) {
2025 if (!(dev
= alloc_etherdev (sizeof (struct de4x5_private
)))) {
2029 lp
= netdev_priv(dev
);
2031 cfid
= (u32
) inl(PCI_CFID
);
2032 lp
->cfrv
= (u_short
) inl(PCI_CFRV
);
2033 device
= (cfid
>> 8) & 0x00ffff00;
2034 vendor
= (u_short
) cfid
;
2036 /* Read the EISA Configuration Registers */
2037 regval
= inb(EISA_REG0
) & (ER0_INTL
| ER0_INTT
);
2039 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2040 * care about the EISA configuration, and thus doesn't
2041 * configure the PLX bridge properly. Oh well... Simply mimic
2042 * the EISA config file to sort it out. */
2044 /* EISA REG1: Assert DecChip 21040 HW Reset */
2045 outb (ER1_IAM
| 1, EISA_REG1
);
2048 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2049 outb (ER1_IAM
, EISA_REG1
);
2052 /* EISA REG3: R/W Burst Transfer Enable */
2053 outb (ER3_BWE
| ER3_BRE
, EISA_REG3
);
2055 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2056 outb (ER0_BSW
| ER0_BMW
| ER0_EPT
| regval
, EISA_REG0
);
2058 irq
= de4x5_irq
[(regval
>> 1) & 0x03];
2061 device
= ((lp
->cfrv
& CFRV_RN
) < DC2114x_BRK
? DC21142
: DC21143
);
2063 lp
->chipset
= device
;
2066 /* Write the PCI Configuration Registers */
2067 outl(PCI_COMMAND_IO
| PCI_COMMAND_MASTER
, PCI_CFCS
);
2068 outl(0x00006000, PCI_CFLT
);
2069 outl(iobase
, PCI_CBIO
);
2071 DevicePresent(dev
, EISA_APROM
);
2075 if (!(status
= de4x5_hw_init (dev
, iobase
, gendev
))) {
2081 release_region (iobase
+ DE4X5_EISA_IO_PORTS
, DE4X5_EISA_TOTAL_SIZE
);
2083 release_region (iobase
, DE4X5_EISA_TOTAL_SIZE
);
2088 static int __devexit
de4x5_eisa_remove (struct device
*device
)
2090 struct net_device
*dev
;
2093 dev
= dev_get_drvdata(device
);
2094 iobase
= dev
->base_addr
;
2096 unregister_netdev (dev
);
2098 release_region (iobase
+ DE4X5_EISA_IO_PORTS
, DE4X5_EISA_TOTAL_SIZE
);
2099 release_region (iobase
, DE4X5_EISA_TOTAL_SIZE
);
2104 static struct eisa_device_id de4x5_eisa_ids
[] = {
2105 { "DEC4250", 0 }, /* 0 is the board name index... */
2108 MODULE_DEVICE_TABLE(eisa
, de4x5_eisa_ids
);
2110 static struct eisa_driver de4x5_eisa_driver
= {
2111 .id_table
= de4x5_eisa_ids
,
2114 .probe
= de4x5_eisa_probe
,
2115 .remove
= __devexit_p (de4x5_eisa_remove
),
2118 MODULE_DEVICE_TABLE(eisa
, de4x5_eisa_ids
);
2124 ** This function searches the current bus (which is >0) for a DECchip with an
2125 ** SROM, so that in multiport cards that have one SROM shared between multiple
2126 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2127 ** For single port cards this is a time waster...
2129 static void __devinit
2130 srom_search(struct net_device
*dev
, struct pci_dev
*pdev
)
2133 u_short vendor
, status
;
2134 u_int irq
= 0, device
;
2135 u_long iobase
= 0; /* Clear upper 32 bits in Alphas */
2137 struct de4x5_private
*lp
= netdev_priv(dev
);
2138 struct list_head
*walk
;
2140 list_for_each(walk
, &pdev
->bus_list
) {
2141 struct pci_dev
*this_dev
= pci_dev_b(walk
);
2143 /* Skip the pci_bus list entry */
2144 if (list_entry(walk
, struct pci_bus
, devices
) == pdev
->bus
) continue;
2146 vendor
= this_dev
->vendor
;
2147 device
= this_dev
->device
<< 8;
2148 if (!(is_DC21040
|| is_DC21041
|| is_DC21140
|| is_DC2114x
)) continue;
2150 /* Get the chip configuration revision register */
2151 pb
= this_dev
->bus
->number
;
2153 /* Set the device number information */
2154 lp
->device
= PCI_SLOT(this_dev
->devfn
);
2157 /* Set the chipset information */
2159 device
= ((this_dev
->revision
& CFRV_RN
) < DC2114x_BRK
2160 ? DC21142
: DC21143
);
2162 lp
->chipset
= device
;
2164 /* Get the board I/O address (64 bits on sparc64) */
2165 iobase
= pci_resource_start(this_dev
, 0);
2167 /* Fetch the IRQ to be used */
2168 irq
= this_dev
->irq
;
2169 if ((irq
== 0) || (irq
== 0xff) || ((int)irq
== -1)) continue;
2171 /* Check if I/O accesses are enabled */
2172 pci_read_config_word(this_dev
, PCI_COMMAND
, &status
);
2173 if (!(status
& PCI_COMMAND_IO
)) continue;
2175 /* Search for a valid SROM attached to this DECchip */
2176 DevicePresent(dev
, DE4X5_APROM
);
2177 for (j
=0, i
=0; i
<ETH_ALEN
; i
++) {
2178 j
+= (u_char
) *((u_char
*)&lp
->srom
+ SROM_HWADD
+ i
);
2180 if (j
!= 0 && j
!= 6 * 0xff) {
2181 last
.chipset
= device
;
2184 for (i
=0; i
<ETH_ALEN
; i
++) {
2185 last
.addr
[i
] = (u_char
)*((u_char
*)&lp
->srom
+ SROM_HWADD
+ i
);
2195 ** PCI bus I/O device probe
2196 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2197 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2198 ** enabled by the user first in the set up utility. Hence we just check for
2199 ** enabled features and silently ignore the card if they're not.
2201 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2202 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2203 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2204 ** PC doesn't conform to the PCI standard)!
2206 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2207 ** kernels use the V0.535[n] drivers.
2210 static int __devinit
de4x5_pci_probe (struct pci_dev
*pdev
,
2211 const struct pci_device_id
*ent
)
2213 u_char pb
, pbus
= 0, dev_num
, dnum
= 0, timer
;
2214 u_short vendor
, status
;
2215 u_int irq
= 0, device
;
2216 u_long iobase
= 0; /* Clear upper 32 bits in Alphas */
2218 struct net_device
*dev
;
2219 struct de4x5_private
*lp
;
2221 dev_num
= PCI_SLOT(pdev
->devfn
);
2222 pb
= pdev
->bus
->number
;
2224 if (io
) { /* probe a single PCI device */
2225 pbus
= (u_short
)(io
>> 8);
2226 dnum
= (u_short
)(io
& 0xff);
2227 if ((pbus
!= pb
) || (dnum
!= dev_num
))
2231 vendor
= pdev
->vendor
;
2232 device
= pdev
->device
<< 8;
2233 if (!(is_DC21040
|| is_DC21041
|| is_DC21140
|| is_DC2114x
))
2236 /* Ok, the device seems to be for us. */
2237 if ((error
= pci_enable_device (pdev
)))
2240 if (!(dev
= alloc_etherdev (sizeof (struct de4x5_private
)))) {
2245 lp
= netdev_priv(dev
);
2249 /* Search for an SROM on this bus */
2250 if (lp
->bus_num
!= pb
) {
2252 srom_search(dev
, pdev
);
2255 /* Get the chip configuration revision register */
2256 lp
->cfrv
= pdev
->revision
;
2258 /* Set the device number information */
2259 lp
->device
= dev_num
;
2262 /* Set the chipset information */
2264 device
= ((lp
->cfrv
& CFRV_RN
) < DC2114x_BRK
? DC21142
: DC21143
);
2266 lp
->chipset
= device
;
2268 /* Get the board I/O address (64 bits on sparc64) */
2269 iobase
= pci_resource_start(pdev
, 0);
2271 /* Fetch the IRQ to be used */
2273 if ((irq
== 0) || (irq
== 0xff) || ((int)irq
== -1)) {
2278 /* Check if I/O accesses and Bus Mastering are enabled */
2279 pci_read_config_word(pdev
, PCI_COMMAND
, &status
);
2281 if (!(status
& PCI_COMMAND_IO
)) {
2282 status
|= PCI_COMMAND_IO
;
2283 pci_write_config_word(pdev
, PCI_COMMAND
, status
);
2284 pci_read_config_word(pdev
, PCI_COMMAND
, &status
);
2286 #endif /* __powerpc__ */
2287 if (!(status
& PCI_COMMAND_IO
)) {
2292 if (!(status
& PCI_COMMAND_MASTER
)) {
2293 status
|= PCI_COMMAND_MASTER
;
2294 pci_write_config_word(pdev
, PCI_COMMAND
, status
);
2295 pci_read_config_word(pdev
, PCI_COMMAND
, &status
);
2297 if (!(status
& PCI_COMMAND_MASTER
)) {
2302 /* Check the latency timer for values >= 0x60 */
2303 pci_read_config_byte(pdev
, PCI_LATENCY_TIMER
, &timer
);
2305 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0x60);
2308 DevicePresent(dev
, DE4X5_APROM
);
2310 if (!request_region (iobase
, DE4X5_PCI_TOTAL_SIZE
, "de4x5")) {
2317 if ((error
= de4x5_hw_init(dev
, iobase
, &pdev
->dev
))) {
2324 release_region (iobase
, DE4X5_PCI_TOTAL_SIZE
);
2328 pci_disable_device (pdev
);
2332 static void __devexit
de4x5_pci_remove (struct pci_dev
*pdev
)
2334 struct net_device
*dev
;
2337 dev
= dev_get_drvdata(&pdev
->dev
);
2338 iobase
= dev
->base_addr
;
2340 unregister_netdev (dev
);
2342 release_region (iobase
, DE4X5_PCI_TOTAL_SIZE
);
2343 pci_disable_device (pdev
);
2346 static struct pci_device_id de4x5_pci_tbl
[] = {
2347 { PCI_VENDOR_ID_DEC
, PCI_DEVICE_ID_DEC_TULIP
,
2348 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
2349 { PCI_VENDOR_ID_DEC
, PCI_DEVICE_ID_DEC_TULIP_PLUS
,
2350 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1 },
2351 { PCI_VENDOR_ID_DEC
, PCI_DEVICE_ID_DEC_TULIP_FAST
,
2352 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2 },
2353 { PCI_VENDOR_ID_DEC
, PCI_DEVICE_ID_DEC_21142
,
2354 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 3 },
2358 static struct pci_driver de4x5_pci_driver
= {
2360 .id_table
= de4x5_pci_tbl
,
2361 .probe
= de4x5_pci_probe
,
2362 .remove
= __devexit_p (de4x5_pci_remove
),
2368 ** Auto configure the media here rather than setting the port at compile
2369 ** time. This routine is called by de4x5_init() and when a loss of media is
2370 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2371 ** [TP] or no recent receive activity) to check whether the user has been
2372 ** sneaky and changed the port on us.
2375 autoconf_media(struct net_device
*dev
)
2377 struct de4x5_private
*lp
= netdev_priv(dev
);
2378 u_long iobase
= dev
->base_addr
;
2382 lp
->c_media
= AUTO
; /* Bogus last media */
2383 inl(DE4X5_MFC
); /* Zero the lost frames counter */
2393 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2394 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2395 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2396 ** The only way to test for that is to place a loopback packet onto the
2397 ** network and watch for errors. Since we're messing with the interrupt mask
2398 ** register, disable the board interrupts and do not allow any more packets to
2399 ** be queued to the hardware. Re-enable everything only when the media is
2401 ** I may have to "age out" locally queued packets so that the higher layer
2402 ** timeouts don't effectively duplicate packets on the network.
2405 dc21040_autoconf(struct net_device
*dev
)
2407 struct de4x5_private
*lp
= netdev_priv(dev
);
2408 u_long iobase
= dev
->base_addr
;
2409 int next_tick
= DE4X5_AUTOSENSE_MS
;
2412 switch (lp
->media
) {
2415 lp
->tx_enable
= false;
2417 de4x5_save_skbs(dev
);
2418 if ((lp
->autosense
== AUTO
) || (lp
->autosense
== TP
)) {
2420 } else if ((lp
->autosense
== BNC
) || (lp
->autosense
== AUI
) || (lp
->autosense
== BNC_AUI
)) {
2421 lp
->media
= BNC_AUI
;
2422 } else if (lp
->autosense
== EXT_SIA
) {
2423 lp
->media
= EXT_SIA
;
2427 lp
->local_state
= 0;
2428 next_tick
= dc21040_autoconf(dev
);
2432 next_tick
= dc21040_state(dev
, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI
,
2433 TP_SUSPECT
, test_tp
);
2437 next_tick
= de4x5_suspect_state(dev
, 1000, TP
, test_tp
, dc21040_autoconf
);
2443 next_tick
= dc21040_state(dev
, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA
,
2444 BNC_AUI_SUSPECT
, ping_media
);
2447 case BNC_AUI_SUSPECT
:
2448 next_tick
= de4x5_suspect_state(dev
, 1000, BNC_AUI
, ping_media
, dc21040_autoconf
);
2452 next_tick
= dc21040_state(dev
, 0x3041, 0x0000, 0x0006, 3000,
2453 NC
, EXT_SIA_SUSPECT
, ping_media
);
2456 case EXT_SIA_SUSPECT
:
2457 next_tick
= de4x5_suspect_state(dev
, 1000, EXT_SIA
, ping_media
, dc21040_autoconf
);
2461 /* default to TP for all */
2462 reset_init_sia(dev
, 0x8f01, 0xffff, 0x0000);
2463 if (lp
->media
!= lp
->c_media
) {
2464 de4x5_dbg_media(dev
);
2465 lp
->c_media
= lp
->media
;
2468 lp
->tx_enable
= false;
2476 dc21040_state(struct net_device
*dev
, int csr13
, int csr14
, int csr15
, int timeout
,
2477 int next_state
, int suspect_state
,
2478 int (*fn
)(struct net_device
*, int))
2480 struct de4x5_private
*lp
= netdev_priv(dev
);
2481 int next_tick
= DE4X5_AUTOSENSE_MS
;
2484 switch (lp
->local_state
) {
2486 reset_init_sia(dev
, csr13
, csr14
, csr15
);
2492 if (!lp
->tx_enable
) {
2493 linkBad
= fn(dev
, timeout
);
2495 next_tick
= linkBad
& ~TIMER_CB
;
2497 if (linkBad
&& (lp
->autosense
== AUTO
)) {
2498 lp
->local_state
= 0;
2499 lp
->media
= next_state
;
2501 de4x5_init_connection(dev
);
2504 } else if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
2505 lp
->media
= suspect_state
;
2515 de4x5_suspect_state(struct net_device
*dev
, int timeout
, int prev_state
,
2516 int (*fn
)(struct net_device
*, int),
2517 int (*asfn
)(struct net_device
*))
2519 struct de4x5_private
*lp
= netdev_priv(dev
);
2520 int next_tick
= DE4X5_AUTOSENSE_MS
;
2523 switch (lp
->local_state
) {
2526 lp
->media
= prev_state
;
2529 next_tick
= asfn(dev
);
2534 linkBad
= fn(dev
, timeout
);
2536 next_tick
= linkBad
& ~TIMER_CB
;
2537 } else if (!linkBad
) {
2539 lp
->media
= prev_state
;
2550 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2551 ** before BNC, because the BNC port will indicate activity if it's not
2552 ** terminated correctly. The only way to test for that is to place a loopback
2553 ** packet onto the network and watch for errors. Since we're messing with
2554 ** the interrupt mask register, disable the board interrupts and do not allow
2555 ** any more packets to be queued to the hardware. Re-enable everything only
2556 ** when the media is found.
2559 dc21041_autoconf(struct net_device
*dev
)
2561 struct de4x5_private
*lp
= netdev_priv(dev
);
2562 u_long iobase
= dev
->base_addr
;
2563 s32 sts
, irqs
, irq_mask
, imr
, omr
;
2564 int next_tick
= DE4X5_AUTOSENSE_MS
;
2566 switch (lp
->media
) {
2569 lp
->tx_enable
= false;
2571 de4x5_save_skbs(dev
); /* Save non transmitted skb's */
2572 if ((lp
->autosense
== AUTO
) || (lp
->autosense
== TP_NW
)) {
2573 lp
->media
= TP
; /* On chip auto negotiation is broken */
2574 } else if (lp
->autosense
== TP
) {
2576 } else if (lp
->autosense
== BNC
) {
2578 } else if (lp
->autosense
== AUI
) {
2583 lp
->local_state
= 0;
2584 next_tick
= dc21041_autoconf(dev
);
2588 if (lp
->timeout
< 0) {
2589 omr
= inl(DE4X5_OMR
);/* Set up full duplex for the autonegotiate */
2590 outl(omr
| OMR_FDX
, DE4X5_OMR
);
2592 irqs
= STS_LNF
| STS_LNP
;
2593 irq_mask
= IMR_LFM
| IMR_LPM
;
2594 sts
= test_media(dev
, irqs
, irq_mask
, 0xef01, 0xffff, 0x0008, 2400);
2596 next_tick
= sts
& ~TIMER_CB
;
2598 if (sts
& STS_LNP
) {
2603 next_tick
= dc21041_autoconf(dev
);
2608 if (!lp
->tx_enable
) {
2611 sts
= test_ans(dev
, irqs
, irq_mask
, 3000);
2613 next_tick
= sts
& ~TIMER_CB
;
2615 if (!(sts
& STS_LNP
) && (lp
->autosense
== AUTO
)) {
2617 next_tick
= dc21041_autoconf(dev
);
2619 lp
->local_state
= 1;
2620 de4x5_init_connection(dev
);
2623 } else if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
2624 lp
->media
= ANS_SUSPECT
;
2630 next_tick
= de4x5_suspect_state(dev
, 1000, ANS
, test_tp
, dc21041_autoconf
);
2634 if (!lp
->tx_enable
) {
2635 if (lp
->timeout
< 0) {
2636 omr
= inl(DE4X5_OMR
); /* Set up half duplex for TP */
2637 outl(omr
& ~OMR_FDX
, DE4X5_OMR
);
2639 irqs
= STS_LNF
| STS_LNP
;
2640 irq_mask
= IMR_LFM
| IMR_LPM
;
2641 sts
= test_media(dev
,irqs
, irq_mask
, 0xef01, 0xff3f, 0x0008, 2400);
2643 next_tick
= sts
& ~TIMER_CB
;
2645 if (!(sts
& STS_LNP
) && (lp
->autosense
== AUTO
)) {
2646 if (inl(DE4X5_SISR
) & SISR_NRA
) {
2647 lp
->media
= AUI
; /* Non selected port activity */
2651 next_tick
= dc21041_autoconf(dev
);
2653 lp
->local_state
= 1;
2654 de4x5_init_connection(dev
);
2657 } else if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
2658 lp
->media
= TP_SUSPECT
;
2664 next_tick
= de4x5_suspect_state(dev
, 1000, TP
, test_tp
, dc21041_autoconf
);
2668 if (!lp
->tx_enable
) {
2669 if (lp
->timeout
< 0) {
2670 omr
= inl(DE4X5_OMR
); /* Set up half duplex for AUI */
2671 outl(omr
& ~OMR_FDX
, DE4X5_OMR
);
2675 sts
= test_media(dev
,irqs
, irq_mask
, 0xef09, 0xf73d, 0x000e, 1000);
2677 next_tick
= sts
& ~TIMER_CB
;
2679 if (!(inl(DE4X5_SISR
) & SISR_SRA
) && (lp
->autosense
== AUTO
)) {
2681 next_tick
= dc21041_autoconf(dev
);
2683 lp
->local_state
= 1;
2684 de4x5_init_connection(dev
);
2687 } else if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
2688 lp
->media
= AUI_SUSPECT
;
2694 next_tick
= de4x5_suspect_state(dev
, 1000, AUI
, ping_media
, dc21041_autoconf
);
2698 switch (lp
->local_state
) {
2700 if (lp
->timeout
< 0) {
2701 omr
= inl(DE4X5_OMR
); /* Set up half duplex for BNC */
2702 outl(omr
& ~OMR_FDX
, DE4X5_OMR
);
2706 sts
= test_media(dev
,irqs
, irq_mask
, 0xef09, 0xf73d, 0x0006, 1000);
2708 next_tick
= sts
& ~TIMER_CB
;
2710 lp
->local_state
++; /* Ensure media connected */
2711 next_tick
= dc21041_autoconf(dev
);
2716 if (!lp
->tx_enable
) {
2717 if ((sts
= ping_media(dev
, 3000)) < 0) {
2718 next_tick
= sts
& ~TIMER_CB
;
2721 lp
->local_state
= 0;
2724 de4x5_init_connection(dev
);
2727 } else if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
2728 lp
->media
= BNC_SUSPECT
;
2736 next_tick
= de4x5_suspect_state(dev
, 1000, BNC
, ping_media
, dc21041_autoconf
);
2740 omr
= inl(DE4X5_OMR
); /* Set up full duplex for the autonegotiate */
2741 outl(omr
| OMR_FDX
, DE4X5_OMR
);
2742 reset_init_sia(dev
, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2743 if (lp
->media
!= lp
->c_media
) {
2744 de4x5_dbg_media(dev
);
2745 lp
->c_media
= lp
->media
;
2748 lp
->tx_enable
= false;
2756 ** Some autonegotiation chips are broken in that they do not return the
2757 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2758 ** register, except at the first power up negotiation.
2761 dc21140m_autoconf(struct net_device
*dev
)
2763 struct de4x5_private
*lp
= netdev_priv(dev
);
2764 int ana
, anlpa
, cap
, cr
, slnk
, sr
;
2765 int next_tick
= DE4X5_AUTOSENSE_MS
;
2766 u_long imr
, omr
, iobase
= dev
->base_addr
;
2770 if (lp
->timeout
< 0) {
2772 lp
->tx_enable
= false;
2774 de4x5_save_skbs(dev
); /* Save non transmitted skb's */
2776 if ((next_tick
= de4x5_reset_phy(dev
)) < 0) {
2777 next_tick
&= ~TIMER_CB
;
2780 if (srom_map_media(dev
) < 0) {
2784 srom_exec(dev
, lp
->phy
[lp
->active
].gep
);
2785 if (lp
->infoblock_media
== ANS
) {
2786 ana
= lp
->phy
[lp
->active
].ana
| MII_ANA_CSMA
;
2787 mii_wr(ana
, MII_ANA
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
2790 lp
->tmp
= MII_SR_ASSC
; /* Fake out the MII speed set */
2792 if (lp
->autosense
== _100Mb
) {
2794 } else if (lp
->autosense
== _10Mb
) {
2796 } else if ((lp
->autosense
== AUTO
) &&
2797 ((sr
=is_anc_capable(dev
)) & MII_SR_ANC
)) {
2798 ana
= (((sr
>> 6) & MII_ANA_TAF
) | MII_ANA_CSMA
);
2799 ana
&= (lp
->fdx
? ~0 : ~MII_ANA_FDAM
);
2800 mii_wr(ana
, MII_ANA
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
2802 } else if (lp
->autosense
== AUTO
) {
2803 lp
->media
= SPD_DET
;
2804 } else if (is_spd_100(dev
) && is_100_up(dev
)) {
2810 lp
->local_state
= 0;
2811 next_tick
= dc21140m_autoconf(dev
);
2816 switch (lp
->local_state
) {
2818 if (lp
->timeout
< 0) {
2819 mii_wr(MII_CR_ASSE
| MII_CR_RAN
, MII_CR
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
2821 cr
= test_mii_reg(dev
, MII_CR
, MII_CR_RAN
, false, 500);
2823 next_tick
= cr
& ~TIMER_CB
;
2826 lp
->local_state
= 0;
2827 lp
->media
= SPD_DET
;
2831 next_tick
= dc21140m_autoconf(dev
);
2836 if ((sr
=test_mii_reg(dev
, MII_SR
, MII_SR_ASSC
, true, 2000)) < 0) {
2837 next_tick
= sr
& ~TIMER_CB
;
2839 lp
->media
= SPD_DET
;
2840 lp
->local_state
= 0;
2841 if (sr
) { /* Success! */
2842 lp
->tmp
= MII_SR_ASSC
;
2843 anlpa
= mii_rd(MII_ANLPA
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
2844 ana
= mii_rd(MII_ANA
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
2845 if (!(anlpa
& MII_ANLPA_RF
) &&
2846 (cap
= anlpa
& MII_ANLPA_TAF
& ana
)) {
2847 if (cap
& MII_ANA_100M
) {
2848 lp
->fdx
= (ana
& anlpa
& MII_ANA_FDAM
& MII_ANA_100M
) != 0;
2850 } else if (cap
& MII_ANA_10M
) {
2851 lp
->fdx
= (ana
& anlpa
& MII_ANA_FDAM
& MII_ANA_10M
) != 0;
2856 } /* Auto Negotiation failed to finish */
2857 next_tick
= dc21140m_autoconf(dev
);
2858 } /* Auto Negotiation failed to start */
2863 case SPD_DET
: /* Choose 10Mb/s or 100Mb/s */
2864 if (lp
->timeout
< 0) {
2865 lp
->tmp
= (lp
->phy
[lp
->active
].id
? MII_SR_LKS
:
2866 (~gep_rd(dev
) & GEP_LNP
));
2869 if ((slnk
= test_for_100Mb(dev
, 6500)) < 0) {
2870 next_tick
= slnk
& ~TIMER_CB
;
2872 if (is_spd_100(dev
) && is_100_up(dev
)) {
2874 } else if ((!is_spd_100(dev
) && (is_10_up(dev
) & lp
->tmp
))) {
2879 next_tick
= dc21140m_autoconf(dev
);
2883 case _100Mb
: /* Set 100Mb/s */
2885 if (!lp
->tx_enable
) {
2887 de4x5_init_connection(dev
);
2889 if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
2890 if (!is_100_up(dev
) || (!lp
->useSROM
&& !is_spd_100(dev
))) {
2893 next_tick
= DE4X5_AUTOSENSE_MS
;
2901 case _10Mb
: /* Set 10Mb/s */
2903 if (!lp
->tx_enable
) {
2905 de4x5_init_connection(dev
);
2907 if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
2908 if (!is_10_up(dev
) || (!lp
->useSROM
&& is_spd_100(dev
))) {
2911 next_tick
= DE4X5_AUTOSENSE_MS
;
2918 if (lp
->media
!= lp
->c_media
) {
2919 de4x5_dbg_media(dev
);
2920 lp
->c_media
= lp
->media
;
2923 lp
->tx_enable
= false;
2931 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2932 ** changing how I figure out the media - but trying to keep it backwards
2933 ** compatible with the de500-xa and de500-aa.
2934 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2935 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2936 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2938 ** When autonegotiation is working, the ANS part searches the SROM for
2939 ** the highest common speed (TP) link that both can run and if that can
2940 ** be full duplex. That infoblock is executed and then the link speed set.
2942 ** Only _10Mb and _100Mb are tested here.
2945 dc2114x_autoconf(struct net_device
*dev
)
2947 struct de4x5_private
*lp
= netdev_priv(dev
);
2948 u_long iobase
= dev
->base_addr
;
2949 s32 cr
, anlpa
, ana
, cap
, irqs
, irq_mask
, imr
, omr
, slnk
, sr
, sts
;
2950 int next_tick
= DE4X5_AUTOSENSE_MS
;
2952 switch (lp
->media
) {
2954 if (lp
->timeout
< 0) {
2956 lp
->tx_enable
= false;
2959 de4x5_save_skbs(dev
); /* Save non transmitted skb's */
2960 if (lp
->params
.autosense
& ~AUTO
) {
2961 srom_map_media(dev
); /* Fixed media requested */
2962 if (lp
->media
!= lp
->params
.autosense
) {
2970 if ((next_tick
= de4x5_reset_phy(dev
)) < 0) {
2971 next_tick
&= ~TIMER_CB
;
2973 if (lp
->autosense
== _100Mb
) {
2975 } else if (lp
->autosense
== _10Mb
) {
2977 } else if (lp
->autosense
== TP
) {
2979 } else if (lp
->autosense
== BNC
) {
2981 } else if (lp
->autosense
== AUI
) {
2984 lp
->media
= SPD_DET
;
2985 if ((lp
->infoblock_media
== ANS
) &&
2986 ((sr
=is_anc_capable(dev
)) & MII_SR_ANC
)) {
2987 ana
= (((sr
>> 6) & MII_ANA_TAF
) | MII_ANA_CSMA
);
2988 ana
&= (lp
->fdx
? ~0 : ~MII_ANA_FDAM
);
2989 mii_wr(ana
, MII_ANA
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
2993 lp
->local_state
= 0;
2994 next_tick
= dc2114x_autoconf(dev
);
2999 switch (lp
->local_state
) {
3001 if (lp
->timeout
< 0) {
3002 mii_wr(MII_CR_ASSE
| MII_CR_RAN
, MII_CR
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
3004 cr
= test_mii_reg(dev
, MII_CR
, MII_CR_RAN
, false, 500);
3006 next_tick
= cr
& ~TIMER_CB
;
3009 lp
->local_state
= 0;
3010 lp
->media
= SPD_DET
;
3014 next_tick
= dc2114x_autoconf(dev
);
3019 sr
= test_mii_reg(dev
, MII_SR
, MII_SR_ASSC
, true, 2000);
3021 next_tick
= sr
& ~TIMER_CB
;
3023 lp
->media
= SPD_DET
;
3024 lp
->local_state
= 0;
3025 if (sr
) { /* Success! */
3026 lp
->tmp
= MII_SR_ASSC
;
3027 anlpa
= mii_rd(MII_ANLPA
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
3028 ana
= mii_rd(MII_ANA
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
3029 if (!(anlpa
& MII_ANLPA_RF
) &&
3030 (cap
= anlpa
& MII_ANLPA_TAF
& ana
)) {
3031 if (cap
& MII_ANA_100M
) {
3032 lp
->fdx
= (ana
& anlpa
& MII_ANA_FDAM
& MII_ANA_100M
) != 0;
3034 } else if (cap
& MII_ANA_10M
) {
3035 lp
->fdx
= (ana
& anlpa
& MII_ANA_FDAM
& MII_ANA_10M
) != 0;
3039 } /* Auto Negotiation failed to finish */
3040 next_tick
= dc2114x_autoconf(dev
);
3041 } /* Auto Negotiation failed to start */
3047 if (!lp
->tx_enable
) {
3048 if (lp
->timeout
< 0) {
3049 omr
= inl(DE4X5_OMR
); /* Set up half duplex for AUI */
3050 outl(omr
& ~OMR_FDX
, DE4X5_OMR
);
3054 sts
= test_media(dev
,irqs
, irq_mask
, 0, 0, 0, 1000);
3056 next_tick
= sts
& ~TIMER_CB
;
3058 if (!(inl(DE4X5_SISR
) & SISR_SRA
) && (lp
->autosense
== AUTO
)) {
3060 next_tick
= dc2114x_autoconf(dev
);
3062 lp
->local_state
= 1;
3063 de4x5_init_connection(dev
);
3066 } else if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
3067 lp
->media
= AUI_SUSPECT
;
3073 next_tick
= de4x5_suspect_state(dev
, 1000, AUI
, ping_media
, dc2114x_autoconf
);
3077 switch (lp
->local_state
) {
3079 if (lp
->timeout
< 0) {
3080 omr
= inl(DE4X5_OMR
); /* Set up half duplex for BNC */
3081 outl(omr
& ~OMR_FDX
, DE4X5_OMR
);
3085 sts
= test_media(dev
,irqs
, irq_mask
, 0, 0, 0, 1000);
3087 next_tick
= sts
& ~TIMER_CB
;
3089 lp
->local_state
++; /* Ensure media connected */
3090 next_tick
= dc2114x_autoconf(dev
);
3095 if (!lp
->tx_enable
) {
3096 if ((sts
= ping_media(dev
, 3000)) < 0) {
3097 next_tick
= sts
& ~TIMER_CB
;
3100 lp
->local_state
= 0;
3104 de4x5_init_connection(dev
);
3107 } else if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
3108 lp
->media
= BNC_SUSPECT
;
3116 next_tick
= de4x5_suspect_state(dev
, 1000, BNC
, ping_media
, dc2114x_autoconf
);
3119 case SPD_DET
: /* Choose 10Mb/s or 100Mb/s */
3120 if (srom_map_media(dev
) < 0) {
3125 if (lp
->media
== _100Mb
) {
3126 if ((slnk
= test_for_100Mb(dev
, 6500)) < 0) {
3127 lp
->media
= SPD_DET
;
3128 return (slnk
& ~TIMER_CB
);
3131 if (wait_for_link(dev
) < 0) {
3132 lp
->media
= SPD_DET
;
3133 return PDET_LINK_WAIT
;
3136 if (lp
->media
== ANS
) { /* Do MII parallel detection */
3137 if (is_spd_100(dev
)) {
3142 next_tick
= dc2114x_autoconf(dev
);
3143 } else if (((lp
->media
== _100Mb
) && is_100_up(dev
)) ||
3144 (((lp
->media
== _10Mb
) || (lp
->media
== TP
) ||
3145 (lp
->media
== BNC
) || (lp
->media
== AUI
)) &&
3147 next_tick
= dc2114x_autoconf(dev
);
3156 if (!lp
->tx_enable
) {
3158 de4x5_init_connection(dev
);
3160 if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
3161 if (!is_10_up(dev
) || (!lp
->useSROM
&& is_spd_100(dev
))) {
3164 next_tick
= DE4X5_AUTOSENSE_MS
;
3172 if (!lp
->tx_enable
) {
3174 de4x5_init_connection(dev
);
3176 if (!lp
->linkOK
&& (lp
->autosense
== AUTO
)) {
3177 if (!is_100_up(dev
) || (!lp
->useSROM
&& !is_spd_100(dev
))) {
3180 next_tick
= DE4X5_AUTOSENSE_MS
;
3188 printk("Huh?: media:%02x\n", lp
->media
);
3197 srom_autoconf(struct net_device
*dev
)
3199 struct de4x5_private
*lp
= netdev_priv(dev
);
3201 return lp
->infoleaf_fn(dev
);
3205 ** This mapping keeps the original media codes and FDX flag unchanged.
3206 ** While it isn't strictly necessary, it helps me for the moment...
3207 ** The early return avoids a media state / SROM media space clash.
3210 srom_map_media(struct net_device
*dev
)
3212 struct de4x5_private
*lp
= netdev_priv(dev
);
3215 if (lp
->infoblock_media
== lp
->media
)
3218 switch(lp
->infoblock_media
) {
3220 if (!lp
->params
.fdx
) return -1;
3223 if (lp
->params
.fdx
&& !lp
->fdx
) return -1;
3224 if ((lp
->chipset
== DC21140
) || ((lp
->chipset
& ~0x00ff) == DC2114x
)) {
3239 case SROM_100BASETF
:
3240 if (!lp
->params
.fdx
) return -1;
3243 if (lp
->params
.fdx
&& !lp
->fdx
) return -1;
3247 case SROM_100BASET4
:
3251 case SROM_100BASEFF
:
3252 if (!lp
->params
.fdx
) return -1;
3255 if (lp
->params
.fdx
&& !lp
->fdx
) return -1;
3261 lp
->fdx
= lp
->params
.fdx
;
3265 printk("%s: Bad media code [%d] detected in SROM!\n", dev
->name
,
3266 lp
->infoblock_media
);
3275 de4x5_init_connection(struct net_device
*dev
)
3277 struct de4x5_private
*lp
= netdev_priv(dev
);
3278 u_long iobase
= dev
->base_addr
;
3281 if (lp
->media
!= lp
->c_media
) {
3282 de4x5_dbg_media(dev
);
3283 lp
->c_media
= lp
->media
; /* Stop scrolling media messages */
3286 spin_lock_irqsave(&lp
->lock
, flags
);
3287 de4x5_rst_desc_ring(dev
);
3288 de4x5_setup_intr(dev
);
3289 lp
->tx_enable
= true;
3290 spin_unlock_irqrestore(&lp
->lock
, flags
);
3291 outl(POLL_DEMAND
, DE4X5_TPD
);
3293 netif_wake_queue(dev
);
3299 ** General PHY reset function. Some MII devices don't reset correctly
3300 ** since their MII address pins can float at voltages that are dependent
3301 ** on the signal pin use. Do a double reset to ensure a reset.
3304 de4x5_reset_phy(struct net_device
*dev
)
3306 struct de4x5_private
*lp
= netdev_priv(dev
);
3307 u_long iobase
= dev
->base_addr
;
3310 if ((lp
->useSROM
) || (lp
->phy
[lp
->active
].id
)) {
3311 if (lp
->timeout
< 0) {
3313 if (lp
->phy
[lp
->active
].rst
) {
3314 srom_exec(dev
, lp
->phy
[lp
->active
].rst
);
3315 srom_exec(dev
, lp
->phy
[lp
->active
].rst
);
3316 } else if (lp
->rst
) { /* Type 5 infoblock reset */
3317 srom_exec(dev
, lp
->rst
);
3318 srom_exec(dev
, lp
->rst
);
3324 mii_wr(MII_CR_RST
, MII_CR
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
3328 next_tick
= test_mii_reg(dev
, MII_CR
, MII_CR_RST
, false, 500);
3330 } else if (lp
->chipset
== DC21140
) {
3338 test_media(struct net_device
*dev
, s32 irqs
, s32 irq_mask
, s32 csr13
, s32 csr14
, s32 csr15
, s32 msec
)
3340 struct de4x5_private
*lp
= netdev_priv(dev
);
3341 u_long iobase
= dev
->base_addr
;
3344 if (lp
->timeout
< 0) {
3345 lp
->timeout
= msec
/100;
3346 if (!lp
->useSROM
) { /* Already done if by SROM, else dc2104[01] */
3347 reset_init_sia(dev
, csr13
, csr14
, csr15
);
3350 /* set up the interrupt mask */
3351 outl(irq_mask
, DE4X5_IMR
);
3353 /* clear all pending interrupts */
3354 sts
= inl(DE4X5_STS
);
3355 outl(sts
, DE4X5_STS
);
3357 /* clear csr12 NRA and SRA bits */
3358 if ((lp
->chipset
== DC21041
) || lp
->useSROM
) {
3359 csr12
= inl(DE4X5_SISR
);
3360 outl(csr12
, DE4X5_SISR
);
3364 sts
= inl(DE4X5_STS
) & ~TIMER_CB
;
3366 if (!(sts
& irqs
) && --lp
->timeout
) {
3367 sts
= 100 | TIMER_CB
;
3376 test_tp(struct net_device
*dev
, s32 msec
)
3378 struct de4x5_private
*lp
= netdev_priv(dev
);
3379 u_long iobase
= dev
->base_addr
;
3382 if (lp
->timeout
< 0) {
3383 lp
->timeout
= msec
/100;
3386 sisr
= (inl(DE4X5_SISR
) & ~TIMER_CB
) & (SISR_LKF
| SISR_NCR
);
3388 if (sisr
&& --lp
->timeout
) {
3389 sisr
= 100 | TIMER_CB
;
3398 ** Samples the 100Mb Link State Signal. The sample interval is important
3399 ** because too fast a rate can give erroneous results and confuse the
3400 ** speed sense algorithm.
3402 #define SAMPLE_INTERVAL 500 /* ms */
3403 #define SAMPLE_DELAY 2000 /* ms */
3405 test_for_100Mb(struct net_device
*dev
, int msec
)
3407 struct de4x5_private
*lp
= netdev_priv(dev
);
3408 int gep
= 0, ret
= ((lp
->chipset
& ~0x00ff)==DC2114x
? -1 :GEP_SLNK
);
3410 if (lp
->timeout
< 0) {
3411 if ((msec
/SAMPLE_INTERVAL
) <= 0) return 0;
3412 if (msec
> SAMPLE_DELAY
) {
3413 lp
->timeout
= (msec
- SAMPLE_DELAY
)/SAMPLE_INTERVAL
;
3414 gep
= SAMPLE_DELAY
| TIMER_CB
;
3417 lp
->timeout
= msec
/SAMPLE_INTERVAL
;
3421 if (lp
->phy
[lp
->active
].id
|| lp
->useSROM
) {
3422 gep
= is_100_up(dev
) | is_spd_100(dev
);
3424 gep
= (~gep_rd(dev
) & (GEP_SLNK
| GEP_LNP
));
3426 if (!(gep
& ret
) && --lp
->timeout
) {
3427 gep
= SAMPLE_INTERVAL
| TIMER_CB
;
3436 wait_for_link(struct net_device
*dev
)
3438 struct de4x5_private
*lp
= netdev_priv(dev
);
3440 if (lp
->timeout
< 0) {
3444 if (lp
->timeout
--) {
3458 test_mii_reg(struct net_device
*dev
, int reg
, int mask
, bool pol
, long msec
)
3460 struct de4x5_private
*lp
= netdev_priv(dev
);
3462 u_long iobase
= dev
->base_addr
;
3464 if (lp
->timeout
< 0) {
3465 lp
->timeout
= msec
/100;
3468 reg
= mii_rd((u_char
)reg
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
) & mask
;
3469 test
= (reg
^ (pol
? ~0 : 0)) & mask
;
3471 if (test
&& --lp
->timeout
) {
3472 reg
= 100 | TIMER_CB
;
3481 is_spd_100(struct net_device
*dev
)
3483 struct de4x5_private
*lp
= netdev_priv(dev
);
3484 u_long iobase
= dev
->base_addr
;
3488 spd
= mii_rd(lp
->phy
[lp
->active
].spd
.reg
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
3489 spd
= ~(spd
^ lp
->phy
[lp
->active
].spd
.value
);
3490 spd
&= lp
->phy
[lp
->active
].spd
.mask
;
3491 } else if (!lp
->useSROM
) { /* de500-xa */
3492 spd
= ((~gep_rd(dev
)) & GEP_SLNK
);
3494 if ((lp
->ibn
== 2) || !lp
->asBitValid
)
3495 return ((lp
->chipset
== DC21143
)?(~inl(DE4X5_SISR
)&SISR_LS100
):0);
3497 spd
= (lp
->asBitValid
& (lp
->asPolarity
^ (gep_rd(dev
) & lp
->asBit
))) |
3498 (lp
->linkOK
& ~lp
->asBitValid
);
3505 is_100_up(struct net_device
*dev
)
3507 struct de4x5_private
*lp
= netdev_priv(dev
);
3508 u_long iobase
= dev
->base_addr
;
3511 /* Double read for sticky bits & temporary drops */
3512 mii_rd(MII_SR
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
3513 return (mii_rd(MII_SR
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
) & MII_SR_LKS
);
3514 } else if (!lp
->useSROM
) { /* de500-xa */
3515 return ((~gep_rd(dev
)) & GEP_SLNK
);
3517 if ((lp
->ibn
== 2) || !lp
->asBitValid
)
3518 return ((lp
->chipset
== DC21143
)?(~inl(DE4X5_SISR
)&SISR_LS100
):0);
3520 return ((lp
->asBitValid
&(lp
->asPolarity
^(gep_rd(dev
)&lp
->asBit
))) |
3521 (lp
->linkOK
& ~lp
->asBitValid
));
3526 is_10_up(struct net_device
*dev
)
3528 struct de4x5_private
*lp
= netdev_priv(dev
);
3529 u_long iobase
= dev
->base_addr
;
3532 /* Double read for sticky bits & temporary drops */
3533 mii_rd(MII_SR
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
);
3534 return (mii_rd(MII_SR
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
) & MII_SR_LKS
);
3535 } else if (!lp
->useSROM
) { /* de500-xa */
3536 return ((~gep_rd(dev
)) & GEP_LNP
);
3538 if ((lp
->ibn
== 2) || !lp
->asBitValid
)
3539 return (((lp
->chipset
& ~0x00ff) == DC2114x
) ?
3540 (~inl(DE4X5_SISR
)&SISR_LS10
):
3543 return ((lp
->asBitValid
&(lp
->asPolarity
^(gep_rd(dev
)&lp
->asBit
))) |
3544 (lp
->linkOK
& ~lp
->asBitValid
));
3549 is_anc_capable(struct net_device
*dev
)
3551 struct de4x5_private
*lp
= netdev_priv(dev
);
3552 u_long iobase
= dev
->base_addr
;
3554 if (lp
->phy
[lp
->active
].id
&& (!lp
->useSROM
|| lp
->useMII
)) {
3555 return (mii_rd(MII_SR
, lp
->phy
[lp
->active
].addr
, DE4X5_MII
));
3556 } else if ((lp
->chipset
& ~0x00ff) == DC2114x
) {
3557 return (inl(DE4X5_SISR
) & SISR_LPN
) >> 12;
3564 ** Send a packet onto the media and watch for send errors that indicate the
3565 ** media is bad or unconnected.
3568 ping_media(struct net_device
*dev
, int msec
)
3570 struct de4x5_private
*lp
= netdev_priv(dev
);
3571 u_long iobase
= dev
->base_addr
;
3574 if (lp
->timeout
< 0) {
3575 lp
->timeout
= msec
/100;
3577 lp
->tmp
= lp
->tx_new
; /* Remember the ring position */
3578 load_packet(dev
, lp
->frame
, TD_LS
| TD_FS
| sizeof(lp
->frame
), (struct sk_buff
*)1);
3579 lp
->tx_new
= (++lp
->tx_new
) % lp
->txRingSize
;
3580 outl(POLL_DEMAND
, DE4X5_TPD
);
3583 sisr
= inl(DE4X5_SISR
);
3585 if ((!(sisr
& SISR_NCR
)) &&
3586 ((s32
)le32_to_cpu(lp
->tx_ring
[lp
->tmp
].status
) < 0) &&
3588 sisr
= 100 | TIMER_CB
;
3590 if ((!(sisr
& SISR_NCR
)) &&
3591 !(le32_to_cpu(lp
->tx_ring
[lp
->tmp
].status
) & (T_OWN
| TD_ES
)) &&
3604 ** This function does 2 things: on Intels it kmalloc's another buffer to
3605 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3606 ** into which the packet is copied.
3608 static struct sk_buff
*
3609 de4x5_alloc_rx_buff(struct net_device
*dev
, int index
, int len
)
3611 struct de4x5_private
*lp
= netdev_priv(dev
);
3614 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3615 struct sk_buff
*ret
;
3618 p
= dev_alloc_skb(IEEE802_3_SZ
+ DE4X5_ALIGN
+ 2);
3619 if (!p
) return NULL
;
3621 tmp
= virt_to_bus(p
->data
);
3622 i
= ((tmp
+ DE4X5_ALIGN
) & ~DE4X5_ALIGN
) - tmp
;
3624 lp
->rx_ring
[index
].buf
= cpu_to_le32(tmp
+ i
);
3626 ret
= lp
->rx_skb
[index
];
3627 lp
->rx_skb
[index
] = p
;
3629 if ((u_long
) ret
> 1) {
3636 if (lp
->state
!= OPEN
) return (struct sk_buff
*)1; /* Fake out the open */
3638 p
= dev_alloc_skb(len
+ 2);
3639 if (!p
) return NULL
;
3641 skb_reserve(p
, 2); /* Align */
3642 if (index
< lp
->rx_old
) { /* Wrapped buffer */
3643 short tlen
= (lp
->rxRingSize
- lp
->rx_old
) * RX_BUFF_SZ
;
3644 memcpy(skb_put(p
,tlen
),lp
->rx_bufs
+ lp
->rx_old
* RX_BUFF_SZ
,tlen
);
3645 memcpy(skb_put(p
,len
-tlen
),lp
->rx_bufs
,len
-tlen
);
3646 } else { /* Linear buffer */
3647 memcpy(skb_put(p
,len
),lp
->rx_bufs
+ lp
->rx_old
* RX_BUFF_SZ
,len
);
3655 de4x5_free_rx_buffs(struct net_device
*dev
)
3657 struct de4x5_private
*lp
= netdev_priv(dev
);
3660 for (i
=0; i
<lp
->rxRingSize
; i
++) {
3661 if ((u_long
) lp
->rx_skb
[i
] > 1) {
3662 dev_kfree_skb(lp
->rx_skb
[i
]);
3664 lp
->rx_ring
[i
].status
= 0;
3665 lp
->rx_skb
[i
] = (struct sk_buff
*)1; /* Dummy entry */
3672 de4x5_free_tx_buffs(struct net_device
*dev
)
3674 struct de4x5_private
*lp
= netdev_priv(dev
);
3677 for (i
=0; i
<lp
->txRingSize
; i
++) {
3679 de4x5_free_tx_buff(lp
, i
);
3680 lp
->tx_ring
[i
].status
= 0;
3683 /* Unload the locally queued packets */
3684 __skb_queue_purge(&lp
->cache
.queue
);
3688 ** When a user pulls a connection, the DECchip can end up in a
3689 ** 'running - waiting for end of transmission' state. This means that we
3690 ** have to perform a chip soft reset to ensure that we can synchronize
3691 ** the hardware and software and make any media probes using a loopback
3692 ** packet meaningful.
3695 de4x5_save_skbs(struct net_device
*dev
)
3697 struct de4x5_private
*lp
= netdev_priv(dev
);
3698 u_long iobase
= dev
->base_addr
;
3701 if (!lp
->cache
.save_cnt
) {
3703 de4x5_tx(dev
); /* Flush any sent skb's */
3704 de4x5_free_tx_buffs(dev
);
3705 de4x5_cache_state(dev
, DE4X5_SAVE_STATE
);
3706 de4x5_sw_reset(dev
);
3707 de4x5_cache_state(dev
, DE4X5_RESTORE_STATE
);
3708 lp
->cache
.save_cnt
++;
3716 de4x5_rst_desc_ring(struct net_device
*dev
)
3718 struct de4x5_private
*lp
= netdev_priv(dev
);
3719 u_long iobase
= dev
->base_addr
;
3723 if (lp
->cache
.save_cnt
) {
3725 outl(lp
->dma_rings
, DE4X5_RRBA
);
3726 outl(lp
->dma_rings
+ NUM_RX_DESC
* sizeof(struct de4x5_desc
),
3729 lp
->rx_new
= lp
->rx_old
= 0;
3730 lp
->tx_new
= lp
->tx_old
= 0;
3732 for (i
= 0; i
< lp
->rxRingSize
; i
++) {
3733 lp
->rx_ring
[i
].status
= cpu_to_le32(R_OWN
);
3736 for (i
= 0; i
< lp
->txRingSize
; i
++) {
3737 lp
->tx_ring
[i
].status
= cpu_to_le32(0);
3741 lp
->cache
.save_cnt
--;
3749 de4x5_cache_state(struct net_device
*dev
, int flag
)
3751 struct de4x5_private
*lp
= netdev_priv(dev
);
3752 u_long iobase
= dev
->base_addr
;
3755 case DE4X5_SAVE_STATE
:
3756 lp
->cache
.csr0
= inl(DE4X5_BMR
);
3757 lp
->cache
.csr6
= (inl(DE4X5_OMR
) & ~(OMR_ST
| OMR_SR
));
3758 lp
->cache
.csr7
= inl(DE4X5_IMR
);
3761 case DE4X5_RESTORE_STATE
:
3762 outl(lp
->cache
.csr0
, DE4X5_BMR
);
3763 outl(lp
->cache
.csr6
, DE4X5_OMR
);
3764 outl(lp
->cache
.csr7
, DE4X5_IMR
);
3765 if (lp
->chipset
== DC21140
) {
3766 gep_wr(lp
->cache
.gepc
, dev
);
3767 gep_wr(lp
->cache
.gep
, dev
);
3769 reset_init_sia(dev
, lp
->cache
.csr13
, lp
->cache
.csr14
,
3779 de4x5_put_cache(struct net_device
*dev
, struct sk_buff
*skb
)
3781 struct de4x5_private
*lp
= netdev_priv(dev
);
3783 __skb_queue_tail(&lp
->cache
.queue
, skb
);
3787 de4x5_putb_cache(struct net_device
*dev
, struct sk_buff
*skb
)
3789 struct de4x5_private
*lp
= netdev_priv(dev
);
3791 __skb_queue_head(&lp
->cache
.queue
, skb
);
3794 static struct sk_buff
*
3795 de4x5_get_cache(struct net_device
*dev
)
3797 struct de4x5_private
*lp
= netdev_priv(dev
);
3799 return __skb_dequeue(&lp
->cache
.queue
);
3803 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3804 ** is received and the auto-negotiation status is NWAY OK.
3807 test_ans(struct net_device
*dev
, s32 irqs
, s32 irq_mask
, s32 msec
)
3809 struct de4x5_private
*lp
= netdev_priv(dev
);
3810 u_long iobase
= dev
->base_addr
;
3813 if (lp
->timeout
< 0) {
3814 lp
->timeout
= msec
/100;
3815 outl(irq_mask
, DE4X5_IMR
);
3817 /* clear all pending interrupts */
3818 sts
= inl(DE4X5_STS
);
3819 outl(sts
, DE4X5_STS
);
3822 ans
= inl(DE4X5_SISR
) & SISR_ANS
;
3823 sts
= inl(DE4X5_STS
) & ~TIMER_CB
;
3825 if (!(sts
& irqs
) && (ans
^ ANS_NWOK
) && --lp
->timeout
) {
3826 sts
= 100 | TIMER_CB
;
3835 de4x5_setup_intr(struct net_device
*dev
)
3837 struct de4x5_private
*lp
= netdev_priv(dev
);
3838 u_long iobase
= dev
->base_addr
;
3841 if (inl(DE4X5_OMR
) & OMR_SR
) { /* Only unmask if TX/RX is enabled */
3844 sts
= inl(DE4X5_STS
); /* Reset any pending (stale) interrupts */
3845 outl(sts
, DE4X5_STS
);
3856 reset_init_sia(struct net_device
*dev
, s32 csr13
, s32 csr14
, s32 csr15
)
3858 struct de4x5_private
*lp
= netdev_priv(dev
);
3859 u_long iobase
= dev
->base_addr
;
3864 srom_exec(dev
, lp
->phy
[lp
->active
].rst
);
3865 srom_exec(dev
, lp
->phy
[lp
->active
].gep
);
3866 outl(1, DE4X5_SICR
);
3869 csr15
= lp
->cache
.csr15
;
3870 csr14
= lp
->cache
.csr14
;
3871 csr13
= lp
->cache
.csr13
;
3872 outl(csr15
| lp
->cache
.gepc
, DE4X5_SIGR
);
3873 outl(csr15
| lp
->cache
.gep
, DE4X5_SIGR
);
3876 outl(csr15
, DE4X5_SIGR
);
3878 outl(csr14
, DE4X5_STRR
);
3879 outl(csr13
, DE4X5_SICR
);
3887 ** Create a loopback ethernet packet
3890 create_packet(struct net_device
*dev
, char *frame
, int len
)
3895 for (i
=0; i
<ETH_ALEN
; i
++) { /* Use this source address */
3896 *buf
++ = dev
->dev_addr
[i
];
3898 for (i
=0; i
<ETH_ALEN
; i
++) { /* Use this destination address */
3899 *buf
++ = dev
->dev_addr
[i
];
3902 *buf
++ = 0; /* Packet length (2 bytes) */
3909 ** Look for a particular board name in the EISA configuration space
3912 EISA_signature(char *name
, struct device
*device
)
3914 int i
, status
= 0, siglen
= ARRAY_SIZE(de4x5_signatures
);
3915 struct eisa_device
*edev
;
3918 edev
= to_eisa_device (device
);
3919 i
= edev
->id
.driver_data
;
3921 if (i
>= 0 && i
< siglen
) {
3922 strcpy (name
, de4x5_signatures
[i
]);
3926 return status
; /* return the device name string */
3930 ** Look for a particular board name in the PCI configuration space
3933 PCI_signature(char *name
, struct de4x5_private
*lp
)
3935 int i
, status
= 0, siglen
= ARRAY_SIZE(de4x5_signatures
);
3937 if (lp
->chipset
== DC21040
) {
3938 strcpy(name
, "DE434/5");
3940 } else { /* Search for a DEC name in the SROM */
3941 int tmp
= *((char *)&lp
->srom
+ 19) * 3;
3942 strncpy(name
, (char *)&lp
->srom
+ 26 + tmp
, 8);
3945 for (i
=0; i
<siglen
; i
++) {
3946 if (strstr(name
,de4x5_signatures
[i
])!=NULL
) break;
3951 } else { /* Use chip name to avoid confusion */
3952 strcpy(name
, (((lp
->chipset
== DC21040
) ? "DC21040" :
3953 ((lp
->chipset
== DC21041
) ? "DC21041" :
3954 ((lp
->chipset
== DC21140
) ? "DC21140" :
3955 ((lp
->chipset
== DC21142
) ? "DC21142" :
3956 ((lp
->chipset
== DC21143
) ? "DC21143" : "UNKNOWN"
3959 if (lp
->chipset
!= DC21041
) {
3960 lp
->useSROM
= true; /* card is not recognisably DEC */
3962 } else if ((lp
->chipset
& ~0x00ff) == DC2114x
) {
3970 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
3971 ** the DC21040, else read the SROM for the other chips.
3972 ** The SROM may not be present in a multi-MAC card, so first read the
3973 ** MAC address and check for a bad address. If there is a bad one then exit
3974 ** immediately with the prior srom contents intact (the h/w address will
3975 ** be fixed up later).
3978 DevicePresent(struct net_device
*dev
, u_long aprom_addr
)
3981 struct de4x5_private
*lp
= netdev_priv(dev
);
3983 if (lp
->chipset
== DC21040
) {
3984 if (lp
->bus
== EISA
) {
3985 enet_addr_rst(aprom_addr
); /* Reset Ethernet Address ROM Pointer */
3987 outl(0, aprom_addr
); /* Reset Ethernet Address ROM Pointer */
3989 } else { /* Read new srom */
3991 __le16
*p
= (__le16
*)((char *)&lp
->srom
+ SROM_HWADD
);
3992 for (i
=0; i
<(ETH_ALEN
>>1); i
++) {
3993 tmp
= srom_rd(aprom_addr
, (SROM_HWADD
>>1) + i
);
3994 j
+= tmp
; /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3995 *p
= cpu_to_le16(tmp
);
3997 if (j
== 0 || j
== 3 * 0xffff) {
3998 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
4002 p
= (__le16
*)&lp
->srom
;
4003 for (i
=0; i
<(sizeof(struct de4x5_srom
)>>1); i
++) {
4004 tmp
= srom_rd(aprom_addr
, i
);
4005 *p
++ = cpu_to_le16(tmp
);
4007 de4x5_dbg_srom((struct de4x5_srom
*)&lp
->srom
);
4014 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4015 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4016 ** it...from depca.c.
4019 enet_addr_rst(u_long aprom_addr
)
4026 char Sig
[sizeof(u32
) << 1];
4032 dev
.llsig
.a
= ETH_PROM_SIG
;
4033 dev
.llsig
.b
= ETH_PROM_SIG
;
4034 sigLength
= sizeof(u32
) << 1;
4036 for (i
=0,j
=0;j
<sigLength
&& i
<PROBE_LENGTH
+sigLength
-1;i
++) {
4037 data
= inb(aprom_addr
);
4038 if (dev
.Sig
[j
] == data
) { /* track signature */
4040 } else { /* lost signature; begin search again */
4041 if (data
== dev
.Sig
[0]) { /* rare case.... */
4053 ** For the bad status case and no SROM, then add one to the previous
4054 ** address. However, need to add one backwards in case we have 0xff
4055 ** as one or more of the bytes. Only the last 3 bytes should be checked
4056 ** as the first three are invariant - assigned to an organisation.
4059 get_hw_addr(struct net_device
*dev
)
4061 u_long iobase
= dev
->base_addr
;
4062 int broken
, i
, k
, tmp
, status
= 0;
4064 struct de4x5_private
*lp
= netdev_priv(dev
);
4066 broken
= de4x5_bad_srom(lp
);
4068 for (i
=0,k
=0,j
=0;j
<3;j
++) {
4070 if (k
> 0xffff) k
-=0xffff;
4072 if (lp
->bus
== PCI
) {
4073 if (lp
->chipset
== DC21040
) {
4074 while ((tmp
= inl(DE4X5_APROM
)) < 0);
4076 dev
->dev_addr
[i
++] = (u_char
) tmp
;
4077 while ((tmp
= inl(DE4X5_APROM
)) < 0);
4078 k
+= (u_short
) (tmp
<< 8);
4079 dev
->dev_addr
[i
++] = (u_char
) tmp
;
4080 } else if (!broken
) {
4081 dev
->dev_addr
[i
] = (u_char
) lp
->srom
.ieee_addr
[i
]; i
++;
4082 dev
->dev_addr
[i
] = (u_char
) lp
->srom
.ieee_addr
[i
]; i
++;
4083 } else if ((broken
== SMC
) || (broken
== ACCTON
)) {
4084 dev
->dev_addr
[i
] = *((u_char
*)&lp
->srom
+ i
); i
++;
4085 dev
->dev_addr
[i
] = *((u_char
*)&lp
->srom
+ i
); i
++;
4088 k
+= (u_char
) (tmp
= inb(EISA_APROM
));
4089 dev
->dev_addr
[i
++] = (u_char
) tmp
;
4090 k
+= (u_short
) ((tmp
= inb(EISA_APROM
)) << 8);
4091 dev
->dev_addr
[i
++] = (u_char
) tmp
;
4094 if (k
> 0xffff) k
-=0xffff;
4096 if (k
== 0xffff) k
=0;
4098 if (lp
->bus
== PCI
) {
4099 if (lp
->chipset
== DC21040
) {
4100 while ((tmp
= inl(DE4X5_APROM
)) < 0);
4101 chksum
= (u_char
) tmp
;
4102 while ((tmp
= inl(DE4X5_APROM
)) < 0);
4103 chksum
|= (u_short
) (tmp
<< 8);
4104 if ((k
!= chksum
) && (dec_only
)) status
= -1;
4107 chksum
= (u_char
) inb(EISA_APROM
);
4108 chksum
|= (u_short
) (inb(EISA_APROM
) << 8);
4109 if ((k
!= chksum
) && (dec_only
)) status
= -1;
4112 /* If possible, try to fix a broken card - SMC only so far */
4113 srom_repair(dev
, broken
);
4115 #ifdef CONFIG_PPC_PMAC
4117 ** If the address starts with 00 a0, we have to bit-reverse
4118 ** each byte of the address.
4120 if ( machine_is(powermac
) &&
4121 (dev
->dev_addr
[0] == 0) &&
4122 (dev
->dev_addr
[1] == 0xa0) )
4124 for (i
= 0; i
< ETH_ALEN
; ++i
)
4126 int x
= dev
->dev_addr
[i
];
4127 x
= ((x
& 0xf) << 4) + ((x
& 0xf0) >> 4);
4128 x
= ((x
& 0x33) << 2) + ((x
& 0xcc) >> 2);
4129 dev
->dev_addr
[i
] = ((x
& 0x55) << 1) + ((x
& 0xaa) >> 1);
4132 #endif /* CONFIG_PPC_PMAC */
4134 /* Test for a bad enet address */
4135 status
= test_bad_enet(dev
, status
);
4141 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4142 ** didn't seem to work here...?
4145 de4x5_bad_srom(struct de4x5_private
*lp
)
4149 for (i
= 0; i
< ARRAY_SIZE(enet_det
); i
++) {
4150 if (!de4x5_strncmp((char *)&lp
->srom
, (char *)&enet_det
[i
], 3) &&
4151 !de4x5_strncmp((char *)&lp
->srom
+0x10, (char *)&enet_det
[i
], 3)) {
4154 } else if (i
== 1) {
4165 de4x5_strncmp(char *a
, char *b
, int n
)
4169 for (;n
&& !ret
; n
--) {
4177 srom_repair(struct net_device
*dev
, int card
)
4179 struct de4x5_private
*lp
= netdev_priv(dev
);
4183 memset((char *)&lp
->srom
, 0, sizeof(struct de4x5_srom
));
4184 memcpy(lp
->srom
.ieee_addr
, (char *)dev
->dev_addr
, ETH_ALEN
);
4185 memcpy(lp
->srom
.info
, (char *)&srom_repair_info
[SMC
-1], 100);
4194 ** Assume that the irq's do not follow the PCI spec - this is seems
4195 ** to be true so far (2 for 2).
4198 test_bad_enet(struct net_device
*dev
, int status
)
4200 struct de4x5_private
*lp
= netdev_priv(dev
);
4203 for (tmp
=0,i
=0; i
<ETH_ALEN
; i
++) tmp
+= (u_char
)dev
->dev_addr
[i
];
4204 if ((tmp
== 0) || (tmp
== 0x5fa)) {
4205 if ((lp
->chipset
== last
.chipset
) &&
4206 (lp
->bus_num
== last
.bus
) && (lp
->bus_num
> 0)) {
4207 for (i
=0; i
<ETH_ALEN
; i
++) dev
->dev_addr
[i
] = last
.addr
[i
];
4208 for (i
=ETH_ALEN
-1; i
>2; --i
) {
4209 dev
->dev_addr
[i
] += 1;
4210 if (dev
->dev_addr
[i
] != 0) break;
4212 for (i
=0; i
<ETH_ALEN
; i
++) last
.addr
[i
] = dev
->dev_addr
[i
];
4213 if (!an_exception(lp
)) {
4214 dev
->irq
= last
.irq
;
4219 } else if (!status
) {
4220 last
.chipset
= lp
->chipset
;
4221 last
.bus
= lp
->bus_num
;
4222 last
.irq
= dev
->irq
;
4223 for (i
=0; i
<ETH_ALEN
; i
++) last
.addr
[i
] = dev
->dev_addr
[i
];
4230 ** List of board exceptions with correctly wired IRQs
4233 an_exception(struct de4x5_private
*lp
)
4235 if ((*(u_short
*)lp
->srom
.sub_vendor_id
== 0x00c0) &&
4236 (*(u_short
*)lp
->srom
.sub_system_id
== 0x95e0)) {
4247 srom_rd(u_long addr
, u_char offset
)
4249 sendto_srom(SROM_RD
| SROM_SR
, addr
);
4251 srom_latch(SROM_RD
| SROM_SR
| DT_CS
, addr
);
4252 srom_command(SROM_RD
| SROM_SR
| DT_IN
| DT_CS
, addr
);
4253 srom_address(SROM_RD
| SROM_SR
| DT_CS
, addr
, offset
);
4255 return srom_data(SROM_RD
| SROM_SR
| DT_CS
, addr
);
4259 srom_latch(u_int command
, u_long addr
)
4261 sendto_srom(command
, addr
);
4262 sendto_srom(command
| DT_CLK
, addr
);
4263 sendto_srom(command
, addr
);
4269 srom_command(u_int command
, u_long addr
)
4271 srom_latch(command
, addr
);
4272 srom_latch(command
, addr
);
4273 srom_latch((command
& 0x0000ff00) | DT_CS
, addr
);
4279 srom_address(u_int command
, u_long addr
, u_char offset
)
4284 for (i
=0; i
<6; i
++, a
<<= 1) {
4285 srom_latch(command
| ((a
& 0x80) ? DT_IN
: 0), addr
);
4289 i
= (getfrom_srom(addr
) >> 3) & 0x01;
4295 srom_data(u_int command
, u_long addr
)
4301 for (i
=0; i
<16; i
++) {
4302 sendto_srom(command
| DT_CLK
, addr
);
4303 tmp
= getfrom_srom(addr
);
4304 sendto_srom(command
, addr
);
4306 word
= (word
<< 1) | ((tmp
>> 3) & 0x01);
4309 sendto_srom(command
& 0x0000ff00, addr
);
4316 srom_busy(u_int command, u_long addr)
4318 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4320 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4324 sendto_srom(command & 0x0000ff00, addr);
4331 sendto_srom(u_int command
, u_long addr
)
4333 outl(command
, addr
);
4340 getfrom_srom(u_long addr
)
4351 srom_infoleaf_info(struct net_device
*dev
)
4353 struct de4x5_private
*lp
= netdev_priv(dev
);
4357 /* Find the infoleaf decoder function that matches this chipset */
4358 for (i
=0; i
<INFOLEAF_SIZE
; i
++) {
4359 if (lp
->chipset
== infoleaf_array
[i
].chipset
) break;
4361 if (i
== INFOLEAF_SIZE
) {
4362 lp
->useSROM
= false;
4363 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4368 lp
->infoleaf_fn
= infoleaf_array
[i
].fn
;
4370 /* Find the information offset that this function should use */
4371 count
= *((u_char
*)&lp
->srom
+ 19);
4372 p
= (u_char
*)&lp
->srom
+ 26;
4375 for (i
=count
; i
; --i
, p
+=3) {
4376 if (lp
->device
== *p
) break;
4379 lp
->useSROM
= false;
4380 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4381 dev
->name
, lp
->device
);
4386 lp
->infoleaf_offset
= get_unaligned_le16(p
+ 1);
4392 ** This routine loads any type 1 or 3 MII info into the mii device
4393 ** struct and executes any type 5 code to reset PHY devices for this
4395 ** The info for the MII devices will be valid since the index used
4396 ** will follow the discovery process from MII address 1-31 then 0.
4399 srom_init(struct net_device
*dev
)
4401 struct de4x5_private
*lp
= netdev_priv(dev
);
4402 u_char
*p
= (u_char
*)&lp
->srom
+ lp
->infoleaf_offset
;
4406 if (lp
->chipset
== DC21140
) {
4407 lp
->cache
.gepc
= (*p
++ | GEP_CTRL
);
4408 gep_wr(lp
->cache
.gepc
, dev
);
4414 /* Jump the infoblocks to find types */
4415 for (;count
; --count
) {
4418 } else if (*(p
+1) == 5) {
4419 type5_infoblock(dev
, 1, p
);
4420 p
+= ((*p
& BLOCK_LEN
) + 1);
4421 } else if (*(p
+1) == 4) {
4422 p
+= ((*p
& BLOCK_LEN
) + 1);
4423 } else if (*(p
+1) == 3) {
4424 type3_infoblock(dev
, 1, p
);
4425 p
+= ((*p
& BLOCK_LEN
) + 1);
4426 } else if (*(p
+1) == 2) {
4427 p
+= ((*p
& BLOCK_LEN
) + 1);
4428 } else if (*(p
+1) == 1) {
4429 type1_infoblock(dev
, 1, p
);
4430 p
+= ((*p
& BLOCK_LEN
) + 1);
4432 p
+= ((*p
& BLOCK_LEN
) + 1);
4440 ** A generic routine that writes GEP control, data and reset information
4441 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4444 srom_exec(struct net_device
*dev
, u_char
*p
)
4446 struct de4x5_private
*lp
= netdev_priv(dev
);
4447 u_long iobase
= dev
->base_addr
;
4448 u_char count
= (p
? *p
++ : 0);
4449 u_short
*w
= (u_short
*)p
;
4451 if (((lp
->ibn
!= 1) && (lp
->ibn
!= 3) && (lp
->ibn
!= 5)) || !count
) return;
4453 if (lp
->chipset
!= DC21140
) RESET_SIA
;
4456 gep_wr(((lp
->chipset
==DC21140
) && (lp
->ibn
!=5) ?
4457 *p
++ : get_unaligned_le16(w
++)), dev
);
4458 mdelay(2); /* 2ms per action */
4461 if (lp
->chipset
!= DC21140
) {
4462 outl(lp
->cache
.csr14
, DE4X5_STRR
);
4463 outl(lp
->cache
.csr13
, DE4X5_SICR
);
4470 ** Basically this function is a NOP since it will never be called,
4471 ** unless I implement the DC21041 SROM functions. There's no need
4472 ** since the existing code will be satisfactory for all boards.
4475 dc21041_infoleaf(struct net_device
*dev
)
4477 return DE4X5_AUTOSENSE_MS
;
4481 dc21140_infoleaf(struct net_device
*dev
)
4483 struct de4x5_private
*lp
= netdev_priv(dev
);
4485 u_char
*p
= (u_char
*)&lp
->srom
+ lp
->infoleaf_offset
;
4486 int next_tick
= DE4X5_AUTOSENSE_MS
;
4488 /* Read the connection type */
4492 lp
->cache
.gepc
= (*p
++ | GEP_CTRL
);
4497 /* Recursively figure out the info blocks */
4499 next_tick
= dc_infoblock
[COMPACT
](dev
, count
, p
);
4501 next_tick
= dc_infoblock
[*(p
+1)](dev
, count
, p
);
4504 if (lp
->tcount
== count
) {
4506 if (lp
->media
!= lp
->c_media
) {
4507 de4x5_dbg_media(dev
);
4508 lp
->c_media
= lp
->media
;
4512 lp
->tx_enable
= false;
4515 return next_tick
& ~TIMER_CB
;
4519 dc21142_infoleaf(struct net_device
*dev
)
4521 struct de4x5_private
*lp
= netdev_priv(dev
);
4523 u_char
*p
= (u_char
*)&lp
->srom
+ lp
->infoleaf_offset
;
4524 int next_tick
= DE4X5_AUTOSENSE_MS
;
4526 /* Read the connection type */
4532 /* Recursively figure out the info blocks */
4534 next_tick
= dc_infoblock
[COMPACT
](dev
, count
, p
);
4536 next_tick
= dc_infoblock
[*(p
+1)](dev
, count
, p
);
4539 if (lp
->tcount
== count
) {
4541 if (lp
->media
!= lp
->c_media
) {
4542 de4x5_dbg_media(dev
);
4543 lp
->c_media
= lp
->media
;
4547 lp
->tx_enable
= false;
4550 return next_tick
& ~TIMER_CB
;
4554 dc21143_infoleaf(struct net_device
*dev
)
4556 struct de4x5_private
*lp
= netdev_priv(dev
);
4558 u_char
*p
= (u_char
*)&lp
->srom
+ lp
->infoleaf_offset
;
4559 int next_tick
= DE4X5_AUTOSENSE_MS
;
4561 /* Read the connection type */
4567 /* Recursively figure out the info blocks */
4569 next_tick
= dc_infoblock
[COMPACT
](dev
, count
, p
);
4571 next_tick
= dc_infoblock
[*(p
+1)](dev
, count
, p
);
4573 if (lp
->tcount
== count
) {
4575 if (lp
->media
!= lp
->c_media
) {
4576 de4x5_dbg_media(dev
);
4577 lp
->c_media
= lp
->media
;
4581 lp
->tx_enable
= false;
4584 return next_tick
& ~TIMER_CB
;
4588 ** The compact infoblock is only designed for DC21140[A] chips, so
4589 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4592 compact_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
)
4594 struct de4x5_private
*lp
= netdev_priv(dev
);
4597 /* Recursively figure out the info blocks */
4598 if (--count
> lp
->tcount
) {
4599 if (*(p
+COMPACT_LEN
) < 128) {
4600 return dc_infoblock
[COMPACT
](dev
, count
, p
+COMPACT_LEN
);
4602 return dc_infoblock
[*(p
+COMPACT_LEN
+1)](dev
, count
, p
+COMPACT_LEN
);
4606 if ((lp
->media
== INIT
) && (lp
->timeout
< 0)) {
4609 gep_wr(lp
->cache
.gepc
, dev
);
4610 lp
->infoblock_media
= (*p
++) & COMPACT_MC
;
4611 lp
->cache
.gep
= *p
++;
4615 lp
->asBitValid
= (flags
& 0x80) ? 0 : -1;
4616 lp
->defMedium
= (flags
& 0x40) ? -1 : 0;
4617 lp
->asBit
= 1 << ((csr6
>> 1) & 0x07);
4618 lp
->asPolarity
= ((csr6
& 0x80) ? -1 : 0) & lp
->asBit
;
4619 lp
->infoblock_csr6
= OMR_DEF
| ((csr6
& 0x71) << 18);
4622 de4x5_switch_mac_port(dev
);
4625 return dc21140m_autoconf(dev
);
4629 ** This block describes non MII media for the DC21140[A] only.
4632 type0_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
)
4634 struct de4x5_private
*lp
= netdev_priv(dev
);
4635 u_char flags
, csr6
, len
= (*p
& BLOCK_LEN
)+1;
4637 /* Recursively figure out the info blocks */
4638 if (--count
> lp
->tcount
) {
4639 if (*(p
+len
) < 128) {
4640 return dc_infoblock
[COMPACT
](dev
, count
, p
+len
);
4642 return dc_infoblock
[*(p
+len
+1)](dev
, count
, p
+len
);
4646 if ((lp
->media
== INIT
) && (lp
->timeout
< 0)) {
4649 gep_wr(lp
->cache
.gepc
, dev
);
4651 lp
->infoblock_media
= (*p
++) & BLOCK0_MC
;
4652 lp
->cache
.gep
= *p
++;
4656 lp
->asBitValid
= (flags
& 0x80) ? 0 : -1;
4657 lp
->defMedium
= (flags
& 0x40) ? -1 : 0;
4658 lp
->asBit
= 1 << ((csr6
>> 1) & 0x07);
4659 lp
->asPolarity
= ((csr6
& 0x80) ? -1 : 0) & lp
->asBit
;
4660 lp
->infoblock_csr6
= OMR_DEF
| ((csr6
& 0x71) << 18);
4663 de4x5_switch_mac_port(dev
);
4666 return dc21140m_autoconf(dev
);
4669 /* These functions are under construction! */
4672 type1_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
)
4674 struct de4x5_private
*lp
= netdev_priv(dev
);
4675 u_char len
= (*p
& BLOCK_LEN
)+1;
4677 /* Recursively figure out the info blocks */
4678 if (--count
> lp
->tcount
) {
4679 if (*(p
+len
) < 128) {
4680 return dc_infoblock
[COMPACT
](dev
, count
, p
+len
);
4682 return dc_infoblock
[*(p
+len
+1)](dev
, count
, p
+len
);
4687 if (lp
->state
== INITIALISED
) {
4690 lp
->phy
[lp
->active
].gep
= (*p
? p
: NULL
); p
+= (*p
+ 1);
4691 lp
->phy
[lp
->active
].rst
= (*p
? p
: NULL
); p
+= (*p
+ 1);
4692 lp
->phy
[lp
->active
].mc
= get_unaligned_le16(p
); p
+= 2;
4693 lp
->phy
[lp
->active
].ana
= get_unaligned_le16(p
); p
+= 2;
4694 lp
->phy
[lp
->active
].fdx
= get_unaligned_le16(p
); p
+= 2;
4695 lp
->phy
[lp
->active
].ttm
= get_unaligned_le16(p
);
4697 } else if ((lp
->media
== INIT
) && (lp
->timeout
< 0)) {
4700 lp
->infoblock_csr6
= OMR_MII_100
;
4702 lp
->infoblock_media
= ANS
;
4704 de4x5_switch_mac_port(dev
);
4707 return dc21140m_autoconf(dev
);
4711 type2_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
)
4713 struct de4x5_private
*lp
= netdev_priv(dev
);
4714 u_char len
= (*p
& BLOCK_LEN
)+1;
4716 /* Recursively figure out the info blocks */
4717 if (--count
> lp
->tcount
) {
4718 if (*(p
+len
) < 128) {
4719 return dc_infoblock
[COMPACT
](dev
, count
, p
+len
);
4721 return dc_infoblock
[*(p
+len
+1)](dev
, count
, p
+len
);
4725 if ((lp
->media
== INIT
) && (lp
->timeout
< 0)) {
4729 lp
->infoblock_media
= (*p
) & MEDIA_CODE
;
4731 if ((*p
++) & EXT_FIELD
) {
4732 lp
->cache
.csr13
= get_unaligned_le16(p
); p
+= 2;
4733 lp
->cache
.csr14
= get_unaligned_le16(p
); p
+= 2;
4734 lp
->cache
.csr15
= get_unaligned_le16(p
); p
+= 2;
4736 lp
->cache
.csr13
= CSR13
;
4737 lp
->cache
.csr14
= CSR14
;
4738 lp
->cache
.csr15
= CSR15
;
4740 lp
->cache
.gepc
= ((s32
)(get_unaligned_le16(p
)) << 16); p
+= 2;
4741 lp
->cache
.gep
= ((s32
)(get_unaligned_le16(p
)) << 16);
4742 lp
->infoblock_csr6
= OMR_SIA
;
4745 de4x5_switch_mac_port(dev
);
4748 return dc2114x_autoconf(dev
);
4752 type3_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
)
4754 struct de4x5_private
*lp
= netdev_priv(dev
);
4755 u_char len
= (*p
& BLOCK_LEN
)+1;
4757 /* Recursively figure out the info blocks */
4758 if (--count
> lp
->tcount
) {
4759 if (*(p
+len
) < 128) {
4760 return dc_infoblock
[COMPACT
](dev
, count
, p
+len
);
4762 return dc_infoblock
[*(p
+len
+1)](dev
, count
, p
+len
);
4767 if (lp
->state
== INITIALISED
) {
4770 if (MOTO_SROM_BUG
) lp
->active
= 0;
4771 lp
->phy
[lp
->active
].gep
= (*p
? p
: NULL
); p
+= (2 * (*p
) + 1);
4772 lp
->phy
[lp
->active
].rst
= (*p
? p
: NULL
); p
+= (2 * (*p
) + 1);
4773 lp
->phy
[lp
->active
].mc
= get_unaligned_le16(p
); p
+= 2;
4774 lp
->phy
[lp
->active
].ana
= get_unaligned_le16(p
); p
+= 2;
4775 lp
->phy
[lp
->active
].fdx
= get_unaligned_le16(p
); p
+= 2;
4776 lp
->phy
[lp
->active
].ttm
= get_unaligned_le16(p
); p
+= 2;
4777 lp
->phy
[lp
->active
].mci
= *p
;
4779 } else if ((lp
->media
== INIT
) && (lp
->timeout
< 0)) {
4782 if (MOTO_SROM_BUG
) lp
->active
= 0;
4783 lp
->infoblock_csr6
= OMR_MII_100
;
4785 lp
->infoblock_media
= ANS
;
4787 de4x5_switch_mac_port(dev
);
4790 return dc2114x_autoconf(dev
);
4794 type4_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
)
4796 struct de4x5_private
*lp
= netdev_priv(dev
);
4797 u_char flags
, csr6
, len
= (*p
& BLOCK_LEN
)+1;
4799 /* Recursively figure out the info blocks */
4800 if (--count
> lp
->tcount
) {
4801 if (*(p
+len
) < 128) {
4802 return dc_infoblock
[COMPACT
](dev
, count
, p
+len
);
4804 return dc_infoblock
[*(p
+len
+1)](dev
, count
, p
+len
);
4808 if ((lp
->media
== INIT
) && (lp
->timeout
< 0)) {
4812 lp
->infoblock_media
= (*p
++) & MEDIA_CODE
;
4813 lp
->cache
.csr13
= CSR13
; /* Hard coded defaults */
4814 lp
->cache
.csr14
= CSR14
;
4815 lp
->cache
.csr15
= CSR15
;
4816 lp
->cache
.gepc
= ((s32
)(get_unaligned_le16(p
)) << 16); p
+= 2;
4817 lp
->cache
.gep
= ((s32
)(get_unaligned_le16(p
)) << 16); p
+= 2;
4821 lp
->asBitValid
= (flags
& 0x80) ? 0 : -1;
4822 lp
->defMedium
= (flags
& 0x40) ? -1 : 0;
4823 lp
->asBit
= 1 << ((csr6
>> 1) & 0x07);
4824 lp
->asPolarity
= ((csr6
& 0x80) ? -1 : 0) & lp
->asBit
;
4825 lp
->infoblock_csr6
= OMR_DEF
| ((csr6
& 0x71) << 18);
4828 de4x5_switch_mac_port(dev
);
4831 return dc2114x_autoconf(dev
);
4835 ** This block type provides information for resetting external devices
4836 ** (chips) through the General Purpose Register.
4839 type5_infoblock(struct net_device
*dev
, u_char count
, u_char
*p
)
4841 struct de4x5_private
*lp
= netdev_priv(dev
);
4842 u_char len
= (*p
& BLOCK_LEN
)+1;
4844 /* Recursively figure out the info blocks */
4845 if (--count
> lp
->tcount
) {
4846 if (*(p
+len
) < 128) {
4847 return dc_infoblock
[COMPACT
](dev
, count
, p
+len
);
4849 return dc_infoblock
[*(p
+len
+1)](dev
, count
, p
+len
);
4853 /* Must be initializing to run this code */
4854 if ((lp
->state
== INITIALISED
) || (lp
->media
== INIT
)) {
4857 srom_exec(dev
, lp
->rst
);
4860 return DE4X5_AUTOSENSE_MS
;
4868 mii_rd(u_char phyreg
, u_char phyaddr
, u_long ioaddr
)
4870 mii_wdata(MII_PREAMBLE
, 2, ioaddr
); /* Start of 34 bit preamble... */
4871 mii_wdata(MII_PREAMBLE
, 32, ioaddr
); /* ...continued */
4872 mii_wdata(MII_STRD
, 4, ioaddr
); /* SFD and Read operation */
4873 mii_address(phyaddr
, ioaddr
); /* PHY address to be accessed */
4874 mii_address(phyreg
, ioaddr
); /* PHY Register to read */
4875 mii_ta(MII_STRD
, ioaddr
); /* Turn around time - 2 MDC */
4877 return mii_rdata(ioaddr
); /* Read data */
4881 mii_wr(int data
, u_char phyreg
, u_char phyaddr
, u_long ioaddr
)
4883 mii_wdata(MII_PREAMBLE
, 2, ioaddr
); /* Start of 34 bit preamble... */
4884 mii_wdata(MII_PREAMBLE
, 32, ioaddr
); /* ...continued */
4885 mii_wdata(MII_STWR
, 4, ioaddr
); /* SFD and Write operation */
4886 mii_address(phyaddr
, ioaddr
); /* PHY address to be accessed */
4887 mii_address(phyreg
, ioaddr
); /* PHY Register to write */
4888 mii_ta(MII_STWR
, ioaddr
); /* Turn around time - 2 MDC */
4889 data
= mii_swap(data
, 16); /* Swap data bit ordering */
4890 mii_wdata(data
, 16, ioaddr
); /* Write data */
4896 mii_rdata(u_long ioaddr
)
4901 for (i
=0; i
<16; i
++) {
4903 tmp
|= getfrom_mii(MII_MRD
| MII_RD
, ioaddr
);
4910 mii_wdata(int data
, int len
, u_long ioaddr
)
4914 for (i
=0; i
<len
; i
++) {
4915 sendto_mii(MII_MWR
| MII_WR
, data
, ioaddr
);
4923 mii_address(u_char addr
, u_long ioaddr
)
4927 addr
= mii_swap(addr
, 5);
4928 for (i
=0; i
<5; i
++) {
4929 sendto_mii(MII_MWR
| MII_WR
, addr
, ioaddr
);
4937 mii_ta(u_long rw
, u_long ioaddr
)
4939 if (rw
== MII_STWR
) {
4940 sendto_mii(MII_MWR
| MII_WR
, 1, ioaddr
);
4941 sendto_mii(MII_MWR
| MII_WR
, 0, ioaddr
);
4943 getfrom_mii(MII_MRD
| MII_RD
, ioaddr
); /* Tri-state MDIO */
4950 mii_swap(int data
, int len
)
4954 for (i
=0; i
<len
; i
++) {
4964 sendto_mii(u32 command
, int data
, u_long ioaddr
)
4968 j
= (data
& 1) << 17;
4969 outl(command
| j
, ioaddr
);
4971 outl(command
| MII_MDC
| j
, ioaddr
);
4978 getfrom_mii(u32 command
, u_long ioaddr
)
4980 outl(command
, ioaddr
);
4982 outl(command
| MII_MDC
, ioaddr
);
4985 return ((inl(ioaddr
) >> 19) & 1);
4989 ** Here's 3 ways to calculate the OUI from the ID registers.
4992 mii_get_oui(u_char phyaddr
, u_long ioaddr
)
4999 int i, r2, r3, ret=0;*/
5002 /* Read r2 and r3 */
5003 r2
= mii_rd(MII_ID0
, phyaddr
, ioaddr
);
5004 r3
= mii_rd(MII_ID1
, phyaddr
, ioaddr
);
5005 /* SEEQ and Cypress way * /
5006 / * Shuffle r2 and r3 * /
5008 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5009 r2 = ((r2>>2)&0x3fff);
5011 / * Bit reverse r3 * /
5018 / * Bit reverse r2 * /
5019 for (i=0;i<16;i++) {
5025 / * Swap r2 bytes * /
5027 a.breg[0]=a.breg[1];
5030 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5031 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5032 return r2
; /* (I did it) My way */
5036 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5039 mii_get_phy(struct net_device
*dev
)
5041 struct de4x5_private
*lp
= netdev_priv(dev
);
5042 u_long iobase
= dev
->base_addr
;
5043 int i
, j
, k
, n
, limit
=ARRAY_SIZE(phy_info
);
5049 /* Search the MII address space for possible PHY devices */
5050 for (n
=0, lp
->mii_cnt
=0, i
=1; !((i
==1) && (n
==1)); i
=(i
+1)%DE4X5_MAX_MII
) {
5051 lp
->phy
[lp
->active
].addr
= i
;
5052 if (i
==0) n
++; /* Count cycles */
5053 while (de4x5_reset_phy(dev
)<0) udelay(100);/* Wait for reset */
5054 id
= mii_get_oui(i
, DE4X5_MII
);
5055 if ((id
== 0) || (id
== 65535)) continue; /* Valid ID? */
5056 for (j
=0; j
<limit
; j
++) { /* Search PHY table */
5057 if (id
!= phy_info
[j
].id
) continue; /* ID match? */
5058 for (k
=0; k
< DE4X5_MAX_PHY
&& lp
->phy
[k
].id
; k
++);
5059 if (k
< DE4X5_MAX_PHY
) {
5060 memcpy((char *)&lp
->phy
[k
],
5061 (char *)&phy_info
[j
], sizeof(struct phy_table
));
5062 lp
->phy
[k
].addr
= i
;
5066 goto purgatory
; /* Stop the search */
5070 if ((j
== limit
) && (i
< DE4X5_MAX_MII
)) {
5071 for (k
=0; k
< DE4X5_MAX_PHY
&& lp
->phy
[k
].id
; k
++);
5072 lp
->phy
[k
].addr
= i
;
5074 lp
->phy
[k
].spd
.reg
= GENERIC_REG
; /* ANLPA register */
5075 lp
->phy
[k
].spd
.mask
= GENERIC_MASK
; /* 100Mb/s technologies */
5076 lp
->phy
[k
].spd
.value
= GENERIC_VALUE
; /* TX & T4, H/F Duplex */
5079 printk("%s: Using generic MII device control. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev
->name
);
5081 de4x5_debug
|= DEBUG_MII
;
5082 de4x5_dbg_mii(dev
, k
);
5089 if (lp
->phy
[0].id
) { /* Reset the PHY devices */
5090 for (k
=0; k
< DE4X5_MAX_PHY
&& lp
->phy
[k
].id
; k
++) { /*For each PHY*/
5091 mii_wr(MII_CR_RST
, MII_CR
, lp
->phy
[k
].addr
, DE4X5_MII
);
5092 while (mii_rd(MII_CR
, lp
->phy
[k
].addr
, DE4X5_MII
) & MII_CR_RST
);
5094 de4x5_dbg_mii(dev
, k
);
5097 if (!lp
->mii_cnt
) lp
->useMII
= false;
5103 build_setup_frame(struct net_device
*dev
, int mode
)
5105 struct de4x5_private
*lp
= netdev_priv(dev
);
5107 char *pa
= lp
->setup_frame
;
5109 /* Initialise the setup frame */
5111 memset(lp
->setup_frame
, 0, SETUP_FRAME_LEN
);
5114 if (lp
->setup_f
== HASH_PERF
) {
5115 for (pa
=lp
->setup_frame
+IMPERF_PA_OFFSET
, i
=0; i
<ETH_ALEN
; i
++) {
5116 *(pa
+ i
) = dev
->dev_addr
[i
]; /* Host address */
5117 if (i
& 0x01) pa
+= 2;
5119 *(lp
->setup_frame
+ (HASH_TABLE_LEN
>> 3) - 3) = 0x80;
5121 for (i
=0; i
<ETH_ALEN
; i
++) { /* Host address */
5122 *(pa
+ (i
&1)) = dev
->dev_addr
[i
];
5123 if (i
& 0x01) pa
+= 4;
5125 for (i
=0; i
<ETH_ALEN
; i
++) { /* Broadcast address */
5126 *(pa
+ (i
&1)) = (char) 0xff;
5127 if (i
& 0x01) pa
+= 4;
5131 return pa
; /* Points to the next entry */
5135 disable_ast(struct net_device
*dev
)
5137 struct de4x5_private
*lp
= netdev_priv(dev
);
5138 del_timer_sync(&lp
->timer
);
5142 de4x5_switch_mac_port(struct net_device
*dev
)
5144 struct de4x5_private
*lp
= netdev_priv(dev
);
5145 u_long iobase
= dev
->base_addr
;
5150 /* Assert the OMR_PS bit in CSR6 */
5151 omr
= (inl(DE4X5_OMR
) & ~(OMR_PS
| OMR_HBD
| OMR_TTM
| OMR_PCS
| OMR_SCR
|
5153 omr
|= lp
->infoblock_csr6
;
5154 if (omr
& OMR_PS
) omr
|= OMR_HBD
;
5155 outl(omr
, DE4X5_OMR
);
5160 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5161 if (lp
->chipset
== DC21140
) {
5162 gep_wr(lp
->cache
.gepc
, dev
);
5163 gep_wr(lp
->cache
.gep
, dev
);
5164 } else if ((lp
->chipset
& ~0x0ff) == DC2114x
) {
5165 reset_init_sia(dev
, lp
->cache
.csr13
, lp
->cache
.csr14
, lp
->cache
.csr15
);
5169 outl(omr
, DE4X5_OMR
);
5178 gep_wr(s32 data
, struct net_device
*dev
)
5180 struct de4x5_private
*lp
= netdev_priv(dev
);
5181 u_long iobase
= dev
->base_addr
;
5183 if (lp
->chipset
== DC21140
) {
5184 outl(data
, DE4X5_GEP
);
5185 } else if ((lp
->chipset
& ~0x00ff) == DC2114x
) {
5186 outl((data
<<16) | lp
->cache
.csr15
, DE4X5_SIGR
);
5193 gep_rd(struct net_device
*dev
)
5195 struct de4x5_private
*lp
= netdev_priv(dev
);
5196 u_long iobase
= dev
->base_addr
;
5198 if (lp
->chipset
== DC21140
) {
5199 return inl(DE4X5_GEP
);
5200 } else if ((lp
->chipset
& ~0x00ff) == DC2114x
) {
5201 return (inl(DE4X5_SIGR
) & 0x000fffff);
5208 yawn(struct net_device
*dev
, int state
)
5210 struct de4x5_private
*lp
= netdev_priv(dev
);
5211 u_long iobase
= dev
->base_addr
;
5213 if ((lp
->chipset
== DC21040
) || (lp
->chipset
== DC21140
)) return;
5215 if(lp
->bus
== EISA
) {
5218 outb(WAKEUP
, PCI_CFPM
);
5223 outb(SNOOZE
, PCI_CFPM
);
5227 outl(0, DE4X5_SICR
);
5228 outb(SLEEP
, PCI_CFPM
);
5232 struct pci_dev
*pdev
= to_pci_dev (lp
->gendev
);
5235 pci_write_config_byte(pdev
, PCI_CFDA_PSM
, WAKEUP
);
5240 pci_write_config_byte(pdev
, PCI_CFDA_PSM
, SNOOZE
);
5244 outl(0, DE4X5_SICR
);
5245 pci_write_config_byte(pdev
, PCI_CFDA_PSM
, SLEEP
);
5254 de4x5_parse_params(struct net_device
*dev
)
5256 struct de4x5_private
*lp
= netdev_priv(dev
);
5260 lp
->params
.autosense
= AUTO
;
5262 if (args
== NULL
) return;
5264 if ((p
= strstr(args
, dev
->name
))) {
5265 if (!(q
= strstr(p
+strlen(dev
->name
), "eth"))) q
= p
+ strlen(p
);
5269 if (strstr(p
, "fdx") || strstr(p
, "FDX")) lp
->params
.fdx
= 1;
5271 if (strstr(p
, "autosense") || strstr(p
, "AUTOSENSE")) {
5272 if (strstr(p
, "TP")) {
5273 lp
->params
.autosense
= TP
;
5274 } else if (strstr(p
, "TP_NW")) {
5275 lp
->params
.autosense
= TP_NW
;
5276 } else if (strstr(p
, "BNC")) {
5277 lp
->params
.autosense
= BNC
;
5278 } else if (strstr(p
, "AUI")) {
5279 lp
->params
.autosense
= AUI
;
5280 } else if (strstr(p
, "BNC_AUI")) {
5281 lp
->params
.autosense
= BNC
;
5282 } else if (strstr(p
, "10Mb")) {
5283 lp
->params
.autosense
= _10Mb
;
5284 } else if (strstr(p
, "100Mb")) {
5285 lp
->params
.autosense
= _100Mb
;
5286 } else if (strstr(p
, "AUTO")) {
5287 lp
->params
.autosense
= AUTO
;
5297 de4x5_dbg_open(struct net_device
*dev
)
5299 struct de4x5_private
*lp
= netdev_priv(dev
);
5302 if (de4x5_debug
& DEBUG_OPEN
) {
5303 printk("%s: de4x5 opening with irq %d\n",dev
->name
,dev
->irq
);
5304 printk("\tphysical address: ");
5306 printk("%2.2x:",(short)dev
->dev_addr
[i
]);
5309 printk("Descriptor head addresses:\n");
5310 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long
)lp
->rx_ring
,(u_long
)lp
->tx_ring
);
5311 printk("Descriptor addresses:\nRX: ");
5312 for (i
=0;i
<lp
->rxRingSize
-1;i
++){
5314 printk("0x%8.8lx ",(u_long
)&lp
->rx_ring
[i
].status
);
5317 printk("...0x%8.8lx\n",(u_long
)&lp
->rx_ring
[i
].status
);
5319 for (i
=0;i
<lp
->txRingSize
-1;i
++){
5321 printk("0x%8.8lx ", (u_long
)&lp
->tx_ring
[i
].status
);
5324 printk("...0x%8.8lx\n", (u_long
)&lp
->tx_ring
[i
].status
);
5325 printk("Descriptor buffers:\nRX: ");
5326 for (i
=0;i
<lp
->rxRingSize
-1;i
++){
5328 printk("0x%8.8x ",le32_to_cpu(lp
->rx_ring
[i
].buf
));
5331 printk("...0x%8.8x\n",le32_to_cpu(lp
->rx_ring
[i
].buf
));
5333 for (i
=0;i
<lp
->txRingSize
-1;i
++){
5335 printk("0x%8.8x ", le32_to_cpu(lp
->tx_ring
[i
].buf
));
5338 printk("...0x%8.8x\n", le32_to_cpu(lp
->tx_ring
[i
].buf
));
5339 printk("Ring size:\nRX: %d\nTX: %d\n",
5340 (short)lp
->rxRingSize
,
5341 (short)lp
->txRingSize
);
5348 de4x5_dbg_mii(struct net_device
*dev
, int k
)
5350 struct de4x5_private
*lp
= netdev_priv(dev
);
5351 u_long iobase
= dev
->base_addr
;
5353 if (de4x5_debug
& DEBUG_MII
) {
5354 printk("\nMII device address: %d\n", lp
->phy
[k
].addr
);
5355 printk("MII CR: %x\n",mii_rd(MII_CR
,lp
->phy
[k
].addr
,DE4X5_MII
));
5356 printk("MII SR: %x\n",mii_rd(MII_SR
,lp
->phy
[k
].addr
,DE4X5_MII
));
5357 printk("MII ID0: %x\n",mii_rd(MII_ID0
,lp
->phy
[k
].addr
,DE4X5_MII
));
5358 printk("MII ID1: %x\n",mii_rd(MII_ID1
,lp
->phy
[k
].addr
,DE4X5_MII
));
5359 if (lp
->phy
[k
].id
!= BROADCOM_T4
) {
5360 printk("MII ANA: %x\n",mii_rd(0x04,lp
->phy
[k
].addr
,DE4X5_MII
));
5361 printk("MII ANC: %x\n",mii_rd(0x05,lp
->phy
[k
].addr
,DE4X5_MII
));
5363 printk("MII 16: %x\n",mii_rd(0x10,lp
->phy
[k
].addr
,DE4X5_MII
));
5364 if (lp
->phy
[k
].id
!= BROADCOM_T4
) {
5365 printk("MII 17: %x\n",mii_rd(0x11,lp
->phy
[k
].addr
,DE4X5_MII
));
5366 printk("MII 18: %x\n",mii_rd(0x12,lp
->phy
[k
].addr
,DE4X5_MII
));
5368 printk("MII 20: %x\n",mii_rd(0x14,lp
->phy
[k
].addr
,DE4X5_MII
));
5376 de4x5_dbg_media(struct net_device
*dev
)
5378 struct de4x5_private
*lp
= netdev_priv(dev
);
5380 if (lp
->media
!= lp
->c_media
) {
5381 if (de4x5_debug
& DEBUG_MEDIA
) {
5382 printk("%s: media is %s%s\n", dev
->name
,
5383 (lp
->media
== NC
? "unconnected, link down or incompatible connection" :
5384 (lp
->media
== TP
? "TP" :
5385 (lp
->media
== ANS
? "TP/Nway" :
5386 (lp
->media
== BNC
? "BNC" :
5387 (lp
->media
== AUI
? "AUI" :
5388 (lp
->media
== BNC_AUI
? "BNC/AUI" :
5389 (lp
->media
== EXT_SIA
? "EXT SIA" :
5390 (lp
->media
== _100Mb
? "100Mb/s" :
5391 (lp
->media
== _10Mb
? "10Mb/s" :
5393 ))))))))), (lp
->fdx
?" full duplex.":"."));
5395 lp
->c_media
= lp
->media
;
5402 de4x5_dbg_srom(struct de4x5_srom
*p
)
5406 if (de4x5_debug
& DEBUG_SROM
) {
5407 printk("Sub-system Vendor ID: %04x\n", *((u_short
*)p
->sub_vendor_id
));
5408 printk("Sub-system ID: %04x\n", *((u_short
*)p
->sub_system_id
));
5409 printk("ID Block CRC: %02x\n", (u_char
)(p
->id_block_crc
));
5410 printk("SROM version: %02x\n", (u_char
)(p
->version
));
5411 printk("# controllers: %02x\n", (u_char
)(p
->num_controllers
));
5413 printk("Hardware Address: %pM\n", p
->ieee_addr
);
5414 printk("CRC checksum: %04x\n", (u_short
)(p
->chksum
));
5415 for (i
=0; i
<64; i
++) {
5416 printk("%3d %04x\n", i
<<1, (u_short
)*((u_short
*)p
+i
));
5424 de4x5_dbg_rx(struct sk_buff
*skb
, int len
)
5428 if (de4x5_debug
& DEBUG_RX
) {
5429 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5430 skb
->data
, &skb
->data
[6],
5431 (u_char
)skb
->data
[12],
5432 (u_char
)skb
->data
[13],
5434 for (j
=0; len
>0;j
+=16, len
-=16) {
5435 printk(" %03x: ",j
);
5436 for (i
=0; i
<16 && i
<len
; i
++) {
5437 printk("%02x ",(u_char
)skb
->data
[i
+j
]);
5447 ** Perform IOCTL call functions here. Some are privileged operations and the
5448 ** effective uid is checked in those cases. In the normal course of events
5449 ** this function is only used for my testing.
5452 de4x5_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
5454 struct de4x5_private
*lp
= netdev_priv(dev
);
5455 struct de4x5_ioctl
*ioc
= (struct de4x5_ioctl
*) &rq
->ifr_ifru
;
5456 u_long iobase
= dev
->base_addr
;
5457 int i
, j
, status
= 0;
5467 case DE4X5_GET_HWADDR
: /* Get the hardware address */
5468 ioc
->len
= ETH_ALEN
;
5469 for (i
=0; i
<ETH_ALEN
; i
++) {
5470 tmp
.addr
[i
] = dev
->dev_addr
[i
];
5472 if (copy_to_user(ioc
->data
, tmp
.addr
, ioc
->len
)) return -EFAULT
;
5475 case DE4X5_SET_HWADDR
: /* Set the hardware address */
5476 if (!capable(CAP_NET_ADMIN
)) return -EPERM
;
5477 if (copy_from_user(tmp
.addr
, ioc
->data
, ETH_ALEN
)) return -EFAULT
;
5478 if (netif_queue_stopped(dev
))
5480 netif_stop_queue(dev
);
5481 for (i
=0; i
<ETH_ALEN
; i
++) {
5482 dev
->dev_addr
[i
] = tmp
.addr
[i
];
5484 build_setup_frame(dev
, PHYS_ADDR_ONLY
);
5485 /* Set up the descriptor and give ownership to the card */
5486 load_packet(dev
, lp
->setup_frame
, TD_IC
| PERFECT_F
| TD_SET
|
5487 SETUP_FRAME_LEN
, (struct sk_buff
*)1);
5488 lp
->tx_new
= (++lp
->tx_new
) % lp
->txRingSize
;
5489 outl(POLL_DEMAND
, DE4X5_TPD
); /* Start the TX */
5490 netif_wake_queue(dev
); /* Unlock the TX ring */
5493 case DE4X5_SAY_BOO
: /* Say "Boo!" to the kernel log file */
5494 if (!capable(CAP_NET_ADMIN
)) return -EPERM
;
5495 printk("%s: Boo!\n", dev
->name
);
5498 case DE4X5_MCA_EN
: /* Enable pass all multicast addressing */
5499 if (!capable(CAP_NET_ADMIN
)) return -EPERM
;
5500 omr
= inl(DE4X5_OMR
);
5502 outl(omr
, DE4X5_OMR
);
5505 case DE4X5_GET_STATS
: /* Get the driver statistics */
5507 struct pkt_stats statbuf
;
5508 ioc
->len
= sizeof(statbuf
);
5509 spin_lock_irqsave(&lp
->lock
, flags
);
5510 memcpy(&statbuf
, &lp
->pktStats
, ioc
->len
);
5511 spin_unlock_irqrestore(&lp
->lock
, flags
);
5512 if (copy_to_user(ioc
->data
, &statbuf
, ioc
->len
))
5516 case DE4X5_CLR_STATS
: /* Zero out the driver statistics */
5517 if (!capable(CAP_NET_ADMIN
)) return -EPERM
;
5518 spin_lock_irqsave(&lp
->lock
, flags
);
5519 memset(&lp
->pktStats
, 0, sizeof(lp
->pktStats
));
5520 spin_unlock_irqrestore(&lp
->lock
, flags
);
5523 case DE4X5_GET_OMR
: /* Get the OMR Register contents */
5524 tmp
.addr
[0] = inl(DE4X5_OMR
);
5525 if (copy_to_user(ioc
->data
, tmp
.addr
, 1)) return -EFAULT
;
5528 case DE4X5_SET_OMR
: /* Set the OMR Register contents */
5529 if (!capable(CAP_NET_ADMIN
)) return -EPERM
;
5530 if (copy_from_user(tmp
.addr
, ioc
->data
, 1)) return -EFAULT
;
5531 outl(tmp
.addr
[0], DE4X5_OMR
);
5534 case DE4X5_GET_REG
: /* Get the DE4X5 Registers */
5536 tmp
.lval
[0] = inl(DE4X5_STS
); j
+=4;
5537 tmp
.lval
[1] = inl(DE4X5_BMR
); j
+=4;
5538 tmp
.lval
[2] = inl(DE4X5_IMR
); j
+=4;
5539 tmp
.lval
[3] = inl(DE4X5_OMR
); j
+=4;
5540 tmp
.lval
[4] = inl(DE4X5_SISR
); j
+=4;
5541 tmp
.lval
[5] = inl(DE4X5_SICR
); j
+=4;
5542 tmp
.lval
[6] = inl(DE4X5_STRR
); j
+=4;
5543 tmp
.lval
[7] = inl(DE4X5_SIGR
); j
+=4;
5545 if (copy_to_user(ioc
->data
, tmp
.addr
, ioc
->len
)) return -EFAULT
;
5548 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5552 tmp.addr[j++] = dev->irq;
5553 for (i=0; i<ETH_ALEN; i++) {
5554 tmp.addr[j++] = dev->dev_addr[i];
5556 tmp.addr[j++] = lp->rxRingSize;
5557 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5558 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5560 for (i=0;i<lp->rxRingSize-1;i++){
5562 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5565 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5566 for (i=0;i<lp->txRingSize-1;i++){
5568 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5571 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5573 for (i=0;i<lp->rxRingSize-1;i++){
5575 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5578 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5579 for (i=0;i<lp->txRingSize-1;i++){
5581 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5584 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5586 for (i=0;i<lp->rxRingSize;i++){
5587 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5589 for (i=0;i<lp->txRingSize;i++){
5590 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5593 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5594 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5595 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5596 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5597 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5598 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5599 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5600 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5601 tmp.lval[j>>2] = lp->chipset; j+=4;
5602 if (lp->chipset == DC21140) {
5603 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5605 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5606 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5607 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5608 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5610 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5611 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5612 tmp.lval[j>>2] = lp->active; j+=4;
5613 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5614 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5615 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5616 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5617 if (lp->phy[lp->active].id != BROADCOM_T4) {
5618 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5619 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5621 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5622 if (lp->phy[lp->active].id != BROADCOM_T4) {
5623 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5624 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5626 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5630 tmp.addr[j++] = lp->txRingSize;
5631 tmp.addr[j++] = netif_queue_stopped(dev);
5634 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5645 static int __init
de4x5_module_init (void)
5650 err
= pci_register_driver(&de4x5_pci_driver
);
5653 err
|= eisa_driver_register (&de4x5_eisa_driver
);
5659 static void __exit
de4x5_module_exit (void)
5662 pci_unregister_driver (&de4x5_pci_driver
);
5665 eisa_driver_unregister (&de4x5_eisa_driver
);
5669 module_init (de4x5_module_init
);
5670 module_exit (de4x5_module_exit
);