2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17 #define DRV_NAME "uli526x"
18 #define DRV_VERSION "0.9.3"
19 #define DRV_RELDATE "2005-7-29"
21 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/skbuff.h>
36 #include <linux/delay.h>
37 #include <linux/spinlock.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/bitops.h>
41 #include <asm/processor.h>
44 #include <asm/uaccess.h>
47 /* Board/System/Debug information/definition ---------------- */
48 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
49 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
51 #define ULI526X_IO_SIZE 0x100
52 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
53 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
54 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
55 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
56 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
57 #define TX_BUF_ALLOC 0x600
58 #define RX_ALLOC_SIZE 0x620
59 #define ULI526X_RESET 1
61 #define CR6_DEFAULT 0x22200000
62 #define CR7_DEFAULT 0x180c1
63 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
64 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
65 #define MAX_PACKET_SIZE 1514
66 #define ULI5261_MAX_MULTICAST 14
67 #define RX_COPY_SIZE 100
68 #define MAX_CHECK_PACKET 0x8000
70 #define ULI526X_10MHF 0
71 #define ULI526X_100MHF 1
72 #define ULI526X_10MFD 4
73 #define ULI526X_100MFD 5
74 #define ULI526X_AUTO 8
76 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
77 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
78 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
79 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
80 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
81 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
83 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
84 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
85 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
87 #define ULI526X_DBUG(dbug_now, msg, value) \
89 if (uli526x_debug || (dbug_now)) \
90 pr_err("%s %lx\n", (msg), (long) (value)); \
93 #define SHOW_MEDIA_TYPE(mode) \
94 pr_err("Change Speed to %sMhz %s duplex\n", \
95 mode & 1 ? "100" : "10", \
96 mode & 4 ? "full" : "half");
99 /* CR9 definition: SROM/MII */
100 #define CR9_SROM_READ 0x4800
102 #define CR9_SRCLK 0x2
103 #define CR9_CRDOUT 0x8
104 #define SROM_DATA_0 0x0
105 #define SROM_DATA_1 0x4
106 #define PHY_DATA_1 0x20000
107 #define PHY_DATA_0 0x00000
108 #define MDCLKH 0x10000
110 #define PHY_POWER_DOWN 0x800
112 #define SROM_V41_CODE 0x14
114 #define SROM_CLK_WRITE(data, ioaddr) \
115 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
117 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
119 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
122 /* Structure/enum declaration ------------------------------- */
124 __le32 tdes0
, tdes1
, tdes2
, tdes3
; /* Data for the card */
125 char *tx_buf_ptr
; /* Data for us */
126 struct tx_desc
*next_tx_desc
;
127 } __attribute__(( aligned(32) ));
130 __le32 rdes0
, rdes1
, rdes2
, rdes3
; /* Data for the card */
131 struct sk_buff
*rx_skb_ptr
; /* Data for us */
132 struct rx_desc
*next_rx_desc
;
133 } __attribute__(( aligned(32) ));
135 struct uli526x_board_info
{
136 u32 chip_id
; /* Chip vendor/Device ID */
137 struct net_device
*next_dev
; /* next device */
138 struct pci_dev
*pdev
; /* PCI device */
141 long ioaddr
; /* I/O base address */
148 /* pointer for memory physical address */
149 dma_addr_t buf_pool_dma_ptr
; /* Tx buffer pool memory */
150 dma_addr_t buf_pool_dma_start
; /* Tx buffer pool align dword */
151 dma_addr_t desc_pool_dma_ptr
; /* descriptor pool memory */
152 dma_addr_t first_tx_desc_dma
;
153 dma_addr_t first_rx_desc_dma
;
155 /* descriptor pointer */
156 unsigned char *buf_pool_ptr
; /* Tx buffer pool memory */
157 unsigned char *buf_pool_start
; /* Tx buffer pool align dword */
158 unsigned char *desc_pool_ptr
; /* descriptor pool memory */
159 struct tx_desc
*first_tx_desc
;
160 struct tx_desc
*tx_insert_ptr
;
161 struct tx_desc
*tx_remove_ptr
;
162 struct rx_desc
*first_rx_desc
;
163 struct rx_desc
*rx_insert_ptr
;
164 struct rx_desc
*rx_ready_ptr
; /* packet come pointer */
165 unsigned long tx_packet_cnt
; /* transmitted packet count */
166 unsigned long rx_avail_cnt
; /* available rx descriptor count */
167 unsigned long interval_rx_cnt
; /* rx packet count a callback time */
170 u16 NIC_capability
; /* NIC media capability */
171 u16 PHY_reg4
; /* Saved Phyxcer register 4 value */
173 u8 media_mode
; /* user specify media mode */
174 u8 op_mode
; /* real work media mode */
176 u8 link_failed
; /* Ever link failed */
177 u8 wait_reset
; /* Hardware failed, need to reset */
178 struct timer_list timer
;
180 /* Driver defined statistic counter */
181 unsigned long tx_fifo_underrun
;
182 unsigned long tx_loss_carrier
;
183 unsigned long tx_no_carrier
;
184 unsigned long tx_late_collision
;
185 unsigned long tx_excessive_collision
;
186 unsigned long tx_jabber_timeout
;
187 unsigned long reset_count
;
188 unsigned long reset_cr8
;
189 unsigned long reset_fatal
;
190 unsigned long reset_TXtimeout
;
193 unsigned char srom
[128];
197 enum uli526x_offsets
{
198 DCR0
= 0x00, DCR1
= 0x08, DCR2
= 0x10, DCR3
= 0x18, DCR4
= 0x20,
199 DCR5
= 0x28, DCR6
= 0x30, DCR7
= 0x38, DCR8
= 0x40, DCR9
= 0x48,
200 DCR10
= 0x50, DCR11
= 0x58, DCR12
= 0x60, DCR13
= 0x68, DCR14
= 0x70,
204 enum uli526x_CR6_bits
{
205 CR6_RXSC
= 0x2, CR6_PBF
= 0x8, CR6_PM
= 0x40, CR6_PAM
= 0x80,
206 CR6_FDM
= 0x200, CR6_TXSC
= 0x2000, CR6_STI
= 0x100000,
207 CR6_SFT
= 0x200000, CR6_RXA
= 0x40000000, CR6_NO_PURGE
= 0x20000000
210 /* Global variable declaration ----------------------------- */
211 static int __devinitdata printed_version
;
212 static const char version
[] __devinitconst
=
213 KERN_INFO DRV_NAME
": ULi M5261/M5263 net driver, version "
214 DRV_VERSION
" (" DRV_RELDATE
")\n";
216 static int uli526x_debug
;
217 static unsigned char uli526x_media_mode
= ULI526X_AUTO
;
218 static u32 uli526x_cr6_user_set
;
220 /* For module input parameter */
225 /* function declaration ------------------------------------- */
226 static int uli526x_open(struct net_device
*);
227 static netdev_tx_t
uli526x_start_xmit(struct sk_buff
*,
228 struct net_device
*);
229 static int uli526x_stop(struct net_device
*);
230 static void uli526x_set_filter_mode(struct net_device
*);
231 static const struct ethtool_ops netdev_ethtool_ops
;
232 static u16
read_srom_word(long, int);
233 static irqreturn_t
uli526x_interrupt(int, void *);
234 #ifdef CONFIG_NET_POLL_CONTROLLER
235 static void uli526x_poll(struct net_device
*dev
);
237 static void uli526x_descriptor_init(struct uli526x_board_info
*, unsigned long);
238 static void allocate_rx_buffer(struct uli526x_board_info
*);
239 static void update_cr6(u32
, unsigned long);
240 static void send_filter_frame(struct net_device
*, int);
241 static u16
phy_read(unsigned long, u8
, u8
, u32
);
242 static u16
phy_readby_cr10(unsigned long, u8
, u8
);
243 static void phy_write(unsigned long, u8
, u8
, u16
, u32
);
244 static void phy_writeby_cr10(unsigned long, u8
, u8
, u16
);
245 static void phy_write_1bit(unsigned long, u32
, u32
);
246 static u16
phy_read_1bit(unsigned long, u32
);
247 static u8
uli526x_sense_speed(struct uli526x_board_info
*);
248 static void uli526x_process_mode(struct uli526x_board_info
*);
249 static void uli526x_timer(unsigned long);
250 static void uli526x_rx_packet(struct net_device
*, struct uli526x_board_info
*);
251 static void uli526x_free_tx_pkt(struct net_device
*, struct uli526x_board_info
*);
252 static void uli526x_reuse_skb(struct uli526x_board_info
*, struct sk_buff
*);
253 static void uli526x_dynamic_reset(struct net_device
*);
254 static void uli526x_free_rxbuffer(struct uli526x_board_info
*);
255 static void uli526x_init(struct net_device
*);
256 static void uli526x_set_phyxcer(struct uli526x_board_info
*);
258 /* ULI526X network board routine ---------------------------- */
260 static const struct net_device_ops netdev_ops
= {
261 .ndo_open
= uli526x_open
,
262 .ndo_stop
= uli526x_stop
,
263 .ndo_start_xmit
= uli526x_start_xmit
,
264 .ndo_set_multicast_list
= uli526x_set_filter_mode
,
265 .ndo_change_mtu
= eth_change_mtu
,
266 .ndo_set_mac_address
= eth_mac_addr
,
267 .ndo_validate_addr
= eth_validate_addr
,
268 #ifdef CONFIG_NET_POLL_CONTROLLER
269 .ndo_poll_controller
= uli526x_poll
,
274 * Search ULI526X board, allocate space and register it
277 static int __devinit
uli526x_init_one (struct pci_dev
*pdev
,
278 const struct pci_device_id
*ent
)
280 struct uli526x_board_info
*db
; /* board information structure */
281 struct net_device
*dev
;
284 ULI526X_DBUG(0, "uli526x_init_one()", 0);
286 if (!printed_version
++)
289 /* Init network device */
290 dev
= alloc_etherdev(sizeof(*db
));
293 SET_NETDEV_DEV(dev
, &pdev
->dev
);
295 if (pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) {
296 pr_warning("32-bit PCI DMA not available\n");
301 /* Enable Master/IO access, Disable memory access */
302 err
= pci_enable_device(pdev
);
306 if (!pci_resource_start(pdev
, 0)) {
307 pr_err("I/O base is zero\n");
309 goto err_out_disable
;
312 if (pci_resource_len(pdev
, 0) < (ULI526X_IO_SIZE
) ) {
313 pr_err("Allocated I/O size too small\n");
315 goto err_out_disable
;
318 if (pci_request_regions(pdev
, DRV_NAME
)) {
319 pr_err("Failed to request PCI regions\n");
321 goto err_out_disable
;
324 /* Init system & device */
325 db
= netdev_priv(dev
);
327 /* Allocate Tx/Rx descriptor memory */
328 db
->desc_pool_ptr
= pci_alloc_consistent(pdev
, sizeof(struct tx_desc
) * DESC_ALL_CNT
+ 0x20, &db
->desc_pool_dma_ptr
);
329 if(db
->desc_pool_ptr
== NULL
)
334 db
->buf_pool_ptr
= pci_alloc_consistent(pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4, &db
->buf_pool_dma_ptr
);
335 if(db
->buf_pool_ptr
== NULL
)
341 db
->first_tx_desc
= (struct tx_desc
*) db
->desc_pool_ptr
;
342 db
->first_tx_desc_dma
= db
->desc_pool_dma_ptr
;
343 db
->buf_pool_start
= db
->buf_pool_ptr
;
344 db
->buf_pool_dma_start
= db
->buf_pool_dma_ptr
;
346 db
->chip_id
= ent
->driver_data
;
347 db
->ioaddr
= pci_resource_start(pdev
, 0);
352 dev
->base_addr
= db
->ioaddr
;
353 dev
->irq
= pdev
->irq
;
354 pci_set_drvdata(pdev
, dev
);
356 /* Register some necessary functions */
357 dev
->netdev_ops
= &netdev_ops
;
358 dev
->ethtool_ops
= &netdev_ethtool_ops
;
360 spin_lock_init(&db
->lock
);
363 /* read 64 word srom data */
364 for (i
= 0; i
< 64; i
++)
365 ((__le16
*) db
->srom
)[i
] = cpu_to_le16(read_srom_word(db
->ioaddr
, i
));
367 /* Set Node address */
368 if(((u16
*) db
->srom
)[0] == 0xffff || ((u16
*) db
->srom
)[0] == 0) /* SROM absent, so read MAC address from ID Table */
370 outl(0x10000, db
->ioaddr
+ DCR0
); //Diagnosis mode
371 outl(0x1c0, db
->ioaddr
+ DCR13
); //Reset dianostic pointer port
372 outl(0, db
->ioaddr
+ DCR14
); //Clear reset port
373 outl(0x10, db
->ioaddr
+ DCR14
); //Reset ID Table pointer
374 outl(0, db
->ioaddr
+ DCR14
); //Clear reset port
375 outl(0, db
->ioaddr
+ DCR13
); //Clear CR13
376 outl(0x1b0, db
->ioaddr
+ DCR13
); //Select ID Table access port
377 //Read MAC address from CR14
378 for (i
= 0; i
< 6; i
++)
379 dev
->dev_addr
[i
] = inl(db
->ioaddr
+ DCR14
);
381 outl(0, db
->ioaddr
+ DCR13
); //Clear CR13
382 outl(0, db
->ioaddr
+ DCR0
); //Clear CR0
387 for (i
= 0; i
< 6; i
++)
388 dev
->dev_addr
[i
] = db
->srom
[20 + i
];
390 err
= register_netdev (dev
);
394 dev_info(&dev
->dev
, "ULi M%04lx at pci%s, %pM, irq %d\n",
395 ent
->driver_data
>> 16, pci_name(pdev
),
396 dev
->dev_addr
, dev
->irq
);
398 pci_set_master(pdev
);
403 pci_release_regions(pdev
);
405 if(db
->desc_pool_ptr
)
406 pci_free_consistent(pdev
, sizeof(struct tx_desc
) * DESC_ALL_CNT
+ 0x20,
407 db
->desc_pool_ptr
, db
->desc_pool_dma_ptr
);
409 if(db
->buf_pool_ptr
!= NULL
)
410 pci_free_consistent(pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4,
411 db
->buf_pool_ptr
, db
->buf_pool_dma_ptr
);
413 pci_disable_device(pdev
);
415 pci_set_drvdata(pdev
, NULL
);
422 static void __devexit
uli526x_remove_one (struct pci_dev
*pdev
)
424 struct net_device
*dev
= pci_get_drvdata(pdev
);
425 struct uli526x_board_info
*db
= netdev_priv(dev
);
427 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
429 pci_free_consistent(db
->pdev
, sizeof(struct tx_desc
) *
430 DESC_ALL_CNT
+ 0x20, db
->desc_pool_ptr
,
431 db
->desc_pool_dma_ptr
);
432 pci_free_consistent(db
->pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4,
433 db
->buf_pool_ptr
, db
->buf_pool_dma_ptr
);
434 unregister_netdev(dev
);
435 pci_release_regions(pdev
);
436 free_netdev(dev
); /* free board information */
437 pci_set_drvdata(pdev
, NULL
);
438 pci_disable_device(pdev
);
439 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
444 * Open the interface.
445 * The interface is opened whenever "ifconfig" activates it.
448 static int uli526x_open(struct net_device
*dev
)
451 struct uli526x_board_info
*db
= netdev_priv(dev
);
453 ULI526X_DBUG(0, "uli526x_open", 0);
455 /* system variable init */
456 db
->cr6_data
= CR6_DEFAULT
| uli526x_cr6_user_set
;
457 db
->tx_packet_cnt
= 0;
458 db
->rx_avail_cnt
= 0;
460 netif_carrier_off(dev
);
463 db
->NIC_capability
= 0xf; /* All capability*/
464 db
->PHY_reg4
= 0x1e0;
466 /* CR6 operation mode decision */
467 db
->cr6_data
|= ULI526X_TXTH_256
;
468 db
->cr0_data
= CR0_DEFAULT
;
470 /* Initialize ULI526X board */
473 ret
= request_irq(dev
->irq
, uli526x_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
477 /* Active System Interface */
478 netif_wake_queue(dev
);
480 /* set and active a timer process */
481 init_timer(&db
->timer
);
482 db
->timer
.expires
= ULI526X_TIMER_WUT
+ HZ
* 2;
483 db
->timer
.data
= (unsigned long)dev
;
484 db
->timer
.function
= &uli526x_timer
;
485 add_timer(&db
->timer
);
491 /* Initialize ULI526X board
492 * Reset ULI526X board
493 * Initialize TX/Rx descriptor chain structure
494 * Send the set-up frame
495 * Enable Tx/Rx machine
498 static void uli526x_init(struct net_device
*dev
)
500 struct uli526x_board_info
*db
= netdev_priv(dev
);
501 unsigned long ioaddr
= db
->ioaddr
;
508 ULI526X_DBUG(0, "uli526x_init()", 0);
510 /* Reset M526x MAC controller */
511 outl(ULI526X_RESET
, ioaddr
+ DCR0
); /* RESET MAC */
513 outl(db
->cr0_data
, ioaddr
+ DCR0
);
516 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
518 for(phy_tmp
=0;phy_tmp
<32;phy_tmp
++)
520 phy_value
=phy_read(db
->ioaddr
,phy_tmp
,3,db
->chip_id
);//peer add
521 if(phy_value
!= 0xffff&&phy_value
!=0)
523 db
->phy_addr
= phy_tmp
;
528 pr_warning("Can not find the phy address!!!");
529 /* Parser SROM and media mode */
530 db
->media_mode
= uli526x_media_mode
;
532 /* phyxcer capability setting */
533 phy_reg_reset
= phy_read(db
->ioaddr
, db
->phy_addr
, 0, db
->chip_id
);
534 phy_reg_reset
= (phy_reg_reset
| 0x8000);
535 phy_write(db
->ioaddr
, db
->phy_addr
, 0, phy_reg_reset
, db
->chip_id
);
537 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
538 * functions") or phy data sheet for details on phy reset
543 phy_read(db
->ioaddr
, db
->phy_addr
, 0, db
->chip_id
) & 0x8000)
546 /* Process Phyxcer Media Mode */
547 uli526x_set_phyxcer(db
);
549 /* Media Mode Process */
550 if ( !(db
->media_mode
& ULI526X_AUTO
) )
551 db
->op_mode
= db
->media_mode
; /* Force Mode */
553 /* Initialize Transmit/Receive decriptor and CR3/4 */
554 uli526x_descriptor_init(db
, ioaddr
);
556 /* Init CR6 to program M526X operation */
557 update_cr6(db
->cr6_data
, ioaddr
);
559 /* Send setup frame */
560 send_filter_frame(dev
, netdev_mc_count(dev
)); /* M5261/M5263 */
562 /* Init CR7, interrupt active bit */
563 db
->cr7_data
= CR7_DEFAULT
;
564 outl(db
->cr7_data
, ioaddr
+ DCR7
);
566 /* Init CR15, Tx jabber and Rx watchdog timer */
567 outl(db
->cr15_data
, ioaddr
+ DCR15
);
569 /* Enable ULI526X Tx/Rx function */
570 db
->cr6_data
|= CR6_RXSC
| CR6_TXSC
;
571 update_cr6(db
->cr6_data
, ioaddr
);
576 * Hardware start transmission.
577 * Send a packet to media from the upper layer.
580 static netdev_tx_t
uli526x_start_xmit(struct sk_buff
*skb
,
581 struct net_device
*dev
)
583 struct uli526x_board_info
*db
= netdev_priv(dev
);
584 struct tx_desc
*txptr
;
587 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
589 /* Resource flag check */
590 netif_stop_queue(dev
);
592 /* Too large packet check */
593 if (skb
->len
> MAX_PACKET_SIZE
) {
594 pr_err("big packet = %d\n", (u16
)skb
->len
);
599 spin_lock_irqsave(&db
->lock
, flags
);
601 /* No Tx resource check, it never happen nromally */
602 if (db
->tx_packet_cnt
>= TX_FREE_DESC_CNT
) {
603 spin_unlock_irqrestore(&db
->lock
, flags
);
604 pr_err("No Tx resource %ld\n", db
->tx_packet_cnt
);
605 return NETDEV_TX_BUSY
;
608 /* Disable NIC interrupt */
609 outl(0, dev
->base_addr
+ DCR7
);
611 /* transmit this packet */
612 txptr
= db
->tx_insert_ptr
;
613 skb_copy_from_linear_data(skb
, txptr
->tx_buf_ptr
, skb
->len
);
614 txptr
->tdes1
= cpu_to_le32(0xe1000000 | skb
->len
);
616 /* Point to next transmit free descriptor */
617 db
->tx_insert_ptr
= txptr
->next_tx_desc
;
619 /* Transmit Packet Process */
620 if ( (db
->tx_packet_cnt
< TX_DESC_CNT
) ) {
621 txptr
->tdes0
= cpu_to_le32(0x80000000); /* Set owner bit */
622 db
->tx_packet_cnt
++; /* Ready to send */
623 outl(0x1, dev
->base_addr
+ DCR1
); /* Issue Tx polling */
624 dev
->trans_start
= jiffies
; /* saved time stamp */
627 /* Tx resource check */
628 if ( db
->tx_packet_cnt
< TX_FREE_DESC_CNT
)
629 netif_wake_queue(dev
);
631 /* Restore CR7 to enable interrupt */
632 spin_unlock_irqrestore(&db
->lock
, flags
);
633 outl(db
->cr7_data
, dev
->base_addr
+ DCR7
);
643 * Stop the interface.
644 * The interface is stopped when it is brought.
647 static int uli526x_stop(struct net_device
*dev
)
649 struct uli526x_board_info
*db
= netdev_priv(dev
);
650 unsigned long ioaddr
= dev
->base_addr
;
652 ULI526X_DBUG(0, "uli526x_stop", 0);
655 netif_stop_queue(dev
);
658 del_timer_sync(&db
->timer
);
660 /* Reset & stop ULI526X board */
661 outl(ULI526X_RESET
, ioaddr
+ DCR0
);
663 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x8000, db
->chip_id
);
666 free_irq(dev
->irq
, dev
);
668 /* free allocated rx buffer */
669 uli526x_free_rxbuffer(db
);
672 /* show statistic counter */
673 printk(DRV_NAME
": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
674 db
->tx_fifo_underrun
, db
->tx_excessive_collision
,
675 db
->tx_late_collision
, db
->tx_no_carrier
, db
->tx_loss_carrier
,
676 db
->tx_jabber_timeout
, db
->reset_count
, db
->reset_cr8
,
677 db
->reset_fatal
, db
->reset_TXtimeout
);
685 * M5261/M5263 insterrupt handler
686 * receive the packet to upper layer, free the transmitted packet
689 static irqreturn_t
uli526x_interrupt(int irq
, void *dev_id
)
691 struct net_device
*dev
= dev_id
;
692 struct uli526x_board_info
*db
= netdev_priv(dev
);
693 unsigned long ioaddr
= dev
->base_addr
;
696 spin_lock_irqsave(&db
->lock
, flags
);
697 outl(0, ioaddr
+ DCR7
);
699 /* Got ULI526X status */
700 db
->cr5_data
= inl(ioaddr
+ DCR5
);
701 outl(db
->cr5_data
, ioaddr
+ DCR5
);
702 if ( !(db
->cr5_data
& 0x180c1) ) {
703 /* Restore CR7 to enable interrupt mask */
704 outl(db
->cr7_data
, ioaddr
+ DCR7
);
705 spin_unlock_irqrestore(&db
->lock
, flags
);
709 /* Check system status */
710 if (db
->cr5_data
& 0x2000) {
711 /* system bus error happen */
712 ULI526X_DBUG(1, "System bus error happen. CR5=", db
->cr5_data
);
714 db
->wait_reset
= 1; /* Need to RESET */
715 spin_unlock_irqrestore(&db
->lock
, flags
);
719 /* Received the coming packet */
720 if ( (db
->cr5_data
& 0x40) && db
->rx_avail_cnt
)
721 uli526x_rx_packet(dev
, db
);
723 /* reallocate rx descriptor buffer */
724 if (db
->rx_avail_cnt
<RX_DESC_CNT
)
725 allocate_rx_buffer(db
);
727 /* Free the transmitted descriptor */
728 if ( db
->cr5_data
& 0x01)
729 uli526x_free_tx_pkt(dev
, db
);
731 /* Restore CR7 to enable interrupt mask */
732 outl(db
->cr7_data
, ioaddr
+ DCR7
);
734 spin_unlock_irqrestore(&db
->lock
, flags
);
738 #ifdef CONFIG_NET_POLL_CONTROLLER
739 static void uli526x_poll(struct net_device
*dev
)
741 /* ISR grabs the irqsave lock, so this should be safe */
742 uli526x_interrupt(dev
->irq
, dev
);
747 * Free TX resource after TX complete
750 static void uli526x_free_tx_pkt(struct net_device
*dev
,
751 struct uli526x_board_info
* db
)
753 struct tx_desc
*txptr
;
756 txptr
= db
->tx_remove_ptr
;
757 while(db
->tx_packet_cnt
) {
758 tdes0
= le32_to_cpu(txptr
->tdes0
);
759 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
760 if (tdes0
& 0x80000000)
763 /* A packet sent completed */
765 dev
->stats
.tx_packets
++;
767 /* Transmit statistic counter */
768 if ( tdes0
!= 0x7fffffff ) {
769 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
770 dev
->stats
.collisions
+= (tdes0
>> 3) & 0xf;
771 dev
->stats
.tx_bytes
+= le32_to_cpu(txptr
->tdes1
) & 0x7ff;
772 if (tdes0
& TDES0_ERR_MASK
) {
773 dev
->stats
.tx_errors
++;
774 if (tdes0
& 0x0002) { /* UnderRun */
775 db
->tx_fifo_underrun
++;
776 if ( !(db
->cr6_data
& CR6_SFT
) ) {
777 db
->cr6_data
= db
->cr6_data
| CR6_SFT
;
778 update_cr6(db
->cr6_data
, db
->ioaddr
);
782 db
->tx_excessive_collision
++;
784 db
->tx_late_collision
++;
788 db
->tx_loss_carrier
++;
790 db
->tx_jabber_timeout
++;
794 txptr
= txptr
->next_tx_desc
;
797 /* Update TX remove pointer to next */
798 db
->tx_remove_ptr
= txptr
;
800 /* Resource available check */
801 if ( db
->tx_packet_cnt
< TX_WAKE_DESC_CNT
)
802 netif_wake_queue(dev
); /* Active upper layer, send again */
807 * Receive the come packet and pass to upper layer
810 static void uli526x_rx_packet(struct net_device
*dev
, struct uli526x_board_info
* db
)
812 struct rx_desc
*rxptr
;
817 rxptr
= db
->rx_ready_ptr
;
819 while(db
->rx_avail_cnt
) {
820 rdes0
= le32_to_cpu(rxptr
->rdes0
);
821 if (rdes0
& 0x80000000) /* packet owner check */
827 db
->interval_rx_cnt
++;
829 pci_unmap_single(db
->pdev
, le32_to_cpu(rxptr
->rdes2
), RX_ALLOC_SIZE
, PCI_DMA_FROMDEVICE
);
830 if ( (rdes0
& 0x300) != 0x300) {
831 /* A packet without First/Last flag */
833 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0
);
834 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
836 /* A packet with First/Last flag */
837 rxlen
= ( (rdes0
>> 16) & 0x3fff) - 4;
839 /* error summary bit check */
840 if (rdes0
& 0x8000) {
841 /* This is a error packet */
842 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
843 dev
->stats
.rx_errors
++;
845 dev
->stats
.rx_fifo_errors
++;
847 dev
->stats
.rx_crc_errors
++;
849 dev
->stats
.rx_length_errors
++;
852 if ( !(rdes0
& 0x8000) ||
853 ((db
->cr6_data
& CR6_PM
) && (rxlen
>6)) ) {
854 skb
= rxptr
->rx_skb_ptr
;
856 /* Good packet, send to upper layer */
857 /* Shorst packet used new SKB */
858 if ( (rxlen
< RX_COPY_SIZE
) &&
859 ( (skb
= dev_alloc_skb(rxlen
+ 2) )
861 /* size less than COPY_SIZE, allocate a rxlen SKB */
862 skb_reserve(skb
, 2); /* 16byte align */
863 memcpy(skb_put(skb
, rxlen
),
864 skb_tail_pointer(rxptr
->rx_skb_ptr
),
866 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
870 skb
->protocol
= eth_type_trans(skb
, dev
);
872 dev
->stats
.rx_packets
++;
873 dev
->stats
.rx_bytes
+= rxlen
;
876 /* Reuse SKB buffer when the packet is error */
877 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0
);
878 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
882 rxptr
= rxptr
->next_rx_desc
;
885 db
->rx_ready_ptr
= rxptr
;
890 * Set ULI526X multicast address
893 static void uli526x_set_filter_mode(struct net_device
* dev
)
895 struct uli526x_board_info
*db
= netdev_priv(dev
);
898 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
899 spin_lock_irqsave(&db
->lock
, flags
);
901 if (dev
->flags
& IFF_PROMISC
) {
902 ULI526X_DBUG(0, "Enable PROM Mode", 0);
903 db
->cr6_data
|= CR6_PM
| CR6_PBF
;
904 update_cr6(db
->cr6_data
, db
->ioaddr
);
905 spin_unlock_irqrestore(&db
->lock
, flags
);
909 if (dev
->flags
& IFF_ALLMULTI
||
910 netdev_mc_count(dev
) > ULI5261_MAX_MULTICAST
) {
911 ULI526X_DBUG(0, "Pass all multicast address",
912 netdev_mc_count(dev
));
913 db
->cr6_data
&= ~(CR6_PM
| CR6_PBF
);
914 db
->cr6_data
|= CR6_PAM
;
915 spin_unlock_irqrestore(&db
->lock
, flags
);
919 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev
));
920 send_filter_frame(dev
, netdev_mc_count(dev
)); /* M5261/M5263 */
921 spin_unlock_irqrestore(&db
->lock
, flags
);
925 ULi_ethtool_gset(struct uli526x_board_info
*db
, struct ethtool_cmd
*ecmd
)
927 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
928 SUPPORTED_10baseT_Full
|
929 SUPPORTED_100baseT_Half
|
930 SUPPORTED_100baseT_Full
|
934 ecmd
->advertising
= (ADVERTISED_10baseT_Half
|
935 ADVERTISED_10baseT_Full
|
936 ADVERTISED_100baseT_Half
|
937 ADVERTISED_100baseT_Full
|
942 ecmd
->port
= PORT_MII
;
943 ecmd
->phy_address
= db
->phy_addr
;
945 ecmd
->transceiver
= XCVR_EXTERNAL
;
948 ecmd
->duplex
= DUPLEX_HALF
;
950 if(db
->op_mode
==ULI526X_100MHF
|| db
->op_mode
==ULI526X_100MFD
)
954 if(db
->op_mode
==ULI526X_10MFD
|| db
->op_mode
==ULI526X_100MFD
)
956 ecmd
->duplex
= DUPLEX_FULL
;
964 if (db
->media_mode
& ULI526X_AUTO
)
966 ecmd
->autoneg
= AUTONEG_ENABLE
;
970 static void netdev_get_drvinfo(struct net_device
*dev
,
971 struct ethtool_drvinfo
*info
)
973 struct uli526x_board_info
*np
= netdev_priv(dev
);
975 strcpy(info
->driver
, DRV_NAME
);
976 strcpy(info
->version
, DRV_VERSION
);
978 strcpy(info
->bus_info
, pci_name(np
->pdev
));
980 sprintf(info
->bus_info
, "EISA 0x%lx %d",
981 dev
->base_addr
, dev
->irq
);
984 static int netdev_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
) {
985 struct uli526x_board_info
*np
= netdev_priv(dev
);
987 ULi_ethtool_gset(np
, cmd
);
992 static u32
netdev_get_link(struct net_device
*dev
) {
993 struct uli526x_board_info
*np
= netdev_priv(dev
);
1001 static void uli526x_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1003 wol
->supported
= WAKE_PHY
| WAKE_MAGIC
;
1007 static const struct ethtool_ops netdev_ethtool_ops
= {
1008 .get_drvinfo
= netdev_get_drvinfo
,
1009 .get_settings
= netdev_get_settings
,
1010 .get_link
= netdev_get_link
,
1011 .get_wol
= uli526x_get_wol
,
1015 * A periodic timer routine
1016 * Dynamic media sense, allocate Rx buffer...
1019 static void uli526x_timer(unsigned long data
)
1022 unsigned char tmp_cr12
=0;
1023 struct net_device
*dev
= (struct net_device
*) data
;
1024 struct uli526x_board_info
*db
= netdev_priv(dev
);
1025 unsigned long flags
;
1028 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1029 spin_lock_irqsave(&db
->lock
, flags
);
1032 /* Dynamic reset ULI526X : system error or transmit time-out */
1033 tmp_cr8
= inl(db
->ioaddr
+ DCR8
);
1034 if ( (db
->interval_rx_cnt
==0) && (tmp_cr8
) ) {
1038 db
->interval_rx_cnt
= 0;
1040 /* TX polling kick monitor */
1041 if ( db
->tx_packet_cnt
&&
1042 time_after(jiffies
, dev
->trans_start
+ ULI526X_TX_KICK
) ) {
1043 outl(0x1, dev
->base_addr
+ DCR1
); // Tx polling again
1046 if ( time_after(jiffies
, dev
->trans_start
+ ULI526X_TX_TIMEOUT
) ) {
1047 db
->reset_TXtimeout
++;
1049 printk( "%s: Tx timeout - resetting\n",
1054 if (db
->wait_reset
) {
1055 ULI526X_DBUG(0, "Dynamic Reset device", db
->tx_packet_cnt
);
1057 uli526x_dynamic_reset(dev
);
1058 db
->timer
.expires
= ULI526X_TIMER_WUT
;
1059 add_timer(&db
->timer
);
1060 spin_unlock_irqrestore(&db
->lock
, flags
);
1064 /* Link status check, Dynamic media type change */
1065 if((phy_read(db
->ioaddr
, db
->phy_addr
, 5, db
->chip_id
) & 0x01e0)!=0)
1068 if ( !(tmp_cr12
& 0x3) && !db
->link_failed
) {
1070 ULI526X_DBUG(0, "Link Failed", tmp_cr12
);
1071 netif_carrier_off(dev
);
1072 pr_info("%s NIC Link is Down\n",dev
->name
);
1073 db
->link_failed
= 1;
1075 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1076 /* AUTO don't need */
1077 if ( !(db
->media_mode
& 0x8) )
1078 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x1000, db
->chip_id
);
1080 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1081 if (db
->media_mode
& ULI526X_AUTO
) {
1082 db
->cr6_data
&=~0x00000200; /* bit9=0, HD mode */
1083 update_cr6(db
->cr6_data
, db
->ioaddr
);
1086 if ((tmp_cr12
& 0x3) && db
->link_failed
) {
1087 ULI526X_DBUG(0, "Link link OK", tmp_cr12
);
1088 db
->link_failed
= 0;
1090 /* Auto Sense Speed */
1091 if ( (db
->media_mode
& ULI526X_AUTO
) &&
1092 uli526x_sense_speed(db
) )
1093 db
->link_failed
= 1;
1094 uli526x_process_mode(db
);
1096 if(db
->link_failed
==0)
1098 if(db
->op_mode
==ULI526X_100MHF
|| db
->op_mode
==ULI526X_100MFD
)
1102 if(db
->op_mode
==ULI526X_10MFD
|| db
->op_mode
==ULI526X_100MFD
)
1104 pr_info("%s NIC Link is Up %d Mbps Full duplex\n",dev
->name
,TmpSpeed
);
1108 pr_info("%s NIC Link is Up %d Mbps Half duplex\n",dev
->name
,TmpSpeed
);
1110 netif_carrier_on(dev
);
1112 /* SHOW_MEDIA_TYPE(db->op_mode); */
1114 else if(!(tmp_cr12
& 0x3) && db
->link_failed
)
1118 pr_info("%s NIC Link is Down\n",dev
->name
);
1119 netif_carrier_off(dev
);
1124 /* Timer active again */
1125 db
->timer
.expires
= ULI526X_TIMER_WUT
;
1126 add_timer(&db
->timer
);
1127 spin_unlock_irqrestore(&db
->lock
, flags
);
1132 * Stop ULI526X board
1133 * Free Tx/Rx allocated memory
1134 * Init system variable
1137 static void uli526x_reset_prepare(struct net_device
*dev
)
1139 struct uli526x_board_info
*db
= netdev_priv(dev
);
1141 /* Sopt MAC controller */
1142 db
->cr6_data
&= ~(CR6_RXSC
| CR6_TXSC
); /* Disable Tx/Rx */
1143 update_cr6(db
->cr6_data
, dev
->base_addr
);
1144 outl(0, dev
->base_addr
+ DCR7
); /* Disable Interrupt */
1145 outl(inl(dev
->base_addr
+ DCR5
), dev
->base_addr
+ DCR5
);
1147 /* Disable upper layer interface */
1148 netif_stop_queue(dev
);
1150 /* Free Rx Allocate buffer */
1151 uli526x_free_rxbuffer(db
);
1153 /* system variable init */
1154 db
->tx_packet_cnt
= 0;
1155 db
->rx_avail_cnt
= 0;
1156 db
->link_failed
= 1;
1163 * Dynamic reset the ULI526X board
1164 * Stop ULI526X board
1165 * Free Tx/Rx allocated memory
1166 * Reset ULI526X board
1167 * Re-initialize ULI526X board
1170 static void uli526x_dynamic_reset(struct net_device
*dev
)
1172 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1174 uli526x_reset_prepare(dev
);
1176 /* Re-initialize ULI526X board */
1179 /* Restart upper layer interface */
1180 netif_wake_queue(dev
);
1187 * Suspend the interface.
1190 static int uli526x_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1192 struct net_device
*dev
= pci_get_drvdata(pdev
);
1193 pci_power_t power_state
;
1196 ULI526X_DBUG(0, "uli526x_suspend", 0);
1198 if (!netdev_priv(dev
))
1201 pci_save_state(pdev
);
1203 if (!netif_running(dev
))
1206 netif_device_detach(dev
);
1207 uli526x_reset_prepare(dev
);
1209 power_state
= pci_choose_state(pdev
, state
);
1210 pci_enable_wake(pdev
, power_state
, 0);
1211 err
= pci_set_power_state(pdev
, power_state
);
1213 netif_device_attach(dev
);
1214 /* Re-initialize ULI526X board */
1216 /* Restart upper layer interface */
1217 netif_wake_queue(dev
);
1224 * Resume the interface.
1227 static int uli526x_resume(struct pci_dev
*pdev
)
1229 struct net_device
*dev
= pci_get_drvdata(pdev
);
1232 ULI526X_DBUG(0, "uli526x_resume", 0);
1234 if (!netdev_priv(dev
))
1237 pci_restore_state(pdev
);
1239 if (!netif_running(dev
))
1242 err
= pci_set_power_state(pdev
, PCI_D0
);
1244 dev_warn(&dev
->dev
, "Could not put device into D0\n");
1248 netif_device_attach(dev
);
1249 /* Re-initialize ULI526X board */
1251 /* Restart upper layer interface */
1252 netif_wake_queue(dev
);
1257 #else /* !CONFIG_PM */
1259 #define uli526x_suspend NULL
1260 #define uli526x_resume NULL
1262 #endif /* !CONFIG_PM */
1266 * free all allocated rx buffer
1269 static void uli526x_free_rxbuffer(struct uli526x_board_info
* db
)
1271 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1273 /* free allocated rx buffer */
1274 while (db
->rx_avail_cnt
) {
1275 dev_kfree_skb(db
->rx_ready_ptr
->rx_skb_ptr
);
1276 db
->rx_ready_ptr
= db
->rx_ready_ptr
->next_rx_desc
;
1283 * Reuse the SK buffer
1286 static void uli526x_reuse_skb(struct uli526x_board_info
*db
, struct sk_buff
* skb
)
1288 struct rx_desc
*rxptr
= db
->rx_insert_ptr
;
1290 if (!(rxptr
->rdes0
& cpu_to_le32(0x80000000))) {
1291 rxptr
->rx_skb_ptr
= skb
;
1292 rxptr
->rdes2
= cpu_to_le32(pci_map_single(db
->pdev
,
1293 skb_tail_pointer(skb
),
1295 PCI_DMA_FROMDEVICE
));
1297 rxptr
->rdes0
= cpu_to_le32(0x80000000);
1299 db
->rx_insert_ptr
= rxptr
->next_rx_desc
;
1301 ULI526X_DBUG(0, "SK Buffer reuse method error", db
->rx_avail_cnt
);
1306 * Initialize transmit/Receive descriptor
1307 * Using Chain structure, and allocate Tx/Rx buffer
1310 static void uli526x_descriptor_init(struct uli526x_board_info
*db
, unsigned long ioaddr
)
1312 struct tx_desc
*tmp_tx
;
1313 struct rx_desc
*tmp_rx
;
1314 unsigned char *tmp_buf
;
1315 dma_addr_t tmp_tx_dma
, tmp_rx_dma
;
1316 dma_addr_t tmp_buf_dma
;
1319 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1321 /* tx descriptor start pointer */
1322 db
->tx_insert_ptr
= db
->first_tx_desc
;
1323 db
->tx_remove_ptr
= db
->first_tx_desc
;
1324 outl(db
->first_tx_desc_dma
, ioaddr
+ DCR4
); /* TX DESC address */
1326 /* rx descriptor start pointer */
1327 db
->first_rx_desc
= (void *)db
->first_tx_desc
+ sizeof(struct tx_desc
) * TX_DESC_CNT
;
1328 db
->first_rx_desc_dma
= db
->first_tx_desc_dma
+ sizeof(struct tx_desc
) * TX_DESC_CNT
;
1329 db
->rx_insert_ptr
= db
->first_rx_desc
;
1330 db
->rx_ready_ptr
= db
->first_rx_desc
;
1331 outl(db
->first_rx_desc_dma
, ioaddr
+ DCR3
); /* RX DESC address */
1333 /* Init Transmit chain */
1334 tmp_buf
= db
->buf_pool_start
;
1335 tmp_buf_dma
= db
->buf_pool_dma_start
;
1336 tmp_tx_dma
= db
->first_tx_desc_dma
;
1337 for (tmp_tx
= db
->first_tx_desc
, i
= 0; i
< TX_DESC_CNT
; i
++, tmp_tx
++) {
1338 tmp_tx
->tx_buf_ptr
= tmp_buf
;
1339 tmp_tx
->tdes0
= cpu_to_le32(0);
1340 tmp_tx
->tdes1
= cpu_to_le32(0x81000000); /* IC, chain */
1341 tmp_tx
->tdes2
= cpu_to_le32(tmp_buf_dma
);
1342 tmp_tx_dma
+= sizeof(struct tx_desc
);
1343 tmp_tx
->tdes3
= cpu_to_le32(tmp_tx_dma
);
1344 tmp_tx
->next_tx_desc
= tmp_tx
+ 1;
1345 tmp_buf
= tmp_buf
+ TX_BUF_ALLOC
;
1346 tmp_buf_dma
= tmp_buf_dma
+ TX_BUF_ALLOC
;
1348 (--tmp_tx
)->tdes3
= cpu_to_le32(db
->first_tx_desc_dma
);
1349 tmp_tx
->next_tx_desc
= db
->first_tx_desc
;
1351 /* Init Receive descriptor chain */
1352 tmp_rx_dma
=db
->first_rx_desc_dma
;
1353 for (tmp_rx
= db
->first_rx_desc
, i
= 0; i
< RX_DESC_CNT
; i
++, tmp_rx
++) {
1354 tmp_rx
->rdes0
= cpu_to_le32(0);
1355 tmp_rx
->rdes1
= cpu_to_le32(0x01000600);
1356 tmp_rx_dma
+= sizeof(struct rx_desc
);
1357 tmp_rx
->rdes3
= cpu_to_le32(tmp_rx_dma
);
1358 tmp_rx
->next_rx_desc
= tmp_rx
+ 1;
1360 (--tmp_rx
)->rdes3
= cpu_to_le32(db
->first_rx_desc_dma
);
1361 tmp_rx
->next_rx_desc
= db
->first_rx_desc
;
1363 /* pre-allocate Rx buffer */
1364 allocate_rx_buffer(db
);
1370 * Firstly stop ULI526X, then written value and start
1373 static void update_cr6(u32 cr6_data
, unsigned long ioaddr
)
1376 outl(cr6_data
, ioaddr
+ DCR6
);
1382 * Send a setup frame for M5261/M5263
1383 * This setup frame initialize ULI526X address filter mode
1387 #define FLT_SHIFT 16
1392 static void send_filter_frame(struct net_device
*dev
, int mc_cnt
)
1394 struct uli526x_board_info
*db
= netdev_priv(dev
);
1395 struct dev_mc_list
*mcptr
;
1396 struct tx_desc
*txptr
;
1401 ULI526X_DBUG(0, "send_filter_frame()", 0);
1403 txptr
= db
->tx_insert_ptr
;
1404 suptr
= (u32
*) txptr
->tx_buf_ptr
;
1407 addrptr
= (u16
*) dev
->dev_addr
;
1408 *suptr
++ = addrptr
[0] << FLT_SHIFT
;
1409 *suptr
++ = addrptr
[1] << FLT_SHIFT
;
1410 *suptr
++ = addrptr
[2] << FLT_SHIFT
;
1412 /* broadcast address */
1413 *suptr
++ = 0xffff << FLT_SHIFT
;
1414 *suptr
++ = 0xffff << FLT_SHIFT
;
1415 *suptr
++ = 0xffff << FLT_SHIFT
;
1417 /* fit the multicast address */
1418 for (mcptr
= dev
->mc_list
, i
= 0; i
< mc_cnt
; i
++, mcptr
= mcptr
->next
) {
1419 addrptr
= (u16
*) mcptr
->dmi_addr
;
1420 *suptr
++ = addrptr
[0] << FLT_SHIFT
;
1421 *suptr
++ = addrptr
[1] << FLT_SHIFT
;
1422 *suptr
++ = addrptr
[2] << FLT_SHIFT
;
1426 *suptr
++ = 0xffff << FLT_SHIFT
;
1427 *suptr
++ = 0xffff << FLT_SHIFT
;
1428 *suptr
++ = 0xffff << FLT_SHIFT
;
1431 /* prepare the setup frame */
1432 db
->tx_insert_ptr
= txptr
->next_tx_desc
;
1433 txptr
->tdes1
= cpu_to_le32(0x890000c0);
1435 /* Resource Check and Send the setup packet */
1436 if (db
->tx_packet_cnt
< TX_DESC_CNT
) {
1437 /* Resource Empty */
1438 db
->tx_packet_cnt
++;
1439 txptr
->tdes0
= cpu_to_le32(0x80000000);
1440 update_cr6(db
->cr6_data
| 0x2000, dev
->base_addr
);
1441 outl(0x1, dev
->base_addr
+ DCR1
); /* Issue Tx polling */
1442 update_cr6(db
->cr6_data
, dev
->base_addr
);
1443 dev
->trans_start
= jiffies
;
1445 pr_err("No Tx resource - Send_filter_frame!\n");
1450 * Allocate rx buffer,
1451 * As possible as allocate maxiumn Rx buffer
1454 static void allocate_rx_buffer(struct uli526x_board_info
*db
)
1456 struct rx_desc
*rxptr
;
1457 struct sk_buff
*skb
;
1459 rxptr
= db
->rx_insert_ptr
;
1461 while(db
->rx_avail_cnt
< RX_DESC_CNT
) {
1462 if ( ( skb
= dev_alloc_skb(RX_ALLOC_SIZE
) ) == NULL
)
1464 rxptr
->rx_skb_ptr
= skb
; /* FIXME (?) */
1465 rxptr
->rdes2
= cpu_to_le32(pci_map_single(db
->pdev
,
1466 skb_tail_pointer(skb
),
1468 PCI_DMA_FROMDEVICE
));
1470 rxptr
->rdes0
= cpu_to_le32(0x80000000);
1471 rxptr
= rxptr
->next_rx_desc
;
1475 db
->rx_insert_ptr
= rxptr
;
1480 * Read one word data from the serial ROM
1483 static u16
read_srom_word(long ioaddr
, int offset
)
1487 long cr9_ioaddr
= ioaddr
+ DCR9
;
1489 outl(CR9_SROM_READ
, cr9_ioaddr
);
1490 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
1492 /* Send the Read Command 110b */
1493 SROM_CLK_WRITE(SROM_DATA_1
, cr9_ioaddr
);
1494 SROM_CLK_WRITE(SROM_DATA_1
, cr9_ioaddr
);
1495 SROM_CLK_WRITE(SROM_DATA_0
, cr9_ioaddr
);
1497 /* Send the offset */
1498 for (i
= 5; i
>= 0; i
--) {
1499 srom_data
= (offset
& (1 << i
)) ? SROM_DATA_1
: SROM_DATA_0
;
1500 SROM_CLK_WRITE(srom_data
, cr9_ioaddr
);
1503 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
1505 for (i
= 16; i
> 0; i
--) {
1506 outl(CR9_SROM_READ
| CR9_SRCS
| CR9_SRCLK
, cr9_ioaddr
);
1508 srom_data
= (srom_data
<< 1) | ((inl(cr9_ioaddr
) & CR9_CRDOUT
) ? 1 : 0);
1509 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
1513 outl(CR9_SROM_READ
, cr9_ioaddr
);
1519 * Auto sense the media mode
1522 static u8
uli526x_sense_speed(struct uli526x_board_info
* db
)
1527 phy_mode
= phy_read(db
->ioaddr
, db
->phy_addr
, 1, db
->chip_id
);
1528 phy_mode
= phy_read(db
->ioaddr
, db
->phy_addr
, 1, db
->chip_id
);
1530 if ( (phy_mode
& 0x24) == 0x24 ) {
1532 phy_mode
= ((phy_read(db
->ioaddr
, db
->phy_addr
, 5, db
->chip_id
) & 0x01e0)<<7);
1535 else if(phy_mode
&0x4000)
1537 else if(phy_mode
&0x2000)
1542 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1544 case 0x1000: db
->op_mode
= ULI526X_10MHF
; break;
1545 case 0x2000: db
->op_mode
= ULI526X_10MFD
; break;
1546 case 0x4000: db
->op_mode
= ULI526X_100MHF
; break;
1547 case 0x8000: db
->op_mode
= ULI526X_100MFD
; break;
1548 default: db
->op_mode
= ULI526X_10MHF
; ErrFlag
= 1; break;
1551 db
->op_mode
= ULI526X_10MHF
;
1552 ULI526X_DBUG(0, "Link Failed :", phy_mode
);
1561 * Set 10/100 phyxcer capability
1562 * AUTO mode : phyxcer register4 is NIC capability
1563 * Force mode: phyxcer register4 is the force media
1566 static void uli526x_set_phyxcer(struct uli526x_board_info
*db
)
1570 /* Phyxcer capability setting */
1571 phy_reg
= phy_read(db
->ioaddr
, db
->phy_addr
, 4, db
->chip_id
) & ~0x01e0;
1573 if (db
->media_mode
& ULI526X_AUTO
) {
1575 phy_reg
|= db
->PHY_reg4
;
1578 switch(db
->media_mode
) {
1579 case ULI526X_10MHF
: phy_reg
|= 0x20; break;
1580 case ULI526X_10MFD
: phy_reg
|= 0x40; break;
1581 case ULI526X_100MHF
: phy_reg
|= 0x80; break;
1582 case ULI526X_100MFD
: phy_reg
|= 0x100; break;
1587 /* Write new capability to Phyxcer Reg4 */
1588 if ( !(phy_reg
& 0x01e0)) {
1589 phy_reg
|=db
->PHY_reg4
;
1590 db
->media_mode
|=ULI526X_AUTO
;
1592 phy_write(db
->ioaddr
, db
->phy_addr
, 4, phy_reg
, db
->chip_id
);
1594 /* Restart Auto-Negotiation */
1595 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x1200, db
->chip_id
);
1602 AUTO mode : PHY controller in Auto-negotiation Mode
1603 * Force mode: PHY controller in force mode with HUB
1604 * N-way force capability with SWITCH
1607 static void uli526x_process_mode(struct uli526x_board_info
*db
)
1611 /* Full Duplex Mode Check */
1612 if (db
->op_mode
& 0x4)
1613 db
->cr6_data
|= CR6_FDM
; /* Set Full Duplex Bit */
1615 db
->cr6_data
&= ~CR6_FDM
; /* Clear Full Duplex Bit */
1617 update_cr6(db
->cr6_data
, db
->ioaddr
);
1619 /* 10/100M phyxcer force mode need */
1620 if ( !(db
->media_mode
& 0x8)) {
1622 phy_reg
= phy_read(db
->ioaddr
, db
->phy_addr
, 6, db
->chip_id
);
1623 if ( !(phy_reg
& 0x1) ) {
1624 /* parter without N-Way capability */
1626 switch(db
->op_mode
) {
1627 case ULI526X_10MHF
: phy_reg
= 0x0; break;
1628 case ULI526X_10MFD
: phy_reg
= 0x100; break;
1629 case ULI526X_100MHF
: phy_reg
= 0x2000; break;
1630 case ULI526X_100MFD
: phy_reg
= 0x2100; break;
1632 phy_write(db
->ioaddr
, db
->phy_addr
, 0, phy_reg
, db
->chip_id
);
1639 * Write a word to Phy register
1642 static void phy_write(unsigned long iobase
, u8 phy_addr
, u8 offset
, u16 phy_data
, u32 chip_id
)
1645 unsigned long ioaddr
;
1647 if(chip_id
== PCI_ULI5263_ID
)
1649 phy_writeby_cr10(iobase
, phy_addr
, offset
, phy_data
);
1652 /* M5261/M5263 Chip */
1653 ioaddr
= iobase
+ DCR9
;
1655 /* Send 33 synchronization clock to Phy controller */
1656 for (i
= 0; i
< 35; i
++)
1657 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1659 /* Send start command(01) to Phy */
1660 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1661 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1663 /* Send write command(01) to Phy */
1664 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1665 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1667 /* Send Phy address */
1668 for (i
= 0x10; i
> 0; i
= i
>> 1)
1669 phy_write_1bit(ioaddr
, phy_addr
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1671 /* Send register address */
1672 for (i
= 0x10; i
> 0; i
= i
>> 1)
1673 phy_write_1bit(ioaddr
, offset
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1675 /* written trasnition */
1676 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1677 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1679 /* Write a word data to PHY controller */
1680 for ( i
= 0x8000; i
> 0; i
>>= 1)
1681 phy_write_1bit(ioaddr
, phy_data
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1687 * Read a word data from phy register
1690 static u16
phy_read(unsigned long iobase
, u8 phy_addr
, u8 offset
, u32 chip_id
)
1694 unsigned long ioaddr
;
1696 if(chip_id
== PCI_ULI5263_ID
)
1697 return phy_readby_cr10(iobase
, phy_addr
, offset
);
1698 /* M5261/M5263 Chip */
1699 ioaddr
= iobase
+ DCR9
;
1701 /* Send 33 synchronization clock to Phy controller */
1702 for (i
= 0; i
< 35; i
++)
1703 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1705 /* Send start command(01) to Phy */
1706 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1707 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1709 /* Send read command(10) to Phy */
1710 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1711 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1713 /* Send Phy address */
1714 for (i
= 0x10; i
> 0; i
= i
>> 1)
1715 phy_write_1bit(ioaddr
, phy_addr
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1717 /* Send register address */
1718 for (i
= 0x10; i
> 0; i
= i
>> 1)
1719 phy_write_1bit(ioaddr
, offset
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1721 /* Skip transition state */
1722 phy_read_1bit(ioaddr
, chip_id
);
1724 /* read 16bit data */
1725 for (phy_data
= 0, i
= 0; i
< 16; i
++) {
1727 phy_data
|= phy_read_1bit(ioaddr
, chip_id
);
1733 static u16
phy_readby_cr10(unsigned long iobase
, u8 phy_addr
, u8 offset
)
1735 unsigned long ioaddr
,cr10_value
;
1737 ioaddr
= iobase
+ DCR10
;
1738 cr10_value
= phy_addr
;
1739 cr10_value
= (cr10_value
<<5) + offset
;
1740 cr10_value
= (cr10_value
<<16) + 0x08000000;
1741 outl(cr10_value
,ioaddr
);
1745 cr10_value
= inl(ioaddr
);
1746 if(cr10_value
&0x10000000)
1749 return (cr10_value
&0x0ffff);
1752 static void phy_writeby_cr10(unsigned long iobase
, u8 phy_addr
, u8 offset
, u16 phy_data
)
1754 unsigned long ioaddr
,cr10_value
;
1756 ioaddr
= iobase
+ DCR10
;
1757 cr10_value
= phy_addr
;
1758 cr10_value
= (cr10_value
<<5) + offset
;
1759 cr10_value
= (cr10_value
<<16) + 0x04000000 + phy_data
;
1760 outl(cr10_value
,ioaddr
);
1764 * Write one bit data to Phy Controller
1767 static void phy_write_1bit(unsigned long ioaddr
, u32 phy_data
, u32 chip_id
)
1769 outl(phy_data
, ioaddr
); /* MII Clock Low */
1771 outl(phy_data
| MDCLKH
, ioaddr
); /* MII Clock High */
1773 outl(phy_data
, ioaddr
); /* MII Clock Low */
1779 * Read one bit phy data from PHY controller
1782 static u16
phy_read_1bit(unsigned long ioaddr
, u32 chip_id
)
1786 outl(0x50000 , ioaddr
);
1788 phy_data
= ( inl(ioaddr
) >> 19 ) & 0x1;
1789 outl(0x40000 , ioaddr
);
1796 static DEFINE_PCI_DEVICE_TABLE(uli526x_pci_tbl
) = {
1797 { 0x10B9, 0x5261, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, PCI_ULI5261_ID
},
1798 { 0x10B9, 0x5263, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, PCI_ULI5263_ID
},
1801 MODULE_DEVICE_TABLE(pci
, uli526x_pci_tbl
);
1804 static struct pci_driver uli526x_driver
= {
1806 .id_table
= uli526x_pci_tbl
,
1807 .probe
= uli526x_init_one
,
1808 .remove
= __devexit_p(uli526x_remove_one
),
1809 .suspend
= uli526x_suspend
,
1810 .resume
= uli526x_resume
,
1813 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1814 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1815 MODULE_LICENSE("GPL");
1817 module_param(debug
, int, 0644);
1818 module_param(mode
, int, 0);
1819 module_param(cr6set
, int, 0);
1820 MODULE_PARM_DESC(debug
, "ULi M5261/M5263 enable debugging (0-1)");
1821 MODULE_PARM_DESC(mode
, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1824 * when user used insmod to add module, system invoked init_module()
1825 * to register the services.
1828 static int __init
uli526x_init_module(void)
1832 printed_version
= 1;
1834 ULI526X_DBUG(0, "init_module() ", debug
);
1837 uli526x_debug
= debug
; /* set debug flag */
1839 uli526x_cr6_user_set
= cr6set
;
1843 case ULI526X_100MHF
:
1845 case ULI526X_100MFD
:
1846 uli526x_media_mode
= mode
;
1849 uli526x_media_mode
= ULI526X_AUTO
;
1853 return pci_register_driver(&uli526x_driver
);
1859 * when user used rmmod to delete module, system invoked clean_module()
1860 * to un-register all registered services.
1863 static void __exit
uli526x_cleanup_module(void)
1865 ULI526X_DBUG(0, "uli526x_clean_module() ", debug
);
1866 pci_unregister_driver(&uli526x_driver
);
1869 module_init(uli526x_init_module
);
1870 module_exit(uli526x_cleanup_module
);