2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
15 #define DRV_NAME "uli526x"
16 #define DRV_VERSION "0.9.3"
17 #define DRV_RELDATE "2005-7-29"
19 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/string.h>
23 #include <linux/timer.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
36 #include <linux/dma-mapping.h>
38 #include <asm/processor.h>
39 #include <asm/bitops.h>
42 #include <asm/uaccess.h>
45 /* Board/System/Debug information/definition ---------------- */
46 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
49 #define ULI526X_IO_SIZE 0x100
50 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55 #define TX_BUF_ALLOC 0x600
56 #define RX_ALLOC_SIZE 0x620
57 #define ULI526X_RESET 1
59 #define CR6_DEFAULT 0x22200000
60 #define CR7_DEFAULT 0x180c1
61 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63 #define MAX_PACKET_SIZE 1514
64 #define ULI5261_MAX_MULTICAST 14
65 #define RX_COPY_SIZE 100
66 #define MAX_CHECK_PACKET 0x8000
68 #define ULI526X_10MHF 0
69 #define ULI526X_100MHF 1
70 #define ULI526X_10MFD 4
71 #define ULI526X_100MFD 5
72 #define ULI526X_AUTO 8
74 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
81 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
85 #define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
87 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
90 /* CR9 definition: SROM/MII */
91 #define CR9_SROM_READ 0x4800
94 #define CR9_CRDOUT 0x8
95 #define SROM_DATA_0 0x0
96 #define SROM_DATA_1 0x4
97 #define PHY_DATA_1 0x20000
98 #define PHY_DATA_0 0x00000
99 #define MDCLKH 0x10000
101 #define PHY_POWER_DOWN 0x800
103 #define SROM_V41_CODE 0x14
105 #define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
113 /* Structure/enum declaration ------------------------------- */
115 u32 tdes0
, tdes1
, tdes2
, tdes3
; /* Data for the card */
116 char *tx_buf_ptr
; /* Data for us */
117 struct tx_desc
*next_tx_desc
;
118 } __attribute__(( aligned(32) ));
121 u32 rdes0
, rdes1
, rdes2
, rdes3
; /* Data for the card */
122 struct sk_buff
*rx_skb_ptr
; /* Data for us */
123 struct rx_desc
*next_rx_desc
;
124 } __attribute__(( aligned(32) ));
126 struct uli526x_board_info
{
127 u32 chip_id
; /* Chip vendor/Device ID */
128 struct net_device
*next_dev
; /* next device */
129 struct pci_dev
*pdev
; /* PCI device */
132 long ioaddr
; /* I/O base address */
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr
; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start
; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr
; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma
;
144 dma_addr_t first_rx_desc_dma
;
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr
; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start
; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr
; /* descriptor pool memory */
150 struct tx_desc
*first_tx_desc
;
151 struct tx_desc
*tx_insert_ptr
;
152 struct tx_desc
*tx_remove_ptr
;
153 struct rx_desc
*first_rx_desc
;
154 struct rx_desc
*rx_insert_ptr
;
155 struct rx_desc
*rx_ready_ptr
; /* packet come pointer */
156 unsigned long tx_packet_cnt
; /* transmitted packet count */
157 unsigned long rx_avail_cnt
; /* available rx descriptor count */
158 unsigned long interval_rx_cnt
; /* rx packet count a callback time */
161 u16 NIC_capability
; /* NIC media capability */
162 u16 PHY_reg4
; /* Saved Phyxcer register 4 value */
164 u8 media_mode
; /* user specify media mode */
165 u8 op_mode
; /* real work media mode */
167 u8 link_failed
; /* Ever link failed */
168 u8 wait_reset
; /* Hardware failed, need to reset */
169 struct timer_list timer
;
171 /* System defined statistic counter */
172 struct net_device_stats stats
;
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun
;
176 unsigned long tx_loss_carrier
;
177 unsigned long tx_no_carrier
;
178 unsigned long tx_late_collision
;
179 unsigned long tx_excessive_collision
;
180 unsigned long tx_jabber_timeout
;
181 unsigned long reset_count
;
182 unsigned long reset_cr8
;
183 unsigned long reset_fatal
;
184 unsigned long reset_TXtimeout
;
187 unsigned char srom
[128];
191 enum uli526x_offsets
{
192 DCR0
= 0x00, DCR1
= 0x08, DCR2
= 0x10, DCR3
= 0x18, DCR4
= 0x20,
193 DCR5
= 0x28, DCR6
= 0x30, DCR7
= 0x38, DCR8
= 0x40, DCR9
= 0x48,
194 DCR10
= 0x50, DCR11
= 0x58, DCR12
= 0x60, DCR13
= 0x68, DCR14
= 0x70,
198 enum uli526x_CR6_bits
{
199 CR6_RXSC
= 0x2, CR6_PBF
= 0x8, CR6_PM
= 0x40, CR6_PAM
= 0x80,
200 CR6_FDM
= 0x200, CR6_TXSC
= 0x2000, CR6_STI
= 0x100000,
201 CR6_SFT
= 0x200000, CR6_RXA
= 0x40000000, CR6_NO_PURGE
= 0x20000000
204 /* Global variable declaration ----------------------------- */
205 static int __devinitdata printed_version
;
206 static char version
[] __devinitdata
=
207 KERN_INFO DRV_NAME
": ULi M5261/M5263 net driver, version "
208 DRV_VERSION
" (" DRV_RELDATE
")\n";
210 static int uli526x_debug
;
211 static unsigned char uli526x_media_mode
= ULI526X_AUTO
;
212 static u32 uli526x_cr6_user_set
;
214 /* For module input parameter */
219 /* function declaration ------------------------------------- */
220 static int uli526x_open(struct net_device
*);
221 static int uli526x_start_xmit(struct sk_buff
*, struct net_device
*);
222 static int uli526x_stop(struct net_device
*);
223 static struct net_device_stats
* uli526x_get_stats(struct net_device
*);
224 static void uli526x_set_filter_mode(struct net_device
*);
225 static const struct ethtool_ops netdev_ethtool_ops
;
226 static u16
read_srom_word(long, int);
227 static irqreturn_t
uli526x_interrupt(int, void *);
228 static void uli526x_descriptor_init(struct uli526x_board_info
*, unsigned long);
229 static void allocate_rx_buffer(struct uli526x_board_info
*);
230 static void update_cr6(u32
, unsigned long);
231 static void send_filter_frame(struct net_device
*, int);
232 static u16
phy_read(unsigned long, u8
, u8
, u32
);
233 static u16
phy_readby_cr10(unsigned long, u8
, u8
);
234 static void phy_write(unsigned long, u8
, u8
, u16
, u32
);
235 static void phy_writeby_cr10(unsigned long, u8
, u8
, u16
);
236 static void phy_write_1bit(unsigned long, u32
, u32
);
237 static u16
phy_read_1bit(unsigned long, u32
);
238 static u8
uli526x_sense_speed(struct uli526x_board_info
*);
239 static void uli526x_process_mode(struct uli526x_board_info
*);
240 static void uli526x_timer(unsigned long);
241 static void uli526x_rx_packet(struct net_device
*, struct uli526x_board_info
*);
242 static void uli526x_free_tx_pkt(struct net_device
*, struct uli526x_board_info
*);
243 static void uli526x_reuse_skb(struct uli526x_board_info
*, struct sk_buff
*);
244 static void uli526x_dynamic_reset(struct net_device
*);
245 static void uli526x_free_rxbuffer(struct uli526x_board_info
*);
246 static void uli526x_init(struct net_device
*);
247 static void uli526x_set_phyxcer(struct uli526x_board_info
*);
249 /* ULI526X network board routine ---------------------------- */
252 * Search ULI526X board, allocate space and register it
255 static int __devinit
uli526x_init_one (struct pci_dev
*pdev
,
256 const struct pci_device_id
*ent
)
258 struct uli526x_board_info
*db
; /* board information structure */
259 struct net_device
*dev
;
261 DECLARE_MAC_BUF(mac
);
263 ULI526X_DBUG(0, "uli526x_init_one()", 0);
265 if (!printed_version
++)
268 /* Init network device */
269 dev
= alloc_etherdev(sizeof(*db
));
272 SET_NETDEV_DEV(dev
, &pdev
->dev
);
274 if (pci_set_dma_mask(pdev
, DMA_32BIT_MASK
)) {
275 printk(KERN_WARNING DRV_NAME
": 32-bit PCI DMA not available.\n");
280 /* Enable Master/IO access, Disable memory access */
281 err
= pci_enable_device(pdev
);
285 if (!pci_resource_start(pdev
, 0)) {
286 printk(KERN_ERR DRV_NAME
": I/O base is zero\n");
288 goto err_out_disable
;
291 if (pci_resource_len(pdev
, 0) < (ULI526X_IO_SIZE
) ) {
292 printk(KERN_ERR DRV_NAME
": Allocated I/O size too small\n");
294 goto err_out_disable
;
297 if (pci_request_regions(pdev
, DRV_NAME
)) {
298 printk(KERN_ERR DRV_NAME
": Failed to request PCI regions\n");
300 goto err_out_disable
;
303 /* Init system & device */
304 db
= netdev_priv(dev
);
306 /* Allocate Tx/Rx descriptor memory */
307 db
->desc_pool_ptr
= pci_alloc_consistent(pdev
, sizeof(struct tx_desc
) * DESC_ALL_CNT
+ 0x20, &db
->desc_pool_dma_ptr
);
308 if(db
->desc_pool_ptr
== NULL
)
313 db
->buf_pool_ptr
= pci_alloc_consistent(pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4, &db
->buf_pool_dma_ptr
);
314 if(db
->buf_pool_ptr
== NULL
)
320 db
->first_tx_desc
= (struct tx_desc
*) db
->desc_pool_ptr
;
321 db
->first_tx_desc_dma
= db
->desc_pool_dma_ptr
;
322 db
->buf_pool_start
= db
->buf_pool_ptr
;
323 db
->buf_pool_dma_start
= db
->buf_pool_dma_ptr
;
325 db
->chip_id
= ent
->driver_data
;
326 db
->ioaddr
= pci_resource_start(pdev
, 0);
331 dev
->base_addr
= db
->ioaddr
;
332 dev
->irq
= pdev
->irq
;
333 pci_set_drvdata(pdev
, dev
);
335 /* Register some necessary functions */
336 dev
->open
= &uli526x_open
;
337 dev
->hard_start_xmit
= &uli526x_start_xmit
;
338 dev
->stop
= &uli526x_stop
;
339 dev
->get_stats
= &uli526x_get_stats
;
340 dev
->set_multicast_list
= &uli526x_set_filter_mode
;
341 dev
->ethtool_ops
= &netdev_ethtool_ops
;
342 spin_lock_init(&db
->lock
);
345 /* read 64 word srom data */
346 for (i
= 0; i
< 64; i
++)
347 ((u16
*) db
->srom
)[i
] = cpu_to_le16(read_srom_word(db
->ioaddr
, i
));
349 /* Set Node address */
350 if(((u16
*) db
->srom
)[0] == 0xffff || ((u16
*) db
->srom
)[0] == 0) /* SROM absent, so read MAC address from ID Table */
352 outl(0x10000, db
->ioaddr
+ DCR0
); //Diagnosis mode
353 outl(0x1c0, db
->ioaddr
+ DCR13
); //Reset dianostic pointer port
354 outl(0, db
->ioaddr
+ DCR14
); //Clear reset port
355 outl(0x10, db
->ioaddr
+ DCR14
); //Reset ID Table pointer
356 outl(0, db
->ioaddr
+ DCR14
); //Clear reset port
357 outl(0, db
->ioaddr
+ DCR13
); //Clear CR13
358 outl(0x1b0, db
->ioaddr
+ DCR13
); //Select ID Table access port
359 //Read MAC address from CR14
360 for (i
= 0; i
< 6; i
++)
361 dev
->dev_addr
[i
] = inl(db
->ioaddr
+ DCR14
);
363 outl(0, db
->ioaddr
+ DCR13
); //Clear CR13
364 outl(0, db
->ioaddr
+ DCR0
); //Clear CR0
369 for (i
= 0; i
< 6; i
++)
370 dev
->dev_addr
[i
] = db
->srom
[20 + i
];
372 err
= register_netdev (dev
);
376 printk(KERN_INFO
"%s: ULi M%04lx at pci%s, %s, irq %d.\n",
377 dev
->name
,ent
->driver_data
>> 16,pci_name(pdev
),
378 print_mac(mac
, dev
->dev_addr
), dev
->irq
);
380 pci_set_master(pdev
);
385 pci_release_regions(pdev
);
387 if(db
->desc_pool_ptr
)
388 pci_free_consistent(pdev
, sizeof(struct tx_desc
) * DESC_ALL_CNT
+ 0x20,
389 db
->desc_pool_ptr
, db
->desc_pool_dma_ptr
);
391 if(db
->buf_pool_ptr
!= NULL
)
392 pci_free_consistent(pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4,
393 db
->buf_pool_ptr
, db
->buf_pool_dma_ptr
);
395 pci_disable_device(pdev
);
397 pci_set_drvdata(pdev
, NULL
);
404 static void __devexit
uli526x_remove_one (struct pci_dev
*pdev
)
406 struct net_device
*dev
= pci_get_drvdata(pdev
);
407 struct uli526x_board_info
*db
= netdev_priv(dev
);
409 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
411 pci_free_consistent(db
->pdev
, sizeof(struct tx_desc
) *
412 DESC_ALL_CNT
+ 0x20, db
->desc_pool_ptr
,
413 db
->desc_pool_dma_ptr
);
414 pci_free_consistent(db
->pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4,
415 db
->buf_pool_ptr
, db
->buf_pool_dma_ptr
);
416 unregister_netdev(dev
);
417 pci_release_regions(pdev
);
418 free_netdev(dev
); /* free board information */
419 pci_set_drvdata(pdev
, NULL
);
420 pci_disable_device(pdev
);
421 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
426 * Open the interface.
427 * The interface is opened whenever "ifconfig" activates it.
430 static int uli526x_open(struct net_device
*dev
)
433 struct uli526x_board_info
*db
= netdev_priv(dev
);
435 ULI526X_DBUG(0, "uli526x_open", 0);
437 ret
= request_irq(dev
->irq
, &uli526x_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
441 /* system variable init */
442 db
->cr6_data
= CR6_DEFAULT
| uli526x_cr6_user_set
;
443 db
->tx_packet_cnt
= 0;
444 db
->rx_avail_cnt
= 0;
446 netif_carrier_off(dev
);
449 db
->NIC_capability
= 0xf; /* All capability*/
450 db
->PHY_reg4
= 0x1e0;
452 /* CR6 operation mode decision */
453 db
->cr6_data
|= ULI526X_TXTH_256
;
454 db
->cr0_data
= CR0_DEFAULT
;
456 /* Initialize ULI526X board */
459 /* Active System Interface */
460 netif_wake_queue(dev
);
462 /* set and active a timer process */
463 init_timer(&db
->timer
);
464 db
->timer
.expires
= ULI526X_TIMER_WUT
+ HZ
* 2;
465 db
->timer
.data
= (unsigned long)dev
;
466 db
->timer
.function
= &uli526x_timer
;
467 add_timer(&db
->timer
);
473 /* Initialize ULI526X board
474 * Reset ULI526X board
475 * Initialize TX/Rx descriptor chain structure
476 * Send the set-up frame
477 * Enable Tx/Rx machine
480 static void uli526x_init(struct net_device
*dev
)
482 struct uli526x_board_info
*db
= netdev_priv(dev
);
483 unsigned long ioaddr
= db
->ioaddr
;
488 ULI526X_DBUG(0, "uli526x_init()", 0);
490 /* Reset M526x MAC controller */
491 outl(ULI526X_RESET
, ioaddr
+ DCR0
); /* RESET MAC */
493 outl(db
->cr0_data
, ioaddr
+ DCR0
);
496 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
498 for(phy_tmp
=0;phy_tmp
<32;phy_tmp
++)
500 phy_value
=phy_read(db
->ioaddr
,phy_tmp
,3,db
->chip_id
);//peer add
501 if(phy_value
!= 0xffff&&phy_value
!=0)
503 db
->phy_addr
= phy_tmp
;
508 printk(KERN_WARNING
"Can not find the phy address!!!");
509 /* Parser SROM and media mode */
510 db
->media_mode
= uli526x_media_mode
;
512 /* Phyxcer capability setting */
513 phy_reg_reset
= phy_read(db
->ioaddr
, db
->phy_addr
, 0, db
->chip_id
);
514 phy_reg_reset
= (phy_reg_reset
| 0x8000);
515 phy_write(db
->ioaddr
, db
->phy_addr
, 0, phy_reg_reset
, db
->chip_id
);
518 /* Process Phyxcer Media Mode */
519 uli526x_set_phyxcer(db
);
521 /* Media Mode Process */
522 if ( !(db
->media_mode
& ULI526X_AUTO
) )
523 db
->op_mode
= db
->media_mode
; /* Force Mode */
525 /* Initialize Transmit/Receive decriptor and CR3/4 */
526 uli526x_descriptor_init(db
, ioaddr
);
528 /* Init CR6 to program M526X operation */
529 update_cr6(db
->cr6_data
, ioaddr
);
531 /* Send setup frame */
532 send_filter_frame(dev
, dev
->mc_count
); /* M5261/M5263 */
534 /* Init CR7, interrupt active bit */
535 db
->cr7_data
= CR7_DEFAULT
;
536 outl(db
->cr7_data
, ioaddr
+ DCR7
);
538 /* Init CR15, Tx jabber and Rx watchdog timer */
539 outl(db
->cr15_data
, ioaddr
+ DCR15
);
541 /* Enable ULI526X Tx/Rx function */
542 db
->cr6_data
|= CR6_RXSC
| CR6_TXSC
;
543 update_cr6(db
->cr6_data
, ioaddr
);
548 * Hardware start transmission.
549 * Send a packet to media from the upper layer.
552 static int uli526x_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
554 struct uli526x_board_info
*db
= netdev_priv(dev
);
555 struct tx_desc
*txptr
;
558 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
560 /* Resource flag check */
561 netif_stop_queue(dev
);
563 /* Too large packet check */
564 if (skb
->len
> MAX_PACKET_SIZE
) {
565 printk(KERN_ERR DRV_NAME
": big packet = %d\n", (u16
)skb
->len
);
570 spin_lock_irqsave(&db
->lock
, flags
);
572 /* No Tx resource check, it never happen nromally */
573 if (db
->tx_packet_cnt
>= TX_FREE_DESC_CNT
) {
574 spin_unlock_irqrestore(&db
->lock
, flags
);
575 printk(KERN_ERR DRV_NAME
": No Tx resource %ld\n", db
->tx_packet_cnt
);
579 /* Disable NIC interrupt */
580 outl(0, dev
->base_addr
+ DCR7
);
582 /* transmit this packet */
583 txptr
= db
->tx_insert_ptr
;
584 skb_copy_from_linear_data(skb
, txptr
->tx_buf_ptr
, skb
->len
);
585 txptr
->tdes1
= cpu_to_le32(0xe1000000 | skb
->len
);
587 /* Point to next transmit free descriptor */
588 db
->tx_insert_ptr
= txptr
->next_tx_desc
;
590 /* Transmit Packet Process */
591 if ( (db
->tx_packet_cnt
< TX_DESC_CNT
) ) {
592 txptr
->tdes0
= cpu_to_le32(0x80000000); /* Set owner bit */
593 db
->tx_packet_cnt
++; /* Ready to send */
594 outl(0x1, dev
->base_addr
+ DCR1
); /* Issue Tx polling */
595 dev
->trans_start
= jiffies
; /* saved time stamp */
598 /* Tx resource check */
599 if ( db
->tx_packet_cnt
< TX_FREE_DESC_CNT
)
600 netif_wake_queue(dev
);
602 /* Restore CR7 to enable interrupt */
603 spin_unlock_irqrestore(&db
->lock
, flags
);
604 outl(db
->cr7_data
, dev
->base_addr
+ DCR7
);
614 * Stop the interface.
615 * The interface is stopped when it is brought.
618 static int uli526x_stop(struct net_device
*dev
)
620 struct uli526x_board_info
*db
= netdev_priv(dev
);
621 unsigned long ioaddr
= dev
->base_addr
;
623 ULI526X_DBUG(0, "uli526x_stop", 0);
626 netif_stop_queue(dev
);
629 del_timer_sync(&db
->timer
);
631 /* Reset & stop ULI526X board */
632 outl(ULI526X_RESET
, ioaddr
+ DCR0
);
634 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x8000, db
->chip_id
);
637 free_irq(dev
->irq
, dev
);
639 /* free allocated rx buffer */
640 uli526x_free_rxbuffer(db
);
643 /* show statistic counter */
644 printk(DRV_NAME
": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
645 db
->tx_fifo_underrun
, db
->tx_excessive_collision
,
646 db
->tx_late_collision
, db
->tx_no_carrier
, db
->tx_loss_carrier
,
647 db
->tx_jabber_timeout
, db
->reset_count
, db
->reset_cr8
,
648 db
->reset_fatal
, db
->reset_TXtimeout
);
656 * M5261/M5263 insterrupt handler
657 * receive the packet to upper layer, free the transmitted packet
660 static irqreturn_t
uli526x_interrupt(int irq
, void *dev_id
)
662 struct net_device
*dev
= dev_id
;
663 struct uli526x_board_info
*db
= netdev_priv(dev
);
664 unsigned long ioaddr
= dev
->base_addr
;
668 ULI526X_DBUG(1, "uli526x_interrupt() without DEVICE arg", 0);
672 spin_lock_irqsave(&db
->lock
, flags
);
673 outl(0, ioaddr
+ DCR7
);
675 /* Got ULI526X status */
676 db
->cr5_data
= inl(ioaddr
+ DCR5
);
677 outl(db
->cr5_data
, ioaddr
+ DCR5
);
678 if ( !(db
->cr5_data
& 0x180c1) ) {
679 spin_unlock_irqrestore(&db
->lock
, flags
);
680 outl(db
->cr7_data
, ioaddr
+ DCR7
);
684 /* Check system status */
685 if (db
->cr5_data
& 0x2000) {
686 /* system bus error happen */
687 ULI526X_DBUG(1, "System bus error happen. CR5=", db
->cr5_data
);
689 db
->wait_reset
= 1; /* Need to RESET */
690 spin_unlock_irqrestore(&db
->lock
, flags
);
694 /* Received the coming packet */
695 if ( (db
->cr5_data
& 0x40) && db
->rx_avail_cnt
)
696 uli526x_rx_packet(dev
, db
);
698 /* reallocate rx descriptor buffer */
699 if (db
->rx_avail_cnt
<RX_DESC_CNT
)
700 allocate_rx_buffer(db
);
702 /* Free the transmitted descriptor */
703 if ( db
->cr5_data
& 0x01)
704 uli526x_free_tx_pkt(dev
, db
);
706 /* Restore CR7 to enable interrupt mask */
707 outl(db
->cr7_data
, ioaddr
+ DCR7
);
709 spin_unlock_irqrestore(&db
->lock
, flags
);
715 * Free TX resource after TX complete
718 static void uli526x_free_tx_pkt(struct net_device
*dev
, struct uli526x_board_info
* db
)
720 struct tx_desc
*txptr
;
723 txptr
= db
->tx_remove_ptr
;
724 while(db
->tx_packet_cnt
) {
725 tdes0
= le32_to_cpu(txptr
->tdes0
);
726 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
727 if (tdes0
& 0x80000000)
730 /* A packet sent completed */
732 db
->stats
.tx_packets
++;
734 /* Transmit statistic counter */
735 if ( tdes0
!= 0x7fffffff ) {
736 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
737 db
->stats
.collisions
+= (tdes0
>> 3) & 0xf;
738 db
->stats
.tx_bytes
+= le32_to_cpu(txptr
->tdes1
) & 0x7ff;
739 if (tdes0
& TDES0_ERR_MASK
) {
740 db
->stats
.tx_errors
++;
741 if (tdes0
& 0x0002) { /* UnderRun */
742 db
->tx_fifo_underrun
++;
743 if ( !(db
->cr6_data
& CR6_SFT
) ) {
744 db
->cr6_data
= db
->cr6_data
| CR6_SFT
;
745 update_cr6(db
->cr6_data
, db
->ioaddr
);
749 db
->tx_excessive_collision
++;
751 db
->tx_late_collision
++;
755 db
->tx_loss_carrier
++;
757 db
->tx_jabber_timeout
++;
761 txptr
= txptr
->next_tx_desc
;
764 /* Update TX remove pointer to next */
765 db
->tx_remove_ptr
= txptr
;
767 /* Resource available check */
768 if ( db
->tx_packet_cnt
< TX_WAKE_DESC_CNT
)
769 netif_wake_queue(dev
); /* Active upper layer, send again */
774 * Receive the come packet and pass to upper layer
777 static void uli526x_rx_packet(struct net_device
*dev
, struct uli526x_board_info
* db
)
779 struct rx_desc
*rxptr
;
784 rxptr
= db
->rx_ready_ptr
;
786 while(db
->rx_avail_cnt
) {
787 rdes0
= le32_to_cpu(rxptr
->rdes0
);
788 if (rdes0
& 0x80000000) /* packet owner check */
794 db
->interval_rx_cnt
++;
796 pci_unmap_single(db
->pdev
, le32_to_cpu(rxptr
->rdes2
), RX_ALLOC_SIZE
, PCI_DMA_FROMDEVICE
);
797 if ( (rdes0
& 0x300) != 0x300) {
798 /* A packet without First/Last flag */
800 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0
);
801 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
803 /* A packet with First/Last flag */
804 rxlen
= ( (rdes0
>> 16) & 0x3fff) - 4;
806 /* error summary bit check */
807 if (rdes0
& 0x8000) {
808 /* This is a error packet */
809 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
810 db
->stats
.rx_errors
++;
812 db
->stats
.rx_fifo_errors
++;
814 db
->stats
.rx_crc_errors
++;
816 db
->stats
.rx_length_errors
++;
819 if ( !(rdes0
& 0x8000) ||
820 ((db
->cr6_data
& CR6_PM
) && (rxlen
>6)) ) {
821 skb
= rxptr
->rx_skb_ptr
;
823 /* Good packet, send to upper layer */
824 /* Shorst packet used new SKB */
825 if ( (rxlen
< RX_COPY_SIZE
) &&
826 ( (skb
= dev_alloc_skb(rxlen
+ 2) )
828 /* size less than COPY_SIZE, allocate a rxlen SKB */
829 skb_reserve(skb
, 2); /* 16byte align */
830 memcpy(skb_put(skb
, rxlen
),
831 skb_tail_pointer(rxptr
->rx_skb_ptr
),
833 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
837 skb
->protocol
= eth_type_trans(skb
, dev
);
839 dev
->last_rx
= jiffies
;
840 db
->stats
.rx_packets
++;
841 db
->stats
.rx_bytes
+= rxlen
;
844 /* Reuse SKB buffer when the packet is error */
845 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0
);
846 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
850 rxptr
= rxptr
->next_rx_desc
;
853 db
->rx_ready_ptr
= rxptr
;
858 * Get statistics from driver.
861 static struct net_device_stats
* uli526x_get_stats(struct net_device
*dev
)
863 struct uli526x_board_info
*db
= netdev_priv(dev
);
865 ULI526X_DBUG(0, "uli526x_get_stats", 0);
871 * Set ULI526X multicast address
874 static void uli526x_set_filter_mode(struct net_device
* dev
)
876 struct uli526x_board_info
*db
= dev
->priv
;
879 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
880 spin_lock_irqsave(&db
->lock
, flags
);
882 if (dev
->flags
& IFF_PROMISC
) {
883 ULI526X_DBUG(0, "Enable PROM Mode", 0);
884 db
->cr6_data
|= CR6_PM
| CR6_PBF
;
885 update_cr6(db
->cr6_data
, db
->ioaddr
);
886 spin_unlock_irqrestore(&db
->lock
, flags
);
890 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_count
> ULI5261_MAX_MULTICAST
) {
891 ULI526X_DBUG(0, "Pass all multicast address", dev
->mc_count
);
892 db
->cr6_data
&= ~(CR6_PM
| CR6_PBF
);
893 db
->cr6_data
|= CR6_PAM
;
894 spin_unlock_irqrestore(&db
->lock
, flags
);
898 ULI526X_DBUG(0, "Set multicast address", dev
->mc_count
);
899 send_filter_frame(dev
, dev
->mc_count
); /* M5261/M5263 */
900 spin_unlock_irqrestore(&db
->lock
, flags
);
904 ULi_ethtool_gset(struct uli526x_board_info
*db
, struct ethtool_cmd
*ecmd
)
906 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
907 SUPPORTED_10baseT_Full
|
908 SUPPORTED_100baseT_Half
|
909 SUPPORTED_100baseT_Full
|
913 ecmd
->advertising
= (ADVERTISED_10baseT_Half
|
914 ADVERTISED_10baseT_Full
|
915 ADVERTISED_100baseT_Half
|
916 ADVERTISED_100baseT_Full
|
921 ecmd
->port
= PORT_MII
;
922 ecmd
->phy_address
= db
->phy_addr
;
924 ecmd
->transceiver
= XCVR_EXTERNAL
;
927 ecmd
->duplex
= DUPLEX_HALF
;
929 if(db
->op_mode
==ULI526X_100MHF
|| db
->op_mode
==ULI526X_100MFD
)
933 if(db
->op_mode
==ULI526X_10MFD
|| db
->op_mode
==ULI526X_100MFD
)
935 ecmd
->duplex
= DUPLEX_FULL
;
943 if (db
->media_mode
& ULI526X_AUTO
)
945 ecmd
->autoneg
= AUTONEG_ENABLE
;
949 static void netdev_get_drvinfo(struct net_device
*dev
,
950 struct ethtool_drvinfo
*info
)
952 struct uli526x_board_info
*np
= netdev_priv(dev
);
954 strcpy(info
->driver
, DRV_NAME
);
955 strcpy(info
->version
, DRV_VERSION
);
957 strcpy(info
->bus_info
, pci_name(np
->pdev
));
959 sprintf(info
->bus_info
, "EISA 0x%lx %d",
960 dev
->base_addr
, dev
->irq
);
963 static int netdev_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
) {
964 struct uli526x_board_info
*np
= netdev_priv(dev
);
966 ULi_ethtool_gset(np
, cmd
);
971 static u32
netdev_get_link(struct net_device
*dev
) {
972 struct uli526x_board_info
*np
= netdev_priv(dev
);
980 static void uli526x_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
982 wol
->supported
= WAKE_PHY
| WAKE_MAGIC
;
986 static const struct ethtool_ops netdev_ethtool_ops
= {
987 .get_drvinfo
= netdev_get_drvinfo
,
988 .get_settings
= netdev_get_settings
,
989 .get_link
= netdev_get_link
,
990 .get_wol
= uli526x_get_wol
,
994 * A periodic timer routine
995 * Dynamic media sense, allocate Rx buffer...
998 static void uli526x_timer(unsigned long data
)
1001 unsigned char tmp_cr12
=0;
1002 struct net_device
*dev
= (struct net_device
*) data
;
1003 struct uli526x_board_info
*db
= netdev_priv(dev
);
1004 unsigned long flags
;
1007 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1008 spin_lock_irqsave(&db
->lock
, flags
);
1011 /* Dynamic reset ULI526X : system error or transmit time-out */
1012 tmp_cr8
= inl(db
->ioaddr
+ DCR8
);
1013 if ( (db
->interval_rx_cnt
==0) && (tmp_cr8
) ) {
1017 db
->interval_rx_cnt
= 0;
1019 /* TX polling kick monitor */
1020 if ( db
->tx_packet_cnt
&&
1021 time_after(jiffies
, dev
->trans_start
+ ULI526X_TX_KICK
) ) {
1022 outl(0x1, dev
->base_addr
+ DCR1
); // Tx polling again
1025 if ( time_after(jiffies
, dev
->trans_start
+ ULI526X_TX_TIMEOUT
) ) {
1026 db
->reset_TXtimeout
++;
1028 printk( "%s: Tx timeout - resetting\n",
1033 if (db
->wait_reset
) {
1034 ULI526X_DBUG(0, "Dynamic Reset device", db
->tx_packet_cnt
);
1036 uli526x_dynamic_reset(dev
);
1037 db
->timer
.expires
= ULI526X_TIMER_WUT
;
1038 add_timer(&db
->timer
);
1039 spin_unlock_irqrestore(&db
->lock
, flags
);
1043 /* Link status check, Dynamic media type change */
1044 if((phy_read(db
->ioaddr
, db
->phy_addr
, 5, db
->chip_id
) & 0x01e0)!=0)
1047 if ( !(tmp_cr12
& 0x3) && !db
->link_failed
) {
1049 ULI526X_DBUG(0, "Link Failed", tmp_cr12
);
1050 netif_carrier_off(dev
);
1051 printk(KERN_INFO
"uli526x: %s NIC Link is Down\n",dev
->name
);
1052 db
->link_failed
= 1;
1054 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1055 /* AUTO don't need */
1056 if ( !(db
->media_mode
& 0x8) )
1057 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x1000, db
->chip_id
);
1059 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1060 if (db
->media_mode
& ULI526X_AUTO
) {
1061 db
->cr6_data
&=~0x00000200; /* bit9=0, HD mode */
1062 update_cr6(db
->cr6_data
, db
->ioaddr
);
1065 if ((tmp_cr12
& 0x3) && db
->link_failed
) {
1066 ULI526X_DBUG(0, "Link link OK", tmp_cr12
);
1067 db
->link_failed
= 0;
1069 /* Auto Sense Speed */
1070 if ( (db
->media_mode
& ULI526X_AUTO
) &&
1071 uli526x_sense_speed(db
) )
1072 db
->link_failed
= 1;
1073 uli526x_process_mode(db
);
1075 if(db
->link_failed
==0)
1077 if(db
->op_mode
==ULI526X_100MHF
|| db
->op_mode
==ULI526X_100MFD
)
1081 if(db
->op_mode
==ULI526X_10MFD
|| db
->op_mode
==ULI526X_100MFD
)
1083 printk(KERN_INFO
"uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev
->name
,TmpSpeed
);
1087 printk(KERN_INFO
"uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev
->name
,TmpSpeed
);
1089 netif_carrier_on(dev
);
1091 /* SHOW_MEDIA_TYPE(db->op_mode); */
1093 else if(!(tmp_cr12
& 0x3) && db
->link_failed
)
1097 printk(KERN_INFO
"uli526x: %s NIC Link is Down\n",dev
->name
);
1098 netif_carrier_off(dev
);
1103 /* Timer active again */
1104 db
->timer
.expires
= ULI526X_TIMER_WUT
;
1105 add_timer(&db
->timer
);
1106 spin_unlock_irqrestore(&db
->lock
, flags
);
1111 * Stop ULI526X board
1112 * Free Tx/Rx allocated memory
1113 * Init system variable
1116 static void uli526x_reset_prepare(struct net_device
*dev
)
1118 struct uli526x_board_info
*db
= netdev_priv(dev
);
1120 /* Sopt MAC controller */
1121 db
->cr6_data
&= ~(CR6_RXSC
| CR6_TXSC
); /* Disable Tx/Rx */
1122 update_cr6(db
->cr6_data
, dev
->base_addr
);
1123 outl(0, dev
->base_addr
+ DCR7
); /* Disable Interrupt */
1124 outl(inl(dev
->base_addr
+ DCR5
), dev
->base_addr
+ DCR5
);
1126 /* Disable upper layer interface */
1127 netif_stop_queue(dev
);
1129 /* Free Rx Allocate buffer */
1130 uli526x_free_rxbuffer(db
);
1132 /* system variable init */
1133 db
->tx_packet_cnt
= 0;
1134 db
->rx_avail_cnt
= 0;
1135 db
->link_failed
= 1;
1142 * Dynamic reset the ULI526X board
1143 * Stop ULI526X board
1144 * Free Tx/Rx allocated memory
1145 * Reset ULI526X board
1146 * Re-initialize ULI526X board
1149 static void uli526x_dynamic_reset(struct net_device
*dev
)
1151 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1153 uli526x_reset_prepare(dev
);
1155 /* Re-initialize ULI526X board */
1158 /* Restart upper layer interface */
1159 netif_wake_queue(dev
);
1166 * Suspend the interface.
1169 static int uli526x_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1171 struct net_device
*dev
= pci_get_drvdata(pdev
);
1172 pci_power_t power_state
;
1175 ULI526X_DBUG(0, "uli526x_suspend", 0);
1177 if (!netdev_priv(dev
))
1180 pci_save_state(pdev
);
1182 if (!netif_running(dev
))
1185 netif_device_detach(dev
);
1186 uli526x_reset_prepare(dev
);
1188 power_state
= pci_choose_state(pdev
, state
);
1189 pci_enable_wake(pdev
, power_state
, 0);
1190 err
= pci_set_power_state(pdev
, power_state
);
1192 netif_device_attach(dev
);
1193 /* Re-initialize ULI526X board */
1195 /* Restart upper layer interface */
1196 netif_wake_queue(dev
);
1203 * Resume the interface.
1206 static int uli526x_resume(struct pci_dev
*pdev
)
1208 struct net_device
*dev
= pci_get_drvdata(pdev
);
1211 ULI526X_DBUG(0, "uli526x_resume", 0);
1213 if (!netdev_priv(dev
))
1216 pci_restore_state(pdev
);
1218 if (!netif_running(dev
))
1221 err
= pci_set_power_state(pdev
, PCI_D0
);
1223 printk(KERN_WARNING
"%s: Could not put device into D0\n",
1228 netif_device_attach(dev
);
1229 /* Re-initialize ULI526X board */
1231 /* Restart upper layer interface */
1232 netif_wake_queue(dev
);
1237 #else /* !CONFIG_PM */
1239 #define uli526x_suspend NULL
1240 #define uli526x_resume NULL
1242 #endif /* !CONFIG_PM */
1246 * free all allocated rx buffer
1249 static void uli526x_free_rxbuffer(struct uli526x_board_info
* db
)
1251 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1253 /* free allocated rx buffer */
1254 while (db
->rx_avail_cnt
) {
1255 dev_kfree_skb(db
->rx_ready_ptr
->rx_skb_ptr
);
1256 db
->rx_ready_ptr
= db
->rx_ready_ptr
->next_rx_desc
;
1263 * Reuse the SK buffer
1266 static void uli526x_reuse_skb(struct uli526x_board_info
*db
, struct sk_buff
* skb
)
1268 struct rx_desc
*rxptr
= db
->rx_insert_ptr
;
1270 if (!(rxptr
->rdes0
& cpu_to_le32(0x80000000))) {
1271 rxptr
->rx_skb_ptr
= skb
;
1272 rxptr
->rdes2
= cpu_to_le32(pci_map_single(db
->pdev
,
1273 skb_tail_pointer(skb
),
1275 PCI_DMA_FROMDEVICE
));
1277 rxptr
->rdes0
= cpu_to_le32(0x80000000);
1279 db
->rx_insert_ptr
= rxptr
->next_rx_desc
;
1281 ULI526X_DBUG(0, "SK Buffer reuse method error", db
->rx_avail_cnt
);
1286 * Initialize transmit/Receive descriptor
1287 * Using Chain structure, and allocate Tx/Rx buffer
1290 static void uli526x_descriptor_init(struct uli526x_board_info
*db
, unsigned long ioaddr
)
1292 struct tx_desc
*tmp_tx
;
1293 struct rx_desc
*tmp_rx
;
1294 unsigned char *tmp_buf
;
1295 dma_addr_t tmp_tx_dma
, tmp_rx_dma
;
1296 dma_addr_t tmp_buf_dma
;
1299 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1301 /* tx descriptor start pointer */
1302 db
->tx_insert_ptr
= db
->first_tx_desc
;
1303 db
->tx_remove_ptr
= db
->first_tx_desc
;
1304 outl(db
->first_tx_desc_dma
, ioaddr
+ DCR4
); /* TX DESC address */
1306 /* rx descriptor start pointer */
1307 db
->first_rx_desc
= (void *)db
->first_tx_desc
+ sizeof(struct tx_desc
) * TX_DESC_CNT
;
1308 db
->first_rx_desc_dma
= db
->first_tx_desc_dma
+ sizeof(struct tx_desc
) * TX_DESC_CNT
;
1309 db
->rx_insert_ptr
= db
->first_rx_desc
;
1310 db
->rx_ready_ptr
= db
->first_rx_desc
;
1311 outl(db
->first_rx_desc_dma
, ioaddr
+ DCR3
); /* RX DESC address */
1313 /* Init Transmit chain */
1314 tmp_buf
= db
->buf_pool_start
;
1315 tmp_buf_dma
= db
->buf_pool_dma_start
;
1316 tmp_tx_dma
= db
->first_tx_desc_dma
;
1317 for (tmp_tx
= db
->first_tx_desc
, i
= 0; i
< TX_DESC_CNT
; i
++, tmp_tx
++) {
1318 tmp_tx
->tx_buf_ptr
= tmp_buf
;
1319 tmp_tx
->tdes0
= cpu_to_le32(0);
1320 tmp_tx
->tdes1
= cpu_to_le32(0x81000000); /* IC, chain */
1321 tmp_tx
->tdes2
= cpu_to_le32(tmp_buf_dma
);
1322 tmp_tx_dma
+= sizeof(struct tx_desc
);
1323 tmp_tx
->tdes3
= cpu_to_le32(tmp_tx_dma
);
1324 tmp_tx
->next_tx_desc
= tmp_tx
+ 1;
1325 tmp_buf
= tmp_buf
+ TX_BUF_ALLOC
;
1326 tmp_buf_dma
= tmp_buf_dma
+ TX_BUF_ALLOC
;
1328 (--tmp_tx
)->tdes3
= cpu_to_le32(db
->first_tx_desc_dma
);
1329 tmp_tx
->next_tx_desc
= db
->first_tx_desc
;
1331 /* Init Receive descriptor chain */
1332 tmp_rx_dma
=db
->first_rx_desc_dma
;
1333 for (tmp_rx
= db
->first_rx_desc
, i
= 0; i
< RX_DESC_CNT
; i
++, tmp_rx
++) {
1334 tmp_rx
->rdes0
= cpu_to_le32(0);
1335 tmp_rx
->rdes1
= cpu_to_le32(0x01000600);
1336 tmp_rx_dma
+= sizeof(struct rx_desc
);
1337 tmp_rx
->rdes3
= cpu_to_le32(tmp_rx_dma
);
1338 tmp_rx
->next_rx_desc
= tmp_rx
+ 1;
1340 (--tmp_rx
)->rdes3
= cpu_to_le32(db
->first_rx_desc_dma
);
1341 tmp_rx
->next_rx_desc
= db
->first_rx_desc
;
1343 /* pre-allocate Rx buffer */
1344 allocate_rx_buffer(db
);
1350 * Firstly stop ULI526X, then written value and start
1353 static void update_cr6(u32 cr6_data
, unsigned long ioaddr
)
1356 outl(cr6_data
, ioaddr
+ DCR6
);
1362 * Send a setup frame for M5261/M5263
1363 * This setup frame initialize ULI526X address filter mode
1366 static void send_filter_frame(struct net_device
*dev
, int mc_cnt
)
1368 struct uli526x_board_info
*db
= netdev_priv(dev
);
1369 struct dev_mc_list
*mcptr
;
1370 struct tx_desc
*txptr
;
1375 ULI526X_DBUG(0, "send_filter_frame()", 0);
1377 txptr
= db
->tx_insert_ptr
;
1378 suptr
= (u32
*) txptr
->tx_buf_ptr
;
1381 addrptr
= (u16
*) dev
->dev_addr
;
1382 *suptr
++ = addrptr
[0];
1383 *suptr
++ = addrptr
[1];
1384 *suptr
++ = addrptr
[2];
1386 /* broadcast address */
1391 /* fit the multicast address */
1392 for (mcptr
= dev
->mc_list
, i
= 0; i
< mc_cnt
; i
++, mcptr
= mcptr
->next
) {
1393 addrptr
= (u16
*) mcptr
->dmi_addr
;
1394 *suptr
++ = addrptr
[0];
1395 *suptr
++ = addrptr
[1];
1396 *suptr
++ = addrptr
[2];
1405 /* prepare the setup frame */
1406 db
->tx_insert_ptr
= txptr
->next_tx_desc
;
1407 txptr
->tdes1
= cpu_to_le32(0x890000c0);
1409 /* Resource Check and Send the setup packet */
1410 if (db
->tx_packet_cnt
< TX_DESC_CNT
) {
1411 /* Resource Empty */
1412 db
->tx_packet_cnt
++;
1413 txptr
->tdes0
= cpu_to_le32(0x80000000);
1414 update_cr6(db
->cr6_data
| 0x2000, dev
->base_addr
);
1415 outl(0x1, dev
->base_addr
+ DCR1
); /* Issue Tx polling */
1416 update_cr6(db
->cr6_data
, dev
->base_addr
);
1417 dev
->trans_start
= jiffies
;
1419 printk(KERN_ERR DRV_NAME
": No Tx resource - Send_filter_frame!\n");
1424 * Allocate rx buffer,
1425 * As possible as allocate maxiumn Rx buffer
1428 static void allocate_rx_buffer(struct uli526x_board_info
*db
)
1430 struct rx_desc
*rxptr
;
1431 struct sk_buff
*skb
;
1433 rxptr
= db
->rx_insert_ptr
;
1435 while(db
->rx_avail_cnt
< RX_DESC_CNT
) {
1436 if ( ( skb
= dev_alloc_skb(RX_ALLOC_SIZE
) ) == NULL
)
1438 rxptr
->rx_skb_ptr
= skb
; /* FIXME (?) */
1439 rxptr
->rdes2
= cpu_to_le32(pci_map_single(db
->pdev
,
1440 skb_tail_pointer(skb
),
1442 PCI_DMA_FROMDEVICE
));
1444 rxptr
->rdes0
= cpu_to_le32(0x80000000);
1445 rxptr
= rxptr
->next_rx_desc
;
1449 db
->rx_insert_ptr
= rxptr
;
1454 * Read one word data from the serial ROM
1457 static u16
read_srom_word(long ioaddr
, int offset
)
1461 long cr9_ioaddr
= ioaddr
+ DCR9
;
1463 outl(CR9_SROM_READ
, cr9_ioaddr
);
1464 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
1466 /* Send the Read Command 110b */
1467 SROM_CLK_WRITE(SROM_DATA_1
, cr9_ioaddr
);
1468 SROM_CLK_WRITE(SROM_DATA_1
, cr9_ioaddr
);
1469 SROM_CLK_WRITE(SROM_DATA_0
, cr9_ioaddr
);
1471 /* Send the offset */
1472 for (i
= 5; i
>= 0; i
--) {
1473 srom_data
= (offset
& (1 << i
)) ? SROM_DATA_1
: SROM_DATA_0
;
1474 SROM_CLK_WRITE(srom_data
, cr9_ioaddr
);
1477 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
1479 for (i
= 16; i
> 0; i
--) {
1480 outl(CR9_SROM_READ
| CR9_SRCS
| CR9_SRCLK
, cr9_ioaddr
);
1482 srom_data
= (srom_data
<< 1) | ((inl(cr9_ioaddr
) & CR9_CRDOUT
) ? 1 : 0);
1483 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
1487 outl(CR9_SROM_READ
, cr9_ioaddr
);
1493 * Auto sense the media mode
1496 static u8
uli526x_sense_speed(struct uli526x_board_info
* db
)
1501 phy_mode
= phy_read(db
->ioaddr
, db
->phy_addr
, 1, db
->chip_id
);
1502 phy_mode
= phy_read(db
->ioaddr
, db
->phy_addr
, 1, db
->chip_id
);
1504 if ( (phy_mode
& 0x24) == 0x24 ) {
1506 phy_mode
= ((phy_read(db
->ioaddr
, db
->phy_addr
, 5, db
->chip_id
) & 0x01e0)<<7);
1509 else if(phy_mode
&0x4000)
1511 else if(phy_mode
&0x2000)
1516 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1518 case 0x1000: db
->op_mode
= ULI526X_10MHF
; break;
1519 case 0x2000: db
->op_mode
= ULI526X_10MFD
; break;
1520 case 0x4000: db
->op_mode
= ULI526X_100MHF
; break;
1521 case 0x8000: db
->op_mode
= ULI526X_100MFD
; break;
1522 default: db
->op_mode
= ULI526X_10MHF
; ErrFlag
= 1; break;
1525 db
->op_mode
= ULI526X_10MHF
;
1526 ULI526X_DBUG(0, "Link Failed :", phy_mode
);
1535 * Set 10/100 phyxcer capability
1536 * AUTO mode : phyxcer register4 is NIC capability
1537 * Force mode: phyxcer register4 is the force media
1540 static void uli526x_set_phyxcer(struct uli526x_board_info
*db
)
1544 /* Phyxcer capability setting */
1545 phy_reg
= phy_read(db
->ioaddr
, db
->phy_addr
, 4, db
->chip_id
) & ~0x01e0;
1547 if (db
->media_mode
& ULI526X_AUTO
) {
1549 phy_reg
|= db
->PHY_reg4
;
1552 switch(db
->media_mode
) {
1553 case ULI526X_10MHF
: phy_reg
|= 0x20; break;
1554 case ULI526X_10MFD
: phy_reg
|= 0x40; break;
1555 case ULI526X_100MHF
: phy_reg
|= 0x80; break;
1556 case ULI526X_100MFD
: phy_reg
|= 0x100; break;
1561 /* Write new capability to Phyxcer Reg4 */
1562 if ( !(phy_reg
& 0x01e0)) {
1563 phy_reg
|=db
->PHY_reg4
;
1564 db
->media_mode
|=ULI526X_AUTO
;
1566 phy_write(db
->ioaddr
, db
->phy_addr
, 4, phy_reg
, db
->chip_id
);
1568 /* Restart Auto-Negotiation */
1569 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x1200, db
->chip_id
);
1576 AUTO mode : PHY controller in Auto-negotiation Mode
1577 * Force mode: PHY controller in force mode with HUB
1578 * N-way force capability with SWITCH
1581 static void uli526x_process_mode(struct uli526x_board_info
*db
)
1585 /* Full Duplex Mode Check */
1586 if (db
->op_mode
& 0x4)
1587 db
->cr6_data
|= CR6_FDM
; /* Set Full Duplex Bit */
1589 db
->cr6_data
&= ~CR6_FDM
; /* Clear Full Duplex Bit */
1591 update_cr6(db
->cr6_data
, db
->ioaddr
);
1593 /* 10/100M phyxcer force mode need */
1594 if ( !(db
->media_mode
& 0x8)) {
1596 phy_reg
= phy_read(db
->ioaddr
, db
->phy_addr
, 6, db
->chip_id
);
1597 if ( !(phy_reg
& 0x1) ) {
1598 /* parter without N-Way capability */
1600 switch(db
->op_mode
) {
1601 case ULI526X_10MHF
: phy_reg
= 0x0; break;
1602 case ULI526X_10MFD
: phy_reg
= 0x100; break;
1603 case ULI526X_100MHF
: phy_reg
= 0x2000; break;
1604 case ULI526X_100MFD
: phy_reg
= 0x2100; break;
1606 phy_write(db
->ioaddr
, db
->phy_addr
, 0, phy_reg
, db
->chip_id
);
1607 phy_write(db
->ioaddr
, db
->phy_addr
, 0, phy_reg
, db
->chip_id
);
1614 * Write a word to Phy register
1617 static void phy_write(unsigned long iobase
, u8 phy_addr
, u8 offset
, u16 phy_data
, u32 chip_id
)
1620 unsigned long ioaddr
;
1622 if(chip_id
== PCI_ULI5263_ID
)
1624 phy_writeby_cr10(iobase
, phy_addr
, offset
, phy_data
);
1627 /* M5261/M5263 Chip */
1628 ioaddr
= iobase
+ DCR9
;
1630 /* Send 33 synchronization clock to Phy controller */
1631 for (i
= 0; i
< 35; i
++)
1632 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1634 /* Send start command(01) to Phy */
1635 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1636 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1638 /* Send write command(01) to Phy */
1639 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1640 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1642 /* Send Phy address */
1643 for (i
= 0x10; i
> 0; i
= i
>> 1)
1644 phy_write_1bit(ioaddr
, phy_addr
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1646 /* Send register address */
1647 for (i
= 0x10; i
> 0; i
= i
>> 1)
1648 phy_write_1bit(ioaddr
, offset
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1650 /* written trasnition */
1651 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1652 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1654 /* Write a word data to PHY controller */
1655 for ( i
= 0x8000; i
> 0; i
>>= 1)
1656 phy_write_1bit(ioaddr
, phy_data
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1662 * Read a word data from phy register
1665 static u16
phy_read(unsigned long iobase
, u8 phy_addr
, u8 offset
, u32 chip_id
)
1669 unsigned long ioaddr
;
1671 if(chip_id
== PCI_ULI5263_ID
)
1672 return phy_readby_cr10(iobase
, phy_addr
, offset
);
1673 /* M5261/M5263 Chip */
1674 ioaddr
= iobase
+ DCR9
;
1676 /* Send 33 synchronization clock to Phy controller */
1677 for (i
= 0; i
< 35; i
++)
1678 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1680 /* Send start command(01) to Phy */
1681 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1682 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1684 /* Send read command(10) to Phy */
1685 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1686 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1688 /* Send Phy address */
1689 for (i
= 0x10; i
> 0; i
= i
>> 1)
1690 phy_write_1bit(ioaddr
, phy_addr
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1692 /* Send register address */
1693 for (i
= 0x10; i
> 0; i
= i
>> 1)
1694 phy_write_1bit(ioaddr
, offset
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1696 /* Skip transition state */
1697 phy_read_1bit(ioaddr
, chip_id
);
1699 /* read 16bit data */
1700 for (phy_data
= 0, i
= 0; i
< 16; i
++) {
1702 phy_data
|= phy_read_1bit(ioaddr
, chip_id
);
1708 static u16
phy_readby_cr10(unsigned long iobase
, u8 phy_addr
, u8 offset
)
1710 unsigned long ioaddr
,cr10_value
;
1712 ioaddr
= iobase
+ DCR10
;
1713 cr10_value
= phy_addr
;
1714 cr10_value
= (cr10_value
<<5) + offset
;
1715 cr10_value
= (cr10_value
<<16) + 0x08000000;
1716 outl(cr10_value
,ioaddr
);
1720 cr10_value
= inl(ioaddr
);
1721 if(cr10_value
&0x10000000)
1724 return (cr10_value
&0x0ffff);
1727 static void phy_writeby_cr10(unsigned long iobase
, u8 phy_addr
, u8 offset
, u16 phy_data
)
1729 unsigned long ioaddr
,cr10_value
;
1731 ioaddr
= iobase
+ DCR10
;
1732 cr10_value
= phy_addr
;
1733 cr10_value
= (cr10_value
<<5) + offset
;
1734 cr10_value
= (cr10_value
<<16) + 0x04000000 + phy_data
;
1735 outl(cr10_value
,ioaddr
);
1739 * Write one bit data to Phy Controller
1742 static void phy_write_1bit(unsigned long ioaddr
, u32 phy_data
, u32 chip_id
)
1744 outl(phy_data
, ioaddr
); /* MII Clock Low */
1746 outl(phy_data
| MDCLKH
, ioaddr
); /* MII Clock High */
1748 outl(phy_data
, ioaddr
); /* MII Clock Low */
1754 * Read one bit phy data from PHY controller
1757 static u16
phy_read_1bit(unsigned long ioaddr
, u32 chip_id
)
1761 outl(0x50000 , ioaddr
);
1763 phy_data
= ( inl(ioaddr
) >> 19 ) & 0x1;
1764 outl(0x40000 , ioaddr
);
1771 static struct pci_device_id uli526x_pci_tbl
[] = {
1772 { 0x10B9, 0x5261, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, PCI_ULI5261_ID
},
1773 { 0x10B9, 0x5263, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, PCI_ULI5263_ID
},
1776 MODULE_DEVICE_TABLE(pci
, uli526x_pci_tbl
);
1779 static struct pci_driver uli526x_driver
= {
1781 .id_table
= uli526x_pci_tbl
,
1782 .probe
= uli526x_init_one
,
1783 .remove
= __devexit_p(uli526x_remove_one
),
1784 .suspend
= uli526x_suspend
,
1785 .resume
= uli526x_resume
,
1788 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1789 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1790 MODULE_LICENSE("GPL");
1792 module_param(debug
, int, 0644);
1793 module_param(mode
, int, 0);
1794 module_param(cr6set
, int, 0);
1795 MODULE_PARM_DESC(debug
, "ULi M5261/M5263 enable debugging (0-1)");
1796 MODULE_PARM_DESC(mode
, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1799 * when user used insmod to add module, system invoked init_module()
1800 * to register the services.
1803 static int __init
uli526x_init_module(void)
1807 printed_version
= 1;
1809 ULI526X_DBUG(0, "init_module() ", debug
);
1812 uli526x_debug
= debug
; /* set debug flag */
1814 uli526x_cr6_user_set
= cr6set
;
1818 case ULI526X_100MHF
:
1820 case ULI526X_100MFD
:
1821 uli526x_media_mode
= mode
;
1824 uli526x_media_mode
= ULI526X_AUTO
;
1828 return pci_register_driver(&uli526x_driver
);
1834 * when user used rmmod to delete module, system invoked clean_module()
1835 * to un-register all registered services.
1838 static void __exit
uli526x_cleanup_module(void)
1840 ULI526X_DBUG(0, "uli526x_clean_module() ", debug
);
1841 pci_unregister_driver(&uli526x_driver
);
1844 module_init(uli526x_init_module
);
1845 module_exit(uli526x_cleanup_module
);