]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/net/ucc_geth.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
net: use NETDEV_TX_OK instead of 0 in ndo_start_xmit() functions
[mirror_ubuntu-artful-kernel.git] / drivers / net / ucc_geth.c
1 /*
2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_platform.h>
32
33 #include <asm/uaccess.h>
34 #include <asm/irq.h>
35 #include <asm/io.h>
36 #include <asm/immap_qe.h>
37 #include <asm/qe.h>
38 #include <asm/ucc.h>
39 #include <asm/ucc_fast.h>
40
41 #include "ucc_geth.h"
42 #include "fsl_pq_mdio.h"
43
44 #undef DEBUG
45
46 #define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
48
49 #define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
57
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
60 #else
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif /* UGETH_VERBOSE_DEBUG */
63 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
64
65
66 static DEFINE_SPINLOCK(ugeth_lock);
67
68 static struct {
69 u32 msg_enable;
70 } debug = { -1 };
71
72 module_param_named(debug, debug.msg_enable, int, 0);
73 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
74
75 static struct ucc_geth_info ugeth_primary_info = {
76 .uf_info = {
77 .bd_mem_part = MEM_PART_SYSTEM,
78 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
79 .max_rx_buf_length = 1536,
80 /* adjusted at startup if max-speed 1000 */
81 .urfs = UCC_GETH_URFS_INIT,
82 .urfet = UCC_GETH_URFET_INIT,
83 .urfset = UCC_GETH_URFSET_INIT,
84 .utfs = UCC_GETH_UTFS_INIT,
85 .utfet = UCC_GETH_UTFET_INIT,
86 .utftt = UCC_GETH_UTFTT_INIT,
87 .ufpt = 256,
88 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
89 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
90 .tenc = UCC_FAST_TX_ENCODING_NRZ,
91 .renc = UCC_FAST_RX_ENCODING_NRZ,
92 .tcrc = UCC_FAST_16_BIT_CRC,
93 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
94 },
95 .numQueuesTx = 1,
96 .numQueuesRx = 1,
97 .extendedFilteringChainPointer = ((uint32_t) NULL),
98 .typeorlen = 3072 /*1536 */ ,
99 .nonBackToBackIfgPart1 = 0x40,
100 .nonBackToBackIfgPart2 = 0x60,
101 .miminumInterFrameGapEnforcement = 0x50,
102 .backToBackInterFrameGap = 0x60,
103 .mblinterval = 128,
104 .nortsrbytetime = 5,
105 .fracsiz = 1,
106 .strictpriorityq = 0xff,
107 .altBebTruncation = 0xa,
108 .excessDefer = 1,
109 .maxRetransmission = 0xf,
110 .collisionWindow = 0x37,
111 .receiveFlowControl = 1,
112 .transmitFlowControl = 1,
113 .maxGroupAddrInHash = 4,
114 .maxIndAddrInHash = 4,
115 .prel = 7,
116 .maxFrameLength = 1518,
117 .minFrameLength = 64,
118 .maxD1Length = 1520,
119 .maxD2Length = 1520,
120 .vlantype = 0x8100,
121 .ecamptr = ((uint32_t) NULL),
122 .eventRegMask = UCCE_OTHER,
123 .pausePeriod = 0xf000,
124 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
125 .bdRingLenTx = {
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN},
134
135 .bdRingLenRx = {
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN},
144
145 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
146 .largestexternallookupkeysize =
147 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
148 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
151 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
152 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
153 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
154 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
155 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
156 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
157 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
158 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160 };
161
162 static struct ucc_geth_info ugeth_info[8];
163
164 #ifdef DEBUG
165 static void mem_disp(u8 *addr, int size)
166 {
167 u8 *i;
168 int size16Aling = (size >> 4) << 4;
169 int size4Aling = (size >> 2) << 2;
170 int notAlign = 0;
171 if (size % 16)
172 notAlign = 1;
173
174 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
175 printk("0x%08x: %08x %08x %08x %08x\r\n",
176 (u32) i,
177 *((u32 *) (i)),
178 *((u32 *) (i + 4)),
179 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
180 if (notAlign == 1)
181 printk("0x%08x: ", (u32) i);
182 for (; (u32) i < (u32) addr + size4Aling; i += 4)
183 printk("%08x ", *((u32 *) (i)));
184 for (; (u32) i < (u32) addr + size; i++)
185 printk("%02x", *((u8 *) (i)));
186 if (notAlign == 1)
187 printk("\r\n");
188 }
189 #endif /* DEBUG */
190
191 static struct list_head *dequeue(struct list_head *lh)
192 {
193 unsigned long flags;
194
195 spin_lock_irqsave(&ugeth_lock, flags);
196 if (!list_empty(lh)) {
197 struct list_head *node = lh->next;
198 list_del(node);
199 spin_unlock_irqrestore(&ugeth_lock, flags);
200 return node;
201 } else {
202 spin_unlock_irqrestore(&ugeth_lock, flags);
203 return NULL;
204 }
205 }
206
207 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
208 u8 __iomem *bd)
209 {
210 struct sk_buff *skb = NULL;
211
212 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
213 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
214
215 if (skb == NULL)
216 return NULL;
217
218 /* We need the data buffer to be aligned properly. We will reserve
219 * as many bytes as needed to align the data properly
220 */
221 skb_reserve(skb,
222 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
223 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
224 1)));
225
226 skb->dev = ugeth->ndev;
227
228 out_be32(&((struct qe_bd __iomem *)bd)->buf,
229 dma_map_single(ugeth->dev,
230 skb->data,
231 ugeth->ug_info->uf_info.max_rx_buf_length +
232 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
233 DMA_FROM_DEVICE));
234
235 out_be32((u32 __iomem *)bd,
236 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
237
238 return skb;
239 }
240
241 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
242 {
243 u8 __iomem *bd;
244 u32 bd_status;
245 struct sk_buff *skb;
246 int i;
247
248 bd = ugeth->p_rx_bd_ring[rxQ];
249 i = 0;
250
251 do {
252 bd_status = in_be32((u32 __iomem *)bd);
253 skb = get_new_skb(ugeth, bd);
254
255 if (!skb) /* If can not allocate data buffer,
256 abort. Cleanup will be elsewhere */
257 return -ENOMEM;
258
259 ugeth->rx_skbuff[rxQ][i] = skb;
260
261 /* advance the BD pointer */
262 bd += sizeof(struct qe_bd);
263 i++;
264 } while (!(bd_status & R_W));
265
266 return 0;
267 }
268
269 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
270 u32 *p_start,
271 u8 num_entries,
272 u32 thread_size,
273 u32 thread_alignment,
274 unsigned int risc,
275 int skip_page_for_first_entry)
276 {
277 u32 init_enet_offset;
278 u8 i;
279 int snum;
280
281 for (i = 0; i < num_entries; i++) {
282 if ((snum = qe_get_snum()) < 0) {
283 if (netif_msg_ifup(ugeth))
284 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
285 return snum;
286 }
287 if ((i == 0) && skip_page_for_first_entry)
288 /* First entry of Rx does not have page */
289 init_enet_offset = 0;
290 else {
291 init_enet_offset =
292 qe_muram_alloc(thread_size, thread_alignment);
293 if (IS_ERR_VALUE(init_enet_offset)) {
294 if (netif_msg_ifup(ugeth))
295 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
296 qe_put_snum((u8) snum);
297 return -ENOMEM;
298 }
299 }
300 *(p_start++) =
301 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
302 | risc;
303 }
304
305 return 0;
306 }
307
308 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
309 u32 *p_start,
310 u8 num_entries,
311 unsigned int risc,
312 int skip_page_for_first_entry)
313 {
314 u32 init_enet_offset;
315 u8 i;
316 int snum;
317
318 for (i = 0; i < num_entries; i++) {
319 u32 val = *p_start;
320
321 /* Check that this entry was actually valid --
322 needed in case failed in allocations */
323 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
324 snum =
325 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
326 ENET_INIT_PARAM_SNUM_SHIFT;
327 qe_put_snum((u8) snum);
328 if (!((i == 0) && skip_page_for_first_entry)) {
329 /* First entry of Rx does not have page */
330 init_enet_offset =
331 (val & ENET_INIT_PARAM_PTR_MASK);
332 qe_muram_free(init_enet_offset);
333 }
334 *p_start++ = 0;
335 }
336 }
337
338 return 0;
339 }
340
341 #ifdef DEBUG
342 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
343 u32 __iomem *p_start,
344 u8 num_entries,
345 u32 thread_size,
346 unsigned int risc,
347 int skip_page_for_first_entry)
348 {
349 u32 init_enet_offset;
350 u8 i;
351 int snum;
352
353 for (i = 0; i < num_entries; i++) {
354 u32 val = in_be32(p_start);
355
356 /* Check that this entry was actually valid --
357 needed in case failed in allocations */
358 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
359 snum =
360 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
361 ENET_INIT_PARAM_SNUM_SHIFT;
362 qe_put_snum((u8) snum);
363 if (!((i == 0) && skip_page_for_first_entry)) {
364 /* First entry of Rx does not have page */
365 init_enet_offset =
366 (in_be32(p_start) &
367 ENET_INIT_PARAM_PTR_MASK);
368 ugeth_info("Init enet entry %d:", i);
369 ugeth_info("Base address: 0x%08x",
370 (u32)
371 qe_muram_addr(init_enet_offset));
372 mem_disp(qe_muram_addr(init_enet_offset),
373 thread_size);
374 }
375 p_start++;
376 }
377 }
378
379 return 0;
380 }
381 #endif
382
383 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
384 {
385 kfree(enet_addr_cont);
386 }
387
388 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
389 {
390 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
391 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
392 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
393 }
394
395 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
396 {
397 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
398
399 if (!(paddr_num < NUM_OF_PADDRS)) {
400 ugeth_warn("%s: Illagel paddr_num.", __func__);
401 return -EINVAL;
402 }
403
404 p_82xx_addr_filt =
405 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
406 addressfiltering;
407
408 /* Writing address ff.ff.ff.ff.ff.ff disables address
409 recognition for this register */
410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
412 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
413
414 return 0;
415 }
416
417 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
418 u8 *p_enet_addr)
419 {
420 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
421 u32 cecr_subblock;
422
423 p_82xx_addr_filt =
424 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
425 addressfiltering;
426
427 cecr_subblock =
428 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
429
430 /* Ethernet frames are defined in Little Endian mode,
431 therefor to insert */
432 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
433
434 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
435
436 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
437 QE_CR_PROTOCOL_ETHERNET, 0);
438 }
439
440 #ifdef CONFIG_UGETH_MAGIC_PACKET
441 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
442 {
443 struct ucc_fast_private *uccf;
444 struct ucc_geth __iomem *ug_regs;
445
446 uccf = ugeth->uccf;
447 ug_regs = ugeth->ug_regs;
448
449 /* Enable interrupts for magic packet detection */
450 setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
451
452 /* Enable magic packet detection */
453 setbits32(&ug_regs->maccfg2, MACCFG2_MPE);
454 }
455
456 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
457 {
458 struct ucc_fast_private *uccf;
459 struct ucc_geth __iomem *ug_regs;
460
461 uccf = ugeth->uccf;
462 ug_regs = ugeth->ug_regs;
463
464 /* Disable interrupts for magic packet detection */
465 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
466
467 /* Disable magic packet detection */
468 clrbits32(&ug_regs->maccfg2, MACCFG2_MPE);
469 }
470 #endif /* MAGIC_PACKET */
471
472 static inline int compare_addr(u8 **addr1, u8 **addr2)
473 {
474 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
475 }
476
477 #ifdef DEBUG
478 static void get_statistics(struct ucc_geth_private *ugeth,
479 struct ucc_geth_tx_firmware_statistics *
480 tx_firmware_statistics,
481 struct ucc_geth_rx_firmware_statistics *
482 rx_firmware_statistics,
483 struct ucc_geth_hardware_statistics *hardware_statistics)
484 {
485 struct ucc_fast __iomem *uf_regs;
486 struct ucc_geth __iomem *ug_regs;
487 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
488 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
489
490 ug_regs = ugeth->ug_regs;
491 uf_regs = (struct ucc_fast __iomem *) ug_regs;
492 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
493 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
494
495 /* Tx firmware only if user handed pointer and driver actually
496 gathers Tx firmware statistics */
497 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
498 tx_firmware_statistics->sicoltx =
499 in_be32(&p_tx_fw_statistics_pram->sicoltx);
500 tx_firmware_statistics->mulcoltx =
501 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
502 tx_firmware_statistics->latecoltxfr =
503 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
504 tx_firmware_statistics->frabortduecol =
505 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
506 tx_firmware_statistics->frlostinmactxer =
507 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
508 tx_firmware_statistics->carriersenseertx =
509 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
510 tx_firmware_statistics->frtxok =
511 in_be32(&p_tx_fw_statistics_pram->frtxok);
512 tx_firmware_statistics->txfrexcessivedefer =
513 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
514 tx_firmware_statistics->txpkts256 =
515 in_be32(&p_tx_fw_statistics_pram->txpkts256);
516 tx_firmware_statistics->txpkts512 =
517 in_be32(&p_tx_fw_statistics_pram->txpkts512);
518 tx_firmware_statistics->txpkts1024 =
519 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
520 tx_firmware_statistics->txpktsjumbo =
521 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
522 }
523
524 /* Rx firmware only if user handed pointer and driver actually
525 * gathers Rx firmware statistics */
526 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
527 int i;
528 rx_firmware_statistics->frrxfcser =
529 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
530 rx_firmware_statistics->fraligner =
531 in_be32(&p_rx_fw_statistics_pram->fraligner);
532 rx_firmware_statistics->inrangelenrxer =
533 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
534 rx_firmware_statistics->outrangelenrxer =
535 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
536 rx_firmware_statistics->frtoolong =
537 in_be32(&p_rx_fw_statistics_pram->frtoolong);
538 rx_firmware_statistics->runt =
539 in_be32(&p_rx_fw_statistics_pram->runt);
540 rx_firmware_statistics->verylongevent =
541 in_be32(&p_rx_fw_statistics_pram->verylongevent);
542 rx_firmware_statistics->symbolerror =
543 in_be32(&p_rx_fw_statistics_pram->symbolerror);
544 rx_firmware_statistics->dropbsy =
545 in_be32(&p_rx_fw_statistics_pram->dropbsy);
546 for (i = 0; i < 0x8; i++)
547 rx_firmware_statistics->res0[i] =
548 p_rx_fw_statistics_pram->res0[i];
549 rx_firmware_statistics->mismatchdrop =
550 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
551 rx_firmware_statistics->underpkts =
552 in_be32(&p_rx_fw_statistics_pram->underpkts);
553 rx_firmware_statistics->pkts256 =
554 in_be32(&p_rx_fw_statistics_pram->pkts256);
555 rx_firmware_statistics->pkts512 =
556 in_be32(&p_rx_fw_statistics_pram->pkts512);
557 rx_firmware_statistics->pkts1024 =
558 in_be32(&p_rx_fw_statistics_pram->pkts1024);
559 rx_firmware_statistics->pktsjumbo =
560 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
561 rx_firmware_statistics->frlossinmacer =
562 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
563 rx_firmware_statistics->pausefr =
564 in_be32(&p_rx_fw_statistics_pram->pausefr);
565 for (i = 0; i < 0x4; i++)
566 rx_firmware_statistics->res1[i] =
567 p_rx_fw_statistics_pram->res1[i];
568 rx_firmware_statistics->removevlan =
569 in_be32(&p_rx_fw_statistics_pram->removevlan);
570 rx_firmware_statistics->replacevlan =
571 in_be32(&p_rx_fw_statistics_pram->replacevlan);
572 rx_firmware_statistics->insertvlan =
573 in_be32(&p_rx_fw_statistics_pram->insertvlan);
574 }
575
576 /* Hardware only if user handed pointer and driver actually
577 gathers hardware statistics */
578 if (hardware_statistics &&
579 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
580 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
581 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
582 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
583 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
584 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
585 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
586 hardware_statistics->txok = in_be32(&ug_regs->txok);
587 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
588 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
589 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
590 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
591 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
592 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
593 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
594 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
595 }
596 }
597
598 static void dump_bds(struct ucc_geth_private *ugeth)
599 {
600 int i;
601 int length;
602
603 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
604 if (ugeth->p_tx_bd_ring[i]) {
605 length =
606 (ugeth->ug_info->bdRingLenTx[i] *
607 sizeof(struct qe_bd));
608 ugeth_info("TX BDs[%d]", i);
609 mem_disp(ugeth->p_tx_bd_ring[i], length);
610 }
611 }
612 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
613 if (ugeth->p_rx_bd_ring[i]) {
614 length =
615 (ugeth->ug_info->bdRingLenRx[i] *
616 sizeof(struct qe_bd));
617 ugeth_info("RX BDs[%d]", i);
618 mem_disp(ugeth->p_rx_bd_ring[i], length);
619 }
620 }
621 }
622
623 static void dump_regs(struct ucc_geth_private *ugeth)
624 {
625 int i;
626
627 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
628 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
629
630 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
631 (u32) & ugeth->ug_regs->maccfg1,
632 in_be32(&ugeth->ug_regs->maccfg1));
633 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
634 (u32) & ugeth->ug_regs->maccfg2,
635 in_be32(&ugeth->ug_regs->maccfg2));
636 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
637 (u32) & ugeth->ug_regs->ipgifg,
638 in_be32(&ugeth->ug_regs->ipgifg));
639 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
640 (u32) & ugeth->ug_regs->hafdup,
641 in_be32(&ugeth->ug_regs->hafdup));
642 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
643 (u32) & ugeth->ug_regs->ifctl,
644 in_be32(&ugeth->ug_regs->ifctl));
645 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
646 (u32) & ugeth->ug_regs->ifstat,
647 in_be32(&ugeth->ug_regs->ifstat));
648 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
649 (u32) & ugeth->ug_regs->macstnaddr1,
650 in_be32(&ugeth->ug_regs->macstnaddr1));
651 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
652 (u32) & ugeth->ug_regs->macstnaddr2,
653 in_be32(&ugeth->ug_regs->macstnaddr2));
654 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
655 (u32) & ugeth->ug_regs->uempr,
656 in_be32(&ugeth->ug_regs->uempr));
657 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
658 (u32) & ugeth->ug_regs->utbipar,
659 in_be32(&ugeth->ug_regs->utbipar));
660 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
661 (u32) & ugeth->ug_regs->uescr,
662 in_be16(&ugeth->ug_regs->uescr));
663 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
664 (u32) & ugeth->ug_regs->tx64,
665 in_be32(&ugeth->ug_regs->tx64));
666 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
667 (u32) & ugeth->ug_regs->tx127,
668 in_be32(&ugeth->ug_regs->tx127));
669 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
670 (u32) & ugeth->ug_regs->tx255,
671 in_be32(&ugeth->ug_regs->tx255));
672 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
673 (u32) & ugeth->ug_regs->rx64,
674 in_be32(&ugeth->ug_regs->rx64));
675 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
676 (u32) & ugeth->ug_regs->rx127,
677 in_be32(&ugeth->ug_regs->rx127));
678 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
679 (u32) & ugeth->ug_regs->rx255,
680 in_be32(&ugeth->ug_regs->rx255));
681 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
682 (u32) & ugeth->ug_regs->txok,
683 in_be32(&ugeth->ug_regs->txok));
684 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
685 (u32) & ugeth->ug_regs->txcf,
686 in_be16(&ugeth->ug_regs->txcf));
687 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
688 (u32) & ugeth->ug_regs->tmca,
689 in_be32(&ugeth->ug_regs->tmca));
690 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
691 (u32) & ugeth->ug_regs->tbca,
692 in_be32(&ugeth->ug_regs->tbca));
693 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
694 (u32) & ugeth->ug_regs->rxfok,
695 in_be32(&ugeth->ug_regs->rxfok));
696 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
697 (u32) & ugeth->ug_regs->rxbok,
698 in_be32(&ugeth->ug_regs->rxbok));
699 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
700 (u32) & ugeth->ug_regs->rbyt,
701 in_be32(&ugeth->ug_regs->rbyt));
702 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
703 (u32) & ugeth->ug_regs->rmca,
704 in_be32(&ugeth->ug_regs->rmca));
705 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
706 (u32) & ugeth->ug_regs->rbca,
707 in_be32(&ugeth->ug_regs->rbca));
708 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
709 (u32) & ugeth->ug_regs->scar,
710 in_be32(&ugeth->ug_regs->scar));
711 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
712 (u32) & ugeth->ug_regs->scam,
713 in_be32(&ugeth->ug_regs->scam));
714
715 if (ugeth->p_thread_data_tx) {
716 int numThreadsTxNumerical;
717 switch (ugeth->ug_info->numThreadsTx) {
718 case UCC_GETH_NUM_OF_THREADS_1:
719 numThreadsTxNumerical = 1;
720 break;
721 case UCC_GETH_NUM_OF_THREADS_2:
722 numThreadsTxNumerical = 2;
723 break;
724 case UCC_GETH_NUM_OF_THREADS_4:
725 numThreadsTxNumerical = 4;
726 break;
727 case UCC_GETH_NUM_OF_THREADS_6:
728 numThreadsTxNumerical = 6;
729 break;
730 case UCC_GETH_NUM_OF_THREADS_8:
731 numThreadsTxNumerical = 8;
732 break;
733 default:
734 numThreadsTxNumerical = 0;
735 break;
736 }
737
738 ugeth_info("Thread data TXs:");
739 ugeth_info("Base address: 0x%08x",
740 (u32) ugeth->p_thread_data_tx);
741 for (i = 0; i < numThreadsTxNumerical; i++) {
742 ugeth_info("Thread data TX[%d]:", i);
743 ugeth_info("Base address: 0x%08x",
744 (u32) & ugeth->p_thread_data_tx[i]);
745 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
746 sizeof(struct ucc_geth_thread_data_tx));
747 }
748 }
749 if (ugeth->p_thread_data_rx) {
750 int numThreadsRxNumerical;
751 switch (ugeth->ug_info->numThreadsRx) {
752 case UCC_GETH_NUM_OF_THREADS_1:
753 numThreadsRxNumerical = 1;
754 break;
755 case UCC_GETH_NUM_OF_THREADS_2:
756 numThreadsRxNumerical = 2;
757 break;
758 case UCC_GETH_NUM_OF_THREADS_4:
759 numThreadsRxNumerical = 4;
760 break;
761 case UCC_GETH_NUM_OF_THREADS_6:
762 numThreadsRxNumerical = 6;
763 break;
764 case UCC_GETH_NUM_OF_THREADS_8:
765 numThreadsRxNumerical = 8;
766 break;
767 default:
768 numThreadsRxNumerical = 0;
769 break;
770 }
771
772 ugeth_info("Thread data RX:");
773 ugeth_info("Base address: 0x%08x",
774 (u32) ugeth->p_thread_data_rx);
775 for (i = 0; i < numThreadsRxNumerical; i++) {
776 ugeth_info("Thread data RX[%d]:", i);
777 ugeth_info("Base address: 0x%08x",
778 (u32) & ugeth->p_thread_data_rx[i]);
779 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
780 sizeof(struct ucc_geth_thread_data_rx));
781 }
782 }
783 if (ugeth->p_exf_glbl_param) {
784 ugeth_info("EXF global param:");
785 ugeth_info("Base address: 0x%08x",
786 (u32) ugeth->p_exf_glbl_param);
787 mem_disp((u8 *) ugeth->p_exf_glbl_param,
788 sizeof(*ugeth->p_exf_glbl_param));
789 }
790 if (ugeth->p_tx_glbl_pram) {
791 ugeth_info("TX global param:");
792 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
793 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
794 (u32) & ugeth->p_tx_glbl_pram->temoder,
795 in_be16(&ugeth->p_tx_glbl_pram->temoder));
796 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
797 (u32) & ugeth->p_tx_glbl_pram->sqptr,
798 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
799 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
800 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
801 in_be32(&ugeth->p_tx_glbl_pram->
802 schedulerbasepointer));
803 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
804 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
805 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
806 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
807 (u32) & ugeth->p_tx_glbl_pram->tstate,
808 in_be32(&ugeth->p_tx_glbl_pram->tstate));
809 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
810 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
811 ugeth->p_tx_glbl_pram->iphoffset[0]);
812 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
813 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
814 ugeth->p_tx_glbl_pram->iphoffset[1]);
815 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
816 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
817 ugeth->p_tx_glbl_pram->iphoffset[2]);
818 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
819 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
820 ugeth->p_tx_glbl_pram->iphoffset[3]);
821 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
822 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
823 ugeth->p_tx_glbl_pram->iphoffset[4]);
824 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
825 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
826 ugeth->p_tx_glbl_pram->iphoffset[5]);
827 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
828 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
829 ugeth->p_tx_glbl_pram->iphoffset[6]);
830 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
831 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
832 ugeth->p_tx_glbl_pram->iphoffset[7]);
833 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
834 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
835 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
836 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
837 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
838 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
839 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
840 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
841 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
842 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
843 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
844 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
845 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
846 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
847 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
848 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
849 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
850 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
851 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
852 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
853 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
854 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
855 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
856 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
857 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
858 (u32) & ugeth->p_tx_glbl_pram->tqptr,
859 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
860 }
861 if (ugeth->p_rx_glbl_pram) {
862 ugeth_info("RX global param:");
863 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
864 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
865 (u32) & ugeth->p_rx_glbl_pram->remoder,
866 in_be32(&ugeth->p_rx_glbl_pram->remoder));
867 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
868 (u32) & ugeth->p_rx_glbl_pram->rqptr,
869 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
870 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
871 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
872 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
873 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
874 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
875 ugeth->p_rx_glbl_pram->rxgstpack);
876 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
877 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
878 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
879 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
880 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
881 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
882 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
883 (u32) & ugeth->p_rx_glbl_pram->rstate,
884 ugeth->p_rx_glbl_pram->rstate);
885 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
886 (u32) & ugeth->p_rx_glbl_pram->mrblr,
887 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
888 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
889 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
890 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
891 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
892 (u32) & ugeth->p_rx_glbl_pram->mflr,
893 in_be16(&ugeth->p_rx_glbl_pram->mflr));
894 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
895 (u32) & ugeth->p_rx_glbl_pram->minflr,
896 in_be16(&ugeth->p_rx_glbl_pram->minflr));
897 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
898 (u32) & ugeth->p_rx_glbl_pram->maxd1,
899 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
900 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
901 (u32) & ugeth->p_rx_glbl_pram->maxd2,
902 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
903 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
904 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
905 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
906 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
907 (u32) & ugeth->p_rx_glbl_pram->l2qt,
908 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
909 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
910 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
911 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
912 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
913 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
914 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
915 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
916 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
917 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
918 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
919 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
920 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
921 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
922 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
923 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
924 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
925 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
926 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
927 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
928 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
929 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
930 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
931 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
932 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
933 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
934 (u32) & ugeth->p_rx_glbl_pram->vlantype,
935 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
936 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
937 (u32) & ugeth->p_rx_glbl_pram->vlantci,
938 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
939 for (i = 0; i < 64; i++)
940 ugeth_info
941 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
942 i,
943 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
944 ugeth->p_rx_glbl_pram->addressfiltering[i]);
945 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
946 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
947 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
948 }
949 if (ugeth->p_send_q_mem_reg) {
950 ugeth_info("Send Q memory registers:");
951 ugeth_info("Base address: 0x%08x",
952 (u32) ugeth->p_send_q_mem_reg);
953 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
954 ugeth_info("SQQD[%d]:", i);
955 ugeth_info("Base address: 0x%08x",
956 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
957 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
958 sizeof(struct ucc_geth_send_queue_qd));
959 }
960 }
961 if (ugeth->p_scheduler) {
962 ugeth_info("Scheduler:");
963 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
964 mem_disp((u8 *) ugeth->p_scheduler,
965 sizeof(*ugeth->p_scheduler));
966 }
967 if (ugeth->p_tx_fw_statistics_pram) {
968 ugeth_info("TX FW statistics pram:");
969 ugeth_info("Base address: 0x%08x",
970 (u32) ugeth->p_tx_fw_statistics_pram);
971 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
972 sizeof(*ugeth->p_tx_fw_statistics_pram));
973 }
974 if (ugeth->p_rx_fw_statistics_pram) {
975 ugeth_info("RX FW statistics pram:");
976 ugeth_info("Base address: 0x%08x",
977 (u32) ugeth->p_rx_fw_statistics_pram);
978 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
979 sizeof(*ugeth->p_rx_fw_statistics_pram));
980 }
981 if (ugeth->p_rx_irq_coalescing_tbl) {
982 ugeth_info("RX IRQ coalescing tables:");
983 ugeth_info("Base address: 0x%08x",
984 (u32) ugeth->p_rx_irq_coalescing_tbl);
985 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
986 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
987 ugeth_info("Base address: 0x%08x",
988 (u32) & ugeth->p_rx_irq_coalescing_tbl->
989 coalescingentry[i]);
990 ugeth_info
991 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
992 (u32) & ugeth->p_rx_irq_coalescing_tbl->
993 coalescingentry[i].interruptcoalescingmaxvalue,
994 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
995 coalescingentry[i].
996 interruptcoalescingmaxvalue));
997 ugeth_info
998 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
999 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1000 coalescingentry[i].interruptcoalescingcounter,
1001 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1002 coalescingentry[i].
1003 interruptcoalescingcounter));
1004 }
1005 }
1006 if (ugeth->p_rx_bd_qs_tbl) {
1007 ugeth_info("RX BD QS tables:");
1008 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1009 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1010 ugeth_info("RX BD QS table[%d]:", i);
1011 ugeth_info("Base address: 0x%08x",
1012 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1013 ugeth_info
1014 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1015 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1016 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1017 ugeth_info
1018 ("bdptr : addr - 0x%08x, val - 0x%08x",
1019 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1020 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1021 ugeth_info
1022 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1023 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1024 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1025 externalbdbaseptr));
1026 ugeth_info
1027 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1028 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1029 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1030 ugeth_info("ucode RX Prefetched BDs:");
1031 ugeth_info("Base address: 0x%08x",
1032 (u32)
1033 qe_muram_addr(in_be32
1034 (&ugeth->p_rx_bd_qs_tbl[i].
1035 bdbaseptr)));
1036 mem_disp((u8 *)
1037 qe_muram_addr(in_be32
1038 (&ugeth->p_rx_bd_qs_tbl[i].
1039 bdbaseptr)),
1040 sizeof(struct ucc_geth_rx_prefetched_bds));
1041 }
1042 }
1043 if (ugeth->p_init_enet_param_shadow) {
1044 int size;
1045 ugeth_info("Init enet param shadow:");
1046 ugeth_info("Base address: 0x%08x",
1047 (u32) ugeth->p_init_enet_param_shadow);
1048 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1049 sizeof(*ugeth->p_init_enet_param_shadow));
1050
1051 size = sizeof(struct ucc_geth_thread_rx_pram);
1052 if (ugeth->ug_info->rxExtendedFiltering) {
1053 size +=
1054 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1055 if (ugeth->ug_info->largestexternallookupkeysize ==
1056 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1057 size +=
1058 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1059 if (ugeth->ug_info->largestexternallookupkeysize ==
1060 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1061 size +=
1062 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1063 }
1064
1065 dump_init_enet_entries(ugeth,
1066 &(ugeth->p_init_enet_param_shadow->
1067 txthread[0]),
1068 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1069 sizeof(struct ucc_geth_thread_tx_pram),
1070 ugeth->ug_info->riscTx, 0);
1071 dump_init_enet_entries(ugeth,
1072 &(ugeth->p_init_enet_param_shadow->
1073 rxthread[0]),
1074 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1075 ugeth->ug_info->riscRx, 1);
1076 }
1077 }
1078 #endif /* DEBUG */
1079
1080 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1081 u32 __iomem *maccfg1_register,
1082 u32 __iomem *maccfg2_register)
1083 {
1084 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1085 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1086 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1087 }
1088
1089 static int init_half_duplex_params(int alt_beb,
1090 int back_pressure_no_backoff,
1091 int no_backoff,
1092 int excess_defer,
1093 u8 alt_beb_truncation,
1094 u8 max_retransmissions,
1095 u8 collision_window,
1096 u32 __iomem *hafdup_register)
1097 {
1098 u32 value = 0;
1099
1100 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1101 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1102 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1103 return -EINVAL;
1104
1105 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1106
1107 if (alt_beb)
1108 value |= HALFDUP_ALT_BEB;
1109 if (back_pressure_no_backoff)
1110 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1111 if (no_backoff)
1112 value |= HALFDUP_NO_BACKOFF;
1113 if (excess_defer)
1114 value |= HALFDUP_EXCESSIVE_DEFER;
1115
1116 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1117
1118 value |= collision_window;
1119
1120 out_be32(hafdup_register, value);
1121 return 0;
1122 }
1123
1124 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1125 u8 non_btb_ipg,
1126 u8 min_ifg,
1127 u8 btb_ipg,
1128 u32 __iomem *ipgifg_register)
1129 {
1130 u32 value = 0;
1131
1132 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1133 IPG part 2 */
1134 if (non_btb_cs_ipg > non_btb_ipg)
1135 return -EINVAL;
1136
1137 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1138 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1139 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1140 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1141 return -EINVAL;
1142
1143 value |=
1144 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1145 IPGIFG_NBTB_CS_IPG_MASK);
1146 value |=
1147 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1148 IPGIFG_NBTB_IPG_MASK);
1149 value |=
1150 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1151 IPGIFG_MIN_IFG_MASK);
1152 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1153
1154 out_be32(ipgifg_register, value);
1155 return 0;
1156 }
1157
1158 int init_flow_control_params(u32 automatic_flow_control_mode,
1159 int rx_flow_control_enable,
1160 int tx_flow_control_enable,
1161 u16 pause_period,
1162 u16 extension_field,
1163 u32 __iomem *upsmr_register,
1164 u32 __iomem *uempr_register,
1165 u32 __iomem *maccfg1_register)
1166 {
1167 u32 value = 0;
1168
1169 /* Set UEMPR register */
1170 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1171 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1172 out_be32(uempr_register, value);
1173
1174 /* Set UPSMR register */
1175 setbits32(upsmr_register, automatic_flow_control_mode);
1176
1177 value = in_be32(maccfg1_register);
1178 if (rx_flow_control_enable)
1179 value |= MACCFG1_FLOW_RX;
1180 if (tx_flow_control_enable)
1181 value |= MACCFG1_FLOW_TX;
1182 out_be32(maccfg1_register, value);
1183
1184 return 0;
1185 }
1186
1187 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1188 int auto_zero_hardware_statistics,
1189 u32 __iomem *upsmr_register,
1190 u16 __iomem *uescr_register)
1191 {
1192 u16 uescr_value = 0;
1193
1194 /* Enable hardware statistics gathering if requested */
1195 if (enable_hardware_statistics)
1196 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1197
1198 /* Clear hardware statistics counters */
1199 uescr_value = in_be16(uescr_register);
1200 uescr_value |= UESCR_CLRCNT;
1201 /* Automatically zero hardware statistics counters on read,
1202 if requested */
1203 if (auto_zero_hardware_statistics)
1204 uescr_value |= UESCR_AUTOZ;
1205 out_be16(uescr_register, uescr_value);
1206
1207 return 0;
1208 }
1209
1210 static int init_firmware_statistics_gathering_mode(int
1211 enable_tx_firmware_statistics,
1212 int enable_rx_firmware_statistics,
1213 u32 __iomem *tx_rmon_base_ptr,
1214 u32 tx_firmware_statistics_structure_address,
1215 u32 __iomem *rx_rmon_base_ptr,
1216 u32 rx_firmware_statistics_structure_address,
1217 u16 __iomem *temoder_register,
1218 u32 __iomem *remoder_register)
1219 {
1220 /* Note: this function does not check if */
1221 /* the parameters it receives are NULL */
1222
1223 if (enable_tx_firmware_statistics) {
1224 out_be32(tx_rmon_base_ptr,
1225 tx_firmware_statistics_structure_address);
1226 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1227 }
1228
1229 if (enable_rx_firmware_statistics) {
1230 out_be32(rx_rmon_base_ptr,
1231 rx_firmware_statistics_structure_address);
1232 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1233 }
1234
1235 return 0;
1236 }
1237
1238 static int init_mac_station_addr_regs(u8 address_byte_0,
1239 u8 address_byte_1,
1240 u8 address_byte_2,
1241 u8 address_byte_3,
1242 u8 address_byte_4,
1243 u8 address_byte_5,
1244 u32 __iomem *macstnaddr1_register,
1245 u32 __iomem *macstnaddr2_register)
1246 {
1247 u32 value = 0;
1248
1249 /* Example: for a station address of 0x12345678ABCD, */
1250 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1251
1252 /* MACSTNADDR1 Register: */
1253
1254 /* 0 7 8 15 */
1255 /* station address byte 5 station address byte 4 */
1256 /* 16 23 24 31 */
1257 /* station address byte 3 station address byte 2 */
1258 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1259 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1260 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1261 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1262
1263 out_be32(macstnaddr1_register, value);
1264
1265 /* MACSTNADDR2 Register: */
1266
1267 /* 0 7 8 15 */
1268 /* station address byte 1 station address byte 0 */
1269 /* 16 23 24 31 */
1270 /* reserved reserved */
1271 value = 0;
1272 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1273 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1274
1275 out_be32(macstnaddr2_register, value);
1276
1277 return 0;
1278 }
1279
1280 static int init_check_frame_length_mode(int length_check,
1281 u32 __iomem *maccfg2_register)
1282 {
1283 u32 value = 0;
1284
1285 value = in_be32(maccfg2_register);
1286
1287 if (length_check)
1288 value |= MACCFG2_LC;
1289 else
1290 value &= ~MACCFG2_LC;
1291
1292 out_be32(maccfg2_register, value);
1293 return 0;
1294 }
1295
1296 static int init_preamble_length(u8 preamble_length,
1297 u32 __iomem *maccfg2_register)
1298 {
1299 if ((preamble_length < 3) || (preamble_length > 7))
1300 return -EINVAL;
1301
1302 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1303 preamble_length << MACCFG2_PREL_SHIFT);
1304
1305 return 0;
1306 }
1307
1308 static int init_rx_parameters(int reject_broadcast,
1309 int receive_short_frames,
1310 int promiscuous, u32 __iomem *upsmr_register)
1311 {
1312 u32 value = 0;
1313
1314 value = in_be32(upsmr_register);
1315
1316 if (reject_broadcast)
1317 value |= UCC_GETH_UPSMR_BRO;
1318 else
1319 value &= ~UCC_GETH_UPSMR_BRO;
1320
1321 if (receive_short_frames)
1322 value |= UCC_GETH_UPSMR_RSH;
1323 else
1324 value &= ~UCC_GETH_UPSMR_RSH;
1325
1326 if (promiscuous)
1327 value |= UCC_GETH_UPSMR_PRO;
1328 else
1329 value &= ~UCC_GETH_UPSMR_PRO;
1330
1331 out_be32(upsmr_register, value);
1332
1333 return 0;
1334 }
1335
1336 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1337 u16 __iomem *mrblr_register)
1338 {
1339 /* max_rx_buf_len value must be a multiple of 128 */
1340 if ((max_rx_buf_len == 0)
1341 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1342 return -EINVAL;
1343
1344 out_be16(mrblr_register, max_rx_buf_len);
1345 return 0;
1346 }
1347
1348 static int init_min_frame_len(u16 min_frame_length,
1349 u16 __iomem *minflr_register,
1350 u16 __iomem *mrblr_register)
1351 {
1352 u16 mrblr_value = 0;
1353
1354 mrblr_value = in_be16(mrblr_register);
1355 if (min_frame_length >= (mrblr_value - 4))
1356 return -EINVAL;
1357
1358 out_be16(minflr_register, min_frame_length);
1359 return 0;
1360 }
1361
1362 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1363 {
1364 struct ucc_geth_info *ug_info;
1365 struct ucc_geth __iomem *ug_regs;
1366 struct ucc_fast __iomem *uf_regs;
1367 int ret_val;
1368 u32 upsmr, maccfg2, tbiBaseAddress;
1369 u16 value;
1370
1371 ugeth_vdbg("%s: IN", __func__);
1372
1373 ug_info = ugeth->ug_info;
1374 ug_regs = ugeth->ug_regs;
1375 uf_regs = ugeth->uccf->uf_regs;
1376
1377 /* Set MACCFG2 */
1378 maccfg2 = in_be32(&ug_regs->maccfg2);
1379 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1380 if ((ugeth->max_speed == SPEED_10) ||
1381 (ugeth->max_speed == SPEED_100))
1382 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1383 else if (ugeth->max_speed == SPEED_1000)
1384 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1385 maccfg2 |= ug_info->padAndCrc;
1386 out_be32(&ug_regs->maccfg2, maccfg2);
1387
1388 /* Set UPSMR */
1389 upsmr = in_be32(&uf_regs->upsmr);
1390 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1391 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1392 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1393 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1394 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1395 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1396 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1397 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1398 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1399 upsmr |= UCC_GETH_UPSMR_RPM;
1400 switch (ugeth->max_speed) {
1401 case SPEED_10:
1402 upsmr |= UCC_GETH_UPSMR_R10M;
1403 /* FALLTHROUGH */
1404 case SPEED_100:
1405 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1406 upsmr |= UCC_GETH_UPSMR_RMM;
1407 }
1408 }
1409 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1410 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1411 upsmr |= UCC_GETH_UPSMR_TBIM;
1412 }
1413 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1414 upsmr |= UCC_GETH_UPSMR_SGMM;
1415
1416 out_be32(&uf_regs->upsmr, upsmr);
1417
1418 /* Disable autonegotiation in tbi mode, because by default it
1419 comes up in autonegotiation mode. */
1420 /* Note that this depends on proper setting in utbipar register. */
1421 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1422 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1423 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1424 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1425 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1426 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1427 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1428 value &= ~0x1000; /* Turn off autonegotiation */
1429 ugeth->phydev->bus->write(ugeth->phydev->bus,
1430 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1431 }
1432
1433 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1434
1435 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1436 if (ret_val != 0) {
1437 if (netif_msg_probe(ugeth))
1438 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1439 __func__);
1440 return ret_val;
1441 }
1442
1443 return 0;
1444 }
1445
1446 /* Called every time the controller might need to be made
1447 * aware of new link state. The PHY code conveys this
1448 * information through variables in the ugeth structure, and this
1449 * function converts those variables into the appropriate
1450 * register values, and can bring down the device if needed.
1451 */
1452
1453 static void adjust_link(struct net_device *dev)
1454 {
1455 struct ucc_geth_private *ugeth = netdev_priv(dev);
1456 struct ucc_geth __iomem *ug_regs;
1457 struct ucc_fast __iomem *uf_regs;
1458 struct phy_device *phydev = ugeth->phydev;
1459 unsigned long flags;
1460 int new_state = 0;
1461
1462 ug_regs = ugeth->ug_regs;
1463 uf_regs = ugeth->uccf->uf_regs;
1464
1465 spin_lock_irqsave(&ugeth->lock, flags);
1466
1467 if (phydev->link) {
1468 u32 tempval = in_be32(&ug_regs->maccfg2);
1469 u32 upsmr = in_be32(&uf_regs->upsmr);
1470 /* Now we make sure that we can be in full duplex mode.
1471 * If not, we operate in half-duplex mode. */
1472 if (phydev->duplex != ugeth->oldduplex) {
1473 new_state = 1;
1474 if (!(phydev->duplex))
1475 tempval &= ~(MACCFG2_FDX);
1476 else
1477 tempval |= MACCFG2_FDX;
1478 ugeth->oldduplex = phydev->duplex;
1479 }
1480
1481 if (phydev->speed != ugeth->oldspeed) {
1482 new_state = 1;
1483 switch (phydev->speed) {
1484 case SPEED_1000:
1485 tempval = ((tempval &
1486 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1487 MACCFG2_INTERFACE_MODE_BYTE);
1488 break;
1489 case SPEED_100:
1490 case SPEED_10:
1491 tempval = ((tempval &
1492 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1493 MACCFG2_INTERFACE_MODE_NIBBLE);
1494 /* if reduced mode, re-set UPSMR.R10M */
1495 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1496 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1497 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1498 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1499 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1500 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1501 if (phydev->speed == SPEED_10)
1502 upsmr |= UCC_GETH_UPSMR_R10M;
1503 else
1504 upsmr &= ~UCC_GETH_UPSMR_R10M;
1505 }
1506 break;
1507 default:
1508 if (netif_msg_link(ugeth))
1509 ugeth_warn(
1510 "%s: Ack! Speed (%d) is not 10/100/1000!",
1511 dev->name, phydev->speed);
1512 break;
1513 }
1514 ugeth->oldspeed = phydev->speed;
1515 }
1516
1517 out_be32(&ug_regs->maccfg2, tempval);
1518 out_be32(&uf_regs->upsmr, upsmr);
1519
1520 if (!ugeth->oldlink) {
1521 new_state = 1;
1522 ugeth->oldlink = 1;
1523 }
1524 } else if (ugeth->oldlink) {
1525 new_state = 1;
1526 ugeth->oldlink = 0;
1527 ugeth->oldspeed = 0;
1528 ugeth->oldduplex = -1;
1529 }
1530
1531 if (new_state && netif_msg_link(ugeth))
1532 phy_print_status(phydev);
1533
1534 spin_unlock_irqrestore(&ugeth->lock, flags);
1535 }
1536
1537 /* Initialize TBI PHY interface for communicating with the
1538 * SERDES lynx PHY on the chip. We communicate with this PHY
1539 * through the MDIO bus on each controller, treating it as a
1540 * "normal" PHY at the address found in the UTBIPA register. We assume
1541 * that the UTBIPA register is valid. Either the MDIO bus code will set
1542 * it to a value that doesn't conflict with other PHYs on the bus, or the
1543 * value doesn't matter, as there are no other PHYs on the bus.
1544 */
1545 static void uec_configure_serdes(struct net_device *dev)
1546 {
1547 struct ucc_geth_private *ugeth = netdev_priv(dev);
1548 struct ucc_geth_info *ug_info = ugeth->ug_info;
1549 struct phy_device *tbiphy;
1550
1551 if (!ug_info->tbi_node) {
1552 dev_warn(&dev->dev, "SGMII mode requires that the device "
1553 "tree specify a tbi-handle\n");
1554 return;
1555 }
1556
1557 tbiphy = of_phy_find_device(ug_info->tbi_node);
1558 if (!tbiphy) {
1559 dev_err(&dev->dev, "error: Could not get TBI device\n");
1560 return;
1561 }
1562
1563 /*
1564 * If the link is already up, we must already be ok, and don't need to
1565 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1566 * everything for us? Resetting it takes the link down and requires
1567 * several seconds for it to come back.
1568 */
1569 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1570 return;
1571
1572 /* Single clk mode, mii mode off(for serdes communication) */
1573 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1574
1575 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1576
1577 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1578 }
1579
1580 /* Configure the PHY for dev.
1581 * returns 0 if success. -1 if failure
1582 */
1583 static int init_phy(struct net_device *dev)
1584 {
1585 struct ucc_geth_private *priv = netdev_priv(dev);
1586 struct ucc_geth_info *ug_info = priv->ug_info;
1587 struct phy_device *phydev;
1588
1589 priv->oldlink = 0;
1590 priv->oldspeed = 0;
1591 priv->oldduplex = -1;
1592
1593 if (!ug_info->phy_node)
1594 return 0;
1595
1596 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1597 priv->phy_interface);
1598 if (!phydev) {
1599 printk("%s: Could not attach to PHY\n", dev->name);
1600 return -ENODEV;
1601 }
1602
1603 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1604 uec_configure_serdes(dev);
1605
1606 phydev->supported &= (ADVERTISED_10baseT_Half |
1607 ADVERTISED_10baseT_Full |
1608 ADVERTISED_100baseT_Half |
1609 ADVERTISED_100baseT_Full);
1610
1611 if (priv->max_speed == SPEED_1000)
1612 phydev->supported |= ADVERTISED_1000baseT_Full;
1613
1614 phydev->advertising = phydev->supported;
1615
1616 priv->phydev = phydev;
1617
1618 return 0;
1619 }
1620
1621
1622
1623 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1624 {
1625 struct ucc_fast_private *uccf;
1626 u32 cecr_subblock;
1627 u32 temp;
1628 int i = 10;
1629
1630 uccf = ugeth->uccf;
1631
1632 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1633 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1634 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1635
1636 /* Issue host command */
1637 cecr_subblock =
1638 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1639 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1640 QE_CR_PROTOCOL_ETHERNET, 0);
1641
1642 /* Wait for command to complete */
1643 do {
1644 msleep(10);
1645 temp = in_be32(uccf->p_ucce);
1646 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1647
1648 uccf->stopped_tx = 1;
1649
1650 return 0;
1651 }
1652
1653 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1654 {
1655 struct ucc_fast_private *uccf;
1656 u32 cecr_subblock;
1657 u8 temp;
1658 int i = 10;
1659
1660 uccf = ugeth->uccf;
1661
1662 /* Clear acknowledge bit */
1663 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1664 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1665 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1666
1667 /* Keep issuing command and checking acknowledge bit until
1668 it is asserted, according to spec */
1669 do {
1670 /* Issue host command */
1671 cecr_subblock =
1672 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1673 ucc_num);
1674 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1675 QE_CR_PROTOCOL_ETHERNET, 0);
1676 msleep(10);
1677 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1678 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1679
1680 uccf->stopped_rx = 1;
1681
1682 return 0;
1683 }
1684
1685 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1686 {
1687 struct ucc_fast_private *uccf;
1688 u32 cecr_subblock;
1689
1690 uccf = ugeth->uccf;
1691
1692 cecr_subblock =
1693 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1694 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1695 uccf->stopped_tx = 0;
1696
1697 return 0;
1698 }
1699
1700 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1701 {
1702 struct ucc_fast_private *uccf;
1703 u32 cecr_subblock;
1704
1705 uccf = ugeth->uccf;
1706
1707 cecr_subblock =
1708 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1709 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1710 0);
1711 uccf->stopped_rx = 0;
1712
1713 return 0;
1714 }
1715
1716 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1717 {
1718 struct ucc_fast_private *uccf;
1719 int enabled_tx, enabled_rx;
1720
1721 uccf = ugeth->uccf;
1722
1723 /* check if the UCC number is in range. */
1724 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1725 if (netif_msg_probe(ugeth))
1726 ugeth_err("%s: ucc_num out of range.", __func__);
1727 return -EINVAL;
1728 }
1729
1730 enabled_tx = uccf->enabled_tx;
1731 enabled_rx = uccf->enabled_rx;
1732
1733 /* Get Tx and Rx going again, in case this channel was actively
1734 disabled. */
1735 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1736 ugeth_restart_tx(ugeth);
1737 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1738 ugeth_restart_rx(ugeth);
1739
1740 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1741
1742 return 0;
1743
1744 }
1745
1746 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1747 {
1748 struct ucc_fast_private *uccf;
1749
1750 uccf = ugeth->uccf;
1751
1752 /* check if the UCC number is in range. */
1753 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1754 if (netif_msg_probe(ugeth))
1755 ugeth_err("%s: ucc_num out of range.", __func__);
1756 return -EINVAL;
1757 }
1758
1759 /* Stop any transmissions */
1760 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1761 ugeth_graceful_stop_tx(ugeth);
1762
1763 /* Stop any receptions */
1764 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1765 ugeth_graceful_stop_rx(ugeth);
1766
1767 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1768
1769 return 0;
1770 }
1771
1772 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1773 {
1774 #ifdef DEBUG
1775 ucc_fast_dump_regs(ugeth->uccf);
1776 dump_regs(ugeth);
1777 dump_bds(ugeth);
1778 #endif
1779 }
1780
1781 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1782 ugeth,
1783 enum enet_addr_type
1784 enet_addr_type)
1785 {
1786 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1787 struct ucc_fast_private *uccf;
1788 enum comm_dir comm_dir;
1789 struct list_head *p_lh;
1790 u16 i, num;
1791 u32 __iomem *addr_h;
1792 u32 __iomem *addr_l;
1793 u8 *p_counter;
1794
1795 uccf = ugeth->uccf;
1796
1797 p_82xx_addr_filt =
1798 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1799 ugeth->p_rx_glbl_pram->addressfiltering;
1800
1801 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1802 addr_h = &(p_82xx_addr_filt->gaddr_h);
1803 addr_l = &(p_82xx_addr_filt->gaddr_l);
1804 p_lh = &ugeth->group_hash_q;
1805 p_counter = &(ugeth->numGroupAddrInHash);
1806 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1807 addr_h = &(p_82xx_addr_filt->iaddr_h);
1808 addr_l = &(p_82xx_addr_filt->iaddr_l);
1809 p_lh = &ugeth->ind_hash_q;
1810 p_counter = &(ugeth->numIndAddrInHash);
1811 } else
1812 return -EINVAL;
1813
1814 comm_dir = 0;
1815 if (uccf->enabled_tx)
1816 comm_dir |= COMM_DIR_TX;
1817 if (uccf->enabled_rx)
1818 comm_dir |= COMM_DIR_RX;
1819 if (comm_dir)
1820 ugeth_disable(ugeth, comm_dir);
1821
1822 /* Clear the hash table. */
1823 out_be32(addr_h, 0x00000000);
1824 out_be32(addr_l, 0x00000000);
1825
1826 if (!p_lh)
1827 return 0;
1828
1829 num = *p_counter;
1830
1831 /* Delete all remaining CQ elements */
1832 for (i = 0; i < num; i++)
1833 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1834
1835 *p_counter = 0;
1836
1837 if (comm_dir)
1838 ugeth_enable(ugeth, comm_dir);
1839
1840 return 0;
1841 }
1842
1843 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1844 u8 paddr_num)
1845 {
1846 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1847 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1848 }
1849
1850 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1851 {
1852 u16 i, j;
1853 u8 __iomem *bd;
1854
1855 if (!ugeth)
1856 return;
1857
1858 if (ugeth->uccf) {
1859 ucc_fast_free(ugeth->uccf);
1860 ugeth->uccf = NULL;
1861 }
1862
1863 if (ugeth->p_thread_data_tx) {
1864 qe_muram_free(ugeth->thread_dat_tx_offset);
1865 ugeth->p_thread_data_tx = NULL;
1866 }
1867 if (ugeth->p_thread_data_rx) {
1868 qe_muram_free(ugeth->thread_dat_rx_offset);
1869 ugeth->p_thread_data_rx = NULL;
1870 }
1871 if (ugeth->p_exf_glbl_param) {
1872 qe_muram_free(ugeth->exf_glbl_param_offset);
1873 ugeth->p_exf_glbl_param = NULL;
1874 }
1875 if (ugeth->p_rx_glbl_pram) {
1876 qe_muram_free(ugeth->rx_glbl_pram_offset);
1877 ugeth->p_rx_glbl_pram = NULL;
1878 }
1879 if (ugeth->p_tx_glbl_pram) {
1880 qe_muram_free(ugeth->tx_glbl_pram_offset);
1881 ugeth->p_tx_glbl_pram = NULL;
1882 }
1883 if (ugeth->p_send_q_mem_reg) {
1884 qe_muram_free(ugeth->send_q_mem_reg_offset);
1885 ugeth->p_send_q_mem_reg = NULL;
1886 }
1887 if (ugeth->p_scheduler) {
1888 qe_muram_free(ugeth->scheduler_offset);
1889 ugeth->p_scheduler = NULL;
1890 }
1891 if (ugeth->p_tx_fw_statistics_pram) {
1892 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1893 ugeth->p_tx_fw_statistics_pram = NULL;
1894 }
1895 if (ugeth->p_rx_fw_statistics_pram) {
1896 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1897 ugeth->p_rx_fw_statistics_pram = NULL;
1898 }
1899 if (ugeth->p_rx_irq_coalescing_tbl) {
1900 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1901 ugeth->p_rx_irq_coalescing_tbl = NULL;
1902 }
1903 if (ugeth->p_rx_bd_qs_tbl) {
1904 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1905 ugeth->p_rx_bd_qs_tbl = NULL;
1906 }
1907 if (ugeth->p_init_enet_param_shadow) {
1908 return_init_enet_entries(ugeth,
1909 &(ugeth->p_init_enet_param_shadow->
1910 rxthread[0]),
1911 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1912 ugeth->ug_info->riscRx, 1);
1913 return_init_enet_entries(ugeth,
1914 &(ugeth->p_init_enet_param_shadow->
1915 txthread[0]),
1916 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1917 ugeth->ug_info->riscTx, 0);
1918 kfree(ugeth->p_init_enet_param_shadow);
1919 ugeth->p_init_enet_param_shadow = NULL;
1920 }
1921 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1922 bd = ugeth->p_tx_bd_ring[i];
1923 if (!bd)
1924 continue;
1925 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1926 if (ugeth->tx_skbuff[i][j]) {
1927 dma_unmap_single(ugeth->dev,
1928 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1929 (in_be32((u32 __iomem *)bd) &
1930 BD_LENGTH_MASK),
1931 DMA_TO_DEVICE);
1932 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1933 ugeth->tx_skbuff[i][j] = NULL;
1934 }
1935 }
1936
1937 kfree(ugeth->tx_skbuff[i]);
1938
1939 if (ugeth->p_tx_bd_ring[i]) {
1940 if (ugeth->ug_info->uf_info.bd_mem_part ==
1941 MEM_PART_SYSTEM)
1942 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1943 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1944 MEM_PART_MURAM)
1945 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1946 ugeth->p_tx_bd_ring[i] = NULL;
1947 }
1948 }
1949 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1950 if (ugeth->p_rx_bd_ring[i]) {
1951 /* Return existing data buffers in ring */
1952 bd = ugeth->p_rx_bd_ring[i];
1953 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1954 if (ugeth->rx_skbuff[i][j]) {
1955 dma_unmap_single(ugeth->dev,
1956 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1957 ugeth->ug_info->
1958 uf_info.max_rx_buf_length +
1959 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1960 DMA_FROM_DEVICE);
1961 dev_kfree_skb_any(
1962 ugeth->rx_skbuff[i][j]);
1963 ugeth->rx_skbuff[i][j] = NULL;
1964 }
1965 bd += sizeof(struct qe_bd);
1966 }
1967
1968 kfree(ugeth->rx_skbuff[i]);
1969
1970 if (ugeth->ug_info->uf_info.bd_mem_part ==
1971 MEM_PART_SYSTEM)
1972 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1973 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1974 MEM_PART_MURAM)
1975 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1976 ugeth->p_rx_bd_ring[i] = NULL;
1977 }
1978 }
1979 while (!list_empty(&ugeth->group_hash_q))
1980 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1981 (dequeue(&ugeth->group_hash_q)));
1982 while (!list_empty(&ugeth->ind_hash_q))
1983 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1984 (dequeue(&ugeth->ind_hash_q)));
1985 if (ugeth->ug_regs) {
1986 iounmap(ugeth->ug_regs);
1987 ugeth->ug_regs = NULL;
1988 }
1989 }
1990
1991 static void ucc_geth_set_multi(struct net_device *dev)
1992 {
1993 struct ucc_geth_private *ugeth;
1994 struct dev_mc_list *dmi;
1995 struct ucc_fast __iomem *uf_regs;
1996 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1997 int i;
1998
1999 ugeth = netdev_priv(dev);
2000
2001 uf_regs = ugeth->uccf->uf_regs;
2002
2003 if (dev->flags & IFF_PROMISC) {
2004 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2005 } else {
2006 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2007
2008 p_82xx_addr_filt =
2009 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2010 p_rx_glbl_pram->addressfiltering;
2011
2012 if (dev->flags & IFF_ALLMULTI) {
2013 /* Catch all multicast addresses, so set the
2014 * filter to all 1's.
2015 */
2016 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2017 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2018 } else {
2019 /* Clear filter and add the addresses in the list.
2020 */
2021 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2022 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2023
2024 dmi = dev->mc_list;
2025
2026 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2027
2028 /* Only support group multicast for now.
2029 */
2030 if (!(dmi->dmi_addr[0] & 1))
2031 continue;
2032
2033 /* Ask CPM to run CRC and set bit in
2034 * filter mask.
2035 */
2036 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
2037 }
2038 }
2039 }
2040 }
2041
2042 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2043 {
2044 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2045 struct phy_device *phydev = ugeth->phydev;
2046
2047 ugeth_vdbg("%s: IN", __func__);
2048
2049 /* Disable the controller */
2050 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2051
2052 /* Tell the kernel the link is down */
2053 phy_stop(phydev);
2054
2055 /* Mask all interrupts */
2056 out_be32(ugeth->uccf->p_uccm, 0x00000000);
2057
2058 /* Clear all interrupts */
2059 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2060
2061 /* Disable Rx and Tx */
2062 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2063
2064 phy_disconnect(ugeth->phydev);
2065 ugeth->phydev = NULL;
2066
2067 ucc_geth_memclean(ugeth);
2068 }
2069
2070 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2071 {
2072 struct ucc_geth_info *ug_info;
2073 struct ucc_fast_info *uf_info;
2074 int i;
2075
2076 ug_info = ugeth->ug_info;
2077 uf_info = &ug_info->uf_info;
2078
2079 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2080 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2081 if (netif_msg_probe(ugeth))
2082 ugeth_err("%s: Bad memory partition value.",
2083 __func__);
2084 return -EINVAL;
2085 }
2086
2087 /* Rx BD lengths */
2088 for (i = 0; i < ug_info->numQueuesRx; i++) {
2089 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2090 (ug_info->bdRingLenRx[i] %
2091 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2092 if (netif_msg_probe(ugeth))
2093 ugeth_err
2094 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2095 __func__);
2096 return -EINVAL;
2097 }
2098 }
2099
2100 /* Tx BD lengths */
2101 for (i = 0; i < ug_info->numQueuesTx; i++) {
2102 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2103 if (netif_msg_probe(ugeth))
2104 ugeth_err
2105 ("%s: Tx BD ring length must be no smaller than 2.",
2106 __func__);
2107 return -EINVAL;
2108 }
2109 }
2110
2111 /* mrblr */
2112 if ((uf_info->max_rx_buf_length == 0) ||
2113 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2114 if (netif_msg_probe(ugeth))
2115 ugeth_err
2116 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2117 __func__);
2118 return -EINVAL;
2119 }
2120
2121 /* num Tx queues */
2122 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2123 if (netif_msg_probe(ugeth))
2124 ugeth_err("%s: number of tx queues too large.", __func__);
2125 return -EINVAL;
2126 }
2127
2128 /* num Rx queues */
2129 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2130 if (netif_msg_probe(ugeth))
2131 ugeth_err("%s: number of rx queues too large.", __func__);
2132 return -EINVAL;
2133 }
2134
2135 /* l2qt */
2136 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2137 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2138 if (netif_msg_probe(ugeth))
2139 ugeth_err
2140 ("%s: VLAN priority table entry must not be"
2141 " larger than number of Rx queues.",
2142 __func__);
2143 return -EINVAL;
2144 }
2145 }
2146
2147 /* l3qt */
2148 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2149 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2150 if (netif_msg_probe(ugeth))
2151 ugeth_err
2152 ("%s: IP priority table entry must not be"
2153 " larger than number of Rx queues.",
2154 __func__);
2155 return -EINVAL;
2156 }
2157 }
2158
2159 if (ug_info->cam && !ug_info->ecamptr) {
2160 if (netif_msg_probe(ugeth))
2161 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2162 __func__);
2163 return -EINVAL;
2164 }
2165
2166 if ((ug_info->numStationAddresses !=
2167 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2168 && ug_info->rxExtendedFiltering) {
2169 if (netif_msg_probe(ugeth))
2170 ugeth_err("%s: Number of station addresses greater than 1 "
2171 "not allowed in extended parsing mode.",
2172 __func__);
2173 return -EINVAL;
2174 }
2175
2176 /* Generate uccm_mask for receive */
2177 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2178 for (i = 0; i < ug_info->numQueuesRx; i++)
2179 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2180
2181 for (i = 0; i < ug_info->numQueuesTx; i++)
2182 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2183 /* Initialize the general fast UCC block. */
2184 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2185 if (netif_msg_probe(ugeth))
2186 ugeth_err("%s: Failed to init uccf.", __func__);
2187 return -ENOMEM;
2188 }
2189
2190 /* read the number of risc engines, update the riscTx and riscRx
2191 * if there are 4 riscs in QE
2192 */
2193 if (qe_get_num_of_risc() == 4) {
2194 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2195 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2196 }
2197
2198 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2199 if (!ugeth->ug_regs) {
2200 if (netif_msg_probe(ugeth))
2201 ugeth_err("%s: Failed to ioremap regs.", __func__);
2202 return -ENOMEM;
2203 }
2204
2205 return 0;
2206 }
2207
2208 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2209 {
2210 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2211 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2212 struct ucc_fast_private *uccf;
2213 struct ucc_geth_info *ug_info;
2214 struct ucc_fast_info *uf_info;
2215 struct ucc_fast __iomem *uf_regs;
2216 struct ucc_geth __iomem *ug_regs;
2217 int ret_val = -EINVAL;
2218 u32 remoder = UCC_GETH_REMODER_INIT;
2219 u32 init_enet_pram_offset, cecr_subblock, command;
2220 u32 ifstat, i, j, size, l2qt, l3qt, length;
2221 u16 temoder = UCC_GETH_TEMODER_INIT;
2222 u16 test;
2223 u8 function_code = 0;
2224 u8 __iomem *bd;
2225 u8 __iomem *endOfRing;
2226 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2227
2228 ugeth_vdbg("%s: IN", __func__);
2229 uccf = ugeth->uccf;
2230 ug_info = ugeth->ug_info;
2231 uf_info = &ug_info->uf_info;
2232 uf_regs = uccf->uf_regs;
2233 ug_regs = ugeth->ug_regs;
2234
2235 switch (ug_info->numThreadsRx) {
2236 case UCC_GETH_NUM_OF_THREADS_1:
2237 numThreadsRxNumerical = 1;
2238 break;
2239 case UCC_GETH_NUM_OF_THREADS_2:
2240 numThreadsRxNumerical = 2;
2241 break;
2242 case UCC_GETH_NUM_OF_THREADS_4:
2243 numThreadsRxNumerical = 4;
2244 break;
2245 case UCC_GETH_NUM_OF_THREADS_6:
2246 numThreadsRxNumerical = 6;
2247 break;
2248 case UCC_GETH_NUM_OF_THREADS_8:
2249 numThreadsRxNumerical = 8;
2250 break;
2251 default:
2252 if (netif_msg_ifup(ugeth))
2253 ugeth_err("%s: Bad number of Rx threads value.",
2254 __func__);
2255 return -EINVAL;
2256 break;
2257 }
2258
2259 switch (ug_info->numThreadsTx) {
2260 case UCC_GETH_NUM_OF_THREADS_1:
2261 numThreadsTxNumerical = 1;
2262 break;
2263 case UCC_GETH_NUM_OF_THREADS_2:
2264 numThreadsTxNumerical = 2;
2265 break;
2266 case UCC_GETH_NUM_OF_THREADS_4:
2267 numThreadsTxNumerical = 4;
2268 break;
2269 case UCC_GETH_NUM_OF_THREADS_6:
2270 numThreadsTxNumerical = 6;
2271 break;
2272 case UCC_GETH_NUM_OF_THREADS_8:
2273 numThreadsTxNumerical = 8;
2274 break;
2275 default:
2276 if (netif_msg_ifup(ugeth))
2277 ugeth_err("%s: Bad number of Tx threads value.",
2278 __func__);
2279 return -EINVAL;
2280 break;
2281 }
2282
2283 /* Calculate rx_extended_features */
2284 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2285 ug_info->ipAddressAlignment ||
2286 (ug_info->numStationAddresses !=
2287 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2288
2289 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2290 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2291 || (ug_info->vlanOperationNonTagged !=
2292 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2293
2294 init_default_reg_vals(&uf_regs->upsmr,
2295 &ug_regs->maccfg1, &ug_regs->maccfg2);
2296
2297 /* Set UPSMR */
2298 /* For more details see the hardware spec. */
2299 init_rx_parameters(ug_info->bro,
2300 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2301
2302 /* We're going to ignore other registers for now, */
2303 /* except as needed to get up and running */
2304
2305 /* Set MACCFG1 */
2306 /* For more details see the hardware spec. */
2307 init_flow_control_params(ug_info->aufc,
2308 ug_info->receiveFlowControl,
2309 ug_info->transmitFlowControl,
2310 ug_info->pausePeriod,
2311 ug_info->extensionField,
2312 &uf_regs->upsmr,
2313 &ug_regs->uempr, &ug_regs->maccfg1);
2314
2315 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2316
2317 /* Set IPGIFG */
2318 /* For more details see the hardware spec. */
2319 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2320 ug_info->nonBackToBackIfgPart2,
2321 ug_info->
2322 miminumInterFrameGapEnforcement,
2323 ug_info->backToBackInterFrameGap,
2324 &ug_regs->ipgifg);
2325 if (ret_val != 0) {
2326 if (netif_msg_ifup(ugeth))
2327 ugeth_err("%s: IPGIFG initialization parameter too large.",
2328 __func__);
2329 return ret_val;
2330 }
2331
2332 /* Set HAFDUP */
2333 /* For more details see the hardware spec. */
2334 ret_val = init_half_duplex_params(ug_info->altBeb,
2335 ug_info->backPressureNoBackoff,
2336 ug_info->noBackoff,
2337 ug_info->excessDefer,
2338 ug_info->altBebTruncation,
2339 ug_info->maxRetransmission,
2340 ug_info->collisionWindow,
2341 &ug_regs->hafdup);
2342 if (ret_val != 0) {
2343 if (netif_msg_ifup(ugeth))
2344 ugeth_err("%s: Half Duplex initialization parameter too large.",
2345 __func__);
2346 return ret_val;
2347 }
2348
2349 /* Set IFSTAT */
2350 /* For more details see the hardware spec. */
2351 /* Read only - resets upon read */
2352 ifstat = in_be32(&ug_regs->ifstat);
2353
2354 /* Clear UEMPR */
2355 /* For more details see the hardware spec. */
2356 out_be32(&ug_regs->uempr, 0);
2357
2358 /* Set UESCR */
2359 /* For more details see the hardware spec. */
2360 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2361 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2362 0, &uf_regs->upsmr, &ug_regs->uescr);
2363
2364 /* Allocate Tx bds */
2365 for (j = 0; j < ug_info->numQueuesTx; j++) {
2366 /* Allocate in multiple of
2367 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2368 according to spec */
2369 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2370 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2371 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2372 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2373 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2374 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2375 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2376 u32 align = 4;
2377 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2378 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2379 ugeth->tx_bd_ring_offset[j] =
2380 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2381
2382 if (ugeth->tx_bd_ring_offset[j] != 0)
2383 ugeth->p_tx_bd_ring[j] =
2384 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2385 align) & ~(align - 1));
2386 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2387 ugeth->tx_bd_ring_offset[j] =
2388 qe_muram_alloc(length,
2389 UCC_GETH_TX_BD_RING_ALIGNMENT);
2390 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2391 ugeth->p_tx_bd_ring[j] =
2392 (u8 __iomem *) qe_muram_addr(ugeth->
2393 tx_bd_ring_offset[j]);
2394 }
2395 if (!ugeth->p_tx_bd_ring[j]) {
2396 if (netif_msg_ifup(ugeth))
2397 ugeth_err
2398 ("%s: Can not allocate memory for Tx bd rings.",
2399 __func__);
2400 return -ENOMEM;
2401 }
2402 /* Zero unused end of bd ring, according to spec */
2403 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2404 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2405 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2406 }
2407
2408 /* Allocate Rx bds */
2409 for (j = 0; j < ug_info->numQueuesRx; j++) {
2410 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2411 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2412 u32 align = 4;
2413 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2414 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2415 ugeth->rx_bd_ring_offset[j] =
2416 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2417 if (ugeth->rx_bd_ring_offset[j] != 0)
2418 ugeth->p_rx_bd_ring[j] =
2419 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2420 align) & ~(align - 1));
2421 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2422 ugeth->rx_bd_ring_offset[j] =
2423 qe_muram_alloc(length,
2424 UCC_GETH_RX_BD_RING_ALIGNMENT);
2425 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2426 ugeth->p_rx_bd_ring[j] =
2427 (u8 __iomem *) qe_muram_addr(ugeth->
2428 rx_bd_ring_offset[j]);
2429 }
2430 if (!ugeth->p_rx_bd_ring[j]) {
2431 if (netif_msg_ifup(ugeth))
2432 ugeth_err
2433 ("%s: Can not allocate memory for Rx bd rings.",
2434 __func__);
2435 return -ENOMEM;
2436 }
2437 }
2438
2439 /* Init Tx bds */
2440 for (j = 0; j < ug_info->numQueuesTx; j++) {
2441 /* Setup the skbuff rings */
2442 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2443 ugeth->ug_info->bdRingLenTx[j],
2444 GFP_KERNEL);
2445
2446 if (ugeth->tx_skbuff[j] == NULL) {
2447 if (netif_msg_ifup(ugeth))
2448 ugeth_err("%s: Could not allocate tx_skbuff",
2449 __func__);
2450 return -ENOMEM;
2451 }
2452
2453 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2454 ugeth->tx_skbuff[j][i] = NULL;
2455
2456 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2457 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2458 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2459 /* clear bd buffer */
2460 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2461 /* set bd status and length */
2462 out_be32((u32 __iomem *)bd, 0);
2463 bd += sizeof(struct qe_bd);
2464 }
2465 bd -= sizeof(struct qe_bd);
2466 /* set bd status and length */
2467 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2468 }
2469
2470 /* Init Rx bds */
2471 for (j = 0; j < ug_info->numQueuesRx; j++) {
2472 /* Setup the skbuff rings */
2473 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2474 ugeth->ug_info->bdRingLenRx[j],
2475 GFP_KERNEL);
2476
2477 if (ugeth->rx_skbuff[j] == NULL) {
2478 if (netif_msg_ifup(ugeth))
2479 ugeth_err("%s: Could not allocate rx_skbuff",
2480 __func__);
2481 return -ENOMEM;
2482 }
2483
2484 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2485 ugeth->rx_skbuff[j][i] = NULL;
2486
2487 ugeth->skb_currx[j] = 0;
2488 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2489 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2490 /* set bd status and length */
2491 out_be32((u32 __iomem *)bd, R_I);
2492 /* clear bd buffer */
2493 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2494 bd += sizeof(struct qe_bd);
2495 }
2496 bd -= sizeof(struct qe_bd);
2497 /* set bd status and length */
2498 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2499 }
2500
2501 /*
2502 * Global PRAM
2503 */
2504 /* Tx global PRAM */
2505 /* Allocate global tx parameter RAM page */
2506 ugeth->tx_glbl_pram_offset =
2507 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2508 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2509 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2510 if (netif_msg_ifup(ugeth))
2511 ugeth_err
2512 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2513 __func__);
2514 return -ENOMEM;
2515 }
2516 ugeth->p_tx_glbl_pram =
2517 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2518 tx_glbl_pram_offset);
2519 /* Zero out p_tx_glbl_pram */
2520 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2521
2522 /* Fill global PRAM */
2523
2524 /* TQPTR */
2525 /* Size varies with number of Tx threads */
2526 ugeth->thread_dat_tx_offset =
2527 qe_muram_alloc(numThreadsTxNumerical *
2528 sizeof(struct ucc_geth_thread_data_tx) +
2529 32 * (numThreadsTxNumerical == 1),
2530 UCC_GETH_THREAD_DATA_ALIGNMENT);
2531 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2532 if (netif_msg_ifup(ugeth))
2533 ugeth_err
2534 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2535 __func__);
2536 return -ENOMEM;
2537 }
2538
2539 ugeth->p_thread_data_tx =
2540 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2541 thread_dat_tx_offset);
2542 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2543
2544 /* vtagtable */
2545 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2546 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2547 ug_info->vtagtable[i]);
2548
2549 /* iphoffset */
2550 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2551 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2552 ug_info->iphoffset[i]);
2553
2554 /* SQPTR */
2555 /* Size varies with number of Tx queues */
2556 ugeth->send_q_mem_reg_offset =
2557 qe_muram_alloc(ug_info->numQueuesTx *
2558 sizeof(struct ucc_geth_send_queue_qd),
2559 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2560 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2561 if (netif_msg_ifup(ugeth))
2562 ugeth_err
2563 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2564 __func__);
2565 return -ENOMEM;
2566 }
2567
2568 ugeth->p_send_q_mem_reg =
2569 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2570 send_q_mem_reg_offset);
2571 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2572
2573 /* Setup the table */
2574 /* Assume BD rings are already established */
2575 for (i = 0; i < ug_info->numQueuesTx; i++) {
2576 endOfRing =
2577 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2578 1) * sizeof(struct qe_bd);
2579 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2580 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2581 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2582 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2583 last_bd_completed_address,
2584 (u32) virt_to_phys(endOfRing));
2585 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2586 MEM_PART_MURAM) {
2587 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2588 (u32) immrbar_virt_to_phys(ugeth->
2589 p_tx_bd_ring[i]));
2590 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2591 last_bd_completed_address,
2592 (u32) immrbar_virt_to_phys(endOfRing));
2593 }
2594 }
2595
2596 /* schedulerbasepointer */
2597
2598 if (ug_info->numQueuesTx > 1) {
2599 /* scheduler exists only if more than 1 tx queue */
2600 ugeth->scheduler_offset =
2601 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2602 UCC_GETH_SCHEDULER_ALIGNMENT);
2603 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2604 if (netif_msg_ifup(ugeth))
2605 ugeth_err
2606 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2607 __func__);
2608 return -ENOMEM;
2609 }
2610
2611 ugeth->p_scheduler =
2612 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2613 scheduler_offset);
2614 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2615 ugeth->scheduler_offset);
2616 /* Zero out p_scheduler */
2617 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2618
2619 /* Set values in scheduler */
2620 out_be32(&ugeth->p_scheduler->mblinterval,
2621 ug_info->mblinterval);
2622 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2623 ug_info->nortsrbytetime);
2624 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2625 out_8(&ugeth->p_scheduler->strictpriorityq,
2626 ug_info->strictpriorityq);
2627 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2628 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2629 for (i = 0; i < NUM_TX_QUEUES; i++)
2630 out_8(&ugeth->p_scheduler->weightfactor[i],
2631 ug_info->weightfactor[i]);
2632
2633 /* Set pointers to cpucount registers in scheduler */
2634 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2635 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2636 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2637 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2638 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2639 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2640 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2641 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2642 }
2643
2644 /* schedulerbasepointer */
2645 /* TxRMON_PTR (statistics) */
2646 if (ug_info->
2647 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2648 ugeth->tx_fw_statistics_pram_offset =
2649 qe_muram_alloc(sizeof
2650 (struct ucc_geth_tx_firmware_statistics_pram),
2651 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2652 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2653 if (netif_msg_ifup(ugeth))
2654 ugeth_err
2655 ("%s: Can not allocate DPRAM memory for"
2656 " p_tx_fw_statistics_pram.",
2657 __func__);
2658 return -ENOMEM;
2659 }
2660 ugeth->p_tx_fw_statistics_pram =
2661 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2662 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2663 /* Zero out p_tx_fw_statistics_pram */
2664 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2665 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2666 }
2667
2668 /* temoder */
2669 /* Already has speed set */
2670
2671 if (ug_info->numQueuesTx > 1)
2672 temoder |= TEMODER_SCHEDULER_ENABLE;
2673 if (ug_info->ipCheckSumGenerate)
2674 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2675 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2676 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2677
2678 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2679
2680 /* Function code register value to be used later */
2681 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2682 /* Required for QE */
2683
2684 /* function code register */
2685 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2686
2687 /* Rx global PRAM */
2688 /* Allocate global rx parameter RAM page */
2689 ugeth->rx_glbl_pram_offset =
2690 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2691 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2692 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2693 if (netif_msg_ifup(ugeth))
2694 ugeth_err
2695 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2696 __func__);
2697 return -ENOMEM;
2698 }
2699 ugeth->p_rx_glbl_pram =
2700 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2701 rx_glbl_pram_offset);
2702 /* Zero out p_rx_glbl_pram */
2703 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2704
2705 /* Fill global PRAM */
2706
2707 /* RQPTR */
2708 /* Size varies with number of Rx threads */
2709 ugeth->thread_dat_rx_offset =
2710 qe_muram_alloc(numThreadsRxNumerical *
2711 sizeof(struct ucc_geth_thread_data_rx),
2712 UCC_GETH_THREAD_DATA_ALIGNMENT);
2713 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2714 if (netif_msg_ifup(ugeth))
2715 ugeth_err
2716 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2717 __func__);
2718 return -ENOMEM;
2719 }
2720
2721 ugeth->p_thread_data_rx =
2722 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2723 thread_dat_rx_offset);
2724 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2725
2726 /* typeorlen */
2727 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2728
2729 /* rxrmonbaseptr (statistics) */
2730 if (ug_info->
2731 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2732 ugeth->rx_fw_statistics_pram_offset =
2733 qe_muram_alloc(sizeof
2734 (struct ucc_geth_rx_firmware_statistics_pram),
2735 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2736 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2737 if (netif_msg_ifup(ugeth))
2738 ugeth_err
2739 ("%s: Can not allocate DPRAM memory for"
2740 " p_rx_fw_statistics_pram.", __func__);
2741 return -ENOMEM;
2742 }
2743 ugeth->p_rx_fw_statistics_pram =
2744 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2745 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2746 /* Zero out p_rx_fw_statistics_pram */
2747 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2748 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2749 }
2750
2751 /* intCoalescingPtr */
2752
2753 /* Size varies with number of Rx queues */
2754 ugeth->rx_irq_coalescing_tbl_offset =
2755 qe_muram_alloc(ug_info->numQueuesRx *
2756 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2757 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2758 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2759 if (netif_msg_ifup(ugeth))
2760 ugeth_err
2761 ("%s: Can not allocate DPRAM memory for"
2762 " p_rx_irq_coalescing_tbl.", __func__);
2763 return -ENOMEM;
2764 }
2765
2766 ugeth->p_rx_irq_coalescing_tbl =
2767 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2768 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2769 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2770 ugeth->rx_irq_coalescing_tbl_offset);
2771
2772 /* Fill interrupt coalescing table */
2773 for (i = 0; i < ug_info->numQueuesRx; i++) {
2774 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2775 interruptcoalescingmaxvalue,
2776 ug_info->interruptcoalescingmaxvalue[i]);
2777 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2778 interruptcoalescingcounter,
2779 ug_info->interruptcoalescingmaxvalue[i]);
2780 }
2781
2782 /* MRBLR */
2783 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2784 &ugeth->p_rx_glbl_pram->mrblr);
2785 /* MFLR */
2786 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2787 /* MINFLR */
2788 init_min_frame_len(ug_info->minFrameLength,
2789 &ugeth->p_rx_glbl_pram->minflr,
2790 &ugeth->p_rx_glbl_pram->mrblr);
2791 /* MAXD1 */
2792 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2793 /* MAXD2 */
2794 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2795
2796 /* l2qt */
2797 l2qt = 0;
2798 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2799 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2800 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2801
2802 /* l3qt */
2803 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2804 l3qt = 0;
2805 for (i = 0; i < 8; i++)
2806 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2807 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2808 }
2809
2810 /* vlantype */
2811 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2812
2813 /* vlantci */
2814 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2815
2816 /* ecamptr */
2817 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2818
2819 /* RBDQPTR */
2820 /* Size varies with number of Rx queues */
2821 ugeth->rx_bd_qs_tbl_offset =
2822 qe_muram_alloc(ug_info->numQueuesRx *
2823 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2824 sizeof(struct ucc_geth_rx_prefetched_bds)),
2825 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2826 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2827 if (netif_msg_ifup(ugeth))
2828 ugeth_err
2829 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2830 __func__);
2831 return -ENOMEM;
2832 }
2833
2834 ugeth->p_rx_bd_qs_tbl =
2835 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2836 rx_bd_qs_tbl_offset);
2837 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2838 /* Zero out p_rx_bd_qs_tbl */
2839 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2840 0,
2841 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2842 sizeof(struct ucc_geth_rx_prefetched_bds)));
2843
2844 /* Setup the table */
2845 /* Assume BD rings are already established */
2846 for (i = 0; i < ug_info->numQueuesRx; i++) {
2847 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2848 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2849 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2850 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2851 MEM_PART_MURAM) {
2852 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2853 (u32) immrbar_virt_to_phys(ugeth->
2854 p_rx_bd_ring[i]));
2855 }
2856 /* rest of fields handled by QE */
2857 }
2858
2859 /* remoder */
2860 /* Already has speed set */
2861
2862 if (ugeth->rx_extended_features)
2863 remoder |= REMODER_RX_EXTENDED_FEATURES;
2864 if (ug_info->rxExtendedFiltering)
2865 remoder |= REMODER_RX_EXTENDED_FILTERING;
2866 if (ug_info->dynamicMaxFrameLength)
2867 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2868 if (ug_info->dynamicMinFrameLength)
2869 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2870 remoder |=
2871 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2872 remoder |=
2873 ug_info->
2874 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2875 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2876 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2877 if (ug_info->ipCheckSumCheck)
2878 remoder |= REMODER_IP_CHECKSUM_CHECK;
2879 if (ug_info->ipAddressAlignment)
2880 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2881 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2882
2883 /* Note that this function must be called */
2884 /* ONLY AFTER p_tx_fw_statistics_pram */
2885 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2886 init_firmware_statistics_gathering_mode((ug_info->
2887 statisticsMode &
2888 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2889 (ug_info->statisticsMode &
2890 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2891 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2892 ugeth->tx_fw_statistics_pram_offset,
2893 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2894 ugeth->rx_fw_statistics_pram_offset,
2895 &ugeth->p_tx_glbl_pram->temoder,
2896 &ugeth->p_rx_glbl_pram->remoder);
2897
2898 /* function code register */
2899 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2900
2901 /* initialize extended filtering */
2902 if (ug_info->rxExtendedFiltering) {
2903 if (!ug_info->extendedFilteringChainPointer) {
2904 if (netif_msg_ifup(ugeth))
2905 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2906 __func__);
2907 return -EINVAL;
2908 }
2909
2910 /* Allocate memory for extended filtering Mode Global
2911 Parameters */
2912 ugeth->exf_glbl_param_offset =
2913 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2914 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2915 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2916 if (netif_msg_ifup(ugeth))
2917 ugeth_err
2918 ("%s: Can not allocate DPRAM memory for"
2919 " p_exf_glbl_param.", __func__);
2920 return -ENOMEM;
2921 }
2922
2923 ugeth->p_exf_glbl_param =
2924 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2925 exf_glbl_param_offset);
2926 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2927 ugeth->exf_glbl_param_offset);
2928 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2929 (u32) ug_info->extendedFilteringChainPointer);
2930
2931 } else { /* initialize 82xx style address filtering */
2932
2933 /* Init individual address recognition registers to disabled */
2934
2935 for (j = 0; j < NUM_OF_PADDRS; j++)
2936 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2937
2938 p_82xx_addr_filt =
2939 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2940 p_rx_glbl_pram->addressfiltering;
2941
2942 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2943 ENET_ADDR_TYPE_GROUP);
2944 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2945 ENET_ADDR_TYPE_INDIVIDUAL);
2946 }
2947
2948 /*
2949 * Initialize UCC at QE level
2950 */
2951
2952 command = QE_INIT_TX_RX;
2953
2954 /* Allocate shadow InitEnet command parameter structure.
2955 * This is needed because after the InitEnet command is executed,
2956 * the structure in DPRAM is released, because DPRAM is a premium
2957 * resource.
2958 * This shadow structure keeps a copy of what was done so that the
2959 * allocated resources can be released when the channel is freed.
2960 */
2961 if (!(ugeth->p_init_enet_param_shadow =
2962 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2963 if (netif_msg_ifup(ugeth))
2964 ugeth_err
2965 ("%s: Can not allocate memory for"
2966 " p_UccInitEnetParamShadows.", __func__);
2967 return -ENOMEM;
2968 }
2969 /* Zero out *p_init_enet_param_shadow */
2970 memset((char *)ugeth->p_init_enet_param_shadow,
2971 0, sizeof(struct ucc_geth_init_pram));
2972
2973 /* Fill shadow InitEnet command parameter structure */
2974
2975 ugeth->p_init_enet_param_shadow->resinit1 =
2976 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2977 ugeth->p_init_enet_param_shadow->resinit2 =
2978 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2979 ugeth->p_init_enet_param_shadow->resinit3 =
2980 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2981 ugeth->p_init_enet_param_shadow->resinit4 =
2982 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2983 ugeth->p_init_enet_param_shadow->resinit5 =
2984 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2985 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2986 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2987 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2988 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2989
2990 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2991 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2992 if ((ug_info->largestexternallookupkeysize !=
2993 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
2994 && (ug_info->largestexternallookupkeysize !=
2995 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2996 && (ug_info->largestexternallookupkeysize !=
2997 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2998 if (netif_msg_ifup(ugeth))
2999 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3000 __func__);
3001 return -EINVAL;
3002 }
3003 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3004 ug_info->largestexternallookupkeysize;
3005 size = sizeof(struct ucc_geth_thread_rx_pram);
3006 if (ug_info->rxExtendedFiltering) {
3007 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3008 if (ug_info->largestexternallookupkeysize ==
3009 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3010 size +=
3011 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3012 if (ug_info->largestexternallookupkeysize ==
3013 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3014 size +=
3015 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3016 }
3017
3018 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3019 p_init_enet_param_shadow->rxthread[0]),
3020 (u8) (numThreadsRxNumerical + 1)
3021 /* Rx needs one extra for terminator */
3022 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3023 ug_info->riscRx, 1)) != 0) {
3024 if (netif_msg_ifup(ugeth))
3025 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3026 __func__);
3027 return ret_val;
3028 }
3029
3030 ugeth->p_init_enet_param_shadow->txglobal =
3031 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3032 if ((ret_val =
3033 fill_init_enet_entries(ugeth,
3034 &(ugeth->p_init_enet_param_shadow->
3035 txthread[0]), numThreadsTxNumerical,
3036 sizeof(struct ucc_geth_thread_tx_pram),
3037 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3038 ug_info->riscTx, 0)) != 0) {
3039 if (netif_msg_ifup(ugeth))
3040 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3041 __func__);
3042 return ret_val;
3043 }
3044
3045 /* Load Rx bds with buffers */
3046 for (i = 0; i < ug_info->numQueuesRx; i++) {
3047 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3048 if (netif_msg_ifup(ugeth))
3049 ugeth_err("%s: Can not fill Rx bds with buffers.",
3050 __func__);
3051 return ret_val;
3052 }
3053 }
3054
3055 /* Allocate InitEnet command parameter structure */
3056 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3057 if (IS_ERR_VALUE(init_enet_pram_offset)) {
3058 if (netif_msg_ifup(ugeth))
3059 ugeth_err
3060 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3061 __func__);
3062 return -ENOMEM;
3063 }
3064 p_init_enet_pram =
3065 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3066
3067 /* Copy shadow InitEnet command parameter structure into PRAM */
3068 out_8(&p_init_enet_pram->resinit1,
3069 ugeth->p_init_enet_param_shadow->resinit1);
3070 out_8(&p_init_enet_pram->resinit2,
3071 ugeth->p_init_enet_param_shadow->resinit2);
3072 out_8(&p_init_enet_pram->resinit3,
3073 ugeth->p_init_enet_param_shadow->resinit3);
3074 out_8(&p_init_enet_pram->resinit4,
3075 ugeth->p_init_enet_param_shadow->resinit4);
3076 out_be16(&p_init_enet_pram->resinit5,
3077 ugeth->p_init_enet_param_shadow->resinit5);
3078 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3079 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3080 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3081 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3082 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3083 out_be32(&p_init_enet_pram->rxthread[i],
3084 ugeth->p_init_enet_param_shadow->rxthread[i]);
3085 out_be32(&p_init_enet_pram->txglobal,
3086 ugeth->p_init_enet_param_shadow->txglobal);
3087 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3088 out_be32(&p_init_enet_pram->txthread[i],
3089 ugeth->p_init_enet_param_shadow->txthread[i]);
3090
3091 /* Issue QE command */
3092 cecr_subblock =
3093 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3094 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3095 init_enet_pram_offset);
3096
3097 /* Free InitEnet command parameter */
3098 qe_muram_free(init_enet_pram_offset);
3099
3100 return 0;
3101 }
3102
3103 /* This is called by the kernel when a frame is ready for transmission. */
3104 /* It is pointed to by the dev->hard_start_xmit function pointer */
3105 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3106 {
3107 struct ucc_geth_private *ugeth = netdev_priv(dev);
3108 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3109 struct ucc_fast_private *uccf;
3110 #endif
3111 u8 __iomem *bd; /* BD pointer */
3112 u32 bd_status;
3113 u8 txQ = 0;
3114
3115 ugeth_vdbg("%s: IN", __func__);
3116
3117 spin_lock_irq(&ugeth->lock);
3118
3119 dev->stats.tx_bytes += skb->len;
3120
3121 /* Start from the next BD that should be filled */
3122 bd = ugeth->txBd[txQ];
3123 bd_status = in_be32((u32 __iomem *)bd);
3124 /* Save the skb pointer so we can free it later */
3125 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3126
3127 /* Update the current skb pointer (wrapping if this was the last) */
3128 ugeth->skb_curtx[txQ] =
3129 (ugeth->skb_curtx[txQ] +
3130 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3131
3132 /* set up the buffer descriptor */
3133 out_be32(&((struct qe_bd __iomem *)bd)->buf,
3134 dma_map_single(ugeth->dev, skb->data,
3135 skb->len, DMA_TO_DEVICE));
3136
3137 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3138
3139 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3140
3141 /* set bd status and length */
3142 out_be32((u32 __iomem *)bd, bd_status);
3143
3144 dev->trans_start = jiffies;
3145
3146 /* Move to next BD in the ring */
3147 if (!(bd_status & T_W))
3148 bd += sizeof(struct qe_bd);
3149 else
3150 bd = ugeth->p_tx_bd_ring[txQ];
3151
3152 /* If the next BD still needs to be cleaned up, then the bds
3153 are full. We need to tell the kernel to stop sending us stuff. */
3154 if (bd == ugeth->confBd[txQ]) {
3155 if (!netif_queue_stopped(dev))
3156 netif_stop_queue(dev);
3157 }
3158
3159 ugeth->txBd[txQ] = bd;
3160
3161 if (ugeth->p_scheduler) {
3162 ugeth->cpucount[txQ]++;
3163 /* Indicate to QE that there are more Tx bds ready for
3164 transmission */
3165 /* This is done by writing a running counter of the bd
3166 count to the scheduler PRAM. */
3167 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3168 }
3169
3170 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3171 uccf = ugeth->uccf;
3172 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3173 #endif
3174 spin_unlock_irq(&ugeth->lock);
3175
3176 return NETDEV_TX_OK;
3177 }
3178
3179 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3180 {
3181 struct sk_buff *skb;
3182 u8 __iomem *bd;
3183 u16 length, howmany = 0;
3184 u32 bd_status;
3185 u8 *bdBuffer;
3186 struct net_device *dev;
3187
3188 ugeth_vdbg("%s: IN", __func__);
3189
3190 dev = ugeth->ndev;
3191
3192 /* collect received buffers */
3193 bd = ugeth->rxBd[rxQ];
3194
3195 bd_status = in_be32((u32 __iomem *)bd);
3196
3197 /* while there are received buffers and BD is full (~R_E) */
3198 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3199 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3200 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3201 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3202
3203 /* determine whether buffer is first, last, first and last
3204 (single buffer frame) or middle (not first and not last) */
3205 if (!skb ||
3206 (!(bd_status & (R_F | R_L))) ||
3207 (bd_status & R_ERRORS_FATAL)) {
3208 if (netif_msg_rx_err(ugeth))
3209 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3210 __func__, __LINE__, (u32) skb);
3211 if (skb)
3212 dev_kfree_skb_any(skb);
3213
3214 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3215 dev->stats.rx_dropped++;
3216 } else {
3217 dev->stats.rx_packets++;
3218 howmany++;
3219
3220 /* Prep the skb for the packet */
3221 skb_put(skb, length);
3222
3223 /* Tell the skb what kind of packet this is */
3224 skb->protocol = eth_type_trans(skb, ugeth->ndev);
3225
3226 dev->stats.rx_bytes += length;
3227 /* Send the packet up the stack */
3228 netif_receive_skb(skb);
3229 }
3230
3231 skb = get_new_skb(ugeth, bd);
3232 if (!skb) {
3233 if (netif_msg_rx_err(ugeth))
3234 ugeth_warn("%s: No Rx Data Buffer", __func__);
3235 dev->stats.rx_dropped++;
3236 break;
3237 }
3238
3239 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3240
3241 /* update to point at the next skb */
3242 ugeth->skb_currx[rxQ] =
3243 (ugeth->skb_currx[rxQ] +
3244 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3245
3246 if (bd_status & R_W)
3247 bd = ugeth->p_rx_bd_ring[rxQ];
3248 else
3249 bd += sizeof(struct qe_bd);
3250
3251 bd_status = in_be32((u32 __iomem *)bd);
3252 }
3253
3254 ugeth->rxBd[rxQ] = bd;
3255 return howmany;
3256 }
3257
3258 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3259 {
3260 /* Start from the next BD that should be filled */
3261 struct ucc_geth_private *ugeth = netdev_priv(dev);
3262 u8 __iomem *bd; /* BD pointer */
3263 u32 bd_status;
3264
3265 bd = ugeth->confBd[txQ];
3266 bd_status = in_be32((u32 __iomem *)bd);
3267
3268 /* Normal processing. */
3269 while ((bd_status & T_R) == 0) {
3270 /* BD contains already transmitted buffer. */
3271 /* Handle the transmitted buffer and release */
3272 /* the BD to be used with the current frame */
3273
3274 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3275 break;
3276
3277 dev->stats.tx_packets++;
3278
3279 /* Free the sk buffer associated with this TxBD */
3280 dev_kfree_skb(ugeth->
3281 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3282 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3283 ugeth->skb_dirtytx[txQ] =
3284 (ugeth->skb_dirtytx[txQ] +
3285 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3286
3287 /* We freed a buffer, so now we can restart transmission */
3288 if (netif_queue_stopped(dev))
3289 netif_wake_queue(dev);
3290
3291 /* Advance the confirmation BD pointer */
3292 if (!(bd_status & T_W))
3293 bd += sizeof(struct qe_bd);
3294 else
3295 bd = ugeth->p_tx_bd_ring[txQ];
3296 bd_status = in_be32((u32 __iomem *)bd);
3297 }
3298 ugeth->confBd[txQ] = bd;
3299 return 0;
3300 }
3301
3302 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3303 {
3304 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3305 struct ucc_geth_info *ug_info;
3306 int howmany, i;
3307
3308 ug_info = ugeth->ug_info;
3309
3310 howmany = 0;
3311 for (i = 0; i < ug_info->numQueuesRx; i++)
3312 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3313
3314 /* Tx event processing */
3315 spin_lock(&ugeth->lock);
3316 for (i = 0; i < ug_info->numQueuesTx; i++)
3317 ucc_geth_tx(ugeth->ndev, i);
3318 spin_unlock(&ugeth->lock);
3319
3320 if (howmany < budget) {
3321 napi_complete(napi);
3322 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3323 }
3324
3325 return howmany;
3326 }
3327
3328 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3329 {
3330 struct net_device *dev = info;
3331 struct ucc_geth_private *ugeth = netdev_priv(dev);
3332 struct ucc_fast_private *uccf;
3333 struct ucc_geth_info *ug_info;
3334 register u32 ucce;
3335 register u32 uccm;
3336
3337 ugeth_vdbg("%s: IN", __func__);
3338
3339 uccf = ugeth->uccf;
3340 ug_info = ugeth->ug_info;
3341
3342 /* read and clear events */
3343 ucce = (u32) in_be32(uccf->p_ucce);
3344 uccm = (u32) in_be32(uccf->p_uccm);
3345 ucce &= uccm;
3346 out_be32(uccf->p_ucce, ucce);
3347
3348 /* check for receive events that require processing */
3349 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3350 if (napi_schedule_prep(&ugeth->napi)) {
3351 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3352 out_be32(uccf->p_uccm, uccm);
3353 __napi_schedule(&ugeth->napi);
3354 }
3355 }
3356
3357 /* Errors and other events */
3358 if (ucce & UCCE_OTHER) {
3359 if (ucce & UCC_GETH_UCCE_BSY)
3360 dev->stats.rx_errors++;
3361 if (ucce & UCC_GETH_UCCE_TXE)
3362 dev->stats.tx_errors++;
3363 }
3364
3365 return IRQ_HANDLED;
3366 }
3367
3368 #ifdef CONFIG_NET_POLL_CONTROLLER
3369 /*
3370 * Polling 'interrupt' - used by things like netconsole to send skbs
3371 * without having to re-enable interrupts. It's not called while
3372 * the interrupt routine is executing.
3373 */
3374 static void ucc_netpoll(struct net_device *dev)
3375 {
3376 struct ucc_geth_private *ugeth = netdev_priv(dev);
3377 int irq = ugeth->ug_info->uf_info.irq;
3378
3379 disable_irq(irq);
3380 ucc_geth_irq_handler(irq, dev);
3381 enable_irq(irq);
3382 }
3383 #endif /* CONFIG_NET_POLL_CONTROLLER */
3384
3385 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3386 {
3387 struct ucc_geth_private *ugeth = netdev_priv(dev);
3388 struct sockaddr *addr = p;
3389
3390 if (!is_valid_ether_addr(addr->sa_data))
3391 return -EADDRNOTAVAIL;
3392
3393 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3394
3395 /*
3396 * If device is not running, we will set mac addr register
3397 * when opening the device.
3398 */
3399 if (!netif_running(dev))
3400 return 0;
3401
3402 spin_lock_irq(&ugeth->lock);
3403 init_mac_station_addr_regs(dev->dev_addr[0],
3404 dev->dev_addr[1],
3405 dev->dev_addr[2],
3406 dev->dev_addr[3],
3407 dev->dev_addr[4],
3408 dev->dev_addr[5],
3409 &ugeth->ug_regs->macstnaddr1,
3410 &ugeth->ug_regs->macstnaddr2);
3411 spin_unlock_irq(&ugeth->lock);
3412
3413 return 0;
3414 }
3415
3416 /* Called when something needs to use the ethernet device */
3417 /* Returns 0 for success. */
3418 static int ucc_geth_open(struct net_device *dev)
3419 {
3420 struct ucc_geth_private *ugeth = netdev_priv(dev);
3421 int err;
3422
3423 ugeth_vdbg("%s: IN", __func__);
3424
3425 /* Test station address */
3426 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3427 if (netif_msg_ifup(ugeth))
3428 ugeth_err("%s: Multicast address used for station address"
3429 " - is this what you wanted?", __func__);
3430 return -EINVAL;
3431 }
3432
3433 err = init_phy(dev);
3434 if (err) {
3435 if (netif_msg_ifup(ugeth))
3436 ugeth_err("%s: Cannot initialize PHY, aborting.",
3437 dev->name);
3438 return err;
3439 }
3440
3441 err = ucc_struct_init(ugeth);
3442 if (err) {
3443 if (netif_msg_ifup(ugeth))
3444 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3445 goto out_err_stop;
3446 }
3447
3448 napi_enable(&ugeth->napi);
3449
3450 err = ucc_geth_startup(ugeth);
3451 if (err) {
3452 if (netif_msg_ifup(ugeth))
3453 ugeth_err("%s: Cannot configure net device, aborting.",
3454 dev->name);
3455 goto out_err;
3456 }
3457
3458 err = adjust_enet_interface(ugeth);
3459 if (err) {
3460 if (netif_msg_ifup(ugeth))
3461 ugeth_err("%s: Cannot configure net device, aborting.",
3462 dev->name);
3463 goto out_err;
3464 }
3465
3466 /* Set MACSTNADDR1, MACSTNADDR2 */
3467 /* For more details see the hardware spec. */
3468 init_mac_station_addr_regs(dev->dev_addr[0],
3469 dev->dev_addr[1],
3470 dev->dev_addr[2],
3471 dev->dev_addr[3],
3472 dev->dev_addr[4],
3473 dev->dev_addr[5],
3474 &ugeth->ug_regs->macstnaddr1,
3475 &ugeth->ug_regs->macstnaddr2);
3476
3477 phy_start(ugeth->phydev);
3478
3479 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3480 if (err) {
3481 if (netif_msg_ifup(ugeth))
3482 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3483 goto out_err;
3484 }
3485
3486 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3487 0, "UCC Geth", dev);
3488 if (err) {
3489 if (netif_msg_ifup(ugeth))
3490 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3491 dev->name);
3492 goto out_err;
3493 }
3494
3495 netif_start_queue(dev);
3496
3497 return err;
3498
3499 out_err:
3500 napi_disable(&ugeth->napi);
3501 out_err_stop:
3502 ucc_geth_stop(ugeth);
3503 return err;
3504 }
3505
3506 /* Stops the kernel queue, and halts the controller */
3507 static int ucc_geth_close(struct net_device *dev)
3508 {
3509 struct ucc_geth_private *ugeth = netdev_priv(dev);
3510
3511 ugeth_vdbg("%s: IN", __func__);
3512
3513 napi_disable(&ugeth->napi);
3514
3515 ucc_geth_stop(ugeth);
3516
3517 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3518
3519 netif_stop_queue(dev);
3520
3521 return 0;
3522 }
3523
3524 /* Reopen device. This will reset the MAC and PHY. */
3525 static void ucc_geth_timeout_work(struct work_struct *work)
3526 {
3527 struct ucc_geth_private *ugeth;
3528 struct net_device *dev;
3529
3530 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3531 dev = ugeth->ndev;
3532
3533 ugeth_vdbg("%s: IN", __func__);
3534
3535 dev->stats.tx_errors++;
3536
3537 ugeth_dump_regs(ugeth);
3538
3539 if (dev->flags & IFF_UP) {
3540 /*
3541 * Must reset MAC *and* PHY. This is done by reopening
3542 * the device.
3543 */
3544 ucc_geth_close(dev);
3545 ucc_geth_open(dev);
3546 }
3547
3548 netif_tx_schedule_all(dev);
3549 }
3550
3551 /*
3552 * ucc_geth_timeout gets called when a packet has not been
3553 * transmitted after a set amount of time.
3554 */
3555 static void ucc_geth_timeout(struct net_device *dev)
3556 {
3557 struct ucc_geth_private *ugeth = netdev_priv(dev);
3558
3559 netif_carrier_off(dev);
3560 schedule_work(&ugeth->timeout_work);
3561 }
3562
3563 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3564 {
3565 if (strcasecmp(phy_connection_type, "mii") == 0)
3566 return PHY_INTERFACE_MODE_MII;
3567 if (strcasecmp(phy_connection_type, "gmii") == 0)
3568 return PHY_INTERFACE_MODE_GMII;
3569 if (strcasecmp(phy_connection_type, "tbi") == 0)
3570 return PHY_INTERFACE_MODE_TBI;
3571 if (strcasecmp(phy_connection_type, "rmii") == 0)
3572 return PHY_INTERFACE_MODE_RMII;
3573 if (strcasecmp(phy_connection_type, "rgmii") == 0)
3574 return PHY_INTERFACE_MODE_RGMII;
3575 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3576 return PHY_INTERFACE_MODE_RGMII_ID;
3577 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3578 return PHY_INTERFACE_MODE_RGMII_TXID;
3579 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3580 return PHY_INTERFACE_MODE_RGMII_RXID;
3581 if (strcasecmp(phy_connection_type, "rtbi") == 0)
3582 return PHY_INTERFACE_MODE_RTBI;
3583 if (strcasecmp(phy_connection_type, "sgmii") == 0)
3584 return PHY_INTERFACE_MODE_SGMII;
3585
3586 return PHY_INTERFACE_MODE_MII;
3587 }
3588
3589 static const struct net_device_ops ucc_geth_netdev_ops = {
3590 .ndo_open = ucc_geth_open,
3591 .ndo_stop = ucc_geth_close,
3592 .ndo_start_xmit = ucc_geth_start_xmit,
3593 .ndo_validate_addr = eth_validate_addr,
3594 .ndo_set_mac_address = ucc_geth_set_mac_addr,
3595 .ndo_change_mtu = eth_change_mtu,
3596 .ndo_set_multicast_list = ucc_geth_set_multi,
3597 .ndo_tx_timeout = ucc_geth_timeout,
3598 #ifdef CONFIG_NET_POLL_CONTROLLER
3599 .ndo_poll_controller = ucc_netpoll,
3600 #endif
3601 };
3602
3603 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3604 {
3605 struct device *device = &ofdev->dev;
3606 struct device_node *np = ofdev->node;
3607 struct net_device *dev = NULL;
3608 struct ucc_geth_private *ugeth = NULL;
3609 struct ucc_geth_info *ug_info;
3610 struct resource res;
3611 struct device_node *phy;
3612 int err, ucc_num, max_speed = 0;
3613 const u32 *fixed_link;
3614 const unsigned int *prop;
3615 const char *sprop;
3616 const void *mac_addr;
3617 phy_interface_t phy_interface;
3618 static const int enet_to_speed[] = {
3619 SPEED_10, SPEED_10, SPEED_10,
3620 SPEED_100, SPEED_100, SPEED_100,
3621 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3622 };
3623 static const phy_interface_t enet_to_phy_interface[] = {
3624 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3625 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3626 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3627 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3628 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3629 PHY_INTERFACE_MODE_SGMII,
3630 };
3631
3632 ugeth_vdbg("%s: IN", __func__);
3633
3634 prop = of_get_property(np, "cell-index", NULL);
3635 if (!prop) {
3636 prop = of_get_property(np, "device-id", NULL);
3637 if (!prop)
3638 return -ENODEV;
3639 }
3640
3641 ucc_num = *prop - 1;
3642 if ((ucc_num < 0) || (ucc_num > 7))
3643 return -ENODEV;
3644
3645 ug_info = &ugeth_info[ucc_num];
3646 if (ug_info == NULL) {
3647 if (netif_msg_probe(&debug))
3648 ugeth_err("%s: [%d] Missing additional data!",
3649 __func__, ucc_num);
3650 return -ENODEV;
3651 }
3652
3653 ug_info->uf_info.ucc_num = ucc_num;
3654
3655 sprop = of_get_property(np, "rx-clock-name", NULL);
3656 if (sprop) {
3657 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3658 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3659 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3660 printk(KERN_ERR
3661 "ucc_geth: invalid rx-clock-name property\n");
3662 return -EINVAL;
3663 }
3664 } else {
3665 prop = of_get_property(np, "rx-clock", NULL);
3666 if (!prop) {
3667 /* If both rx-clock-name and rx-clock are missing,
3668 we want to tell people to use rx-clock-name. */
3669 printk(KERN_ERR
3670 "ucc_geth: missing rx-clock-name property\n");
3671 return -EINVAL;
3672 }
3673 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3674 printk(KERN_ERR
3675 "ucc_geth: invalid rx-clock propperty\n");
3676 return -EINVAL;
3677 }
3678 ug_info->uf_info.rx_clock = *prop;
3679 }
3680
3681 sprop = of_get_property(np, "tx-clock-name", NULL);
3682 if (sprop) {
3683 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3684 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3685 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3686 printk(KERN_ERR
3687 "ucc_geth: invalid tx-clock-name property\n");
3688 return -EINVAL;
3689 }
3690 } else {
3691 prop = of_get_property(np, "tx-clock", NULL);
3692 if (!prop) {
3693 printk(KERN_ERR
3694 "ucc_geth: mising tx-clock-name property\n");
3695 return -EINVAL;
3696 }
3697 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3698 printk(KERN_ERR
3699 "ucc_geth: invalid tx-clock property\n");
3700 return -EINVAL;
3701 }
3702 ug_info->uf_info.tx_clock = *prop;
3703 }
3704
3705 err = of_address_to_resource(np, 0, &res);
3706 if (err)
3707 return -EINVAL;
3708
3709 ug_info->uf_info.regs = res.start;
3710 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3711 fixed_link = of_get_property(np, "fixed-link", NULL);
3712 if (fixed_link) {
3713 phy = NULL;
3714 } else {
3715 phy = of_parse_phandle(np, "phy-handle", 0);
3716 if (phy == NULL)
3717 return -ENODEV;
3718 }
3719 ug_info->phy_node = phy;
3720
3721 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3722 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3723
3724 /* get the phy interface type, or default to MII */
3725 prop = of_get_property(np, "phy-connection-type", NULL);
3726 if (!prop) {
3727 /* handle interface property present in old trees */
3728 prop = of_get_property(phy, "interface", NULL);
3729 if (prop != NULL) {
3730 phy_interface = enet_to_phy_interface[*prop];
3731 max_speed = enet_to_speed[*prop];
3732 } else
3733 phy_interface = PHY_INTERFACE_MODE_MII;
3734 } else {
3735 phy_interface = to_phy_interface((const char *)prop);
3736 }
3737
3738 /* get speed, or derive from PHY interface */
3739 if (max_speed == 0)
3740 switch (phy_interface) {
3741 case PHY_INTERFACE_MODE_GMII:
3742 case PHY_INTERFACE_MODE_RGMII:
3743 case PHY_INTERFACE_MODE_RGMII_ID:
3744 case PHY_INTERFACE_MODE_RGMII_RXID:
3745 case PHY_INTERFACE_MODE_RGMII_TXID:
3746 case PHY_INTERFACE_MODE_TBI:
3747 case PHY_INTERFACE_MODE_RTBI:
3748 case PHY_INTERFACE_MODE_SGMII:
3749 max_speed = SPEED_1000;
3750 break;
3751 default:
3752 max_speed = SPEED_100;
3753 break;
3754 }
3755
3756 if (max_speed == SPEED_1000) {
3757 /* configure muram FIFOs for gigabit operation */
3758 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3759 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3760 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3761 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3762 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3763 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3764 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3765
3766 /* If QE's snum number is 46 which means we need to support
3767 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3768 * more Threads to Rx.
3769 */
3770 if (qe_get_num_of_snums() == 46)
3771 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3772 else
3773 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3774 }
3775
3776 if (netif_msg_probe(&debug))
3777 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3778 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3779 ug_info->uf_info.irq);
3780
3781 /* Create an ethernet device instance */
3782 dev = alloc_etherdev(sizeof(*ugeth));
3783
3784 if (dev == NULL)
3785 return -ENOMEM;
3786
3787 ugeth = netdev_priv(dev);
3788 spin_lock_init(&ugeth->lock);
3789
3790 /* Create CQs for hash tables */
3791 INIT_LIST_HEAD(&ugeth->group_hash_q);
3792 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3793
3794 dev_set_drvdata(device, dev);
3795
3796 /* Set the dev->base_addr to the gfar reg region */
3797 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3798
3799 SET_NETDEV_DEV(dev, device);
3800
3801 /* Fill in the dev structure */
3802 uec_set_ethtool_ops(dev);
3803 dev->netdev_ops = &ucc_geth_netdev_ops;
3804 dev->watchdog_timeo = TX_TIMEOUT;
3805 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3806 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3807 dev->mtu = 1500;
3808
3809 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3810 ugeth->phy_interface = phy_interface;
3811 ugeth->max_speed = max_speed;
3812
3813 err = register_netdev(dev);
3814 if (err) {
3815 if (netif_msg_probe(ugeth))
3816 ugeth_err("%s: Cannot register net device, aborting.",
3817 dev->name);
3818 free_netdev(dev);
3819 return err;
3820 }
3821
3822 mac_addr = of_get_mac_address(np);
3823 if (mac_addr)
3824 memcpy(dev->dev_addr, mac_addr, 6);
3825
3826 ugeth->ug_info = ug_info;
3827 ugeth->dev = device;
3828 ugeth->ndev = dev;
3829 ugeth->node = np;
3830
3831 return 0;
3832 }
3833
3834 static int ucc_geth_remove(struct of_device* ofdev)
3835 {
3836 struct device *device = &ofdev->dev;
3837 struct net_device *dev = dev_get_drvdata(device);
3838 struct ucc_geth_private *ugeth = netdev_priv(dev);
3839
3840 unregister_netdev(dev);
3841 free_netdev(dev);
3842 ucc_geth_memclean(ugeth);
3843 dev_set_drvdata(device, NULL);
3844
3845 return 0;
3846 }
3847
3848 static struct of_device_id ucc_geth_match[] = {
3849 {
3850 .type = "network",
3851 .compatible = "ucc_geth",
3852 },
3853 {},
3854 };
3855
3856 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3857
3858 static struct of_platform_driver ucc_geth_driver = {
3859 .name = DRV_NAME,
3860 .match_table = ucc_geth_match,
3861 .probe = ucc_geth_probe,
3862 .remove = ucc_geth_remove,
3863 };
3864
3865 static int __init ucc_geth_init(void)
3866 {
3867 int i, ret;
3868
3869 if (netif_msg_drv(&debug))
3870 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3871 for (i = 0; i < 8; i++)
3872 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3873 sizeof(ugeth_primary_info));
3874
3875 ret = of_register_platform_driver(&ucc_geth_driver);
3876
3877 return ret;
3878 }
3879
3880 static void __exit ucc_geth_exit(void)
3881 {
3882 of_unregister_platform_driver(&ucc_geth_driver);
3883 }
3884
3885 module_init(ucc_geth_init);
3886 module_exit(ucc_geth_exit);
3887
3888 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3889 MODULE_DESCRIPTION(DRV_DESC);
3890 MODULE_VERSION(DRV_VERSION);
3891 MODULE_LICENSE("GPL");
Ubuntu Artful kernel mirror