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net: asix: see 802.3 spec for phy reset
[mirror_ubuntu-zesty-kernel.git] / drivers / net / usb / asix_devices.c
1 /*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "asix.h"
23
24 #define PHY_MODE_MARVELL 0x0000
25 #define MII_MARVELL_LED_CTRL 0x0018
26 #define MII_MARVELL_STATUS 0x001b
27 #define MII_MARVELL_CTRL 0x0014
28
29 #define MARVELL_LED_MANUAL 0x0019
30
31 #define MARVELL_STATUS_HWCFG 0x0004
32
33 #define MARVELL_CTRL_TXDELAY 0x0002
34 #define MARVELL_CTRL_RXDELAY 0x0080
35
36 #define PHY_MODE_RTL8211CL 0x000C
37
38 #define AX88772A_PHY14H 0x14
39 #define AX88772A_PHY14H_DEFAULT 0x442C
40
41 #define AX88772A_PHY15H 0x15
42 #define AX88772A_PHY15H_DEFAULT 0x03C8
43
44 #define AX88772A_PHY16H 0x16
45 #define AX88772A_PHY16H_DEFAULT 0x4044
46
47 struct ax88172_int_data {
48 __le16 res1;
49 u8 link;
50 __le16 res2;
51 u8 status;
52 __le16 res3;
53 } __packed;
54
55 static void asix_status(struct usbnet *dev, struct urb *urb)
56 {
57 struct ax88172_int_data *event;
58 int link;
59
60 if (urb->actual_length < 8)
61 return;
62
63 event = urb->transfer_buffer;
64 link = event->link & 0x01;
65 if (netif_carrier_ok(dev->net) != link) {
66 usbnet_link_change(dev, link, 1);
67 netdev_dbg(dev->net, "Link Status is: %d\n", link);
68 }
69 }
70
71 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
72 {
73 if (is_valid_ether_addr(addr)) {
74 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
75 } else {
76 netdev_info(dev->net, "invalid hw address, using random\n");
77 eth_hw_addr_random(dev->net);
78 }
79 }
80
81 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
82 static u32 asix_get_phyid(struct usbnet *dev)
83 {
84 int phy_reg;
85 u32 phy_id;
86 int i;
87
88 /* Poll for the rare case the FW or phy isn't ready yet. */
89 for (i = 0; i < 100; i++) {
90 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
91 if (phy_reg < 0)
92 return 0;
93 if (phy_reg != 0 && phy_reg != 0xFFFF)
94 break;
95 mdelay(1);
96 }
97
98 if (phy_reg <= 0 || phy_reg == 0xFFFF)
99 return 0;
100
101 phy_id = (phy_reg & 0xffff) << 16;
102
103 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
104 if (phy_reg < 0)
105 return 0;
106
107 phy_id |= (phy_reg & 0xffff);
108
109 return phy_id;
110 }
111
112 static u32 asix_get_link(struct net_device *net)
113 {
114 struct usbnet *dev = netdev_priv(net);
115
116 return mii_link_ok(&dev->mii);
117 }
118
119 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
120 {
121 struct usbnet *dev = netdev_priv(net);
122
123 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
124 }
125
126 /* We need to override some ethtool_ops so we require our
127 own structure so we don't interfere with other usbnet
128 devices that may be connected at the same time. */
129 static const struct ethtool_ops ax88172_ethtool_ops = {
130 .get_drvinfo = asix_get_drvinfo,
131 .get_link = asix_get_link,
132 .get_msglevel = usbnet_get_msglevel,
133 .set_msglevel = usbnet_set_msglevel,
134 .get_wol = asix_get_wol,
135 .set_wol = asix_set_wol,
136 .get_eeprom_len = asix_get_eeprom_len,
137 .get_eeprom = asix_get_eeprom,
138 .set_eeprom = asix_set_eeprom,
139 .get_settings = usbnet_get_settings,
140 .set_settings = usbnet_set_settings,
141 .nway_reset = usbnet_nway_reset,
142 };
143
144 static void ax88172_set_multicast(struct net_device *net)
145 {
146 struct usbnet *dev = netdev_priv(net);
147 struct asix_data *data = (struct asix_data *)&dev->data;
148 u8 rx_ctl = 0x8c;
149
150 if (net->flags & IFF_PROMISC) {
151 rx_ctl |= 0x01;
152 } else if (net->flags & IFF_ALLMULTI ||
153 netdev_mc_count(net) > AX_MAX_MCAST) {
154 rx_ctl |= 0x02;
155 } else if (netdev_mc_empty(net)) {
156 /* just broadcast and directed */
157 } else {
158 /* We use the 20 byte dev->data
159 * for our 8 byte filter buffer
160 * to avoid allocating memory that
161 * is tricky to free later */
162 struct netdev_hw_addr *ha;
163 u32 crc_bits;
164
165 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
166
167 /* Build the multicast hash filter. */
168 netdev_for_each_mc_addr(ha, net) {
169 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
170 data->multi_filter[crc_bits >> 3] |=
171 1 << (crc_bits & 7);
172 }
173
174 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
175 AX_MCAST_FILTER_SIZE, data->multi_filter);
176
177 rx_ctl |= 0x10;
178 }
179
180 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
181 }
182
183 static int ax88172_link_reset(struct usbnet *dev)
184 {
185 u8 mode;
186 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
187
188 mii_check_media(&dev->mii, 1, 1);
189 mii_ethtool_gset(&dev->mii, &ecmd);
190 mode = AX88172_MEDIUM_DEFAULT;
191
192 if (ecmd.duplex != DUPLEX_FULL)
193 mode |= ~AX88172_MEDIUM_FD;
194
195 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
196 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
197
198 asix_write_medium_mode(dev, mode, 0);
199
200 return 0;
201 }
202
203 static const struct net_device_ops ax88172_netdev_ops = {
204 .ndo_open = usbnet_open,
205 .ndo_stop = usbnet_stop,
206 .ndo_start_xmit = usbnet_start_xmit,
207 .ndo_tx_timeout = usbnet_tx_timeout,
208 .ndo_change_mtu = usbnet_change_mtu,
209 .ndo_set_mac_address = eth_mac_addr,
210 .ndo_validate_addr = eth_validate_addr,
211 .ndo_do_ioctl = asix_ioctl,
212 .ndo_set_rx_mode = ax88172_set_multicast,
213 };
214
215 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
216 {
217 unsigned int timeout = 5000;
218
219 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
220
221 /* give phy_id a chance to process reset */
222 udelay(500);
223
224 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
225 while (timeout--) {
226 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
227 & BMCR_RESET)
228 udelay(100);
229 else
230 return;
231 }
232
233 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
234 dev->mii.phy_id);
235 }
236
237 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
238 {
239 int ret = 0;
240 u8 buf[ETH_ALEN];
241 int i;
242 unsigned long gpio_bits = dev->driver_info->data;
243
244 usbnet_get_endpoints(dev,intf);
245
246 /* Toggle the GPIOs in a manufacturer/model specific way */
247 for (i = 2; i >= 0; i--) {
248 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
249 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
250 if (ret < 0)
251 goto out;
252 msleep(5);
253 }
254
255 ret = asix_write_rx_ctl(dev, 0x80, 0);
256 if (ret < 0)
257 goto out;
258
259 /* Get the MAC address */
260 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
261 0, 0, ETH_ALEN, buf, 0);
262 if (ret < 0) {
263 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
264 ret);
265 goto out;
266 }
267
268 asix_set_netdev_dev_addr(dev, buf);
269
270 /* Initialize MII structure */
271 dev->mii.dev = dev->net;
272 dev->mii.mdio_read = asix_mdio_read;
273 dev->mii.mdio_write = asix_mdio_write;
274 dev->mii.phy_id_mask = 0x3f;
275 dev->mii.reg_num_mask = 0x1f;
276 dev->mii.phy_id = asix_get_phy_addr(dev);
277
278 dev->net->netdev_ops = &ax88172_netdev_ops;
279 dev->net->ethtool_ops = &ax88172_ethtool_ops;
280 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
281 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
282
283 asix_phy_reset(dev, BMCR_RESET);
284 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
285 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
286 mii_nway_restart(&dev->mii);
287
288 return 0;
289
290 out:
291 return ret;
292 }
293
294 static const struct ethtool_ops ax88772_ethtool_ops = {
295 .get_drvinfo = asix_get_drvinfo,
296 .get_link = asix_get_link,
297 .get_msglevel = usbnet_get_msglevel,
298 .set_msglevel = usbnet_set_msglevel,
299 .get_wol = asix_get_wol,
300 .set_wol = asix_set_wol,
301 .get_eeprom_len = asix_get_eeprom_len,
302 .get_eeprom = asix_get_eeprom,
303 .set_eeprom = asix_set_eeprom,
304 .get_settings = usbnet_get_settings,
305 .set_settings = usbnet_set_settings,
306 .nway_reset = usbnet_nway_reset,
307 };
308
309 static int ax88772_link_reset(struct usbnet *dev)
310 {
311 u16 mode;
312 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
313
314 mii_check_media(&dev->mii, 1, 1);
315 mii_ethtool_gset(&dev->mii, &ecmd);
316 mode = AX88772_MEDIUM_DEFAULT;
317
318 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
319 mode &= ~AX_MEDIUM_PS;
320
321 if (ecmd.duplex != DUPLEX_FULL)
322 mode &= ~AX_MEDIUM_FD;
323
324 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
325 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
326
327 asix_write_medium_mode(dev, mode, 0);
328
329 return 0;
330 }
331
332 static int ax88772_reset(struct usbnet *dev)
333 {
334 struct asix_data *data = (struct asix_data *)&dev->data;
335 int ret;
336
337 /* Rewrite MAC address */
338 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
339 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
340 ETH_ALEN, data->mac_addr, 0);
341 if (ret < 0)
342 goto out;
343
344 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
345 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
346 if (ret < 0)
347 goto out;
348
349 asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
350 if (ret < 0)
351 goto out;
352
353 return 0;
354
355 out:
356 return ret;
357 }
358
359 static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
360 {
361 struct asix_data *data = (struct asix_data *)&dev->data;
362 int ret, embd_phy;
363 u16 rx_ctl;
364
365 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
366 AX_GPIO_GPO2EN, 5, in_pm);
367 if (ret < 0)
368 goto out;
369
370 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
371
372 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy,
373 0, 0, NULL, in_pm);
374 if (ret < 0) {
375 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
376 goto out;
377 }
378
379 if (embd_phy) {
380 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
381 if (ret < 0)
382 goto out;
383
384 usleep_range(10000, 11000);
385
386 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
387 if (ret < 0)
388 goto out;
389
390 msleep(60);
391
392 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
393 in_pm);
394 if (ret < 0)
395 goto out;
396 } else {
397 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
398 in_pm);
399 if (ret < 0)
400 goto out;
401 }
402
403 msleep(150);
404
405 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
406 MII_PHYSID1))){
407 ret = -EIO;
408 goto out;
409 }
410
411 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
412 if (ret < 0)
413 goto out;
414
415 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
416 if (ret < 0)
417 goto out;
418
419 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
420 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
421 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
422 if (ret < 0) {
423 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
424 goto out;
425 }
426
427 /* Rewrite MAC address */
428 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
429 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
430 ETH_ALEN, data->mac_addr, in_pm);
431 if (ret < 0)
432 goto out;
433
434 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
435 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
436 if (ret < 0)
437 goto out;
438
439 rx_ctl = asix_read_rx_ctl(dev, in_pm);
440 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
441 rx_ctl);
442
443 rx_ctl = asix_read_medium_status(dev, in_pm);
444 netdev_dbg(dev->net,
445 "Medium Status is 0x%04x after all initializations\n",
446 rx_ctl);
447
448 return 0;
449
450 out:
451 return ret;
452 }
453
454 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
455 {
456 struct asix_data *data = (struct asix_data *)&dev->data;
457 int ret, embd_phy;
458 u16 rx_ctl, phy14h, phy15h, phy16h;
459 u8 chipcode = 0;
460
461 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
462 if (ret < 0)
463 goto out;
464
465 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
466
467 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy |
468 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
469 if (ret < 0) {
470 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
471 goto out;
472 }
473 usleep_range(10000, 11000);
474
475 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
476 if (ret < 0)
477 goto out;
478
479 usleep_range(10000, 11000);
480
481 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
482 if (ret < 0)
483 goto out;
484
485 msleep(160);
486
487 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
488 if (ret < 0)
489 goto out;
490
491 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
492 if (ret < 0)
493 goto out;
494
495 msleep(200);
496
497 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
498 MII_PHYSID1))) {
499 ret = -1;
500 goto out;
501 }
502
503 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0,
504 0, 1, &chipcode, in_pm);
505 if (ret < 0)
506 goto out;
507
508 if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) {
509 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
510 0, NULL, in_pm);
511 if (ret < 0) {
512 netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
513 ret);
514 goto out;
515 }
516 } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) {
517 /* Check if the PHY registers have default settings */
518 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
519 AX88772A_PHY14H);
520 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
521 AX88772A_PHY15H);
522 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
523 AX88772A_PHY16H);
524
525 netdev_dbg(dev->net,
526 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
527 phy14h, phy15h, phy16h);
528
529 /* Restore PHY registers default setting if not */
530 if (phy14h != AX88772A_PHY14H_DEFAULT)
531 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
532 AX88772A_PHY14H,
533 AX88772A_PHY14H_DEFAULT);
534 if (phy15h != AX88772A_PHY15H_DEFAULT)
535 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
536 AX88772A_PHY15H,
537 AX88772A_PHY15H_DEFAULT);
538 if (phy16h != AX88772A_PHY16H_DEFAULT)
539 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
540 AX88772A_PHY16H,
541 AX88772A_PHY16H_DEFAULT);
542 }
543
544 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
545 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
546 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
547 if (ret < 0) {
548 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
549 goto out;
550 }
551
552 /* Rewrite MAC address */
553 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
554 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
555 data->mac_addr, in_pm);
556 if (ret < 0)
557 goto out;
558
559 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
560 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
561 if (ret < 0)
562 goto out;
563
564 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
565 if (ret < 0)
566 return ret;
567
568 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
569 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
570 if (ret < 0)
571 goto out;
572
573 rx_ctl = asix_read_rx_ctl(dev, in_pm);
574 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
575 rx_ctl);
576
577 rx_ctl = asix_read_medium_status(dev, in_pm);
578 netdev_dbg(dev->net,
579 "Medium Status is 0x%04x after all initializations\n",
580 rx_ctl);
581
582 return 0;
583
584 out:
585 return ret;
586 }
587
588 static const struct net_device_ops ax88772_netdev_ops = {
589 .ndo_open = usbnet_open,
590 .ndo_stop = usbnet_stop,
591 .ndo_start_xmit = usbnet_start_xmit,
592 .ndo_tx_timeout = usbnet_tx_timeout,
593 .ndo_change_mtu = usbnet_change_mtu,
594 .ndo_set_mac_address = asix_set_mac_address,
595 .ndo_validate_addr = eth_validate_addr,
596 .ndo_do_ioctl = asix_ioctl,
597 .ndo_set_rx_mode = asix_set_multicast,
598 };
599
600 static void ax88772_suspend(struct usbnet *dev)
601 {
602 struct asix_common_private *priv = dev->driver_priv;
603 u16 medium;
604
605 /* Stop MAC operation */
606 medium = asix_read_medium_status(dev, 0);
607 medium &= ~AX_MEDIUM_RE;
608 asix_write_medium_mode(dev, medium, 0);
609
610 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
611 asix_read_medium_status(dev, 0));
612
613 /* Preserve BMCR for restoring */
614 priv->presvd_phy_bmcr =
615 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);
616
617 /* Preserve ANAR for restoring */
618 priv->presvd_phy_advertise =
619 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);
620 }
621
622 static int asix_suspend(struct usb_interface *intf, pm_message_t message)
623 {
624 struct usbnet *dev = usb_get_intfdata(intf);
625 struct asix_common_private *priv = dev->driver_priv;
626
627 if (priv->suspend)
628 priv->suspend(dev);
629
630 return usbnet_suspend(intf, message);
631 }
632
633 static void ax88772_restore_phy(struct usbnet *dev)
634 {
635 struct asix_common_private *priv = dev->driver_priv;
636
637 if (priv->presvd_phy_advertise) {
638 /* Restore Advertisement control reg */
639 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,
640 priv->presvd_phy_advertise);
641
642 /* Restore BMCR */
643 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,
644 priv->presvd_phy_bmcr);
645
646 mii_nway_restart(&dev->mii);
647 priv->presvd_phy_advertise = 0;
648 priv->presvd_phy_bmcr = 0;
649 }
650 }
651
652 static void ax88772_resume(struct usbnet *dev)
653 {
654 int i;
655
656 for (i = 0; i < 3; i++)
657 if (!ax88772_hw_reset(dev, 1))
658 break;
659 ax88772_restore_phy(dev);
660 }
661
662 static void ax88772a_resume(struct usbnet *dev)
663 {
664 int i;
665
666 for (i = 0; i < 3; i++) {
667 if (!ax88772a_hw_reset(dev, 1))
668 break;
669 }
670
671 ax88772_restore_phy(dev);
672 }
673
674 static int asix_resume(struct usb_interface *intf)
675 {
676 struct usbnet *dev = usb_get_intfdata(intf);
677 struct asix_common_private *priv = dev->driver_priv;
678
679 if (priv->resume)
680 priv->resume(dev);
681
682 return usbnet_resume(intf);
683 }
684
685 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
686 {
687 int ret, i;
688 u8 buf[ETH_ALEN], chipcode = 0;
689 u32 phyid;
690 struct asix_common_private *priv;
691
692 usbnet_get_endpoints(dev,intf);
693
694 /* Get the MAC address */
695 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
696 for (i = 0; i < (ETH_ALEN >> 1); i++) {
697 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x04 + i,
698 0, 2, buf + i * 2, 0);
699 if (ret < 0)
700 break;
701 }
702 } else {
703 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
704 0, 0, ETH_ALEN, buf, 0);
705 }
706
707 if (ret < 0) {
708 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
709 return ret;
710 }
711
712 asix_set_netdev_dev_addr(dev, buf);
713
714 /* Initialize MII structure */
715 dev->mii.dev = dev->net;
716 dev->mii.mdio_read = asix_mdio_read;
717 dev->mii.mdio_write = asix_mdio_write;
718 dev->mii.phy_id_mask = 0x1f;
719 dev->mii.reg_num_mask = 0x1f;
720 dev->mii.phy_id = asix_get_phy_addr(dev);
721
722 dev->net->netdev_ops = &ax88772_netdev_ops;
723 dev->net->ethtool_ops = &ax88772_ethtool_ops;
724 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
725 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
726
727 asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0);
728 chipcode &= AX_CHIPCODE_MASK;
729
730 (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) :
731 ax88772a_hw_reset(dev, 0);
732
733 /* Read PHYID register *AFTER* the PHY was reset properly */
734 phyid = asix_get_phyid(dev);
735 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
736
737 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
738 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
739 /* hard_mtu is still the default - the device does not support
740 jumbo eth frames */
741 dev->rx_urb_size = 2048;
742 }
743
744 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
745 if (!dev->driver_priv)
746 return -ENOMEM;
747
748 priv = dev->driver_priv;
749
750 priv->presvd_phy_bmcr = 0;
751 priv->presvd_phy_advertise = 0;
752 if (chipcode == AX_AX88772_CHIPCODE) {
753 priv->resume = ax88772_resume;
754 priv->suspend = ax88772_suspend;
755 } else {
756 priv->resume = ax88772a_resume;
757 priv->suspend = ax88772_suspend;
758 }
759
760 return 0;
761 }
762
763 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
764 {
765 kfree(dev->driver_priv);
766 }
767
768 static const struct ethtool_ops ax88178_ethtool_ops = {
769 .get_drvinfo = asix_get_drvinfo,
770 .get_link = asix_get_link,
771 .get_msglevel = usbnet_get_msglevel,
772 .set_msglevel = usbnet_set_msglevel,
773 .get_wol = asix_get_wol,
774 .set_wol = asix_set_wol,
775 .get_eeprom_len = asix_get_eeprom_len,
776 .get_eeprom = asix_get_eeprom,
777 .set_eeprom = asix_set_eeprom,
778 .get_settings = usbnet_get_settings,
779 .set_settings = usbnet_set_settings,
780 .nway_reset = usbnet_nway_reset,
781 };
782
783 static int marvell_phy_init(struct usbnet *dev)
784 {
785 struct asix_data *data = (struct asix_data *)&dev->data;
786 u16 reg;
787
788 netdev_dbg(dev->net, "marvell_phy_init()\n");
789
790 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
791 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
792
793 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
794 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
795
796 if (data->ledmode) {
797 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
798 MII_MARVELL_LED_CTRL);
799 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
800
801 reg &= 0xf8ff;
802 reg |= (1 + 0x0100);
803 asix_mdio_write(dev->net, dev->mii.phy_id,
804 MII_MARVELL_LED_CTRL, reg);
805
806 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
807 MII_MARVELL_LED_CTRL);
808 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
809 reg &= 0xfc0f;
810 }
811
812 return 0;
813 }
814
815 static int rtl8211cl_phy_init(struct usbnet *dev)
816 {
817 struct asix_data *data = (struct asix_data *)&dev->data;
818
819 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
820
821 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
822 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
823 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
824 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
825 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
826
827 if (data->ledmode == 12) {
828 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
829 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
830 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
831 }
832
833 return 0;
834 }
835
836 static int marvell_led_status(struct usbnet *dev, u16 speed)
837 {
838 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
839
840 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
841
842 /* Clear out the center LED bits - 0x03F0 */
843 reg &= 0xfc0f;
844
845 switch (speed) {
846 case SPEED_1000:
847 reg |= 0x03e0;
848 break;
849 case SPEED_100:
850 reg |= 0x03b0;
851 break;
852 default:
853 reg |= 0x02f0;
854 }
855
856 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
857 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
858
859 return 0;
860 }
861
862 static int ax88178_reset(struct usbnet *dev)
863 {
864 struct asix_data *data = (struct asix_data *)&dev->data;
865 int ret;
866 __le16 eeprom;
867 u8 status;
868 int gpio0 = 0;
869 u32 phyid;
870
871 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
872 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
873
874 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
875 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
876 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
877
878 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
879
880 if (eeprom == cpu_to_le16(0xffff)) {
881 data->phymode = PHY_MODE_MARVELL;
882 data->ledmode = 0;
883 gpio0 = 1;
884 } else {
885 data->phymode = le16_to_cpu(eeprom) & 0x7F;
886 data->ledmode = le16_to_cpu(eeprom) >> 8;
887 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
888 }
889 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
890
891 /* Power up external GigaPHY through AX88178 GPIO pin */
892 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
893 AX_GPIO_GPO1EN, 40, 0);
894 if ((le16_to_cpu(eeprom) >> 8) != 1) {
895 asix_write_gpio(dev, 0x003c, 30, 0);
896 asix_write_gpio(dev, 0x001c, 300, 0);
897 asix_write_gpio(dev, 0x003c, 30, 0);
898 } else {
899 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
900 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
901 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
902 }
903
904 /* Read PHYID register *AFTER* powering up PHY */
905 phyid = asix_get_phyid(dev);
906 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
907
908 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
909 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
910
911 asix_sw_reset(dev, 0, 0);
912 msleep(150);
913
914 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
915 msleep(150);
916
917 asix_write_rx_ctl(dev, 0, 0);
918
919 if (data->phymode == PHY_MODE_MARVELL) {
920 marvell_phy_init(dev);
921 msleep(60);
922 } else if (data->phymode == PHY_MODE_RTL8211CL)
923 rtl8211cl_phy_init(dev);
924
925 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
926 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
927 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
928 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
929 ADVERTISE_1000FULL);
930
931 mii_nway_restart(&dev->mii);
932
933 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
934 if (ret < 0)
935 return ret;
936
937 /* Rewrite MAC address */
938 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
939 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
940 data->mac_addr, 0);
941 if (ret < 0)
942 return ret;
943
944 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
945 if (ret < 0)
946 return ret;
947
948 return 0;
949 }
950
951 static int ax88178_link_reset(struct usbnet *dev)
952 {
953 u16 mode;
954 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
955 struct asix_data *data = (struct asix_data *)&dev->data;
956 u32 speed;
957
958 netdev_dbg(dev->net, "ax88178_link_reset()\n");
959
960 mii_check_media(&dev->mii, 1, 1);
961 mii_ethtool_gset(&dev->mii, &ecmd);
962 mode = AX88178_MEDIUM_DEFAULT;
963 speed = ethtool_cmd_speed(&ecmd);
964
965 if (speed == SPEED_1000)
966 mode |= AX_MEDIUM_GM;
967 else if (speed == SPEED_100)
968 mode |= AX_MEDIUM_PS;
969 else
970 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
971
972 mode |= AX_MEDIUM_ENCK;
973
974 if (ecmd.duplex == DUPLEX_FULL)
975 mode |= AX_MEDIUM_FD;
976 else
977 mode &= ~AX_MEDIUM_FD;
978
979 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
980 speed, ecmd.duplex, mode);
981
982 asix_write_medium_mode(dev, mode, 0);
983
984 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
985 marvell_led_status(dev, speed);
986
987 return 0;
988 }
989
990 static void ax88178_set_mfb(struct usbnet *dev)
991 {
992 u16 mfb = AX_RX_CTL_MFB_16384;
993 u16 rxctl;
994 u16 medium;
995 int old_rx_urb_size = dev->rx_urb_size;
996
997 if (dev->hard_mtu < 2048) {
998 dev->rx_urb_size = 2048;
999 mfb = AX_RX_CTL_MFB_2048;
1000 } else if (dev->hard_mtu < 4096) {
1001 dev->rx_urb_size = 4096;
1002 mfb = AX_RX_CTL_MFB_4096;
1003 } else if (dev->hard_mtu < 8192) {
1004 dev->rx_urb_size = 8192;
1005 mfb = AX_RX_CTL_MFB_8192;
1006 } else if (dev->hard_mtu < 16384) {
1007 dev->rx_urb_size = 16384;
1008 mfb = AX_RX_CTL_MFB_16384;
1009 }
1010
1011 rxctl = asix_read_rx_ctl(dev, 0);
1012 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
1013
1014 medium = asix_read_medium_status(dev, 0);
1015 if (dev->net->mtu > 1500)
1016 medium |= AX_MEDIUM_JFE;
1017 else
1018 medium &= ~AX_MEDIUM_JFE;
1019 asix_write_medium_mode(dev, medium, 0);
1020
1021 if (dev->rx_urb_size > old_rx_urb_size)
1022 usbnet_unlink_rx_urbs(dev);
1023 }
1024
1025 static int ax88178_change_mtu(struct net_device *net, int new_mtu)
1026 {
1027 struct usbnet *dev = netdev_priv(net);
1028 int ll_mtu = new_mtu + net->hard_header_len + 4;
1029
1030 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
1031
1032 if (new_mtu <= 0 || ll_mtu > 16384)
1033 return -EINVAL;
1034
1035 if ((ll_mtu % dev->maxpacket) == 0)
1036 return -EDOM;
1037
1038 net->mtu = new_mtu;
1039 dev->hard_mtu = net->mtu + net->hard_header_len;
1040 ax88178_set_mfb(dev);
1041
1042 /* max qlen depend on hard_mtu and rx_urb_size */
1043 usbnet_update_max_qlen(dev);
1044
1045 return 0;
1046 }
1047
1048 static const struct net_device_ops ax88178_netdev_ops = {
1049 .ndo_open = usbnet_open,
1050 .ndo_stop = usbnet_stop,
1051 .ndo_start_xmit = usbnet_start_xmit,
1052 .ndo_tx_timeout = usbnet_tx_timeout,
1053 .ndo_set_mac_address = asix_set_mac_address,
1054 .ndo_validate_addr = eth_validate_addr,
1055 .ndo_set_rx_mode = asix_set_multicast,
1056 .ndo_do_ioctl = asix_ioctl,
1057 .ndo_change_mtu = ax88178_change_mtu,
1058 };
1059
1060 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1061 {
1062 int ret;
1063 u8 buf[ETH_ALEN];
1064
1065 usbnet_get_endpoints(dev,intf);
1066
1067 /* Get the MAC address */
1068 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
1069 if (ret < 0) {
1070 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
1071 return ret;
1072 }
1073
1074 asix_set_netdev_dev_addr(dev, buf);
1075
1076 /* Initialize MII structure */
1077 dev->mii.dev = dev->net;
1078 dev->mii.mdio_read = asix_mdio_read;
1079 dev->mii.mdio_write = asix_mdio_write;
1080 dev->mii.phy_id_mask = 0x1f;
1081 dev->mii.reg_num_mask = 0xff;
1082 dev->mii.supports_gmii = 1;
1083 dev->mii.phy_id = asix_get_phy_addr(dev);
1084
1085 dev->net->netdev_ops = &ax88178_netdev_ops;
1086 dev->net->ethtool_ops = &ax88178_ethtool_ops;
1087
1088 /* Blink LEDS so users know driver saw dongle */
1089 asix_sw_reset(dev, 0, 0);
1090 msleep(150);
1091
1092 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
1093 msleep(150);
1094
1095 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1096 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1097 /* hard_mtu is still the default - the device does not support
1098 jumbo eth frames */
1099 dev->rx_urb_size = 2048;
1100 }
1101
1102 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1103 if (!dev->driver_priv)
1104 return -ENOMEM;
1105
1106 return 0;
1107 }
1108
1109 static const struct driver_info ax8817x_info = {
1110 .description = "ASIX AX8817x USB 2.0 Ethernet",
1111 .bind = ax88172_bind,
1112 .status = asix_status,
1113 .link_reset = ax88172_link_reset,
1114 .reset = ax88172_link_reset,
1115 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1116 .data = 0x00130103,
1117 };
1118
1119 static const struct driver_info dlink_dub_e100_info = {
1120 .description = "DLink DUB-E100 USB Ethernet",
1121 .bind = ax88172_bind,
1122 .status = asix_status,
1123 .link_reset = ax88172_link_reset,
1124 .reset = ax88172_link_reset,
1125 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1126 .data = 0x009f9d9f,
1127 };
1128
1129 static const struct driver_info netgear_fa120_info = {
1130 .description = "Netgear FA-120 USB Ethernet",
1131 .bind = ax88172_bind,
1132 .status = asix_status,
1133 .link_reset = ax88172_link_reset,
1134 .reset = ax88172_link_reset,
1135 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1136 .data = 0x00130103,
1137 };
1138
1139 static const struct driver_info hawking_uf200_info = {
1140 .description = "Hawking UF200 USB Ethernet",
1141 .bind = ax88172_bind,
1142 .status = asix_status,
1143 .link_reset = ax88172_link_reset,
1144 .reset = ax88172_link_reset,
1145 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1146 .data = 0x001f1d1f,
1147 };
1148
1149 static const struct driver_info ax88772_info = {
1150 .description = "ASIX AX88772 USB 2.0 Ethernet",
1151 .bind = ax88772_bind,
1152 .unbind = ax88772_unbind,
1153 .status = asix_status,
1154 .link_reset = ax88772_link_reset,
1155 .reset = ax88772_reset,
1156 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
1157 .rx_fixup = asix_rx_fixup_common,
1158 .tx_fixup = asix_tx_fixup,
1159 };
1160
1161 static const struct driver_info ax88772b_info = {
1162 .description = "ASIX AX88772B USB 2.0 Ethernet",
1163 .bind = ax88772_bind,
1164 .unbind = ax88772_unbind,
1165 .status = asix_status,
1166 .link_reset = ax88772_link_reset,
1167 .reset = ax88772_reset,
1168 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1169 FLAG_MULTI_PACKET,
1170 .rx_fixup = asix_rx_fixup_common,
1171 .tx_fixup = asix_tx_fixup,
1172 .data = FLAG_EEPROM_MAC,
1173 };
1174
1175 static const struct driver_info ax88178_info = {
1176 .description = "ASIX AX88178 USB 2.0 Ethernet",
1177 .bind = ax88178_bind,
1178 .unbind = ax88772_unbind,
1179 .status = asix_status,
1180 .link_reset = ax88178_link_reset,
1181 .reset = ax88178_reset,
1182 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1183 FLAG_MULTI_PACKET,
1184 .rx_fixup = asix_rx_fixup_common,
1185 .tx_fixup = asix_tx_fixup,
1186 };
1187
1188 /*
1189 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1190 * no-name packaging.
1191 * USB device strings are:
1192 * 1: Manufacturer: USBLINK
1193 * 2: Product: HG20F9 USB2.0
1194 * 3: Serial: 000003
1195 * Appears to be compatible with Asix 88772B.
1196 */
1197 static const struct driver_info hg20f9_info = {
1198 .description = "HG20F9 USB 2.0 Ethernet",
1199 .bind = ax88772_bind,
1200 .unbind = ax88772_unbind,
1201 .status = asix_status,
1202 .link_reset = ax88772_link_reset,
1203 .reset = ax88772_reset,
1204 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1205 FLAG_MULTI_PACKET,
1206 .rx_fixup = asix_rx_fixup_common,
1207 .tx_fixup = asix_tx_fixup,
1208 .data = FLAG_EEPROM_MAC,
1209 };
1210
1211 static const struct usb_device_id products [] = {
1212 {
1213 // Linksys USB200M
1214 USB_DEVICE (0x077b, 0x2226),
1215 .driver_info = (unsigned long) &ax8817x_info,
1216 }, {
1217 // Netgear FA120
1218 USB_DEVICE (0x0846, 0x1040),
1219 .driver_info = (unsigned long) &netgear_fa120_info,
1220 }, {
1221 // DLink DUB-E100
1222 USB_DEVICE (0x2001, 0x1a00),
1223 .driver_info = (unsigned long) &dlink_dub_e100_info,
1224 }, {
1225 // Intellinet, ST Lab USB Ethernet
1226 USB_DEVICE (0x0b95, 0x1720),
1227 .driver_info = (unsigned long) &ax8817x_info,
1228 }, {
1229 // Hawking UF200, TrendNet TU2-ET100
1230 USB_DEVICE (0x07b8, 0x420a),
1231 .driver_info = (unsigned long) &hawking_uf200_info,
1232 }, {
1233 // Billionton Systems, USB2AR
1234 USB_DEVICE (0x08dd, 0x90ff),
1235 .driver_info = (unsigned long) &ax8817x_info,
1236 }, {
1237 // Billionton Systems, GUSB2AM-1G-B
1238 USB_DEVICE(0x08dd, 0x0114),
1239 .driver_info = (unsigned long) &ax88178_info,
1240 }, {
1241 // ATEN UC210T
1242 USB_DEVICE (0x0557, 0x2009),
1243 .driver_info = (unsigned long) &ax8817x_info,
1244 }, {
1245 // Buffalo LUA-U2-KTX
1246 USB_DEVICE (0x0411, 0x003d),
1247 .driver_info = (unsigned long) &ax8817x_info,
1248 }, {
1249 // Buffalo LUA-U2-GT 10/100/1000
1250 USB_DEVICE (0x0411, 0x006e),
1251 .driver_info = (unsigned long) &ax88178_info,
1252 }, {
1253 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1254 USB_DEVICE (0x6189, 0x182d),
1255 .driver_info = (unsigned long) &ax8817x_info,
1256 }, {
1257 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1258 USB_DEVICE (0x0df6, 0x0056),
1259 .driver_info = (unsigned long) &ax88178_info,
1260 }, {
1261 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1262 USB_DEVICE (0x0df6, 0x061c),
1263 .driver_info = (unsigned long) &ax88178_info,
1264 }, {
1265 // corega FEther USB2-TX
1266 USB_DEVICE (0x07aa, 0x0017),
1267 .driver_info = (unsigned long) &ax8817x_info,
1268 }, {
1269 // Surecom EP-1427X-2
1270 USB_DEVICE (0x1189, 0x0893),
1271 .driver_info = (unsigned long) &ax8817x_info,
1272 }, {
1273 // goodway corp usb gwusb2e
1274 USB_DEVICE (0x1631, 0x6200),
1275 .driver_info = (unsigned long) &ax8817x_info,
1276 }, {
1277 // JVC MP-PRX1 Port Replicator
1278 USB_DEVICE (0x04f1, 0x3008),
1279 .driver_info = (unsigned long) &ax8817x_info,
1280 }, {
1281 // Lenovo U2L100P 10/100
1282 USB_DEVICE (0x17ef, 0x7203),
1283 .driver_info = (unsigned long)&ax88772b_info,
1284 }, {
1285 // ASIX AX88772B 10/100
1286 USB_DEVICE (0x0b95, 0x772b),
1287 .driver_info = (unsigned long) &ax88772b_info,
1288 }, {
1289 // ASIX AX88772 10/100
1290 USB_DEVICE (0x0b95, 0x7720),
1291 .driver_info = (unsigned long) &ax88772_info,
1292 }, {
1293 // ASIX AX88178 10/100/1000
1294 USB_DEVICE (0x0b95, 0x1780),
1295 .driver_info = (unsigned long) &ax88178_info,
1296 }, {
1297 // Logitec LAN-GTJ/U2A
1298 USB_DEVICE (0x0789, 0x0160),
1299 .driver_info = (unsigned long) &ax88178_info,
1300 }, {
1301 // Linksys USB200M Rev 2
1302 USB_DEVICE (0x13b1, 0x0018),
1303 .driver_info = (unsigned long) &ax88772_info,
1304 }, {
1305 // 0Q0 cable ethernet
1306 USB_DEVICE (0x1557, 0x7720),
1307 .driver_info = (unsigned long) &ax88772_info,
1308 }, {
1309 // DLink DUB-E100 H/W Ver B1
1310 USB_DEVICE (0x07d1, 0x3c05),
1311 .driver_info = (unsigned long) &ax88772_info,
1312 }, {
1313 // DLink DUB-E100 H/W Ver B1 Alternate
1314 USB_DEVICE (0x2001, 0x3c05),
1315 .driver_info = (unsigned long) &ax88772_info,
1316 }, {
1317 // DLink DUB-E100 H/W Ver C1
1318 USB_DEVICE (0x2001, 0x1a02),
1319 .driver_info = (unsigned long) &ax88772_info,
1320 }, {
1321 // Linksys USB1000
1322 USB_DEVICE (0x1737, 0x0039),
1323 .driver_info = (unsigned long) &ax88178_info,
1324 }, {
1325 // IO-DATA ETG-US2
1326 USB_DEVICE (0x04bb, 0x0930),
1327 .driver_info = (unsigned long) &ax88178_info,
1328 }, {
1329 // Belkin F5D5055
1330 USB_DEVICE(0x050d, 0x5055),
1331 .driver_info = (unsigned long) &ax88178_info,
1332 }, {
1333 // Apple USB Ethernet Adapter
1334 USB_DEVICE(0x05ac, 0x1402),
1335 .driver_info = (unsigned long) &ax88772_info,
1336 }, {
1337 // Cables-to-Go USB Ethernet Adapter
1338 USB_DEVICE(0x0b95, 0x772a),
1339 .driver_info = (unsigned long) &ax88772_info,
1340 }, {
1341 // ABOCOM for pci
1342 USB_DEVICE(0x14ea, 0xab11),
1343 .driver_info = (unsigned long) &ax88178_info,
1344 }, {
1345 // ASIX 88772a
1346 USB_DEVICE(0x0db0, 0xa877),
1347 .driver_info = (unsigned long) &ax88772_info,
1348 }, {
1349 // Asus USB Ethernet Adapter
1350 USB_DEVICE (0x0b95, 0x7e2b),
1351 .driver_info = (unsigned long)&ax88772b_info,
1352 }, {
1353 /* ASIX 88172a demo board */
1354 USB_DEVICE(0x0b95, 0x172a),
1355 .driver_info = (unsigned long) &ax88172a_info,
1356 }, {
1357 /*
1358 * USBLINK HG20F9 "USB 2.0 LAN"
1359 * Appears to have gazumped Linksys's manufacturer ID but
1360 * doesn't (yet) conflict with any known Linksys product.
1361 */
1362 USB_DEVICE(0x066b, 0x20f9),
1363 .driver_info = (unsigned long) &hg20f9_info,
1364 },
1365 { }, // END
1366 };
1367 MODULE_DEVICE_TABLE(usb, products);
1368
1369 static struct usb_driver asix_driver = {
1370 .name = DRIVER_NAME,
1371 .id_table = products,
1372 .probe = usbnet_probe,
1373 .suspend = asix_suspend,
1374 .resume = asix_resume,
1375 .disconnect = usbnet_disconnect,
1376 .supports_autosuspend = 1,
1377 .disable_hub_initiated_lpm = 1,
1378 };
1379
1380 module_usb_driver(asix_driver);
1381
1382 MODULE_AUTHOR("David Hollis");
1383 MODULE_VERSION(DRIVER_VERSION);
1384 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1385 MODULE_LICENSE("GPL");
1386
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