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1 /*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27
28 /* Version Information */
29 #define DRIVER_VERSION "v1.07.0 (2014/10/09)"
30 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
31 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
32 #define MODULENAME "r8152"
33
34 #define R8152_PHY_ID 32
35
36 #define PLA_IDR 0xc000
37 #define PLA_RCR 0xc010
38 #define PLA_RMS 0xc016
39 #define PLA_RXFIFO_CTRL0 0xc0a0
40 #define PLA_RXFIFO_CTRL1 0xc0a4
41 #define PLA_RXFIFO_CTRL2 0xc0a8
42 #define PLA_FMC 0xc0b4
43 #define PLA_CFG_WOL 0xc0b6
44 #define PLA_TEREDO_CFG 0xc0bc
45 #define PLA_MAR 0xcd00
46 #define PLA_BACKUP 0xd000
47 #define PAL_BDC_CR 0xd1a0
48 #define PLA_TEREDO_TIMER 0xd2cc
49 #define PLA_REALWOW_TIMER 0xd2e8
50 #define PLA_LEDSEL 0xdd90
51 #define PLA_LED_FEATURE 0xdd92
52 #define PLA_PHYAR 0xde00
53 #define PLA_BOOT_CTRL 0xe004
54 #define PLA_GPHY_INTR_IMR 0xe022
55 #define PLA_EEE_CR 0xe040
56 #define PLA_EEEP_CR 0xe080
57 #define PLA_MAC_PWR_CTRL 0xe0c0
58 #define PLA_MAC_PWR_CTRL2 0xe0ca
59 #define PLA_MAC_PWR_CTRL3 0xe0cc
60 #define PLA_MAC_PWR_CTRL4 0xe0ce
61 #define PLA_WDT6_CTRL 0xe428
62 #define PLA_TCR0 0xe610
63 #define PLA_TCR1 0xe612
64 #define PLA_MTPS 0xe615
65 #define PLA_TXFIFO_CTRL 0xe618
66 #define PLA_RSTTALLY 0xe800
67 #define PLA_CR 0xe813
68 #define PLA_CRWECR 0xe81c
69 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
70 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
71 #define PLA_CONFIG5 0xe822
72 #define PLA_PHY_PWR 0xe84c
73 #define PLA_OOB_CTRL 0xe84f
74 #define PLA_CPCR 0xe854
75 #define PLA_MISC_0 0xe858
76 #define PLA_MISC_1 0xe85a
77 #define PLA_OCP_GPHY_BASE 0xe86c
78 #define PLA_TALLYCNT 0xe890
79 #define PLA_SFF_STS_7 0xe8de
80 #define PLA_PHYSTATUS 0xe908
81 #define PLA_BP_BA 0xfc26
82 #define PLA_BP_0 0xfc28
83 #define PLA_BP_1 0xfc2a
84 #define PLA_BP_2 0xfc2c
85 #define PLA_BP_3 0xfc2e
86 #define PLA_BP_4 0xfc30
87 #define PLA_BP_5 0xfc32
88 #define PLA_BP_6 0xfc34
89 #define PLA_BP_7 0xfc36
90 #define PLA_BP_EN 0xfc38
91
92 #define USB_U2P3_CTRL 0xb460
93 #define USB_DEV_STAT 0xb808
94 #define USB_USB_CTRL 0xd406
95 #define USB_PHY_CTRL 0xd408
96 #define USB_TX_AGG 0xd40a
97 #define USB_RX_BUF_TH 0xd40c
98 #define USB_USB_TIMER 0xd428
99 #define USB_RX_EARLY_AGG 0xd42c
100 #define USB_PM_CTRL_STATUS 0xd432
101 #define USB_TX_DMA 0xd434
102 #define USB_TOLERANCE 0xd490
103 #define USB_LPM_CTRL 0xd41a
104 #define USB_UPS_CTRL 0xd800
105 #define USB_MISC_0 0xd81a
106 #define USB_POWER_CUT 0xd80a
107 #define USB_AFE_CTRL2 0xd824
108 #define USB_WDT11_CTRL 0xe43c
109 #define USB_BP_BA 0xfc26
110 #define USB_BP_0 0xfc28
111 #define USB_BP_1 0xfc2a
112 #define USB_BP_2 0xfc2c
113 #define USB_BP_3 0xfc2e
114 #define USB_BP_4 0xfc30
115 #define USB_BP_5 0xfc32
116 #define USB_BP_6 0xfc34
117 #define USB_BP_7 0xfc36
118 #define USB_BP_EN 0xfc38
119
120 /* OCP Registers */
121 #define OCP_ALDPS_CONFIG 0x2010
122 #define OCP_EEE_CONFIG1 0x2080
123 #define OCP_EEE_CONFIG2 0x2092
124 #define OCP_EEE_CONFIG3 0x2094
125 #define OCP_BASE_MII 0xa400
126 #define OCP_EEE_AR 0xa41a
127 #define OCP_EEE_DATA 0xa41c
128 #define OCP_PHY_STATUS 0xa420
129 #define OCP_POWER_CFG 0xa430
130 #define OCP_EEE_CFG 0xa432
131 #define OCP_SRAM_ADDR 0xa436
132 #define OCP_SRAM_DATA 0xa438
133 #define OCP_DOWN_SPEED 0xa442
134 #define OCP_EEE_ABLE 0xa5c4
135 #define OCP_EEE_ADV 0xa5d0
136 #define OCP_EEE_LPABLE 0xa5d2
137 #define OCP_ADC_CFG 0xbc06
138
139 /* SRAM Register */
140 #define SRAM_LPF_CFG 0x8012
141 #define SRAM_10M_AMP1 0x8080
142 #define SRAM_10M_AMP2 0x8082
143 #define SRAM_IMPEDANCE 0x8084
144
145 /* PLA_RCR */
146 #define RCR_AAP 0x00000001
147 #define RCR_APM 0x00000002
148 #define RCR_AM 0x00000004
149 #define RCR_AB 0x00000008
150 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
151
152 /* PLA_RXFIFO_CTRL0 */
153 #define RXFIFO_THR1_NORMAL 0x00080002
154 #define RXFIFO_THR1_OOB 0x01800003
155
156 /* PLA_RXFIFO_CTRL1 */
157 #define RXFIFO_THR2_FULL 0x00000060
158 #define RXFIFO_THR2_HIGH 0x00000038
159 #define RXFIFO_THR2_OOB 0x0000004a
160 #define RXFIFO_THR2_NORMAL 0x00a0
161
162 /* PLA_RXFIFO_CTRL2 */
163 #define RXFIFO_THR3_FULL 0x00000078
164 #define RXFIFO_THR3_HIGH 0x00000048
165 #define RXFIFO_THR3_OOB 0x0000005a
166 #define RXFIFO_THR3_NORMAL 0x0110
167
168 /* PLA_TXFIFO_CTRL */
169 #define TXFIFO_THR_NORMAL 0x00400008
170 #define TXFIFO_THR_NORMAL2 0x01000008
171
172 /* PLA_FMC */
173 #define FMC_FCR_MCU_EN 0x0001
174
175 /* PLA_EEEP_CR */
176 #define EEEP_CR_EEEP_TX 0x0002
177
178 /* PLA_WDT6_CTRL */
179 #define WDT6_SET_MODE 0x0010
180
181 /* PLA_TCR0 */
182 #define TCR0_TX_EMPTY 0x0800
183 #define TCR0_AUTO_FIFO 0x0080
184
185 /* PLA_TCR1 */
186 #define VERSION_MASK 0x7cf0
187
188 /* PLA_MTPS */
189 #define MTPS_JUMBO (12 * 1024 / 64)
190 #define MTPS_DEFAULT (6 * 1024 / 64)
191
192 /* PLA_RSTTALLY */
193 #define TALLY_RESET 0x0001
194
195 /* PLA_CR */
196 #define CR_RST 0x10
197 #define CR_RE 0x08
198 #define CR_TE 0x04
199
200 /* PLA_CRWECR */
201 #define CRWECR_NORAML 0x00
202 #define CRWECR_CONFIG 0xc0
203
204 /* PLA_OOB_CTRL */
205 #define NOW_IS_OOB 0x80
206 #define TXFIFO_EMPTY 0x20
207 #define RXFIFO_EMPTY 0x10
208 #define LINK_LIST_READY 0x02
209 #define DIS_MCU_CLROOB 0x01
210 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
211
212 /* PLA_MISC_1 */
213 #define RXDY_GATED_EN 0x0008
214
215 /* PLA_SFF_STS_7 */
216 #define RE_INIT_LL 0x8000
217 #define MCU_BORW_EN 0x4000
218
219 /* PLA_CPCR */
220 #define CPCR_RX_VLAN 0x0040
221
222 /* PLA_CFG_WOL */
223 #define MAGIC_EN 0x0001
224
225 /* PLA_TEREDO_CFG */
226 #define TEREDO_SEL 0x8000
227 #define TEREDO_WAKE_MASK 0x7f00
228 #define TEREDO_RS_EVENT_MASK 0x00fe
229 #define OOB_TEREDO_EN 0x0001
230
231 /* PAL_BDC_CR */
232 #define ALDPS_PROXY_MODE 0x0001
233
234 /* PLA_CONFIG34 */
235 #define LINK_ON_WAKE_EN 0x0010
236 #define LINK_OFF_WAKE_EN 0x0008
237
238 /* PLA_CONFIG5 */
239 #define BWF_EN 0x0040
240 #define MWF_EN 0x0020
241 #define UWF_EN 0x0010
242 #define LAN_WAKE_EN 0x0002
243
244 /* PLA_LED_FEATURE */
245 #define LED_MODE_MASK 0x0700
246
247 /* PLA_PHY_PWR */
248 #define TX_10M_IDLE_EN 0x0080
249 #define PFM_PWM_SWITCH 0x0040
250
251 /* PLA_MAC_PWR_CTRL */
252 #define D3_CLK_GATED_EN 0x00004000
253 #define MCU_CLK_RATIO 0x07010f07
254 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
255 #define ALDPS_SPDWN_RATIO 0x0f87
256
257 /* PLA_MAC_PWR_CTRL2 */
258 #define EEE_SPDWN_RATIO 0x8007
259
260 /* PLA_MAC_PWR_CTRL3 */
261 #define PKT_AVAIL_SPDWN_EN 0x0100
262 #define SUSPEND_SPDWN_EN 0x0004
263 #define U1U2_SPDWN_EN 0x0002
264 #define L1_SPDWN_EN 0x0001
265
266 /* PLA_MAC_PWR_CTRL4 */
267 #define PWRSAVE_SPDWN_EN 0x1000
268 #define RXDV_SPDWN_EN 0x0800
269 #define TX10MIDLE_EN 0x0100
270 #define TP100_SPDWN_EN 0x0020
271 #define TP500_SPDWN_EN 0x0010
272 #define TP1000_SPDWN_EN 0x0008
273 #define EEE_SPDWN_EN 0x0001
274
275 /* PLA_GPHY_INTR_IMR */
276 #define GPHY_STS_MSK 0x0001
277 #define SPEED_DOWN_MSK 0x0002
278 #define SPDWN_RXDV_MSK 0x0004
279 #define SPDWN_LINKCHG_MSK 0x0008
280
281 /* PLA_PHYAR */
282 #define PHYAR_FLAG 0x80000000
283
284 /* PLA_EEE_CR */
285 #define EEE_RX_EN 0x0001
286 #define EEE_TX_EN 0x0002
287
288 /* PLA_BOOT_CTRL */
289 #define AUTOLOAD_DONE 0x0002
290
291 /* USB_DEV_STAT */
292 #define STAT_SPEED_MASK 0x0006
293 #define STAT_SPEED_HIGH 0x0000
294 #define STAT_SPEED_FULL 0x0002
295
296 /* USB_TX_AGG */
297 #define TX_AGG_MAX_THRESHOLD 0x03
298
299 /* USB_RX_BUF_TH */
300 #define RX_THR_SUPPER 0x0c350180
301 #define RX_THR_HIGH 0x7a120180
302 #define RX_THR_SLOW 0xffff0180
303
304 /* USB_TX_DMA */
305 #define TEST_MODE_DISABLE 0x00000001
306 #define TX_SIZE_ADJUST1 0x00000100
307
308 /* USB_UPS_CTRL */
309 #define POWER_CUT 0x0100
310
311 /* USB_PM_CTRL_STATUS */
312 #define RESUME_INDICATE 0x0001
313
314 /* USB_USB_CTRL */
315 #define RX_AGG_DISABLE 0x0010
316
317 /* USB_U2P3_CTRL */
318 #define U2P3_ENABLE 0x0001
319
320 /* USB_POWER_CUT */
321 #define PWR_EN 0x0001
322 #define PHASE2_EN 0x0008
323
324 /* USB_MISC_0 */
325 #define PCUT_STATUS 0x0001
326
327 /* USB_RX_EARLY_AGG */
328 #define EARLY_AGG_SUPPER 0x0e832981
329 #define EARLY_AGG_HIGH 0x0e837a12
330 #define EARLY_AGG_SLOW 0x0e83ffff
331
332 /* USB_WDT11_CTRL */
333 #define TIMER11_EN 0x0001
334
335 /* USB_LPM_CTRL */
336 #define LPM_TIMER_MASK 0x0c
337 #define LPM_TIMER_500MS 0x04 /* 500 ms */
338 #define LPM_TIMER_500US 0x0c /* 500 us */
339
340 /* USB_AFE_CTRL2 */
341 #define SEN_VAL_MASK 0xf800
342 #define SEN_VAL_NORMAL 0xa000
343 #define SEL_RXIDLE 0x0100
344
345 /* OCP_ALDPS_CONFIG */
346 #define ENPWRSAVE 0x8000
347 #define ENPDNPS 0x0200
348 #define LINKENA 0x0100
349 #define DIS_SDSAVE 0x0010
350
351 /* OCP_PHY_STATUS */
352 #define PHY_STAT_MASK 0x0007
353 #define PHY_STAT_LAN_ON 3
354 #define PHY_STAT_PWRDN 5
355
356 /* OCP_POWER_CFG */
357 #define EEE_CLKDIV_EN 0x8000
358 #define EN_ALDPS 0x0004
359 #define EN_10M_PLLOFF 0x0001
360
361 /* OCP_EEE_CONFIG1 */
362 #define RG_TXLPI_MSK_HFDUP 0x8000
363 #define RG_MATCLR_EN 0x4000
364 #define EEE_10_CAP 0x2000
365 #define EEE_NWAY_EN 0x1000
366 #define TX_QUIET_EN 0x0200
367 #define RX_QUIET_EN 0x0100
368 #define sd_rise_time_mask 0x0070
369 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
370 #define RG_RXLPI_MSK_HFDUP 0x0008
371 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
372
373 /* OCP_EEE_CONFIG2 */
374 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
375 #define RG_DACQUIET_EN 0x0400
376 #define RG_LDVQUIET_EN 0x0200
377 #define RG_CKRSEL 0x0020
378 #define RG_EEEPRG_EN 0x0010
379
380 /* OCP_EEE_CONFIG3 */
381 #define fast_snr_mask 0xff80
382 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
383 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
384 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
385
386 /* OCP_EEE_AR */
387 /* bit[15:14] function */
388 #define FUN_ADDR 0x0000
389 #define FUN_DATA 0x4000
390 /* bit[4:0] device addr */
391
392 /* OCP_EEE_CFG */
393 #define CTAP_SHORT_EN 0x0040
394 #define EEE10_EN 0x0010
395
396 /* OCP_DOWN_SPEED */
397 #define EN_10M_BGOFF 0x0080
398
399 /* OCP_ADC_CFG */
400 #define CKADSEL_L 0x0100
401 #define ADC_EN 0x0080
402 #define EN_EMI_L 0x0040
403
404 /* SRAM_LPF_CFG */
405 #define LPF_AUTO_TUNE 0x8000
406
407 /* SRAM_10M_AMP1 */
408 #define GDAC_IB_UPALL 0x0008
409
410 /* SRAM_10M_AMP2 */
411 #define AMP_DN 0x0200
412
413 /* SRAM_IMPEDANCE */
414 #define RX_DRIVING_MASK 0x6000
415
416 enum rtl_register_content {
417 _1000bps = 0x10,
418 _100bps = 0x08,
419 _10bps = 0x04,
420 LINK_STATUS = 0x02,
421 FULL_DUP = 0x01,
422 };
423
424 #define RTL8152_MAX_TX 4
425 #define RTL8152_MAX_RX 10
426 #define INTBUFSIZE 2
427 #define CRC_SIZE 4
428 #define TX_ALIGN 4
429 #define RX_ALIGN 8
430
431 #define INTR_LINK 0x0004
432
433 #define RTL8152_REQT_READ 0xc0
434 #define RTL8152_REQT_WRITE 0x40
435 #define RTL8152_REQ_GET_REGS 0x05
436 #define RTL8152_REQ_SET_REGS 0x05
437
438 #define BYTE_EN_DWORD 0xff
439 #define BYTE_EN_WORD 0x33
440 #define BYTE_EN_BYTE 0x11
441 #define BYTE_EN_SIX_BYTES 0x3f
442 #define BYTE_EN_START_MASK 0x0f
443 #define BYTE_EN_END_MASK 0xf0
444
445 #define RTL8153_MAX_PACKET 9216 /* 9K */
446 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
447 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
448 #define RTL8153_RMS RTL8153_MAX_PACKET
449 #define RTL8152_TX_TIMEOUT (5 * HZ)
450
451 /* rtl8152 flags */
452 enum rtl8152_flags {
453 RTL8152_UNPLUG = 0,
454 RTL8152_SET_RX_MODE,
455 WORK_ENABLE,
456 RTL8152_LINK_CHG,
457 SELECTIVE_SUSPEND,
458 PHY_RESET,
459 SCHEDULE_TASKLET,
460 };
461
462 /* Define these values to match your device */
463 #define VENDOR_ID_REALTEK 0x0bda
464 #define VENDOR_ID_SAMSUNG 0x04e8
465
466 #define MCU_TYPE_PLA 0x0100
467 #define MCU_TYPE_USB 0x0000
468
469 #define REALTEK_USB_DEVICE(vend, prod) \
470 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
471
472 struct tally_counter {
473 __le64 tx_packets;
474 __le64 rx_packets;
475 __le64 tx_errors;
476 __le32 rx_errors;
477 __le16 rx_missed;
478 __le16 align_errors;
479 __le32 tx_one_collision;
480 __le32 tx_multi_collision;
481 __le64 rx_unicast;
482 __le64 rx_broadcast;
483 __le32 rx_multicast;
484 __le16 tx_aborted;
485 __le16 tx_underrun;
486 };
487
488 struct rx_desc {
489 __le32 opts1;
490 #define RX_LEN_MASK 0x7fff
491
492 __le32 opts2;
493 #define RD_UDP_CS (1 << 23)
494 #define RD_TCP_CS (1 << 22)
495 #define RD_IPV6_CS (1 << 20)
496 #define RD_IPV4_CS (1 << 19)
497
498 __le32 opts3;
499 #define IPF (1 << 23) /* IP checksum fail */
500 #define UDPF (1 << 22) /* UDP checksum fail */
501 #define TCPF (1 << 21) /* TCP checksum fail */
502 #define RX_VLAN_TAG (1 << 16)
503
504 __le32 opts4;
505 __le32 opts5;
506 __le32 opts6;
507 };
508
509 struct tx_desc {
510 __le32 opts1;
511 #define TX_FS (1 << 31) /* First segment of a packet */
512 #define TX_LS (1 << 30) /* Final segment of a packet */
513 #define GTSENDV4 (1 << 28)
514 #define GTSENDV6 (1 << 27)
515 #define GTTCPHO_SHIFT 18
516 #define GTTCPHO_MAX 0x7fU
517 #define TX_LEN_MAX 0x3ffffU
518
519 __le32 opts2;
520 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
521 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
522 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
523 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
524 #define MSS_SHIFT 17
525 #define MSS_MAX 0x7ffU
526 #define TCPHO_SHIFT 17
527 #define TCPHO_MAX 0x7ffU
528 #define TX_VLAN_TAG (1 << 16)
529 };
530
531 struct r8152;
532
533 struct rx_agg {
534 struct list_head list;
535 struct urb *urb;
536 struct r8152 *context;
537 void *buffer;
538 void *head;
539 };
540
541 struct tx_agg {
542 struct list_head list;
543 struct urb *urb;
544 struct r8152 *context;
545 void *buffer;
546 void *head;
547 u32 skb_num;
548 u32 skb_len;
549 };
550
551 struct r8152 {
552 unsigned long flags;
553 struct usb_device *udev;
554 struct tasklet_struct tl;
555 struct usb_interface *intf;
556 struct net_device *netdev;
557 struct urb *intr_urb;
558 struct tx_agg tx_info[RTL8152_MAX_TX];
559 struct rx_agg rx_info[RTL8152_MAX_RX];
560 struct list_head rx_done, tx_free;
561 struct sk_buff_head tx_queue;
562 spinlock_t rx_lock, tx_lock;
563 struct delayed_work schedule;
564 struct mii_if_info mii;
565 struct mutex control; /* use for hw setting */
566
567 struct rtl_ops {
568 void (*init)(struct r8152 *);
569 int (*enable)(struct r8152 *);
570 void (*disable)(struct r8152 *);
571 void (*up)(struct r8152 *);
572 void (*down)(struct r8152 *);
573 void (*unload)(struct r8152 *);
574 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
575 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
576 } rtl_ops;
577
578 int intr_interval;
579 u32 saved_wolopts;
580 u32 msg_enable;
581 u32 tx_qlen;
582 u16 ocp_base;
583 u8 *intr_buff;
584 u8 version;
585 u8 speed;
586 };
587
588 enum rtl_version {
589 RTL_VER_UNKNOWN = 0,
590 RTL_VER_01,
591 RTL_VER_02,
592 RTL_VER_03,
593 RTL_VER_04,
594 RTL_VER_05,
595 RTL_VER_MAX
596 };
597
598 enum tx_csum_stat {
599 TX_CSUM_SUCCESS = 0,
600 TX_CSUM_TSO,
601 TX_CSUM_NONE
602 };
603
604 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
605 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
606 */
607 static const int multicast_filter_limit = 32;
608 static unsigned int agg_buf_sz = 16384;
609
610 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
611 VLAN_ETH_HLEN - VLAN_HLEN)
612
613 static
614 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
615 {
616 int ret;
617 void *tmp;
618
619 tmp = kmalloc(size, GFP_KERNEL);
620 if (!tmp)
621 return -ENOMEM;
622
623 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
624 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
625 value, index, tmp, size, 500);
626
627 memcpy(data, tmp, size);
628 kfree(tmp);
629
630 return ret;
631 }
632
633 static
634 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
635 {
636 int ret;
637 void *tmp;
638
639 tmp = kmemdup(data, size, GFP_KERNEL);
640 if (!tmp)
641 return -ENOMEM;
642
643 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
644 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
645 value, index, tmp, size, 500);
646
647 kfree(tmp);
648
649 return ret;
650 }
651
652 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
653 void *data, u16 type)
654 {
655 u16 limit = 64;
656 int ret = 0;
657
658 if (test_bit(RTL8152_UNPLUG, &tp->flags))
659 return -ENODEV;
660
661 /* both size and indix must be 4 bytes align */
662 if ((size & 3) || !size || (index & 3) || !data)
663 return -EPERM;
664
665 if ((u32)index + (u32)size > 0xffff)
666 return -EPERM;
667
668 while (size) {
669 if (size > limit) {
670 ret = get_registers(tp, index, type, limit, data);
671 if (ret < 0)
672 break;
673
674 index += limit;
675 data += limit;
676 size -= limit;
677 } else {
678 ret = get_registers(tp, index, type, size, data);
679 if (ret < 0)
680 break;
681
682 index += size;
683 data += size;
684 size = 0;
685 break;
686 }
687 }
688
689 if (ret == -ENODEV)
690 set_bit(RTL8152_UNPLUG, &tp->flags);
691
692 return ret;
693 }
694
695 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
696 u16 size, void *data, u16 type)
697 {
698 int ret;
699 u16 byteen_start, byteen_end, byen;
700 u16 limit = 512;
701
702 if (test_bit(RTL8152_UNPLUG, &tp->flags))
703 return -ENODEV;
704
705 /* both size and indix must be 4 bytes align */
706 if ((size & 3) || !size || (index & 3) || !data)
707 return -EPERM;
708
709 if ((u32)index + (u32)size > 0xffff)
710 return -EPERM;
711
712 byteen_start = byteen & BYTE_EN_START_MASK;
713 byteen_end = byteen & BYTE_EN_END_MASK;
714
715 byen = byteen_start | (byteen_start << 4);
716 ret = set_registers(tp, index, type | byen, 4, data);
717 if (ret < 0)
718 goto error1;
719
720 index += 4;
721 data += 4;
722 size -= 4;
723
724 if (size) {
725 size -= 4;
726
727 while (size) {
728 if (size > limit) {
729 ret = set_registers(tp, index,
730 type | BYTE_EN_DWORD,
731 limit, data);
732 if (ret < 0)
733 goto error1;
734
735 index += limit;
736 data += limit;
737 size -= limit;
738 } else {
739 ret = set_registers(tp, index,
740 type | BYTE_EN_DWORD,
741 size, data);
742 if (ret < 0)
743 goto error1;
744
745 index += size;
746 data += size;
747 size = 0;
748 break;
749 }
750 }
751
752 byen = byteen_end | (byteen_end >> 4);
753 ret = set_registers(tp, index, type | byen, 4, data);
754 if (ret < 0)
755 goto error1;
756 }
757
758 error1:
759 if (ret == -ENODEV)
760 set_bit(RTL8152_UNPLUG, &tp->flags);
761
762 return ret;
763 }
764
765 static inline
766 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
767 {
768 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
769 }
770
771 static inline
772 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
773 {
774 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
775 }
776
777 static inline
778 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
779 {
780 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
781 }
782
783 static inline
784 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
785 {
786 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
787 }
788
789 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
790 {
791 __le32 data;
792
793 generic_ocp_read(tp, index, sizeof(data), &data, type);
794
795 return __le32_to_cpu(data);
796 }
797
798 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
799 {
800 __le32 tmp = __cpu_to_le32(data);
801
802 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
803 }
804
805 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
806 {
807 u32 data;
808 __le32 tmp;
809 u8 shift = index & 2;
810
811 index &= ~3;
812
813 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
814
815 data = __le32_to_cpu(tmp);
816 data >>= (shift * 8);
817 data &= 0xffff;
818
819 return (u16)data;
820 }
821
822 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
823 {
824 u32 mask = 0xffff;
825 __le32 tmp;
826 u16 byen = BYTE_EN_WORD;
827 u8 shift = index & 2;
828
829 data &= mask;
830
831 if (index & 2) {
832 byen <<= shift;
833 mask <<= (shift * 8);
834 data <<= (shift * 8);
835 index &= ~3;
836 }
837
838 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
839
840 data |= __le32_to_cpu(tmp) & ~mask;
841 tmp = __cpu_to_le32(data);
842
843 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
844 }
845
846 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
847 {
848 u32 data;
849 __le32 tmp;
850 u8 shift = index & 3;
851
852 index &= ~3;
853
854 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
855
856 data = __le32_to_cpu(tmp);
857 data >>= (shift * 8);
858 data &= 0xff;
859
860 return (u8)data;
861 }
862
863 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
864 {
865 u32 mask = 0xff;
866 __le32 tmp;
867 u16 byen = BYTE_EN_BYTE;
868 u8 shift = index & 3;
869
870 data &= mask;
871
872 if (index & 3) {
873 byen <<= shift;
874 mask <<= (shift * 8);
875 data <<= (shift * 8);
876 index &= ~3;
877 }
878
879 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
880
881 data |= __le32_to_cpu(tmp) & ~mask;
882 tmp = __cpu_to_le32(data);
883
884 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
885 }
886
887 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
888 {
889 u16 ocp_base, ocp_index;
890
891 ocp_base = addr & 0xf000;
892 if (ocp_base != tp->ocp_base) {
893 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
894 tp->ocp_base = ocp_base;
895 }
896
897 ocp_index = (addr & 0x0fff) | 0xb000;
898 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
899 }
900
901 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
902 {
903 u16 ocp_base, ocp_index;
904
905 ocp_base = addr & 0xf000;
906 if (ocp_base != tp->ocp_base) {
907 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
908 tp->ocp_base = ocp_base;
909 }
910
911 ocp_index = (addr & 0x0fff) | 0xb000;
912 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
913 }
914
915 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
916 {
917 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
918 }
919
920 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
921 {
922 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
923 }
924
925 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
926 {
927 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
928 ocp_reg_write(tp, OCP_SRAM_DATA, data);
929 }
930
931 static u16 sram_read(struct r8152 *tp, u16 addr)
932 {
933 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
934 return ocp_reg_read(tp, OCP_SRAM_DATA);
935 }
936
937 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
938 {
939 struct r8152 *tp = netdev_priv(netdev);
940 int ret;
941
942 if (test_bit(RTL8152_UNPLUG, &tp->flags))
943 return -ENODEV;
944
945 if (phy_id != R8152_PHY_ID)
946 return -EINVAL;
947
948 ret = r8152_mdio_read(tp, reg);
949
950 return ret;
951 }
952
953 static
954 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
955 {
956 struct r8152 *tp = netdev_priv(netdev);
957
958 if (test_bit(RTL8152_UNPLUG, &tp->flags))
959 return;
960
961 if (phy_id != R8152_PHY_ID)
962 return;
963
964 r8152_mdio_write(tp, reg, val);
965 }
966
967 static int
968 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
969
970 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
971 {
972 struct r8152 *tp = netdev_priv(netdev);
973 struct sockaddr *addr = p;
974 int ret = -EADDRNOTAVAIL;
975
976 if (!is_valid_ether_addr(addr->sa_data))
977 goto out1;
978
979 ret = usb_autopm_get_interface(tp->intf);
980 if (ret < 0)
981 goto out1;
982
983 mutex_lock(&tp->control);
984
985 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
986
987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
988 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
989 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
990
991 mutex_unlock(&tp->control);
992
993 usb_autopm_put_interface(tp->intf);
994 out1:
995 return ret;
996 }
997
998 static int set_ethernet_addr(struct r8152 *tp)
999 {
1000 struct net_device *dev = tp->netdev;
1001 struct sockaddr sa;
1002 int ret;
1003
1004 if (tp->version == RTL_VER_01)
1005 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1006 else
1007 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1008
1009 if (ret < 0) {
1010 netif_err(tp, probe, dev, "Get ether addr fail\n");
1011 } else if (!is_valid_ether_addr(sa.sa_data)) {
1012 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1013 sa.sa_data);
1014 eth_hw_addr_random(dev);
1015 ether_addr_copy(sa.sa_data, dev->dev_addr);
1016 ret = rtl8152_set_mac_address(dev, &sa);
1017 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1018 sa.sa_data);
1019 } else {
1020 if (tp->version == RTL_VER_01)
1021 ether_addr_copy(dev->dev_addr, sa.sa_data);
1022 else
1023 ret = rtl8152_set_mac_address(dev, &sa);
1024 }
1025
1026 return ret;
1027 }
1028
1029 static void read_bulk_callback(struct urb *urb)
1030 {
1031 struct net_device *netdev;
1032 int status = urb->status;
1033 struct rx_agg *agg;
1034 struct r8152 *tp;
1035
1036 agg = urb->context;
1037 if (!agg)
1038 return;
1039
1040 tp = agg->context;
1041 if (!tp)
1042 return;
1043
1044 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1045 return;
1046
1047 if (!test_bit(WORK_ENABLE, &tp->flags))
1048 return;
1049
1050 netdev = tp->netdev;
1051
1052 /* When link down, the driver would cancel all bulks. */
1053 /* This avoid the re-submitting bulk */
1054 if (!netif_carrier_ok(netdev))
1055 return;
1056
1057 usb_mark_last_busy(tp->udev);
1058
1059 switch (status) {
1060 case 0:
1061 if (urb->actual_length < ETH_ZLEN)
1062 break;
1063
1064 spin_lock(&tp->rx_lock);
1065 list_add_tail(&agg->list, &tp->rx_done);
1066 spin_unlock(&tp->rx_lock);
1067 tasklet_schedule(&tp->tl);
1068 return;
1069 case -ESHUTDOWN:
1070 set_bit(RTL8152_UNPLUG, &tp->flags);
1071 netif_device_detach(tp->netdev);
1072 return;
1073 case -ENOENT:
1074 return; /* the urb is in unlink state */
1075 case -ETIME:
1076 if (net_ratelimit())
1077 netdev_warn(netdev, "maybe reset is needed?\n");
1078 break;
1079 default:
1080 if (net_ratelimit())
1081 netdev_warn(netdev, "Rx status %d\n", status);
1082 break;
1083 }
1084
1085 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1086 }
1087
1088 static void write_bulk_callback(struct urb *urb)
1089 {
1090 struct net_device_stats *stats;
1091 struct net_device *netdev;
1092 struct tx_agg *agg;
1093 struct r8152 *tp;
1094 int status = urb->status;
1095
1096 agg = urb->context;
1097 if (!agg)
1098 return;
1099
1100 tp = agg->context;
1101 if (!tp)
1102 return;
1103
1104 netdev = tp->netdev;
1105 stats = &netdev->stats;
1106 if (status) {
1107 if (net_ratelimit())
1108 netdev_warn(netdev, "Tx status %d\n", status);
1109 stats->tx_errors += agg->skb_num;
1110 } else {
1111 stats->tx_packets += agg->skb_num;
1112 stats->tx_bytes += agg->skb_len;
1113 }
1114
1115 spin_lock(&tp->tx_lock);
1116 list_add_tail(&agg->list, &tp->tx_free);
1117 spin_unlock(&tp->tx_lock);
1118
1119 usb_autopm_put_interface_async(tp->intf);
1120
1121 if (!netif_carrier_ok(netdev))
1122 return;
1123
1124 if (!test_bit(WORK_ENABLE, &tp->flags))
1125 return;
1126
1127 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1128 return;
1129
1130 if (!skb_queue_empty(&tp->tx_queue))
1131 tasklet_schedule(&tp->tl);
1132 }
1133
1134 static void intr_callback(struct urb *urb)
1135 {
1136 struct r8152 *tp;
1137 __le16 *d;
1138 int status = urb->status;
1139 int res;
1140
1141 tp = urb->context;
1142 if (!tp)
1143 return;
1144
1145 if (!test_bit(WORK_ENABLE, &tp->flags))
1146 return;
1147
1148 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1149 return;
1150
1151 switch (status) {
1152 case 0: /* success */
1153 break;
1154 case -ECONNRESET: /* unlink */
1155 case -ESHUTDOWN:
1156 netif_device_detach(tp->netdev);
1157 case -ENOENT:
1158 case -EPROTO:
1159 netif_info(tp, intr, tp->netdev,
1160 "Stop submitting intr, status %d\n", status);
1161 return;
1162 case -EOVERFLOW:
1163 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1164 goto resubmit;
1165 /* -EPIPE: should clear the halt */
1166 default:
1167 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1168 goto resubmit;
1169 }
1170
1171 d = urb->transfer_buffer;
1172 if (INTR_LINK & __le16_to_cpu(d[0])) {
1173 if (!(tp->speed & LINK_STATUS)) {
1174 set_bit(RTL8152_LINK_CHG, &tp->flags);
1175 schedule_delayed_work(&tp->schedule, 0);
1176 }
1177 } else {
1178 if (tp->speed & LINK_STATUS) {
1179 set_bit(RTL8152_LINK_CHG, &tp->flags);
1180 schedule_delayed_work(&tp->schedule, 0);
1181 }
1182 }
1183
1184 resubmit:
1185 res = usb_submit_urb(urb, GFP_ATOMIC);
1186 if (res == -ENODEV) {
1187 set_bit(RTL8152_UNPLUG, &tp->flags);
1188 netif_device_detach(tp->netdev);
1189 } else if (res) {
1190 netif_err(tp, intr, tp->netdev,
1191 "can't resubmit intr, status %d\n", res);
1192 }
1193 }
1194
1195 static inline void *rx_agg_align(void *data)
1196 {
1197 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1198 }
1199
1200 static inline void *tx_agg_align(void *data)
1201 {
1202 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1203 }
1204
1205 static void free_all_mem(struct r8152 *tp)
1206 {
1207 int i;
1208
1209 for (i = 0; i < RTL8152_MAX_RX; i++) {
1210 usb_free_urb(tp->rx_info[i].urb);
1211 tp->rx_info[i].urb = NULL;
1212
1213 kfree(tp->rx_info[i].buffer);
1214 tp->rx_info[i].buffer = NULL;
1215 tp->rx_info[i].head = NULL;
1216 }
1217
1218 for (i = 0; i < RTL8152_MAX_TX; i++) {
1219 usb_free_urb(tp->tx_info[i].urb);
1220 tp->tx_info[i].urb = NULL;
1221
1222 kfree(tp->tx_info[i].buffer);
1223 tp->tx_info[i].buffer = NULL;
1224 tp->tx_info[i].head = NULL;
1225 }
1226
1227 usb_free_urb(tp->intr_urb);
1228 tp->intr_urb = NULL;
1229
1230 kfree(tp->intr_buff);
1231 tp->intr_buff = NULL;
1232 }
1233
1234 static int alloc_all_mem(struct r8152 *tp)
1235 {
1236 struct net_device *netdev = tp->netdev;
1237 struct usb_interface *intf = tp->intf;
1238 struct usb_host_interface *alt = intf->cur_altsetting;
1239 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1240 struct urb *urb;
1241 int node, i;
1242 u8 *buf;
1243
1244 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1245
1246 spin_lock_init(&tp->rx_lock);
1247 spin_lock_init(&tp->tx_lock);
1248 INIT_LIST_HEAD(&tp->tx_free);
1249 skb_queue_head_init(&tp->tx_queue);
1250
1251 for (i = 0; i < RTL8152_MAX_RX; i++) {
1252 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1253 if (!buf)
1254 goto err1;
1255
1256 if (buf != rx_agg_align(buf)) {
1257 kfree(buf);
1258 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1259 node);
1260 if (!buf)
1261 goto err1;
1262 }
1263
1264 urb = usb_alloc_urb(0, GFP_KERNEL);
1265 if (!urb) {
1266 kfree(buf);
1267 goto err1;
1268 }
1269
1270 INIT_LIST_HEAD(&tp->rx_info[i].list);
1271 tp->rx_info[i].context = tp;
1272 tp->rx_info[i].urb = urb;
1273 tp->rx_info[i].buffer = buf;
1274 tp->rx_info[i].head = rx_agg_align(buf);
1275 }
1276
1277 for (i = 0; i < RTL8152_MAX_TX; i++) {
1278 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1279 if (!buf)
1280 goto err1;
1281
1282 if (buf != tx_agg_align(buf)) {
1283 kfree(buf);
1284 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1285 node);
1286 if (!buf)
1287 goto err1;
1288 }
1289
1290 urb = usb_alloc_urb(0, GFP_KERNEL);
1291 if (!urb) {
1292 kfree(buf);
1293 goto err1;
1294 }
1295
1296 INIT_LIST_HEAD(&tp->tx_info[i].list);
1297 tp->tx_info[i].context = tp;
1298 tp->tx_info[i].urb = urb;
1299 tp->tx_info[i].buffer = buf;
1300 tp->tx_info[i].head = tx_agg_align(buf);
1301
1302 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1303 }
1304
1305 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1306 if (!tp->intr_urb)
1307 goto err1;
1308
1309 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1310 if (!tp->intr_buff)
1311 goto err1;
1312
1313 tp->intr_interval = (int)ep_intr->desc.bInterval;
1314 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1315 tp->intr_buff, INTBUFSIZE, intr_callback,
1316 tp, tp->intr_interval);
1317
1318 return 0;
1319
1320 err1:
1321 free_all_mem(tp);
1322 return -ENOMEM;
1323 }
1324
1325 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1326 {
1327 struct tx_agg *agg = NULL;
1328 unsigned long flags;
1329
1330 if (list_empty(&tp->tx_free))
1331 return NULL;
1332
1333 spin_lock_irqsave(&tp->tx_lock, flags);
1334 if (!list_empty(&tp->tx_free)) {
1335 struct list_head *cursor;
1336
1337 cursor = tp->tx_free.next;
1338 list_del_init(cursor);
1339 agg = list_entry(cursor, struct tx_agg, list);
1340 }
1341 spin_unlock_irqrestore(&tp->tx_lock, flags);
1342
1343 return agg;
1344 }
1345
1346 static inline __be16 get_protocol(struct sk_buff *skb)
1347 {
1348 __be16 protocol;
1349
1350 if (skb->protocol == htons(ETH_P_8021Q))
1351 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1352 else
1353 protocol = skb->protocol;
1354
1355 return protocol;
1356 }
1357
1358 /* r8152_csum_workaround()
1359 * The hw limites the value the transport offset. When the offset is out of the
1360 * range, calculate the checksum by sw.
1361 */
1362 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1363 struct sk_buff_head *list)
1364 {
1365 if (skb_shinfo(skb)->gso_size) {
1366 netdev_features_t features = tp->netdev->features;
1367 struct sk_buff_head seg_list;
1368 struct sk_buff *segs, *nskb;
1369
1370 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1371 segs = skb_gso_segment(skb, features);
1372 if (IS_ERR(segs) || !segs)
1373 goto drop;
1374
1375 __skb_queue_head_init(&seg_list);
1376
1377 do {
1378 nskb = segs;
1379 segs = segs->next;
1380 nskb->next = NULL;
1381 __skb_queue_tail(&seg_list, nskb);
1382 } while (segs);
1383
1384 skb_queue_splice(&seg_list, list);
1385 dev_kfree_skb(skb);
1386 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1387 if (skb_checksum_help(skb) < 0)
1388 goto drop;
1389
1390 __skb_queue_head(list, skb);
1391 } else {
1392 struct net_device_stats *stats;
1393
1394 drop:
1395 stats = &tp->netdev->stats;
1396 stats->tx_dropped++;
1397 dev_kfree_skb(skb);
1398 }
1399 }
1400
1401 /* msdn_giant_send_check()
1402 * According to the document of microsoft, the TCP Pseudo Header excludes the
1403 * packet length for IPv6 TCP large packets.
1404 */
1405 static int msdn_giant_send_check(struct sk_buff *skb)
1406 {
1407 const struct ipv6hdr *ipv6h;
1408 struct tcphdr *th;
1409 int ret;
1410
1411 ret = skb_cow_head(skb, 0);
1412 if (ret)
1413 return ret;
1414
1415 ipv6h = ipv6_hdr(skb);
1416 th = tcp_hdr(skb);
1417
1418 th->check = 0;
1419 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1420
1421 return ret;
1422 }
1423
1424 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1425 {
1426 if (vlan_tx_tag_present(skb)) {
1427 u32 opts2;
1428
1429 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1430 desc->opts2 |= cpu_to_le32(opts2);
1431 }
1432 }
1433
1434 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1435 {
1436 u32 opts2 = le32_to_cpu(desc->opts2);
1437
1438 if (opts2 & RX_VLAN_TAG)
1439 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1440 swab16(opts2 & 0xffff));
1441 }
1442
1443 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1444 struct sk_buff *skb, u32 len, u32 transport_offset)
1445 {
1446 u32 mss = skb_shinfo(skb)->gso_size;
1447 u32 opts1, opts2 = 0;
1448 int ret = TX_CSUM_SUCCESS;
1449
1450 WARN_ON_ONCE(len > TX_LEN_MAX);
1451
1452 opts1 = len | TX_FS | TX_LS;
1453
1454 if (mss) {
1455 if (transport_offset > GTTCPHO_MAX) {
1456 netif_warn(tp, tx_err, tp->netdev,
1457 "Invalid transport offset 0x%x for TSO\n",
1458 transport_offset);
1459 ret = TX_CSUM_TSO;
1460 goto unavailable;
1461 }
1462
1463 switch (get_protocol(skb)) {
1464 case htons(ETH_P_IP):
1465 opts1 |= GTSENDV4;
1466 break;
1467
1468 case htons(ETH_P_IPV6):
1469 if (msdn_giant_send_check(skb)) {
1470 ret = TX_CSUM_TSO;
1471 goto unavailable;
1472 }
1473 opts1 |= GTSENDV6;
1474 break;
1475
1476 default:
1477 WARN_ON_ONCE(1);
1478 break;
1479 }
1480
1481 opts1 |= transport_offset << GTTCPHO_SHIFT;
1482 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1483 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1484 u8 ip_protocol;
1485
1486 if (transport_offset > TCPHO_MAX) {
1487 netif_warn(tp, tx_err, tp->netdev,
1488 "Invalid transport offset 0x%x\n",
1489 transport_offset);
1490 ret = TX_CSUM_NONE;
1491 goto unavailable;
1492 }
1493
1494 switch (get_protocol(skb)) {
1495 case htons(ETH_P_IP):
1496 opts2 |= IPV4_CS;
1497 ip_protocol = ip_hdr(skb)->protocol;
1498 break;
1499
1500 case htons(ETH_P_IPV6):
1501 opts2 |= IPV6_CS;
1502 ip_protocol = ipv6_hdr(skb)->nexthdr;
1503 break;
1504
1505 default:
1506 ip_protocol = IPPROTO_RAW;
1507 break;
1508 }
1509
1510 if (ip_protocol == IPPROTO_TCP)
1511 opts2 |= TCP_CS;
1512 else if (ip_protocol == IPPROTO_UDP)
1513 opts2 |= UDP_CS;
1514 else
1515 WARN_ON_ONCE(1);
1516
1517 opts2 |= transport_offset << TCPHO_SHIFT;
1518 }
1519
1520 desc->opts2 = cpu_to_le32(opts2);
1521 desc->opts1 = cpu_to_le32(opts1);
1522
1523 unavailable:
1524 return ret;
1525 }
1526
1527 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1528 {
1529 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1530 int remain, ret;
1531 u8 *tx_data;
1532
1533 __skb_queue_head_init(&skb_head);
1534 spin_lock(&tx_queue->lock);
1535 skb_queue_splice_init(tx_queue, &skb_head);
1536 spin_unlock(&tx_queue->lock);
1537
1538 tx_data = agg->head;
1539 agg->skb_num = 0;
1540 agg->skb_len = 0;
1541 remain = agg_buf_sz;
1542
1543 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1544 struct tx_desc *tx_desc;
1545 struct sk_buff *skb;
1546 unsigned int len;
1547 u32 offset;
1548
1549 skb = __skb_dequeue(&skb_head);
1550 if (!skb)
1551 break;
1552
1553 len = skb->len + sizeof(*tx_desc);
1554
1555 if (len > remain) {
1556 __skb_queue_head(&skb_head, skb);
1557 break;
1558 }
1559
1560 tx_data = tx_agg_align(tx_data);
1561 tx_desc = (struct tx_desc *)tx_data;
1562
1563 offset = (u32)skb_transport_offset(skb);
1564
1565 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1566 r8152_csum_workaround(tp, skb, &skb_head);
1567 continue;
1568 }
1569
1570 rtl_tx_vlan_tag(tx_desc, skb);
1571
1572 tx_data += sizeof(*tx_desc);
1573
1574 len = skb->len;
1575 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1576 struct net_device_stats *stats = &tp->netdev->stats;
1577
1578 stats->tx_dropped++;
1579 dev_kfree_skb_any(skb);
1580 tx_data -= sizeof(*tx_desc);
1581 continue;
1582 }
1583
1584 tx_data += len;
1585 agg->skb_len += len;
1586 agg->skb_num++;
1587
1588 dev_kfree_skb_any(skb);
1589
1590 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1591 }
1592
1593 if (!skb_queue_empty(&skb_head)) {
1594 spin_lock(&tx_queue->lock);
1595 skb_queue_splice(&skb_head, tx_queue);
1596 spin_unlock(&tx_queue->lock);
1597 }
1598
1599 netif_tx_lock(tp->netdev);
1600
1601 if (netif_queue_stopped(tp->netdev) &&
1602 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1603 netif_wake_queue(tp->netdev);
1604
1605 netif_tx_unlock(tp->netdev);
1606
1607 ret = usb_autopm_get_interface_async(tp->intf);
1608 if (ret < 0)
1609 goto out_tx_fill;
1610
1611 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1612 agg->head, (int)(tx_data - (u8 *)agg->head),
1613 (usb_complete_t)write_bulk_callback, agg);
1614
1615 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1616 if (ret < 0)
1617 usb_autopm_put_interface_async(tp->intf);
1618
1619 out_tx_fill:
1620 return ret;
1621 }
1622
1623 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1624 {
1625 u8 checksum = CHECKSUM_NONE;
1626 u32 opts2, opts3;
1627
1628 if (tp->version == RTL_VER_01)
1629 goto return_result;
1630
1631 opts2 = le32_to_cpu(rx_desc->opts2);
1632 opts3 = le32_to_cpu(rx_desc->opts3);
1633
1634 if (opts2 & RD_IPV4_CS) {
1635 if (opts3 & IPF)
1636 checksum = CHECKSUM_NONE;
1637 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1638 checksum = CHECKSUM_NONE;
1639 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1640 checksum = CHECKSUM_NONE;
1641 else
1642 checksum = CHECKSUM_UNNECESSARY;
1643 } else if (RD_IPV6_CS) {
1644 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1645 checksum = CHECKSUM_UNNECESSARY;
1646 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1647 checksum = CHECKSUM_UNNECESSARY;
1648 }
1649
1650 return_result:
1651 return checksum;
1652 }
1653
1654 static void rx_bottom(struct r8152 *tp)
1655 {
1656 unsigned long flags;
1657 struct list_head *cursor, *next, rx_queue;
1658
1659 if (list_empty(&tp->rx_done))
1660 return;
1661
1662 INIT_LIST_HEAD(&rx_queue);
1663 spin_lock_irqsave(&tp->rx_lock, flags);
1664 list_splice_init(&tp->rx_done, &rx_queue);
1665 spin_unlock_irqrestore(&tp->rx_lock, flags);
1666
1667 list_for_each_safe(cursor, next, &rx_queue) {
1668 struct rx_desc *rx_desc;
1669 struct rx_agg *agg;
1670 int len_used = 0;
1671 struct urb *urb;
1672 u8 *rx_data;
1673
1674 list_del_init(cursor);
1675
1676 agg = list_entry(cursor, struct rx_agg, list);
1677 urb = agg->urb;
1678 if (urb->actual_length < ETH_ZLEN)
1679 goto submit;
1680
1681 rx_desc = agg->head;
1682 rx_data = agg->head;
1683 len_used += sizeof(struct rx_desc);
1684
1685 while (urb->actual_length > len_used) {
1686 struct net_device *netdev = tp->netdev;
1687 struct net_device_stats *stats = &netdev->stats;
1688 unsigned int pkt_len;
1689 struct sk_buff *skb;
1690
1691 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1692 if (pkt_len < ETH_ZLEN)
1693 break;
1694
1695 len_used += pkt_len;
1696 if (urb->actual_length < len_used)
1697 break;
1698
1699 pkt_len -= CRC_SIZE;
1700 rx_data += sizeof(struct rx_desc);
1701
1702 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1703 if (!skb) {
1704 stats->rx_dropped++;
1705 goto find_next_rx;
1706 }
1707
1708 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1709 memcpy(skb->data, rx_data, pkt_len);
1710 skb_put(skb, pkt_len);
1711 skb->protocol = eth_type_trans(skb, netdev);
1712 rtl_rx_vlan_tag(rx_desc, skb);
1713 netif_receive_skb(skb);
1714 stats->rx_packets++;
1715 stats->rx_bytes += pkt_len;
1716
1717 find_next_rx:
1718 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1719 rx_desc = (struct rx_desc *)rx_data;
1720 len_used = (int)(rx_data - (u8 *)agg->head);
1721 len_used += sizeof(struct rx_desc);
1722 }
1723
1724 submit:
1725 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1726 }
1727 }
1728
1729 static void tx_bottom(struct r8152 *tp)
1730 {
1731 int res;
1732
1733 do {
1734 struct tx_agg *agg;
1735
1736 if (skb_queue_empty(&tp->tx_queue))
1737 break;
1738
1739 agg = r8152_get_tx_agg(tp);
1740 if (!agg)
1741 break;
1742
1743 res = r8152_tx_agg_fill(tp, agg);
1744 if (res) {
1745 struct net_device *netdev = tp->netdev;
1746
1747 if (res == -ENODEV) {
1748 set_bit(RTL8152_UNPLUG, &tp->flags);
1749 netif_device_detach(netdev);
1750 } else {
1751 struct net_device_stats *stats = &netdev->stats;
1752 unsigned long flags;
1753
1754 netif_warn(tp, tx_err, netdev,
1755 "failed tx_urb %d\n", res);
1756 stats->tx_dropped += agg->skb_num;
1757
1758 spin_lock_irqsave(&tp->tx_lock, flags);
1759 list_add_tail(&agg->list, &tp->tx_free);
1760 spin_unlock_irqrestore(&tp->tx_lock, flags);
1761 }
1762 }
1763 } while (res == 0);
1764 }
1765
1766 static void bottom_half(unsigned long data)
1767 {
1768 struct r8152 *tp;
1769
1770 tp = (struct r8152 *)data;
1771
1772 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1773 return;
1774
1775 if (!test_bit(WORK_ENABLE, &tp->flags))
1776 return;
1777
1778 /* When link down, the driver would cancel all bulks. */
1779 /* This avoid the re-submitting bulk */
1780 if (!netif_carrier_ok(tp->netdev))
1781 return;
1782
1783 clear_bit(SCHEDULE_TASKLET, &tp->flags);
1784
1785 rx_bottom(tp);
1786 tx_bottom(tp);
1787 }
1788
1789 static
1790 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1791 {
1792 int ret;
1793
1794 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1795 agg->head, agg_buf_sz,
1796 (usb_complete_t)read_bulk_callback, agg);
1797
1798 ret = usb_submit_urb(agg->urb, mem_flags);
1799 if (ret == -ENODEV) {
1800 set_bit(RTL8152_UNPLUG, &tp->flags);
1801 netif_device_detach(tp->netdev);
1802 } else if (ret) {
1803 struct urb *urb = agg->urb;
1804 unsigned long flags;
1805
1806 urb->actual_length = 0;
1807 spin_lock_irqsave(&tp->rx_lock, flags);
1808 list_add_tail(&agg->list, &tp->rx_done);
1809 spin_unlock_irqrestore(&tp->rx_lock, flags);
1810 tasklet_schedule(&tp->tl);
1811 }
1812
1813 return ret;
1814 }
1815
1816 static void rtl_drop_queued_tx(struct r8152 *tp)
1817 {
1818 struct net_device_stats *stats = &tp->netdev->stats;
1819 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1820 struct sk_buff *skb;
1821
1822 if (skb_queue_empty(tx_queue))
1823 return;
1824
1825 __skb_queue_head_init(&skb_head);
1826 spin_lock_bh(&tx_queue->lock);
1827 skb_queue_splice_init(tx_queue, &skb_head);
1828 spin_unlock_bh(&tx_queue->lock);
1829
1830 while ((skb = __skb_dequeue(&skb_head))) {
1831 dev_kfree_skb(skb);
1832 stats->tx_dropped++;
1833 }
1834 }
1835
1836 static void rtl8152_tx_timeout(struct net_device *netdev)
1837 {
1838 struct r8152 *tp = netdev_priv(netdev);
1839 int i;
1840
1841 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1842 for (i = 0; i < RTL8152_MAX_TX; i++)
1843 usb_unlink_urb(tp->tx_info[i].urb);
1844 }
1845
1846 static void rtl8152_set_rx_mode(struct net_device *netdev)
1847 {
1848 struct r8152 *tp = netdev_priv(netdev);
1849
1850 if (tp->speed & LINK_STATUS) {
1851 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1852 schedule_delayed_work(&tp->schedule, 0);
1853 }
1854 }
1855
1856 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1857 {
1858 struct r8152 *tp = netdev_priv(netdev);
1859 u32 mc_filter[2]; /* Multicast hash filter */
1860 __le32 tmp[2];
1861 u32 ocp_data;
1862
1863 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1864 netif_stop_queue(netdev);
1865 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1866 ocp_data &= ~RCR_ACPT_ALL;
1867 ocp_data |= RCR_AB | RCR_APM;
1868
1869 if (netdev->flags & IFF_PROMISC) {
1870 /* Unconditionally log net taps. */
1871 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1872 ocp_data |= RCR_AM | RCR_AAP;
1873 mc_filter[1] = 0xffffffff;
1874 mc_filter[0] = 0xffffffff;
1875 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1876 (netdev->flags & IFF_ALLMULTI)) {
1877 /* Too many to filter perfectly -- accept all multicasts. */
1878 ocp_data |= RCR_AM;
1879 mc_filter[1] = 0xffffffff;
1880 mc_filter[0] = 0xffffffff;
1881 } else {
1882 struct netdev_hw_addr *ha;
1883
1884 mc_filter[1] = 0;
1885 mc_filter[0] = 0;
1886 netdev_for_each_mc_addr(ha, netdev) {
1887 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1888
1889 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1890 ocp_data |= RCR_AM;
1891 }
1892 }
1893
1894 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1895 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1896
1897 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1898 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1899 netif_wake_queue(netdev);
1900 }
1901
1902 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1903 struct net_device *netdev)
1904 {
1905 struct r8152 *tp = netdev_priv(netdev);
1906
1907 skb_tx_timestamp(skb);
1908
1909 skb_queue_tail(&tp->tx_queue, skb);
1910
1911 if (!list_empty(&tp->tx_free)) {
1912 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1913 set_bit(SCHEDULE_TASKLET, &tp->flags);
1914 schedule_delayed_work(&tp->schedule, 0);
1915 } else {
1916 usb_mark_last_busy(tp->udev);
1917 tasklet_schedule(&tp->tl);
1918 }
1919 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1920 netif_stop_queue(netdev);
1921 }
1922
1923 return NETDEV_TX_OK;
1924 }
1925
1926 static void r8152b_reset_packet_filter(struct r8152 *tp)
1927 {
1928 u32 ocp_data;
1929
1930 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1931 ocp_data &= ~FMC_FCR_MCU_EN;
1932 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1933 ocp_data |= FMC_FCR_MCU_EN;
1934 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1935 }
1936
1937 static void rtl8152_nic_reset(struct r8152 *tp)
1938 {
1939 int i;
1940
1941 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1942
1943 for (i = 0; i < 1000; i++) {
1944 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1945 break;
1946 usleep_range(100, 400);
1947 }
1948 }
1949
1950 static void set_tx_qlen(struct r8152 *tp)
1951 {
1952 struct net_device *netdev = tp->netdev;
1953
1954 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1955 sizeof(struct tx_desc));
1956 }
1957
1958 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1959 {
1960 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1961 }
1962
1963 static void rtl_set_eee_plus(struct r8152 *tp)
1964 {
1965 u32 ocp_data;
1966 u8 speed;
1967
1968 speed = rtl8152_get_speed(tp);
1969 if (speed & _10bps) {
1970 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1971 ocp_data |= EEEP_CR_EEEP_TX;
1972 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1973 } else {
1974 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1975 ocp_data &= ~EEEP_CR_EEEP_TX;
1976 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1977 }
1978 }
1979
1980 static void rxdy_gated_en(struct r8152 *tp, bool enable)
1981 {
1982 u32 ocp_data;
1983
1984 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1985 if (enable)
1986 ocp_data |= RXDY_GATED_EN;
1987 else
1988 ocp_data &= ~RXDY_GATED_EN;
1989 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1990 }
1991
1992 static int rtl_start_rx(struct r8152 *tp)
1993 {
1994 int i, ret = 0;
1995
1996 INIT_LIST_HEAD(&tp->rx_done);
1997 for (i = 0; i < RTL8152_MAX_RX; i++) {
1998 INIT_LIST_HEAD(&tp->rx_info[i].list);
1999 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2000 if (ret)
2001 break;
2002 }
2003
2004 return ret;
2005 }
2006
2007 static int rtl_stop_rx(struct r8152 *tp)
2008 {
2009 int i;
2010
2011 for (i = 0; i < RTL8152_MAX_RX; i++)
2012 usb_kill_urb(tp->rx_info[i].urb);
2013
2014 return 0;
2015 }
2016
2017 static int rtl_enable(struct r8152 *tp)
2018 {
2019 u32 ocp_data;
2020
2021 r8152b_reset_packet_filter(tp);
2022
2023 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2024 ocp_data |= CR_RE | CR_TE;
2025 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2026
2027 rxdy_gated_en(tp, false);
2028
2029 return rtl_start_rx(tp);
2030 }
2031
2032 static int rtl8152_enable(struct r8152 *tp)
2033 {
2034 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2035 return -ENODEV;
2036
2037 set_tx_qlen(tp);
2038 rtl_set_eee_plus(tp);
2039
2040 return rtl_enable(tp);
2041 }
2042
2043 static void r8153_set_rx_agg(struct r8152 *tp)
2044 {
2045 u8 speed;
2046
2047 speed = rtl8152_get_speed(tp);
2048 if (speed & _1000bps) {
2049 if (tp->udev->speed == USB_SPEED_SUPER) {
2050 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2051 RX_THR_SUPPER);
2052 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2053 EARLY_AGG_SUPPER);
2054 } else {
2055 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2056 RX_THR_HIGH);
2057 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2058 EARLY_AGG_HIGH);
2059 }
2060 } else {
2061 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2062 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2063 EARLY_AGG_SLOW);
2064 }
2065 }
2066
2067 static int rtl8153_enable(struct r8152 *tp)
2068 {
2069 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2070 return -ENODEV;
2071
2072 set_tx_qlen(tp);
2073 rtl_set_eee_plus(tp);
2074 r8153_set_rx_agg(tp);
2075
2076 return rtl_enable(tp);
2077 }
2078
2079 static void rtl_disable(struct r8152 *tp)
2080 {
2081 u32 ocp_data;
2082 int i;
2083
2084 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2085 rtl_drop_queued_tx(tp);
2086 return;
2087 }
2088
2089 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2090 ocp_data &= ~RCR_ACPT_ALL;
2091 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2092
2093 rtl_drop_queued_tx(tp);
2094
2095 for (i = 0; i < RTL8152_MAX_TX; i++)
2096 usb_kill_urb(tp->tx_info[i].urb);
2097
2098 rxdy_gated_en(tp, true);
2099
2100 for (i = 0; i < 1000; i++) {
2101 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2102 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2103 break;
2104 usleep_range(1000, 2000);
2105 }
2106
2107 for (i = 0; i < 1000; i++) {
2108 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2109 break;
2110 usleep_range(1000, 2000);
2111 }
2112
2113 rtl_stop_rx(tp);
2114
2115 rtl8152_nic_reset(tp);
2116 }
2117
2118 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2119 {
2120 u32 ocp_data;
2121
2122 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2123 if (enable)
2124 ocp_data |= POWER_CUT;
2125 else
2126 ocp_data &= ~POWER_CUT;
2127 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2128
2129 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2130 ocp_data &= ~RESUME_INDICATE;
2131 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2132 }
2133
2134 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2135 {
2136 u32 ocp_data;
2137
2138 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2139 if (enable)
2140 ocp_data |= CPCR_RX_VLAN;
2141 else
2142 ocp_data &= ~CPCR_RX_VLAN;
2143 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2144 }
2145
2146 static int rtl8152_set_features(struct net_device *dev,
2147 netdev_features_t features)
2148 {
2149 netdev_features_t changed = features ^ dev->features;
2150 struct r8152 *tp = netdev_priv(dev);
2151 int ret;
2152
2153 ret = usb_autopm_get_interface(tp->intf);
2154 if (ret < 0)
2155 goto out;
2156
2157 mutex_lock(&tp->control);
2158
2159 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2160 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2161 rtl_rx_vlan_en(tp, true);
2162 else
2163 rtl_rx_vlan_en(tp, false);
2164 }
2165
2166 mutex_unlock(&tp->control);
2167
2168 usb_autopm_put_interface(tp->intf);
2169
2170 out:
2171 return ret;
2172 }
2173
2174 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2175
2176 static u32 __rtl_get_wol(struct r8152 *tp)
2177 {
2178 u32 ocp_data;
2179 u32 wolopts = 0;
2180
2181 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2182 if (!(ocp_data & LAN_WAKE_EN))
2183 return 0;
2184
2185 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2186 if (ocp_data & LINK_ON_WAKE_EN)
2187 wolopts |= WAKE_PHY;
2188
2189 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2190 if (ocp_data & UWF_EN)
2191 wolopts |= WAKE_UCAST;
2192 if (ocp_data & BWF_EN)
2193 wolopts |= WAKE_BCAST;
2194 if (ocp_data & MWF_EN)
2195 wolopts |= WAKE_MCAST;
2196
2197 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2198 if (ocp_data & MAGIC_EN)
2199 wolopts |= WAKE_MAGIC;
2200
2201 return wolopts;
2202 }
2203
2204 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2205 {
2206 u32 ocp_data;
2207
2208 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2209
2210 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2211 ocp_data &= ~LINK_ON_WAKE_EN;
2212 if (wolopts & WAKE_PHY)
2213 ocp_data |= LINK_ON_WAKE_EN;
2214 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2215
2216 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2217 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2218 if (wolopts & WAKE_UCAST)
2219 ocp_data |= UWF_EN;
2220 if (wolopts & WAKE_BCAST)
2221 ocp_data |= BWF_EN;
2222 if (wolopts & WAKE_MCAST)
2223 ocp_data |= MWF_EN;
2224 if (wolopts & WAKE_ANY)
2225 ocp_data |= LAN_WAKE_EN;
2226 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2227
2228 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2229
2230 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2231 ocp_data &= ~MAGIC_EN;
2232 if (wolopts & WAKE_MAGIC)
2233 ocp_data |= MAGIC_EN;
2234 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2235
2236 if (wolopts & WAKE_ANY)
2237 device_set_wakeup_enable(&tp->udev->dev, true);
2238 else
2239 device_set_wakeup_enable(&tp->udev->dev, false);
2240 }
2241
2242 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2243 {
2244 if (enable) {
2245 u32 ocp_data;
2246
2247 __rtl_set_wol(tp, WAKE_ANY);
2248
2249 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2250
2251 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2252 ocp_data |= LINK_OFF_WAKE_EN;
2253 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2254
2255 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2256 } else {
2257 __rtl_set_wol(tp, tp->saved_wolopts);
2258 }
2259 }
2260
2261 static void rtl_phy_reset(struct r8152 *tp)
2262 {
2263 u16 data;
2264 int i;
2265
2266 clear_bit(PHY_RESET, &tp->flags);
2267
2268 data = r8152_mdio_read(tp, MII_BMCR);
2269
2270 /* don't reset again before the previous one complete */
2271 if (data & BMCR_RESET)
2272 return;
2273
2274 data |= BMCR_RESET;
2275 r8152_mdio_write(tp, MII_BMCR, data);
2276
2277 for (i = 0; i < 50; i++) {
2278 msleep(20);
2279 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2280 break;
2281 }
2282 }
2283
2284 static void r8153_teredo_off(struct r8152 *tp)
2285 {
2286 u32 ocp_data;
2287
2288 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2289 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2290 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2291
2292 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2293 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2294 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2295 }
2296
2297 static void r8152b_disable_aldps(struct r8152 *tp)
2298 {
2299 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2300 msleep(20);
2301 }
2302
2303 static inline void r8152b_enable_aldps(struct r8152 *tp)
2304 {
2305 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2306 LINKENA | DIS_SDSAVE);
2307 }
2308
2309 static void rtl8152_disable(struct r8152 *tp)
2310 {
2311 r8152b_disable_aldps(tp);
2312 rtl_disable(tp);
2313 r8152b_enable_aldps(tp);
2314 }
2315
2316 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2317 {
2318 u16 data;
2319
2320 data = r8152_mdio_read(tp, MII_BMCR);
2321 if (data & BMCR_PDOWN) {
2322 data &= ~BMCR_PDOWN;
2323 r8152_mdio_write(tp, MII_BMCR, data);
2324 }
2325
2326 set_bit(PHY_RESET, &tp->flags);
2327 }
2328
2329 static void r8152b_exit_oob(struct r8152 *tp)
2330 {
2331 u32 ocp_data;
2332 int i;
2333
2334 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2335 ocp_data &= ~RCR_ACPT_ALL;
2336 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2337
2338 rxdy_gated_en(tp, true);
2339 r8153_teredo_off(tp);
2340 r8152b_hw_phy_cfg(tp);
2341
2342 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2343 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2344
2345 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2346 ocp_data &= ~NOW_IS_OOB;
2347 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2348
2349 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2350 ocp_data &= ~MCU_BORW_EN;
2351 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2352
2353 for (i = 0; i < 1000; i++) {
2354 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2355 if (ocp_data & LINK_LIST_READY)
2356 break;
2357 usleep_range(1000, 2000);
2358 }
2359
2360 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2361 ocp_data |= RE_INIT_LL;
2362 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2363
2364 for (i = 0; i < 1000; i++) {
2365 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2366 if (ocp_data & LINK_LIST_READY)
2367 break;
2368 usleep_range(1000, 2000);
2369 }
2370
2371 rtl8152_nic_reset(tp);
2372
2373 /* rx share fifo credit full threshold */
2374 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2375
2376 if (tp->udev->speed == USB_SPEED_FULL ||
2377 tp->udev->speed == USB_SPEED_LOW) {
2378 /* rx share fifo credit near full threshold */
2379 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2380 RXFIFO_THR2_FULL);
2381 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2382 RXFIFO_THR3_FULL);
2383 } else {
2384 /* rx share fifo credit near full threshold */
2385 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2386 RXFIFO_THR2_HIGH);
2387 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2388 RXFIFO_THR3_HIGH);
2389 }
2390
2391 /* TX share fifo free credit full threshold */
2392 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2393
2394 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2395 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2396 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2397 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2398
2399 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2400
2401 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2402
2403 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2404 ocp_data |= TCR0_AUTO_FIFO;
2405 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2406 }
2407
2408 static void r8152b_enter_oob(struct r8152 *tp)
2409 {
2410 u32 ocp_data;
2411 int i;
2412
2413 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2414 ocp_data &= ~NOW_IS_OOB;
2415 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2416
2417 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2418 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2419 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2420
2421 rtl_disable(tp);
2422
2423 for (i = 0; i < 1000; i++) {
2424 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2425 if (ocp_data & LINK_LIST_READY)
2426 break;
2427 usleep_range(1000, 2000);
2428 }
2429
2430 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2431 ocp_data |= RE_INIT_LL;
2432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2433
2434 for (i = 0; i < 1000; i++) {
2435 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2436 if (ocp_data & LINK_LIST_READY)
2437 break;
2438 usleep_range(1000, 2000);
2439 }
2440
2441 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2442
2443 rtl_rx_vlan_en(tp, true);
2444
2445 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2446 ocp_data |= ALDPS_PROXY_MODE;
2447 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2448
2449 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2450 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2451 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2452
2453 rxdy_gated_en(tp, false);
2454
2455 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2456 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2457 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2458 }
2459
2460 static void r8153_hw_phy_cfg(struct r8152 *tp)
2461 {
2462 u32 ocp_data;
2463 u16 data;
2464
2465 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2466 data = r8152_mdio_read(tp, MII_BMCR);
2467 if (data & BMCR_PDOWN) {
2468 data &= ~BMCR_PDOWN;
2469 r8152_mdio_write(tp, MII_BMCR, data);
2470 }
2471
2472 if (tp->version == RTL_VER_03) {
2473 data = ocp_reg_read(tp, OCP_EEE_CFG);
2474 data &= ~CTAP_SHORT_EN;
2475 ocp_reg_write(tp, OCP_EEE_CFG, data);
2476 }
2477
2478 data = ocp_reg_read(tp, OCP_POWER_CFG);
2479 data |= EEE_CLKDIV_EN;
2480 ocp_reg_write(tp, OCP_POWER_CFG, data);
2481
2482 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2483 data |= EN_10M_BGOFF;
2484 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2485 data = ocp_reg_read(tp, OCP_POWER_CFG);
2486 data |= EN_10M_PLLOFF;
2487 ocp_reg_write(tp, OCP_POWER_CFG, data);
2488 data = sram_read(tp, SRAM_IMPEDANCE);
2489 data &= ~RX_DRIVING_MASK;
2490 sram_write(tp, SRAM_IMPEDANCE, data);
2491
2492 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2493 ocp_data |= PFM_PWM_SWITCH;
2494 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2495
2496 data = sram_read(tp, SRAM_LPF_CFG);
2497 data |= LPF_AUTO_TUNE;
2498 sram_write(tp, SRAM_LPF_CFG, data);
2499
2500 data = sram_read(tp, SRAM_10M_AMP1);
2501 data |= GDAC_IB_UPALL;
2502 sram_write(tp, SRAM_10M_AMP1, data);
2503 data = sram_read(tp, SRAM_10M_AMP2);
2504 data |= AMP_DN;
2505 sram_write(tp, SRAM_10M_AMP2, data);
2506
2507 set_bit(PHY_RESET, &tp->flags);
2508 }
2509
2510 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2511 {
2512 u8 u1u2[8];
2513
2514 if (enable)
2515 memset(u1u2, 0xff, sizeof(u1u2));
2516 else
2517 memset(u1u2, 0x00, sizeof(u1u2));
2518
2519 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2520 }
2521
2522 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2523 {
2524 u32 ocp_data;
2525
2526 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2527 if (enable)
2528 ocp_data |= U2P3_ENABLE;
2529 else
2530 ocp_data &= ~U2P3_ENABLE;
2531 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2532 }
2533
2534 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2535 {
2536 u32 ocp_data;
2537
2538 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2539 if (enable)
2540 ocp_data |= PWR_EN | PHASE2_EN;
2541 else
2542 ocp_data &= ~(PWR_EN | PHASE2_EN);
2543 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2544
2545 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2546 ocp_data &= ~PCUT_STATUS;
2547 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2548 }
2549
2550 static void r8153_first_init(struct r8152 *tp)
2551 {
2552 u32 ocp_data;
2553 int i;
2554
2555 rxdy_gated_en(tp, true);
2556 r8153_teredo_off(tp);
2557
2558 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2559 ocp_data &= ~RCR_ACPT_ALL;
2560 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2561
2562 r8153_hw_phy_cfg(tp);
2563
2564 rtl8152_nic_reset(tp);
2565
2566 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2567 ocp_data &= ~NOW_IS_OOB;
2568 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2569
2570 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2571 ocp_data &= ~MCU_BORW_EN;
2572 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2573
2574 for (i = 0; i < 1000; i++) {
2575 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2576 if (ocp_data & LINK_LIST_READY)
2577 break;
2578 usleep_range(1000, 2000);
2579 }
2580
2581 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2582 ocp_data |= RE_INIT_LL;
2583 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2584
2585 for (i = 0; i < 1000; i++) {
2586 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2587 if (ocp_data & LINK_LIST_READY)
2588 break;
2589 usleep_range(1000, 2000);
2590 }
2591
2592 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2593
2594 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2595 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2596
2597 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2598 ocp_data |= TCR0_AUTO_FIFO;
2599 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2600
2601 rtl8152_nic_reset(tp);
2602
2603 /* rx share fifo credit full threshold */
2604 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2606 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2607 /* TX share fifo free credit full threshold */
2608 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2609
2610 /* rx aggregation */
2611 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2612 ocp_data &= ~RX_AGG_DISABLE;
2613 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2614 }
2615
2616 static void r8153_enter_oob(struct r8152 *tp)
2617 {
2618 u32 ocp_data;
2619 int i;
2620
2621 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2622 ocp_data &= ~NOW_IS_OOB;
2623 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2624
2625 rtl_disable(tp);
2626
2627 for (i = 0; i < 1000; i++) {
2628 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2629 if (ocp_data & LINK_LIST_READY)
2630 break;
2631 usleep_range(1000, 2000);
2632 }
2633
2634 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2635 ocp_data |= RE_INIT_LL;
2636 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2637
2638 for (i = 0; i < 1000; i++) {
2639 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2640 if (ocp_data & LINK_LIST_READY)
2641 break;
2642 usleep_range(1000, 2000);
2643 }
2644
2645 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2646
2647 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2648 ocp_data &= ~TEREDO_WAKE_MASK;
2649 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2650
2651 rtl_rx_vlan_en(tp, true);
2652
2653 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2654 ocp_data |= ALDPS_PROXY_MODE;
2655 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2656
2657 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2658 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2659 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2660
2661 rxdy_gated_en(tp, false);
2662
2663 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2664 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2665 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2666 }
2667
2668 static void r8153_disable_aldps(struct r8152 *tp)
2669 {
2670 u16 data;
2671
2672 data = ocp_reg_read(tp, OCP_POWER_CFG);
2673 data &= ~EN_ALDPS;
2674 ocp_reg_write(tp, OCP_POWER_CFG, data);
2675 msleep(20);
2676 }
2677
2678 static void r8153_enable_aldps(struct r8152 *tp)
2679 {
2680 u16 data;
2681
2682 data = ocp_reg_read(tp, OCP_POWER_CFG);
2683 data |= EN_ALDPS;
2684 ocp_reg_write(tp, OCP_POWER_CFG, data);
2685 }
2686
2687 static void rtl8153_disable(struct r8152 *tp)
2688 {
2689 r8153_disable_aldps(tp);
2690 rtl_disable(tp);
2691 r8153_enable_aldps(tp);
2692 }
2693
2694 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2695 {
2696 u16 bmcr, anar, gbcr;
2697 int ret = 0;
2698
2699 cancel_delayed_work_sync(&tp->schedule);
2700 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2701 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2702 ADVERTISE_100HALF | ADVERTISE_100FULL);
2703 if (tp->mii.supports_gmii) {
2704 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2705 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2706 } else {
2707 gbcr = 0;
2708 }
2709
2710 if (autoneg == AUTONEG_DISABLE) {
2711 if (speed == SPEED_10) {
2712 bmcr = 0;
2713 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2714 } else if (speed == SPEED_100) {
2715 bmcr = BMCR_SPEED100;
2716 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2717 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2718 bmcr = BMCR_SPEED1000;
2719 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2720 } else {
2721 ret = -EINVAL;
2722 goto out;
2723 }
2724
2725 if (duplex == DUPLEX_FULL)
2726 bmcr |= BMCR_FULLDPLX;
2727 } else {
2728 if (speed == SPEED_10) {
2729 if (duplex == DUPLEX_FULL)
2730 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2731 else
2732 anar |= ADVERTISE_10HALF;
2733 } else if (speed == SPEED_100) {
2734 if (duplex == DUPLEX_FULL) {
2735 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2736 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2737 } else {
2738 anar |= ADVERTISE_10HALF;
2739 anar |= ADVERTISE_100HALF;
2740 }
2741 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2742 if (duplex == DUPLEX_FULL) {
2743 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2744 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2745 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2746 } else {
2747 anar |= ADVERTISE_10HALF;
2748 anar |= ADVERTISE_100HALF;
2749 gbcr |= ADVERTISE_1000HALF;
2750 }
2751 } else {
2752 ret = -EINVAL;
2753 goto out;
2754 }
2755
2756 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2757 }
2758
2759 if (test_bit(PHY_RESET, &tp->flags))
2760 bmcr |= BMCR_RESET;
2761
2762 if (tp->mii.supports_gmii)
2763 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2764
2765 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2766 r8152_mdio_write(tp, MII_BMCR, bmcr);
2767
2768 if (test_bit(PHY_RESET, &tp->flags)) {
2769 int i;
2770
2771 clear_bit(PHY_RESET, &tp->flags);
2772 for (i = 0; i < 50; i++) {
2773 msleep(20);
2774 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2775 break;
2776 }
2777 }
2778
2779 out:
2780
2781 return ret;
2782 }
2783
2784 static void rtl8152_up(struct r8152 *tp)
2785 {
2786 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2787 return;
2788
2789 r8152b_disable_aldps(tp);
2790 r8152b_exit_oob(tp);
2791 r8152b_enable_aldps(tp);
2792 }
2793
2794 static void rtl8152_down(struct r8152 *tp)
2795 {
2796 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2797 rtl_drop_queued_tx(tp);
2798 return;
2799 }
2800
2801 r8152_power_cut_en(tp, false);
2802 r8152b_disable_aldps(tp);
2803 r8152b_enter_oob(tp);
2804 r8152b_enable_aldps(tp);
2805 }
2806
2807 static void rtl8153_up(struct r8152 *tp)
2808 {
2809 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2810 return;
2811
2812 r8153_disable_aldps(tp);
2813 r8153_first_init(tp);
2814 r8153_enable_aldps(tp);
2815 }
2816
2817 static void rtl8153_down(struct r8152 *tp)
2818 {
2819 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2820 rtl_drop_queued_tx(tp);
2821 return;
2822 }
2823
2824 r8153_u1u2en(tp, false);
2825 r8153_power_cut_en(tp, false);
2826 r8153_disable_aldps(tp);
2827 r8153_enter_oob(tp);
2828 r8153_enable_aldps(tp);
2829 }
2830
2831 static void set_carrier(struct r8152 *tp)
2832 {
2833 struct net_device *netdev = tp->netdev;
2834 u8 speed;
2835
2836 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2837 speed = rtl8152_get_speed(tp);
2838
2839 if (speed & LINK_STATUS) {
2840 if (!(tp->speed & LINK_STATUS)) {
2841 tp->rtl_ops.enable(tp);
2842 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2843 netif_carrier_on(netdev);
2844 }
2845 } else {
2846 if (tp->speed & LINK_STATUS) {
2847 netif_carrier_off(netdev);
2848 tasklet_disable(&tp->tl);
2849 tp->rtl_ops.disable(tp);
2850 tasklet_enable(&tp->tl);
2851 }
2852 }
2853 tp->speed = speed;
2854 }
2855
2856 static void rtl_work_func_t(struct work_struct *work)
2857 {
2858 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2859
2860 /* If the device is unplugged or !netif_running(), the workqueue
2861 * doesn't need to wake the device, and could return directly.
2862 */
2863 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2864 return;
2865
2866 if (usb_autopm_get_interface(tp->intf) < 0)
2867 return;
2868
2869 if (!test_bit(WORK_ENABLE, &tp->flags))
2870 goto out1;
2871
2872 if (!mutex_trylock(&tp->control)) {
2873 schedule_delayed_work(&tp->schedule, 0);
2874 goto out1;
2875 }
2876
2877 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2878 set_carrier(tp);
2879
2880 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2881 _rtl8152_set_rx_mode(tp->netdev);
2882
2883 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2884 (tp->speed & LINK_STATUS)) {
2885 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2886 tasklet_schedule(&tp->tl);
2887 }
2888
2889 if (test_bit(PHY_RESET, &tp->flags))
2890 rtl_phy_reset(tp);
2891
2892 mutex_unlock(&tp->control);
2893
2894 out1:
2895 usb_autopm_put_interface(tp->intf);
2896 }
2897
2898 static int rtl8152_open(struct net_device *netdev)
2899 {
2900 struct r8152 *tp = netdev_priv(netdev);
2901 int res = 0;
2902
2903 res = alloc_all_mem(tp);
2904 if (res)
2905 goto out;
2906
2907 /* set speed to 0 to avoid autoresume try to submit rx */
2908 tp->speed = 0;
2909
2910 res = usb_autopm_get_interface(tp->intf);
2911 if (res < 0) {
2912 free_all_mem(tp);
2913 goto out;
2914 }
2915
2916 mutex_lock(&tp->control);
2917
2918 /* The WORK_ENABLE may be set when autoresume occurs */
2919 if (test_bit(WORK_ENABLE, &tp->flags)) {
2920 clear_bit(WORK_ENABLE, &tp->flags);
2921 usb_kill_urb(tp->intr_urb);
2922 cancel_delayed_work_sync(&tp->schedule);
2923
2924 /* disable the tx/rx, if the workqueue has enabled them. */
2925 if (tp->speed & LINK_STATUS)
2926 tp->rtl_ops.disable(tp);
2927 }
2928
2929 tp->rtl_ops.up(tp);
2930
2931 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2932 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2933 DUPLEX_FULL);
2934 tp->speed = 0;
2935 netif_carrier_off(netdev);
2936 netif_start_queue(netdev);
2937 set_bit(WORK_ENABLE, &tp->flags);
2938
2939 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2940 if (res) {
2941 if (res == -ENODEV)
2942 netif_device_detach(tp->netdev);
2943 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2944 res);
2945 free_all_mem(tp);
2946 } else {
2947 tasklet_enable(&tp->tl);
2948 }
2949
2950 mutex_unlock(&tp->control);
2951
2952 usb_autopm_put_interface(tp->intf);
2953
2954 out:
2955 return res;
2956 }
2957
2958 static int rtl8152_close(struct net_device *netdev)
2959 {
2960 struct r8152 *tp = netdev_priv(netdev);
2961 int res = 0;
2962
2963 tasklet_disable(&tp->tl);
2964 clear_bit(WORK_ENABLE, &tp->flags);
2965 usb_kill_urb(tp->intr_urb);
2966 cancel_delayed_work_sync(&tp->schedule);
2967 netif_stop_queue(netdev);
2968
2969 res = usb_autopm_get_interface(tp->intf);
2970 if (res < 0) {
2971 rtl_drop_queued_tx(tp);
2972 } else {
2973 mutex_lock(&tp->control);
2974
2975 /* The autosuspend may have been enabled and wouldn't
2976 * be disable when autoresume occurs, because the
2977 * netif_running() would be false.
2978 */
2979 rtl_runtime_suspend_enable(tp, false);
2980
2981 tp->rtl_ops.down(tp);
2982
2983 mutex_unlock(&tp->control);
2984
2985 usb_autopm_put_interface(tp->intf);
2986 }
2987
2988 free_all_mem(tp);
2989
2990 return res;
2991 }
2992
2993 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2994 {
2995 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2996 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2997 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2998 }
2999
3000 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3001 {
3002 u16 data;
3003
3004 r8152_mmd_indirect(tp, dev, reg);
3005 data = ocp_reg_read(tp, OCP_EEE_DATA);
3006 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3007
3008 return data;
3009 }
3010
3011 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3012 {
3013 r8152_mmd_indirect(tp, dev, reg);
3014 ocp_reg_write(tp, OCP_EEE_DATA, data);
3015 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3016 }
3017
3018 static void r8152_eee_en(struct r8152 *tp, bool enable)
3019 {
3020 u16 config1, config2, config3;
3021 u32 ocp_data;
3022
3023 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3024 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3025 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3026 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3027
3028 if (enable) {
3029 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3030 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3031 config1 |= sd_rise_time(1);
3032 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3033 config3 |= fast_snr(42);
3034 } else {
3035 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3036 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3037 RX_QUIET_EN);
3038 config1 |= sd_rise_time(7);
3039 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3040 config3 |= fast_snr(511);
3041 }
3042
3043 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3044 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3045 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3046 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3047 }
3048
3049 static void r8152b_enable_eee(struct r8152 *tp)
3050 {
3051 r8152_eee_en(tp, true);
3052 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3053 }
3054
3055 static void r8153_eee_en(struct r8152 *tp, bool enable)
3056 {
3057 u32 ocp_data;
3058 u16 config;
3059
3060 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3061 config = ocp_reg_read(tp, OCP_EEE_CFG);
3062
3063 if (enable) {
3064 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3065 config |= EEE10_EN;
3066 } else {
3067 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3068 config &= ~EEE10_EN;
3069 }
3070
3071 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3072 ocp_reg_write(tp, OCP_EEE_CFG, config);
3073 }
3074
3075 static void r8153_enable_eee(struct r8152 *tp)
3076 {
3077 r8153_eee_en(tp, true);
3078 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3079 }
3080
3081 static void r8152b_enable_fc(struct r8152 *tp)
3082 {
3083 u16 anar;
3084
3085 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3086 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3087 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3088 }
3089
3090 static void rtl_tally_reset(struct r8152 *tp)
3091 {
3092 u32 ocp_data;
3093
3094 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3095 ocp_data |= TALLY_RESET;
3096 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3097 }
3098
3099 static void r8152b_init(struct r8152 *tp)
3100 {
3101 u32 ocp_data;
3102
3103 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3104 return;
3105
3106 r8152b_disable_aldps(tp);
3107
3108 if (tp->version == RTL_VER_01) {
3109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3110 ocp_data &= ~LED_MODE_MASK;
3111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3112 }
3113
3114 r8152_power_cut_en(tp, false);
3115
3116 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3117 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3119 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3120 ocp_data &= ~MCU_CLK_RATIO_MASK;
3121 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3122 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3123 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3124 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3125 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3126
3127 r8152b_enable_eee(tp);
3128 r8152b_enable_aldps(tp);
3129 r8152b_enable_fc(tp);
3130 rtl_tally_reset(tp);
3131
3132 /* enable rx aggregation */
3133 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3134 ocp_data &= ~RX_AGG_DISABLE;
3135 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3136 }
3137
3138 static void r8153_init(struct r8152 *tp)
3139 {
3140 u32 ocp_data;
3141 int i;
3142
3143 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3144 return;
3145
3146 r8153_disable_aldps(tp);
3147 r8153_u1u2en(tp, false);
3148
3149 for (i = 0; i < 500; i++) {
3150 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3151 AUTOLOAD_DONE)
3152 break;
3153 msleep(20);
3154 }
3155
3156 for (i = 0; i < 500; i++) {
3157 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3158 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3159 break;
3160 msleep(20);
3161 }
3162
3163 r8153_u2p3en(tp, false);
3164
3165 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3166 ocp_data &= ~TIMER11_EN;
3167 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3168
3169 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3170 ocp_data &= ~LED_MODE_MASK;
3171 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3172
3173 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3174 ocp_data &= ~LPM_TIMER_MASK;
3175 if (tp->udev->speed == USB_SPEED_SUPER)
3176 ocp_data |= LPM_TIMER_500US;
3177 else
3178 ocp_data |= LPM_TIMER_500MS;
3179 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3180
3181 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3182 ocp_data &= ~SEN_VAL_MASK;
3183 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3184 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3185
3186 r8153_power_cut_en(tp, false);
3187 r8153_u1u2en(tp, true);
3188
3189 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3190 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3191 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3192 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3193 U1U2_SPDWN_EN | L1_SPDWN_EN);
3194 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3195 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3196 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3197 EEE_SPDWN_EN);
3198
3199 r8153_enable_eee(tp);
3200 r8153_enable_aldps(tp);
3201 r8152b_enable_fc(tp);
3202 rtl_tally_reset(tp);
3203 }
3204
3205 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3206 {
3207 struct r8152 *tp = usb_get_intfdata(intf);
3208 struct net_device *netdev = tp->netdev;
3209 int ret = 0;
3210
3211 mutex_lock(&tp->control);
3212
3213 if (PMSG_IS_AUTO(message)) {
3214 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3215 ret = -EBUSY;
3216 goto out1;
3217 }
3218
3219 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3220 } else {
3221 netif_device_detach(netdev);
3222 }
3223
3224 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3225 clear_bit(WORK_ENABLE, &tp->flags);
3226 usb_kill_urb(tp->intr_urb);
3227 tasklet_disable(&tp->tl);
3228 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3229 rtl_stop_rx(tp);
3230 rtl_runtime_suspend_enable(tp, true);
3231 } else {
3232 cancel_delayed_work_sync(&tp->schedule);
3233 tp->rtl_ops.down(tp);
3234 }
3235 tasklet_enable(&tp->tl);
3236 }
3237 out1:
3238 mutex_unlock(&tp->control);
3239
3240 return ret;
3241 }
3242
3243 static int rtl8152_resume(struct usb_interface *intf)
3244 {
3245 struct r8152 *tp = usb_get_intfdata(intf);
3246
3247 mutex_lock(&tp->control);
3248
3249 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3250 tp->rtl_ops.init(tp);
3251 netif_device_attach(tp->netdev);
3252 }
3253
3254 if (netif_running(tp->netdev)) {
3255 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3256 rtl_runtime_suspend_enable(tp, false);
3257 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3258 set_bit(WORK_ENABLE, &tp->flags);
3259 if (tp->speed & LINK_STATUS)
3260 rtl_start_rx(tp);
3261 } else {
3262 tp->rtl_ops.up(tp);
3263 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3264 tp->mii.supports_gmii ?
3265 SPEED_1000 : SPEED_100,
3266 DUPLEX_FULL);
3267 tp->speed = 0;
3268 netif_carrier_off(tp->netdev);
3269 set_bit(WORK_ENABLE, &tp->flags);
3270 }
3271 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3272 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3273 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3274 }
3275
3276 mutex_unlock(&tp->control);
3277
3278 return 0;
3279 }
3280
3281 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3282 {
3283 struct r8152 *tp = netdev_priv(dev);
3284
3285 if (usb_autopm_get_interface(tp->intf) < 0)
3286 return;
3287
3288 mutex_lock(&tp->control);
3289
3290 wol->supported = WAKE_ANY;
3291 wol->wolopts = __rtl_get_wol(tp);
3292
3293 mutex_unlock(&tp->control);
3294
3295 usb_autopm_put_interface(tp->intf);
3296 }
3297
3298 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3299 {
3300 struct r8152 *tp = netdev_priv(dev);
3301 int ret;
3302
3303 ret = usb_autopm_get_interface(tp->intf);
3304 if (ret < 0)
3305 goto out_set_wol;
3306
3307 mutex_lock(&tp->control);
3308
3309 __rtl_set_wol(tp, wol->wolopts);
3310 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3311
3312 mutex_unlock(&tp->control);
3313
3314 usb_autopm_put_interface(tp->intf);
3315
3316 out_set_wol:
3317 return ret;
3318 }
3319
3320 static u32 rtl8152_get_msglevel(struct net_device *dev)
3321 {
3322 struct r8152 *tp = netdev_priv(dev);
3323
3324 return tp->msg_enable;
3325 }
3326
3327 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3328 {
3329 struct r8152 *tp = netdev_priv(dev);
3330
3331 tp->msg_enable = value;
3332 }
3333
3334 static void rtl8152_get_drvinfo(struct net_device *netdev,
3335 struct ethtool_drvinfo *info)
3336 {
3337 struct r8152 *tp = netdev_priv(netdev);
3338
3339 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3340 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3341 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3342 }
3343
3344 static
3345 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3346 {
3347 struct r8152 *tp = netdev_priv(netdev);
3348 int ret;
3349
3350 if (!tp->mii.mdio_read)
3351 return -EOPNOTSUPP;
3352
3353 ret = usb_autopm_get_interface(tp->intf);
3354 if (ret < 0)
3355 goto out;
3356
3357 mutex_lock(&tp->control);
3358
3359 ret = mii_ethtool_gset(&tp->mii, cmd);
3360
3361 mutex_unlock(&tp->control);
3362
3363 usb_autopm_put_interface(tp->intf);
3364
3365 out:
3366 return ret;
3367 }
3368
3369 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3370 {
3371 struct r8152 *tp = netdev_priv(dev);
3372 int ret;
3373
3374 ret = usb_autopm_get_interface(tp->intf);
3375 if (ret < 0)
3376 goto out;
3377
3378 mutex_lock(&tp->control);
3379
3380 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3381
3382 mutex_unlock(&tp->control);
3383
3384 usb_autopm_put_interface(tp->intf);
3385
3386 out:
3387 return ret;
3388 }
3389
3390 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3391 "tx_packets",
3392 "rx_packets",
3393 "tx_errors",
3394 "rx_errors",
3395 "rx_missed",
3396 "align_errors",
3397 "tx_single_collisions",
3398 "tx_multi_collisions",
3399 "rx_unicast",
3400 "rx_broadcast",
3401 "rx_multicast",
3402 "tx_aborted",
3403 "tx_underrun",
3404 };
3405
3406 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3407 {
3408 switch (sset) {
3409 case ETH_SS_STATS:
3410 return ARRAY_SIZE(rtl8152_gstrings);
3411 default:
3412 return -EOPNOTSUPP;
3413 }
3414 }
3415
3416 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3417 struct ethtool_stats *stats, u64 *data)
3418 {
3419 struct r8152 *tp = netdev_priv(dev);
3420 struct tally_counter tally;
3421
3422 if (usb_autopm_get_interface(tp->intf) < 0)
3423 return;
3424
3425 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3426
3427 usb_autopm_put_interface(tp->intf);
3428
3429 data[0] = le64_to_cpu(tally.tx_packets);
3430 data[1] = le64_to_cpu(tally.rx_packets);
3431 data[2] = le64_to_cpu(tally.tx_errors);
3432 data[3] = le32_to_cpu(tally.rx_errors);
3433 data[4] = le16_to_cpu(tally.rx_missed);
3434 data[5] = le16_to_cpu(tally.align_errors);
3435 data[6] = le32_to_cpu(tally.tx_one_collision);
3436 data[7] = le32_to_cpu(tally.tx_multi_collision);
3437 data[8] = le64_to_cpu(tally.rx_unicast);
3438 data[9] = le64_to_cpu(tally.rx_broadcast);
3439 data[10] = le32_to_cpu(tally.rx_multicast);
3440 data[11] = le16_to_cpu(tally.tx_aborted);
3441 data[12] = le16_to_cpu(tally.tx_underrun);
3442 }
3443
3444 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3445 {
3446 switch (stringset) {
3447 case ETH_SS_STATS:
3448 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3449 break;
3450 }
3451 }
3452
3453 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3454 {
3455 u32 ocp_data, lp, adv, supported = 0;
3456 u16 val;
3457
3458 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3459 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3460
3461 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3462 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3463
3464 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3465 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3466
3467 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3468 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3469
3470 eee->eee_enabled = !!ocp_data;
3471 eee->eee_active = !!(supported & adv & lp);
3472 eee->supported = supported;
3473 eee->advertised = adv;
3474 eee->lp_advertised = lp;
3475
3476 return 0;
3477 }
3478
3479 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3480 {
3481 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3482
3483 r8152_eee_en(tp, eee->eee_enabled);
3484
3485 if (!eee->eee_enabled)
3486 val = 0;
3487
3488 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3489
3490 return 0;
3491 }
3492
3493 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3494 {
3495 u32 ocp_data, lp, adv, supported = 0;
3496 u16 val;
3497
3498 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3499 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3500
3501 val = ocp_reg_read(tp, OCP_EEE_ADV);
3502 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3503
3504 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3505 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3506
3507 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3508 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3509
3510 eee->eee_enabled = !!ocp_data;
3511 eee->eee_active = !!(supported & adv & lp);
3512 eee->supported = supported;
3513 eee->advertised = adv;
3514 eee->lp_advertised = lp;
3515
3516 return 0;
3517 }
3518
3519 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3520 {
3521 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3522
3523 r8153_eee_en(tp, eee->eee_enabled);
3524
3525 if (!eee->eee_enabled)
3526 val = 0;
3527
3528 ocp_reg_write(tp, OCP_EEE_ADV, val);
3529
3530 return 0;
3531 }
3532
3533 static int
3534 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3535 {
3536 struct r8152 *tp = netdev_priv(net);
3537 int ret;
3538
3539 ret = usb_autopm_get_interface(tp->intf);
3540 if (ret < 0)
3541 goto out;
3542
3543 mutex_lock(&tp->control);
3544
3545 ret = tp->rtl_ops.eee_get(tp, edata);
3546
3547 mutex_unlock(&tp->control);
3548
3549 usb_autopm_put_interface(tp->intf);
3550
3551 out:
3552 return ret;
3553 }
3554
3555 static int
3556 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3557 {
3558 struct r8152 *tp = netdev_priv(net);
3559 int ret;
3560
3561 ret = usb_autopm_get_interface(tp->intf);
3562 if (ret < 0)
3563 goto out;
3564
3565 mutex_lock(&tp->control);
3566
3567 ret = tp->rtl_ops.eee_set(tp, edata);
3568 if (!ret)
3569 ret = mii_nway_restart(&tp->mii);
3570
3571 mutex_unlock(&tp->control);
3572
3573 usb_autopm_put_interface(tp->intf);
3574
3575 out:
3576 return ret;
3577 }
3578
3579 static int rtl8152_nway_reset(struct net_device *dev)
3580 {
3581 struct r8152 *tp = netdev_priv(dev);
3582 int ret;
3583
3584 ret = usb_autopm_get_interface(tp->intf);
3585 if (ret < 0)
3586 goto out;
3587
3588 mutex_lock(&tp->control);
3589
3590 ret = mii_nway_restart(&tp->mii);
3591
3592 mutex_unlock(&tp->control);
3593
3594 usb_autopm_put_interface(tp->intf);
3595
3596 out:
3597 return ret;
3598 }
3599
3600 static struct ethtool_ops ops = {
3601 .get_drvinfo = rtl8152_get_drvinfo,
3602 .get_settings = rtl8152_get_settings,
3603 .set_settings = rtl8152_set_settings,
3604 .get_link = ethtool_op_get_link,
3605 .nway_reset = rtl8152_nway_reset,
3606 .get_msglevel = rtl8152_get_msglevel,
3607 .set_msglevel = rtl8152_set_msglevel,
3608 .get_wol = rtl8152_get_wol,
3609 .set_wol = rtl8152_set_wol,
3610 .get_strings = rtl8152_get_strings,
3611 .get_sset_count = rtl8152_get_sset_count,
3612 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3613 .get_eee = rtl_ethtool_get_eee,
3614 .set_eee = rtl_ethtool_set_eee,
3615 };
3616
3617 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3618 {
3619 struct r8152 *tp = netdev_priv(netdev);
3620 struct mii_ioctl_data *data = if_mii(rq);
3621 int res;
3622
3623 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3624 return -ENODEV;
3625
3626 res = usb_autopm_get_interface(tp->intf);
3627 if (res < 0)
3628 goto out;
3629
3630 switch (cmd) {
3631 case SIOCGMIIPHY:
3632 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3633 break;
3634
3635 case SIOCGMIIREG:
3636 mutex_lock(&tp->control);
3637 data->val_out = r8152_mdio_read(tp, data->reg_num);
3638 mutex_unlock(&tp->control);
3639 break;
3640
3641 case SIOCSMIIREG:
3642 if (!capable(CAP_NET_ADMIN)) {
3643 res = -EPERM;
3644 break;
3645 }
3646 mutex_lock(&tp->control);
3647 r8152_mdio_write(tp, data->reg_num, data->val_in);
3648 mutex_unlock(&tp->control);
3649 break;
3650
3651 default:
3652 res = -EOPNOTSUPP;
3653 }
3654
3655 usb_autopm_put_interface(tp->intf);
3656
3657 out:
3658 return res;
3659 }
3660
3661 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3662 {
3663 struct r8152 *tp = netdev_priv(dev);
3664
3665 switch (tp->version) {
3666 case RTL_VER_01:
3667 case RTL_VER_02:
3668 return eth_change_mtu(dev, new_mtu);
3669 default:
3670 break;
3671 }
3672
3673 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3674 return -EINVAL;
3675
3676 dev->mtu = new_mtu;
3677
3678 return 0;
3679 }
3680
3681 static const struct net_device_ops rtl8152_netdev_ops = {
3682 .ndo_open = rtl8152_open,
3683 .ndo_stop = rtl8152_close,
3684 .ndo_do_ioctl = rtl8152_ioctl,
3685 .ndo_start_xmit = rtl8152_start_xmit,
3686 .ndo_tx_timeout = rtl8152_tx_timeout,
3687 .ndo_set_features = rtl8152_set_features,
3688 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3689 .ndo_set_mac_address = rtl8152_set_mac_address,
3690 .ndo_change_mtu = rtl8152_change_mtu,
3691 .ndo_validate_addr = eth_validate_addr,
3692 };
3693
3694 static void r8152b_get_version(struct r8152 *tp)
3695 {
3696 u32 ocp_data;
3697 u16 version;
3698
3699 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3700 version = (u16)(ocp_data & VERSION_MASK);
3701
3702 switch (version) {
3703 case 0x4c00:
3704 tp->version = RTL_VER_01;
3705 break;
3706 case 0x4c10:
3707 tp->version = RTL_VER_02;
3708 break;
3709 case 0x5c00:
3710 tp->version = RTL_VER_03;
3711 tp->mii.supports_gmii = 1;
3712 break;
3713 case 0x5c10:
3714 tp->version = RTL_VER_04;
3715 tp->mii.supports_gmii = 1;
3716 break;
3717 case 0x5c20:
3718 tp->version = RTL_VER_05;
3719 tp->mii.supports_gmii = 1;
3720 break;
3721 default:
3722 netif_info(tp, probe, tp->netdev,
3723 "Unknown version 0x%04x\n", version);
3724 break;
3725 }
3726 }
3727
3728 static void rtl8152_unload(struct r8152 *tp)
3729 {
3730 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3731 return;
3732
3733 if (tp->version != RTL_VER_01)
3734 r8152_power_cut_en(tp, true);
3735 }
3736
3737 static void rtl8153_unload(struct r8152 *tp)
3738 {
3739 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3740 return;
3741
3742 r8153_power_cut_en(tp, false);
3743 }
3744
3745 static int rtl_ops_init(struct r8152 *tp)
3746 {
3747 struct rtl_ops *ops = &tp->rtl_ops;
3748 int ret = 0;
3749
3750 switch (tp->version) {
3751 case RTL_VER_01:
3752 case RTL_VER_02:
3753 ops->init = r8152b_init;
3754 ops->enable = rtl8152_enable;
3755 ops->disable = rtl8152_disable;
3756 ops->up = rtl8152_up;
3757 ops->down = rtl8152_down;
3758 ops->unload = rtl8152_unload;
3759 ops->eee_get = r8152_get_eee;
3760 ops->eee_set = r8152_set_eee;
3761 break;
3762
3763 case RTL_VER_03:
3764 case RTL_VER_04:
3765 case RTL_VER_05:
3766 ops->init = r8153_init;
3767 ops->enable = rtl8153_enable;
3768 ops->disable = rtl8153_disable;
3769 ops->up = rtl8153_up;
3770 ops->down = rtl8153_down;
3771 ops->unload = rtl8153_unload;
3772 ops->eee_get = r8153_get_eee;
3773 ops->eee_set = r8153_set_eee;
3774 break;
3775
3776 default:
3777 ret = -ENODEV;
3778 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3779 break;
3780 }
3781
3782 return ret;
3783 }
3784
3785 static int rtl8152_probe(struct usb_interface *intf,
3786 const struct usb_device_id *id)
3787 {
3788 struct usb_device *udev = interface_to_usbdev(intf);
3789 struct r8152 *tp;
3790 struct net_device *netdev;
3791 int ret;
3792
3793 if (udev->actconfig->desc.bConfigurationValue != 1) {
3794 usb_driver_set_configuration(udev, 1);
3795 return -ENODEV;
3796 }
3797
3798 usb_reset_device(udev);
3799 netdev = alloc_etherdev(sizeof(struct r8152));
3800 if (!netdev) {
3801 dev_err(&intf->dev, "Out of memory\n");
3802 return -ENOMEM;
3803 }
3804
3805 SET_NETDEV_DEV(netdev, &intf->dev);
3806 tp = netdev_priv(netdev);
3807 tp->msg_enable = 0x7FFF;
3808
3809 tp->udev = udev;
3810 tp->netdev = netdev;
3811 tp->intf = intf;
3812
3813 r8152b_get_version(tp);
3814 ret = rtl_ops_init(tp);
3815 if (ret)
3816 goto out;
3817
3818 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3819 mutex_init(&tp->control);
3820 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3821
3822 netdev->netdev_ops = &rtl8152_netdev_ops;
3823 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3824
3825 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3826 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3827 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3828 NETIF_F_HW_VLAN_CTAG_TX;
3829 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3830 NETIF_F_TSO | NETIF_F_FRAGLIST |
3831 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3832 NETIF_F_HW_VLAN_CTAG_RX |
3833 NETIF_F_HW_VLAN_CTAG_TX;
3834 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3835 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3836 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3837
3838 netdev->ethtool_ops = &ops;
3839 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3840
3841 tp->mii.dev = netdev;
3842 tp->mii.mdio_read = read_mii_word;
3843 tp->mii.mdio_write = write_mii_word;
3844 tp->mii.phy_id_mask = 0x3f;
3845 tp->mii.reg_num_mask = 0x1f;
3846 tp->mii.phy_id = R8152_PHY_ID;
3847
3848 intf->needs_remote_wakeup = 1;
3849
3850 tp->rtl_ops.init(tp);
3851 set_ethernet_addr(tp);
3852
3853 usb_set_intfdata(intf, tp);
3854
3855 ret = register_netdev(netdev);
3856 if (ret != 0) {
3857 netif_err(tp, probe, netdev, "couldn't register the device\n");
3858 goto out1;
3859 }
3860
3861 tp->saved_wolopts = __rtl_get_wol(tp);
3862 if (tp->saved_wolopts)
3863 device_set_wakeup_enable(&udev->dev, true);
3864 else
3865 device_set_wakeup_enable(&udev->dev, false);
3866
3867 tasklet_disable(&tp->tl);
3868
3869 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3870
3871 return 0;
3872
3873 out1:
3874 usb_set_intfdata(intf, NULL);
3875 tasklet_kill(&tp->tl);
3876 out:
3877 free_netdev(netdev);
3878 return ret;
3879 }
3880
3881 static void rtl8152_disconnect(struct usb_interface *intf)
3882 {
3883 struct r8152 *tp = usb_get_intfdata(intf);
3884
3885 usb_set_intfdata(intf, NULL);
3886 if (tp) {
3887 struct usb_device *udev = tp->udev;
3888
3889 if (udev->state == USB_STATE_NOTATTACHED)
3890 set_bit(RTL8152_UNPLUG, &tp->flags);
3891
3892 tasklet_kill(&tp->tl);
3893 unregister_netdev(tp->netdev);
3894 tp->rtl_ops.unload(tp);
3895 free_netdev(tp->netdev);
3896 }
3897 }
3898
3899 /* table of devices that work with this driver */
3900 static struct usb_device_id rtl8152_table[] = {
3901 {USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
3902 {USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
3903 {USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
3904 {}
3905 };
3906
3907 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3908
3909 static struct usb_driver rtl8152_driver = {
3910 .name = MODULENAME,
3911 .id_table = rtl8152_table,
3912 .probe = rtl8152_probe,
3913 .disconnect = rtl8152_disconnect,
3914 .suspend = rtl8152_suspend,
3915 .resume = rtl8152_resume,
3916 .reset_resume = rtl8152_resume,
3917 .supports_autosuspend = 1,
3918 .disable_hub_initiated_lpm = 1,
3919 };
3920
3921 module_usb_driver(rtl8152_driver);
3922
3923 MODULE_AUTHOR(DRIVER_AUTHOR);
3924 MODULE_DESCRIPTION(DRIVER_DESC);
3925 MODULE_LICENSE("GPL");