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r8152: Fix an error on RTL8153-BD MAC Address Passthrough support
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1 /*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION "09"
33
34 /* Information for net */
35 #define NET_VERSION "9"
36
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID 32
43
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PAL_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_EFUSE_DATA 0xdd00
61 #define PLA_EFUSE_CMD 0xdd02
62 #define PLA_LEDSEL 0xdd90
63 #define PLA_LED_FEATURE 0xdd92
64 #define PLA_PHYAR 0xde00
65 #define PLA_BOOT_CTRL 0xe004
66 #define PLA_GPHY_INTR_IMR 0xe022
67 #define PLA_EEE_CR 0xe040
68 #define PLA_EEEP_CR 0xe080
69 #define PLA_MAC_PWR_CTRL 0xe0c0
70 #define PLA_MAC_PWR_CTRL2 0xe0ca
71 #define PLA_MAC_PWR_CTRL3 0xe0cc
72 #define PLA_MAC_PWR_CTRL4 0xe0ce
73 #define PLA_WDT6_CTRL 0xe428
74 #define PLA_TCR0 0xe610
75 #define PLA_TCR1 0xe612
76 #define PLA_MTPS 0xe615
77 #define PLA_TXFIFO_CTRL 0xe618
78 #define PLA_RSTTALLY 0xe800
79 #define PLA_CR 0xe813
80 #define PLA_CRWECR 0xe81c
81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5 0xe822
84 #define PLA_PHY_PWR 0xe84c
85 #define PLA_OOB_CTRL 0xe84f
86 #define PLA_CPCR 0xe854
87 #define PLA_MISC_0 0xe858
88 #define PLA_MISC_1 0xe85a
89 #define PLA_OCP_GPHY_BASE 0xe86c
90 #define PLA_TALLYCNT 0xe890
91 #define PLA_SFF_STS_7 0xe8de
92 #define PLA_PHYSTATUS 0xe908
93 #define PLA_BP_BA 0xfc26
94 #define PLA_BP_0 0xfc28
95 #define PLA_BP_1 0xfc2a
96 #define PLA_BP_2 0xfc2c
97 #define PLA_BP_3 0xfc2e
98 #define PLA_BP_4 0xfc30
99 #define PLA_BP_5 0xfc32
100 #define PLA_BP_6 0xfc34
101 #define PLA_BP_7 0xfc36
102 #define PLA_BP_EN 0xfc38
103
104 #define USB_USB2PHY 0xb41e
105 #define USB_SSPHYLINK2 0xb428
106 #define USB_U2P3_CTRL 0xb460
107 #define USB_CSR_DUMMY1 0xb464
108 #define USB_CSR_DUMMY2 0xb466
109 #define USB_DEV_STAT 0xb808
110 #define USB_CONNECT_TIMER 0xcbf8
111 #define USB_MSC_TIMER 0xcbfc
112 #define USB_BURST_SIZE 0xcfc0
113 #define USB_LPM_CONFIG 0xcfd8
114 #define USB_USB_CTRL 0xd406
115 #define USB_PHY_CTRL 0xd408
116 #define USB_TX_AGG 0xd40a
117 #define USB_RX_BUF_TH 0xd40c
118 #define USB_USB_TIMER 0xd428
119 #define USB_RX_EARLY_TIMEOUT 0xd42c
120 #define USB_RX_EARLY_SIZE 0xd42e
121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
123 #define USB_TX_DMA 0xd434
124 #define USB_UPT_RXDMA_OWN 0xd437
125 #define USB_TOLERANCE 0xd490
126 #define USB_LPM_CTRL 0xd41a
127 #define USB_BMU_RESET 0xd4b0
128 #define USB_U1U2_TIMER 0xd4da
129 #define USB_UPS_CTRL 0xd800
130 #define USB_POWER_CUT 0xd80a
131 #define USB_MISC_0 0xd81a
132 #define USB_MISC_1 0xd81f
133 #define USB_AFE_CTRL2 0xd824
134 #define USB_UPS_CFG 0xd842
135 #define USB_UPS_FLAGS 0xd848
136 #define USB_WDT11_CTRL 0xe43c
137 #define USB_BP_BA 0xfc26
138 #define USB_BP_0 0xfc28
139 #define USB_BP_1 0xfc2a
140 #define USB_BP_2 0xfc2c
141 #define USB_BP_3 0xfc2e
142 #define USB_BP_4 0xfc30
143 #define USB_BP_5 0xfc32
144 #define USB_BP_6 0xfc34
145 #define USB_BP_7 0xfc36
146 #define USB_BP_EN 0xfc38
147 #define USB_BP_8 0xfc38
148 #define USB_BP_9 0xfc3a
149 #define USB_BP_10 0xfc3c
150 #define USB_BP_11 0xfc3e
151 #define USB_BP_12 0xfc40
152 #define USB_BP_13 0xfc42
153 #define USB_BP_14 0xfc44
154 #define USB_BP_15 0xfc46
155 #define USB_BP2_EN 0xfc48
156
157 /* OCP Registers */
158 #define OCP_ALDPS_CONFIG 0x2010
159 #define OCP_EEE_CONFIG1 0x2080
160 #define OCP_EEE_CONFIG2 0x2092
161 #define OCP_EEE_CONFIG3 0x2094
162 #define OCP_BASE_MII 0xa400
163 #define OCP_EEE_AR 0xa41a
164 #define OCP_EEE_DATA 0xa41c
165 #define OCP_PHY_STATUS 0xa420
166 #define OCP_NCTL_CFG 0xa42c
167 #define OCP_POWER_CFG 0xa430
168 #define OCP_EEE_CFG 0xa432
169 #define OCP_SRAM_ADDR 0xa436
170 #define OCP_SRAM_DATA 0xa438
171 #define OCP_DOWN_SPEED 0xa442
172 #define OCP_EEE_ABLE 0xa5c4
173 #define OCP_EEE_ADV 0xa5d0
174 #define OCP_EEE_LPABLE 0xa5d2
175 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
176 #define OCP_PHY_PATCH_STAT 0xb800
177 #define OCP_PHY_PATCH_CMD 0xb820
178 #define OCP_ADC_IOFFSET 0xbcfc
179 #define OCP_ADC_CFG 0xbc06
180 #define OCP_SYSCLK_CFG 0xc416
181
182 /* SRAM Register */
183 #define SRAM_GREEN_CFG 0x8011
184 #define SRAM_LPF_CFG 0x8012
185 #define SRAM_10M_AMP1 0x8080
186 #define SRAM_10M_AMP2 0x8082
187 #define SRAM_IMPEDANCE 0x8084
188
189 /* PLA_RCR */
190 #define RCR_AAP 0x00000001
191 #define RCR_APM 0x00000002
192 #define RCR_AM 0x00000004
193 #define RCR_AB 0x00000008
194 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195
196 /* PLA_RXFIFO_CTRL0 */
197 #define RXFIFO_THR1_NORMAL 0x00080002
198 #define RXFIFO_THR1_OOB 0x01800003
199
200 /* PLA_RXFIFO_CTRL1 */
201 #define RXFIFO_THR2_FULL 0x00000060
202 #define RXFIFO_THR2_HIGH 0x00000038
203 #define RXFIFO_THR2_OOB 0x0000004a
204 #define RXFIFO_THR2_NORMAL 0x00a0
205
206 /* PLA_RXFIFO_CTRL2 */
207 #define RXFIFO_THR3_FULL 0x00000078
208 #define RXFIFO_THR3_HIGH 0x00000048
209 #define RXFIFO_THR3_OOB 0x0000005a
210 #define RXFIFO_THR3_NORMAL 0x0110
211
212 /* PLA_TXFIFO_CTRL */
213 #define TXFIFO_THR_NORMAL 0x00400008
214 #define TXFIFO_THR_NORMAL2 0x01000008
215
216 /* PLA_DMY_REG0 */
217 #define ECM_ALDPS 0x0002
218
219 /* PLA_FMC */
220 #define FMC_FCR_MCU_EN 0x0001
221
222 /* PLA_EEEP_CR */
223 #define EEEP_CR_EEEP_TX 0x0002
224
225 /* PLA_WDT6_CTRL */
226 #define WDT6_SET_MODE 0x0010
227
228 /* PLA_TCR0 */
229 #define TCR0_TX_EMPTY 0x0800
230 #define TCR0_AUTO_FIFO 0x0080
231
232 /* PLA_TCR1 */
233 #define VERSION_MASK 0x7cf0
234
235 /* PLA_MTPS */
236 #define MTPS_JUMBO (12 * 1024 / 64)
237 #define MTPS_DEFAULT (6 * 1024 / 64)
238
239 /* PLA_RSTTALLY */
240 #define TALLY_RESET 0x0001
241
242 /* PLA_CR */
243 #define CR_RST 0x10
244 #define CR_RE 0x08
245 #define CR_TE 0x04
246
247 /* PLA_CRWECR */
248 #define CRWECR_NORAML 0x00
249 #define CRWECR_CONFIG 0xc0
250
251 /* PLA_OOB_CTRL */
252 #define NOW_IS_OOB 0x80
253 #define TXFIFO_EMPTY 0x20
254 #define RXFIFO_EMPTY 0x10
255 #define LINK_LIST_READY 0x02
256 #define DIS_MCU_CLROOB 0x01
257 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
258
259 /* PLA_MISC_1 */
260 #define RXDY_GATED_EN 0x0008
261
262 /* PLA_SFF_STS_7 */
263 #define RE_INIT_LL 0x8000
264 #define MCU_BORW_EN 0x4000
265
266 /* PLA_CPCR */
267 #define CPCR_RX_VLAN 0x0040
268
269 /* PLA_CFG_WOL */
270 #define MAGIC_EN 0x0001
271
272 /* PLA_TEREDO_CFG */
273 #define TEREDO_SEL 0x8000
274 #define TEREDO_WAKE_MASK 0x7f00
275 #define TEREDO_RS_EVENT_MASK 0x00fe
276 #define OOB_TEREDO_EN 0x0001
277
278 /* PAL_BDC_CR */
279 #define ALDPS_PROXY_MODE 0x0001
280
281 /* PLA_EFUSE_CMD */
282 #define EFUSE_READ_CMD BIT(15)
283 #define EFUSE_DATA_BIT16 BIT(7)
284
285 /* PLA_CONFIG34 */
286 #define LINK_ON_WAKE_EN 0x0010
287 #define LINK_OFF_WAKE_EN 0x0008
288
289 /* PLA_CONFIG5 */
290 #define BWF_EN 0x0040
291 #define MWF_EN 0x0020
292 #define UWF_EN 0x0010
293 #define LAN_WAKE_EN 0x0002
294
295 /* PLA_LED_FEATURE */
296 #define LED_MODE_MASK 0x0700
297
298 /* PLA_PHY_PWR */
299 #define TX_10M_IDLE_EN 0x0080
300 #define PFM_PWM_SWITCH 0x0040
301
302 /* PLA_MAC_PWR_CTRL */
303 #define D3_CLK_GATED_EN 0x00004000
304 #define MCU_CLK_RATIO 0x07010f07
305 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
306 #define ALDPS_SPDWN_RATIO 0x0f87
307
308 /* PLA_MAC_PWR_CTRL2 */
309 #define EEE_SPDWN_RATIO 0x8007
310 #define MAC_CLK_SPDWN_EN BIT(15)
311
312 /* PLA_MAC_PWR_CTRL3 */
313 #define PKT_AVAIL_SPDWN_EN 0x0100
314 #define SUSPEND_SPDWN_EN 0x0004
315 #define U1U2_SPDWN_EN 0x0002
316 #define L1_SPDWN_EN 0x0001
317
318 /* PLA_MAC_PWR_CTRL4 */
319 #define PWRSAVE_SPDWN_EN 0x1000
320 #define RXDV_SPDWN_EN 0x0800
321 #define TX10MIDLE_EN 0x0100
322 #define TP100_SPDWN_EN 0x0020
323 #define TP500_SPDWN_EN 0x0010
324 #define TP1000_SPDWN_EN 0x0008
325 #define EEE_SPDWN_EN 0x0001
326
327 /* PLA_GPHY_INTR_IMR */
328 #define GPHY_STS_MSK 0x0001
329 #define SPEED_DOWN_MSK 0x0002
330 #define SPDWN_RXDV_MSK 0x0004
331 #define SPDWN_LINKCHG_MSK 0x0008
332
333 /* PLA_PHYAR */
334 #define PHYAR_FLAG 0x80000000
335
336 /* PLA_EEE_CR */
337 #define EEE_RX_EN 0x0001
338 #define EEE_TX_EN 0x0002
339
340 /* PLA_BOOT_CTRL */
341 #define AUTOLOAD_DONE 0x0002
342
343 /* USB_USB2PHY */
344 #define USB2PHY_SUSPEND 0x0001
345 #define USB2PHY_L1 0x0002
346
347 /* USB_SSPHYLINK2 */
348 #define pwd_dn_scale_mask 0x3ffe
349 #define pwd_dn_scale(x) ((x) << 1)
350
351 /* USB_CSR_DUMMY1 */
352 #define DYNAMIC_BURST 0x0001
353
354 /* USB_CSR_DUMMY2 */
355 #define EP4_FULL_FC 0x0001
356
357 /* USB_DEV_STAT */
358 #define STAT_SPEED_MASK 0x0006
359 #define STAT_SPEED_HIGH 0x0000
360 #define STAT_SPEED_FULL 0x0002
361
362 /* USB_LPM_CONFIG */
363 #define LPM_U1U2_EN BIT(0)
364
365 /* USB_TX_AGG */
366 #define TX_AGG_MAX_THRESHOLD 0x03
367
368 /* USB_RX_BUF_TH */
369 #define RX_THR_SUPPER 0x0c350180
370 #define RX_THR_HIGH 0x7a120180
371 #define RX_THR_SLOW 0xffff0180
372 #define RX_THR_B 0x00010001
373
374 /* USB_TX_DMA */
375 #define TEST_MODE_DISABLE 0x00000001
376 #define TX_SIZE_ADJUST1 0x00000100
377
378 /* USB_BMU_RESET */
379 #define BMU_RESET_EP_IN 0x01
380 #define BMU_RESET_EP_OUT 0x02
381
382 /* USB_UPT_RXDMA_OWN */
383 #define OWN_UPDATE BIT(0)
384 #define OWN_CLEAR BIT(1)
385
386 /* USB_UPS_CTRL */
387 #define POWER_CUT 0x0100
388
389 /* USB_PM_CTRL_STATUS */
390 #define RESUME_INDICATE 0x0001
391
392 /* USB_USB_CTRL */
393 #define RX_AGG_DISABLE 0x0010
394 #define RX_ZERO_EN 0x0080
395
396 /* USB_U2P3_CTRL */
397 #define U2P3_ENABLE 0x0001
398
399 /* USB_POWER_CUT */
400 #define PWR_EN 0x0001
401 #define PHASE2_EN 0x0008
402 #define UPS_EN BIT(4)
403 #define USP_PREWAKE BIT(5)
404
405 /* USB_MISC_0 */
406 #define PCUT_STATUS 0x0001
407
408 /* USB_RX_EARLY_TIMEOUT */
409 #define COALESCE_SUPER 85000U
410 #define COALESCE_HIGH 250000U
411 #define COALESCE_SLOW 524280U
412
413 /* USB_WDT11_CTRL */
414 #define TIMER11_EN 0x0001
415
416 /* USB_LPM_CTRL */
417 /* bit 4 ~ 5: fifo empty boundary */
418 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
419 /* bit 2 ~ 3: LMP timer */
420 #define LPM_TIMER_MASK 0x0c
421 #define LPM_TIMER_500MS 0x04 /* 500 ms */
422 #define LPM_TIMER_500US 0x0c /* 500 us */
423 #define ROK_EXIT_LPM 0x02
424
425 /* USB_AFE_CTRL2 */
426 #define SEN_VAL_MASK 0xf800
427 #define SEN_VAL_NORMAL 0xa000
428 #define SEL_RXIDLE 0x0100
429
430 /* USB_UPS_CFG */
431 #define SAW_CNT_1MS_MASK 0x0fff
432
433 /* USB_UPS_FLAGS */
434 #define UPS_FLAGS_R_TUNE BIT(0)
435 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
436 #define UPS_FLAGS_250M_CKDIV BIT(2)
437 #define UPS_FLAGS_EN_ALDPS BIT(3)
438 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
439 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
440 #define ups_flags_speed(x) ((x) << 16)
441 #define UPS_FLAGS_EN_EEE BIT(20)
442 #define UPS_FLAGS_EN_500M_EEE BIT(21)
443 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
444 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
445 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
446 #define UPS_FLAGS_EN_GREEN BIT(26)
447 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
448
449 enum spd_duplex {
450 NWAY_10M_HALF = 1,
451 NWAY_10M_FULL,
452 NWAY_100M_HALF,
453 NWAY_100M_FULL,
454 NWAY_1000M_FULL,
455 FORCE_10M_HALF,
456 FORCE_10M_FULL,
457 FORCE_100M_HALF,
458 FORCE_100M_FULL,
459 };
460
461 /* OCP_ALDPS_CONFIG */
462 #define ENPWRSAVE 0x8000
463 #define ENPDNPS 0x0200
464 #define LINKENA 0x0100
465 #define DIS_SDSAVE 0x0010
466
467 /* OCP_PHY_STATUS */
468 #define PHY_STAT_MASK 0x0007
469 #define PHY_STAT_EXT_INIT 2
470 #define PHY_STAT_LAN_ON 3
471 #define PHY_STAT_PWRDN 5
472
473 /* OCP_NCTL_CFG */
474 #define PGA_RETURN_EN BIT(1)
475
476 /* OCP_POWER_CFG */
477 #define EEE_CLKDIV_EN 0x8000
478 #define EN_ALDPS 0x0004
479 #define EN_10M_PLLOFF 0x0001
480
481 /* OCP_EEE_CONFIG1 */
482 #define RG_TXLPI_MSK_HFDUP 0x8000
483 #define RG_MATCLR_EN 0x4000
484 #define EEE_10_CAP 0x2000
485 #define EEE_NWAY_EN 0x1000
486 #define TX_QUIET_EN 0x0200
487 #define RX_QUIET_EN 0x0100
488 #define sd_rise_time_mask 0x0070
489 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
490 #define RG_RXLPI_MSK_HFDUP 0x0008
491 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
492
493 /* OCP_EEE_CONFIG2 */
494 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
495 #define RG_DACQUIET_EN 0x0400
496 #define RG_LDVQUIET_EN 0x0200
497 #define RG_CKRSEL 0x0020
498 #define RG_EEEPRG_EN 0x0010
499
500 /* OCP_EEE_CONFIG3 */
501 #define fast_snr_mask 0xff80
502 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
503 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
504 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
505
506 /* OCP_EEE_AR */
507 /* bit[15:14] function */
508 #define FUN_ADDR 0x0000
509 #define FUN_DATA 0x4000
510 /* bit[4:0] device addr */
511
512 /* OCP_EEE_CFG */
513 #define CTAP_SHORT_EN 0x0040
514 #define EEE10_EN 0x0010
515
516 /* OCP_DOWN_SPEED */
517 #define EN_EEE_CMODE BIT(14)
518 #define EN_EEE_1000 BIT(13)
519 #define EN_EEE_100 BIT(12)
520 #define EN_10M_CLKDIV BIT(11)
521 #define EN_10M_BGOFF 0x0080
522
523 /* OCP_PHY_STATE */
524 #define TXDIS_STATE 0x01
525 #define ABD_STATE 0x02
526
527 /* OCP_PHY_PATCH_STAT */
528 #define PATCH_READY BIT(6)
529
530 /* OCP_PHY_PATCH_CMD */
531 #define PATCH_REQUEST BIT(4)
532
533 /* OCP_ADC_CFG */
534 #define CKADSEL_L 0x0100
535 #define ADC_EN 0x0080
536 #define EN_EMI_L 0x0040
537
538 /* OCP_SYSCLK_CFG */
539 #define clk_div_expo(x) (min(x, 5) << 8)
540
541 /* SRAM_GREEN_CFG */
542 #define GREEN_ETH_EN BIT(15)
543 #define R_TUNE_EN BIT(11)
544
545 /* SRAM_LPF_CFG */
546 #define LPF_AUTO_TUNE 0x8000
547
548 /* SRAM_10M_AMP1 */
549 #define GDAC_IB_UPALL 0x0008
550
551 /* SRAM_10M_AMP2 */
552 #define AMP_DN 0x0200
553
554 /* SRAM_IMPEDANCE */
555 #define RX_DRIVING_MASK 0x6000
556
557 /* MAC PASSTHRU */
558 #define AD_MASK 0xfee0
559 #define BND_MASK 0x0004
560 #define BD_MASK 0x0001
561 #define EFUSE 0xcfdb
562 #define PASS_THRU_MASK 0x1
563
564 enum rtl_register_content {
565 _1000bps = 0x10,
566 _100bps = 0x08,
567 _10bps = 0x04,
568 LINK_STATUS = 0x02,
569 FULL_DUP = 0x01,
570 };
571
572 #define RTL8152_MAX_TX 4
573 #define RTL8152_MAX_RX 10
574 #define INTBUFSIZE 2
575 #define TX_ALIGN 4
576 #define RX_ALIGN 8
577
578 #define INTR_LINK 0x0004
579
580 #define RTL8152_REQT_READ 0xc0
581 #define RTL8152_REQT_WRITE 0x40
582 #define RTL8152_REQ_GET_REGS 0x05
583 #define RTL8152_REQ_SET_REGS 0x05
584
585 #define BYTE_EN_DWORD 0xff
586 #define BYTE_EN_WORD 0x33
587 #define BYTE_EN_BYTE 0x11
588 #define BYTE_EN_SIX_BYTES 0x3f
589 #define BYTE_EN_START_MASK 0x0f
590 #define BYTE_EN_END_MASK 0xf0
591
592 #define RTL8153_MAX_PACKET 9216 /* 9K */
593 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
594 ETH_FCS_LEN)
595 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
596 #define RTL8153_RMS RTL8153_MAX_PACKET
597 #define RTL8152_TX_TIMEOUT (5 * HZ)
598 #define RTL8152_NAPI_WEIGHT 64
599 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
600 sizeof(struct rx_desc) + RX_ALIGN)
601
602 /* rtl8152 flags */
603 enum rtl8152_flags {
604 RTL8152_UNPLUG = 0,
605 RTL8152_SET_RX_MODE,
606 WORK_ENABLE,
607 RTL8152_LINK_CHG,
608 SELECTIVE_SUSPEND,
609 PHY_RESET,
610 SCHEDULE_NAPI,
611 GREEN_ETHERNET,
612 DELL_TB_RX_AGG_BUG,
613 };
614
615 /* Define these values to match your device */
616 #define VENDOR_ID_REALTEK 0x0bda
617 #define VENDOR_ID_MICROSOFT 0x045e
618 #define VENDOR_ID_SAMSUNG 0x04e8
619 #define VENDOR_ID_LENOVO 0x17ef
620 #define VENDOR_ID_LINKSYS 0x13b1
621 #define VENDOR_ID_NVIDIA 0x0955
622 #define VENDOR_ID_TPLINK 0x2357
623
624 #define MCU_TYPE_PLA 0x0100
625 #define MCU_TYPE_USB 0x0000
626
627 struct tally_counter {
628 __le64 tx_packets;
629 __le64 rx_packets;
630 __le64 tx_errors;
631 __le32 rx_errors;
632 __le16 rx_missed;
633 __le16 align_errors;
634 __le32 tx_one_collision;
635 __le32 tx_multi_collision;
636 __le64 rx_unicast;
637 __le64 rx_broadcast;
638 __le32 rx_multicast;
639 __le16 tx_aborted;
640 __le16 tx_underrun;
641 };
642
643 struct rx_desc {
644 __le32 opts1;
645 #define RX_LEN_MASK 0x7fff
646
647 __le32 opts2;
648 #define RD_UDP_CS BIT(23)
649 #define RD_TCP_CS BIT(22)
650 #define RD_IPV6_CS BIT(20)
651 #define RD_IPV4_CS BIT(19)
652
653 __le32 opts3;
654 #define IPF BIT(23) /* IP checksum fail */
655 #define UDPF BIT(22) /* UDP checksum fail */
656 #define TCPF BIT(21) /* TCP checksum fail */
657 #define RX_VLAN_TAG BIT(16)
658
659 __le32 opts4;
660 __le32 opts5;
661 __le32 opts6;
662 };
663
664 struct tx_desc {
665 __le32 opts1;
666 #define TX_FS BIT(31) /* First segment of a packet */
667 #define TX_LS BIT(30) /* Final segment of a packet */
668 #define GTSENDV4 BIT(28)
669 #define GTSENDV6 BIT(27)
670 #define GTTCPHO_SHIFT 18
671 #define GTTCPHO_MAX 0x7fU
672 #define TX_LEN_MAX 0x3ffffU
673
674 __le32 opts2;
675 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
676 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
677 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
678 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
679 #define MSS_SHIFT 17
680 #define MSS_MAX 0x7ffU
681 #define TCPHO_SHIFT 17
682 #define TCPHO_MAX 0x7ffU
683 #define TX_VLAN_TAG BIT(16)
684 };
685
686 struct r8152;
687
688 struct rx_agg {
689 struct list_head list;
690 struct urb *urb;
691 struct r8152 *context;
692 void *buffer;
693 void *head;
694 };
695
696 struct tx_agg {
697 struct list_head list;
698 struct urb *urb;
699 struct r8152 *context;
700 void *buffer;
701 void *head;
702 u32 skb_num;
703 u32 skb_len;
704 };
705
706 struct r8152 {
707 unsigned long flags;
708 struct usb_device *udev;
709 struct napi_struct napi;
710 struct usb_interface *intf;
711 struct net_device *netdev;
712 struct urb *intr_urb;
713 struct tx_agg tx_info[RTL8152_MAX_TX];
714 struct rx_agg rx_info[RTL8152_MAX_RX];
715 struct list_head rx_done, tx_free;
716 struct sk_buff_head tx_queue, rx_queue;
717 spinlock_t rx_lock, tx_lock;
718 struct delayed_work schedule, hw_phy_work;
719 struct mii_if_info mii;
720 struct mutex control; /* use for hw setting */
721 #ifdef CONFIG_PM_SLEEP
722 struct notifier_block pm_notifier;
723 #endif
724
725 struct rtl_ops {
726 void (*init)(struct r8152 *);
727 int (*enable)(struct r8152 *);
728 void (*disable)(struct r8152 *);
729 void (*up)(struct r8152 *);
730 void (*down)(struct r8152 *);
731 void (*unload)(struct r8152 *);
732 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
733 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
734 bool (*in_nway)(struct r8152 *);
735 void (*hw_phy_cfg)(struct r8152 *);
736 void (*autosuspend_en)(struct r8152 *tp, bool enable);
737 } rtl_ops;
738
739 int intr_interval;
740 u32 saved_wolopts;
741 u32 msg_enable;
742 u32 tx_qlen;
743 u32 coalesce;
744 u16 ocp_base;
745 u16 speed;
746 u8 *intr_buff;
747 u8 version;
748 u8 duplex;
749 u8 autoneg;
750 };
751
752 enum rtl_version {
753 RTL_VER_UNKNOWN = 0,
754 RTL_VER_01,
755 RTL_VER_02,
756 RTL_VER_03,
757 RTL_VER_04,
758 RTL_VER_05,
759 RTL_VER_06,
760 RTL_VER_07,
761 RTL_VER_08,
762 RTL_VER_09,
763 RTL_VER_MAX
764 };
765
766 enum tx_csum_stat {
767 TX_CSUM_SUCCESS = 0,
768 TX_CSUM_TSO,
769 TX_CSUM_NONE
770 };
771
772 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
773 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
774 */
775 static const int multicast_filter_limit = 32;
776 static unsigned int agg_buf_sz = 16384;
777
778 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
779 VLAN_ETH_HLEN - ETH_FCS_LEN)
780
781 static
782 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
783 {
784 int ret;
785 void *tmp;
786
787 tmp = kmalloc(size, GFP_KERNEL);
788 if (!tmp)
789 return -ENOMEM;
790
791 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
792 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
793 value, index, tmp, size, 500);
794
795 memcpy(data, tmp, size);
796 kfree(tmp);
797
798 return ret;
799 }
800
801 static
802 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
803 {
804 int ret;
805 void *tmp;
806
807 tmp = kmemdup(data, size, GFP_KERNEL);
808 if (!tmp)
809 return -ENOMEM;
810
811 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
812 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
813 value, index, tmp, size, 500);
814
815 kfree(tmp);
816
817 return ret;
818 }
819
820 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
821 void *data, u16 type)
822 {
823 u16 limit = 64;
824 int ret = 0;
825
826 if (test_bit(RTL8152_UNPLUG, &tp->flags))
827 return -ENODEV;
828
829 /* both size and indix must be 4 bytes align */
830 if ((size & 3) || !size || (index & 3) || !data)
831 return -EPERM;
832
833 if ((u32)index + (u32)size > 0xffff)
834 return -EPERM;
835
836 while (size) {
837 if (size > limit) {
838 ret = get_registers(tp, index, type, limit, data);
839 if (ret < 0)
840 break;
841
842 index += limit;
843 data += limit;
844 size -= limit;
845 } else {
846 ret = get_registers(tp, index, type, size, data);
847 if (ret < 0)
848 break;
849
850 index += size;
851 data += size;
852 size = 0;
853 break;
854 }
855 }
856
857 if (ret == -ENODEV)
858 set_bit(RTL8152_UNPLUG, &tp->flags);
859
860 return ret;
861 }
862
863 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
864 u16 size, void *data, u16 type)
865 {
866 int ret;
867 u16 byteen_start, byteen_end, byen;
868 u16 limit = 512;
869
870 if (test_bit(RTL8152_UNPLUG, &tp->flags))
871 return -ENODEV;
872
873 /* both size and indix must be 4 bytes align */
874 if ((size & 3) || !size || (index & 3) || !data)
875 return -EPERM;
876
877 if ((u32)index + (u32)size > 0xffff)
878 return -EPERM;
879
880 byteen_start = byteen & BYTE_EN_START_MASK;
881 byteen_end = byteen & BYTE_EN_END_MASK;
882
883 byen = byteen_start | (byteen_start << 4);
884 ret = set_registers(tp, index, type | byen, 4, data);
885 if (ret < 0)
886 goto error1;
887
888 index += 4;
889 data += 4;
890 size -= 4;
891
892 if (size) {
893 size -= 4;
894
895 while (size) {
896 if (size > limit) {
897 ret = set_registers(tp, index,
898 type | BYTE_EN_DWORD,
899 limit, data);
900 if (ret < 0)
901 goto error1;
902
903 index += limit;
904 data += limit;
905 size -= limit;
906 } else {
907 ret = set_registers(tp, index,
908 type | BYTE_EN_DWORD,
909 size, data);
910 if (ret < 0)
911 goto error1;
912
913 index += size;
914 data += size;
915 size = 0;
916 break;
917 }
918 }
919
920 byen = byteen_end | (byteen_end >> 4);
921 ret = set_registers(tp, index, type | byen, 4, data);
922 if (ret < 0)
923 goto error1;
924 }
925
926 error1:
927 if (ret == -ENODEV)
928 set_bit(RTL8152_UNPLUG, &tp->flags);
929
930 return ret;
931 }
932
933 static inline
934 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
935 {
936 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
937 }
938
939 static inline
940 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
941 {
942 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
943 }
944
945 static inline
946 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
947 {
948 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
949 }
950
951 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
952 {
953 __le32 data;
954
955 generic_ocp_read(tp, index, sizeof(data), &data, type);
956
957 return __le32_to_cpu(data);
958 }
959
960 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
961 {
962 __le32 tmp = __cpu_to_le32(data);
963
964 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
965 }
966
967 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
968 {
969 u32 data;
970 __le32 tmp;
971 u16 byen = BYTE_EN_WORD;
972 u8 shift = index & 2;
973
974 index &= ~3;
975 byen <<= shift;
976
977 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
978
979 data = __le32_to_cpu(tmp);
980 data >>= (shift * 8);
981 data &= 0xffff;
982
983 return (u16)data;
984 }
985
986 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
987 {
988 u32 mask = 0xffff;
989 __le32 tmp;
990 u16 byen = BYTE_EN_WORD;
991 u8 shift = index & 2;
992
993 data &= mask;
994
995 if (index & 2) {
996 byen <<= shift;
997 mask <<= (shift * 8);
998 data <<= (shift * 8);
999 index &= ~3;
1000 }
1001
1002 tmp = __cpu_to_le32(data);
1003
1004 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1005 }
1006
1007 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1008 {
1009 u32 data;
1010 __le32 tmp;
1011 u8 shift = index & 3;
1012
1013 index &= ~3;
1014
1015 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1016
1017 data = __le32_to_cpu(tmp);
1018 data >>= (shift * 8);
1019 data &= 0xff;
1020
1021 return (u8)data;
1022 }
1023
1024 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1025 {
1026 u32 mask = 0xff;
1027 __le32 tmp;
1028 u16 byen = BYTE_EN_BYTE;
1029 u8 shift = index & 3;
1030
1031 data &= mask;
1032
1033 if (index & 3) {
1034 byen <<= shift;
1035 mask <<= (shift * 8);
1036 data <<= (shift * 8);
1037 index &= ~3;
1038 }
1039
1040 tmp = __cpu_to_le32(data);
1041
1042 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1043 }
1044
1045 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1046 {
1047 u16 ocp_base, ocp_index;
1048
1049 ocp_base = addr & 0xf000;
1050 if (ocp_base != tp->ocp_base) {
1051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1052 tp->ocp_base = ocp_base;
1053 }
1054
1055 ocp_index = (addr & 0x0fff) | 0xb000;
1056 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1057 }
1058
1059 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1060 {
1061 u16 ocp_base, ocp_index;
1062
1063 ocp_base = addr & 0xf000;
1064 if (ocp_base != tp->ocp_base) {
1065 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1066 tp->ocp_base = ocp_base;
1067 }
1068
1069 ocp_index = (addr & 0x0fff) | 0xb000;
1070 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1071 }
1072
1073 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1074 {
1075 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1076 }
1077
1078 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1079 {
1080 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1081 }
1082
1083 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1084 {
1085 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1086 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1087 }
1088
1089 static u16 sram_read(struct r8152 *tp, u16 addr)
1090 {
1091 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1092 return ocp_reg_read(tp, OCP_SRAM_DATA);
1093 }
1094
1095 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1096 {
1097 struct r8152 *tp = netdev_priv(netdev);
1098 int ret;
1099
1100 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1101 return -ENODEV;
1102
1103 if (phy_id != R8152_PHY_ID)
1104 return -EINVAL;
1105
1106 ret = r8152_mdio_read(tp, reg);
1107
1108 return ret;
1109 }
1110
1111 static
1112 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1113 {
1114 struct r8152 *tp = netdev_priv(netdev);
1115
1116 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1117 return;
1118
1119 if (phy_id != R8152_PHY_ID)
1120 return;
1121
1122 r8152_mdio_write(tp, reg, val);
1123 }
1124
1125 static int
1126 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1127
1128 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1129 {
1130 struct r8152 *tp = netdev_priv(netdev);
1131 struct sockaddr *addr = p;
1132 int ret = -EADDRNOTAVAIL;
1133
1134 if (!is_valid_ether_addr(addr->sa_data))
1135 goto out1;
1136
1137 ret = usb_autopm_get_interface(tp->intf);
1138 if (ret < 0)
1139 goto out1;
1140
1141 mutex_lock(&tp->control);
1142
1143 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1144
1145 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1146 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1147 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1148
1149 mutex_unlock(&tp->control);
1150
1151 usb_autopm_put_interface(tp->intf);
1152 out1:
1153 return ret;
1154 }
1155
1156 /* Devices containing proper chips can support a persistent
1157 * host system provided MAC address.
1158 * Examples of this are Dell TB15 and Dell WD15 docks
1159 */
1160 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1161 {
1162 acpi_status status;
1163 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1164 union acpi_object *obj;
1165 int ret = -EINVAL;
1166 u32 ocp_data;
1167 unsigned char buf[6];
1168
1169 /* test for -AD variant of RTL8153 */
1170 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1171 if ((ocp_data & AD_MASK) == 0x1000) {
1172 /* test for MAC address pass-through bit */
1173 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1174 if ((ocp_data & PASS_THRU_MASK) != 1) {
1175 netif_dbg(tp, probe, tp->netdev,
1176 "No efuse for RTL8153-AD MAC pass through\n");
1177 return -ENODEV;
1178 }
1179 } else {
1180 /* test for RTL8153-BND and RTL8153-BD */
1181 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1182 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1183 netif_dbg(tp, probe, tp->netdev,
1184 "Invalid variant for MAC pass through\n");
1185 return -ENODEV;
1186 }
1187 }
1188
1189 /* returns _AUXMAC_#AABBCCDDEEFF# */
1190 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1191 obj = (union acpi_object *)buffer.pointer;
1192 if (!ACPI_SUCCESS(status))
1193 return -ENODEV;
1194 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1195 netif_warn(tp, probe, tp->netdev,
1196 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1197 obj->type, obj->string.length);
1198 goto amacout;
1199 }
1200 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1201 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1202 netif_warn(tp, probe, tp->netdev,
1203 "Invalid header when reading pass-thru MAC addr\n");
1204 goto amacout;
1205 }
1206 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1207 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1208 netif_warn(tp, probe, tp->netdev,
1209 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1210 ret, buf);
1211 ret = -EINVAL;
1212 goto amacout;
1213 }
1214 memcpy(sa->sa_data, buf, 6);
1215 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1216 netif_info(tp, probe, tp->netdev,
1217 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1218
1219 amacout:
1220 kfree(obj);
1221 return ret;
1222 }
1223
1224 static int set_ethernet_addr(struct r8152 *tp)
1225 {
1226 struct net_device *dev = tp->netdev;
1227 struct sockaddr sa;
1228 int ret;
1229
1230 if (tp->version == RTL_VER_01) {
1231 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1232 } else {
1233 /* if device doesn't support MAC pass through this will
1234 * be expected to be non-zero
1235 */
1236 ret = vendor_mac_passthru_addr_read(tp, &sa);
1237 if (ret < 0)
1238 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1239 }
1240
1241 if (ret < 0) {
1242 netif_err(tp, probe, dev, "Get ether addr fail\n");
1243 } else if (!is_valid_ether_addr(sa.sa_data)) {
1244 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1245 sa.sa_data);
1246 eth_hw_addr_random(dev);
1247 ether_addr_copy(sa.sa_data, dev->dev_addr);
1248 ret = rtl8152_set_mac_address(dev, &sa);
1249 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1250 sa.sa_data);
1251 } else {
1252 if (tp->version == RTL_VER_01)
1253 ether_addr_copy(dev->dev_addr, sa.sa_data);
1254 else
1255 ret = rtl8152_set_mac_address(dev, &sa);
1256 }
1257
1258 return ret;
1259 }
1260
1261 static void read_bulk_callback(struct urb *urb)
1262 {
1263 struct net_device *netdev;
1264 int status = urb->status;
1265 struct rx_agg *agg;
1266 struct r8152 *tp;
1267
1268 agg = urb->context;
1269 if (!agg)
1270 return;
1271
1272 tp = agg->context;
1273 if (!tp)
1274 return;
1275
1276 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1277 return;
1278
1279 if (!test_bit(WORK_ENABLE, &tp->flags))
1280 return;
1281
1282 netdev = tp->netdev;
1283
1284 /* When link down, the driver would cancel all bulks. */
1285 /* This avoid the re-submitting bulk */
1286 if (!netif_carrier_ok(netdev))
1287 return;
1288
1289 usb_mark_last_busy(tp->udev);
1290
1291 switch (status) {
1292 case 0:
1293 if (urb->actual_length < ETH_ZLEN)
1294 break;
1295
1296 spin_lock(&tp->rx_lock);
1297 list_add_tail(&agg->list, &tp->rx_done);
1298 spin_unlock(&tp->rx_lock);
1299 napi_schedule(&tp->napi);
1300 return;
1301 case -ESHUTDOWN:
1302 set_bit(RTL8152_UNPLUG, &tp->flags);
1303 netif_device_detach(tp->netdev);
1304 return;
1305 case -ENOENT:
1306 return; /* the urb is in unlink state */
1307 case -ETIME:
1308 if (net_ratelimit())
1309 netdev_warn(netdev, "maybe reset is needed?\n");
1310 break;
1311 default:
1312 if (net_ratelimit())
1313 netdev_warn(netdev, "Rx status %d\n", status);
1314 break;
1315 }
1316
1317 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1318 }
1319
1320 static void write_bulk_callback(struct urb *urb)
1321 {
1322 struct net_device_stats *stats;
1323 struct net_device *netdev;
1324 struct tx_agg *agg;
1325 struct r8152 *tp;
1326 int status = urb->status;
1327
1328 agg = urb->context;
1329 if (!agg)
1330 return;
1331
1332 tp = agg->context;
1333 if (!tp)
1334 return;
1335
1336 netdev = tp->netdev;
1337 stats = &netdev->stats;
1338 if (status) {
1339 if (net_ratelimit())
1340 netdev_warn(netdev, "Tx status %d\n", status);
1341 stats->tx_errors += agg->skb_num;
1342 } else {
1343 stats->tx_packets += agg->skb_num;
1344 stats->tx_bytes += agg->skb_len;
1345 }
1346
1347 spin_lock(&tp->tx_lock);
1348 list_add_tail(&agg->list, &tp->tx_free);
1349 spin_unlock(&tp->tx_lock);
1350
1351 usb_autopm_put_interface_async(tp->intf);
1352
1353 if (!netif_carrier_ok(netdev))
1354 return;
1355
1356 if (!test_bit(WORK_ENABLE, &tp->flags))
1357 return;
1358
1359 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1360 return;
1361
1362 if (!skb_queue_empty(&tp->tx_queue))
1363 napi_schedule(&tp->napi);
1364 }
1365
1366 static void intr_callback(struct urb *urb)
1367 {
1368 struct r8152 *tp;
1369 __le16 *d;
1370 int status = urb->status;
1371 int res;
1372
1373 tp = urb->context;
1374 if (!tp)
1375 return;
1376
1377 if (!test_bit(WORK_ENABLE, &tp->flags))
1378 return;
1379
1380 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1381 return;
1382
1383 switch (status) {
1384 case 0: /* success */
1385 break;
1386 case -ECONNRESET: /* unlink */
1387 case -ESHUTDOWN:
1388 netif_device_detach(tp->netdev);
1389 case -ENOENT:
1390 case -EPROTO:
1391 netif_info(tp, intr, tp->netdev,
1392 "Stop submitting intr, status %d\n", status);
1393 return;
1394 case -EOVERFLOW:
1395 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1396 goto resubmit;
1397 /* -EPIPE: should clear the halt */
1398 default:
1399 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1400 goto resubmit;
1401 }
1402
1403 d = urb->transfer_buffer;
1404 if (INTR_LINK & __le16_to_cpu(d[0])) {
1405 if (!netif_carrier_ok(tp->netdev)) {
1406 set_bit(RTL8152_LINK_CHG, &tp->flags);
1407 schedule_delayed_work(&tp->schedule, 0);
1408 }
1409 } else {
1410 if (netif_carrier_ok(tp->netdev)) {
1411 netif_stop_queue(tp->netdev);
1412 set_bit(RTL8152_LINK_CHG, &tp->flags);
1413 schedule_delayed_work(&tp->schedule, 0);
1414 }
1415 }
1416
1417 resubmit:
1418 res = usb_submit_urb(urb, GFP_ATOMIC);
1419 if (res == -ENODEV) {
1420 set_bit(RTL8152_UNPLUG, &tp->flags);
1421 netif_device_detach(tp->netdev);
1422 } else if (res) {
1423 netif_err(tp, intr, tp->netdev,
1424 "can't resubmit intr, status %d\n", res);
1425 }
1426 }
1427
1428 static inline void *rx_agg_align(void *data)
1429 {
1430 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1431 }
1432
1433 static inline void *tx_agg_align(void *data)
1434 {
1435 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1436 }
1437
1438 static void free_all_mem(struct r8152 *tp)
1439 {
1440 int i;
1441
1442 for (i = 0; i < RTL8152_MAX_RX; i++) {
1443 usb_free_urb(tp->rx_info[i].urb);
1444 tp->rx_info[i].urb = NULL;
1445
1446 kfree(tp->rx_info[i].buffer);
1447 tp->rx_info[i].buffer = NULL;
1448 tp->rx_info[i].head = NULL;
1449 }
1450
1451 for (i = 0; i < RTL8152_MAX_TX; i++) {
1452 usb_free_urb(tp->tx_info[i].urb);
1453 tp->tx_info[i].urb = NULL;
1454
1455 kfree(tp->tx_info[i].buffer);
1456 tp->tx_info[i].buffer = NULL;
1457 tp->tx_info[i].head = NULL;
1458 }
1459
1460 usb_free_urb(tp->intr_urb);
1461 tp->intr_urb = NULL;
1462
1463 kfree(tp->intr_buff);
1464 tp->intr_buff = NULL;
1465 }
1466
1467 static int alloc_all_mem(struct r8152 *tp)
1468 {
1469 struct net_device *netdev = tp->netdev;
1470 struct usb_interface *intf = tp->intf;
1471 struct usb_host_interface *alt = intf->cur_altsetting;
1472 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1473 struct urb *urb;
1474 int node, i;
1475 u8 *buf;
1476
1477 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1478
1479 spin_lock_init(&tp->rx_lock);
1480 spin_lock_init(&tp->tx_lock);
1481 INIT_LIST_HEAD(&tp->tx_free);
1482 INIT_LIST_HEAD(&tp->rx_done);
1483 skb_queue_head_init(&tp->tx_queue);
1484 skb_queue_head_init(&tp->rx_queue);
1485
1486 for (i = 0; i < RTL8152_MAX_RX; i++) {
1487 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1488 if (!buf)
1489 goto err1;
1490
1491 if (buf != rx_agg_align(buf)) {
1492 kfree(buf);
1493 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1494 node);
1495 if (!buf)
1496 goto err1;
1497 }
1498
1499 urb = usb_alloc_urb(0, GFP_KERNEL);
1500 if (!urb) {
1501 kfree(buf);
1502 goto err1;
1503 }
1504
1505 INIT_LIST_HEAD(&tp->rx_info[i].list);
1506 tp->rx_info[i].context = tp;
1507 tp->rx_info[i].urb = urb;
1508 tp->rx_info[i].buffer = buf;
1509 tp->rx_info[i].head = rx_agg_align(buf);
1510 }
1511
1512 for (i = 0; i < RTL8152_MAX_TX; i++) {
1513 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1514 if (!buf)
1515 goto err1;
1516
1517 if (buf != tx_agg_align(buf)) {
1518 kfree(buf);
1519 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1520 node);
1521 if (!buf)
1522 goto err1;
1523 }
1524
1525 urb = usb_alloc_urb(0, GFP_KERNEL);
1526 if (!urb) {
1527 kfree(buf);
1528 goto err1;
1529 }
1530
1531 INIT_LIST_HEAD(&tp->tx_info[i].list);
1532 tp->tx_info[i].context = tp;
1533 tp->tx_info[i].urb = urb;
1534 tp->tx_info[i].buffer = buf;
1535 tp->tx_info[i].head = tx_agg_align(buf);
1536
1537 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1538 }
1539
1540 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1541 if (!tp->intr_urb)
1542 goto err1;
1543
1544 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1545 if (!tp->intr_buff)
1546 goto err1;
1547
1548 tp->intr_interval = (int)ep_intr->desc.bInterval;
1549 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1550 tp->intr_buff, INTBUFSIZE, intr_callback,
1551 tp, tp->intr_interval);
1552
1553 return 0;
1554
1555 err1:
1556 free_all_mem(tp);
1557 return -ENOMEM;
1558 }
1559
1560 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1561 {
1562 struct tx_agg *agg = NULL;
1563 unsigned long flags;
1564
1565 if (list_empty(&tp->tx_free))
1566 return NULL;
1567
1568 spin_lock_irqsave(&tp->tx_lock, flags);
1569 if (!list_empty(&tp->tx_free)) {
1570 struct list_head *cursor;
1571
1572 cursor = tp->tx_free.next;
1573 list_del_init(cursor);
1574 agg = list_entry(cursor, struct tx_agg, list);
1575 }
1576 spin_unlock_irqrestore(&tp->tx_lock, flags);
1577
1578 return agg;
1579 }
1580
1581 /* r8152_csum_workaround()
1582 * The hw limites the value the transport offset. When the offset is out of the
1583 * range, calculate the checksum by sw.
1584 */
1585 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1586 struct sk_buff_head *list)
1587 {
1588 if (skb_shinfo(skb)->gso_size) {
1589 netdev_features_t features = tp->netdev->features;
1590 struct sk_buff_head seg_list;
1591 struct sk_buff *segs, *nskb;
1592
1593 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1594 segs = skb_gso_segment(skb, features);
1595 if (IS_ERR(segs) || !segs)
1596 goto drop;
1597
1598 __skb_queue_head_init(&seg_list);
1599
1600 do {
1601 nskb = segs;
1602 segs = segs->next;
1603 nskb->next = NULL;
1604 __skb_queue_tail(&seg_list, nskb);
1605 } while (segs);
1606
1607 skb_queue_splice(&seg_list, list);
1608 dev_kfree_skb(skb);
1609 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1610 if (skb_checksum_help(skb) < 0)
1611 goto drop;
1612
1613 __skb_queue_head(list, skb);
1614 } else {
1615 struct net_device_stats *stats;
1616
1617 drop:
1618 stats = &tp->netdev->stats;
1619 stats->tx_dropped++;
1620 dev_kfree_skb(skb);
1621 }
1622 }
1623
1624 /* msdn_giant_send_check()
1625 * According to the document of microsoft, the TCP Pseudo Header excludes the
1626 * packet length for IPv6 TCP large packets.
1627 */
1628 static int msdn_giant_send_check(struct sk_buff *skb)
1629 {
1630 const struct ipv6hdr *ipv6h;
1631 struct tcphdr *th;
1632 int ret;
1633
1634 ret = skb_cow_head(skb, 0);
1635 if (ret)
1636 return ret;
1637
1638 ipv6h = ipv6_hdr(skb);
1639 th = tcp_hdr(skb);
1640
1641 th->check = 0;
1642 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1643
1644 return ret;
1645 }
1646
1647 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1648 {
1649 if (skb_vlan_tag_present(skb)) {
1650 u32 opts2;
1651
1652 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1653 desc->opts2 |= cpu_to_le32(opts2);
1654 }
1655 }
1656
1657 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1658 {
1659 u32 opts2 = le32_to_cpu(desc->opts2);
1660
1661 if (opts2 & RX_VLAN_TAG)
1662 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1663 swab16(opts2 & 0xffff));
1664 }
1665
1666 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1667 struct sk_buff *skb, u32 len, u32 transport_offset)
1668 {
1669 u32 mss = skb_shinfo(skb)->gso_size;
1670 u32 opts1, opts2 = 0;
1671 int ret = TX_CSUM_SUCCESS;
1672
1673 WARN_ON_ONCE(len > TX_LEN_MAX);
1674
1675 opts1 = len | TX_FS | TX_LS;
1676
1677 if (mss) {
1678 if (transport_offset > GTTCPHO_MAX) {
1679 netif_warn(tp, tx_err, tp->netdev,
1680 "Invalid transport offset 0x%x for TSO\n",
1681 transport_offset);
1682 ret = TX_CSUM_TSO;
1683 goto unavailable;
1684 }
1685
1686 switch (vlan_get_protocol(skb)) {
1687 case htons(ETH_P_IP):
1688 opts1 |= GTSENDV4;
1689 break;
1690
1691 case htons(ETH_P_IPV6):
1692 if (msdn_giant_send_check(skb)) {
1693 ret = TX_CSUM_TSO;
1694 goto unavailable;
1695 }
1696 opts1 |= GTSENDV6;
1697 break;
1698
1699 default:
1700 WARN_ON_ONCE(1);
1701 break;
1702 }
1703
1704 opts1 |= transport_offset << GTTCPHO_SHIFT;
1705 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1706 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1707 u8 ip_protocol;
1708
1709 if (transport_offset > TCPHO_MAX) {
1710 netif_warn(tp, tx_err, tp->netdev,
1711 "Invalid transport offset 0x%x\n",
1712 transport_offset);
1713 ret = TX_CSUM_NONE;
1714 goto unavailable;
1715 }
1716
1717 switch (vlan_get_protocol(skb)) {
1718 case htons(ETH_P_IP):
1719 opts2 |= IPV4_CS;
1720 ip_protocol = ip_hdr(skb)->protocol;
1721 break;
1722
1723 case htons(ETH_P_IPV6):
1724 opts2 |= IPV6_CS;
1725 ip_protocol = ipv6_hdr(skb)->nexthdr;
1726 break;
1727
1728 default:
1729 ip_protocol = IPPROTO_RAW;
1730 break;
1731 }
1732
1733 if (ip_protocol == IPPROTO_TCP)
1734 opts2 |= TCP_CS;
1735 else if (ip_protocol == IPPROTO_UDP)
1736 opts2 |= UDP_CS;
1737 else
1738 WARN_ON_ONCE(1);
1739
1740 opts2 |= transport_offset << TCPHO_SHIFT;
1741 }
1742
1743 desc->opts2 = cpu_to_le32(opts2);
1744 desc->opts1 = cpu_to_le32(opts1);
1745
1746 unavailable:
1747 return ret;
1748 }
1749
1750 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1751 {
1752 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1753 int remain, ret;
1754 u8 *tx_data;
1755
1756 __skb_queue_head_init(&skb_head);
1757 spin_lock(&tx_queue->lock);
1758 skb_queue_splice_init(tx_queue, &skb_head);
1759 spin_unlock(&tx_queue->lock);
1760
1761 tx_data = agg->head;
1762 agg->skb_num = 0;
1763 agg->skb_len = 0;
1764 remain = agg_buf_sz;
1765
1766 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1767 struct tx_desc *tx_desc;
1768 struct sk_buff *skb;
1769 unsigned int len;
1770 u32 offset;
1771
1772 skb = __skb_dequeue(&skb_head);
1773 if (!skb)
1774 break;
1775
1776 len = skb->len + sizeof(*tx_desc);
1777
1778 if (len > remain) {
1779 __skb_queue_head(&skb_head, skb);
1780 break;
1781 }
1782
1783 tx_data = tx_agg_align(tx_data);
1784 tx_desc = (struct tx_desc *)tx_data;
1785
1786 offset = (u32)skb_transport_offset(skb);
1787
1788 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1789 r8152_csum_workaround(tp, skb, &skb_head);
1790 continue;
1791 }
1792
1793 rtl_tx_vlan_tag(tx_desc, skb);
1794
1795 tx_data += sizeof(*tx_desc);
1796
1797 len = skb->len;
1798 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1799 struct net_device_stats *stats = &tp->netdev->stats;
1800
1801 stats->tx_dropped++;
1802 dev_kfree_skb_any(skb);
1803 tx_data -= sizeof(*tx_desc);
1804 continue;
1805 }
1806
1807 tx_data += len;
1808 agg->skb_len += len;
1809 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1810
1811 dev_kfree_skb_any(skb);
1812
1813 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1814
1815 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1816 break;
1817 }
1818
1819 if (!skb_queue_empty(&skb_head)) {
1820 spin_lock(&tx_queue->lock);
1821 skb_queue_splice(&skb_head, tx_queue);
1822 spin_unlock(&tx_queue->lock);
1823 }
1824
1825 netif_tx_lock(tp->netdev);
1826
1827 if (netif_queue_stopped(tp->netdev) &&
1828 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1829 netif_wake_queue(tp->netdev);
1830
1831 netif_tx_unlock(tp->netdev);
1832
1833 ret = usb_autopm_get_interface_async(tp->intf);
1834 if (ret < 0)
1835 goto out_tx_fill;
1836
1837 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1838 agg->head, (int)(tx_data - (u8 *)agg->head),
1839 (usb_complete_t)write_bulk_callback, agg);
1840
1841 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1842 if (ret < 0)
1843 usb_autopm_put_interface_async(tp->intf);
1844
1845 out_tx_fill:
1846 return ret;
1847 }
1848
1849 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1850 {
1851 u8 checksum = CHECKSUM_NONE;
1852 u32 opts2, opts3;
1853
1854 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1855 goto return_result;
1856
1857 opts2 = le32_to_cpu(rx_desc->opts2);
1858 opts3 = le32_to_cpu(rx_desc->opts3);
1859
1860 if (opts2 & RD_IPV4_CS) {
1861 if (opts3 & IPF)
1862 checksum = CHECKSUM_NONE;
1863 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1864 checksum = CHECKSUM_NONE;
1865 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1866 checksum = CHECKSUM_NONE;
1867 else
1868 checksum = CHECKSUM_UNNECESSARY;
1869 } else if (opts2 & RD_IPV6_CS) {
1870 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1871 checksum = CHECKSUM_UNNECESSARY;
1872 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1873 checksum = CHECKSUM_UNNECESSARY;
1874 }
1875
1876 return_result:
1877 return checksum;
1878 }
1879
1880 static int rx_bottom(struct r8152 *tp, int budget)
1881 {
1882 unsigned long flags;
1883 struct list_head *cursor, *next, rx_queue;
1884 int ret = 0, work_done = 0;
1885 struct napi_struct *napi = &tp->napi;
1886
1887 if (!skb_queue_empty(&tp->rx_queue)) {
1888 while (work_done < budget) {
1889 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1890 struct net_device *netdev = tp->netdev;
1891 struct net_device_stats *stats = &netdev->stats;
1892 unsigned int pkt_len;
1893
1894 if (!skb)
1895 break;
1896
1897 pkt_len = skb->len;
1898 napi_gro_receive(napi, skb);
1899 work_done++;
1900 stats->rx_packets++;
1901 stats->rx_bytes += pkt_len;
1902 }
1903 }
1904
1905 if (list_empty(&tp->rx_done))
1906 goto out1;
1907
1908 INIT_LIST_HEAD(&rx_queue);
1909 spin_lock_irqsave(&tp->rx_lock, flags);
1910 list_splice_init(&tp->rx_done, &rx_queue);
1911 spin_unlock_irqrestore(&tp->rx_lock, flags);
1912
1913 list_for_each_safe(cursor, next, &rx_queue) {
1914 struct rx_desc *rx_desc;
1915 struct rx_agg *agg;
1916 int len_used = 0;
1917 struct urb *urb;
1918 u8 *rx_data;
1919
1920 list_del_init(cursor);
1921
1922 agg = list_entry(cursor, struct rx_agg, list);
1923 urb = agg->urb;
1924 if (urb->actual_length < ETH_ZLEN)
1925 goto submit;
1926
1927 rx_desc = agg->head;
1928 rx_data = agg->head;
1929 len_used += sizeof(struct rx_desc);
1930
1931 while (urb->actual_length > len_used) {
1932 struct net_device *netdev = tp->netdev;
1933 struct net_device_stats *stats = &netdev->stats;
1934 unsigned int pkt_len;
1935 struct sk_buff *skb;
1936
1937 /* limite the skb numbers for rx_queue */
1938 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1939 break;
1940
1941 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1942 if (pkt_len < ETH_ZLEN)
1943 break;
1944
1945 len_used += pkt_len;
1946 if (urb->actual_length < len_used)
1947 break;
1948
1949 pkt_len -= ETH_FCS_LEN;
1950 rx_data += sizeof(struct rx_desc);
1951
1952 skb = napi_alloc_skb(napi, pkt_len);
1953 if (!skb) {
1954 stats->rx_dropped++;
1955 goto find_next_rx;
1956 }
1957
1958 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1959 memcpy(skb->data, rx_data, pkt_len);
1960 skb_put(skb, pkt_len);
1961 skb->protocol = eth_type_trans(skb, netdev);
1962 rtl_rx_vlan_tag(rx_desc, skb);
1963 if (work_done < budget) {
1964 napi_gro_receive(napi, skb);
1965 work_done++;
1966 stats->rx_packets++;
1967 stats->rx_bytes += pkt_len;
1968 } else {
1969 __skb_queue_tail(&tp->rx_queue, skb);
1970 }
1971
1972 find_next_rx:
1973 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1974 rx_desc = (struct rx_desc *)rx_data;
1975 len_used = (int)(rx_data - (u8 *)agg->head);
1976 len_used += sizeof(struct rx_desc);
1977 }
1978
1979 submit:
1980 if (!ret) {
1981 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1982 } else {
1983 urb->actual_length = 0;
1984 list_add_tail(&agg->list, next);
1985 }
1986 }
1987
1988 if (!list_empty(&rx_queue)) {
1989 spin_lock_irqsave(&tp->rx_lock, flags);
1990 list_splice_tail(&rx_queue, &tp->rx_done);
1991 spin_unlock_irqrestore(&tp->rx_lock, flags);
1992 }
1993
1994 out1:
1995 return work_done;
1996 }
1997
1998 static void tx_bottom(struct r8152 *tp)
1999 {
2000 int res;
2001
2002 do {
2003 struct tx_agg *agg;
2004
2005 if (skb_queue_empty(&tp->tx_queue))
2006 break;
2007
2008 agg = r8152_get_tx_agg(tp);
2009 if (!agg)
2010 break;
2011
2012 res = r8152_tx_agg_fill(tp, agg);
2013 if (res) {
2014 struct net_device *netdev = tp->netdev;
2015
2016 if (res == -ENODEV) {
2017 set_bit(RTL8152_UNPLUG, &tp->flags);
2018 netif_device_detach(netdev);
2019 } else {
2020 struct net_device_stats *stats = &netdev->stats;
2021 unsigned long flags;
2022
2023 netif_warn(tp, tx_err, netdev,
2024 "failed tx_urb %d\n", res);
2025 stats->tx_dropped += agg->skb_num;
2026
2027 spin_lock_irqsave(&tp->tx_lock, flags);
2028 list_add_tail(&agg->list, &tp->tx_free);
2029 spin_unlock_irqrestore(&tp->tx_lock, flags);
2030 }
2031 }
2032 } while (res == 0);
2033 }
2034
2035 static void bottom_half(struct r8152 *tp)
2036 {
2037 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2038 return;
2039
2040 if (!test_bit(WORK_ENABLE, &tp->flags))
2041 return;
2042
2043 /* When link down, the driver would cancel all bulks. */
2044 /* This avoid the re-submitting bulk */
2045 if (!netif_carrier_ok(tp->netdev))
2046 return;
2047
2048 clear_bit(SCHEDULE_NAPI, &tp->flags);
2049
2050 tx_bottom(tp);
2051 }
2052
2053 static int r8152_poll(struct napi_struct *napi, int budget)
2054 {
2055 struct r8152 *tp = container_of(napi, struct r8152, napi);
2056 int work_done;
2057
2058 work_done = rx_bottom(tp, budget);
2059 bottom_half(tp);
2060
2061 if (work_done < budget) {
2062 if (!napi_complete_done(napi, work_done))
2063 goto out;
2064 if (!list_empty(&tp->rx_done))
2065 napi_schedule(napi);
2066 else if (!skb_queue_empty(&tp->tx_queue) &&
2067 !list_empty(&tp->tx_free))
2068 napi_schedule(napi);
2069 }
2070
2071 out:
2072 return work_done;
2073 }
2074
2075 static
2076 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2077 {
2078 int ret;
2079
2080 /* The rx would be stopped, so skip submitting */
2081 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2082 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2083 return 0;
2084
2085 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2086 agg->head, agg_buf_sz,
2087 (usb_complete_t)read_bulk_callback, agg);
2088
2089 ret = usb_submit_urb(agg->urb, mem_flags);
2090 if (ret == -ENODEV) {
2091 set_bit(RTL8152_UNPLUG, &tp->flags);
2092 netif_device_detach(tp->netdev);
2093 } else if (ret) {
2094 struct urb *urb = agg->urb;
2095 unsigned long flags;
2096
2097 urb->actual_length = 0;
2098 spin_lock_irqsave(&tp->rx_lock, flags);
2099 list_add_tail(&agg->list, &tp->rx_done);
2100 spin_unlock_irqrestore(&tp->rx_lock, flags);
2101
2102 netif_err(tp, rx_err, tp->netdev,
2103 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2104
2105 napi_schedule(&tp->napi);
2106 }
2107
2108 return ret;
2109 }
2110
2111 static void rtl_drop_queued_tx(struct r8152 *tp)
2112 {
2113 struct net_device_stats *stats = &tp->netdev->stats;
2114 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2115 struct sk_buff *skb;
2116
2117 if (skb_queue_empty(tx_queue))
2118 return;
2119
2120 __skb_queue_head_init(&skb_head);
2121 spin_lock_bh(&tx_queue->lock);
2122 skb_queue_splice_init(tx_queue, &skb_head);
2123 spin_unlock_bh(&tx_queue->lock);
2124
2125 while ((skb = __skb_dequeue(&skb_head))) {
2126 dev_kfree_skb(skb);
2127 stats->tx_dropped++;
2128 }
2129 }
2130
2131 static void rtl8152_tx_timeout(struct net_device *netdev)
2132 {
2133 struct r8152 *tp = netdev_priv(netdev);
2134
2135 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2136
2137 usb_queue_reset_device(tp->intf);
2138 }
2139
2140 static void rtl8152_set_rx_mode(struct net_device *netdev)
2141 {
2142 struct r8152 *tp = netdev_priv(netdev);
2143
2144 if (netif_carrier_ok(netdev)) {
2145 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2146 schedule_delayed_work(&tp->schedule, 0);
2147 }
2148 }
2149
2150 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2151 {
2152 struct r8152 *tp = netdev_priv(netdev);
2153 u32 mc_filter[2]; /* Multicast hash filter */
2154 __le32 tmp[2];
2155 u32 ocp_data;
2156
2157 netif_stop_queue(netdev);
2158 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2159 ocp_data &= ~RCR_ACPT_ALL;
2160 ocp_data |= RCR_AB | RCR_APM;
2161
2162 if (netdev->flags & IFF_PROMISC) {
2163 /* Unconditionally log net taps. */
2164 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2165 ocp_data |= RCR_AM | RCR_AAP;
2166 mc_filter[1] = 0xffffffff;
2167 mc_filter[0] = 0xffffffff;
2168 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2169 (netdev->flags & IFF_ALLMULTI)) {
2170 /* Too many to filter perfectly -- accept all multicasts. */
2171 ocp_data |= RCR_AM;
2172 mc_filter[1] = 0xffffffff;
2173 mc_filter[0] = 0xffffffff;
2174 } else {
2175 struct netdev_hw_addr *ha;
2176
2177 mc_filter[1] = 0;
2178 mc_filter[0] = 0;
2179 netdev_for_each_mc_addr(ha, netdev) {
2180 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2181
2182 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2183 ocp_data |= RCR_AM;
2184 }
2185 }
2186
2187 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2188 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2189
2190 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2191 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2192 netif_wake_queue(netdev);
2193 }
2194
2195 static netdev_features_t
2196 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2197 netdev_features_t features)
2198 {
2199 u32 mss = skb_shinfo(skb)->gso_size;
2200 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2201 int offset = skb_transport_offset(skb);
2202
2203 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2204 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2205 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2206 features &= ~NETIF_F_GSO_MASK;
2207
2208 return features;
2209 }
2210
2211 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2212 struct net_device *netdev)
2213 {
2214 struct r8152 *tp = netdev_priv(netdev);
2215
2216 skb_tx_timestamp(skb);
2217
2218 skb_queue_tail(&tp->tx_queue, skb);
2219
2220 if (!list_empty(&tp->tx_free)) {
2221 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2222 set_bit(SCHEDULE_NAPI, &tp->flags);
2223 schedule_delayed_work(&tp->schedule, 0);
2224 } else {
2225 usb_mark_last_busy(tp->udev);
2226 napi_schedule(&tp->napi);
2227 }
2228 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2229 netif_stop_queue(netdev);
2230 }
2231
2232 return NETDEV_TX_OK;
2233 }
2234
2235 static void r8152b_reset_packet_filter(struct r8152 *tp)
2236 {
2237 u32 ocp_data;
2238
2239 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2240 ocp_data &= ~FMC_FCR_MCU_EN;
2241 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2242 ocp_data |= FMC_FCR_MCU_EN;
2243 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2244 }
2245
2246 static void rtl8152_nic_reset(struct r8152 *tp)
2247 {
2248 int i;
2249
2250 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2251
2252 for (i = 0; i < 1000; i++) {
2253 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2254 break;
2255 usleep_range(100, 400);
2256 }
2257 }
2258
2259 static void set_tx_qlen(struct r8152 *tp)
2260 {
2261 struct net_device *netdev = tp->netdev;
2262
2263 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2264 sizeof(struct tx_desc));
2265 }
2266
2267 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2268 {
2269 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2270 }
2271
2272 static void rtl_set_eee_plus(struct r8152 *tp)
2273 {
2274 u32 ocp_data;
2275 u8 speed;
2276
2277 speed = rtl8152_get_speed(tp);
2278 if (speed & _10bps) {
2279 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2280 ocp_data |= EEEP_CR_EEEP_TX;
2281 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2282 } else {
2283 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2284 ocp_data &= ~EEEP_CR_EEEP_TX;
2285 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2286 }
2287 }
2288
2289 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2290 {
2291 u32 ocp_data;
2292
2293 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2294 if (enable)
2295 ocp_data |= RXDY_GATED_EN;
2296 else
2297 ocp_data &= ~RXDY_GATED_EN;
2298 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2299 }
2300
2301 static int rtl_start_rx(struct r8152 *tp)
2302 {
2303 int i, ret = 0;
2304
2305 INIT_LIST_HEAD(&tp->rx_done);
2306 for (i = 0; i < RTL8152_MAX_RX; i++) {
2307 INIT_LIST_HEAD(&tp->rx_info[i].list);
2308 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2309 if (ret)
2310 break;
2311 }
2312
2313 if (ret && ++i < RTL8152_MAX_RX) {
2314 struct list_head rx_queue;
2315 unsigned long flags;
2316
2317 INIT_LIST_HEAD(&rx_queue);
2318
2319 do {
2320 struct rx_agg *agg = &tp->rx_info[i++];
2321 struct urb *urb = agg->urb;
2322
2323 urb->actual_length = 0;
2324 list_add_tail(&agg->list, &rx_queue);
2325 } while (i < RTL8152_MAX_RX);
2326
2327 spin_lock_irqsave(&tp->rx_lock, flags);
2328 list_splice_tail(&rx_queue, &tp->rx_done);
2329 spin_unlock_irqrestore(&tp->rx_lock, flags);
2330 }
2331
2332 return ret;
2333 }
2334
2335 static int rtl_stop_rx(struct r8152 *tp)
2336 {
2337 int i;
2338
2339 for (i = 0; i < RTL8152_MAX_RX; i++)
2340 usb_kill_urb(tp->rx_info[i].urb);
2341
2342 while (!skb_queue_empty(&tp->rx_queue))
2343 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2344
2345 return 0;
2346 }
2347
2348 static int rtl_enable(struct r8152 *tp)
2349 {
2350 u32 ocp_data;
2351
2352 r8152b_reset_packet_filter(tp);
2353
2354 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2355 ocp_data |= CR_RE | CR_TE;
2356 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2357
2358 rxdy_gated_en(tp, false);
2359
2360 return 0;
2361 }
2362
2363 static int rtl8152_enable(struct r8152 *tp)
2364 {
2365 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2366 return -ENODEV;
2367
2368 set_tx_qlen(tp);
2369 rtl_set_eee_plus(tp);
2370
2371 return rtl_enable(tp);
2372 }
2373
2374 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2375 {
2376 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2377 OWN_UPDATE | OWN_CLEAR);
2378 }
2379
2380 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2381 {
2382 u32 ocp_data = tp->coalesce / 8;
2383
2384 switch (tp->version) {
2385 case RTL_VER_03:
2386 case RTL_VER_04:
2387 case RTL_VER_05:
2388 case RTL_VER_06:
2389 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2390 ocp_data);
2391 break;
2392
2393 case RTL_VER_08:
2394 case RTL_VER_09:
2395 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2396 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2397 */
2398 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2399 128 / 8);
2400 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2401 ocp_data);
2402 r8153b_rx_agg_chg_indicate(tp);
2403 break;
2404
2405 default:
2406 break;
2407 }
2408 }
2409
2410 static void r8153_set_rx_early_size(struct r8152 *tp)
2411 {
2412 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2413
2414 switch (tp->version) {
2415 case RTL_VER_03:
2416 case RTL_VER_04:
2417 case RTL_VER_05:
2418 case RTL_VER_06:
2419 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2420 ocp_data / 4);
2421 break;
2422 case RTL_VER_08:
2423 case RTL_VER_09:
2424 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2425 ocp_data / 8);
2426 r8153b_rx_agg_chg_indicate(tp);
2427 break;
2428 default:
2429 WARN_ON_ONCE(1);
2430 break;
2431 }
2432 }
2433
2434 static int rtl8153_enable(struct r8152 *tp)
2435 {
2436 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2437 return -ENODEV;
2438
2439 set_tx_qlen(tp);
2440 rtl_set_eee_plus(tp);
2441 r8153_set_rx_early_timeout(tp);
2442 r8153_set_rx_early_size(tp);
2443
2444 return rtl_enable(tp);
2445 }
2446
2447 static void rtl_disable(struct r8152 *tp)
2448 {
2449 u32 ocp_data;
2450 int i;
2451
2452 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2453 rtl_drop_queued_tx(tp);
2454 return;
2455 }
2456
2457 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2458 ocp_data &= ~RCR_ACPT_ALL;
2459 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2460
2461 rtl_drop_queued_tx(tp);
2462
2463 for (i = 0; i < RTL8152_MAX_TX; i++)
2464 usb_kill_urb(tp->tx_info[i].urb);
2465
2466 rxdy_gated_en(tp, true);
2467
2468 for (i = 0; i < 1000; i++) {
2469 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2470 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2471 break;
2472 usleep_range(1000, 2000);
2473 }
2474
2475 for (i = 0; i < 1000; i++) {
2476 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2477 break;
2478 usleep_range(1000, 2000);
2479 }
2480
2481 rtl_stop_rx(tp);
2482
2483 rtl8152_nic_reset(tp);
2484 }
2485
2486 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2487 {
2488 u32 ocp_data;
2489
2490 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2491 if (enable)
2492 ocp_data |= POWER_CUT;
2493 else
2494 ocp_data &= ~POWER_CUT;
2495 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2496
2497 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2498 ocp_data &= ~RESUME_INDICATE;
2499 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2500 }
2501
2502 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2503 {
2504 u32 ocp_data;
2505
2506 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2507 if (enable)
2508 ocp_data |= CPCR_RX_VLAN;
2509 else
2510 ocp_data &= ~CPCR_RX_VLAN;
2511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2512 }
2513
2514 static int rtl8152_set_features(struct net_device *dev,
2515 netdev_features_t features)
2516 {
2517 netdev_features_t changed = features ^ dev->features;
2518 struct r8152 *tp = netdev_priv(dev);
2519 int ret;
2520
2521 ret = usb_autopm_get_interface(tp->intf);
2522 if (ret < 0)
2523 goto out;
2524
2525 mutex_lock(&tp->control);
2526
2527 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2528 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2529 rtl_rx_vlan_en(tp, true);
2530 else
2531 rtl_rx_vlan_en(tp, false);
2532 }
2533
2534 mutex_unlock(&tp->control);
2535
2536 usb_autopm_put_interface(tp->intf);
2537
2538 out:
2539 return ret;
2540 }
2541
2542 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2543
2544 static u32 __rtl_get_wol(struct r8152 *tp)
2545 {
2546 u32 ocp_data;
2547 u32 wolopts = 0;
2548
2549 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2550 if (ocp_data & LINK_ON_WAKE_EN)
2551 wolopts |= WAKE_PHY;
2552
2553 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2554 if (ocp_data & UWF_EN)
2555 wolopts |= WAKE_UCAST;
2556 if (ocp_data & BWF_EN)
2557 wolopts |= WAKE_BCAST;
2558 if (ocp_data & MWF_EN)
2559 wolopts |= WAKE_MCAST;
2560
2561 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2562 if (ocp_data & MAGIC_EN)
2563 wolopts |= WAKE_MAGIC;
2564
2565 return wolopts;
2566 }
2567
2568 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2569 {
2570 u32 ocp_data;
2571
2572 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2573
2574 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2575 ocp_data &= ~LINK_ON_WAKE_EN;
2576 if (wolopts & WAKE_PHY)
2577 ocp_data |= LINK_ON_WAKE_EN;
2578 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2579
2580 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2581 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2582 if (wolopts & WAKE_UCAST)
2583 ocp_data |= UWF_EN;
2584 if (wolopts & WAKE_BCAST)
2585 ocp_data |= BWF_EN;
2586 if (wolopts & WAKE_MCAST)
2587 ocp_data |= MWF_EN;
2588 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2589
2590 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2591
2592 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2593 ocp_data &= ~MAGIC_EN;
2594 if (wolopts & WAKE_MAGIC)
2595 ocp_data |= MAGIC_EN;
2596 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2597
2598 if (wolopts & WAKE_ANY)
2599 device_set_wakeup_enable(&tp->udev->dev, true);
2600 else
2601 device_set_wakeup_enable(&tp->udev->dev, false);
2602 }
2603
2604 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2605 {
2606 /* MAC clock speed down */
2607 if (enable) {
2608 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2609 ALDPS_SPDWN_RATIO);
2610 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2611 EEE_SPDWN_RATIO);
2612 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2613 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2614 U1U2_SPDWN_EN | L1_SPDWN_EN);
2615 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2616 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2617 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2618 TP1000_SPDWN_EN);
2619 } else {
2620 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2621 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2622 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2623 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2624 }
2625 }
2626
2627 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2628 {
2629 u8 u1u2[8];
2630
2631 if (enable)
2632 memset(u1u2, 0xff, sizeof(u1u2));
2633 else
2634 memset(u1u2, 0x00, sizeof(u1u2));
2635
2636 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2637 }
2638
2639 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2640 {
2641 u32 ocp_data;
2642
2643 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2644 if (enable)
2645 ocp_data |= LPM_U1U2_EN;
2646 else
2647 ocp_data &= ~LPM_U1U2_EN;
2648
2649 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2650 }
2651
2652 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2653 {
2654 u32 ocp_data;
2655
2656 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2657 if (enable)
2658 ocp_data |= U2P3_ENABLE;
2659 else
2660 ocp_data &= ~U2P3_ENABLE;
2661 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2662 }
2663
2664 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2665 {
2666 u32 ocp_data;
2667
2668 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2669 ocp_data &= ~clear;
2670 ocp_data |= set;
2671 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2672 }
2673
2674 static void r8153b_green_en(struct r8152 *tp, bool enable)
2675 {
2676 u16 data;
2677
2678 if (enable) {
2679 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
2680 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2681 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2682 } else {
2683 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2684 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2685 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2686 }
2687
2688 data = sram_read(tp, SRAM_GREEN_CFG);
2689 data |= GREEN_ETH_EN;
2690 sram_write(tp, SRAM_GREEN_CFG, data);
2691
2692 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2693 }
2694
2695 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2696 {
2697 u16 data;
2698 int i;
2699
2700 for (i = 0; i < 500; i++) {
2701 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2702 data &= PHY_STAT_MASK;
2703 if (desired) {
2704 if (data == desired)
2705 break;
2706 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2707 data == PHY_STAT_EXT_INIT) {
2708 break;
2709 }
2710
2711 msleep(20);
2712 }
2713
2714 return data;
2715 }
2716
2717 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2718 {
2719 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2720
2721 if (enable) {
2722 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2723 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2724
2725 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2726 ocp_data |= BIT(0);
2727 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2728 } else {
2729 u16 data;
2730
2731 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2732 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2733
2734 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2735 ocp_data &= ~BIT(0);
2736 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2737
2738 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2739 ocp_data &= ~PCUT_STATUS;
2740 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2741
2742 data = r8153_phy_status(tp, 0);
2743
2744 switch (data) {
2745 case PHY_STAT_PWRDN:
2746 case PHY_STAT_EXT_INIT:
2747 r8153b_green_en(tp,
2748 test_bit(GREEN_ETHERNET, &tp->flags));
2749
2750 data = r8152_mdio_read(tp, MII_BMCR);
2751 data &= ~BMCR_PDOWN;
2752 data |= BMCR_RESET;
2753 r8152_mdio_write(tp, MII_BMCR, data);
2754
2755 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2756
2757 default:
2758 if (data != PHY_STAT_LAN_ON)
2759 netif_warn(tp, link, tp->netdev,
2760 "PHY not ready");
2761 break;
2762 }
2763 }
2764 }
2765
2766 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2767 {
2768 u32 ocp_data;
2769
2770 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2771 if (enable)
2772 ocp_data |= PWR_EN | PHASE2_EN;
2773 else
2774 ocp_data &= ~(PWR_EN | PHASE2_EN);
2775 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2776
2777 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2778 ocp_data &= ~PCUT_STATUS;
2779 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2780 }
2781
2782 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2783 {
2784 u32 ocp_data;
2785
2786 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2787 if (enable)
2788 ocp_data |= PWR_EN | PHASE2_EN;
2789 else
2790 ocp_data &= ~PWR_EN;
2791 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2792
2793 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2794 ocp_data &= ~PCUT_STATUS;
2795 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2796 }
2797
2798 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2799 {
2800 u32 ocp_data;
2801
2802 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2803 if (enable)
2804 ocp_data |= BIT(0);
2805 else
2806 ocp_data &= ~BIT(0);
2807 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2808
2809 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2810 ocp_data &= ~BIT(0);
2811 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2812 }
2813
2814 static bool rtl_can_wakeup(struct r8152 *tp)
2815 {
2816 struct usb_device *udev = tp->udev;
2817
2818 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2819 }
2820
2821 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2822 {
2823 if (enable) {
2824 u32 ocp_data;
2825
2826 __rtl_set_wol(tp, WAKE_ANY);
2827
2828 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2829
2830 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2831 ocp_data |= LINK_OFF_WAKE_EN;
2832 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2833
2834 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2835 } else {
2836 u32 ocp_data;
2837
2838 __rtl_set_wol(tp, tp->saved_wolopts);
2839
2840 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2841
2842 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2843 ocp_data &= ~LINK_OFF_WAKE_EN;
2844 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2845
2846 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2847 }
2848 }
2849
2850 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2851 {
2852 if (enable) {
2853 r8153_u1u2en(tp, false);
2854 r8153_u2p3en(tp, false);
2855 r8153_mac_clk_spd(tp, true);
2856 rtl_runtime_suspend_enable(tp, true);
2857 } else {
2858 rtl_runtime_suspend_enable(tp, false);
2859 r8153_mac_clk_spd(tp, false);
2860
2861 switch (tp->version) {
2862 case RTL_VER_03:
2863 case RTL_VER_04:
2864 break;
2865 case RTL_VER_05:
2866 case RTL_VER_06:
2867 default:
2868 r8153_u2p3en(tp, true);
2869 break;
2870 }
2871
2872 r8153_u1u2en(tp, true);
2873 }
2874 }
2875
2876 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2877 {
2878 if (enable) {
2879 r8153b_queue_wake(tp, true);
2880 r8153b_u1u2en(tp, false);
2881 r8153_u2p3en(tp, false);
2882 rtl_runtime_suspend_enable(tp, true);
2883 r8153b_ups_en(tp, true);
2884 } else {
2885 r8153b_ups_en(tp, false);
2886 r8153b_queue_wake(tp, false);
2887 rtl_runtime_suspend_enable(tp, false);
2888 r8153_u2p3en(tp, true);
2889 r8153b_u1u2en(tp, true);
2890 }
2891 }
2892
2893 static void r8153_teredo_off(struct r8152 *tp)
2894 {
2895 u32 ocp_data;
2896
2897 switch (tp->version) {
2898 case RTL_VER_01:
2899 case RTL_VER_02:
2900 case RTL_VER_03:
2901 case RTL_VER_04:
2902 case RTL_VER_05:
2903 case RTL_VER_06:
2904 case RTL_VER_07:
2905 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2906 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2907 OOB_TEREDO_EN);
2908 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2909 break;
2910
2911 case RTL_VER_08:
2912 case RTL_VER_09:
2913 /* The bit 0 ~ 7 are relative with teredo settings. They are
2914 * W1C (write 1 to clear), so set all 1 to disable it.
2915 */
2916 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2917 break;
2918
2919 default:
2920 break;
2921 }
2922
2923 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2924 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2925 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2926 }
2927
2928 static void rtl_reset_bmu(struct r8152 *tp)
2929 {
2930 u32 ocp_data;
2931
2932 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2933 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2934 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2935 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2936 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2937 }
2938
2939 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2940 {
2941 if (enable) {
2942 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2943 LINKENA | DIS_SDSAVE);
2944 } else {
2945 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2946 DIS_SDSAVE);
2947 msleep(20);
2948 }
2949 }
2950
2951 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2952 {
2953 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2954 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2955 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2956 }
2957
2958 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2959 {
2960 u16 data;
2961
2962 r8152_mmd_indirect(tp, dev, reg);
2963 data = ocp_reg_read(tp, OCP_EEE_DATA);
2964 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2965
2966 return data;
2967 }
2968
2969 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2970 {
2971 r8152_mmd_indirect(tp, dev, reg);
2972 ocp_reg_write(tp, OCP_EEE_DATA, data);
2973 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2974 }
2975
2976 static void r8152_eee_en(struct r8152 *tp, bool enable)
2977 {
2978 u16 config1, config2, config3;
2979 u32 ocp_data;
2980
2981 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2982 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2983 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2984 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2985
2986 if (enable) {
2987 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2988 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2989 config1 |= sd_rise_time(1);
2990 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2991 config3 |= fast_snr(42);
2992 } else {
2993 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2994 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2995 RX_QUIET_EN);
2996 config1 |= sd_rise_time(7);
2997 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2998 config3 |= fast_snr(511);
2999 }
3000
3001 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3002 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3003 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3004 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3005 }
3006
3007 static void r8152b_enable_eee(struct r8152 *tp)
3008 {
3009 r8152_eee_en(tp, true);
3010 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3011 }
3012
3013 static void r8152b_enable_fc(struct r8152 *tp)
3014 {
3015 u16 anar;
3016
3017 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3018 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3019 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3020 }
3021
3022 static void rtl8152_disable(struct r8152 *tp)
3023 {
3024 r8152_aldps_en(tp, false);
3025 rtl_disable(tp);
3026 r8152_aldps_en(tp, true);
3027 }
3028
3029 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3030 {
3031 r8152b_enable_eee(tp);
3032 r8152_aldps_en(tp, true);
3033 r8152b_enable_fc(tp);
3034
3035 set_bit(PHY_RESET, &tp->flags);
3036 }
3037
3038 static void r8152b_exit_oob(struct r8152 *tp)
3039 {
3040 u32 ocp_data;
3041 int i;
3042
3043 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3044 ocp_data &= ~RCR_ACPT_ALL;
3045 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3046
3047 rxdy_gated_en(tp, true);
3048 r8153_teredo_off(tp);
3049 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3050 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3051
3052 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3053 ocp_data &= ~NOW_IS_OOB;
3054 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3055
3056 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3057 ocp_data &= ~MCU_BORW_EN;
3058 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3059
3060 for (i = 0; i < 1000; i++) {
3061 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3062 if (ocp_data & LINK_LIST_READY)
3063 break;
3064 usleep_range(1000, 2000);
3065 }
3066
3067 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3068 ocp_data |= RE_INIT_LL;
3069 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3070
3071 for (i = 0; i < 1000; i++) {
3072 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3073 if (ocp_data & LINK_LIST_READY)
3074 break;
3075 usleep_range(1000, 2000);
3076 }
3077
3078 rtl8152_nic_reset(tp);
3079
3080 /* rx share fifo credit full threshold */
3081 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3082
3083 if (tp->udev->speed == USB_SPEED_FULL ||
3084 tp->udev->speed == USB_SPEED_LOW) {
3085 /* rx share fifo credit near full threshold */
3086 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3087 RXFIFO_THR2_FULL);
3088 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3089 RXFIFO_THR3_FULL);
3090 } else {
3091 /* rx share fifo credit near full threshold */
3092 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3093 RXFIFO_THR2_HIGH);
3094 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3095 RXFIFO_THR3_HIGH);
3096 }
3097
3098 /* TX share fifo free credit full threshold */
3099 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3100
3101 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3102 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3103 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3104 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3105
3106 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3107
3108 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3109
3110 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3111 ocp_data |= TCR0_AUTO_FIFO;
3112 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3113 }
3114
3115 static void r8152b_enter_oob(struct r8152 *tp)
3116 {
3117 u32 ocp_data;
3118 int i;
3119
3120 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3121 ocp_data &= ~NOW_IS_OOB;
3122 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3123
3124 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3125 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3126 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3127
3128 rtl_disable(tp);
3129
3130 for (i = 0; i < 1000; i++) {
3131 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3132 if (ocp_data & LINK_LIST_READY)
3133 break;
3134 usleep_range(1000, 2000);
3135 }
3136
3137 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3138 ocp_data |= RE_INIT_LL;
3139 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3140
3141 for (i = 0; i < 1000; i++) {
3142 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3143 if (ocp_data & LINK_LIST_READY)
3144 break;
3145 usleep_range(1000, 2000);
3146 }
3147
3148 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3149
3150 rtl_rx_vlan_en(tp, true);
3151
3152 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3153 ocp_data |= ALDPS_PROXY_MODE;
3154 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3155
3156 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3157 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3158 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3159
3160 rxdy_gated_en(tp, false);
3161
3162 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3163 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3164 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3165 }
3166
3167 static int r8153_patch_request(struct r8152 *tp, bool request)
3168 {
3169 u16 data;
3170 int i;
3171
3172 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3173 if (request)
3174 data |= PATCH_REQUEST;
3175 else
3176 data &= ~PATCH_REQUEST;
3177 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3178
3179 for (i = 0; request && i < 5000; i++) {
3180 usleep_range(1000, 2000);
3181 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3182 break;
3183 }
3184
3185 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3186 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3187 r8153_patch_request(tp, false);
3188 return -ETIME;
3189 } else {
3190 return 0;
3191 }
3192 }
3193
3194 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3195 {
3196 u16 data;
3197
3198 data = ocp_reg_read(tp, OCP_POWER_CFG);
3199 if (enable) {
3200 data |= EN_ALDPS;
3201 ocp_reg_write(tp, OCP_POWER_CFG, data);
3202 } else {
3203 int i;
3204
3205 data &= ~EN_ALDPS;
3206 ocp_reg_write(tp, OCP_POWER_CFG, data);
3207 for (i = 0; i < 20; i++) {
3208 usleep_range(1000, 2000);
3209 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3210 break;
3211 }
3212 }
3213 }
3214
3215 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3216 {
3217 r8153_aldps_en(tp, enable);
3218
3219 if (enable)
3220 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3221 else
3222 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3223 }
3224
3225 static void r8153_eee_en(struct r8152 *tp, bool enable)
3226 {
3227 u32 ocp_data;
3228 u16 config;
3229
3230 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3231 config = ocp_reg_read(tp, OCP_EEE_CFG);
3232
3233 if (enable) {
3234 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3235 config |= EEE10_EN;
3236 } else {
3237 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3238 config &= ~EEE10_EN;
3239 }
3240
3241 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3242 ocp_reg_write(tp, OCP_EEE_CFG, config);
3243 }
3244
3245 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3246 {
3247 r8153_eee_en(tp, enable);
3248
3249 if (enable)
3250 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3251 else
3252 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3253 }
3254
3255 static void r8153b_enable_fc(struct r8152 *tp)
3256 {
3257 r8152b_enable_fc(tp);
3258 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3259 }
3260
3261 static void r8153_hw_phy_cfg(struct r8152 *tp)
3262 {
3263 u32 ocp_data;
3264 u16 data;
3265
3266 /* disable ALDPS before updating the PHY parameters */
3267 r8153_aldps_en(tp, false);
3268
3269 /* disable EEE before updating the PHY parameters */
3270 r8153_eee_en(tp, false);
3271 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3272
3273 if (tp->version == RTL_VER_03) {
3274 data = ocp_reg_read(tp, OCP_EEE_CFG);
3275 data &= ~CTAP_SHORT_EN;
3276 ocp_reg_write(tp, OCP_EEE_CFG, data);
3277 }
3278
3279 data = ocp_reg_read(tp, OCP_POWER_CFG);
3280 data |= EEE_CLKDIV_EN;
3281 ocp_reg_write(tp, OCP_POWER_CFG, data);
3282
3283 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3284 data |= EN_10M_BGOFF;
3285 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3286 data = ocp_reg_read(tp, OCP_POWER_CFG);
3287 data |= EN_10M_PLLOFF;
3288 ocp_reg_write(tp, OCP_POWER_CFG, data);
3289 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3290
3291 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3292 ocp_data |= PFM_PWM_SWITCH;
3293 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3294
3295 /* Enable LPF corner auto tune */
3296 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3297
3298 /* Adjust 10M Amplitude */
3299 sram_write(tp, SRAM_10M_AMP1, 0x00af);
3300 sram_write(tp, SRAM_10M_AMP2, 0x0208);
3301
3302 r8153_eee_en(tp, true);
3303 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3304
3305 r8153_aldps_en(tp, true);
3306 r8152b_enable_fc(tp);
3307
3308 switch (tp->version) {
3309 case RTL_VER_03:
3310 case RTL_VER_04:
3311 break;
3312 case RTL_VER_05:
3313 case RTL_VER_06:
3314 default:
3315 r8153_u2p3en(tp, true);
3316 break;
3317 }
3318
3319 set_bit(PHY_RESET, &tp->flags);
3320 }
3321
3322 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3323 {
3324 u32 ocp_data;
3325
3326 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3328 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
3329 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3330
3331 return ocp_data;
3332 }
3333
3334 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3335 {
3336 u32 ocp_data, ups_flags = 0;
3337 u16 data;
3338
3339 /* disable ALDPS before updating the PHY parameters */
3340 r8153b_aldps_en(tp, false);
3341
3342 /* disable EEE before updating the PHY parameters */
3343 r8153b_eee_en(tp, false);
3344 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3345
3346 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3347
3348 data = sram_read(tp, SRAM_GREEN_CFG);
3349 data |= R_TUNE_EN;
3350 sram_write(tp, SRAM_GREEN_CFG, data);
3351 data = ocp_reg_read(tp, OCP_NCTL_CFG);
3352 data |= PGA_RETURN_EN;
3353 ocp_reg_write(tp, OCP_NCTL_CFG, data);
3354
3355 /* ADC Bias Calibration:
3356 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3357 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3358 * ADC ioffset.
3359 */
3360 ocp_data = r8152_efuse_read(tp, 0x7d);
3361 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3362 if (data != 0xffff)
3363 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3364
3365 /* ups mode tx-link-pulse timing adjustment:
3366 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3367 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3368 */
3369 ocp_data = ocp_reg_read(tp, 0xc426);
3370 ocp_data &= 0x3fff;
3371 if (ocp_data) {
3372 u32 swr_cnt_1ms_ini;
3373
3374 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3375 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3376 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3377 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3378 }
3379
3380 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3381 ocp_data |= PFM_PWM_SWITCH;
3382 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3383
3384 /* Advnace EEE */
3385 if (!r8153_patch_request(tp, true)) {
3386 data = ocp_reg_read(tp, OCP_POWER_CFG);
3387 data |= EEE_CLKDIV_EN;
3388 ocp_reg_write(tp, OCP_POWER_CFG, data);
3389
3390 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3391 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3392 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3393
3394 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3395 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3396
3397 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3398 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3399 UPS_FLAGS_EEE_PLLOFF_GIGA;
3400
3401 r8153_patch_request(tp, false);
3402 }
3403
3404 r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3405
3406 r8153b_eee_en(tp, true);
3407 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3408
3409 r8153b_aldps_en(tp, true);
3410 r8153b_enable_fc(tp);
3411 r8153_u2p3en(tp, true);
3412
3413 set_bit(PHY_RESET, &tp->flags);
3414 }
3415
3416 static void r8153_first_init(struct r8152 *tp)
3417 {
3418 u32 ocp_data;
3419 int i;
3420
3421 r8153_mac_clk_spd(tp, false);
3422 rxdy_gated_en(tp, true);
3423 r8153_teredo_off(tp);
3424
3425 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3426 ocp_data &= ~RCR_ACPT_ALL;
3427 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3428
3429 rtl8152_nic_reset(tp);
3430 rtl_reset_bmu(tp);
3431
3432 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3433 ocp_data &= ~NOW_IS_OOB;
3434 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3435
3436 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3437 ocp_data &= ~MCU_BORW_EN;
3438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3439
3440 for (i = 0; i < 1000; i++) {
3441 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3442 if (ocp_data & LINK_LIST_READY)
3443 break;
3444 usleep_range(1000, 2000);
3445 }
3446
3447 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3448 ocp_data |= RE_INIT_LL;
3449 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3450
3451 for (i = 0; i < 1000; i++) {
3452 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3453 if (ocp_data & LINK_LIST_READY)
3454 break;
3455 usleep_range(1000, 2000);
3456 }
3457
3458 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3459
3460 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3461 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3462 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3463
3464 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3465 ocp_data |= TCR0_AUTO_FIFO;
3466 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3467
3468 rtl8152_nic_reset(tp);
3469
3470 /* rx share fifo credit full threshold */
3471 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3473 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3474 /* TX share fifo free credit full threshold */
3475 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3476 }
3477
3478 static void r8153_enter_oob(struct r8152 *tp)
3479 {
3480 u32 ocp_data;
3481 int i;
3482
3483 r8153_mac_clk_spd(tp, true);
3484
3485 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3486 ocp_data &= ~NOW_IS_OOB;
3487 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3488
3489 rtl_disable(tp);
3490 rtl_reset_bmu(tp);
3491
3492 for (i = 0; i < 1000; i++) {
3493 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3494 if (ocp_data & LINK_LIST_READY)
3495 break;
3496 usleep_range(1000, 2000);
3497 }
3498
3499 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3500 ocp_data |= RE_INIT_LL;
3501 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3502
3503 for (i = 0; i < 1000; i++) {
3504 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3505 if (ocp_data & LINK_LIST_READY)
3506 break;
3507 usleep_range(1000, 2000);
3508 }
3509
3510 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3512
3513 switch (tp->version) {
3514 case RTL_VER_03:
3515 case RTL_VER_04:
3516 case RTL_VER_05:
3517 case RTL_VER_06:
3518 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3519 ocp_data &= ~TEREDO_WAKE_MASK;
3520 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3521 break;
3522
3523 case RTL_VER_08:
3524 case RTL_VER_09:
3525 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3526 * type. Set it to zero. bits[7:0] are the W1C bits about
3527 * the events. Set them to all 1 to clear them.
3528 */
3529 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3530 break;
3531
3532 default:
3533 break;
3534 }
3535
3536 rtl_rx_vlan_en(tp, true);
3537
3538 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3539 ocp_data |= ALDPS_PROXY_MODE;
3540 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3541
3542 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3543 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3544 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3545
3546 rxdy_gated_en(tp, false);
3547
3548 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3549 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3550 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3551 }
3552
3553 static void rtl8153_disable(struct r8152 *tp)
3554 {
3555 r8153_aldps_en(tp, false);
3556 rtl_disable(tp);
3557 rtl_reset_bmu(tp);
3558 r8153_aldps_en(tp, true);
3559 }
3560
3561 static void rtl8153b_disable(struct r8152 *tp)
3562 {
3563 r8153b_aldps_en(tp, false);
3564 rtl_disable(tp);
3565 rtl_reset_bmu(tp);
3566 r8153b_aldps_en(tp, true);
3567 }
3568
3569 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3570 {
3571 u16 bmcr, anar, gbcr;
3572 enum spd_duplex speed_duplex;
3573 int ret = 0;
3574
3575 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3576 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3577 ADVERTISE_100HALF | ADVERTISE_100FULL);
3578 if (tp->mii.supports_gmii) {
3579 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3580 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3581 } else {
3582 gbcr = 0;
3583 }
3584
3585 if (autoneg == AUTONEG_DISABLE) {
3586 if (speed == SPEED_10) {
3587 bmcr = 0;
3588 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3589 speed_duplex = FORCE_10M_HALF;
3590 } else if (speed == SPEED_100) {
3591 bmcr = BMCR_SPEED100;
3592 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3593 speed_duplex = FORCE_100M_HALF;
3594 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3595 bmcr = BMCR_SPEED1000;
3596 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3597 speed_duplex = NWAY_1000M_FULL;
3598 } else {
3599 ret = -EINVAL;
3600 goto out;
3601 }
3602
3603 if (duplex == DUPLEX_FULL) {
3604 bmcr |= BMCR_FULLDPLX;
3605 if (speed != SPEED_1000)
3606 speed_duplex++;
3607 }
3608 } else {
3609 if (speed == SPEED_10) {
3610 if (duplex == DUPLEX_FULL) {
3611 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3612 speed_duplex = NWAY_10M_FULL;
3613 } else {
3614 anar |= ADVERTISE_10HALF;
3615 speed_duplex = NWAY_10M_HALF;
3616 }
3617 } else if (speed == SPEED_100) {
3618 if (duplex == DUPLEX_FULL) {
3619 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3620 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3621 speed_duplex = NWAY_100M_FULL;
3622 } else {
3623 anar |= ADVERTISE_10HALF;
3624 anar |= ADVERTISE_100HALF;
3625 speed_duplex = NWAY_100M_HALF;
3626 }
3627 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3628 if (duplex == DUPLEX_FULL) {
3629 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3630 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3631 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3632 } else {
3633 anar |= ADVERTISE_10HALF;
3634 anar |= ADVERTISE_100HALF;
3635 gbcr |= ADVERTISE_1000HALF;
3636 }
3637 speed_duplex = NWAY_1000M_FULL;
3638 } else {
3639 ret = -EINVAL;
3640 goto out;
3641 }
3642
3643 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3644 }
3645
3646 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3647 bmcr |= BMCR_RESET;
3648
3649 if (tp->mii.supports_gmii)
3650 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3651
3652 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3653 r8152_mdio_write(tp, MII_BMCR, bmcr);
3654
3655 switch (tp->version) {
3656 case RTL_VER_08:
3657 case RTL_VER_09:
3658 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3659 UPS_FLAGS_SPEED_MASK);
3660 break;
3661
3662 default:
3663 break;
3664 }
3665
3666 if (bmcr & BMCR_RESET) {
3667 int i;
3668
3669 for (i = 0; i < 50; i++) {
3670 msleep(20);
3671 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3672 break;
3673 }
3674 }
3675
3676 out:
3677 return ret;
3678 }
3679
3680 static void rtl8152_up(struct r8152 *tp)
3681 {
3682 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3683 return;
3684
3685 r8152_aldps_en(tp, false);
3686 r8152b_exit_oob(tp);
3687 r8152_aldps_en(tp, true);
3688 }
3689
3690 static void rtl8152_down(struct r8152 *tp)
3691 {
3692 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3693 rtl_drop_queued_tx(tp);
3694 return;
3695 }
3696
3697 r8152_power_cut_en(tp, false);
3698 r8152_aldps_en(tp, false);
3699 r8152b_enter_oob(tp);
3700 r8152_aldps_en(tp, true);
3701 }
3702
3703 static void rtl8153_up(struct r8152 *tp)
3704 {
3705 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3706 return;
3707
3708 r8153_u1u2en(tp, false);
3709 r8153_u2p3en(tp, false);
3710 r8153_aldps_en(tp, false);
3711 r8153_first_init(tp);
3712 r8153_aldps_en(tp, true);
3713
3714 switch (tp->version) {
3715 case RTL_VER_03:
3716 case RTL_VER_04:
3717 break;
3718 case RTL_VER_05:
3719 case RTL_VER_06:
3720 default:
3721 r8153_u2p3en(tp, true);
3722 break;
3723 }
3724
3725 r8153_u1u2en(tp, true);
3726 }
3727
3728 static void rtl8153_down(struct r8152 *tp)
3729 {
3730 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3731 rtl_drop_queued_tx(tp);
3732 return;
3733 }
3734
3735 r8153_u1u2en(tp, false);
3736 r8153_u2p3en(tp, false);
3737 r8153_power_cut_en(tp, false);
3738 r8153_aldps_en(tp, false);
3739 r8153_enter_oob(tp);
3740 r8153_aldps_en(tp, true);
3741 }
3742
3743 static void rtl8153b_up(struct r8152 *tp)
3744 {
3745 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3746 return;
3747
3748 r8153b_u1u2en(tp, false);
3749 r8153_u2p3en(tp, false);
3750 r8153b_aldps_en(tp, false);
3751
3752 r8153_first_init(tp);
3753 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3754
3755 r8153b_aldps_en(tp, true);
3756 r8153_u2p3en(tp, true);
3757 r8153b_u1u2en(tp, true);
3758 }
3759
3760 static void rtl8153b_down(struct r8152 *tp)
3761 {
3762 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3763 rtl_drop_queued_tx(tp);
3764 return;
3765 }
3766
3767 r8153b_u1u2en(tp, false);
3768 r8153_u2p3en(tp, false);
3769 r8153b_power_cut_en(tp, false);
3770 r8153b_aldps_en(tp, false);
3771 r8153_enter_oob(tp);
3772 r8153b_aldps_en(tp, true);
3773 }
3774
3775 static bool rtl8152_in_nway(struct r8152 *tp)
3776 {
3777 u16 nway_state;
3778
3779 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3780 tp->ocp_base = 0x2000;
3781 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3782 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3783
3784 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3785 if (nway_state & 0xc000)
3786 return false;
3787 else
3788 return true;
3789 }
3790
3791 static bool rtl8153_in_nway(struct r8152 *tp)
3792 {
3793 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3794
3795 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3796 return false;
3797 else
3798 return true;
3799 }
3800
3801 static void set_carrier(struct r8152 *tp)
3802 {
3803 struct net_device *netdev = tp->netdev;
3804 struct napi_struct *napi = &tp->napi;
3805 u8 speed;
3806
3807 speed = rtl8152_get_speed(tp);
3808
3809 if (speed & LINK_STATUS) {
3810 if (!netif_carrier_ok(netdev)) {
3811 tp->rtl_ops.enable(tp);
3812 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
3813 netif_stop_queue(netdev);
3814 napi_disable(napi);
3815 netif_carrier_on(netdev);
3816 rtl_start_rx(tp);
3817 napi_enable(&tp->napi);
3818 netif_wake_queue(netdev);
3819 netif_info(tp, link, netdev, "carrier on\n");
3820 } else if (netif_queue_stopped(netdev) &&
3821 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3822 netif_wake_queue(netdev);
3823 }
3824 } else {
3825 if (netif_carrier_ok(netdev)) {
3826 netif_carrier_off(netdev);
3827 napi_disable(napi);
3828 tp->rtl_ops.disable(tp);
3829 napi_enable(napi);
3830 netif_info(tp, link, netdev, "carrier off\n");
3831 }
3832 }
3833 }
3834
3835 static void rtl_work_func_t(struct work_struct *work)
3836 {
3837 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3838
3839 /* If the device is unplugged or !netif_running(), the workqueue
3840 * doesn't need to wake the device, and could return directly.
3841 */
3842 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3843 return;
3844
3845 if (usb_autopm_get_interface(tp->intf) < 0)
3846 return;
3847
3848 if (!test_bit(WORK_ENABLE, &tp->flags))
3849 goto out1;
3850
3851 if (!mutex_trylock(&tp->control)) {
3852 schedule_delayed_work(&tp->schedule, 0);
3853 goto out1;
3854 }
3855
3856 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3857 set_carrier(tp);
3858
3859 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3860 _rtl8152_set_rx_mode(tp->netdev);
3861
3862 /* don't schedule napi before linking */
3863 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3864 netif_carrier_ok(tp->netdev))
3865 napi_schedule(&tp->napi);
3866
3867 mutex_unlock(&tp->control);
3868
3869 out1:
3870 usb_autopm_put_interface(tp->intf);
3871 }
3872
3873 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3874 {
3875 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3876
3877 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3878 return;
3879
3880 if (usb_autopm_get_interface(tp->intf) < 0)
3881 return;
3882
3883 mutex_lock(&tp->control);
3884
3885 tp->rtl_ops.hw_phy_cfg(tp);
3886
3887 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3888
3889 mutex_unlock(&tp->control);
3890
3891 usb_autopm_put_interface(tp->intf);
3892 }
3893
3894 #ifdef CONFIG_PM_SLEEP
3895 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3896 void *data)
3897 {
3898 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3899
3900 switch (action) {
3901 case PM_HIBERNATION_PREPARE:
3902 case PM_SUSPEND_PREPARE:
3903 usb_autopm_get_interface(tp->intf);
3904 break;
3905
3906 case PM_POST_HIBERNATION:
3907 case PM_POST_SUSPEND:
3908 usb_autopm_put_interface(tp->intf);
3909 break;
3910
3911 case PM_POST_RESTORE:
3912 case PM_RESTORE_PREPARE:
3913 default:
3914 break;
3915 }
3916
3917 return NOTIFY_DONE;
3918 }
3919 #endif
3920
3921 static int rtl8152_open(struct net_device *netdev)
3922 {
3923 struct r8152 *tp = netdev_priv(netdev);
3924 int res = 0;
3925
3926 res = alloc_all_mem(tp);
3927 if (res)
3928 goto out;
3929
3930 res = usb_autopm_get_interface(tp->intf);
3931 if (res < 0)
3932 goto out_free;
3933
3934 mutex_lock(&tp->control);
3935
3936 tp->rtl_ops.up(tp);
3937
3938 netif_carrier_off(netdev);
3939 netif_start_queue(netdev);
3940 set_bit(WORK_ENABLE, &tp->flags);
3941
3942 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3943 if (res) {
3944 if (res == -ENODEV)
3945 netif_device_detach(tp->netdev);
3946 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3947 res);
3948 goto out_unlock;
3949 }
3950 napi_enable(&tp->napi);
3951
3952 mutex_unlock(&tp->control);
3953
3954 usb_autopm_put_interface(tp->intf);
3955 #ifdef CONFIG_PM_SLEEP
3956 tp->pm_notifier.notifier_call = rtl_notifier;
3957 register_pm_notifier(&tp->pm_notifier);
3958 #endif
3959 return 0;
3960
3961 out_unlock:
3962 mutex_unlock(&tp->control);
3963 usb_autopm_put_interface(tp->intf);
3964 out_free:
3965 free_all_mem(tp);
3966 out:
3967 return res;
3968 }
3969
3970 static int rtl8152_close(struct net_device *netdev)
3971 {
3972 struct r8152 *tp = netdev_priv(netdev);
3973 int res = 0;
3974
3975 #ifdef CONFIG_PM_SLEEP
3976 unregister_pm_notifier(&tp->pm_notifier);
3977 #endif
3978 if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3979 napi_disable(&tp->napi);
3980 clear_bit(WORK_ENABLE, &tp->flags);
3981 usb_kill_urb(tp->intr_urb);
3982 cancel_delayed_work_sync(&tp->schedule);
3983 netif_stop_queue(netdev);
3984
3985 res = usb_autopm_get_interface(tp->intf);
3986 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3987 rtl_drop_queued_tx(tp);
3988 rtl_stop_rx(tp);
3989 } else {
3990 mutex_lock(&tp->control);
3991
3992 tp->rtl_ops.down(tp);
3993
3994 mutex_unlock(&tp->control);
3995
3996 usb_autopm_put_interface(tp->intf);
3997 }
3998
3999 free_all_mem(tp);
4000
4001 return res;
4002 }
4003
4004 static void rtl_tally_reset(struct r8152 *tp)
4005 {
4006 u32 ocp_data;
4007
4008 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4009 ocp_data |= TALLY_RESET;
4010 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4011 }
4012
4013 static void r8152b_init(struct r8152 *tp)
4014 {
4015 u32 ocp_data;
4016 u16 data;
4017
4018 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4019 return;
4020
4021 data = r8152_mdio_read(tp, MII_BMCR);
4022 if (data & BMCR_PDOWN) {
4023 data &= ~BMCR_PDOWN;
4024 r8152_mdio_write(tp, MII_BMCR, data);
4025 }
4026
4027 r8152_aldps_en(tp, false);
4028
4029 if (tp->version == RTL_VER_01) {
4030 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4031 ocp_data &= ~LED_MODE_MASK;
4032 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4033 }
4034
4035 r8152_power_cut_en(tp, false);
4036
4037 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4038 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4039 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4040 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4041 ocp_data &= ~MCU_CLK_RATIO_MASK;
4042 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4043 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4044 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4045 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4046 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4047
4048 rtl_tally_reset(tp);
4049
4050 /* enable rx aggregation */
4051 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4052 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4053 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4054 }
4055
4056 static void r8153_init(struct r8152 *tp)
4057 {
4058 u32 ocp_data;
4059 u16 data;
4060 int i;
4061
4062 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4063 return;
4064
4065 r8153_u1u2en(tp, false);
4066
4067 for (i = 0; i < 500; i++) {
4068 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4069 AUTOLOAD_DONE)
4070 break;
4071 msleep(20);
4072 }
4073
4074 data = r8153_phy_status(tp, 0);
4075
4076 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4077 tp->version == RTL_VER_05)
4078 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4079
4080 data = r8152_mdio_read(tp, MII_BMCR);
4081 if (data & BMCR_PDOWN) {
4082 data &= ~BMCR_PDOWN;
4083 r8152_mdio_write(tp, MII_BMCR, data);
4084 }
4085
4086 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4087
4088 r8153_u2p3en(tp, false);
4089
4090 if (tp->version == RTL_VER_04) {
4091 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4092 ocp_data &= ~pwd_dn_scale_mask;
4093 ocp_data |= pwd_dn_scale(96);
4094 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4095
4096 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4097 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4098 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4099 } else if (tp->version == RTL_VER_05) {
4100 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4101 ocp_data &= ~ECM_ALDPS;
4102 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4103
4104 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4105 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4106 ocp_data &= ~DYNAMIC_BURST;
4107 else
4108 ocp_data |= DYNAMIC_BURST;
4109 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4110 } else if (tp->version == RTL_VER_06) {
4111 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4112 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4113 ocp_data &= ~DYNAMIC_BURST;
4114 else
4115 ocp_data |= DYNAMIC_BURST;
4116 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4117 }
4118
4119 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4120 ocp_data |= EP4_FULL_FC;
4121 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4122
4123 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4124 ocp_data &= ~TIMER11_EN;
4125 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4126
4127 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4128 ocp_data &= ~LED_MODE_MASK;
4129 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4130
4131 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4132 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4133 ocp_data |= LPM_TIMER_500MS;
4134 else
4135 ocp_data |= LPM_TIMER_500US;
4136 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4137
4138 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4139 ocp_data &= ~SEN_VAL_MASK;
4140 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4141 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4142
4143 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4144
4145 r8153_power_cut_en(tp, false);
4146 r8153_u1u2en(tp, true);
4147 r8153_mac_clk_spd(tp, false);
4148 usb_enable_lpm(tp->udev);
4149
4150 /* rx aggregation */
4151 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4152 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4153 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4154 ocp_data |= RX_AGG_DISABLE;
4155
4156 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4157
4158 rtl_tally_reset(tp);
4159
4160 switch (tp->udev->speed) {
4161 case USB_SPEED_SUPER:
4162 case USB_SPEED_SUPER_PLUS:
4163 tp->coalesce = COALESCE_SUPER;
4164 break;
4165 case USB_SPEED_HIGH:
4166 tp->coalesce = COALESCE_HIGH;
4167 break;
4168 default:
4169 tp->coalesce = COALESCE_SLOW;
4170 break;
4171 }
4172 }
4173
4174 static void r8153b_init(struct r8152 *tp)
4175 {
4176 u32 ocp_data;
4177 u16 data;
4178 int i;
4179
4180 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4181 return;
4182
4183 r8153b_u1u2en(tp, false);
4184
4185 for (i = 0; i < 500; i++) {
4186 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4187 AUTOLOAD_DONE)
4188 break;
4189 msleep(20);
4190 }
4191
4192 data = r8153_phy_status(tp, 0);
4193
4194 data = r8152_mdio_read(tp, MII_BMCR);
4195 if (data & BMCR_PDOWN) {
4196 data &= ~BMCR_PDOWN;
4197 r8152_mdio_write(tp, MII_BMCR, data);
4198 }
4199
4200 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4201
4202 r8153_u2p3en(tp, false);
4203
4204 /* MSC timer = 0xfff * 8ms = 32760 ms */
4205 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4206
4207 /* U1/U2/L1 idle timer. 500 us */
4208 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4209
4210 r8153b_power_cut_en(tp, false);
4211 r8153b_ups_en(tp, false);
4212 r8153b_queue_wake(tp, false);
4213 rtl_runtime_suspend_enable(tp, false);
4214 r8153b_u1u2en(tp, true);
4215 usb_enable_lpm(tp->udev);
4216
4217 /* MAC clock speed down */
4218 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4219 ocp_data |= MAC_CLK_SPDWN_EN;
4220 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4221
4222 set_bit(GREEN_ETHERNET, &tp->flags);
4223
4224 /* rx aggregation */
4225 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4226 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4227 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4228
4229 rtl_tally_reset(tp);
4230
4231 tp->coalesce = 15000; /* 15 us */
4232 }
4233
4234 static int rtl8152_pre_reset(struct usb_interface *intf)
4235 {
4236 struct r8152 *tp = usb_get_intfdata(intf);
4237 struct net_device *netdev;
4238
4239 if (!tp)
4240 return 0;
4241
4242 netdev = tp->netdev;
4243 if (!netif_running(netdev))
4244 return 0;
4245
4246 netif_stop_queue(netdev);
4247 napi_disable(&tp->napi);
4248 clear_bit(WORK_ENABLE, &tp->flags);
4249 usb_kill_urb(tp->intr_urb);
4250 cancel_delayed_work_sync(&tp->schedule);
4251 if (netif_carrier_ok(netdev)) {
4252 mutex_lock(&tp->control);
4253 tp->rtl_ops.disable(tp);
4254 mutex_unlock(&tp->control);
4255 }
4256
4257 return 0;
4258 }
4259
4260 static int rtl8152_post_reset(struct usb_interface *intf)
4261 {
4262 struct r8152 *tp = usb_get_intfdata(intf);
4263 struct net_device *netdev;
4264
4265 if (!tp)
4266 return 0;
4267
4268 netdev = tp->netdev;
4269 if (!netif_running(netdev))
4270 return 0;
4271
4272 set_bit(WORK_ENABLE, &tp->flags);
4273 if (netif_carrier_ok(netdev)) {
4274 mutex_lock(&tp->control);
4275 tp->rtl_ops.enable(tp);
4276 rtl_start_rx(tp);
4277 rtl8152_set_rx_mode(netdev);
4278 mutex_unlock(&tp->control);
4279 }
4280
4281 napi_enable(&tp->napi);
4282 netif_wake_queue(netdev);
4283 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4284
4285 if (!list_empty(&tp->rx_done))
4286 napi_schedule(&tp->napi);
4287
4288 return 0;
4289 }
4290
4291 static bool delay_autosuspend(struct r8152 *tp)
4292 {
4293 bool sw_linking = !!netif_carrier_ok(tp->netdev);
4294 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4295
4296 /* This means a linking change occurs and the driver doesn't detect it,
4297 * yet. If the driver has disabled tx/rx and hw is linking on, the
4298 * device wouldn't wake up by receiving any packet.
4299 */
4300 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4301 return true;
4302
4303 /* If the linking down is occurred by nway, the device may miss the
4304 * linking change event. And it wouldn't wake when linking on.
4305 */
4306 if (!sw_linking && tp->rtl_ops.in_nway(tp))
4307 return true;
4308 else if (!skb_queue_empty(&tp->tx_queue))
4309 return true;
4310 else
4311 return false;
4312 }
4313
4314 static int rtl8152_runtime_resume(struct r8152 *tp)
4315 {
4316 struct net_device *netdev = tp->netdev;
4317
4318 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4319 struct napi_struct *napi = &tp->napi;
4320
4321 tp->rtl_ops.autosuspend_en(tp, false);
4322 napi_disable(napi);
4323 set_bit(WORK_ENABLE, &tp->flags);
4324
4325 if (netif_carrier_ok(netdev)) {
4326 if (rtl8152_get_speed(tp) & LINK_STATUS) {
4327 rtl_start_rx(tp);
4328 } else {
4329 netif_carrier_off(netdev);
4330 tp->rtl_ops.disable(tp);
4331 netif_info(tp, link, netdev, "linking down\n");
4332 }
4333 }
4334
4335 napi_enable(napi);
4336 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4337 smp_mb__after_atomic();
4338
4339 if (!list_empty(&tp->rx_done))
4340 napi_schedule(&tp->napi);
4341
4342 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4343 } else {
4344 if (netdev->flags & IFF_UP)
4345 tp->rtl_ops.autosuspend_en(tp, false);
4346
4347 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4348 }
4349
4350 return 0;
4351 }
4352
4353 static int rtl8152_system_resume(struct r8152 *tp)
4354 {
4355 struct net_device *netdev = tp->netdev;
4356
4357 netif_device_attach(netdev);
4358
4359 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4360 tp->rtl_ops.up(tp);
4361 netif_carrier_off(netdev);
4362 set_bit(WORK_ENABLE, &tp->flags);
4363 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4364 }
4365
4366 return 0;
4367 }
4368
4369 static int rtl8152_runtime_suspend(struct r8152 *tp)
4370 {
4371 struct net_device *netdev = tp->netdev;
4372 int ret = 0;
4373
4374 set_bit(SELECTIVE_SUSPEND, &tp->flags);
4375 smp_mb__after_atomic();
4376
4377 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4378 u32 rcr = 0;
4379
4380 if (netif_carrier_ok(netdev)) {
4381 u32 ocp_data;
4382
4383 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4384 ocp_data = rcr & ~RCR_ACPT_ALL;
4385 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4386 rxdy_gated_en(tp, true);
4387 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4388 PLA_OOB_CTRL);
4389 if (!(ocp_data & RXFIFO_EMPTY)) {
4390 rxdy_gated_en(tp, false);
4391 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4392 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4393 smp_mb__after_atomic();
4394 ret = -EBUSY;
4395 goto out1;
4396 }
4397 }
4398
4399 clear_bit(WORK_ENABLE, &tp->flags);
4400 usb_kill_urb(tp->intr_urb);
4401
4402 tp->rtl_ops.autosuspend_en(tp, true);
4403
4404 if (netif_carrier_ok(netdev)) {
4405 struct napi_struct *napi = &tp->napi;
4406
4407 napi_disable(napi);
4408 rtl_stop_rx(tp);
4409 rxdy_gated_en(tp, false);
4410 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4411 napi_enable(napi);
4412 }
4413
4414 if (delay_autosuspend(tp)) {
4415 rtl8152_runtime_resume(tp);
4416 ret = -EBUSY;
4417 }
4418 }
4419
4420 out1:
4421 return ret;
4422 }
4423
4424 static int rtl8152_system_suspend(struct r8152 *tp)
4425 {
4426 struct net_device *netdev = tp->netdev;
4427 int ret = 0;
4428
4429 netif_device_detach(netdev);
4430
4431 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4432 struct napi_struct *napi = &tp->napi;
4433
4434 clear_bit(WORK_ENABLE, &tp->flags);
4435 usb_kill_urb(tp->intr_urb);
4436 napi_disable(napi);
4437 cancel_delayed_work_sync(&tp->schedule);
4438 tp->rtl_ops.down(tp);
4439 napi_enable(napi);
4440 }
4441
4442 return ret;
4443 }
4444
4445 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4446 {
4447 struct r8152 *tp = usb_get_intfdata(intf);
4448 int ret;
4449
4450 mutex_lock(&tp->control);
4451
4452 if (PMSG_IS_AUTO(message))
4453 ret = rtl8152_runtime_suspend(tp);
4454 else
4455 ret = rtl8152_system_suspend(tp);
4456
4457 mutex_unlock(&tp->control);
4458
4459 return ret;
4460 }
4461
4462 static int rtl8152_resume(struct usb_interface *intf)
4463 {
4464 struct r8152 *tp = usb_get_intfdata(intf);
4465 int ret;
4466
4467 mutex_lock(&tp->control);
4468
4469 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4470 ret = rtl8152_runtime_resume(tp);
4471 else
4472 ret = rtl8152_system_resume(tp);
4473
4474 mutex_unlock(&tp->control);
4475
4476 return ret;
4477 }
4478
4479 static int rtl8152_reset_resume(struct usb_interface *intf)
4480 {
4481 struct r8152 *tp = usb_get_intfdata(intf);
4482
4483 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4484 mutex_lock(&tp->control);
4485 tp->rtl_ops.init(tp);
4486 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4487 mutex_unlock(&tp->control);
4488 return rtl8152_resume(intf);
4489 }
4490
4491 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4492 {
4493 struct r8152 *tp = netdev_priv(dev);
4494
4495 if (usb_autopm_get_interface(tp->intf) < 0)
4496 return;
4497
4498 if (!rtl_can_wakeup(tp)) {
4499 wol->supported = 0;
4500 wol->wolopts = 0;
4501 } else {
4502 mutex_lock(&tp->control);
4503 wol->supported = WAKE_ANY;
4504 wol->wolopts = __rtl_get_wol(tp);
4505 mutex_unlock(&tp->control);
4506 }
4507
4508 usb_autopm_put_interface(tp->intf);
4509 }
4510
4511 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4512 {
4513 struct r8152 *tp = netdev_priv(dev);
4514 int ret;
4515
4516 if (!rtl_can_wakeup(tp))
4517 return -EOPNOTSUPP;
4518
4519 ret = usb_autopm_get_interface(tp->intf);
4520 if (ret < 0)
4521 goto out_set_wol;
4522
4523 mutex_lock(&tp->control);
4524
4525 __rtl_set_wol(tp, wol->wolopts);
4526 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4527
4528 mutex_unlock(&tp->control);
4529
4530 usb_autopm_put_interface(tp->intf);
4531
4532 out_set_wol:
4533 return ret;
4534 }
4535
4536 static u32 rtl8152_get_msglevel(struct net_device *dev)
4537 {
4538 struct r8152 *tp = netdev_priv(dev);
4539
4540 return tp->msg_enable;
4541 }
4542
4543 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4544 {
4545 struct r8152 *tp = netdev_priv(dev);
4546
4547 tp->msg_enable = value;
4548 }
4549
4550 static void rtl8152_get_drvinfo(struct net_device *netdev,
4551 struct ethtool_drvinfo *info)
4552 {
4553 struct r8152 *tp = netdev_priv(netdev);
4554
4555 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4556 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4557 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4558 }
4559
4560 static
4561 int rtl8152_get_link_ksettings(struct net_device *netdev,
4562 struct ethtool_link_ksettings *cmd)
4563 {
4564 struct r8152 *tp = netdev_priv(netdev);
4565 int ret;
4566
4567 if (!tp->mii.mdio_read)
4568 return -EOPNOTSUPP;
4569
4570 ret = usb_autopm_get_interface(tp->intf);
4571 if (ret < 0)
4572 goto out;
4573
4574 mutex_lock(&tp->control);
4575
4576 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4577
4578 mutex_unlock(&tp->control);
4579
4580 usb_autopm_put_interface(tp->intf);
4581
4582 out:
4583 return ret;
4584 }
4585
4586 static int rtl8152_set_link_ksettings(struct net_device *dev,
4587 const struct ethtool_link_ksettings *cmd)
4588 {
4589 struct r8152 *tp = netdev_priv(dev);
4590 int ret;
4591
4592 ret = usb_autopm_get_interface(tp->intf);
4593 if (ret < 0)
4594 goto out;
4595
4596 mutex_lock(&tp->control);
4597
4598 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4599 cmd->base.duplex);
4600 if (!ret) {
4601 tp->autoneg = cmd->base.autoneg;
4602 tp->speed = cmd->base.speed;
4603 tp->duplex = cmd->base.duplex;
4604 }
4605
4606 mutex_unlock(&tp->control);
4607
4608 usb_autopm_put_interface(tp->intf);
4609
4610 out:
4611 return ret;
4612 }
4613
4614 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4615 "tx_packets",
4616 "rx_packets",
4617 "tx_errors",
4618 "rx_errors",
4619 "rx_missed",
4620 "align_errors",
4621 "tx_single_collisions",
4622 "tx_multi_collisions",
4623 "rx_unicast",
4624 "rx_broadcast",
4625 "rx_multicast",
4626 "tx_aborted",
4627 "tx_underrun",
4628 };
4629
4630 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4631 {
4632 switch (sset) {
4633 case ETH_SS_STATS:
4634 return ARRAY_SIZE(rtl8152_gstrings);
4635 default:
4636 return -EOPNOTSUPP;
4637 }
4638 }
4639
4640 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4641 struct ethtool_stats *stats, u64 *data)
4642 {
4643 struct r8152 *tp = netdev_priv(dev);
4644 struct tally_counter tally;
4645
4646 if (usb_autopm_get_interface(tp->intf) < 0)
4647 return;
4648
4649 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4650
4651 usb_autopm_put_interface(tp->intf);
4652
4653 data[0] = le64_to_cpu(tally.tx_packets);
4654 data[1] = le64_to_cpu(tally.rx_packets);
4655 data[2] = le64_to_cpu(tally.tx_errors);
4656 data[3] = le32_to_cpu(tally.rx_errors);
4657 data[4] = le16_to_cpu(tally.rx_missed);
4658 data[5] = le16_to_cpu(tally.align_errors);
4659 data[6] = le32_to_cpu(tally.tx_one_collision);
4660 data[7] = le32_to_cpu(tally.tx_multi_collision);
4661 data[8] = le64_to_cpu(tally.rx_unicast);
4662 data[9] = le64_to_cpu(tally.rx_broadcast);
4663 data[10] = le32_to_cpu(tally.rx_multicast);
4664 data[11] = le16_to_cpu(tally.tx_aborted);
4665 data[12] = le16_to_cpu(tally.tx_underrun);
4666 }
4667
4668 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4669 {
4670 switch (stringset) {
4671 case ETH_SS_STATS:
4672 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4673 break;
4674 }
4675 }
4676
4677 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4678 {
4679 u32 ocp_data, lp, adv, supported = 0;
4680 u16 val;
4681
4682 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4683 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4684
4685 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4686 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4687
4688 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4689 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4690
4691 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4692 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4693
4694 eee->eee_enabled = !!ocp_data;
4695 eee->eee_active = !!(supported & adv & lp);
4696 eee->supported = supported;
4697 eee->advertised = adv;
4698 eee->lp_advertised = lp;
4699
4700 return 0;
4701 }
4702
4703 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4704 {
4705 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4706
4707 r8152_eee_en(tp, eee->eee_enabled);
4708
4709 if (!eee->eee_enabled)
4710 val = 0;
4711
4712 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4713
4714 return 0;
4715 }
4716
4717 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4718 {
4719 u32 ocp_data, lp, adv, supported = 0;
4720 u16 val;
4721
4722 val = ocp_reg_read(tp, OCP_EEE_ABLE);
4723 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4724
4725 val = ocp_reg_read(tp, OCP_EEE_ADV);
4726 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4727
4728 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4729 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4730
4731 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4732 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4733
4734 eee->eee_enabled = !!ocp_data;
4735 eee->eee_active = !!(supported & adv & lp);
4736 eee->supported = supported;
4737 eee->advertised = adv;
4738 eee->lp_advertised = lp;
4739
4740 return 0;
4741 }
4742
4743 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4744 {
4745 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4746
4747 r8153_eee_en(tp, eee->eee_enabled);
4748
4749 if (!eee->eee_enabled)
4750 val = 0;
4751
4752 ocp_reg_write(tp, OCP_EEE_ADV, val);
4753
4754 return 0;
4755 }
4756
4757 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4758 {
4759 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4760
4761 r8153b_eee_en(tp, eee->eee_enabled);
4762
4763 if (!eee->eee_enabled)
4764 val = 0;
4765
4766 ocp_reg_write(tp, OCP_EEE_ADV, val);
4767
4768 return 0;
4769 }
4770
4771 static int
4772 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4773 {
4774 struct r8152 *tp = netdev_priv(net);
4775 int ret;
4776
4777 ret = usb_autopm_get_interface(tp->intf);
4778 if (ret < 0)
4779 goto out;
4780
4781 mutex_lock(&tp->control);
4782
4783 ret = tp->rtl_ops.eee_get(tp, edata);
4784
4785 mutex_unlock(&tp->control);
4786
4787 usb_autopm_put_interface(tp->intf);
4788
4789 out:
4790 return ret;
4791 }
4792
4793 static int
4794 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4795 {
4796 struct r8152 *tp = netdev_priv(net);
4797 int ret;
4798
4799 ret = usb_autopm_get_interface(tp->intf);
4800 if (ret < 0)
4801 goto out;
4802
4803 mutex_lock(&tp->control);
4804
4805 ret = tp->rtl_ops.eee_set(tp, edata);
4806 if (!ret)
4807 ret = mii_nway_restart(&tp->mii);
4808
4809 mutex_unlock(&tp->control);
4810
4811 usb_autopm_put_interface(tp->intf);
4812
4813 out:
4814 return ret;
4815 }
4816
4817 static int rtl8152_nway_reset(struct net_device *dev)
4818 {
4819 struct r8152 *tp = netdev_priv(dev);
4820 int ret;
4821
4822 ret = usb_autopm_get_interface(tp->intf);
4823 if (ret < 0)
4824 goto out;
4825
4826 mutex_lock(&tp->control);
4827
4828 ret = mii_nway_restart(&tp->mii);
4829
4830 mutex_unlock(&tp->control);
4831
4832 usb_autopm_put_interface(tp->intf);
4833
4834 out:
4835 return ret;
4836 }
4837
4838 static int rtl8152_get_coalesce(struct net_device *netdev,
4839 struct ethtool_coalesce *coalesce)
4840 {
4841 struct r8152 *tp = netdev_priv(netdev);
4842
4843 switch (tp->version) {
4844 case RTL_VER_01:
4845 case RTL_VER_02:
4846 case RTL_VER_07:
4847 return -EOPNOTSUPP;
4848 default:
4849 break;
4850 }
4851
4852 coalesce->rx_coalesce_usecs = tp->coalesce;
4853
4854 return 0;
4855 }
4856
4857 static int rtl8152_set_coalesce(struct net_device *netdev,
4858 struct ethtool_coalesce *coalesce)
4859 {
4860 struct r8152 *tp = netdev_priv(netdev);
4861 int ret;
4862
4863 switch (tp->version) {
4864 case RTL_VER_01:
4865 case RTL_VER_02:
4866 case RTL_VER_07:
4867 return -EOPNOTSUPP;
4868 default:
4869 break;
4870 }
4871
4872 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4873 return -EINVAL;
4874
4875 ret = usb_autopm_get_interface(tp->intf);
4876 if (ret < 0)
4877 return ret;
4878
4879 mutex_lock(&tp->control);
4880
4881 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4882 tp->coalesce = coalesce->rx_coalesce_usecs;
4883
4884 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4885 r8153_set_rx_early_timeout(tp);
4886 }
4887
4888 mutex_unlock(&tp->control);
4889
4890 usb_autopm_put_interface(tp->intf);
4891
4892 return ret;
4893 }
4894
4895 static const struct ethtool_ops ops = {
4896 .get_drvinfo = rtl8152_get_drvinfo,
4897 .get_link = ethtool_op_get_link,
4898 .nway_reset = rtl8152_nway_reset,
4899 .get_msglevel = rtl8152_get_msglevel,
4900 .set_msglevel = rtl8152_set_msglevel,
4901 .get_wol = rtl8152_get_wol,
4902 .set_wol = rtl8152_set_wol,
4903 .get_strings = rtl8152_get_strings,
4904 .get_sset_count = rtl8152_get_sset_count,
4905 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4906 .get_coalesce = rtl8152_get_coalesce,
4907 .set_coalesce = rtl8152_set_coalesce,
4908 .get_eee = rtl_ethtool_get_eee,
4909 .set_eee = rtl_ethtool_set_eee,
4910 .get_link_ksettings = rtl8152_get_link_ksettings,
4911 .set_link_ksettings = rtl8152_set_link_ksettings,
4912 };
4913
4914 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4915 {
4916 struct r8152 *tp = netdev_priv(netdev);
4917 struct mii_ioctl_data *data = if_mii(rq);
4918 int res;
4919
4920 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4921 return -ENODEV;
4922
4923 res = usb_autopm_get_interface(tp->intf);
4924 if (res < 0)
4925 goto out;
4926
4927 switch (cmd) {
4928 case SIOCGMIIPHY:
4929 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4930 break;
4931
4932 case SIOCGMIIREG:
4933 mutex_lock(&tp->control);
4934 data->val_out = r8152_mdio_read(tp, data->reg_num);
4935 mutex_unlock(&tp->control);
4936 break;
4937
4938 case SIOCSMIIREG:
4939 if (!capable(CAP_NET_ADMIN)) {
4940 res = -EPERM;
4941 break;
4942 }
4943 mutex_lock(&tp->control);
4944 r8152_mdio_write(tp, data->reg_num, data->val_in);
4945 mutex_unlock(&tp->control);
4946 break;
4947
4948 default:
4949 res = -EOPNOTSUPP;
4950 }
4951
4952 usb_autopm_put_interface(tp->intf);
4953
4954 out:
4955 return res;
4956 }
4957
4958 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4959 {
4960 struct r8152 *tp = netdev_priv(dev);
4961 int ret;
4962
4963 switch (tp->version) {
4964 case RTL_VER_01:
4965 case RTL_VER_02:
4966 case RTL_VER_07:
4967 dev->mtu = new_mtu;
4968 return 0;
4969 default:
4970 break;
4971 }
4972
4973 ret = usb_autopm_get_interface(tp->intf);
4974 if (ret < 0)
4975 return ret;
4976
4977 mutex_lock(&tp->control);
4978
4979 dev->mtu = new_mtu;
4980
4981 if (netif_running(dev)) {
4982 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4983
4984 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4985
4986 if (netif_carrier_ok(dev))
4987 r8153_set_rx_early_size(tp);
4988 }
4989
4990 mutex_unlock(&tp->control);
4991
4992 usb_autopm_put_interface(tp->intf);
4993
4994 return ret;
4995 }
4996
4997 static const struct net_device_ops rtl8152_netdev_ops = {
4998 .ndo_open = rtl8152_open,
4999 .ndo_stop = rtl8152_close,
5000 .ndo_do_ioctl = rtl8152_ioctl,
5001 .ndo_start_xmit = rtl8152_start_xmit,
5002 .ndo_tx_timeout = rtl8152_tx_timeout,
5003 .ndo_set_features = rtl8152_set_features,
5004 .ndo_set_rx_mode = rtl8152_set_rx_mode,
5005 .ndo_set_mac_address = rtl8152_set_mac_address,
5006 .ndo_change_mtu = rtl8152_change_mtu,
5007 .ndo_validate_addr = eth_validate_addr,
5008 .ndo_features_check = rtl8152_features_check,
5009 };
5010
5011 static void rtl8152_unload(struct r8152 *tp)
5012 {
5013 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5014 return;
5015
5016 if (tp->version != RTL_VER_01)
5017 r8152_power_cut_en(tp, true);
5018 }
5019
5020 static void rtl8153_unload(struct r8152 *tp)
5021 {
5022 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5023 return;
5024
5025 r8153_power_cut_en(tp, false);
5026 }
5027
5028 static void rtl8153b_unload(struct r8152 *tp)
5029 {
5030 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5031 return;
5032
5033 r8153b_power_cut_en(tp, false);
5034 }
5035
5036 static int rtl_ops_init(struct r8152 *tp)
5037 {
5038 struct rtl_ops *ops = &tp->rtl_ops;
5039 int ret = 0;
5040
5041 switch (tp->version) {
5042 case RTL_VER_01:
5043 case RTL_VER_02:
5044 case RTL_VER_07:
5045 ops->init = r8152b_init;
5046 ops->enable = rtl8152_enable;
5047 ops->disable = rtl8152_disable;
5048 ops->up = rtl8152_up;
5049 ops->down = rtl8152_down;
5050 ops->unload = rtl8152_unload;
5051 ops->eee_get = r8152_get_eee;
5052 ops->eee_set = r8152_set_eee;
5053 ops->in_nway = rtl8152_in_nway;
5054 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
5055 ops->autosuspend_en = rtl_runtime_suspend_enable;
5056 break;
5057
5058 case RTL_VER_03:
5059 case RTL_VER_04:
5060 case RTL_VER_05:
5061 case RTL_VER_06:
5062 ops->init = r8153_init;
5063 ops->enable = rtl8153_enable;
5064 ops->disable = rtl8153_disable;
5065 ops->up = rtl8153_up;
5066 ops->down = rtl8153_down;
5067 ops->unload = rtl8153_unload;
5068 ops->eee_get = r8153_get_eee;
5069 ops->eee_set = r8153_set_eee;
5070 ops->in_nway = rtl8153_in_nway;
5071 ops->hw_phy_cfg = r8153_hw_phy_cfg;
5072 ops->autosuspend_en = rtl8153_runtime_enable;
5073 break;
5074
5075 case RTL_VER_08:
5076 case RTL_VER_09:
5077 ops->init = r8153b_init;
5078 ops->enable = rtl8153_enable;
5079 ops->disable = rtl8153b_disable;
5080 ops->up = rtl8153b_up;
5081 ops->down = rtl8153b_down;
5082 ops->unload = rtl8153b_unload;
5083 ops->eee_get = r8153_get_eee;
5084 ops->eee_set = r8153b_set_eee;
5085 ops->in_nway = rtl8153_in_nway;
5086 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
5087 ops->autosuspend_en = rtl8153b_runtime_enable;
5088 break;
5089
5090 default:
5091 ret = -ENODEV;
5092 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5093 break;
5094 }
5095
5096 return ret;
5097 }
5098
5099 static u8 rtl_get_version(struct usb_interface *intf)
5100 {
5101 struct usb_device *udev = interface_to_usbdev(intf);
5102 u32 ocp_data = 0;
5103 __le32 *tmp;
5104 u8 version;
5105 int ret;
5106
5107 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5108 if (!tmp)
5109 return 0;
5110
5111 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5112 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5113 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5114 if (ret > 0)
5115 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5116
5117 kfree(tmp);
5118
5119 switch (ocp_data) {
5120 case 0x4c00:
5121 version = RTL_VER_01;
5122 break;
5123 case 0x4c10:
5124 version = RTL_VER_02;
5125 break;
5126 case 0x5c00:
5127 version = RTL_VER_03;
5128 break;
5129 case 0x5c10:
5130 version = RTL_VER_04;
5131 break;
5132 case 0x5c20:
5133 version = RTL_VER_05;
5134 break;
5135 case 0x5c30:
5136 version = RTL_VER_06;
5137 break;
5138 case 0x4800:
5139 version = RTL_VER_07;
5140 break;
5141 case 0x6000:
5142 version = RTL_VER_08;
5143 break;
5144 case 0x6010:
5145 version = RTL_VER_09;
5146 break;
5147 default:
5148 version = RTL_VER_UNKNOWN;
5149 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5150 break;
5151 }
5152
5153 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5154
5155 return version;
5156 }
5157
5158 static int rtl8152_probe(struct usb_interface *intf,
5159 const struct usb_device_id *id)
5160 {
5161 struct usb_device *udev = interface_to_usbdev(intf);
5162 u8 version = rtl_get_version(intf);
5163 struct r8152 *tp;
5164 struct net_device *netdev;
5165 int ret;
5166
5167 if (version == RTL_VER_UNKNOWN)
5168 return -ENODEV;
5169
5170 if (udev->actconfig->desc.bConfigurationValue != 1) {
5171 usb_driver_set_configuration(udev, 1);
5172 return -ENODEV;
5173 }
5174
5175 usb_reset_device(udev);
5176 netdev = alloc_etherdev(sizeof(struct r8152));
5177 if (!netdev) {
5178 dev_err(&intf->dev, "Out of memory\n");
5179 return -ENOMEM;
5180 }
5181
5182 SET_NETDEV_DEV(netdev, &intf->dev);
5183 tp = netdev_priv(netdev);
5184 tp->msg_enable = 0x7FFF;
5185
5186 tp->udev = udev;
5187 tp->netdev = netdev;
5188 tp->intf = intf;
5189 tp->version = version;
5190
5191 switch (version) {
5192 case RTL_VER_01:
5193 case RTL_VER_02:
5194 case RTL_VER_07:
5195 tp->mii.supports_gmii = 0;
5196 break;
5197 default:
5198 tp->mii.supports_gmii = 1;
5199 break;
5200 }
5201
5202 ret = rtl_ops_init(tp);
5203 if (ret)
5204 goto out;
5205
5206 mutex_init(&tp->control);
5207 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5208 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5209
5210 netdev->netdev_ops = &rtl8152_netdev_ops;
5211 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5212
5213 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5214 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5215 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5216 NETIF_F_HW_VLAN_CTAG_TX;
5217 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5218 NETIF_F_TSO | NETIF_F_FRAGLIST |
5219 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5220 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5221 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5222 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5223 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5224
5225 if (tp->version == RTL_VER_01) {
5226 netdev->features &= ~NETIF_F_RXCSUM;
5227 netdev->hw_features &= ~NETIF_F_RXCSUM;
5228 }
5229
5230 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5231 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5232 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5233 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5234 }
5235
5236 netdev->ethtool_ops = &ops;
5237 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5238
5239 /* MTU range: 68 - 1500 or 9194 */
5240 netdev->min_mtu = ETH_MIN_MTU;
5241 switch (tp->version) {
5242 case RTL_VER_01:
5243 case RTL_VER_02:
5244 netdev->max_mtu = ETH_DATA_LEN;
5245 break;
5246 default:
5247 netdev->max_mtu = RTL8153_MAX_MTU;
5248 break;
5249 }
5250
5251 tp->mii.dev = netdev;
5252 tp->mii.mdio_read = read_mii_word;
5253 tp->mii.mdio_write = write_mii_word;
5254 tp->mii.phy_id_mask = 0x3f;
5255 tp->mii.reg_num_mask = 0x1f;
5256 tp->mii.phy_id = R8152_PHY_ID;
5257
5258 tp->autoneg = AUTONEG_ENABLE;
5259 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5260 tp->duplex = DUPLEX_FULL;
5261
5262 intf->needs_remote_wakeup = 1;
5263
5264 tp->rtl_ops.init(tp);
5265 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5266 set_ethernet_addr(tp);
5267
5268 usb_set_intfdata(intf, tp);
5269 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5270
5271 ret = register_netdev(netdev);
5272 if (ret != 0) {
5273 netif_err(tp, probe, netdev, "couldn't register the device\n");
5274 goto out1;
5275 }
5276
5277 if (!rtl_can_wakeup(tp))
5278 __rtl_set_wol(tp, 0);
5279
5280 tp->saved_wolopts = __rtl_get_wol(tp);
5281 if (tp->saved_wolopts)
5282 device_set_wakeup_enable(&udev->dev, true);
5283 else
5284 device_set_wakeup_enable(&udev->dev, false);
5285
5286 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5287
5288 return 0;
5289
5290 out1:
5291 netif_napi_del(&tp->napi);
5292 usb_set_intfdata(intf, NULL);
5293 out:
5294 free_netdev(netdev);
5295 return ret;
5296 }
5297
5298 static void rtl8152_disconnect(struct usb_interface *intf)
5299 {
5300 struct r8152 *tp = usb_get_intfdata(intf);
5301
5302 usb_set_intfdata(intf, NULL);
5303 if (tp) {
5304 struct usb_device *udev = tp->udev;
5305
5306 if (udev->state == USB_STATE_NOTATTACHED)
5307 set_bit(RTL8152_UNPLUG, &tp->flags);
5308
5309 netif_napi_del(&tp->napi);
5310 unregister_netdev(tp->netdev);
5311 cancel_delayed_work_sync(&tp->hw_phy_work);
5312 tp->rtl_ops.unload(tp);
5313 free_netdev(tp->netdev);
5314 }
5315 }
5316
5317 #define REALTEK_USB_DEVICE(vend, prod) \
5318 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5319 USB_DEVICE_ID_MATCH_INT_CLASS, \
5320 .idVendor = (vend), \
5321 .idProduct = (prod), \
5322 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5323 }, \
5324 { \
5325 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5326 USB_DEVICE_ID_MATCH_DEVICE, \
5327 .idVendor = (vend), \
5328 .idProduct = (prod), \
5329 .bInterfaceClass = USB_CLASS_COMM, \
5330 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5331 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5332
5333 /* table of devices that work with this driver */
5334 static const struct usb_device_id rtl8152_table[] = {
5335 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5336 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5337 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5338 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5339 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5340 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5341 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5342 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5343 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5344 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5345 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5346 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5347 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5348 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5349 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
5350 {}
5351 };
5352
5353 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5354
5355 static struct usb_driver rtl8152_driver = {
5356 .name = MODULENAME,
5357 .id_table = rtl8152_table,
5358 .probe = rtl8152_probe,
5359 .disconnect = rtl8152_disconnect,
5360 .suspend = rtl8152_suspend,
5361 .resume = rtl8152_resume,
5362 .reset_resume = rtl8152_reset_resume,
5363 .pre_reset = rtl8152_pre_reset,
5364 .post_reset = rtl8152_post_reset,
5365 .supports_autosuspend = 1,
5366 .disable_hub_initiated_lpm = 1,
5367 };
5368
5369 module_usb_driver(rtl8152_driver);
5370
5371 MODULE_AUTHOR(DRIVER_AUTHOR);
5372 MODULE_DESCRIPTION(DRIVER_DESC);
5373 MODULE_LICENSE("GPL");
5374 MODULE_VERSION(DRIVER_VERSION);