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r8152: don't execute runtime suspend if the tx is not empty
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1 /*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION "08"
33
34 /* Information for net */
35 #define NET_VERSION "2"
36
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID 32
43
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_MAR 0xcd00
55 #define PLA_BACKUP 0xd000
56 #define PAL_BDC_CR 0xd1a0
57 #define PLA_TEREDO_TIMER 0xd2cc
58 #define PLA_REALWOW_TIMER 0xd2e8
59 #define PLA_LEDSEL 0xdd90
60 #define PLA_LED_FEATURE 0xdd92
61 #define PLA_PHYAR 0xde00
62 #define PLA_BOOT_CTRL 0xe004
63 #define PLA_GPHY_INTR_IMR 0xe022
64 #define PLA_EEE_CR 0xe040
65 #define PLA_EEEP_CR 0xe080
66 #define PLA_MAC_PWR_CTRL 0xe0c0
67 #define PLA_MAC_PWR_CTRL2 0xe0ca
68 #define PLA_MAC_PWR_CTRL3 0xe0cc
69 #define PLA_MAC_PWR_CTRL4 0xe0ce
70 #define PLA_WDT6_CTRL 0xe428
71 #define PLA_TCR0 0xe610
72 #define PLA_TCR1 0xe612
73 #define PLA_MTPS 0xe615
74 #define PLA_TXFIFO_CTRL 0xe618
75 #define PLA_RSTTALLY 0xe800
76 #define PLA_CR 0xe813
77 #define PLA_CRWECR 0xe81c
78 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
79 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
80 #define PLA_CONFIG5 0xe822
81 #define PLA_PHY_PWR 0xe84c
82 #define PLA_OOB_CTRL 0xe84f
83 #define PLA_CPCR 0xe854
84 #define PLA_MISC_0 0xe858
85 #define PLA_MISC_1 0xe85a
86 #define PLA_OCP_GPHY_BASE 0xe86c
87 #define PLA_TALLYCNT 0xe890
88 #define PLA_SFF_STS_7 0xe8de
89 #define PLA_PHYSTATUS 0xe908
90 #define PLA_BP_BA 0xfc26
91 #define PLA_BP_0 0xfc28
92 #define PLA_BP_1 0xfc2a
93 #define PLA_BP_2 0xfc2c
94 #define PLA_BP_3 0xfc2e
95 #define PLA_BP_4 0xfc30
96 #define PLA_BP_5 0xfc32
97 #define PLA_BP_6 0xfc34
98 #define PLA_BP_7 0xfc36
99 #define PLA_BP_EN 0xfc38
100
101 #define USB_USB2PHY 0xb41e
102 #define USB_SSPHYLINK2 0xb428
103 #define USB_U2P3_CTRL 0xb460
104 #define USB_CSR_DUMMY1 0xb464
105 #define USB_CSR_DUMMY2 0xb466
106 #define USB_DEV_STAT 0xb808
107 #define USB_CONNECT_TIMER 0xcbf8
108 #define USB_BURST_SIZE 0xcfc0
109 #define USB_USB_CTRL 0xd406
110 #define USB_PHY_CTRL 0xd408
111 #define USB_TX_AGG 0xd40a
112 #define USB_RX_BUF_TH 0xd40c
113 #define USB_USB_TIMER 0xd428
114 #define USB_RX_EARLY_TIMEOUT 0xd42c
115 #define USB_RX_EARLY_SIZE 0xd42e
116 #define USB_PM_CTRL_STATUS 0xd432
117 #define USB_TX_DMA 0xd434
118 #define USB_TOLERANCE 0xd490
119 #define USB_LPM_CTRL 0xd41a
120 #define USB_UPS_CTRL 0xd800
121 #define USB_MISC_0 0xd81a
122 #define USB_POWER_CUT 0xd80a
123 #define USB_AFE_CTRL2 0xd824
124 #define USB_WDT11_CTRL 0xe43c
125 #define USB_BP_BA 0xfc26
126 #define USB_BP_0 0xfc28
127 #define USB_BP_1 0xfc2a
128 #define USB_BP_2 0xfc2c
129 #define USB_BP_3 0xfc2e
130 #define USB_BP_4 0xfc30
131 #define USB_BP_5 0xfc32
132 #define USB_BP_6 0xfc34
133 #define USB_BP_7 0xfc36
134 #define USB_BP_EN 0xfc38
135
136 /* OCP Registers */
137 #define OCP_ALDPS_CONFIG 0x2010
138 #define OCP_EEE_CONFIG1 0x2080
139 #define OCP_EEE_CONFIG2 0x2092
140 #define OCP_EEE_CONFIG3 0x2094
141 #define OCP_BASE_MII 0xa400
142 #define OCP_EEE_AR 0xa41a
143 #define OCP_EEE_DATA 0xa41c
144 #define OCP_PHY_STATUS 0xa420
145 #define OCP_POWER_CFG 0xa430
146 #define OCP_EEE_CFG 0xa432
147 #define OCP_SRAM_ADDR 0xa436
148 #define OCP_SRAM_DATA 0xa438
149 #define OCP_DOWN_SPEED 0xa442
150 #define OCP_EEE_ABLE 0xa5c4
151 #define OCP_EEE_ADV 0xa5d0
152 #define OCP_EEE_LPABLE 0xa5d2
153 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
154 #define OCP_ADC_CFG 0xbc06
155
156 /* SRAM Register */
157 #define SRAM_LPF_CFG 0x8012
158 #define SRAM_10M_AMP1 0x8080
159 #define SRAM_10M_AMP2 0x8082
160 #define SRAM_IMPEDANCE 0x8084
161
162 /* PLA_RCR */
163 #define RCR_AAP 0x00000001
164 #define RCR_APM 0x00000002
165 #define RCR_AM 0x00000004
166 #define RCR_AB 0x00000008
167 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
168
169 /* PLA_RXFIFO_CTRL0 */
170 #define RXFIFO_THR1_NORMAL 0x00080002
171 #define RXFIFO_THR1_OOB 0x01800003
172
173 /* PLA_RXFIFO_CTRL1 */
174 #define RXFIFO_THR2_FULL 0x00000060
175 #define RXFIFO_THR2_HIGH 0x00000038
176 #define RXFIFO_THR2_OOB 0x0000004a
177 #define RXFIFO_THR2_NORMAL 0x00a0
178
179 /* PLA_RXFIFO_CTRL2 */
180 #define RXFIFO_THR3_FULL 0x00000078
181 #define RXFIFO_THR3_HIGH 0x00000048
182 #define RXFIFO_THR3_OOB 0x0000005a
183 #define RXFIFO_THR3_NORMAL 0x0110
184
185 /* PLA_TXFIFO_CTRL */
186 #define TXFIFO_THR_NORMAL 0x00400008
187 #define TXFIFO_THR_NORMAL2 0x01000008
188
189 /* PLA_DMY_REG0 */
190 #define ECM_ALDPS 0x0002
191
192 /* PLA_FMC */
193 #define FMC_FCR_MCU_EN 0x0001
194
195 /* PLA_EEEP_CR */
196 #define EEEP_CR_EEEP_TX 0x0002
197
198 /* PLA_WDT6_CTRL */
199 #define WDT6_SET_MODE 0x0010
200
201 /* PLA_TCR0 */
202 #define TCR0_TX_EMPTY 0x0800
203 #define TCR0_AUTO_FIFO 0x0080
204
205 /* PLA_TCR1 */
206 #define VERSION_MASK 0x7cf0
207
208 /* PLA_MTPS */
209 #define MTPS_JUMBO (12 * 1024 / 64)
210 #define MTPS_DEFAULT (6 * 1024 / 64)
211
212 /* PLA_RSTTALLY */
213 #define TALLY_RESET 0x0001
214
215 /* PLA_CR */
216 #define CR_RST 0x10
217 #define CR_RE 0x08
218 #define CR_TE 0x04
219
220 /* PLA_CRWECR */
221 #define CRWECR_NORAML 0x00
222 #define CRWECR_CONFIG 0xc0
223
224 /* PLA_OOB_CTRL */
225 #define NOW_IS_OOB 0x80
226 #define TXFIFO_EMPTY 0x20
227 #define RXFIFO_EMPTY 0x10
228 #define LINK_LIST_READY 0x02
229 #define DIS_MCU_CLROOB 0x01
230 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
231
232 /* PLA_MISC_1 */
233 #define RXDY_GATED_EN 0x0008
234
235 /* PLA_SFF_STS_7 */
236 #define RE_INIT_LL 0x8000
237 #define MCU_BORW_EN 0x4000
238
239 /* PLA_CPCR */
240 #define CPCR_RX_VLAN 0x0040
241
242 /* PLA_CFG_WOL */
243 #define MAGIC_EN 0x0001
244
245 /* PLA_TEREDO_CFG */
246 #define TEREDO_SEL 0x8000
247 #define TEREDO_WAKE_MASK 0x7f00
248 #define TEREDO_RS_EVENT_MASK 0x00fe
249 #define OOB_TEREDO_EN 0x0001
250
251 /* PAL_BDC_CR */
252 #define ALDPS_PROXY_MODE 0x0001
253
254 /* PLA_CONFIG34 */
255 #define LINK_ON_WAKE_EN 0x0010
256 #define LINK_OFF_WAKE_EN 0x0008
257
258 /* PLA_CONFIG5 */
259 #define BWF_EN 0x0040
260 #define MWF_EN 0x0020
261 #define UWF_EN 0x0010
262 #define LAN_WAKE_EN 0x0002
263
264 /* PLA_LED_FEATURE */
265 #define LED_MODE_MASK 0x0700
266
267 /* PLA_PHY_PWR */
268 #define TX_10M_IDLE_EN 0x0080
269 #define PFM_PWM_SWITCH 0x0040
270
271 /* PLA_MAC_PWR_CTRL */
272 #define D3_CLK_GATED_EN 0x00004000
273 #define MCU_CLK_RATIO 0x07010f07
274 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
275 #define ALDPS_SPDWN_RATIO 0x0f87
276
277 /* PLA_MAC_PWR_CTRL2 */
278 #define EEE_SPDWN_RATIO 0x8007
279
280 /* PLA_MAC_PWR_CTRL3 */
281 #define PKT_AVAIL_SPDWN_EN 0x0100
282 #define SUSPEND_SPDWN_EN 0x0004
283 #define U1U2_SPDWN_EN 0x0002
284 #define L1_SPDWN_EN 0x0001
285
286 /* PLA_MAC_PWR_CTRL4 */
287 #define PWRSAVE_SPDWN_EN 0x1000
288 #define RXDV_SPDWN_EN 0x0800
289 #define TX10MIDLE_EN 0x0100
290 #define TP100_SPDWN_EN 0x0020
291 #define TP500_SPDWN_EN 0x0010
292 #define TP1000_SPDWN_EN 0x0008
293 #define EEE_SPDWN_EN 0x0001
294
295 /* PLA_GPHY_INTR_IMR */
296 #define GPHY_STS_MSK 0x0001
297 #define SPEED_DOWN_MSK 0x0002
298 #define SPDWN_RXDV_MSK 0x0004
299 #define SPDWN_LINKCHG_MSK 0x0008
300
301 /* PLA_PHYAR */
302 #define PHYAR_FLAG 0x80000000
303
304 /* PLA_EEE_CR */
305 #define EEE_RX_EN 0x0001
306 #define EEE_TX_EN 0x0002
307
308 /* PLA_BOOT_CTRL */
309 #define AUTOLOAD_DONE 0x0002
310
311 /* USB_USB2PHY */
312 #define USB2PHY_SUSPEND 0x0001
313 #define USB2PHY_L1 0x0002
314
315 /* USB_SSPHYLINK2 */
316 #define pwd_dn_scale_mask 0x3ffe
317 #define pwd_dn_scale(x) ((x) << 1)
318
319 /* USB_CSR_DUMMY1 */
320 #define DYNAMIC_BURST 0x0001
321
322 /* USB_CSR_DUMMY2 */
323 #define EP4_FULL_FC 0x0001
324
325 /* USB_DEV_STAT */
326 #define STAT_SPEED_MASK 0x0006
327 #define STAT_SPEED_HIGH 0x0000
328 #define STAT_SPEED_FULL 0x0002
329
330 /* USB_TX_AGG */
331 #define TX_AGG_MAX_THRESHOLD 0x03
332
333 /* USB_RX_BUF_TH */
334 #define RX_THR_SUPPER 0x0c350180
335 #define RX_THR_HIGH 0x7a120180
336 #define RX_THR_SLOW 0xffff0180
337
338 /* USB_TX_DMA */
339 #define TEST_MODE_DISABLE 0x00000001
340 #define TX_SIZE_ADJUST1 0x00000100
341
342 /* USB_UPS_CTRL */
343 #define POWER_CUT 0x0100
344
345 /* USB_PM_CTRL_STATUS */
346 #define RESUME_INDICATE 0x0001
347
348 /* USB_USB_CTRL */
349 #define RX_AGG_DISABLE 0x0010
350 #define RX_ZERO_EN 0x0080
351
352 /* USB_U2P3_CTRL */
353 #define U2P3_ENABLE 0x0001
354
355 /* USB_POWER_CUT */
356 #define PWR_EN 0x0001
357 #define PHASE2_EN 0x0008
358
359 /* USB_MISC_0 */
360 #define PCUT_STATUS 0x0001
361
362 /* USB_RX_EARLY_TIMEOUT */
363 #define COALESCE_SUPER 85000U
364 #define COALESCE_HIGH 250000U
365 #define COALESCE_SLOW 524280U
366
367 /* USB_WDT11_CTRL */
368 #define TIMER11_EN 0x0001
369
370 /* USB_LPM_CTRL */
371 /* bit 4 ~ 5: fifo empty boundary */
372 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
373 /* bit 2 ~ 3: LMP timer */
374 #define LPM_TIMER_MASK 0x0c
375 #define LPM_TIMER_500MS 0x04 /* 500 ms */
376 #define LPM_TIMER_500US 0x0c /* 500 us */
377 #define ROK_EXIT_LPM 0x02
378
379 /* USB_AFE_CTRL2 */
380 #define SEN_VAL_MASK 0xf800
381 #define SEN_VAL_NORMAL 0xa000
382 #define SEL_RXIDLE 0x0100
383
384 /* OCP_ALDPS_CONFIG */
385 #define ENPWRSAVE 0x8000
386 #define ENPDNPS 0x0200
387 #define LINKENA 0x0100
388 #define DIS_SDSAVE 0x0010
389
390 /* OCP_PHY_STATUS */
391 #define PHY_STAT_MASK 0x0007
392 #define PHY_STAT_LAN_ON 3
393 #define PHY_STAT_PWRDN 5
394
395 /* OCP_POWER_CFG */
396 #define EEE_CLKDIV_EN 0x8000
397 #define EN_ALDPS 0x0004
398 #define EN_10M_PLLOFF 0x0001
399
400 /* OCP_EEE_CONFIG1 */
401 #define RG_TXLPI_MSK_HFDUP 0x8000
402 #define RG_MATCLR_EN 0x4000
403 #define EEE_10_CAP 0x2000
404 #define EEE_NWAY_EN 0x1000
405 #define TX_QUIET_EN 0x0200
406 #define RX_QUIET_EN 0x0100
407 #define sd_rise_time_mask 0x0070
408 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
409 #define RG_RXLPI_MSK_HFDUP 0x0008
410 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
411
412 /* OCP_EEE_CONFIG2 */
413 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
414 #define RG_DACQUIET_EN 0x0400
415 #define RG_LDVQUIET_EN 0x0200
416 #define RG_CKRSEL 0x0020
417 #define RG_EEEPRG_EN 0x0010
418
419 /* OCP_EEE_CONFIG3 */
420 #define fast_snr_mask 0xff80
421 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
422 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
423 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
424
425 /* OCP_EEE_AR */
426 /* bit[15:14] function */
427 #define FUN_ADDR 0x0000
428 #define FUN_DATA 0x4000
429 /* bit[4:0] device addr */
430
431 /* OCP_EEE_CFG */
432 #define CTAP_SHORT_EN 0x0040
433 #define EEE10_EN 0x0010
434
435 /* OCP_DOWN_SPEED */
436 #define EN_10M_BGOFF 0x0080
437
438 /* OCP_PHY_STATE */
439 #define TXDIS_STATE 0x01
440 #define ABD_STATE 0x02
441
442 /* OCP_ADC_CFG */
443 #define CKADSEL_L 0x0100
444 #define ADC_EN 0x0080
445 #define EN_EMI_L 0x0040
446
447 /* SRAM_LPF_CFG */
448 #define LPF_AUTO_TUNE 0x8000
449
450 /* SRAM_10M_AMP1 */
451 #define GDAC_IB_UPALL 0x0008
452
453 /* SRAM_10M_AMP2 */
454 #define AMP_DN 0x0200
455
456 /* SRAM_IMPEDANCE */
457 #define RX_DRIVING_MASK 0x6000
458
459 /* MAC PASSTHRU */
460 #define AD_MASK 0xfee0
461 #define EFUSE 0xcfdb
462 #define PASS_THRU_MASK 0x1
463
464 enum rtl_register_content {
465 _1000bps = 0x10,
466 _100bps = 0x08,
467 _10bps = 0x04,
468 LINK_STATUS = 0x02,
469 FULL_DUP = 0x01,
470 };
471
472 #define RTL8152_MAX_TX 4
473 #define RTL8152_MAX_RX 10
474 #define INTBUFSIZE 2
475 #define CRC_SIZE 4
476 #define TX_ALIGN 4
477 #define RX_ALIGN 8
478
479 #define INTR_LINK 0x0004
480
481 #define RTL8152_REQT_READ 0xc0
482 #define RTL8152_REQT_WRITE 0x40
483 #define RTL8152_REQ_GET_REGS 0x05
484 #define RTL8152_REQ_SET_REGS 0x05
485
486 #define BYTE_EN_DWORD 0xff
487 #define BYTE_EN_WORD 0x33
488 #define BYTE_EN_BYTE 0x11
489 #define BYTE_EN_SIX_BYTES 0x3f
490 #define BYTE_EN_START_MASK 0x0f
491 #define BYTE_EN_END_MASK 0xf0
492
493 #define RTL8153_MAX_PACKET 9216 /* 9K */
494 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
495 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
496 #define RTL8153_RMS RTL8153_MAX_PACKET
497 #define RTL8152_TX_TIMEOUT (5 * HZ)
498 #define RTL8152_NAPI_WEIGHT 64
499
500 /* rtl8152 flags */
501 enum rtl8152_flags {
502 RTL8152_UNPLUG = 0,
503 RTL8152_SET_RX_MODE,
504 WORK_ENABLE,
505 RTL8152_LINK_CHG,
506 SELECTIVE_SUSPEND,
507 PHY_RESET,
508 SCHEDULE_NAPI,
509 };
510
511 /* Define these values to match your device */
512 #define VENDOR_ID_REALTEK 0x0bda
513 #define VENDOR_ID_SAMSUNG 0x04e8
514 #define VENDOR_ID_LENOVO 0x17ef
515 #define VENDOR_ID_NVIDIA 0x0955
516
517 #define MCU_TYPE_PLA 0x0100
518 #define MCU_TYPE_USB 0x0000
519
520 struct tally_counter {
521 __le64 tx_packets;
522 __le64 rx_packets;
523 __le64 tx_errors;
524 __le32 rx_errors;
525 __le16 rx_missed;
526 __le16 align_errors;
527 __le32 tx_one_collision;
528 __le32 tx_multi_collision;
529 __le64 rx_unicast;
530 __le64 rx_broadcast;
531 __le32 rx_multicast;
532 __le16 tx_aborted;
533 __le16 tx_underrun;
534 };
535
536 struct rx_desc {
537 __le32 opts1;
538 #define RX_LEN_MASK 0x7fff
539
540 __le32 opts2;
541 #define RD_UDP_CS BIT(23)
542 #define RD_TCP_CS BIT(22)
543 #define RD_IPV6_CS BIT(20)
544 #define RD_IPV4_CS BIT(19)
545
546 __le32 opts3;
547 #define IPF BIT(23) /* IP checksum fail */
548 #define UDPF BIT(22) /* UDP checksum fail */
549 #define TCPF BIT(21) /* TCP checksum fail */
550 #define RX_VLAN_TAG BIT(16)
551
552 __le32 opts4;
553 __le32 opts5;
554 __le32 opts6;
555 };
556
557 struct tx_desc {
558 __le32 opts1;
559 #define TX_FS BIT(31) /* First segment of a packet */
560 #define TX_LS BIT(30) /* Final segment of a packet */
561 #define GTSENDV4 BIT(28)
562 #define GTSENDV6 BIT(27)
563 #define GTTCPHO_SHIFT 18
564 #define GTTCPHO_MAX 0x7fU
565 #define TX_LEN_MAX 0x3ffffU
566
567 __le32 opts2;
568 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
569 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
570 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
571 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
572 #define MSS_SHIFT 17
573 #define MSS_MAX 0x7ffU
574 #define TCPHO_SHIFT 17
575 #define TCPHO_MAX 0x7ffU
576 #define TX_VLAN_TAG BIT(16)
577 };
578
579 struct r8152;
580
581 struct rx_agg {
582 struct list_head list;
583 struct urb *urb;
584 struct r8152 *context;
585 void *buffer;
586 void *head;
587 };
588
589 struct tx_agg {
590 struct list_head list;
591 struct urb *urb;
592 struct r8152 *context;
593 void *buffer;
594 void *head;
595 u32 skb_num;
596 u32 skb_len;
597 };
598
599 struct r8152 {
600 unsigned long flags;
601 struct usb_device *udev;
602 struct napi_struct napi;
603 struct usb_interface *intf;
604 struct net_device *netdev;
605 struct urb *intr_urb;
606 struct tx_agg tx_info[RTL8152_MAX_TX];
607 struct rx_agg rx_info[RTL8152_MAX_RX];
608 struct list_head rx_done, tx_free;
609 struct sk_buff_head tx_queue, rx_queue;
610 spinlock_t rx_lock, tx_lock;
611 struct delayed_work schedule;
612 struct mii_if_info mii;
613 struct mutex control; /* use for hw setting */
614
615 struct rtl_ops {
616 void (*init)(struct r8152 *);
617 int (*enable)(struct r8152 *);
618 void (*disable)(struct r8152 *);
619 void (*up)(struct r8152 *);
620 void (*down)(struct r8152 *);
621 void (*unload)(struct r8152 *);
622 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
623 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
624 bool (*in_nway)(struct r8152 *);
625 } rtl_ops;
626
627 int intr_interval;
628 u32 saved_wolopts;
629 u32 msg_enable;
630 u32 tx_qlen;
631 u32 coalesce;
632 u16 ocp_base;
633 u8 *intr_buff;
634 u8 version;
635 };
636
637 enum rtl_version {
638 RTL_VER_UNKNOWN = 0,
639 RTL_VER_01,
640 RTL_VER_02,
641 RTL_VER_03,
642 RTL_VER_04,
643 RTL_VER_05,
644 RTL_VER_06,
645 RTL_VER_MAX
646 };
647
648 enum tx_csum_stat {
649 TX_CSUM_SUCCESS = 0,
650 TX_CSUM_TSO,
651 TX_CSUM_NONE
652 };
653
654 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
655 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
656 */
657 static const int multicast_filter_limit = 32;
658 static unsigned int agg_buf_sz = 16384;
659
660 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
661 VLAN_ETH_HLEN - VLAN_HLEN)
662
663 static
664 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
665 {
666 int ret;
667 void *tmp;
668
669 tmp = kmalloc(size, GFP_KERNEL);
670 if (!tmp)
671 return -ENOMEM;
672
673 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
674 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
675 value, index, tmp, size, 500);
676
677 memcpy(data, tmp, size);
678 kfree(tmp);
679
680 return ret;
681 }
682
683 static
684 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
685 {
686 int ret;
687 void *tmp;
688
689 tmp = kmemdup(data, size, GFP_KERNEL);
690 if (!tmp)
691 return -ENOMEM;
692
693 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
694 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
695 value, index, tmp, size, 500);
696
697 kfree(tmp);
698
699 return ret;
700 }
701
702 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
703 void *data, u16 type)
704 {
705 u16 limit = 64;
706 int ret = 0;
707
708 if (test_bit(RTL8152_UNPLUG, &tp->flags))
709 return -ENODEV;
710
711 /* both size and indix must be 4 bytes align */
712 if ((size & 3) || !size || (index & 3) || !data)
713 return -EPERM;
714
715 if ((u32)index + (u32)size > 0xffff)
716 return -EPERM;
717
718 while (size) {
719 if (size > limit) {
720 ret = get_registers(tp, index, type, limit, data);
721 if (ret < 0)
722 break;
723
724 index += limit;
725 data += limit;
726 size -= limit;
727 } else {
728 ret = get_registers(tp, index, type, size, data);
729 if (ret < 0)
730 break;
731
732 index += size;
733 data += size;
734 size = 0;
735 break;
736 }
737 }
738
739 if (ret == -ENODEV)
740 set_bit(RTL8152_UNPLUG, &tp->flags);
741
742 return ret;
743 }
744
745 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
746 u16 size, void *data, u16 type)
747 {
748 int ret;
749 u16 byteen_start, byteen_end, byen;
750 u16 limit = 512;
751
752 if (test_bit(RTL8152_UNPLUG, &tp->flags))
753 return -ENODEV;
754
755 /* both size and indix must be 4 bytes align */
756 if ((size & 3) || !size || (index & 3) || !data)
757 return -EPERM;
758
759 if ((u32)index + (u32)size > 0xffff)
760 return -EPERM;
761
762 byteen_start = byteen & BYTE_EN_START_MASK;
763 byteen_end = byteen & BYTE_EN_END_MASK;
764
765 byen = byteen_start | (byteen_start << 4);
766 ret = set_registers(tp, index, type | byen, 4, data);
767 if (ret < 0)
768 goto error1;
769
770 index += 4;
771 data += 4;
772 size -= 4;
773
774 if (size) {
775 size -= 4;
776
777 while (size) {
778 if (size > limit) {
779 ret = set_registers(tp, index,
780 type | BYTE_EN_DWORD,
781 limit, data);
782 if (ret < 0)
783 goto error1;
784
785 index += limit;
786 data += limit;
787 size -= limit;
788 } else {
789 ret = set_registers(tp, index,
790 type | BYTE_EN_DWORD,
791 size, data);
792 if (ret < 0)
793 goto error1;
794
795 index += size;
796 data += size;
797 size = 0;
798 break;
799 }
800 }
801
802 byen = byteen_end | (byteen_end >> 4);
803 ret = set_registers(tp, index, type | byen, 4, data);
804 if (ret < 0)
805 goto error1;
806 }
807
808 error1:
809 if (ret == -ENODEV)
810 set_bit(RTL8152_UNPLUG, &tp->flags);
811
812 return ret;
813 }
814
815 static inline
816 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
817 {
818 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
819 }
820
821 static inline
822 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
823 {
824 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
825 }
826
827 static inline
828 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
829 {
830 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
831 }
832
833 static inline
834 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
835 {
836 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
837 }
838
839 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
840 {
841 __le32 data;
842
843 generic_ocp_read(tp, index, sizeof(data), &data, type);
844
845 return __le32_to_cpu(data);
846 }
847
848 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
849 {
850 __le32 tmp = __cpu_to_le32(data);
851
852 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
853 }
854
855 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
856 {
857 u32 data;
858 __le32 tmp;
859 u8 shift = index & 2;
860
861 index &= ~3;
862
863 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
864
865 data = __le32_to_cpu(tmp);
866 data >>= (shift * 8);
867 data &= 0xffff;
868
869 return (u16)data;
870 }
871
872 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
873 {
874 u32 mask = 0xffff;
875 __le32 tmp;
876 u16 byen = BYTE_EN_WORD;
877 u8 shift = index & 2;
878
879 data &= mask;
880
881 if (index & 2) {
882 byen <<= shift;
883 mask <<= (shift * 8);
884 data <<= (shift * 8);
885 index &= ~3;
886 }
887
888 tmp = __cpu_to_le32(data);
889
890 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
891 }
892
893 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
894 {
895 u32 data;
896 __le32 tmp;
897 u8 shift = index & 3;
898
899 index &= ~3;
900
901 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
902
903 data = __le32_to_cpu(tmp);
904 data >>= (shift * 8);
905 data &= 0xff;
906
907 return (u8)data;
908 }
909
910 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
911 {
912 u32 mask = 0xff;
913 __le32 tmp;
914 u16 byen = BYTE_EN_BYTE;
915 u8 shift = index & 3;
916
917 data &= mask;
918
919 if (index & 3) {
920 byen <<= shift;
921 mask <<= (shift * 8);
922 data <<= (shift * 8);
923 index &= ~3;
924 }
925
926 tmp = __cpu_to_le32(data);
927
928 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
929 }
930
931 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
932 {
933 u16 ocp_base, ocp_index;
934
935 ocp_base = addr & 0xf000;
936 if (ocp_base != tp->ocp_base) {
937 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
938 tp->ocp_base = ocp_base;
939 }
940
941 ocp_index = (addr & 0x0fff) | 0xb000;
942 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
943 }
944
945 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
946 {
947 u16 ocp_base, ocp_index;
948
949 ocp_base = addr & 0xf000;
950 if (ocp_base != tp->ocp_base) {
951 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
952 tp->ocp_base = ocp_base;
953 }
954
955 ocp_index = (addr & 0x0fff) | 0xb000;
956 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
957 }
958
959 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
960 {
961 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
962 }
963
964 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
965 {
966 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
967 }
968
969 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
970 {
971 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
972 ocp_reg_write(tp, OCP_SRAM_DATA, data);
973 }
974
975 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
976 {
977 struct r8152 *tp = netdev_priv(netdev);
978 int ret;
979
980 if (test_bit(RTL8152_UNPLUG, &tp->flags))
981 return -ENODEV;
982
983 if (phy_id != R8152_PHY_ID)
984 return -EINVAL;
985
986 ret = r8152_mdio_read(tp, reg);
987
988 return ret;
989 }
990
991 static
992 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
993 {
994 struct r8152 *tp = netdev_priv(netdev);
995
996 if (test_bit(RTL8152_UNPLUG, &tp->flags))
997 return;
998
999 if (phy_id != R8152_PHY_ID)
1000 return;
1001
1002 r8152_mdio_write(tp, reg, val);
1003 }
1004
1005 static int
1006 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1007
1008 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1009 {
1010 struct r8152 *tp = netdev_priv(netdev);
1011 struct sockaddr *addr = p;
1012 int ret = -EADDRNOTAVAIL;
1013
1014 if (!is_valid_ether_addr(addr->sa_data))
1015 goto out1;
1016
1017 ret = usb_autopm_get_interface(tp->intf);
1018 if (ret < 0)
1019 goto out1;
1020
1021 mutex_lock(&tp->control);
1022
1023 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1024
1025 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1026 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1027 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1028
1029 mutex_unlock(&tp->control);
1030
1031 usb_autopm_put_interface(tp->intf);
1032 out1:
1033 return ret;
1034 }
1035
1036 /* Devices containing RTL8153-AD can support a persistent
1037 * host system provided MAC address.
1038 * Examples of this are Dell TB15 and Dell WD15 docks
1039 */
1040 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1041 {
1042 acpi_status status;
1043 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1044 union acpi_object *obj;
1045 int ret = -EINVAL;
1046 u32 ocp_data;
1047 unsigned char buf[6];
1048
1049 /* test for -AD variant of RTL8153 */
1050 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1051 if ((ocp_data & AD_MASK) != 0x1000)
1052 return -ENODEV;
1053
1054 /* test for MAC address pass-through bit */
1055 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1056 if ((ocp_data & PASS_THRU_MASK) != 1)
1057 return -ENODEV;
1058
1059 /* returns _AUXMAC_#AABBCCDDEEFF# */
1060 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1061 obj = (union acpi_object *)buffer.pointer;
1062 if (!ACPI_SUCCESS(status))
1063 return -ENODEV;
1064 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1065 netif_warn(tp, probe, tp->netdev,
1066 "Invalid buffer when reading pass-thru MAC addr: "
1067 "(%d, %d)\n",
1068 obj->type, obj->string.length);
1069 goto amacout;
1070 }
1071 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1072 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1073 netif_warn(tp, probe, tp->netdev,
1074 "Invalid header when reading pass-thru MAC addr\n");
1075 goto amacout;
1076 }
1077 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1078 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1079 netif_warn(tp, probe, tp->netdev,
1080 "Invalid MAC when reading pass-thru MAC addr: "
1081 "%d, %pM\n", ret, buf);
1082 ret = -EINVAL;
1083 goto amacout;
1084 }
1085 memcpy(sa->sa_data, buf, 6);
1086 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1087 netif_info(tp, probe, tp->netdev,
1088 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1089
1090 amacout:
1091 kfree(obj);
1092 return ret;
1093 }
1094
1095 static int set_ethernet_addr(struct r8152 *tp)
1096 {
1097 struct net_device *dev = tp->netdev;
1098 struct sockaddr sa;
1099 int ret;
1100
1101 if (tp->version == RTL_VER_01)
1102 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1103 else {
1104 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1105 * or system doesn't provide valid _SB.AMAC this will be
1106 * be expected to non-zero
1107 */
1108 ret = vendor_mac_passthru_addr_read(tp, &sa);
1109 if (ret < 0)
1110 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1111 }
1112
1113 if (ret < 0) {
1114 netif_err(tp, probe, dev, "Get ether addr fail\n");
1115 } else if (!is_valid_ether_addr(sa.sa_data)) {
1116 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1117 sa.sa_data);
1118 eth_hw_addr_random(dev);
1119 ether_addr_copy(sa.sa_data, dev->dev_addr);
1120 ret = rtl8152_set_mac_address(dev, &sa);
1121 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1122 sa.sa_data);
1123 } else {
1124 if (tp->version == RTL_VER_01)
1125 ether_addr_copy(dev->dev_addr, sa.sa_data);
1126 else
1127 ret = rtl8152_set_mac_address(dev, &sa);
1128 }
1129
1130 return ret;
1131 }
1132
1133 static void read_bulk_callback(struct urb *urb)
1134 {
1135 struct net_device *netdev;
1136 int status = urb->status;
1137 struct rx_agg *agg;
1138 struct r8152 *tp;
1139
1140 agg = urb->context;
1141 if (!agg)
1142 return;
1143
1144 tp = agg->context;
1145 if (!tp)
1146 return;
1147
1148 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1149 return;
1150
1151 if (!test_bit(WORK_ENABLE, &tp->flags))
1152 return;
1153
1154 netdev = tp->netdev;
1155
1156 /* When link down, the driver would cancel all bulks. */
1157 /* This avoid the re-submitting bulk */
1158 if (!netif_carrier_ok(netdev))
1159 return;
1160
1161 usb_mark_last_busy(tp->udev);
1162
1163 switch (status) {
1164 case 0:
1165 if (urb->actual_length < ETH_ZLEN)
1166 break;
1167
1168 spin_lock(&tp->rx_lock);
1169 list_add_tail(&agg->list, &tp->rx_done);
1170 spin_unlock(&tp->rx_lock);
1171 napi_schedule(&tp->napi);
1172 return;
1173 case -ESHUTDOWN:
1174 set_bit(RTL8152_UNPLUG, &tp->flags);
1175 netif_device_detach(tp->netdev);
1176 return;
1177 case -ENOENT:
1178 return; /* the urb is in unlink state */
1179 case -ETIME:
1180 if (net_ratelimit())
1181 netdev_warn(netdev, "maybe reset is needed?\n");
1182 break;
1183 default:
1184 if (net_ratelimit())
1185 netdev_warn(netdev, "Rx status %d\n", status);
1186 break;
1187 }
1188
1189 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1190 }
1191
1192 static void write_bulk_callback(struct urb *urb)
1193 {
1194 struct net_device_stats *stats;
1195 struct net_device *netdev;
1196 struct tx_agg *agg;
1197 struct r8152 *tp;
1198 int status = urb->status;
1199
1200 agg = urb->context;
1201 if (!agg)
1202 return;
1203
1204 tp = agg->context;
1205 if (!tp)
1206 return;
1207
1208 netdev = tp->netdev;
1209 stats = &netdev->stats;
1210 if (status) {
1211 if (net_ratelimit())
1212 netdev_warn(netdev, "Tx status %d\n", status);
1213 stats->tx_errors += agg->skb_num;
1214 } else {
1215 stats->tx_packets += agg->skb_num;
1216 stats->tx_bytes += agg->skb_len;
1217 }
1218
1219 spin_lock(&tp->tx_lock);
1220 list_add_tail(&agg->list, &tp->tx_free);
1221 spin_unlock(&tp->tx_lock);
1222
1223 usb_autopm_put_interface_async(tp->intf);
1224
1225 if (!netif_carrier_ok(netdev))
1226 return;
1227
1228 if (!test_bit(WORK_ENABLE, &tp->flags))
1229 return;
1230
1231 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1232 return;
1233
1234 if (!skb_queue_empty(&tp->tx_queue))
1235 napi_schedule(&tp->napi);
1236 }
1237
1238 static void intr_callback(struct urb *urb)
1239 {
1240 struct r8152 *tp;
1241 __le16 *d;
1242 int status = urb->status;
1243 int res;
1244
1245 tp = urb->context;
1246 if (!tp)
1247 return;
1248
1249 if (!test_bit(WORK_ENABLE, &tp->flags))
1250 return;
1251
1252 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1253 return;
1254
1255 switch (status) {
1256 case 0: /* success */
1257 break;
1258 case -ECONNRESET: /* unlink */
1259 case -ESHUTDOWN:
1260 netif_device_detach(tp->netdev);
1261 case -ENOENT:
1262 case -EPROTO:
1263 netif_info(tp, intr, tp->netdev,
1264 "Stop submitting intr, status %d\n", status);
1265 return;
1266 case -EOVERFLOW:
1267 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1268 goto resubmit;
1269 /* -EPIPE: should clear the halt */
1270 default:
1271 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1272 goto resubmit;
1273 }
1274
1275 d = urb->transfer_buffer;
1276 if (INTR_LINK & __le16_to_cpu(d[0])) {
1277 if (!netif_carrier_ok(tp->netdev)) {
1278 set_bit(RTL8152_LINK_CHG, &tp->flags);
1279 schedule_delayed_work(&tp->schedule, 0);
1280 }
1281 } else {
1282 if (netif_carrier_ok(tp->netdev)) {
1283 set_bit(RTL8152_LINK_CHG, &tp->flags);
1284 schedule_delayed_work(&tp->schedule, 0);
1285 }
1286 }
1287
1288 resubmit:
1289 res = usb_submit_urb(urb, GFP_ATOMIC);
1290 if (res == -ENODEV) {
1291 set_bit(RTL8152_UNPLUG, &tp->flags);
1292 netif_device_detach(tp->netdev);
1293 } else if (res) {
1294 netif_err(tp, intr, tp->netdev,
1295 "can't resubmit intr, status %d\n", res);
1296 }
1297 }
1298
1299 static inline void *rx_agg_align(void *data)
1300 {
1301 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1302 }
1303
1304 static inline void *tx_agg_align(void *data)
1305 {
1306 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1307 }
1308
1309 static void free_all_mem(struct r8152 *tp)
1310 {
1311 int i;
1312
1313 for (i = 0; i < RTL8152_MAX_RX; i++) {
1314 usb_free_urb(tp->rx_info[i].urb);
1315 tp->rx_info[i].urb = NULL;
1316
1317 kfree(tp->rx_info[i].buffer);
1318 tp->rx_info[i].buffer = NULL;
1319 tp->rx_info[i].head = NULL;
1320 }
1321
1322 for (i = 0; i < RTL8152_MAX_TX; i++) {
1323 usb_free_urb(tp->tx_info[i].urb);
1324 tp->tx_info[i].urb = NULL;
1325
1326 kfree(tp->tx_info[i].buffer);
1327 tp->tx_info[i].buffer = NULL;
1328 tp->tx_info[i].head = NULL;
1329 }
1330
1331 usb_free_urb(tp->intr_urb);
1332 tp->intr_urb = NULL;
1333
1334 kfree(tp->intr_buff);
1335 tp->intr_buff = NULL;
1336 }
1337
1338 static int alloc_all_mem(struct r8152 *tp)
1339 {
1340 struct net_device *netdev = tp->netdev;
1341 struct usb_interface *intf = tp->intf;
1342 struct usb_host_interface *alt = intf->cur_altsetting;
1343 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1344 struct urb *urb;
1345 int node, i;
1346 u8 *buf;
1347
1348 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1349
1350 spin_lock_init(&tp->rx_lock);
1351 spin_lock_init(&tp->tx_lock);
1352 INIT_LIST_HEAD(&tp->tx_free);
1353 skb_queue_head_init(&tp->tx_queue);
1354 skb_queue_head_init(&tp->rx_queue);
1355
1356 for (i = 0; i < RTL8152_MAX_RX; i++) {
1357 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1358 if (!buf)
1359 goto err1;
1360
1361 if (buf != rx_agg_align(buf)) {
1362 kfree(buf);
1363 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1364 node);
1365 if (!buf)
1366 goto err1;
1367 }
1368
1369 urb = usb_alloc_urb(0, GFP_KERNEL);
1370 if (!urb) {
1371 kfree(buf);
1372 goto err1;
1373 }
1374
1375 INIT_LIST_HEAD(&tp->rx_info[i].list);
1376 tp->rx_info[i].context = tp;
1377 tp->rx_info[i].urb = urb;
1378 tp->rx_info[i].buffer = buf;
1379 tp->rx_info[i].head = rx_agg_align(buf);
1380 }
1381
1382 for (i = 0; i < RTL8152_MAX_TX; i++) {
1383 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1384 if (!buf)
1385 goto err1;
1386
1387 if (buf != tx_agg_align(buf)) {
1388 kfree(buf);
1389 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1390 node);
1391 if (!buf)
1392 goto err1;
1393 }
1394
1395 urb = usb_alloc_urb(0, GFP_KERNEL);
1396 if (!urb) {
1397 kfree(buf);
1398 goto err1;
1399 }
1400
1401 INIT_LIST_HEAD(&tp->tx_info[i].list);
1402 tp->tx_info[i].context = tp;
1403 tp->tx_info[i].urb = urb;
1404 tp->tx_info[i].buffer = buf;
1405 tp->tx_info[i].head = tx_agg_align(buf);
1406
1407 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1408 }
1409
1410 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1411 if (!tp->intr_urb)
1412 goto err1;
1413
1414 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1415 if (!tp->intr_buff)
1416 goto err1;
1417
1418 tp->intr_interval = (int)ep_intr->desc.bInterval;
1419 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1420 tp->intr_buff, INTBUFSIZE, intr_callback,
1421 tp, tp->intr_interval);
1422
1423 return 0;
1424
1425 err1:
1426 free_all_mem(tp);
1427 return -ENOMEM;
1428 }
1429
1430 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1431 {
1432 struct tx_agg *agg = NULL;
1433 unsigned long flags;
1434
1435 if (list_empty(&tp->tx_free))
1436 return NULL;
1437
1438 spin_lock_irqsave(&tp->tx_lock, flags);
1439 if (!list_empty(&tp->tx_free)) {
1440 struct list_head *cursor;
1441
1442 cursor = tp->tx_free.next;
1443 list_del_init(cursor);
1444 agg = list_entry(cursor, struct tx_agg, list);
1445 }
1446 spin_unlock_irqrestore(&tp->tx_lock, flags);
1447
1448 return agg;
1449 }
1450
1451 /* r8152_csum_workaround()
1452 * The hw limites the value the transport offset. When the offset is out of the
1453 * range, calculate the checksum by sw.
1454 */
1455 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1456 struct sk_buff_head *list)
1457 {
1458 if (skb_shinfo(skb)->gso_size) {
1459 netdev_features_t features = tp->netdev->features;
1460 struct sk_buff_head seg_list;
1461 struct sk_buff *segs, *nskb;
1462
1463 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1464 segs = skb_gso_segment(skb, features);
1465 if (IS_ERR(segs) || !segs)
1466 goto drop;
1467
1468 __skb_queue_head_init(&seg_list);
1469
1470 do {
1471 nskb = segs;
1472 segs = segs->next;
1473 nskb->next = NULL;
1474 __skb_queue_tail(&seg_list, nskb);
1475 } while (segs);
1476
1477 skb_queue_splice(&seg_list, list);
1478 dev_kfree_skb(skb);
1479 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1480 if (skb_checksum_help(skb) < 0)
1481 goto drop;
1482
1483 __skb_queue_head(list, skb);
1484 } else {
1485 struct net_device_stats *stats;
1486
1487 drop:
1488 stats = &tp->netdev->stats;
1489 stats->tx_dropped++;
1490 dev_kfree_skb(skb);
1491 }
1492 }
1493
1494 /* msdn_giant_send_check()
1495 * According to the document of microsoft, the TCP Pseudo Header excludes the
1496 * packet length for IPv6 TCP large packets.
1497 */
1498 static int msdn_giant_send_check(struct sk_buff *skb)
1499 {
1500 const struct ipv6hdr *ipv6h;
1501 struct tcphdr *th;
1502 int ret;
1503
1504 ret = skb_cow_head(skb, 0);
1505 if (ret)
1506 return ret;
1507
1508 ipv6h = ipv6_hdr(skb);
1509 th = tcp_hdr(skb);
1510
1511 th->check = 0;
1512 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1513
1514 return ret;
1515 }
1516
1517 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1518 {
1519 if (skb_vlan_tag_present(skb)) {
1520 u32 opts2;
1521
1522 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1523 desc->opts2 |= cpu_to_le32(opts2);
1524 }
1525 }
1526
1527 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1528 {
1529 u32 opts2 = le32_to_cpu(desc->opts2);
1530
1531 if (opts2 & RX_VLAN_TAG)
1532 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1533 swab16(opts2 & 0xffff));
1534 }
1535
1536 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1537 struct sk_buff *skb, u32 len, u32 transport_offset)
1538 {
1539 u32 mss = skb_shinfo(skb)->gso_size;
1540 u32 opts1, opts2 = 0;
1541 int ret = TX_CSUM_SUCCESS;
1542
1543 WARN_ON_ONCE(len > TX_LEN_MAX);
1544
1545 opts1 = len | TX_FS | TX_LS;
1546
1547 if (mss) {
1548 if (transport_offset > GTTCPHO_MAX) {
1549 netif_warn(tp, tx_err, tp->netdev,
1550 "Invalid transport offset 0x%x for TSO\n",
1551 transport_offset);
1552 ret = TX_CSUM_TSO;
1553 goto unavailable;
1554 }
1555
1556 switch (vlan_get_protocol(skb)) {
1557 case htons(ETH_P_IP):
1558 opts1 |= GTSENDV4;
1559 break;
1560
1561 case htons(ETH_P_IPV6):
1562 if (msdn_giant_send_check(skb)) {
1563 ret = TX_CSUM_TSO;
1564 goto unavailable;
1565 }
1566 opts1 |= GTSENDV6;
1567 break;
1568
1569 default:
1570 WARN_ON_ONCE(1);
1571 break;
1572 }
1573
1574 opts1 |= transport_offset << GTTCPHO_SHIFT;
1575 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1576 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1577 u8 ip_protocol;
1578
1579 if (transport_offset > TCPHO_MAX) {
1580 netif_warn(tp, tx_err, tp->netdev,
1581 "Invalid transport offset 0x%x\n",
1582 transport_offset);
1583 ret = TX_CSUM_NONE;
1584 goto unavailable;
1585 }
1586
1587 switch (vlan_get_protocol(skb)) {
1588 case htons(ETH_P_IP):
1589 opts2 |= IPV4_CS;
1590 ip_protocol = ip_hdr(skb)->protocol;
1591 break;
1592
1593 case htons(ETH_P_IPV6):
1594 opts2 |= IPV6_CS;
1595 ip_protocol = ipv6_hdr(skb)->nexthdr;
1596 break;
1597
1598 default:
1599 ip_protocol = IPPROTO_RAW;
1600 break;
1601 }
1602
1603 if (ip_protocol == IPPROTO_TCP)
1604 opts2 |= TCP_CS;
1605 else if (ip_protocol == IPPROTO_UDP)
1606 opts2 |= UDP_CS;
1607 else
1608 WARN_ON_ONCE(1);
1609
1610 opts2 |= transport_offset << TCPHO_SHIFT;
1611 }
1612
1613 desc->opts2 = cpu_to_le32(opts2);
1614 desc->opts1 = cpu_to_le32(opts1);
1615
1616 unavailable:
1617 return ret;
1618 }
1619
1620 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1621 {
1622 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1623 int remain, ret;
1624 u8 *tx_data;
1625
1626 __skb_queue_head_init(&skb_head);
1627 spin_lock(&tx_queue->lock);
1628 skb_queue_splice_init(tx_queue, &skb_head);
1629 spin_unlock(&tx_queue->lock);
1630
1631 tx_data = agg->head;
1632 agg->skb_num = 0;
1633 agg->skb_len = 0;
1634 remain = agg_buf_sz;
1635
1636 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1637 struct tx_desc *tx_desc;
1638 struct sk_buff *skb;
1639 unsigned int len;
1640 u32 offset;
1641
1642 skb = __skb_dequeue(&skb_head);
1643 if (!skb)
1644 break;
1645
1646 len = skb->len + sizeof(*tx_desc);
1647
1648 if (len > remain) {
1649 __skb_queue_head(&skb_head, skb);
1650 break;
1651 }
1652
1653 tx_data = tx_agg_align(tx_data);
1654 tx_desc = (struct tx_desc *)tx_data;
1655
1656 offset = (u32)skb_transport_offset(skb);
1657
1658 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1659 r8152_csum_workaround(tp, skb, &skb_head);
1660 continue;
1661 }
1662
1663 rtl_tx_vlan_tag(tx_desc, skb);
1664
1665 tx_data += sizeof(*tx_desc);
1666
1667 len = skb->len;
1668 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1669 struct net_device_stats *stats = &tp->netdev->stats;
1670
1671 stats->tx_dropped++;
1672 dev_kfree_skb_any(skb);
1673 tx_data -= sizeof(*tx_desc);
1674 continue;
1675 }
1676
1677 tx_data += len;
1678 agg->skb_len += len;
1679 agg->skb_num++;
1680
1681 dev_kfree_skb_any(skb);
1682
1683 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1684 }
1685
1686 if (!skb_queue_empty(&skb_head)) {
1687 spin_lock(&tx_queue->lock);
1688 skb_queue_splice(&skb_head, tx_queue);
1689 spin_unlock(&tx_queue->lock);
1690 }
1691
1692 netif_tx_lock(tp->netdev);
1693
1694 if (netif_queue_stopped(tp->netdev) &&
1695 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1696 netif_wake_queue(tp->netdev);
1697
1698 netif_tx_unlock(tp->netdev);
1699
1700 ret = usb_autopm_get_interface_async(tp->intf);
1701 if (ret < 0)
1702 goto out_tx_fill;
1703
1704 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1705 agg->head, (int)(tx_data - (u8 *)agg->head),
1706 (usb_complete_t)write_bulk_callback, agg);
1707
1708 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1709 if (ret < 0)
1710 usb_autopm_put_interface_async(tp->intf);
1711
1712 out_tx_fill:
1713 return ret;
1714 }
1715
1716 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1717 {
1718 u8 checksum = CHECKSUM_NONE;
1719 u32 opts2, opts3;
1720
1721 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1722 goto return_result;
1723
1724 opts2 = le32_to_cpu(rx_desc->opts2);
1725 opts3 = le32_to_cpu(rx_desc->opts3);
1726
1727 if (opts2 & RD_IPV4_CS) {
1728 if (opts3 & IPF)
1729 checksum = CHECKSUM_NONE;
1730 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1731 checksum = CHECKSUM_NONE;
1732 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1733 checksum = CHECKSUM_NONE;
1734 else
1735 checksum = CHECKSUM_UNNECESSARY;
1736 } else if (RD_IPV6_CS) {
1737 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1738 checksum = CHECKSUM_UNNECESSARY;
1739 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1740 checksum = CHECKSUM_UNNECESSARY;
1741 }
1742
1743 return_result:
1744 return checksum;
1745 }
1746
1747 static int rx_bottom(struct r8152 *tp, int budget)
1748 {
1749 unsigned long flags;
1750 struct list_head *cursor, *next, rx_queue;
1751 int ret = 0, work_done = 0;
1752
1753 if (!skb_queue_empty(&tp->rx_queue)) {
1754 while (work_done < budget) {
1755 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1756 struct net_device *netdev = tp->netdev;
1757 struct net_device_stats *stats = &netdev->stats;
1758 unsigned int pkt_len;
1759
1760 if (!skb)
1761 break;
1762
1763 pkt_len = skb->len;
1764 napi_gro_receive(&tp->napi, skb);
1765 work_done++;
1766 stats->rx_packets++;
1767 stats->rx_bytes += pkt_len;
1768 }
1769 }
1770
1771 if (list_empty(&tp->rx_done))
1772 goto out1;
1773
1774 INIT_LIST_HEAD(&rx_queue);
1775 spin_lock_irqsave(&tp->rx_lock, flags);
1776 list_splice_init(&tp->rx_done, &rx_queue);
1777 spin_unlock_irqrestore(&tp->rx_lock, flags);
1778
1779 list_for_each_safe(cursor, next, &rx_queue) {
1780 struct rx_desc *rx_desc;
1781 struct rx_agg *agg;
1782 int len_used = 0;
1783 struct urb *urb;
1784 u8 *rx_data;
1785
1786 list_del_init(cursor);
1787
1788 agg = list_entry(cursor, struct rx_agg, list);
1789 urb = agg->urb;
1790 if (urb->actual_length < ETH_ZLEN)
1791 goto submit;
1792
1793 rx_desc = agg->head;
1794 rx_data = agg->head;
1795 len_used += sizeof(struct rx_desc);
1796
1797 while (urb->actual_length > len_used) {
1798 struct net_device *netdev = tp->netdev;
1799 struct net_device_stats *stats = &netdev->stats;
1800 unsigned int pkt_len;
1801 struct sk_buff *skb;
1802
1803 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1804 if (pkt_len < ETH_ZLEN)
1805 break;
1806
1807 len_used += pkt_len;
1808 if (urb->actual_length < len_used)
1809 break;
1810
1811 pkt_len -= CRC_SIZE;
1812 rx_data += sizeof(struct rx_desc);
1813
1814 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1815 if (!skb) {
1816 stats->rx_dropped++;
1817 goto find_next_rx;
1818 }
1819
1820 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1821 memcpy(skb->data, rx_data, pkt_len);
1822 skb_put(skb, pkt_len);
1823 skb->protocol = eth_type_trans(skb, netdev);
1824 rtl_rx_vlan_tag(rx_desc, skb);
1825 if (work_done < budget) {
1826 napi_gro_receive(&tp->napi, skb);
1827 work_done++;
1828 stats->rx_packets++;
1829 stats->rx_bytes += pkt_len;
1830 } else {
1831 __skb_queue_tail(&tp->rx_queue, skb);
1832 }
1833
1834 find_next_rx:
1835 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1836 rx_desc = (struct rx_desc *)rx_data;
1837 len_used = (int)(rx_data - (u8 *)agg->head);
1838 len_used += sizeof(struct rx_desc);
1839 }
1840
1841 submit:
1842 if (!ret) {
1843 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1844 } else {
1845 urb->actual_length = 0;
1846 list_add_tail(&agg->list, next);
1847 }
1848 }
1849
1850 if (!list_empty(&rx_queue)) {
1851 spin_lock_irqsave(&tp->rx_lock, flags);
1852 list_splice_tail(&rx_queue, &tp->rx_done);
1853 spin_unlock_irqrestore(&tp->rx_lock, flags);
1854 }
1855
1856 out1:
1857 return work_done;
1858 }
1859
1860 static void tx_bottom(struct r8152 *tp)
1861 {
1862 int res;
1863
1864 do {
1865 struct tx_agg *agg;
1866
1867 if (skb_queue_empty(&tp->tx_queue))
1868 break;
1869
1870 agg = r8152_get_tx_agg(tp);
1871 if (!agg)
1872 break;
1873
1874 res = r8152_tx_agg_fill(tp, agg);
1875 if (res) {
1876 struct net_device *netdev = tp->netdev;
1877
1878 if (res == -ENODEV) {
1879 set_bit(RTL8152_UNPLUG, &tp->flags);
1880 netif_device_detach(netdev);
1881 } else {
1882 struct net_device_stats *stats = &netdev->stats;
1883 unsigned long flags;
1884
1885 netif_warn(tp, tx_err, netdev,
1886 "failed tx_urb %d\n", res);
1887 stats->tx_dropped += agg->skb_num;
1888
1889 spin_lock_irqsave(&tp->tx_lock, flags);
1890 list_add_tail(&agg->list, &tp->tx_free);
1891 spin_unlock_irqrestore(&tp->tx_lock, flags);
1892 }
1893 }
1894 } while (res == 0);
1895 }
1896
1897 static void bottom_half(struct r8152 *tp)
1898 {
1899 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1900 return;
1901
1902 if (!test_bit(WORK_ENABLE, &tp->flags))
1903 return;
1904
1905 /* When link down, the driver would cancel all bulks. */
1906 /* This avoid the re-submitting bulk */
1907 if (!netif_carrier_ok(tp->netdev))
1908 return;
1909
1910 clear_bit(SCHEDULE_NAPI, &tp->flags);
1911
1912 tx_bottom(tp);
1913 }
1914
1915 static int r8152_poll(struct napi_struct *napi, int budget)
1916 {
1917 struct r8152 *tp = container_of(napi, struct r8152, napi);
1918 int work_done;
1919
1920 work_done = rx_bottom(tp, budget);
1921 bottom_half(tp);
1922
1923 if (work_done < budget) {
1924 napi_complete(napi);
1925 if (!list_empty(&tp->rx_done))
1926 napi_schedule(napi);
1927 }
1928
1929 return work_done;
1930 }
1931
1932 static
1933 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1934 {
1935 int ret;
1936
1937 /* The rx would be stopped, so skip submitting */
1938 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1939 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1940 return 0;
1941
1942 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1943 agg->head, agg_buf_sz,
1944 (usb_complete_t)read_bulk_callback, agg);
1945
1946 ret = usb_submit_urb(agg->urb, mem_flags);
1947 if (ret == -ENODEV) {
1948 set_bit(RTL8152_UNPLUG, &tp->flags);
1949 netif_device_detach(tp->netdev);
1950 } else if (ret) {
1951 struct urb *urb = agg->urb;
1952 unsigned long flags;
1953
1954 urb->actual_length = 0;
1955 spin_lock_irqsave(&tp->rx_lock, flags);
1956 list_add_tail(&agg->list, &tp->rx_done);
1957 spin_unlock_irqrestore(&tp->rx_lock, flags);
1958
1959 netif_err(tp, rx_err, tp->netdev,
1960 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1961
1962 napi_schedule(&tp->napi);
1963 }
1964
1965 return ret;
1966 }
1967
1968 static void rtl_drop_queued_tx(struct r8152 *tp)
1969 {
1970 struct net_device_stats *stats = &tp->netdev->stats;
1971 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1972 struct sk_buff *skb;
1973
1974 if (skb_queue_empty(tx_queue))
1975 return;
1976
1977 __skb_queue_head_init(&skb_head);
1978 spin_lock_bh(&tx_queue->lock);
1979 skb_queue_splice_init(tx_queue, &skb_head);
1980 spin_unlock_bh(&tx_queue->lock);
1981
1982 while ((skb = __skb_dequeue(&skb_head))) {
1983 dev_kfree_skb(skb);
1984 stats->tx_dropped++;
1985 }
1986 }
1987
1988 static void rtl8152_tx_timeout(struct net_device *netdev)
1989 {
1990 struct r8152 *tp = netdev_priv(netdev);
1991
1992 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1993
1994 usb_queue_reset_device(tp->intf);
1995 }
1996
1997 static void rtl8152_set_rx_mode(struct net_device *netdev)
1998 {
1999 struct r8152 *tp = netdev_priv(netdev);
2000
2001 if (netif_carrier_ok(netdev)) {
2002 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2003 schedule_delayed_work(&tp->schedule, 0);
2004 }
2005 }
2006
2007 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2008 {
2009 struct r8152 *tp = netdev_priv(netdev);
2010 u32 mc_filter[2]; /* Multicast hash filter */
2011 __le32 tmp[2];
2012 u32 ocp_data;
2013
2014 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
2015 netif_stop_queue(netdev);
2016 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2017 ocp_data &= ~RCR_ACPT_ALL;
2018 ocp_data |= RCR_AB | RCR_APM;
2019
2020 if (netdev->flags & IFF_PROMISC) {
2021 /* Unconditionally log net taps. */
2022 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2023 ocp_data |= RCR_AM | RCR_AAP;
2024 mc_filter[1] = 0xffffffff;
2025 mc_filter[0] = 0xffffffff;
2026 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2027 (netdev->flags & IFF_ALLMULTI)) {
2028 /* Too many to filter perfectly -- accept all multicasts. */
2029 ocp_data |= RCR_AM;
2030 mc_filter[1] = 0xffffffff;
2031 mc_filter[0] = 0xffffffff;
2032 } else {
2033 struct netdev_hw_addr *ha;
2034
2035 mc_filter[1] = 0;
2036 mc_filter[0] = 0;
2037 netdev_for_each_mc_addr(ha, netdev) {
2038 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2039
2040 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2041 ocp_data |= RCR_AM;
2042 }
2043 }
2044
2045 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2046 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2047
2048 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2049 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2050 netif_wake_queue(netdev);
2051 }
2052
2053 static netdev_features_t
2054 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2055 netdev_features_t features)
2056 {
2057 u32 mss = skb_shinfo(skb)->gso_size;
2058 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2059 int offset = skb_transport_offset(skb);
2060
2061 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2062 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
2063 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2064 features &= ~NETIF_F_GSO_MASK;
2065
2066 return features;
2067 }
2068
2069 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2070 struct net_device *netdev)
2071 {
2072 struct r8152 *tp = netdev_priv(netdev);
2073
2074 skb_tx_timestamp(skb);
2075
2076 skb_queue_tail(&tp->tx_queue, skb);
2077
2078 if (!list_empty(&tp->tx_free)) {
2079 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2080 set_bit(SCHEDULE_NAPI, &tp->flags);
2081 schedule_delayed_work(&tp->schedule, 0);
2082 } else {
2083 usb_mark_last_busy(tp->udev);
2084 napi_schedule(&tp->napi);
2085 }
2086 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2087 netif_stop_queue(netdev);
2088 }
2089
2090 return NETDEV_TX_OK;
2091 }
2092
2093 static void r8152b_reset_packet_filter(struct r8152 *tp)
2094 {
2095 u32 ocp_data;
2096
2097 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2098 ocp_data &= ~FMC_FCR_MCU_EN;
2099 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2100 ocp_data |= FMC_FCR_MCU_EN;
2101 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2102 }
2103
2104 static void rtl8152_nic_reset(struct r8152 *tp)
2105 {
2106 int i;
2107
2108 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2109
2110 for (i = 0; i < 1000; i++) {
2111 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2112 break;
2113 usleep_range(100, 400);
2114 }
2115 }
2116
2117 static void set_tx_qlen(struct r8152 *tp)
2118 {
2119 struct net_device *netdev = tp->netdev;
2120
2121 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2122 sizeof(struct tx_desc));
2123 }
2124
2125 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2126 {
2127 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2128 }
2129
2130 static void rtl_set_eee_plus(struct r8152 *tp)
2131 {
2132 u32 ocp_data;
2133 u8 speed;
2134
2135 speed = rtl8152_get_speed(tp);
2136 if (speed & _10bps) {
2137 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2138 ocp_data |= EEEP_CR_EEEP_TX;
2139 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2140 } else {
2141 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2142 ocp_data &= ~EEEP_CR_EEEP_TX;
2143 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2144 }
2145 }
2146
2147 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2148 {
2149 u32 ocp_data;
2150
2151 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2152 if (enable)
2153 ocp_data |= RXDY_GATED_EN;
2154 else
2155 ocp_data &= ~RXDY_GATED_EN;
2156 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2157 }
2158
2159 static int rtl_start_rx(struct r8152 *tp)
2160 {
2161 int i, ret = 0;
2162
2163 INIT_LIST_HEAD(&tp->rx_done);
2164 for (i = 0; i < RTL8152_MAX_RX; i++) {
2165 INIT_LIST_HEAD(&tp->rx_info[i].list);
2166 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2167 if (ret)
2168 break;
2169 }
2170
2171 if (ret && ++i < RTL8152_MAX_RX) {
2172 struct list_head rx_queue;
2173 unsigned long flags;
2174
2175 INIT_LIST_HEAD(&rx_queue);
2176
2177 do {
2178 struct rx_agg *agg = &tp->rx_info[i++];
2179 struct urb *urb = agg->urb;
2180
2181 urb->actual_length = 0;
2182 list_add_tail(&agg->list, &rx_queue);
2183 } while (i < RTL8152_MAX_RX);
2184
2185 spin_lock_irqsave(&tp->rx_lock, flags);
2186 list_splice_tail(&rx_queue, &tp->rx_done);
2187 spin_unlock_irqrestore(&tp->rx_lock, flags);
2188 }
2189
2190 return ret;
2191 }
2192
2193 static int rtl_stop_rx(struct r8152 *tp)
2194 {
2195 int i;
2196
2197 for (i = 0; i < RTL8152_MAX_RX; i++)
2198 usb_kill_urb(tp->rx_info[i].urb);
2199
2200 while (!skb_queue_empty(&tp->rx_queue))
2201 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2202
2203 return 0;
2204 }
2205
2206 static int rtl_enable(struct r8152 *tp)
2207 {
2208 u32 ocp_data;
2209
2210 r8152b_reset_packet_filter(tp);
2211
2212 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2213 ocp_data |= CR_RE | CR_TE;
2214 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2215
2216 rxdy_gated_en(tp, false);
2217
2218 return 0;
2219 }
2220
2221 static int rtl8152_enable(struct r8152 *tp)
2222 {
2223 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2224 return -ENODEV;
2225
2226 set_tx_qlen(tp);
2227 rtl_set_eee_plus(tp);
2228
2229 return rtl_enable(tp);
2230 }
2231
2232 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2233 {
2234 u32 ocp_data = tp->coalesce / 8;
2235
2236 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2237 }
2238
2239 static void r8153_set_rx_early_size(struct r8152 *tp)
2240 {
2241 u32 mtu = tp->netdev->mtu;
2242 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
2243
2244 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
2245 }
2246
2247 static int rtl8153_enable(struct r8152 *tp)
2248 {
2249 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2250 return -ENODEV;
2251
2252 usb_disable_lpm(tp->udev);
2253 set_tx_qlen(tp);
2254 rtl_set_eee_plus(tp);
2255 r8153_set_rx_early_timeout(tp);
2256 r8153_set_rx_early_size(tp);
2257
2258 return rtl_enable(tp);
2259 }
2260
2261 static void rtl_disable(struct r8152 *tp)
2262 {
2263 u32 ocp_data;
2264 int i;
2265
2266 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2267 rtl_drop_queued_tx(tp);
2268 return;
2269 }
2270
2271 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2272 ocp_data &= ~RCR_ACPT_ALL;
2273 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2274
2275 rtl_drop_queued_tx(tp);
2276
2277 for (i = 0; i < RTL8152_MAX_TX; i++)
2278 usb_kill_urb(tp->tx_info[i].urb);
2279
2280 rxdy_gated_en(tp, true);
2281
2282 for (i = 0; i < 1000; i++) {
2283 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2284 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2285 break;
2286 usleep_range(1000, 2000);
2287 }
2288
2289 for (i = 0; i < 1000; i++) {
2290 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2291 break;
2292 usleep_range(1000, 2000);
2293 }
2294
2295 rtl_stop_rx(tp);
2296
2297 rtl8152_nic_reset(tp);
2298 }
2299
2300 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2301 {
2302 u32 ocp_data;
2303
2304 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2305 if (enable)
2306 ocp_data |= POWER_CUT;
2307 else
2308 ocp_data &= ~POWER_CUT;
2309 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2310
2311 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2312 ocp_data &= ~RESUME_INDICATE;
2313 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2314 }
2315
2316 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2317 {
2318 u32 ocp_data;
2319
2320 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2321 if (enable)
2322 ocp_data |= CPCR_RX_VLAN;
2323 else
2324 ocp_data &= ~CPCR_RX_VLAN;
2325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2326 }
2327
2328 static int rtl8152_set_features(struct net_device *dev,
2329 netdev_features_t features)
2330 {
2331 netdev_features_t changed = features ^ dev->features;
2332 struct r8152 *tp = netdev_priv(dev);
2333 int ret;
2334
2335 ret = usb_autopm_get_interface(tp->intf);
2336 if (ret < 0)
2337 goto out;
2338
2339 mutex_lock(&tp->control);
2340
2341 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2342 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2343 rtl_rx_vlan_en(tp, true);
2344 else
2345 rtl_rx_vlan_en(tp, false);
2346 }
2347
2348 mutex_unlock(&tp->control);
2349
2350 usb_autopm_put_interface(tp->intf);
2351
2352 out:
2353 return ret;
2354 }
2355
2356 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2357
2358 static u32 __rtl_get_wol(struct r8152 *tp)
2359 {
2360 u32 ocp_data;
2361 u32 wolopts = 0;
2362
2363 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2364 if (!(ocp_data & LAN_WAKE_EN))
2365 return 0;
2366
2367 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2368 if (ocp_data & LINK_ON_WAKE_EN)
2369 wolopts |= WAKE_PHY;
2370
2371 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2372 if (ocp_data & UWF_EN)
2373 wolopts |= WAKE_UCAST;
2374 if (ocp_data & BWF_EN)
2375 wolopts |= WAKE_BCAST;
2376 if (ocp_data & MWF_EN)
2377 wolopts |= WAKE_MCAST;
2378
2379 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2380 if (ocp_data & MAGIC_EN)
2381 wolopts |= WAKE_MAGIC;
2382
2383 return wolopts;
2384 }
2385
2386 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2387 {
2388 u32 ocp_data;
2389
2390 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2391
2392 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2393 ocp_data &= ~LINK_ON_WAKE_EN;
2394 if (wolopts & WAKE_PHY)
2395 ocp_data |= LINK_ON_WAKE_EN;
2396 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2397
2398 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2399 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2400 if (wolopts & WAKE_UCAST)
2401 ocp_data |= UWF_EN;
2402 if (wolopts & WAKE_BCAST)
2403 ocp_data |= BWF_EN;
2404 if (wolopts & WAKE_MCAST)
2405 ocp_data |= MWF_EN;
2406 if (wolopts & WAKE_ANY)
2407 ocp_data |= LAN_WAKE_EN;
2408 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2409
2410 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2411
2412 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2413 ocp_data &= ~MAGIC_EN;
2414 if (wolopts & WAKE_MAGIC)
2415 ocp_data |= MAGIC_EN;
2416 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2417
2418 if (wolopts & WAKE_ANY)
2419 device_set_wakeup_enable(&tp->udev->dev, true);
2420 else
2421 device_set_wakeup_enable(&tp->udev->dev, false);
2422 }
2423
2424 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2425 {
2426 u8 u1u2[8];
2427
2428 if (enable)
2429 memset(u1u2, 0xff, sizeof(u1u2));
2430 else
2431 memset(u1u2, 0x00, sizeof(u1u2));
2432
2433 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2434 }
2435
2436 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2437 {
2438 u32 ocp_data;
2439
2440 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2441 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
2442 ocp_data |= U2P3_ENABLE;
2443 else
2444 ocp_data &= ~U2P3_ENABLE;
2445 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2446 }
2447
2448 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2449 {
2450 u32 ocp_data;
2451
2452 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2453 if (enable)
2454 ocp_data |= PWR_EN | PHASE2_EN;
2455 else
2456 ocp_data &= ~(PWR_EN | PHASE2_EN);
2457 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2458
2459 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2460 ocp_data &= ~PCUT_STATUS;
2461 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2462 }
2463
2464 static bool rtl_can_wakeup(struct r8152 *tp)
2465 {
2466 struct usb_device *udev = tp->udev;
2467
2468 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2469 }
2470
2471 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2472 {
2473 if (enable) {
2474 u32 ocp_data;
2475
2476 r8153_u1u2en(tp, false);
2477 r8153_u2p3en(tp, false);
2478
2479 __rtl_set_wol(tp, WAKE_ANY);
2480
2481 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2482
2483 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2484 ocp_data |= LINK_OFF_WAKE_EN;
2485 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2486
2487 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2488 } else {
2489 __rtl_set_wol(tp, tp->saved_wolopts);
2490 r8153_u2p3en(tp, true);
2491 r8153_u1u2en(tp, true);
2492 }
2493 }
2494
2495 static void rtl_phy_reset(struct r8152 *tp)
2496 {
2497 u16 data;
2498 int i;
2499
2500 clear_bit(PHY_RESET, &tp->flags);
2501
2502 data = r8152_mdio_read(tp, MII_BMCR);
2503
2504 /* don't reset again before the previous one complete */
2505 if (data & BMCR_RESET)
2506 return;
2507
2508 data |= BMCR_RESET;
2509 r8152_mdio_write(tp, MII_BMCR, data);
2510
2511 for (i = 0; i < 50; i++) {
2512 msleep(20);
2513 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2514 break;
2515 }
2516 }
2517
2518 static void r8153_teredo_off(struct r8152 *tp)
2519 {
2520 u32 ocp_data;
2521
2522 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2523 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2524 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2525
2526 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2528 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2529 }
2530
2531 static void r8152b_disable_aldps(struct r8152 *tp)
2532 {
2533 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2534 msleep(20);
2535 }
2536
2537 static inline void r8152b_enable_aldps(struct r8152 *tp)
2538 {
2539 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2540 LINKENA | DIS_SDSAVE);
2541 }
2542
2543 static void rtl8152_disable(struct r8152 *tp)
2544 {
2545 r8152b_disable_aldps(tp);
2546 rtl_disable(tp);
2547 r8152b_enable_aldps(tp);
2548 }
2549
2550 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2551 {
2552 u16 data;
2553
2554 data = r8152_mdio_read(tp, MII_BMCR);
2555 if (data & BMCR_PDOWN) {
2556 data &= ~BMCR_PDOWN;
2557 r8152_mdio_write(tp, MII_BMCR, data);
2558 }
2559
2560 set_bit(PHY_RESET, &tp->flags);
2561 }
2562
2563 static void r8152b_exit_oob(struct r8152 *tp)
2564 {
2565 u32 ocp_data;
2566 int i;
2567
2568 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2569 ocp_data &= ~RCR_ACPT_ALL;
2570 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2571
2572 rxdy_gated_en(tp, true);
2573 r8153_teredo_off(tp);
2574 r8152b_hw_phy_cfg(tp);
2575
2576 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2577 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2578
2579 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2580 ocp_data &= ~NOW_IS_OOB;
2581 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2582
2583 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2584 ocp_data &= ~MCU_BORW_EN;
2585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2586
2587 for (i = 0; i < 1000; i++) {
2588 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2589 if (ocp_data & LINK_LIST_READY)
2590 break;
2591 usleep_range(1000, 2000);
2592 }
2593
2594 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2595 ocp_data |= RE_INIT_LL;
2596 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2597
2598 for (i = 0; i < 1000; i++) {
2599 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2600 if (ocp_data & LINK_LIST_READY)
2601 break;
2602 usleep_range(1000, 2000);
2603 }
2604
2605 rtl8152_nic_reset(tp);
2606
2607 /* rx share fifo credit full threshold */
2608 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2609
2610 if (tp->udev->speed == USB_SPEED_FULL ||
2611 tp->udev->speed == USB_SPEED_LOW) {
2612 /* rx share fifo credit near full threshold */
2613 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2614 RXFIFO_THR2_FULL);
2615 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2616 RXFIFO_THR3_FULL);
2617 } else {
2618 /* rx share fifo credit near full threshold */
2619 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2620 RXFIFO_THR2_HIGH);
2621 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2622 RXFIFO_THR3_HIGH);
2623 }
2624
2625 /* TX share fifo free credit full threshold */
2626 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2627
2628 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2629 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2630 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2631 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2632
2633 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2634
2635 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2636
2637 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2638 ocp_data |= TCR0_AUTO_FIFO;
2639 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2640 }
2641
2642 static void r8152b_enter_oob(struct r8152 *tp)
2643 {
2644 u32 ocp_data;
2645 int i;
2646
2647 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2648 ocp_data &= ~NOW_IS_OOB;
2649 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2650
2651 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2652 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2653 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2654
2655 rtl_disable(tp);
2656
2657 for (i = 0; i < 1000; i++) {
2658 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2659 if (ocp_data & LINK_LIST_READY)
2660 break;
2661 usleep_range(1000, 2000);
2662 }
2663
2664 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2665 ocp_data |= RE_INIT_LL;
2666 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2667
2668 for (i = 0; i < 1000; i++) {
2669 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2670 if (ocp_data & LINK_LIST_READY)
2671 break;
2672 usleep_range(1000, 2000);
2673 }
2674
2675 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2676
2677 rtl_rx_vlan_en(tp, true);
2678
2679 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2680 ocp_data |= ALDPS_PROXY_MODE;
2681 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2682
2683 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2684 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2685 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2686
2687 rxdy_gated_en(tp, false);
2688
2689 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2690 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2691 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2692 }
2693
2694 static void r8153_hw_phy_cfg(struct r8152 *tp)
2695 {
2696 u32 ocp_data;
2697 u16 data;
2698
2699 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
2700 tp->version == RTL_VER_05)
2701 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2702
2703 data = r8152_mdio_read(tp, MII_BMCR);
2704 if (data & BMCR_PDOWN) {
2705 data &= ~BMCR_PDOWN;
2706 r8152_mdio_write(tp, MII_BMCR, data);
2707 }
2708
2709 if (tp->version == RTL_VER_03) {
2710 data = ocp_reg_read(tp, OCP_EEE_CFG);
2711 data &= ~CTAP_SHORT_EN;
2712 ocp_reg_write(tp, OCP_EEE_CFG, data);
2713 }
2714
2715 data = ocp_reg_read(tp, OCP_POWER_CFG);
2716 data |= EEE_CLKDIV_EN;
2717 ocp_reg_write(tp, OCP_POWER_CFG, data);
2718
2719 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2720 data |= EN_10M_BGOFF;
2721 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2722 data = ocp_reg_read(tp, OCP_POWER_CFG);
2723 data |= EN_10M_PLLOFF;
2724 ocp_reg_write(tp, OCP_POWER_CFG, data);
2725 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
2726
2727 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2728 ocp_data |= PFM_PWM_SWITCH;
2729 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2730
2731 /* Enable LPF corner auto tune */
2732 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
2733
2734 /* Adjust 10M Amplitude */
2735 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2736 sram_write(tp, SRAM_10M_AMP2, 0x0208);
2737
2738 set_bit(PHY_RESET, &tp->flags);
2739 }
2740
2741 static void r8153_first_init(struct r8152 *tp)
2742 {
2743 u32 ocp_data;
2744 int i;
2745
2746 rxdy_gated_en(tp, true);
2747 r8153_teredo_off(tp);
2748
2749 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2750 ocp_data &= ~RCR_ACPT_ALL;
2751 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2752
2753 r8153_hw_phy_cfg(tp);
2754
2755 rtl8152_nic_reset(tp);
2756
2757 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2758 ocp_data &= ~NOW_IS_OOB;
2759 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2760
2761 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2762 ocp_data &= ~MCU_BORW_EN;
2763 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2764
2765 for (i = 0; i < 1000; i++) {
2766 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2767 if (ocp_data & LINK_LIST_READY)
2768 break;
2769 usleep_range(1000, 2000);
2770 }
2771
2772 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2773 ocp_data |= RE_INIT_LL;
2774 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2775
2776 for (i = 0; i < 1000; i++) {
2777 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2778 if (ocp_data & LINK_LIST_READY)
2779 break;
2780 usleep_range(1000, 2000);
2781 }
2782
2783 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2784
2785 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2786 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2787
2788 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2789 ocp_data |= TCR0_AUTO_FIFO;
2790 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2791
2792 rtl8152_nic_reset(tp);
2793
2794 /* rx share fifo credit full threshold */
2795 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2796 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2797 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2798 /* TX share fifo free credit full threshold */
2799 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2800
2801 /* rx aggregation */
2802 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2803 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
2804 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2805 }
2806
2807 static void r8153_enter_oob(struct r8152 *tp)
2808 {
2809 u32 ocp_data;
2810 int i;
2811
2812 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2813 ocp_data &= ~NOW_IS_OOB;
2814 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2815
2816 rtl_disable(tp);
2817
2818 for (i = 0; i < 1000; i++) {
2819 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2820 if (ocp_data & LINK_LIST_READY)
2821 break;
2822 usleep_range(1000, 2000);
2823 }
2824
2825 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2826 ocp_data |= RE_INIT_LL;
2827 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2828
2829 for (i = 0; i < 1000; i++) {
2830 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2831 if (ocp_data & LINK_LIST_READY)
2832 break;
2833 usleep_range(1000, 2000);
2834 }
2835
2836 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2837
2838 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2839 ocp_data &= ~TEREDO_WAKE_MASK;
2840 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2841
2842 rtl_rx_vlan_en(tp, true);
2843
2844 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2845 ocp_data |= ALDPS_PROXY_MODE;
2846 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2847
2848 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2849 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2850 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2851
2852 rxdy_gated_en(tp, false);
2853
2854 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2855 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2856 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2857 }
2858
2859 static void r8153_disable_aldps(struct r8152 *tp)
2860 {
2861 u16 data;
2862
2863 data = ocp_reg_read(tp, OCP_POWER_CFG);
2864 data &= ~EN_ALDPS;
2865 ocp_reg_write(tp, OCP_POWER_CFG, data);
2866 msleep(20);
2867 }
2868
2869 static void r8153_enable_aldps(struct r8152 *tp)
2870 {
2871 u16 data;
2872
2873 data = ocp_reg_read(tp, OCP_POWER_CFG);
2874 data |= EN_ALDPS;
2875 ocp_reg_write(tp, OCP_POWER_CFG, data);
2876 }
2877
2878 static void rtl8153_disable(struct r8152 *tp)
2879 {
2880 r8153_disable_aldps(tp);
2881 rtl_disable(tp);
2882 r8153_enable_aldps(tp);
2883 usb_enable_lpm(tp->udev);
2884 }
2885
2886 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2887 {
2888 u16 bmcr, anar, gbcr;
2889 int ret = 0;
2890
2891 cancel_delayed_work_sync(&tp->schedule);
2892 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2893 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2894 ADVERTISE_100HALF | ADVERTISE_100FULL);
2895 if (tp->mii.supports_gmii) {
2896 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2897 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2898 } else {
2899 gbcr = 0;
2900 }
2901
2902 if (autoneg == AUTONEG_DISABLE) {
2903 if (speed == SPEED_10) {
2904 bmcr = 0;
2905 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2906 } else if (speed == SPEED_100) {
2907 bmcr = BMCR_SPEED100;
2908 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2909 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2910 bmcr = BMCR_SPEED1000;
2911 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2912 } else {
2913 ret = -EINVAL;
2914 goto out;
2915 }
2916
2917 if (duplex == DUPLEX_FULL)
2918 bmcr |= BMCR_FULLDPLX;
2919 } else {
2920 if (speed == SPEED_10) {
2921 if (duplex == DUPLEX_FULL)
2922 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2923 else
2924 anar |= ADVERTISE_10HALF;
2925 } else if (speed == SPEED_100) {
2926 if (duplex == DUPLEX_FULL) {
2927 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2928 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2929 } else {
2930 anar |= ADVERTISE_10HALF;
2931 anar |= ADVERTISE_100HALF;
2932 }
2933 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2934 if (duplex == DUPLEX_FULL) {
2935 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2936 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2937 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2938 } else {
2939 anar |= ADVERTISE_10HALF;
2940 anar |= ADVERTISE_100HALF;
2941 gbcr |= ADVERTISE_1000HALF;
2942 }
2943 } else {
2944 ret = -EINVAL;
2945 goto out;
2946 }
2947
2948 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2949 }
2950
2951 if (test_bit(PHY_RESET, &tp->flags))
2952 bmcr |= BMCR_RESET;
2953
2954 if (tp->mii.supports_gmii)
2955 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2956
2957 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2958 r8152_mdio_write(tp, MII_BMCR, bmcr);
2959
2960 if (test_bit(PHY_RESET, &tp->flags)) {
2961 int i;
2962
2963 clear_bit(PHY_RESET, &tp->flags);
2964 for (i = 0; i < 50; i++) {
2965 msleep(20);
2966 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2967 break;
2968 }
2969 }
2970
2971 out:
2972
2973 return ret;
2974 }
2975
2976 static void rtl8152_up(struct r8152 *tp)
2977 {
2978 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2979 return;
2980
2981 r8152b_disable_aldps(tp);
2982 r8152b_exit_oob(tp);
2983 r8152b_enable_aldps(tp);
2984 }
2985
2986 static void rtl8152_down(struct r8152 *tp)
2987 {
2988 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2989 rtl_drop_queued_tx(tp);
2990 return;
2991 }
2992
2993 r8152_power_cut_en(tp, false);
2994 r8152b_disable_aldps(tp);
2995 r8152b_enter_oob(tp);
2996 r8152b_enable_aldps(tp);
2997 }
2998
2999 static void rtl8153_up(struct r8152 *tp)
3000 {
3001 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3002 return;
3003
3004 r8153_u1u2en(tp, false);
3005 r8153_disable_aldps(tp);
3006 r8153_first_init(tp);
3007 r8153_enable_aldps(tp);
3008 r8153_u2p3en(tp, true);
3009 r8153_u1u2en(tp, true);
3010 usb_enable_lpm(tp->udev);
3011 }
3012
3013 static void rtl8153_down(struct r8152 *tp)
3014 {
3015 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3016 rtl_drop_queued_tx(tp);
3017 return;
3018 }
3019
3020 r8153_u1u2en(tp, false);
3021 r8153_u2p3en(tp, false);
3022 r8153_power_cut_en(tp, false);
3023 r8153_disable_aldps(tp);
3024 r8153_enter_oob(tp);
3025 r8153_enable_aldps(tp);
3026 }
3027
3028 static bool rtl8152_in_nway(struct r8152 *tp)
3029 {
3030 u16 nway_state;
3031
3032 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3033 tp->ocp_base = 0x2000;
3034 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3035 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3036
3037 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3038 if (nway_state & 0xc000)
3039 return false;
3040 else
3041 return true;
3042 }
3043
3044 static bool rtl8153_in_nway(struct r8152 *tp)
3045 {
3046 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3047
3048 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3049 return false;
3050 else
3051 return true;
3052 }
3053
3054 static void set_carrier(struct r8152 *tp)
3055 {
3056 struct net_device *netdev = tp->netdev;
3057 u8 speed;
3058
3059 clear_bit(RTL8152_LINK_CHG, &tp->flags);
3060 speed = rtl8152_get_speed(tp);
3061
3062 if (speed & LINK_STATUS) {
3063 if (!netif_carrier_ok(netdev)) {
3064 tp->rtl_ops.enable(tp);
3065 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
3066 napi_disable(&tp->napi);
3067 netif_carrier_on(netdev);
3068 rtl_start_rx(tp);
3069 napi_enable(&tp->napi);
3070 }
3071 } else {
3072 if (netif_carrier_ok(netdev)) {
3073 netif_carrier_off(netdev);
3074 napi_disable(&tp->napi);
3075 tp->rtl_ops.disable(tp);
3076 napi_enable(&tp->napi);
3077 }
3078 }
3079 }
3080
3081 static void rtl_work_func_t(struct work_struct *work)
3082 {
3083 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3084
3085 /* If the device is unplugged or !netif_running(), the workqueue
3086 * doesn't need to wake the device, and could return directly.
3087 */
3088 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3089 return;
3090
3091 if (usb_autopm_get_interface(tp->intf) < 0)
3092 return;
3093
3094 if (!test_bit(WORK_ENABLE, &tp->flags))
3095 goto out1;
3096
3097 if (!mutex_trylock(&tp->control)) {
3098 schedule_delayed_work(&tp->schedule, 0);
3099 goto out1;
3100 }
3101
3102 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
3103 set_carrier(tp);
3104
3105 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
3106 _rtl8152_set_rx_mode(tp->netdev);
3107
3108 /* don't schedule napi before linking */
3109 if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
3110 netif_carrier_ok(tp->netdev)) {
3111 clear_bit(SCHEDULE_NAPI, &tp->flags);
3112 napi_schedule(&tp->napi);
3113 }
3114
3115 if (test_bit(PHY_RESET, &tp->flags))
3116 rtl_phy_reset(tp);
3117
3118 mutex_unlock(&tp->control);
3119
3120 out1:
3121 usb_autopm_put_interface(tp->intf);
3122 }
3123
3124 static int rtl8152_open(struct net_device *netdev)
3125 {
3126 struct r8152 *tp = netdev_priv(netdev);
3127 int res = 0;
3128
3129 res = alloc_all_mem(tp);
3130 if (res)
3131 goto out;
3132
3133 netif_carrier_off(netdev);
3134
3135 res = usb_autopm_get_interface(tp->intf);
3136 if (res < 0) {
3137 free_all_mem(tp);
3138 goto out;
3139 }
3140
3141 mutex_lock(&tp->control);
3142
3143 tp->rtl_ops.up(tp);
3144
3145 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3146 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3147 DUPLEX_FULL);
3148 netif_carrier_off(netdev);
3149 netif_start_queue(netdev);
3150 set_bit(WORK_ENABLE, &tp->flags);
3151
3152 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3153 if (res) {
3154 if (res == -ENODEV)
3155 netif_device_detach(tp->netdev);
3156 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3157 res);
3158 free_all_mem(tp);
3159 } else {
3160 napi_enable(&tp->napi);
3161 }
3162
3163 mutex_unlock(&tp->control);
3164
3165 usb_autopm_put_interface(tp->intf);
3166
3167 out:
3168 return res;
3169 }
3170
3171 static int rtl8152_close(struct net_device *netdev)
3172 {
3173 struct r8152 *tp = netdev_priv(netdev);
3174 int res = 0;
3175
3176 napi_disable(&tp->napi);
3177 clear_bit(WORK_ENABLE, &tp->flags);
3178 usb_kill_urb(tp->intr_urb);
3179 cancel_delayed_work_sync(&tp->schedule);
3180 netif_stop_queue(netdev);
3181
3182 res = usb_autopm_get_interface(tp->intf);
3183 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3184 rtl_drop_queued_tx(tp);
3185 rtl_stop_rx(tp);
3186 } else {
3187 mutex_lock(&tp->control);
3188
3189 tp->rtl_ops.down(tp);
3190
3191 mutex_unlock(&tp->control);
3192
3193 usb_autopm_put_interface(tp->intf);
3194 }
3195
3196 free_all_mem(tp);
3197
3198 return res;
3199 }
3200
3201 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3202 {
3203 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3204 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3205 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3206 }
3207
3208 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3209 {
3210 u16 data;
3211
3212 r8152_mmd_indirect(tp, dev, reg);
3213 data = ocp_reg_read(tp, OCP_EEE_DATA);
3214 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3215
3216 return data;
3217 }
3218
3219 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3220 {
3221 r8152_mmd_indirect(tp, dev, reg);
3222 ocp_reg_write(tp, OCP_EEE_DATA, data);
3223 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3224 }
3225
3226 static void r8152_eee_en(struct r8152 *tp, bool enable)
3227 {
3228 u16 config1, config2, config3;
3229 u32 ocp_data;
3230
3231 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3232 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3233 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3234 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3235
3236 if (enable) {
3237 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3238 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3239 config1 |= sd_rise_time(1);
3240 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3241 config3 |= fast_snr(42);
3242 } else {
3243 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3244 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3245 RX_QUIET_EN);
3246 config1 |= sd_rise_time(7);
3247 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3248 config3 |= fast_snr(511);
3249 }
3250
3251 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3252 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3253 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3254 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3255 }
3256
3257 static void r8152b_enable_eee(struct r8152 *tp)
3258 {
3259 r8152_eee_en(tp, true);
3260 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3261 }
3262
3263 static void r8153_eee_en(struct r8152 *tp, bool enable)
3264 {
3265 u32 ocp_data;
3266 u16 config;
3267
3268 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3269 config = ocp_reg_read(tp, OCP_EEE_CFG);
3270
3271 if (enable) {
3272 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3273 config |= EEE10_EN;
3274 } else {
3275 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3276 config &= ~EEE10_EN;
3277 }
3278
3279 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3280 ocp_reg_write(tp, OCP_EEE_CFG, config);
3281 }
3282
3283 static void r8153_enable_eee(struct r8152 *tp)
3284 {
3285 r8153_eee_en(tp, true);
3286 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3287 }
3288
3289 static void r8152b_enable_fc(struct r8152 *tp)
3290 {
3291 u16 anar;
3292
3293 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3294 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3295 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3296 }
3297
3298 static void rtl_tally_reset(struct r8152 *tp)
3299 {
3300 u32 ocp_data;
3301
3302 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3303 ocp_data |= TALLY_RESET;
3304 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3305 }
3306
3307 static void r8152b_init(struct r8152 *tp)
3308 {
3309 u32 ocp_data;
3310
3311 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3312 return;
3313
3314 r8152b_disable_aldps(tp);
3315
3316 if (tp->version == RTL_VER_01) {
3317 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3318 ocp_data &= ~LED_MODE_MASK;
3319 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3320 }
3321
3322 r8152_power_cut_en(tp, false);
3323
3324 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3325 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3326 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3327 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3328 ocp_data &= ~MCU_CLK_RATIO_MASK;
3329 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3330 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3331 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3332 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3333 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3334
3335 r8152b_enable_eee(tp);
3336 r8152b_enable_aldps(tp);
3337 r8152b_enable_fc(tp);
3338 rtl_tally_reset(tp);
3339
3340 /* enable rx aggregation */
3341 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3342 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
3343 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3344 }
3345
3346 static void r8153_init(struct r8152 *tp)
3347 {
3348 u32 ocp_data;
3349 int i;
3350
3351 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3352 return;
3353
3354 r8153_disable_aldps(tp);
3355 r8153_u1u2en(tp, false);
3356
3357 for (i = 0; i < 500; i++) {
3358 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3359 AUTOLOAD_DONE)
3360 break;
3361 msleep(20);
3362 }
3363
3364 for (i = 0; i < 500; i++) {
3365 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3366 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3367 break;
3368 msleep(20);
3369 }
3370
3371 usb_disable_lpm(tp->udev);
3372 r8153_u2p3en(tp, false);
3373
3374 if (tp->version == RTL_VER_04) {
3375 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3376 ocp_data &= ~pwd_dn_scale_mask;
3377 ocp_data |= pwd_dn_scale(96);
3378 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3379
3380 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3381 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3382 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3383 } else if (tp->version == RTL_VER_05) {
3384 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3385 ocp_data &= ~ECM_ALDPS;
3386 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3387
3388 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3389 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3390 ocp_data &= ~DYNAMIC_BURST;
3391 else
3392 ocp_data |= DYNAMIC_BURST;
3393 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3394 } else if (tp->version == RTL_VER_06) {
3395 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3396 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3397 ocp_data &= ~DYNAMIC_BURST;
3398 else
3399 ocp_data |= DYNAMIC_BURST;
3400 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3401 }
3402
3403 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3404 ocp_data |= EP4_FULL_FC;
3405 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3406
3407 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3408 ocp_data &= ~TIMER11_EN;
3409 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3410
3411 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3412 ocp_data &= ~LED_MODE_MASK;
3413 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3414
3415 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
3416 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
3417 ocp_data |= LPM_TIMER_500MS;
3418 else
3419 ocp_data |= LPM_TIMER_500US;
3420 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3421
3422 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3423 ocp_data &= ~SEN_VAL_MASK;
3424 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3425 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3426
3427 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3428
3429 r8153_power_cut_en(tp, false);
3430 r8153_u1u2en(tp, true);
3431
3432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3433 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3434 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3435 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3436 U1U2_SPDWN_EN | L1_SPDWN_EN);
3437 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3438 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3439 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3440 EEE_SPDWN_EN);
3441
3442 r8153_enable_eee(tp);
3443 r8153_enable_aldps(tp);
3444 r8152b_enable_fc(tp);
3445 rtl_tally_reset(tp);
3446 r8153_u2p3en(tp, true);
3447 }
3448
3449 static int rtl8152_pre_reset(struct usb_interface *intf)
3450 {
3451 struct r8152 *tp = usb_get_intfdata(intf);
3452 struct net_device *netdev;
3453
3454 if (!tp)
3455 return 0;
3456
3457 netdev = tp->netdev;
3458 if (!netif_running(netdev))
3459 return 0;
3460
3461 napi_disable(&tp->napi);
3462 clear_bit(WORK_ENABLE, &tp->flags);
3463 usb_kill_urb(tp->intr_urb);
3464 cancel_delayed_work_sync(&tp->schedule);
3465 if (netif_carrier_ok(netdev)) {
3466 netif_stop_queue(netdev);
3467 mutex_lock(&tp->control);
3468 tp->rtl_ops.disable(tp);
3469 mutex_unlock(&tp->control);
3470 }
3471
3472 return 0;
3473 }
3474
3475 static int rtl8152_post_reset(struct usb_interface *intf)
3476 {
3477 struct r8152 *tp = usb_get_intfdata(intf);
3478 struct net_device *netdev;
3479
3480 if (!tp)
3481 return 0;
3482
3483 netdev = tp->netdev;
3484 if (!netif_running(netdev))
3485 return 0;
3486
3487 set_bit(WORK_ENABLE, &tp->flags);
3488 if (netif_carrier_ok(netdev)) {
3489 mutex_lock(&tp->control);
3490 tp->rtl_ops.enable(tp);
3491 rtl8152_set_rx_mode(netdev);
3492 mutex_unlock(&tp->control);
3493 netif_wake_queue(netdev);
3494 }
3495
3496 napi_enable(&tp->napi);
3497
3498 return 0;
3499 }
3500
3501 static bool delay_autosuspend(struct r8152 *tp)
3502 {
3503 bool sw_linking = !!netif_carrier_ok(tp->netdev);
3504 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
3505
3506 /* This means a linking change occurs and the driver doesn't detect it,
3507 * yet. If the driver has disabled tx/rx and hw is linking on, the
3508 * device wouldn't wake up by receiving any packet.
3509 */
3510 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
3511 return true;
3512
3513 /* If the linking down is occurred by nway, the device may miss the
3514 * linking change event. And it wouldn't wake when linking on.
3515 */
3516 if (!sw_linking && tp->rtl_ops.in_nway(tp))
3517 return true;
3518 else if (!skb_queue_empty(&tp->tx_queue))
3519 return true;
3520 else
3521 return false;
3522 }
3523
3524 static int rtl8152_rumtime_suspend(struct r8152 *tp)
3525 {
3526 struct net_device *netdev = tp->netdev;
3527 int ret = 0;
3528
3529 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3530 u32 rcr = 0;
3531
3532 if (delay_autosuspend(tp)) {
3533 ret = -EBUSY;
3534 goto out1;
3535 }
3536
3537 if (netif_carrier_ok(netdev)) {
3538 u32 ocp_data;
3539
3540 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3541 ocp_data = rcr & ~RCR_ACPT_ALL;
3542 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3543 rxdy_gated_en(tp, true);
3544 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
3545 PLA_OOB_CTRL);
3546 if (!(ocp_data & RXFIFO_EMPTY)) {
3547 rxdy_gated_en(tp, false);
3548 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
3549 ret = -EBUSY;
3550 goto out1;
3551 }
3552 }
3553
3554 clear_bit(WORK_ENABLE, &tp->flags);
3555 usb_kill_urb(tp->intr_urb);
3556
3557 rtl_runtime_suspend_enable(tp, true);
3558
3559 if (netif_carrier_ok(netdev)) {
3560 napi_disable(&tp->napi);
3561 rtl_stop_rx(tp);
3562 rxdy_gated_en(tp, false);
3563 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
3564 napi_enable(&tp->napi);
3565 }
3566 }
3567
3568 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3569
3570 out1:
3571 return ret;
3572 }
3573
3574 static int rtl8152_system_suspend(struct r8152 *tp)
3575 {
3576 struct net_device *netdev = tp->netdev;
3577 int ret = 0;
3578
3579 netif_device_detach(netdev);
3580
3581 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3582 clear_bit(WORK_ENABLE, &tp->flags);
3583 usb_kill_urb(tp->intr_urb);
3584 napi_disable(&tp->napi);
3585 cancel_delayed_work_sync(&tp->schedule);
3586 tp->rtl_ops.down(tp);
3587 napi_enable(&tp->napi);
3588 }
3589
3590 return ret;
3591 }
3592
3593 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3594 {
3595 struct r8152 *tp = usb_get_intfdata(intf);
3596 int ret;
3597
3598 mutex_lock(&tp->control);
3599
3600 if (PMSG_IS_AUTO(message))
3601 ret = rtl8152_rumtime_suspend(tp);
3602 else
3603 ret = rtl8152_system_suspend(tp);
3604
3605 mutex_unlock(&tp->control);
3606
3607 return ret;
3608 }
3609
3610 static int rtl8152_resume(struct usb_interface *intf)
3611 {
3612 struct r8152 *tp = usb_get_intfdata(intf);
3613
3614 mutex_lock(&tp->control);
3615
3616 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3617 tp->rtl_ops.init(tp);
3618 netif_device_attach(tp->netdev);
3619 }
3620
3621 if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
3622 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3623 rtl_runtime_suspend_enable(tp, false);
3624 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3625 napi_disable(&tp->napi);
3626 set_bit(WORK_ENABLE, &tp->flags);
3627 if (netif_carrier_ok(tp->netdev))
3628 rtl_start_rx(tp);
3629 napi_enable(&tp->napi);
3630 } else {
3631 tp->rtl_ops.up(tp);
3632 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3633 tp->mii.supports_gmii ?
3634 SPEED_1000 : SPEED_100,
3635 DUPLEX_FULL);
3636 netif_carrier_off(tp->netdev);
3637 set_bit(WORK_ENABLE, &tp->flags);
3638 }
3639 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3640 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3641 if (tp->netdev->flags & IFF_UP)
3642 rtl_runtime_suspend_enable(tp, false);
3643 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3644 }
3645
3646 mutex_unlock(&tp->control);
3647
3648 return 0;
3649 }
3650
3651 static int rtl8152_reset_resume(struct usb_interface *intf)
3652 {
3653 struct r8152 *tp = usb_get_intfdata(intf);
3654
3655 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3656 return rtl8152_resume(intf);
3657 }
3658
3659 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3660 {
3661 struct r8152 *tp = netdev_priv(dev);
3662
3663 if (usb_autopm_get_interface(tp->intf) < 0)
3664 return;
3665
3666 if (!rtl_can_wakeup(tp)) {
3667 wol->supported = 0;
3668 wol->wolopts = 0;
3669 } else {
3670 mutex_lock(&tp->control);
3671 wol->supported = WAKE_ANY;
3672 wol->wolopts = __rtl_get_wol(tp);
3673 mutex_unlock(&tp->control);
3674 }
3675
3676 usb_autopm_put_interface(tp->intf);
3677 }
3678
3679 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3680 {
3681 struct r8152 *tp = netdev_priv(dev);
3682 int ret;
3683
3684 if (!rtl_can_wakeup(tp))
3685 return -EOPNOTSUPP;
3686
3687 ret = usb_autopm_get_interface(tp->intf);
3688 if (ret < 0)
3689 goto out_set_wol;
3690
3691 mutex_lock(&tp->control);
3692
3693 __rtl_set_wol(tp, wol->wolopts);
3694 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3695
3696 mutex_unlock(&tp->control);
3697
3698 usb_autopm_put_interface(tp->intf);
3699
3700 out_set_wol:
3701 return ret;
3702 }
3703
3704 static u32 rtl8152_get_msglevel(struct net_device *dev)
3705 {
3706 struct r8152 *tp = netdev_priv(dev);
3707
3708 return tp->msg_enable;
3709 }
3710
3711 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3712 {
3713 struct r8152 *tp = netdev_priv(dev);
3714
3715 tp->msg_enable = value;
3716 }
3717
3718 static void rtl8152_get_drvinfo(struct net_device *netdev,
3719 struct ethtool_drvinfo *info)
3720 {
3721 struct r8152 *tp = netdev_priv(netdev);
3722
3723 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3724 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3725 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3726 }
3727
3728 static
3729 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3730 {
3731 struct r8152 *tp = netdev_priv(netdev);
3732 int ret;
3733
3734 if (!tp->mii.mdio_read)
3735 return -EOPNOTSUPP;
3736
3737 ret = usb_autopm_get_interface(tp->intf);
3738 if (ret < 0)
3739 goto out;
3740
3741 mutex_lock(&tp->control);
3742
3743 ret = mii_ethtool_gset(&tp->mii, cmd);
3744
3745 mutex_unlock(&tp->control);
3746
3747 usb_autopm_put_interface(tp->intf);
3748
3749 out:
3750 return ret;
3751 }
3752
3753 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3754 {
3755 struct r8152 *tp = netdev_priv(dev);
3756 int ret;
3757
3758 ret = usb_autopm_get_interface(tp->intf);
3759 if (ret < 0)
3760 goto out;
3761
3762 mutex_lock(&tp->control);
3763
3764 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3765
3766 mutex_unlock(&tp->control);
3767
3768 usb_autopm_put_interface(tp->intf);
3769
3770 out:
3771 return ret;
3772 }
3773
3774 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3775 "tx_packets",
3776 "rx_packets",
3777 "tx_errors",
3778 "rx_errors",
3779 "rx_missed",
3780 "align_errors",
3781 "tx_single_collisions",
3782 "tx_multi_collisions",
3783 "rx_unicast",
3784 "rx_broadcast",
3785 "rx_multicast",
3786 "tx_aborted",
3787 "tx_underrun",
3788 };
3789
3790 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3791 {
3792 switch (sset) {
3793 case ETH_SS_STATS:
3794 return ARRAY_SIZE(rtl8152_gstrings);
3795 default:
3796 return -EOPNOTSUPP;
3797 }
3798 }
3799
3800 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3801 struct ethtool_stats *stats, u64 *data)
3802 {
3803 struct r8152 *tp = netdev_priv(dev);
3804 struct tally_counter tally;
3805
3806 if (usb_autopm_get_interface(tp->intf) < 0)
3807 return;
3808
3809 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3810
3811 usb_autopm_put_interface(tp->intf);
3812
3813 data[0] = le64_to_cpu(tally.tx_packets);
3814 data[1] = le64_to_cpu(tally.rx_packets);
3815 data[2] = le64_to_cpu(tally.tx_errors);
3816 data[3] = le32_to_cpu(tally.rx_errors);
3817 data[4] = le16_to_cpu(tally.rx_missed);
3818 data[5] = le16_to_cpu(tally.align_errors);
3819 data[6] = le32_to_cpu(tally.tx_one_collision);
3820 data[7] = le32_to_cpu(tally.tx_multi_collision);
3821 data[8] = le64_to_cpu(tally.rx_unicast);
3822 data[9] = le64_to_cpu(tally.rx_broadcast);
3823 data[10] = le32_to_cpu(tally.rx_multicast);
3824 data[11] = le16_to_cpu(tally.tx_aborted);
3825 data[12] = le16_to_cpu(tally.tx_underrun);
3826 }
3827
3828 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3829 {
3830 switch (stringset) {
3831 case ETH_SS_STATS:
3832 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3833 break;
3834 }
3835 }
3836
3837 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3838 {
3839 u32 ocp_data, lp, adv, supported = 0;
3840 u16 val;
3841
3842 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3843 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3844
3845 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3846 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3847
3848 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3849 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3850
3851 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3852 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3853
3854 eee->eee_enabled = !!ocp_data;
3855 eee->eee_active = !!(supported & adv & lp);
3856 eee->supported = supported;
3857 eee->advertised = adv;
3858 eee->lp_advertised = lp;
3859
3860 return 0;
3861 }
3862
3863 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3864 {
3865 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3866
3867 r8152_eee_en(tp, eee->eee_enabled);
3868
3869 if (!eee->eee_enabled)
3870 val = 0;
3871
3872 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3873
3874 return 0;
3875 }
3876
3877 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3878 {
3879 u32 ocp_data, lp, adv, supported = 0;
3880 u16 val;
3881
3882 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3883 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3884
3885 val = ocp_reg_read(tp, OCP_EEE_ADV);
3886 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3887
3888 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3889 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3890
3891 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3892 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3893
3894 eee->eee_enabled = !!ocp_data;
3895 eee->eee_active = !!(supported & adv & lp);
3896 eee->supported = supported;
3897 eee->advertised = adv;
3898 eee->lp_advertised = lp;
3899
3900 return 0;
3901 }
3902
3903 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3904 {
3905 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3906
3907 r8153_eee_en(tp, eee->eee_enabled);
3908
3909 if (!eee->eee_enabled)
3910 val = 0;
3911
3912 ocp_reg_write(tp, OCP_EEE_ADV, val);
3913
3914 return 0;
3915 }
3916
3917 static int
3918 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3919 {
3920 struct r8152 *tp = netdev_priv(net);
3921 int ret;
3922
3923 ret = usb_autopm_get_interface(tp->intf);
3924 if (ret < 0)
3925 goto out;
3926
3927 mutex_lock(&tp->control);
3928
3929 ret = tp->rtl_ops.eee_get(tp, edata);
3930
3931 mutex_unlock(&tp->control);
3932
3933 usb_autopm_put_interface(tp->intf);
3934
3935 out:
3936 return ret;
3937 }
3938
3939 static int
3940 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3941 {
3942 struct r8152 *tp = netdev_priv(net);
3943 int ret;
3944
3945 ret = usb_autopm_get_interface(tp->intf);
3946 if (ret < 0)
3947 goto out;
3948
3949 mutex_lock(&tp->control);
3950
3951 ret = tp->rtl_ops.eee_set(tp, edata);
3952 if (!ret)
3953 ret = mii_nway_restart(&tp->mii);
3954
3955 mutex_unlock(&tp->control);
3956
3957 usb_autopm_put_interface(tp->intf);
3958
3959 out:
3960 return ret;
3961 }
3962
3963 static int rtl8152_nway_reset(struct net_device *dev)
3964 {
3965 struct r8152 *tp = netdev_priv(dev);
3966 int ret;
3967
3968 ret = usb_autopm_get_interface(tp->intf);
3969 if (ret < 0)
3970 goto out;
3971
3972 mutex_lock(&tp->control);
3973
3974 ret = mii_nway_restart(&tp->mii);
3975
3976 mutex_unlock(&tp->control);
3977
3978 usb_autopm_put_interface(tp->intf);
3979
3980 out:
3981 return ret;
3982 }
3983
3984 static int rtl8152_get_coalesce(struct net_device *netdev,
3985 struct ethtool_coalesce *coalesce)
3986 {
3987 struct r8152 *tp = netdev_priv(netdev);
3988
3989 switch (tp->version) {
3990 case RTL_VER_01:
3991 case RTL_VER_02:
3992 return -EOPNOTSUPP;
3993 default:
3994 break;
3995 }
3996
3997 coalesce->rx_coalesce_usecs = tp->coalesce;
3998
3999 return 0;
4000 }
4001
4002 static int rtl8152_set_coalesce(struct net_device *netdev,
4003 struct ethtool_coalesce *coalesce)
4004 {
4005 struct r8152 *tp = netdev_priv(netdev);
4006 int ret;
4007
4008 switch (tp->version) {
4009 case RTL_VER_01:
4010 case RTL_VER_02:
4011 return -EOPNOTSUPP;
4012 default:
4013 break;
4014 }
4015
4016 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4017 return -EINVAL;
4018
4019 ret = usb_autopm_get_interface(tp->intf);
4020 if (ret < 0)
4021 return ret;
4022
4023 mutex_lock(&tp->control);
4024
4025 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4026 tp->coalesce = coalesce->rx_coalesce_usecs;
4027
4028 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4029 r8153_set_rx_early_timeout(tp);
4030 }
4031
4032 mutex_unlock(&tp->control);
4033
4034 usb_autopm_put_interface(tp->intf);
4035
4036 return ret;
4037 }
4038
4039 static struct ethtool_ops ops = {
4040 .get_drvinfo = rtl8152_get_drvinfo,
4041 .get_settings = rtl8152_get_settings,
4042 .set_settings = rtl8152_set_settings,
4043 .get_link = ethtool_op_get_link,
4044 .nway_reset = rtl8152_nway_reset,
4045 .get_msglevel = rtl8152_get_msglevel,
4046 .set_msglevel = rtl8152_set_msglevel,
4047 .get_wol = rtl8152_get_wol,
4048 .set_wol = rtl8152_set_wol,
4049 .get_strings = rtl8152_get_strings,
4050 .get_sset_count = rtl8152_get_sset_count,
4051 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4052 .get_coalesce = rtl8152_get_coalesce,
4053 .set_coalesce = rtl8152_set_coalesce,
4054 .get_eee = rtl_ethtool_get_eee,
4055 .set_eee = rtl_ethtool_set_eee,
4056 };
4057
4058 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4059 {
4060 struct r8152 *tp = netdev_priv(netdev);
4061 struct mii_ioctl_data *data = if_mii(rq);
4062 int res;
4063
4064 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4065 return -ENODEV;
4066
4067 res = usb_autopm_get_interface(tp->intf);
4068 if (res < 0)
4069 goto out;
4070
4071 switch (cmd) {
4072 case SIOCGMIIPHY:
4073 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4074 break;
4075
4076 case SIOCGMIIREG:
4077 mutex_lock(&tp->control);
4078 data->val_out = r8152_mdio_read(tp, data->reg_num);
4079 mutex_unlock(&tp->control);
4080 break;
4081
4082 case SIOCSMIIREG:
4083 if (!capable(CAP_NET_ADMIN)) {
4084 res = -EPERM;
4085 break;
4086 }
4087 mutex_lock(&tp->control);
4088 r8152_mdio_write(tp, data->reg_num, data->val_in);
4089 mutex_unlock(&tp->control);
4090 break;
4091
4092 default:
4093 res = -EOPNOTSUPP;
4094 }
4095
4096 usb_autopm_put_interface(tp->intf);
4097
4098 out:
4099 return res;
4100 }
4101
4102 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4103 {
4104 struct r8152 *tp = netdev_priv(dev);
4105 int ret;
4106
4107 switch (tp->version) {
4108 case RTL_VER_01:
4109 case RTL_VER_02:
4110 return eth_change_mtu(dev, new_mtu);
4111 default:
4112 break;
4113 }
4114
4115 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
4116 return -EINVAL;
4117
4118 ret = usb_autopm_get_interface(tp->intf);
4119 if (ret < 0)
4120 return ret;
4121
4122 mutex_lock(&tp->control);
4123
4124 dev->mtu = new_mtu;
4125
4126 if (netif_running(dev) && netif_carrier_ok(dev))
4127 r8153_set_rx_early_size(tp);
4128
4129 mutex_unlock(&tp->control);
4130
4131 usb_autopm_put_interface(tp->intf);
4132
4133 return ret;
4134 }
4135
4136 static const struct net_device_ops rtl8152_netdev_ops = {
4137 .ndo_open = rtl8152_open,
4138 .ndo_stop = rtl8152_close,
4139 .ndo_do_ioctl = rtl8152_ioctl,
4140 .ndo_start_xmit = rtl8152_start_xmit,
4141 .ndo_tx_timeout = rtl8152_tx_timeout,
4142 .ndo_set_features = rtl8152_set_features,
4143 .ndo_set_rx_mode = rtl8152_set_rx_mode,
4144 .ndo_set_mac_address = rtl8152_set_mac_address,
4145 .ndo_change_mtu = rtl8152_change_mtu,
4146 .ndo_validate_addr = eth_validate_addr,
4147 .ndo_features_check = rtl8152_features_check,
4148 };
4149
4150 static void r8152b_get_version(struct r8152 *tp)
4151 {
4152 u32 ocp_data;
4153 u16 version;
4154
4155 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
4156 version = (u16)(ocp_data & VERSION_MASK);
4157
4158 switch (version) {
4159 case 0x4c00:
4160 tp->version = RTL_VER_01;
4161 break;
4162 case 0x4c10:
4163 tp->version = RTL_VER_02;
4164 break;
4165 case 0x5c00:
4166 tp->version = RTL_VER_03;
4167 tp->mii.supports_gmii = 1;
4168 break;
4169 case 0x5c10:
4170 tp->version = RTL_VER_04;
4171 tp->mii.supports_gmii = 1;
4172 break;
4173 case 0x5c20:
4174 tp->version = RTL_VER_05;
4175 tp->mii.supports_gmii = 1;
4176 break;
4177 case 0x5c30:
4178 tp->version = RTL_VER_06;
4179 tp->mii.supports_gmii = 1;
4180 break;
4181 default:
4182 netif_info(tp, probe, tp->netdev,
4183 "Unknown version 0x%04x\n", version);
4184 break;
4185 }
4186 }
4187
4188 static void rtl8152_unload(struct r8152 *tp)
4189 {
4190 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4191 return;
4192
4193 if (tp->version != RTL_VER_01)
4194 r8152_power_cut_en(tp, true);
4195 }
4196
4197 static void rtl8153_unload(struct r8152 *tp)
4198 {
4199 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4200 return;
4201
4202 r8153_power_cut_en(tp, false);
4203 }
4204
4205 static int rtl_ops_init(struct r8152 *tp)
4206 {
4207 struct rtl_ops *ops = &tp->rtl_ops;
4208 int ret = 0;
4209
4210 switch (tp->version) {
4211 case RTL_VER_01:
4212 case RTL_VER_02:
4213 ops->init = r8152b_init;
4214 ops->enable = rtl8152_enable;
4215 ops->disable = rtl8152_disable;
4216 ops->up = rtl8152_up;
4217 ops->down = rtl8152_down;
4218 ops->unload = rtl8152_unload;
4219 ops->eee_get = r8152_get_eee;
4220 ops->eee_set = r8152_set_eee;
4221 ops->in_nway = rtl8152_in_nway;
4222 break;
4223
4224 case RTL_VER_03:
4225 case RTL_VER_04:
4226 case RTL_VER_05:
4227 case RTL_VER_06:
4228 ops->init = r8153_init;
4229 ops->enable = rtl8153_enable;
4230 ops->disable = rtl8153_disable;
4231 ops->up = rtl8153_up;
4232 ops->down = rtl8153_down;
4233 ops->unload = rtl8153_unload;
4234 ops->eee_get = r8153_get_eee;
4235 ops->eee_set = r8153_set_eee;
4236 ops->in_nway = rtl8153_in_nway;
4237 break;
4238
4239 default:
4240 ret = -ENODEV;
4241 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
4242 break;
4243 }
4244
4245 return ret;
4246 }
4247
4248 static int rtl8152_probe(struct usb_interface *intf,
4249 const struct usb_device_id *id)
4250 {
4251 struct usb_device *udev = interface_to_usbdev(intf);
4252 struct r8152 *tp;
4253 struct net_device *netdev;
4254 int ret;
4255
4256 if (udev->actconfig->desc.bConfigurationValue != 1) {
4257 usb_driver_set_configuration(udev, 1);
4258 return -ENODEV;
4259 }
4260
4261 usb_reset_device(udev);
4262 netdev = alloc_etherdev(sizeof(struct r8152));
4263 if (!netdev) {
4264 dev_err(&intf->dev, "Out of memory\n");
4265 return -ENOMEM;
4266 }
4267
4268 SET_NETDEV_DEV(netdev, &intf->dev);
4269 tp = netdev_priv(netdev);
4270 tp->msg_enable = 0x7FFF;
4271
4272 tp->udev = udev;
4273 tp->netdev = netdev;
4274 tp->intf = intf;
4275
4276 r8152b_get_version(tp);
4277 ret = rtl_ops_init(tp);
4278 if (ret)
4279 goto out;
4280
4281 mutex_init(&tp->control);
4282 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
4283
4284 netdev->netdev_ops = &rtl8152_netdev_ops;
4285 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
4286
4287 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4288 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
4289 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4290 NETIF_F_HW_VLAN_CTAG_TX;
4291 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4292 NETIF_F_TSO | NETIF_F_FRAGLIST |
4293 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
4294 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
4295 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4296 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4297 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
4298
4299 if (tp->version == RTL_VER_01) {
4300 netdev->features &= ~NETIF_F_RXCSUM;
4301 netdev->hw_features &= ~NETIF_F_RXCSUM;
4302 }
4303
4304 netdev->ethtool_ops = &ops;
4305 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
4306
4307 tp->mii.dev = netdev;
4308 tp->mii.mdio_read = read_mii_word;
4309 tp->mii.mdio_write = write_mii_word;
4310 tp->mii.phy_id_mask = 0x3f;
4311 tp->mii.reg_num_mask = 0x1f;
4312 tp->mii.phy_id = R8152_PHY_ID;
4313
4314 switch (udev->speed) {
4315 case USB_SPEED_SUPER:
4316 tp->coalesce = COALESCE_SUPER;
4317 break;
4318 case USB_SPEED_HIGH:
4319 tp->coalesce = COALESCE_HIGH;
4320 break;
4321 default:
4322 tp->coalesce = COALESCE_SLOW;
4323 break;
4324 }
4325
4326 intf->needs_remote_wakeup = 1;
4327
4328 tp->rtl_ops.init(tp);
4329 set_ethernet_addr(tp);
4330
4331 usb_set_intfdata(intf, tp);
4332 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
4333
4334 ret = register_netdev(netdev);
4335 if (ret != 0) {
4336 netif_err(tp, probe, netdev, "couldn't register the device\n");
4337 goto out1;
4338 }
4339
4340 if (!rtl_can_wakeup(tp))
4341 __rtl_set_wol(tp, 0);
4342
4343 tp->saved_wolopts = __rtl_get_wol(tp);
4344 if (tp->saved_wolopts)
4345 device_set_wakeup_enable(&udev->dev, true);
4346 else
4347 device_set_wakeup_enable(&udev->dev, false);
4348
4349 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
4350
4351 return 0;
4352
4353 out1:
4354 netif_napi_del(&tp->napi);
4355 usb_set_intfdata(intf, NULL);
4356 out:
4357 free_netdev(netdev);
4358 return ret;
4359 }
4360
4361 static void rtl8152_disconnect(struct usb_interface *intf)
4362 {
4363 struct r8152 *tp = usb_get_intfdata(intf);
4364
4365 usb_set_intfdata(intf, NULL);
4366 if (tp) {
4367 struct usb_device *udev = tp->udev;
4368
4369 if (udev->state == USB_STATE_NOTATTACHED)
4370 set_bit(RTL8152_UNPLUG, &tp->flags);
4371
4372 netif_napi_del(&tp->napi);
4373 unregister_netdev(tp->netdev);
4374 tp->rtl_ops.unload(tp);
4375 free_netdev(tp->netdev);
4376 }
4377 }
4378
4379 #define REALTEK_USB_DEVICE(vend, prod) \
4380 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4381 USB_DEVICE_ID_MATCH_INT_CLASS, \
4382 .idVendor = (vend), \
4383 .idProduct = (prod), \
4384 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4385 }, \
4386 { \
4387 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4388 USB_DEVICE_ID_MATCH_DEVICE, \
4389 .idVendor = (vend), \
4390 .idProduct = (prod), \
4391 .bInterfaceClass = USB_CLASS_COMM, \
4392 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4393 .bInterfaceProtocol = USB_CDC_PROTO_NONE
4394
4395 /* table of devices that work with this driver */
4396 static struct usb_device_id rtl8152_table[] = {
4397 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4398 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4399 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
4400 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
4401 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
4402 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
4403 {}
4404 };
4405
4406 MODULE_DEVICE_TABLE(usb, rtl8152_table);
4407
4408 static struct usb_driver rtl8152_driver = {
4409 .name = MODULENAME,
4410 .id_table = rtl8152_table,
4411 .probe = rtl8152_probe,
4412 .disconnect = rtl8152_disconnect,
4413 .suspend = rtl8152_suspend,
4414 .resume = rtl8152_resume,
4415 .reset_resume = rtl8152_reset_resume,
4416 .pre_reset = rtl8152_pre_reset,
4417 .post_reset = rtl8152_post_reset,
4418 .supports_autosuspend = 1,
4419 .disable_hub_initiated_lpm = 1,
4420 };
4421
4422 module_usb_driver(rtl8152_driver);
4423
4424 MODULE_AUTHOR(DRIVER_AUTHOR);
4425 MODULE_DESCRIPTION(DRIVER_DESC);
4426 MODULE_LICENSE("GPL");